Datasets:

weiber2002
/

ICRTL

---
license: mit
task_categories:
- text-generation
- text-to-code
language:
- en
tags:
- verilog
- systemverilog
- rtl-design
- llm-evaluation
- electronic-design-automation
pretty_name: IC-RTL Benchmark
size_categories:
- n<1K
---

# IC-RTL: Industrial-Scale RTL Design Benchmark

[![arXiv](https://img.shields.io/badge/arXiv-2601.18067-b31b1b.svg)](https://arxiv.org/abs/2601.18067)
[![License: MIT](https://img.shields.io/badge/License-MIT-yellow.svg)](https://opensource.org/licenses/MIT)

## 📖 Overview

This repository contains a collection of industrial-level RTL design challenges selected from the National Taiwan Integrated Circuit Design Contest and handcrafted problems, complete with our reference implementations and specs. Each challenge targets specific algorithms or hardware modules used in industry. We present this collection as the **ICRTL benchmark**, designed to evaluate PPA (Power, Performance, Area) optimization on complex problems — a level of difficulty previously unexplored in the application of LLMs to RTL design.

This dataset is hosted here as a `jsonl` file (`train.jsonl`) for easy integration with ML pipelines.

> **Official Benchmark for the paper:**
> **[EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization](https://arxiv.org/abs/2601.18067)**

---

## ⚡ Quick Start: Reconstructing the Environment

To run the benchmarks (using the testbenches and auxiliary files), **you must first reconstruct the directory structure** from the dataset.

Run the following Python script to download the dataset and restore the full environment locally:

```python
import os
from datasets import load_dataset

# 1. Load the dataset from Hugging Face
# Replace 'weiber2002/IC-RTL' with your actual username if different
dataset = load_dataset("weiber2002/IC-RTL") 

print("Downloading and reconstructing IC-RTL benchmark...")

# 2. Iterate through tasks and set up the environment
for sample in dataset['train']:
    task_name = sample['task_id']
    print(f"  -> Restoring: {task_name}")
    
    # Create directory for the task
    os.makedirs(task_name, exist_ok=True)

    # Restore Testbench
    with open(os.path.join(task_name, "test.sv"), "w", encoding="utf-8") as f:
        f.write(sample['testbench'])

    # Restore Initial RTL Template
    if sample['rtl_code']:
        with open(os.path.join(task_name, "initial.sv"), "w", encoding="utf-8") as f:
            f.write(sample['rtl_code'])

    # Restore Specification
    with open(os.path.join(task_name, "problem_spec.md"), "w", encoding="utf-8") as f:
        f.write(sample['description'])

    # Restore all auxiliary files (hex, dat) preserving their paths
    if sample['auxiliary_files']:
        for filename, content in sample['auxiliary_files'].items():
            file_path = os.path.join(task_name, filename)
            
            # Ensure subdirectories exist (e.g., Q1_LBP/data/inst.hex)
            os.makedirs(os.path.dirname(file_path), exist_ok=True)
            
            # Write content (handling potential binary/text differences)
            mode = "w" if isinstance(content, str) else "wb"
            encoding = "utf-8" if isinstance(content, str) else None
            
            with open(file_path, mode, encoding=encoding) as f:
                f.write(content)

print("\n✅ Reconstruction Complete! You can now follow the 'How to Run' instructions below.")

```

---

## 🧩 Challenges Overview

The benchmark consists of 6 core problems (`Q1` through `Q6`), each containing the problem specification, testbench, and reference solution foundation.

| ID | Problem Name | Description |
| --- | --- | --- |
| **Q1** | **LBP** (Local Binary Pattern) | Design an accelerator to compute Local Binary Patterns for 128x128 grayscale images. |
| **Q2** | **GEMM** (Systolic Array) | Implement a Systolic Array based matrix processing unit. |
| **Q3** | **CONV** (Convolution) | Develop a hardware accelerator for 2D convolution operations on 64x64 images. |
| **Q4** | **HC** (Huffman Coding) | Create a hardware Huffman Coding generator for lossless compression. |
| **Q5** | **JAM** (Job Assignment Machine) | Implement an exhaustive search solver for the Job Assignment problem (finding min cost assignment). |
| **Q6** | **DT** (Distance Transform) | Design an engine to compute the Distance Transform (chessboard distance) for binary images. |

---

Each `Q*` folder typically contains:

* `00_TB/`: Testbench files.
* `ref_solution/`: Initial RTL templates or reference solutions.
* `referenced_spec/`: Detailed problem specifications (look for `human.md`).
* `result/`: Directory for storing simulation/synthesis results.
* `01_run.sh`: Shell script for open-source flow execution.

---

## 🚀 How to Run

There are two primary ways to run the designs: using the provided open-source scripts (Icarus Verilog + Yosys) or the commercial tool flow (VCS).

> **Note:** For the full execution scripts (e.g., `01_run.sh`, `VCS/` folder) and dependencies, please refer to our **[GitHub Repository](https://github.com/weiber2002/ICRTL)** if they are not included in the dataset reconstruction.

### Method 1: Open-Source Flow (Icarus Verilog & Yosys)

Each problem folder contains a `01_run.sh` script that runs simulation using `iverilog` and synthesis using `yosys`.

**Prerequisites:**

* `iverilog` (Icarus Verilog)
* `yosys` (Yosys Open SYnthesis Suite)

**Steps:**

1. Navigate to the problem directory (e.g., `Q1_LBP`).
2. Execute the run script:
```bash
cd Q1_LBP
bash 01_run.sh

```


3. Check `result/` for logs:
* `latency.log`: Simulation output.
* `area.log`: Synthesis area report.

---

## 🔗 Citation

If you use **ICRTL** or the **EvolVE** framework in your research, please cite our paper:

```bibtex
@article{hsin2026evolve,
  title={EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization},
  author={Hsin, Wei-Po and Deng, Ren-Hao and Hsieh, Yao-Ting and Huang, En-Ming and Hung, Shih-Hao},
  journal={arXiv preprint arXiv:2601.18067},
  year={2026},
  url={[https://arxiv.org/abs/2601.18067](https://arxiv.org/abs/2601.18067)}
}

```