Transform WakeWord app with MobileNet UI/UX design and add SR Vela integration

- Apply same modern card-based UI as MobileNet demo
- Add real-time SR110 Vela compiler integration
- Include model upload functionality with compile and download features
- Add CSS overrides to preserve SR110 results colors
- Enhance keyword display with visual grid layout
- Maintain original DSCNN functionality with improved interface

app.py

@@ -4,9 +4,16 @@ import librosa
 import tensorflow as tf
 from scipy.fftpack import dct
 import os
+import tempfile
+import shutil
+import subprocess
+import re
+import requests
+from io import BytesIO
 
 # DSCNN model configuration
 MODEL_PATH = "ds_cnn_l_quantized.tflite"
+DEFAULT_CONFIG = "u55_eval_with_TA_config_400_and_200_MHz.ini"
 
 # Keywords based on Speech Commands dataset (12 classes)
 KEYWORDS = [
@@ -35,6 +42,164 @@ except Exception as e:
     print(f"❌ Error loading DSCNN model: {e}")
     interpreter = None
 
+# Vela config file is copied from SR app
+def extract_summary_from_log(log_text):
+    summary_keys = [
+        "Accelerator configuration",
+        "Accelerator clock",
+        "Total SRAM used",
+        "Total On-chip Flash used",
+        "CPU operators",
+        "NPU operators",
+        "Batch Inference time"
+    ]
+    summary = []
+    for key in summary_keys:
+        match = re.search(rf"{re.escape(key)}\s+(.+)", log_text)
+        if match:
+            value = match.group(1).strip()
+            if key == "Batch Inference time":
+                value = value.split(",")[0].strip()
+                key = "Inference time"
+            summary.append((key, value))
+    return summary
+
+def run_vela(model_file):
+    accel = "ethos-u55-128"
+    optimise = "Size"
+    mem_mode = "Sram_Only"
+    sys_config = "Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.05_GBs"
+    tmpdir = tempfile.mkdtemp()
+    try:
+        # Use the original uploaded model filename
+        original_model_name = os.path.basename(model_file)
+        model_path = os.path.join(tmpdir, original_model_name)
+        shutil.copy(model_file, model_path)
+
+        config_path = os.path.join(tmpdir, DEFAULT_CONFIG)
+        shutil.copy(DEFAULT_CONFIG, config_path)
+
+        output_dir = os.path.join(tmpdir, "vela_out")
+        os.makedirs(output_dir, exist_ok=True)
+
+        cmd = [
+            "vela",
+            f"--accelerator-config={accel}",
+            f"--optimise={optimise}",
+            f"--config={config_path}",
+            f"--memory-mode={mem_mode}",
+            f"--system-config={sys_config}",
+            model_path,
+            "--verbose-cycle-estimate",
+            "--verbose-performance",
+            f"--output-dir={output_dir}"
+        ]
+
+        result = subprocess.run(cmd, capture_output=True, text=True, check=True)
+        vela_stdout = result.stdout
+
+        # Check for unsupported model patterns in logs
+        unsupported_patterns = [
+            "Warning: Unsupported TensorFlow Lite semantics",
+            "Network Tops/s                                    nan Tops/s",
+            "Neural network macs                                 0 MACs/batch"
+        ]
+        if any(pat in vela_stdout for pat in unsupported_patterns):
+            summary_html = (
+                "<div class='sr110-results' style='background:#fff3f3;border-radius:14px;padding:24px 18px 18px 18px;"
+                "max-width:430px;min-width:320px;width:100%;margin:auto;color:#d32f2f;font-family:sans-serif;"
+                "font-size:1.1em;text-align:left;font-weight:600;'>"
+                "This model has unsupported layers and needs investigation based on layers.<br>"
+                "Please use Vela compiler on your Host Machine for further analysis."
+                "</div>"
+            )
+            # Try to provide per-layer.csv if available for download
+            per_layer_csv = None
+            for log_fname in os.listdir(output_dir):
+                if log_fname.endswith("per-layer.csv"):
+                    per_layer_csv = os.path.join("/tmp", log_fname)
+                    shutil.copy(os.path.join(output_dir, log_fname), per_layer_csv)
+                    break
+            return summary_html, None, per_layer_csv
+
+        model_filename = os.path.basename(model_file)
+        if model_filename:
+            vela_stdout = vela_stdout.replace(
+                "Network summary for",
+                f"Network summary for {model_filename} ("
+            )
+
+        summary_items = extract_summary_from_log(vela_stdout)
+        # Convert summary_items to dict for easy access
+        summary_dict = dict(summary_items) if summary_items else {}
+
+        # Build 4 cards for results
+        def clean_ops(val):
+            # Remove '=' and leading/trailing spaces
+            return val.lstrip("= ").strip() if isinstance(val, str) else val
+
+        summary_html = (
+            "<div class='sr110-results' style='background:#1e1e2f;border-radius:18px;padding:18px 18px 12px 18px;"
+            "max-width:430px;min-width:320px;width:100%;margin:auto;color:#eee;font-family:sans-serif;'>"
+            "<h3 class='sr110-title' style='margin-top:0;margin-bottom:12px;font-size:1.35em;color:#00b0ff;text-align:left;'>Estimated Results on SR110</h3>"
+            "<div style='display:flex;flex-wrap:wrap;gap:10px;justify-content:center;'>"
+            # Card 1: Accelerator
+            "<div class='sr110-card' style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>"
+            "<div class='sr110-title' style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>🚀 Accelerator</div>"
+            f"<div style='margin-bottom:2px;'><span class='sr110-label' style='color:#ccc;'>Configuration:</span> <span class='sr110-value' style='color:#fff;font-weight:500'>{summary_dict.get('Accelerator configuration','-')}</span></div>"
+            f"<div><span class='sr110-label' style='color:#ccc;'>Accelerator clock:</span> <span class='sr110-value' style='color:#fff;font-weight:500'>{summary_dict.get('Accelerator clock','-')}</span></div>"
+            "</div>"
+            # Card 2: Memory Usage
+            "<div class='sr110-card' style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>"
+            "<div class='sr110-title' style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>💾 Memory Usage</div>"
+            f"<div style='margin-bottom:2px;'><span class='sr110-label' style='color:#ccc;'>Total SRAM:</span> <span class='sr110-value' style='color:#fff;font-weight:500'>{summary_dict.get('Total SRAM used','-')}</span></div>"
+            f"<div><span class='sr110-label' style='color:#ccc;'>Total On-chip Flash:</span> <span class='sr110-value' style='color:#fff;font-weight:500'>{summary_dict.get('Total On-chip Flash used','-')}</span></div>"
+            "</div>"
+            # Card 3: Operator Distribution
+            "<div class='sr110-card' style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>"
+            "<div class='sr110-title' style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>📈 Operator Distribution</div>"
+            f"<div style='margin-bottom:2px;'><span class='sr110-label' style='color:#ccc;'>CPU Operators:</span> <span class='sr110-value' style='color:#fff;font-weight:500'>{clean_ops(summary_dict.get('CPU operators','-'))}</span></div>"
+            f"<div><span class='sr110-label' style='color:#ccc;'>NPU Operators:</span> <span class='sr110-value' style='color:#fff;font-weight:500'>{clean_ops(summary_dict.get('NPU operators','-'))}</span></div>"
+            "</div>"
+            # Card 4: Performance
+            "<div class='sr110-card' style='flex:1 1 170px;min-width:170px;max-width:180px;background:#23233a;border-radius:12px;padding:10px 10px 8px 10px;'>"
+            "<div class='sr110-title' style='font-size:1em;font-weight:520;margin-bottom:6px;color:#00b0ff;'>⚡ Performance</div>"
+            f"<div><span class='sr110-label' style='color:#ccc;'>Inference time:</span> <span class='sr110-value' style='color:#fff;font-weight:500'>{summary_dict.get('Inference time','-')}</span></div>"
+            "</div>"
+            "</div></div>"
+        ) if summary_items else "<div style='color:red'>Summary info not found in log.</div>"
+
+        for fname in os.listdir(output_dir):
+            if fname.endswith("vela.tflite"):
+                final_path = os.path.join("/tmp", fname)
+                shutil.copy(os.path.join(output_dir, fname), final_path)
+                # Find per-layer.csv file for logs
+                per_layer_csv = None
+                for log_fname in os.listdir(output_dir):
+                    if log_fname.endswith("per-layer.csv"):
+                        per_layer_csv = os.path.join("/tmp", log_fname)
+                        shutil.copy(os.path.join(output_dir, log_fname), per_layer_csv)
+                        break
+                return summary_html, final_path, per_layer_csv
+
+        # If no tflite, still try to return per-layer.csv if present
+        per_layer_csv = None
+        for log_fname in os.listdir(output_dir):
+            if log_fname.endswith("per-layer.csv"):
+                per_layer_csv = os.path.join("/tmp", log_fname)
+                shutil.copy(os.path.join(output_dir, log_fname), per_layer_csv)
+                break
+        return summary_html, None, per_layer_csv
+    finally:
+        shutil.rmtree(tmpdir)
+
+# Run Vela analysis on startup and cache results
+print("Running Vela analysis on DSCNN model...")
+try:
+    vela_html, compiled_model, per_layer_csv = run_vela(MODEL_PATH)
+except Exception as e:
+    vela_html = f"<div style='color:red'>Vela analysis failed: {str(e)}</div>"
+
 def extract_mfcc_features(audio_path, target_length=490):
     """
     Extract MFCC features exactly as specified in the original DSCNN paper.
@@ -167,7 +332,7 @@ def classify_audio(audio_input):
             confidence = pred['score'] * 100
             label = pred['label']
             indicator = "🎯" if i == 0 else "  "
-            results.append(f"{indicator} {i+1}. {label}: {confidence:.1f}%")
+            results.append(f"{indicator} {i+1}. **{label}**: {confidence:.1f}%")
         
         return "\n".join(results)
         
@@ -180,28 +345,390 @@ def classify_audio(audio_input):
         else:
             return f"❌ Error processing audio: {error_msg}\n\nTip: Try recording a clear 1-second word like 'yes' or 'stop'."
 
-# Create the Gradio interface
-demo = gr.Interface(
-    fn=classify_audio,
-    inputs=gr.Audio(sources=["microphone", "upload"], type="filepath", label="Record or Upload Audio"),
-    outputs=gr.Textbox(label="DSCNN Keyword Predictions", lines=8),
-    title="🎤 DSCNN Wake Word Detection Demo",
-    description="""
-    **Advanced wake word detection using Depthwise Separable CNN (DSCNN)**
+def load_example_audio(example_name):
+    """Load example audio for demonstration."""
+    # This would load pre-recorded examples if available
+    return None
+
+def compile_uploaded_model(model_file):
+    """Compile uploaded model with Vela and return results"""
+    if model_file is None:
+        error_html = (
+            "<div class='sr110-results' style='background:#fff3f3;border-radius:14px;padding:24px 18px 18px 18px;"
+            "max-width:430px;min-width:320px;width:100%;margin:auto;color:#d32f2f;font-family:sans-serif;"
+            "font-size:1.1em;text-align:center;font-weight:600;'>"
+            "No model file uploaded."
+            "</div>"
+        )
+        return (
+            error_html,
+            gr.update(visible=False, value=None),
+            gr.update(visible=False, value=None)
+        )
+    
+    try:
+        # Run Vela analysis on uploaded model
+        results_html, compiled_model_path, per_layer_csv = run_vela(model_file)
+        
+        return (
+            results_html,
+            gr.update(visible=compiled_model_path is not None, value=compiled_model_path),
+            gr.update(visible=per_layer_csv is not None, value=per_layer_csv)
+        )
+    except Exception as e:
+        error_html = (
+            "<div class='sr110-results' style='background:#fff3f3;border-radius:14px;padding:24px 18px 18px 18px;"
+            "max-width:430px;min-width:320px;width:100%;margin:auto;color:#d32f2f;font-family:sans-serif;"
+            "font-size:1.1em;text-align:center;font-weight:600;'>"
+            f"Vela compilation failed: {str(e)}"
+            "</div>"
+        )
+        return (
+            error_html,
+            gr.update(visible=False, value=None),
+            gr.update(visible=False, value=None)
+        )
+
+# Create Gradio interface
+with gr.Blocks(
+    theme=gr.themes.Default(),
+    title="DSCNN Wake Word Detection",
+    css="""
+        body {
+            background: #fafafa !important;
+        }
+        .gradio-container {
+            max-width: 1200px !important;
+            margin-left: auto !important;
+            margin-right: auto !important;
+            background-color: #fafafa !important;
+            font-family: 'Inter', 'Segoe UI', -apple-system, sans-serif !important;
+        }
+        .gr-row {
+            display: flex !important;
+            justify-content: center !important;
+            align-items: flex-start !important;
+            gap: 48px !important;
+        }
+        .gr-column {
+            align-items: flex-start !important;
+            justify-content: flex-start !important;
+        }
+        .fixed-upload-box {
+            width: 100% !important;
+            max-width: 420px !important;
+            margin-bottom: 18px !important;
+        }
+        .download-btn-custom, .compile-btn-custom {
+            width: 100% !important;
+            margin-bottom: 18px !important;
+        }
+        .upload-file-box .w-full, .download-file-box .w-full {
+            height: 120px !important;
+            background: #232b36 !important;
+            border-radius: 8px !important;
+            color: #fff !important;
+            font-weight: 600 !important;
+            font-size: 1.1em !important;
+            box-shadow: none !important;
+            display: flex !important;
+            align-items: center !important;
+            justify-content: center !important;
+        }
+        .upload-file-box .w-full .file-preview {
+            margin: 0 auto !important;
+            text-align: center !important;
+            width: 100%;
+        }
+        #run-vela-btn, .compile-btn, .compile-btn-custom {
+            background-color: #007dc3 !important;
+            color: white !important;
+            font-size: 1.1em;
+            border-radius: 8px;
+            margin-top: 12px;
+            margin-bottom: 18px;
+            text-align: center;
+            height: 40px !important;
+        }
+        .results-summary-box, #results-summary {
+            margin-left: 0 !important;
+        }
+        h1, h3, .gr-markdown h1, .gr-markdown h3 { color: #1976d2 !important; }
+        p, .gr-markdown p, .gr-markdown span, .gr-markdown { color: #222 !important; }
+        .custom-footer {
+            display: block !important;
+            margin: 40px auto 0 auto !important;
+            max-width: 600px !important;
+            width: 100% !important;
+            background: #e6f4ff !important;
+            border-radius: 10px !important;
+            box-shadow: 0 2px 2px #0001 !important;
+            padding: 24px 32px 24px 32px !important;
+            font-size: 1.13em !important;
+            color: #0a2540 !important;
+            font-family: sans-serif !important;
+            text-align: center !important;
+            position: relative !important;
+            z-index: 10 !important;
+        }
+        .custom-footer a {
+            color: #0074d9 !important;
+            text-decoration: underline !important;
+            font-weight: 700 !important;
+        }
+        .card {
+            background: white !important;
+            border-radius: 12px !important;
+            box-shadow: 0 4px 6px -1px rgba(0, 0, 0, 0.1), 0 2px 4px -1px rgba(0, 0, 0, 0.06) !important;
+            border: 1px solid #e5e7eb !important;
+            margin-bottom: 1.5rem !important;
+            transition: all 0.2s ease-in-out !important;
+            overflow: hidden !important;
+        }
+        .card > * {
+            padding: 0 !important;
+            margin: 0 !important;
+        }
+        .card:hover {
+            box-shadow: 0 10px 15px -3px rgba(0, 0, 0, 0.1), 0 4px 6px -2px rgba(0, 0, 0, 0.05) !important;
+            transform: translateY(-1px) !important;
+        }
+        .card-header {
+            background: linear-gradient(135deg, #1975cf 0%, #1557b0 100%) !important;
+            color: white !important;
+            padding: 1rem 1.5rem !important;
+            border-radius: 12px 12px 0 0 !important;
+            font-weight: 600 !important;
+            font-size: 1.1rem !important;
+        }
+        .card-header,
+        div.card-header,
+        div.card-header span,
+        div.card-header * {
+            color: white !important;
+        }
+        .card-content {
+            padding: 1.5rem !important;
+            color: #4b5563 !important;
+            line-height: 1.6 !important;
+            background: white !important;
+        }
+        .stats-grid {
+            display: grid !important;
+            grid-template-columns: 1fr 1fr !important;
+            gap: 1.5rem !important;
+            margin-top: 1.5rem !important;
+        }
+        .stat-item {
+            background: #f8fafc !important;
+            padding: 1rem !important;
+            border-radius: 8px !important;
+            border-left: 4px solid #1975cf !important;
+        }
+        .stat-label {
+            font-weight: 600 !important;
+            color: #4b5563 !important;
+            font-size: 0.9rem !important;
+            margin-bottom: 0.5rem !important;
+        }
+        .stat-value {
+            color: #4b5563 !important;
+            font-size: 0.85rem !important;
+        }
+        .btn-example {
+            background: #f1f5f9 !important;
+            border: 1px solid #cbd5e1 !important;
+            color: #4b5563 !important;
+            border-radius: 6px !important;
+            transition: all 0.2s ease !important;
+            margin: 0.35rem !important;
+            padding: 0.5rem 1rem !important;
+        }
+        .btn-example:hover {
+            background: #1975cf !important;
+            border-color: #1975cf !important;
+            color: white !important;
+        }
+        .btn-primary {
+            background: #1975cf !important;
+            border-color: #1975cf !important;
+            color: white !important;
+        }
+        .btn-primary:hover {
+            background: #1557b0 !important;
+            border-color: #1557b0 !important;
+        }
+        .markdown {
+            color: #374151 !important;
+        }
+        .results-text {
+            color: #4b5563 !important;
+            font-weight: 500 !important;
+            padding: 0 !important;
+            margin: 0 !important;
+        }
+        .results-text p {
+            color: #4b5563 !important;
+            margin: 0.5rem 0 !important;
+        }
+        .results-text * {
+            color: #4b5563 !important;
+        }
+        div[data-testid="markdown"] p {
+            color: #4b5563 !important;
+        }
+        .prose {
+            color: #4b5563 !important;
+        }
+        .prose * {
+            color: #4b5563 !important;
+        }
+        .card-header,
+        .card-header * {
+            color: white !important;
+        }
+        /* Override grey colors for SR110 Vela results section - MUST be after prose rules */
+        .prose .sr110-results,
+        .prose .sr110-results *,
+        .prose .sr110-results h3,
+        .prose .sr110-results div,
+        .prose .sr110-results span,
+        .sr110-results,
+        .sr110-results *,
+        .sr110-results h3,
+        .sr110-results div,
+        .sr110-results span {
+            color: inherit !important;
+        }
+        /* Preserve original colors for dark theme cards with higher specificity */
+        .prose .sr110-results .sr110-card,
+        .sr110-results .sr110-card {
+            background: #23233a !important;
+        }
+        .prose .sr110-results .sr110-title,
+        .sr110-results .sr110-title {
+            color: #00b0ff !important;
+        }
+        .prose .sr110-results .sr110-label,
+        .sr110-results .sr110-label {
+            color: #ccc !important;
+        }
+        .prose .sr110-results .sr110-value,
+        .sr110-results .sr110-value {
+            color: #fff !important;
+        }
+    """
+) as demo:
     
-    This demo uses a quantized DSCNN model optimized for edge deployment. Upload audio or record directly to test keyword recognition.
+    gr.HTML("""
+    <div class="main-header">
+        <h1>🎤 DSCNN Wake Word Detection</h1>
+    </div>
+    """)
     
-    **Supported Keywords:** yes, no, up, down, left, right, on, off, stop, go, silence, unknown
+    with gr.Row():
+        with gr.Column(scale=1):
+            
+            input_audio = gr.Audio(
+                sources=["microphone", "upload"],
+                type="filepath",
+                label="Record or Upload Audio",
+                value=None
+            )
+            
+            classify_btn = gr.Button(
+                "Detect Wake Word",
+                variant="primary",
+                size="lg",
+                elem_classes=["btn-primary"]
+            )
+            
+            with gr.Group(elem_classes=["card"]):
+                gr.HTML('<div class="card-header"><span style="color: white; font-weight: 600;">Supported Keywords</span></div>')
+                
+                with gr.Column(elem_classes=["card-content"]):
+                    gr.HTML("""
+                    <div style="display: grid; grid-template-columns: repeat(3, 1fr); gap: 0.5rem; text-align: center;">
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">yes</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">no</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">up</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">down</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">left</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">right</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">on</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">off</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">stop</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">go</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">silence</div>
+                        <div style="padding: 0.5rem; background: #f8fafc; border-radius: 6px; font-weight: 500;">unknown</div>
+                    </div>
+                    """)
+            
+            # Add Model Upload Section
+            with gr.Group(elem_classes=["card"]):
+                gr.HTML('<div class="card-header"><span style="color: white; font-weight: 600;">Upload Your TFLite Model</span></div>')
+                
+                with gr.Column(elem_classes=["card-content"]):
+                    model_file = gr.File(
+                        file_types=[".tflite"],
+                        label="Upload .tflite model for Vela analysis",
+                        interactive=True
+                    )
+                    
+                    compile_btn = gr.Button(
+                        "Compile Model for SR110",
+                        variant="primary",
+                        size="lg",
+                        elem_classes=["btn-primary"]
+                    )
+                    
+                    download_model_btn = gr.DownloadButton(
+                        label="Download Compiled Model",
+                        visible=False,
+                        elem_classes=["btn-primary"]
+                    )
+                    
+                    download_logs_btn = gr.DownloadButton(
+                        label="Download Per Layer Logs",
+                        visible=False,
+                        elem_classes=["btn-primary"]
+                    )
+        
+        with gr.Column(scale=1):
+            # Display Vela analysis results (dynamic)
+            vela_results_html = gr.HTML(vela_html)
+            
+            with gr.Group(elem_classes=["card"]):
+                gr.HTML('<div class="card-header"><span style="color: white; font-weight: 600;">Wake Word Detection Results</span></div>')
+                
+                with gr.Column(elem_classes=["card-content"]):
+                    output_text = gr.Markdown(
+                        value="Record or upload audio to see wake word predictions...",
+                        label="",
+                        elem_classes=["results-text"]
+                    )
     
-    **Model Details:**
-    - Architecture: Depthwise Separable CNN (DSCNN) 
-    - Quantization: INT8 (504KB model size)
-    - Accuracy: 94.5% on Google Speech Commands
-    - Input: MFCC features (1×490)
-    - Optimized for: ARM Cortex-M, embedded systems
-    """
-)
+    # Set up event handlers
+    classify_btn.click(
+        fn=classify_audio,
+        inputs=input_audio,
+        outputs=output_text
+    )
+    
+    # Model compile handler
+    compile_btn.click(
+        fn=compile_uploaded_model,
+        inputs=[model_file],
+        outputs=[vela_results_html, download_model_btn, download_logs_btn]
+    )
+    
+    # Auto-classify when audio is uploaded
+    input_audio.change(
+        fn=classify_audio,
+        inputs=input_audio,
+        outputs=output_text
+    )
 
 # Launch the demo
 if __name__ == "__main__":
-    demo.launch(share=True) 
+    demo.launch()

requirements.txt

@@ -4,4 +4,7 @@ librosa>=0.10.0
 soundfile>=0.12.0
 numpy>=1.21.0
 scipy>=1.9.0
-pydantic==2.10.6 
+pydantic==2.10.6
+ethos-u-vela
+requests
+pillow 

u55_eval_with_TA_config_400_and_200_MHz.ini

@@ -0,0 +1,565 @@
+; Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved.
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Licensed under the Apache License, Version 2.0 (the License); you may
+; not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+; www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+
+; -----------------------------------------------------------------------------
+; Vela configuration file
+
+; -----------------------------------------------------------------------------
+; System Configuration
+
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (3.2 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_3.2_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=1.0
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=12
+OffChipFlash_write_latency=12
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (1.6 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_1.6_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.5
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=15
+OffChipFlash_write_latency=15
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "2000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.8 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.8_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.25
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=18
+OffChipFlash_write_latency=18
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "1000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.4 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.4_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.125
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=24
+OffChipFlash_write_latency=24
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "500"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.2 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.2_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0625
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=36
+OffChipFlash_write_latency=36
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "250"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.1 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.1_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0312
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=60
+OffChipFlash_write_latency=60
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "125"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.05 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.05_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0156
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=108
+OffChipFlash_write_latency=108
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "62"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 400 MHz, SRAM (3.2 GB/s) and Flash (0.025 GB/s)
+[System_Config.Ethos_U55_400MHz_SRAM_3.2_GBs_Flash_0.025_GBs]
+core_clock=400e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0078
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=204
+OffChipFlash_write_latency=204
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "31"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+
+
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (1.6 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_1.6_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=1.0
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=12
+OffChipFlash_write_latency=12
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "12"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.8 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.8_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.5
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=15
+OffChipFlash_write_latency=15
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "15"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "2000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.4 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.4_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.25
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=18
+OffChipFlash_write_latency=18
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "18"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "1000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.2 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.2_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.125
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=24
+OffChipFlash_write_latency=24
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "24"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "500"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.1 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.1_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0625
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=36
+OffChipFlash_write_latency=36
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "36"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "250"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.05 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.05_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0312
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=60
+OffChipFlash_write_latency=60
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "60"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "125"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.025 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.025_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0156
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=108
+OffChipFlash_write_latency=108
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "108"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "62"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;Ethos-U55 : 200 MHz, SRAM (1.6 GB/s) and Flash (0.0125 GB/s)
+[System_Config.Ethos_U55_200MHz_SRAM_1.6_GBs_Flash_0.0125_GBs]
+core_clock=200e6
+axi0_port=Sram
+axi1_port=OffChipFlash
+Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=8
+Sram_write_latency=8
+OffChipFlash_clock_scale=0.0078
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=204
+OffChipFlash_write_latency=204
+
+;set(TA0_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA0_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA0_RLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA0_WLATENCY    "8"        CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA0_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA0_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA0_BWCAP       "4000"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+;set(TA1_MAXR        "4"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+;set(TA1_MAXW        "4"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+;set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+;set(TA1_RLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+;set(TA1_WLATENCY    "204"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+;set(TA1_PULSE_ON    "3999"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+;set(TA1_PULSE_OFF   "1"        CACHE STRING "No. of cycles addresses blocked (0-65535).")
+;set(TA1_BWCAP       "31"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+
+
+
+; -----------------------------------------------------------------------------
+; Memory Mode
+
+; SRAM Only: only one AXI port is used and the SRAM is used for all storage
+[Memory_Mode.Sram_Only]
+const_mem_area=Axi0
+arena_mem_area=Axi0
+cache_mem_area=Axi0
+
+; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software
+; The non-SRAM memory is assumed to be read-only
+[Memory_Mode.Shared_Sram]
+const_mem_area=Axi1
+arena_mem_area=Axi0
+cache_mem_area=Axi0
+
+; Dedicated SRAM: the SRAM (384KB) is only for use by the Ethos-U
+; The non-SRAM memory is assumed to be read-writeable
+[Memory_Mode.Dedicated_Sram]
+const_mem_area=Axi1
+arena_mem_area=Axi1
+cache_mem_area=Axi0
+arena_cache_size=393216
+
+; Dedicated SRAM 512KB: the SRAM (512KB) is only for use by the Ethos-U
+; The non-SRAM memory is assumed to be read-writeable
+[Memory_Mode.Dedicated_Sram_512KB]
+inherit=Memory_Mode.Dedicated_Sram
+arena_cache_size=524288