VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Paper
• 2309.07544 • Published
• 2
Verilog Code Generation
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CodeV-R1: Reasoning-Enhanced Verilog Generation
Paper • 2505.24183 • Published • 9 -
VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
Paper • 2505.20302 • Published • 1 -
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
Paper • 2506.00005 • Published -
CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization
Paper • 2407.10424 • Published • 12 -
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Paper • 2212.11140 • Published • 1 -
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model
Paper • 2504.14560 • Published -
PyraNet: A Multi-Layered Hierarchical Dataset for Verilog
Paper • 2412.06947 • Published • 1 -
VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation
Paper • 2504.15659 • Published -
AIvril: AI-Driven RTL Generation With Verification In-The-Loop
Paper • 2409.11411 • Published -
ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generation
Paper • 2407.12022 • Published -
VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
Paper • 2505.11849 • Published • 2 -
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
Paper • 2504.15804 • Published