INSTRUCTION
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| RESPONSE
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: return: True if two Value instances are same: note: not just equal
|
def isSameHVal(a: Value, b: Value) -> bool:
"""
:return: True if two Value instances are same
:note: not just equal
"""
return a is b or (isinstance(a, Value)
and isinstance(b, Value)
and a.val == b.val
and a.vldMask == b.vldMask)
|
: return: True if two vectors of Value instances are same: note: not just equal
|
def areSameHVals(a: Union[None, List[Value]],
b: Union[None, List[Value]]) -> bool:
"""
:return: True if two vectors of Value instances are same
:note: not just equal
"""
if a is b:
return True
if a is None or b is None:
return False
if len(a) == len(b):
for a_, b_ in zip(a, b):
if not isSameHVal(a_, b_):
return False
return True
else:
return False
|
: return: True if two lists of HdlStatement instances are same
|
def isSameStatementList(stmListA: List[HdlStatement],
stmListB: List[HdlStatement]) -> bool:
"""
:return: True if two lists of HdlStatement instances are same
"""
if stmListA is stmListB:
return True
if stmListA is None or stmListB is None:
return False
for a, b in zip(stmListA, stmListB):
if not a.isSame(b):
return False
return True
|
: return: True if all statements are same
|
def statementsAreSame(statements: List[HdlStatement]) -> bool:
"""
:return: True if all statements are same
"""
iterator = iter(statements)
try:
first = next(iterator)
except StopIteration:
return True
return all(first.isSame(rest) for rest in iterator)
|
: return: first statement with rank > 0 or None if iterator empty
|
def _get_stm_with_branches(stm_it):
"""
:return: first statement with rank > 0 or None if iterator empty
"""
last = None
while last is None or last.rank == 0:
try:
last = next(stm_it)
except StopIteration:
last = None
break
return last
|
Clean informations about enclosure for outputs and sensitivity of this statement
|
def _clean_signal_meta(self):
"""
Clean informations about enclosure for outputs and sensitivity
of this statement
"""
self._enclosed_for = None
self._sensitivity = None
for stm in self._iter_stms():
stm._clean_signal_meta()
|
Collect inputs/ outputs from all child statements to: py: attr: ~_input/: py: attr: _output attribure on this object
|
def _collect_io(self) -> None:
"""
Collect inputs/outputs from all child statements
to :py:attr:`~_input` / :py:attr:`_output` attribure on this object
"""
in_add = self._inputs.extend
out_add = self._outputs.extend
for stm in self._iter_stms():
in_add(stm._inputs)
out_add(stm._outputs)
|
Discover enclosure for list of statements
|
def _discover_enclosure_for_statements(statements: List['HdlStatement'],
outputs: List['HdlStatement']):
"""
Discover enclosure for list of statements
:param statements: list of statements in one code branch
:param outputs: list of outputs which should be driven from this statement list
:return: set of signals for which this statement list have always some driver
(is enclosed)
"""
result = set()
if not statements:
return result
for stm in statements:
stm._discover_enclosure()
for o in outputs:
has_driver = False
for stm in statements:
if o in stm._outputs:
assert not has_driver
has_driver = False
if o in stm._enclosed_for:
result.add(o)
else:
pass
return result
|
Discover sensitivity for list of signals
|
def _discover_sensitivity_seq(self,
signals: List[RtlSignalBase],
seen: set, ctx: SensitivityCtx)\
-> None:
"""
Discover sensitivity for list of signals
"""
casualSensitivity = set()
for s in signals:
s._walk_sensitivity(casualSensitivity, seen, ctx)
if ctx.contains_ev_dependency:
break
# if event dependent sensitivity found do not add other sensitivity
if not ctx.contains_ev_dependency:
ctx.extend(casualSensitivity)
|
get RtlNetlist context from signals
|
def _get_rtl_context(self):
"""
get RtlNetlist context from signals
"""
for sig in chain(self._inputs, self._outputs):
if sig.ctx:
return sig.ctx
else:
# Param instances does not have context
continue
raise HwtSyntaxError(
"Statement does not have any signal in any context", self)
|
Update signal IO after reuce atempt
|
def _on_reduce(self, self_reduced: bool, io_changed: bool,
result_statements: List["HdlStatement"]) -> None:
"""
Update signal IO after reuce atempt
:param self_reduced: if True this object was reduced
:param io_changed: if True IO of this object may changed
and has to be updated
:param result_statements: list of statements which are result
of reduce operation on this statement
"""
parentStm = self.parentStm
if self_reduced:
was_top = parentStm is None
# update signal drivers/endpoints
if was_top:
# disconnect self from signals
ctx = self._get_rtl_context()
ctx.statements.remove(self)
ctx.statements.update(result_statements)
for i in self._inputs:
i.endpoints.discard(self)
for o in self._outputs:
o.drivers.remove(self)
for stm in result_statements:
stm.parentStm = parentStm
if parentStm is None:
# conect signals to child statements
for inp in stm._inputs:
inp.endpoints.append(stm)
for outp in stm._outputs:
outp.drivers.append(stm)
else:
# parent has to update it's inputs/outputs
if io_changed:
self._inputs = UniqList()
self._outputs = UniqList()
self._collect_io()
|
After merging statements update IO sensitivity and context
|
def _on_merge(self, other):
"""
After merging statements update IO, sensitivity and context
:attention: rank is not updated
"""
self._inputs.extend(other._inputs)
self._outputs.extend(other._outputs)
if self._sensitivity is not None:
self._sensitivity.extend(other._sensitivity)
else:
assert other._sensitivity is None
if self._enclosed_for is not None:
self._enclosed_for.update(other._enclosed_for)
else:
assert other._enclosed_for is None
other_was_top = other.parentStm is None
if other_was_top:
other._get_rtl_context().statements.remove(other)
for s in other._inputs:
s.endpoints.discard(other)
s.endpoints.append(self)
for s in other._outputs:
s.drivers.discard(other)
s.drivers.append(self)
|
Walk statements and compare if they can be merged into one statement list
|
def _is_mergable_statement_list(cls, stmsA, stmsB):
"""
Walk statements and compare if they can be merged into one statement list
"""
if stmsA is None and stmsB is None:
return True
elif stmsA is None or stmsB is None:
return False
a_it = iter(stmsA)
b_it = iter(stmsB)
a = _get_stm_with_branches(a_it)
b = _get_stm_with_branches(b_it)
while a is not None or b is not None:
if a is None or b is None or not a._is_mergable(b):
return False
a = _get_stm_with_branches(a_it)
b = _get_stm_with_branches(b_it)
# lists are empty
return True
|
Merge statements in list to remove duplicated if - then - else trees
|
def _merge_statements(statements: List["HdlStatement"])\
-> Tuple[List["HdlStatement"], int]:
"""
Merge statements in list to remove duplicated if-then-else trees
:return: tuple (list of merged statements, rank decrease due merging)
:note: rank decrease is sum of ranks of reduced statements
:attention: statement list has to me mergable
"""
order = {}
for i, stm in enumerate(statements):
order[stm] = i
new_statements = []
rank_decrease = 0
for rank, stms in groupedby(statements, lambda s: s.rank):
if rank == 0:
new_statements.extend(stms)
else:
if len(stms) == 1:
new_statements.extend(stms)
continue
# try to merge statements if they are same condition tree
for iA, stmA in enumerate(stms):
if stmA is None:
continue
for iB, stmB in enumerate(islice(stms, iA + 1, None)):
if stmB is None:
continue
if stmA._is_mergable(stmB):
rank_decrease += stmB.rank
stmA._merge_with_other_stm(stmB)
stms[iA + 1 + iB] = None
new_statements.append(stmA)
else:
new_statements.append(stmA)
new_statements.append(stmB)
new_statements.sort(key=lambda stm: order[stm])
return new_statements, rank_decrease
|
Merge two lists of statements into one
|
def _merge_statement_lists(stmsA: List["HdlStatement"], stmsB: List["HdlStatement"])\
-> List["HdlStatement"]:
"""
Merge two lists of statements into one
:return: list of merged statements
"""
if stmsA is None and stmsB is None:
return None
tmp = []
a_it = iter(stmsA)
b_it = iter(stmsB)
a = None
b = None
a_empty = False
b_empty = False
while not a_empty and not b_empty:
while not a_empty:
a = next(a_it, None)
if a is None:
a_empty = True
break
elif a.rank == 0:
# simple statement does not require merging
tmp.append(a)
a = None
else:
break
while not b_empty:
b = next(b_it, None)
if b is None:
b_empty = True
break
elif b.rank == 0:
# simple statement does not require merging
tmp.append(b)
b = None
else:
break
if a is not None or b is not None:
a._merge_with_other_stm(b)
tmp.append(a)
a = None
b = None
return tmp
|
Simplify statements in the list
|
def _try_reduce_list(statements: List["HdlStatement"]):
"""
Simplify statements in the list
"""
io_change = False
new_statements = []
for stm in statements:
reduced, _io_change = stm._try_reduce()
new_statements.extend(reduced)
io_change |= _io_change
new_statements, rank_decrease = HdlStatement._merge_statements(
new_statements)
return new_statements, rank_decrease, io_change
|
After parrent statement become event dependent propagate event dependency flag to child statements
|
def _on_parent_event_dependent(self):
"""
After parrent statement become event dependent
propagate event dependency flag to child statements
"""
if not self._is_completly_event_dependent:
self._is_completly_event_dependent = True
for stm in self._iter_stms():
stm._on_parent_event_dependent()
|
Assign parent statement and propagate dependency flags if necessary
|
def _set_parent_stm(self, parentStm: "HdlStatement"):
"""
Assign parent statement and propagate dependency flags if necessary
"""
was_top = self.parentStm is None
self.parentStm = parentStm
if not self._now_is_event_dependent\
and parentStm._now_is_event_dependent:
self._on_parent_event_dependent()
topStatement = parentStm
while topStatement.parentStm is not None:
topStatement = topStatement.parentStm
parent_out_add = topStatement._outputs.append
parent_in_add = topStatement._inputs.append
if was_top:
for inp in self._inputs:
inp.endpoints.discard(self)
inp.endpoints.append(topStatement)
parent_in_add(inp)
for outp in self._outputs:
outp.drivers.discard(self)
outp.drivers.append(topStatement)
parent_out_add(outp)
ctx = self._get_rtl_context()
ctx.statements.discard(self)
parentStm.rank += self.rank
|
Append statements to this container under conditions specified by condSet
|
def _register_stements(self, statements: List["HdlStatement"],
target: List["HdlStatement"]):
"""
Append statements to this container under conditions specified
by condSet
"""
for stm in flatten(statements):
assert stm.parentStm is None, stm
stm._set_parent_stm(self)
target.append(stm)
|
Disconnect this statement from signals and delete it from RtlNetlist context
|
def _destroy(self):
"""
Disconnect this statement from signals and delete it from RtlNetlist context
:attention: signal endpoints/drivers will be altered
that means they can not be used for iteration
"""
ctx = self._get_rtl_context()
for i in self._inputs:
i.endpoints.discard(self)
for o in self._outputs:
o.drivers.remove(self)
ctx.statements.remove(self)
|
: param val: python string or None: param typeObj: instance of String HdlType: param vldMask: if is None validity is resolved from val if is 0 value is invalidated if is 1 value has to be valid
|
def fromPy(cls, val, typeObj, vldMask=None):
"""
:param val: python string or None
:param typeObj: instance of String HdlType
:param vldMask: if is None validity is resolved from val
if is 0 value is invalidated
if is 1 value has to be valid
"""
assert isinstance(val, str) or val is None
vld = 0 if val is None else 1
if not vld:
assert vldMask is None or vldMask == 0
val = ""
else:
if vldMask == 0:
val = ""
vld = 0
return cls(val, typeObj, vld)
|
Create register in this unit
|
def _reg(self, name, dtype=BIT, defVal=None, clk=None, rst=None):
"""
Create register in this unit
:param defVal: default value of this register,
if this value is specified reset of this component is used
(unit has to have single interface of class Rst or Rst_n)
:param clk: optional clok signal specification
:param rst: optional reset signal specification
:note: rst/rst_n resolution is done from signal type,
if it is negated type it is rst_n
:note: if clk or rst is not specifid default signal
from parent unit will be used
"""
if clk is None:
clk = getClk(self)
if defVal is None:
# if no value is specified reset is not required
rst = None
else:
rst = getRst(self)._sig
if isinstance(dtype, HStruct):
if defVal is not None:
raise NotImplementedError()
container = dtype.fromPy(None)
for f in dtype.fields:
if f.name is not None:
r = self._reg("%s_%s" % (name, f.name), f.dtype)
setattr(container, f.name, r)
return container
return self._ctx.sig(name,
dtype=dtype,
clk=clk._sig,
syncRst=rst,
defVal=defVal)
|
Create signal in this unit
|
def _sig(self, name, dtype=BIT, defVal=None):
"""
Create signal in this unit
"""
if isinstance(dtype, HStruct):
if defVal is not None:
raise NotImplementedError()
container = dtype.fromPy(None)
for f in dtype.fields:
if f.name is not None:
r = self._sig("%s_%s" % (name, f.name), f.dtype)
setattr(container, f.name, r)
return container
return self._ctx.sig(name, dtype=dtype, defVal=defVal)
|
Disconnect internal signals so unit can be reused by parent unit
|
def _cleanAsSubunit(self):
"""Disconnect internal signals so unit can be reused by parent unit"""
for pi in self._entity.ports:
pi.connectInternSig()
for i in chain(self._interfaces, self._private_interfaces):
i._clean()
|
Select fields from structure ( rest will become spacing )
|
def HStruct_selectFields(structT, fieldsToUse):
"""
Select fields from structure (rest will become spacing)
:param structT: HStruct type instance
:param fieldsToUse: dict {name:{...}} or set of names to select,
dictionary is used to select nested fields
in HStruct or HUnion fields
(f.e. {"struct1": {"field1", "field2"}, "field3":{}}
will select field1 and 2 from struct1 and field3 from root)
"""
template = []
fieldsToUse = fieldsToUse
foundNames = set()
for f in structT.fields:
name = None
subfields = []
if f.name is not None:
try:
if isinstance(fieldsToUse, dict):
subfields = fieldsToUse[f.name]
name = f.name
else:
if f.name in fieldsToUse:
name = f.name
except KeyError:
name = None
if name is not None and subfields:
fields = HStruct_selectFields(f.dtype, subfields)
template.append(HStructField(fields, name))
else:
template.append(HStructField(f.dtype, name))
if f.name is not None:
foundNames.add(f.name)
if isinstance(fieldsToUse, dict):
fieldsToUse = set(fieldsToUse.keys())
assert fieldsToUse.issubset(foundNames)
return HStruct(*template)
|
Walk all simple values in HStruct or HArray
|
def walkFlattenFields(sigOrVal, skipPadding=True):
"""
Walk all simple values in HStruct or HArray
"""
t = sigOrVal._dtype
if isinstance(t, Bits):
yield sigOrVal
elif isinstance(t, HUnion):
yield from walkFlattenFields(sigOrVal._val, skipPadding=skipPadding)
elif isinstance(t, HStruct):
for f in t.fields:
isPadding = f.name is None
if not isPadding or not skipPadding:
if isPadding:
v = f.dtype.fromPy(None)
else:
v = getattr(sigOrVal, f.name)
yield from walkFlattenFields(v)
elif isinstance(t, HArray):
for item in sigOrVal:
yield from walkFlattenFields(item)
else:
raise NotImplementedError(t)
|
opposite of packAxiSFrame
|
def HStruct_unpack(structT, data, getDataFn=None, dataWidth=None):
"""
opposite of packAxiSFrame
"""
if getDataFn is None:
assert dataWidth is not None
def _getDataFn(x):
return toHVal(x)._auto_cast(Bits(dataWidth))
getDataFn = _getDataFn
val = structT.fromPy(None)
fData = iter(data)
# actual is storage variable for items from frameData
actualOffset = 0
actual = None
for v in walkFlattenFields(val, skipPadding=False):
# walk flatten fields and take values from fData and parse them to
# field
required = v._dtype.bit_length()
if actual is None:
actualOffset = 0
try:
actual = getDataFn(next(fData))
except StopIteration:
raise Exception("Input data too short")
if dataWidth is None:
dataWidth = actual._dtype.bit_length()
actuallyHave = dataWidth
else:
actuallyHave = actual._dtype.bit_length() - actualOffset
while actuallyHave < required:
# collect data for this field
try:
d = getDataFn(next(fData))
except StopIteration:
raise Exception("Input data too short")
actual = d._concat(actual)
actuallyHave += dataWidth
if actuallyHave >= required:
# parse value of actual to field
# skip padding
_v = actual[(required + actualOffset):actualOffset]
_v = _v._auto_cast(v._dtype)
v.val = _v.val
v.vldMask = _v.vldMask
v.updateTime = _v.updateTime
# update slice out what was taken
actuallyHave -= required
actualOffset += required
if actuallyHave == 0:
actual = None
if actual is not None:
assert actual._dtype.bit_length(
) - actualOffset < dataWidth, "It should be just a padding at the end of frame"
return val
|
Convert signum no bit manipulation just data are represented differently
|
def _convSign(self, signed):
"""
Convert signum, no bit manipulation just data are represented
differently
:param signed: if True value will be signed,
if False value will be unsigned,
if None value will be vector without any sign specification
"""
if isinstance(self, Value):
return self._convSign__val(signed)
else:
if self._dtype.signed == signed:
return self
t = copy(self._dtype)
t.signed = signed
if signed is None:
cnv = AllOps.BitsAsVec
elif signed:
cnv = AllOps.BitsAsSigned
else:
cnv = AllOps.BitsAsUnsigned
return Operator.withRes(cnv, [self], t)
|
Construct value from pythonic value ( int bytes enum. Enum member )
|
def fromPy(cls, val, typeObj, vldMask=None):
"""
Construct value from pythonic value (int, bytes, enum.Enum member)
"""
assert not isinstance(val, Value)
if val is None:
vld = 0
val = 0
assert vldMask is None or vldMask == 0
else:
allMask = typeObj.all_mask()
w = typeObj.bit_length()
if isinstance(val, bytes):
val = int.from_bytes(
val, byteorder="little", signed=bool(typeObj.signed))
else:
try:
val = int(val)
except TypeError as e:
if isinstance(val, enum.Enum):
val = int(val.value)
else:
raise e
if vldMask is None:
vld = allMask
else:
assert vldMask <= allMask and vldMask >= 0
vld = vldMask
if val < 0:
assert typeObj.signed
assert signFix(val & allMask, w) == val, (
val, signFix(val & allMask, w))
val = signFix(val & vld, w)
else:
if typeObj.signed:
msb = 1 << (w - 1)
if msb & val:
assert val < 0, val
if val & allMask != val:
raise ValueError(
"Not enought bits to represent value",
val, val & allMask)
val = val & vld
return cls(val, typeObj, vld)
|
Concatenate this with other to one wider value/ signal
|
def _concat(self, other):
"""
Concatenate this with other to one wider value/signal
"""
w = self._dtype.bit_length()
try:
other_bit_length = other._dtype.bit_length
except AttributeError:
raise TypeError("Can not concat bits and", other._dtype)
other_w = other_bit_length()
resWidth = w + other_w
resT = Bits(resWidth)
if areValues(self, other):
return self._concat__val(other)
else:
w = self._dtype.bit_length()
other_w = other._dtype.bit_length()
resWidth = w + other_w
resT = Bits(resWidth)
# is instance of signal
if isinstance(other, InterfaceBase):
other = other._sig
if isinstance(other._dtype, Bits):
if other._dtype.signed is not None:
other = other._vec()
elif other._dtype == BOOL:
other = other._auto_cast(BIT)
else:
raise TypeError(other._dtype)
if self._dtype.signed is not None:
self = self._vec()
return Operator.withRes(AllOps.CONCAT, [self, other], resT)\
._auto_cast(Bits(resWidth,
signed=self._dtype.signed))
|
register sensitivity for process
|
def sensitivity(proc: HWProcess, *sensitiveTo):
"""
register sensitivity for process
"""
for s in sensitiveTo:
if isinstance(s, tuple):
sen, s = s
if sen == SENSITIVITY.ANY:
s.simSensProcs.add(proc)
elif sen == SENSITIVITY.RISING:
s.simRisingSensProcs.add(proc)
elif sen == SENSITIVITY.FALLING:
s.simFallingSensProcs.add(proc)
else:
raise AssertionError(sen)
else:
s.simSensProcs.add(proc)
|
Evaluate list of values as condition
|
def simEvalCond(simulator, *conds):
"""
Evaluate list of values as condition
"""
_cond = True
_vld = True
for v in conds:
val = bool(v.val)
fullVld = v.vldMask == 1
if fullVld:
if not val:
return False, True
else:
return False, False
_cond = _cond and val
_vld = _vld and fullVld
return _cond, _vld
|
Connect ports of simulation models by name
|
def connectSimPort(simUnit, subSimUnit, srcName, dstName, direction):
"""
Connect ports of simulation models by name
"""
if direction == DIRECTION.OUT:
origPort = getattr(subSimUnit, srcName)
newPort = getattr(simUnit, dstName)
setattr(subSimUnit, srcName, newPort)
else:
origPort = getattr(subSimUnit, dstName)
newPort = getattr(simUnit, srcName)
setattr(subSimUnit, dstName, newPort)
subSimUnit._ctx.signals.remove(origPort)
|
Create value updater for simulation
|
def mkUpdater(nextVal: Value, invalidate: bool):
"""
Create value updater for simulation
:param nextVal: instance of Value which will be asssiggned to signal
:param invalidate: flag which tells if value has been compromised
and if it should be invaidated
:return: function(value) -> tuple(valueHasChangedFlag, nextVal)
"""
def updater(currentVal):
_nextVal = nextVal.clone()
if invalidate:
_nextVal.vldMask = 0
return (valueHasChanged(currentVal, _nextVal), _nextVal)
return updater
|
Create value updater for simulation for value of array type
|
def mkArrayUpdater(nextItemVal: Value, indexes: Tuple[Value],
invalidate: bool):
"""
Create value updater for simulation for value of array type
:param nextVal: instance of Value which will be asssiggned to signal
:param indexes: tuple on indexes where value should be updated
in target array
:return: function(value) -> tuple(valueHasChangedFlag, nextVal)
"""
def updater(currentVal):
if len(indexes) > 1:
raise NotImplementedError("[TODO] implement for more indexes")
_nextItemVal = nextItemVal.clone()
if invalidate:
_nextItemVal.vldMask = 0
index = indexes[0]
change = valueHasChanged(currentVal._getitem__val(index), _nextItemVal)
currentVal._setitem__val(index, _nextItemVal)
return (change, currentVal)
return updater
|
: param val: None or dictionary { index: value } or iterrable of values: param vldMask: if is None validity is resolved from val if is 0 value is invalidated if is 1 value has to be valid
|
def fromPy(cls, val, typeObj, vldMask=None):
"""
:param val: None or dictionary {index:value} or iterrable of values
:param vldMask: if is None validity is resolved from val
if is 0 value is invalidated
if is 1 value has to be valid
"""
size = evalParam(typeObj.size)
if isinstance(size, Value):
size = int(size)
elements = {}
if vldMask == 0:
val = None
if val is None:
pass
elif isinstance(val, dict):
for k, v in val.items():
if not isinstance(k, int):
k = int(k)
elements[k] = typeObj.elmType.fromPy(v)
else:
for k, v in enumerate(val):
if isinstance(v, RtlSignalBase): # is signal
assert v._dtype == typeObj.elmType
e = v
else:
e = typeObj.elmType.fromPy(v)
elements[k] = e
_mask = int(bool(val))
if vldMask is None:
vldMask = _mask
else:
assert (vldMask == _mask)
return cls(elements, typeObj, vldMask)
|
: atention: this will clone item from array iterate over. val if you need to modify items
|
def _getitem__val(self, key):
"""
:atention: this will clone item from array, iterate over .val
if you need to modify items
"""
try:
kv = key.val
if not key._isFullVld():
raise KeyError()
else:
if kv >= self._dtype.size:
raise KeyError()
return self.val[kv].clone()
except KeyError:
return self._dtype.elmType.fromPy(None)
|
create hdl vector value
|
def vec(val, width, signed=None):
"""create hdl vector value"""
return Bits(width, signed, forceVector=True).fromPy(val)
|
Collect data from interface
|
def monitor(self, sim):
"""
Collect data from interface
"""
r = sim.read
if self.notReset(sim):
# update rd signal only if required
if self._lastRd is not 1:
self.wrRd(sim.write, 1)
self._lastRd = 1
# try to run onMonitorReady if there is any
try:
onMonitorReady = self.onMonitorReady
except AttributeError:
onMonitorReady = None
if onMonitorReady is not None:
onMonitorReady(sim)
# wait for response of master
yield sim.waitOnCombUpdate()
vld = self.isVld(r)
assert vld.vldMask, (sim.now, self.intf,
"vld signal is in invalid state")
if vld.val:
# master responded with positive ack, do read data
d = self.doRead(sim)
if self._debugOutput is not None:
self._debugOutput.write(
"%s, read, %d: %r\n" % (
self.intf._getFullName(),
sim.now, d))
self.data.append(d)
if self._afterRead is not None:
self._afterRead(sim)
else:
if self._lastRd is not 0:
# can not receive, say it to masters
self.wrRd(sim.write, 0)
self._lastRd = 0
|
Push data to interface
|
def driver(self, sim):
"""
Push data to interface
set vld high and wait on rd in high then pass new data
"""
r = sim.read
# pop new data if there are not any pending
if self.actualData is NOP and self.data:
self.actualData = self.data.popleft()
doSend = self.actualData is not NOP
# update data on signals if is required
if self.actualData is not self._lastWritten:
if doSend:
self.doWrite(sim, self.actualData)
else:
self.doWrite(sim, None)
self._lastWritten = self.actualData
en = self.notReset(sim)
vld = int(en and doSend)
if self._lastVld is not vld:
self.wrVld(sim.write, vld)
self._lastVld = vld
if not self._enabled:
# we can not check rd it in this function because we can not wait
# because we can be reactivated in this same time
sim.add_process(self.checkIfRdWillBeValid(sim))
return
# wait of response of slave
yield sim.waitOnCombUpdate()
rd = self.isRd(r)
assert rd.vldMask, (sim.now, self.intf,
"rd signal in invalid state")
if not vld:
return
if rd.val:
# slave did read data, take new one
if self._debugOutput is not None:
self._debugOutput.write("%s, wrote, %d: %r\n" % (
self.intf._getFullName(),
sim.now,
self.actualData))
a = self.actualData
# pop new data, because actual was read by slave
if self.data:
self.actualData = self.data.popleft()
else:
self.actualData = NOP
# try to run onDriverWriteAck if there is any
onDriverWriteAck = getattr(self, "onDriverWriteAck", None)
if onDriverWriteAck is not None:
onDriverWriteAck(sim)
onDone = getattr(a, "onDone", None)
if onDone is not None:
onDone(sim)
|
Gues resource usage by HWProcess
|
def HWProcess(cls, proc: HWProcess, ctx: ResourceContext) -> None:
"""
Gues resource usage by HWProcess
"""
seen = ctx.seen
for stm in proc.statements:
encl = stm._enclosed_for
full_ev_dep = stm._is_completly_event_dependent
now_ev_dep = stm._now_is_event_dependent
ev_dep = full_ev_dep or now_ev_dep
out_mux_dim = count_mux_inputs_for_outputs(stm)
for o in stm._outputs:
if o in seen:
continue
i = out_mux_dim[o]
if isinstance(o._dtype, HArray):
assert i == 1, (o, i, " only one ram port per HWProcess")
for a in walk_assignments(stm, o):
assert len(a.indexes) == 1, "one address per RAM port"
addr = a.indexes[0]
ctx.registerRAM_write_port(o, addr, ev_dep)
elif ev_dep:
ctx.registerFF(o)
if i > 1:
ctx.registerMUX(stm, o, i)
elif o not in encl:
ctx.registerLatch(o)
if i > 1:
ctx.registerMUX(stm, o, i)
elif i > 1:
ctx.registerMUX(stm, o, i)
else:
# just a connection
continue
if isinstance(stm, SwitchContainer):
caseEqs = set([stm.switchOn._eq(c[0]) for c in stm.cases])
inputs = chain(
[sig for sig in stm._inputs if sig not in caseEqs], [stm.switchOn])
else:
inputs = stm._inputs
for i in inputs:
# discover only internal signals in this statements for
# operators
if not i.hidden or i in seen:
continue
cls.HWProcess_operators(i, ctx, ev_dep)
|
: return: bit width for this type
|
def bit_length(self):
"""
:return: bit width for this type
"""
try:
itemSize = self.elmType.bit_length
except AttributeError:
itemSize = None
if itemSize is None:
raise TypeError(
"Can not determine size of array because item has"
" not determinable size")
s = self.size
if isinstance(s, RtlSignalBase):
s = int(s.staticEval())
return s * itemSize()
|
Get value of parameter
|
def evalParam(p):
"""
Get value of parameter
"""
while isinstance(p, Param):
p = p.get()
if isinstance(p, RtlSignalBase):
return p.staticEval()
# use rather param inheritance instead of param as param value
return toHVal(p)
|
set value of this param
|
def set(self, val):
"""
set value of this param
"""
assert not self.__isReadOnly, \
("This parameter(%s) was locked"
" and now it can not be changed" % self.name)
assert self.replacedWith is None, \
("This param was replaced with new one and this "
"should not exists")
val = toHVal(val)
self.defVal = val
self._val = val.staticEval()
self._dtype = self._val._dtype
|
Generate flattened register map for HStruct
|
def HTypeFromIntfMap(interfaceMap):
"""
Generate flattened register map for HStruct
:param interfaceMap: sequence of
tuple (type, name) or (will create standard struct field member)
interface or (will create a struct field from interface)
instance of hdl type (is used as padding)
tuple (list of interface, name)
:param DATA_WIDTH: width of word
:param terminalNodes: None or set whre are placed StructField instances
which are derived directly from interface
:return: generator of tuple (type, name, BusFieldInfo)
"""
structFields = []
for m in interfaceMap:
f = HTypeFromIntfMapItem(m)
structFields.append(f)
return HStruct(*structFields)
|
mux record is in format ( self. MUX n m ) where n is number of bits of this mux and m is number of possible inputs
|
def registerMUX(self, stm: Union[HdlStatement, Operator], sig: RtlSignal,
inputs_cnt: int):
"""
mux record is in format (self.MUX, n, m)
where n is number of bits of this mux
and m is number of possible inputs
"""
assert inputs_cnt > 1
res = self.resources
w = sig._dtype.bit_length()
k = (ResourceMUX, w, inputs_cnt)
res[k] = res.get(k, 0) + 1
self.resource_for_object[(stm, sig)] = k
|
Resolve ports of discovered memories
|
def finalize(self):
"""
Resolve ports of discovered memories
"""
ff_to_remove = 0
res = self.resources
for m, addrDict in self.memories.items():
rwSyncPorts, rSyncPorts, wSyncPorts = 0, 0, 0
rwAsyncPorts, rAsyncPorts, wAsyncPorts = 0, 0, 0
rSync_wAsyncPorts, rAsync_wSyncPorts = 0, 0
for _, (rSync, wSync, rAsync, wAsync) in addrDict.items():
if rSync:
ff_to_remove += rSync * m._dtype.elmType.bit_length()
# resolve port count for this addr signal
rwSync = min(rSync, wSync)
rSync -= rwSync
wSync -= rwSync
rwAsync = min(rAsync, wAsync)
rAsync -= rwAsync
wAsync -= rwAsync
rSync_wAsync = min(rSync, wAsync)
rSync -= rSync_wAsync
wAsync -= rSync_wAsync
rAsync_wSync = min(rAsync, wSync)
rAsync -= rAsync_wSync
wSync -= rAsync_wSync
# update port counts for mem
rwSyncPorts += rwSync
rSyncPorts += rSync
wSyncPorts += wSync
rwAsyncPorts += rwAsync
rAsyncPorts += rAsync
wAsyncPorts += wAsync
rSync_wAsyncPorts += rSync_wAsync
rAsync_wSyncPorts += rAsync_wSync
k = ResourceRAM(m._dtype.elmType.bit_length(),
int(m._dtype.size),
rwSyncPorts, rSyncPorts, wSyncPorts,
rSync_wAsyncPorts,
rwAsyncPorts, rAsyncPorts, wAsyncPorts,
rAsync_wSyncPorts)
res[k] = res.get(k, 0) + 1
self.memories.clear()
# remove register on read ports which will be merged into ram
if ff_to_remove:
ff_cnt = res[ResourceFF]
ff_cnt -= ff_to_remove
if ff_cnt:
res[ResourceFF] = ff_cnt
else:
del res[ResourceFF]
|
Try lookup operator with this parameters in _usedOps if not found create new one and soter it in _usedOps
|
def naryOp(self, operator, opCreateDelegate, *otherOps) -> RtlSignalBase:
"""
Try lookup operator with this parameters in _usedOps
if not found create new one and soter it in _usedOps
:param operator: instance of OpDefinition
:param opCreateDelegate: function (*ops) to create operator
:param otherOps: other operands (ops = self + otherOps)
:return: RtlSignal which is result of newly created operator
"""
k = (operator, *otherOps)
used = self._usedOps
try:
return used[k]
except KeyError:
pass
o = opCreateDelegate(self, *otherOps)
# input operads may be type converted,
# search if this happend, and return always same result signal
try:
op_instanciated = (o.origin.operator == operator
and o.origin.operands[0] is self)
except AttributeError:
op_instanciated = False
if op_instanciated:
k_real = (operator, *o.origin.operands[1:])
real_o = used.get(k_real, None)
if real_o is not None:
# destroy newly created operator and result, because it is same
# as
ctx = self.ctx
if ctx is not None:
ctx.signals.remove(o)
op = o.origin
o.origin = None
o.drivers.clear()
for inp in op.operands:
if isinstance(inp, RtlSignalBase):
inp.endpoints.remove(op)
o = real_o
else:
used[k_real] = o
used[k] = o
return o
|
__eq__ is not overloaded because it will destroy hashability of object
|
def _eq(self, other):
"""
__eq__ is not overloaded because it will destroy hashability of object
"""
return self.naryOp(AllOps.EQ, tv(self)._eq, other)
|
Find out if this signal is something indexed
|
def _getIndexCascade(self):
"""
Find out if this signal is something indexed
"""
try:
# now I am result of the index xxx[xx] <= source
# get index op
d = self.singleDriver()
try:
op = d.operator
except AttributeError:
return
if op == AllOps.INDEX:
# get signal on which is index applied
indexedOn = d.operands[0]
if isinstance(indexedOn, RtlSignalBase):
# [TODO] multidimensional indexing
return indexedOn, [d.operands[1]]
else:
raise Exception(
"can not drive static value %r" % indexedOn)
except (MultipleDriversErr, NoDriverErr):
pass
|
Construct value of this type. Delegated on value class for this type
|
def fromPy(self, v, vldMask=None):
"""
Construct value of this type.
Delegated on value class for this type
"""
return self.getValueCls().fromPy(v, self, vldMask=vldMask)
|
Cast value or signal of this type to another compatible type.
|
def auto_cast(self, sigOrVal, toType):
"""
Cast value or signal of this type to another compatible type.
:param sigOrVal: instance of signal or value to cast
:param toType: instance of HdlType to cast into
"""
if sigOrVal._dtype == toType:
return sigOrVal
try:
c = self._auto_cast_fn
except AttributeError:
c = self.get_auto_cast_fn()
self._auto_cast_fn = c
return c(self, sigOrVal, toType)
|
Cast value or signal of this type to another type of same size.
|
def reinterpret_cast(self, sigOrVal, toType):
"""
Cast value or signal of this type to another type of same size.
:param sigOrVal: instance of signal or value to cast
:param toType: instance of HdlType to cast into
"""
try:
return self.auto_cast(sigOrVal, toType)
except TypeConversionErr:
pass
try:
r = self._reinterpret_cast_fn
except AttributeError:
r = self.get_reinterpret_cast_fn()
self._reinterpret_cast_fn = r
return r(self, sigOrVal, toType)
|
walk parameter instances on this interface
|
def walkParams(intf, discovered):
"""
walk parameter instances on this interface
"""
for si in intf._interfaces:
yield from walkParams(si, discovered)
for p in intf._params:
if p not in discovered:
discovered.add(p)
yield p
|
Connect 1D vector signal to this structuralized interface
|
def connectPacked(srcPacked, dstInterface, exclude=None):
"""
Connect 1D vector signal to this structuralized interface
:param packedSrc: vector which should be connected
:param dstInterface: structuralized interface where should
packedSrc be connected to
:param exclude: sub interfaces of self which should be excluded
"""
offset = 0
connections = []
for i in reversed(list(walkPhysInterfaces(dstInterface))):
if exclude is not None and i in exclude:
continue
sig = i._sig
t = sig._dtype
if t == BIT:
s = srcPacked[offset]
offset += 1
else:
w = t.bit_length()
s = srcPacked[(w + offset): offset]
offset += w
connections.append(sig(s))
return connections
|
: param shouldEnterIntfFn: function ( actual interface ) returns tuple ( shouldEnter shouldYield )
|
def walkFlatten(interface, shouldEnterIntfFn):
"""
:param shouldEnterIntfFn: function (actual interface)
returns tuple (shouldEnter, shouldYield)
"""
_shouldEnter, _shouldYield = shouldEnterIntfFn(interface)
if _shouldYield:
yield interface
if shouldEnterIntfFn:
for intf in interface._interfaces:
yield from walkFlatten(intf, shouldEnterIntfFn)
|
Concatenate all signals to one big signal recursively
|
def packIntf(intf, masterDirEqTo=DIRECTION.OUT, exclude=None):
"""
Concatenate all signals to one big signal, recursively
:param masterDirEqTo: only signals with this direction are packed
:param exclude: sequence of signals/interfaces to exclude
"""
if not intf._interfaces:
if intf._masterDir == masterDirEqTo:
return intf._sig
return None
res = None
for i in intf._interfaces:
if exclude is not None and i in exclude:
continue
if i._interfaces:
if i._masterDir == DIRECTION.IN:
d = DIRECTION.opposite(masterDirEqTo)
else:
d = masterDirEqTo
s = i._pack(d, exclude=exclude)
else:
if i._masterDir == masterDirEqTo:
s = i._sig
else:
s = None
if s is not None:
if res is None:
res = s
else:
res = res._concat(s)
return res
|
Due to verilog restrictions it is not posible to use array constants and rom memories has to be hardcoded as process
|
def hardcodeRomIntoProcess(cls, rom):
"""
Due to verilog restrictions it is not posible to use array constants
and rom memories has to be hardcoded as process
"""
processes = []
signals = []
for e in rom.endpoints:
assert isinstance(e, Operator) and e.operator == AllOps.INDEX, e
me, index = e.operands
assert me is rom
# construct output of the rom
romValSig = rom.ctx.sig(rom.name, dtype=e.result._dtype)
signals.append(romValSig)
romValSig.hidden = False
# construct process which will represent content of the rom
cases = [(toHVal(i), [romValSig(v), ])
for i, v in enumerate(rom.defVal.val)]
statements = [SwitchContainer(index, cases), ]
for (_, (stm, )) in cases:
stm.parentStm = statements[0]
p = HWProcess(rom.name, statements, {index, },
{index, }, {romValSig, })
processes.append(p)
# override usage of original index operator on rom
# to use signal generated from this process
def replaceOrigRomIndexExpr(x):
if x is e.result:
return romValSig
else:
return x
for _e in e.result.endpoints:
_e.operands = tuple(map(replaceOrigRomIndexExpr, _e.operands))
e.result = romValSig
return processes, signals
|
: return: list of extra discovered processes
|
def Architecture_var(cls, v, serializerVars, extraTypes,
extraTypes_serialized, ctx, childCtx):
"""
:return: list of extra discovered processes
"""
t = v._dtype
# if type requires extra definition
if isinstance(t, HArray) and v.defVal.vldMask:
if v.drivers:
raise SerializerException("Verilog does not support RAMs"
" with initialized value")
eProcs, eVars = cls.hardcodeRomIntoProcess(v)
for _v in eVars:
_procs = cls.Architecture_var(_v, serializerVars, extraTypes,
extraTypes_serialized, ctx,
childCtx)
eProcs.extend(_procs)
return eProcs
v.name = ctx.scope.checkedName(v.name, v)
serializedVar = cls.SignalItem(v, childCtx, declaration=True)
serializerVars.append(serializedVar)
return []
|
synthesize all subunits make connections between them build entity and component for this unit
|
def _toRtl(self, targetPlatform: DummyPlatform):
"""
synthesize all subunits, make connections between them,
build entity and component for this unit
"""
assert not self._wasSynthetised()
self._targetPlatform = targetPlatform
if not hasattr(self, "_name"):
self._name = self._getDefaultName()
for proc in targetPlatform.beforeToRtl:
proc(self)
self._ctx.params = self._buildParams()
self._externInterf = []
# prepare subunits
for u in self._units:
yield from u._toRtl(targetPlatform)
for u in self._units:
subUnitName = u._name
u._signalsForMyEntity(self._ctx, "sig_" + subUnitName)
# prepare signals for interfaces
for i in self._interfaces:
signals = i._signalsForInterface(self._ctx)
if i._isExtern:
self._externInterf.extend(signals)
for proc in targetPlatform.beforeToRtlImpl:
proc(self)
self._loadMyImplementations()
yield from self._lazyLoaded
if not self._externInterf:
raise IntfLvlConfErr(
"Can not find any external interface for unit %s"
"- unit without interfaces are not allowed"
% self._name)
for proc in targetPlatform.afterToRtlImpl:
proc(self)
yield from self._synthetiseContext(self._externInterf)
self._checkArchCompInstances()
for proc in targetPlatform.afterToRtl:
proc(self)
|
Load all declarations from _decl () method recursively for all interfaces/ units.
|
def _loadDeclarations(self):
"""
Load all declarations from _decl() method, recursively
for all interfaces/units.
"""
if not hasattr(self, "_interfaces"):
self._interfaces = []
if not hasattr(self, "_private_interfaces"):
self._private_interfaces = []
if not hasattr(self, "_units"):
self._units = []
self._setAttrListener = self._declrCollector
self._declr()
self._setAttrListener = None
for i in self._interfaces:
self._loadInterface(i, True)
# if I am a unit load subunits
for u in self._units:
u._loadDeclarations()
for p in self._params:
p.setReadOnly()
|
Register interface in implementation phase
|
def _registerIntfInImpl(self, iName, intf):
"""
Register interface in implementation phase
"""
self._registerInterface(iName, intf, isPrivate=True)
self._loadInterface(intf, False)
intf._signalsForInterface(self._ctx)
|
Reverse byteorder ( littleendian/ bigendian ) of signal or value
|
def reverseByteOrder(signalOrVal):
"""
Reverse byteorder (littleendian/bigendian) of signal or value
"""
w = signalOrVal._dtype.bit_length()
i = w
items = []
while i > 0:
# take last 8 bytes or rest
lower = max(i - 8, 0)
items.append(signalOrVal[i:lower])
i -= 8
return Concat(*items)
|
Return sig and val reduced by & operator or None if it is not possible to statically reduce expression
|
def tryReduceAnd(sig, val):
"""
Return sig and val reduced by & operator or None
if it is not possible to statically reduce expression
"""
m = sig._dtype.all_mask()
if val._isFullVld():
v = val.val
if v == m:
return sig
elif v == 0:
return val
|
Return sig and val reduced by ^ operator or None if it is not possible to statically reduce expression
|
def tryReduceXor(sig, val):
"""
Return sig and val reduced by ^ operator or None
if it is not possible to statically reduce expression
"""
m = sig._dtype.all_mask()
if not val.vldMask:
return val
if val._isFullVld():
v = val.val
if v == m:
return ~sig
elif v == 0:
return sig
|
Get root of name space
|
def getBaseNameScope(cls):
"""
Get root of name space
"""
s = NameScope(False)
s.setLevel(1)
s[0].update(cls._keywords_dict)
return s
|
Convert object to HDL string
|
def asHdl(cls, obj, ctx: SerializerCtx):
"""
Convert object to HDL string
:param obj: object to serialize
:param ctx: SerializerCtx instance
"""
if isinstance(obj, RtlSignalBase):
return cls.SignalItem(obj, ctx)
elif isinstance(obj, Value):
return cls.Value(obj, ctx)
else:
try:
serFn = getattr(cls, obj.__class__.__name__)
except AttributeError:
raise SerializerException("Not implemented for", obj)
return serFn(obj, ctx)
|
Entity is just forward declaration of Architecture it is not used in most HDL languages as there is no recursion in hierarchy
|
def Entity(cls, ent: Entity, ctx: SerializerCtx):
"""
Entity is just forward declaration of Architecture, it is not used
in most HDL languages as there is no recursion in hierarchy
"""
ent.name = ctx.scope.checkedName(ent.name, ent, isGlobal=True)
return ""
|
Decide if this unit should be serialized or not eventually fix name to fit same already serialized unit
|
def serializationDecision(cls, obj, serializedClasses,
serializedConfiguredUnits):
"""
Decide if this unit should be serialized or not eventually fix name
to fit same already serialized unit
:param obj: object to serialize
:param serializedClasses: dict {unitCls : unitobj}
:param serializedConfiguredUnits: (unitCls, paramsValues) : unitObj
where paramsValues are named tuple name:value
"""
isDeclaration = isinstance(obj, Entity)
isDefinition = isinstance(obj, Architecture)
if isDeclaration:
unit = obj.origin
elif isDefinition:
unit = obj.entity.origin
else:
return True
assert isinstance(unit, Unit)
sd = unit._serializeDecision
if sd is None:
return True
else:
prevPriv = serializedClasses.get(unit.__class__, None)
seriazlize, nextPriv = sd(unit, obj, isDeclaration, prevPriv)
serializedClasses[unit.__class__] = nextPriv
return seriazlize
|
Serialize HdlType instance
|
def HdlType(cls, typ: HdlType, ctx: SerializerCtx, declaration=False):
"""
Serialize HdlType instance
"""
if isinstance(typ, Bits):
sFn = cls.HdlType_bits
elif isinstance(typ, HEnum):
sFn = cls.HdlType_enum
elif isinstance(typ, HArray):
sFn = cls.HdlType_array
elif isinstance(typ, Integer):
sFn = cls.HdlType_int
elif isinstance(typ, HBool):
sFn = cls.HdlType_bool
else:
raise NotImplementedError("type declaration is not implemented"
" for type %s"
% (typ.name))
return sFn(typ, ctx, declaration=declaration)
|
Srialize IfContainer instance
|
def IfContainer(cls, ifc: IfContainer, ctx: SerializerCtx):
"""
Srialize IfContainer instance
"""
childCtx = ctx.withIndent()
def asHdl(statements):
return [cls.asHdl(s, childCtx) for s in statements]
try:
cond = cls.condAsHdl(ifc.cond, True, ctx)
except UnsupportedEventOpErr as e:
cond = None
if cond is None:
assert not ifc.elIfs
assert not ifc.ifFalse
stmBuff = [cls.asHdl(s, ctx) for s in ifc.ifTrue]
return "\n".join(stmBuff)
elIfs = []
ifTrue = ifc.ifTrue
ifFalse = ifc.ifFalse
if ifFalse is None:
ifFalse = []
for c, statements in ifc.elIfs:
try:
elIfs.append((cls.condAsHdl(c, True, ctx), asHdl(statements)))
except UnsupportedEventOpErr as e:
if len(ifc.elIfs) == 1 and not ifFalse:
# register expression is in valid format and this
# is just register with asynchronous reset or etc...
ifFalse = statements
else:
raise e
return cls.ifTmpl.render(
indent=getIndent(ctx.indent),
cond=cond,
ifTrue=asHdl(ifTrue),
elIfs=elIfs,
ifFalse=asHdl(ifFalse))
|
: return: simulation driver which keeps signal value high for initDelay then it sets value to 0
|
def pullDownAfter(sig, initDelay=6 * Time.ns):
"""
:return: simulation driver which keeps signal value high for initDelay
then it sets value to 0
"""
def _pullDownAfter(s):
s.write(True, sig)
yield s.wait(initDelay)
s.write(False, sig)
return _pullDownAfter
|
if is negated return original cond and negated flag
|
def getBaseCond(c):
"""
if is negated return original cond and negated flag
"""
isNegated = False
try:
drivers = c.drivers
except AttributeError:
return (c, isNegated)
if len(drivers) == 1:
d = list(c.drivers)[0]
if isinstance(d, Operator) and d.operator == AllOps.NOT:
c = d.operands[0]
isNegated = True
return (c, isNegated)
|
Construct SimBitsT with cache
|
def simBitsT(width: int, signed: Union[bool, None]):
"""
Construct SimBitsT with cache
"""
k = (width, signed)
try:
return __simBitsTCache[k]
except KeyError:
t = SimBitsT(width, signed)
__simBitsTCache[k] = t
return t
|
: param val: None or dict { field name: field value }: param typeObj: instance of String HdlType: param vldMask: if is None validity is resolved from val if is 0 value is invalidated if is 1 value has to be valid
|
def fromPy(cls, val, typeObj, vldMask=None):
"""
:param val: None or dict {field name: field value}
:param typeObj: instance of String HdlType
:param vldMask: if is None validity is resolved from val
if is 0 value is invalidated
if is 1 value has to be valid
"""
if vldMask == 0:
val = None
return cls(val, typeObj)
|
Create basic: class:. Signal interface where type is vector
|
def VectSignal(width,
signed=None,
masterDir=D.OUT,
loadConfig=True):
"""
Create basic :class:`.Signal` interface where type is vector
"""
return Signal(masterDir,
Bits(width, signed, forceVector=True),
loadConfig)
|
Get constant name for value name of constant is reused if same value was used before
|
def getConstName(self, val):
"""
Get constant name for value
name of constant is reused if same value was used before
"""
try:
return self._cache[val]
except KeyError:
if isinstance(val.val, int):
name = "const_%d_" % val.val
else:
name = "const_"
c = self.nameCheckFn(name, val)
self._cache[val] = c
return c
|
Cut off statements which are driver of specified signal
|
def _cut_off_drivers_of(self, sig: RtlSignalBase):
"""
Cut off statements which are driver of specified signal
"""
if self.dst is sig:
self.parentStm = None
return self
else:
return None
|
Parse HArray type to this transaction template instance
|
def _loadFromArray(self, dtype: HdlType, bitAddr: int) -> int:
"""
Parse HArray type to this transaction template instance
:return: address of it's end
"""
self.itemCnt = evalParam(dtype.size).val
self.children = TransTmpl(
dtype.elmType, 0, parent=self, origin=self.origin)
return bitAddr + self.itemCnt * self.children.bitAddrEnd
|
Parse HStruct type to this transaction template instance
|
def _loadFromHStruct(self, dtype: HdlType, bitAddr: int):
"""
Parse HStruct type to this transaction template instance
:return: address of it's end
"""
for f in dtype.fields:
t = f.dtype
origin = f
isPadding = f.name is None
if isPadding:
width = t.bit_length()
bitAddr += width
else:
fi = TransTmpl(t, bitAddr, parent=self, origin=origin)
self.children.append(fi)
bitAddr = fi.bitAddrEnd
return bitAddr
|
Parse HUnion type to this transaction template instance
|
def _loadFromUnion(self, dtype: HdlType, bitAddr: int) -> int:
"""
Parse HUnion type to this transaction template instance
:return: address of it's end
"""
for field in dtype.fields.values():
ch = TransTmpl(field.dtype, 0, parent=self, origin=field)
self.children.append(ch)
return bitAddr + dtype.bit_length()
|
Parse HUnion type to this transaction template instance
|
def _loadFromHStream(self, dtype: HStream, bitAddr: int) -> int:
"""
Parse HUnion type to this transaction template instance
:return: address of it's end
"""
ch = TransTmpl(dtype.elmType, 0, parent=self, origin=self.origin)
self.children.append(ch)
return bitAddr + dtype.elmType.bit_length()
|
Parse any HDL type to this transaction template instance
|
def _loadFromHType(self, dtype: HdlType, bitAddr: int) -> None:
"""
Parse any HDL type to this transaction template instance
"""
self.bitAddr = bitAddr
childrenAreChoice = False
if isinstance(dtype, Bits):
ld = self._loadFromBits
elif isinstance(dtype, HStruct):
ld = self._loadFromHStruct
elif isinstance(dtype, HArray):
ld = self._loadFromArray
elif isinstance(dtype, HStream):
ld = self._loadFromHStream
elif isinstance(dtype, HUnion):
ld = self._loadFromUnion
childrenAreChoice = True
else:
raise TypeError("expected instance of HdlType", dtype)
self.bitAddrEnd = ld(dtype, bitAddr)
self.childrenAreChoice = childrenAreChoice
|
Only for transactions derived from HArray
|
def getItemWidth(self) -> int:
"""
Only for transactions derived from HArray
:return: width of item in original array
"""
if not isinstance(self.dtype, HArray):
raise TypeError()
return (self.bitAddrEnd - self.bitAddr) // self.itemCnt
|
Walk fields in instance of TransTmpl
|
def walkFlatten(self, offset: int=0,
shouldEnterFn=_default_shouldEnterFn,
otherObjItCtx: ObjIteratorCtx =_DummyIteratorCtx()
) -> Generator[
Union[Tuple[Tuple[int, int], 'TransTmpl'], 'OneOfTransaction'],
None, None]:
"""
Walk fields in instance of TransTmpl
:param offset: optional offset for all children in this TransTmpl
:param shouldEnterFn: function (transTmpl) which returns True
when field should be split on it's children
:param shouldEnterFn: function(transTmpl) which should return
(shouldEnter, shouldUse) where shouldEnter is flag that means
iterator should look inside of this actual object
and shouldUse flag means that this field should be used
(=generator should yield it)
:return: generator of tuples ((startBitAddress, endBitAddress),
TransTmpl instance)
"""
t = self.dtype
base = self.bitAddr + offset
end = self.bitAddrEnd + offset
shouldEnter, shouldYield = shouldEnterFn(self)
if shouldYield:
yield ((base, end), self)
if shouldEnter:
if isinstance(t, Bits):
pass
elif isinstance(t, HStruct):
for ch in self.children:
with otherObjItCtx(ch.origin.name):
yield from ch.walkFlatten(
offset,
shouldEnterFn,
otherObjItCtx)
elif isinstance(t, HArray):
itemSize = (self.bitAddrEnd - self.bitAddr) // self.itemCnt
for i in range(self.itemCnt):
with otherObjItCtx(i):
yield from self.children.walkFlatten(
base + i * itemSize,
shouldEnterFn,
otherObjItCtx)
elif isinstance(t, HUnion):
yield OneOfTransaction(self, offset, shouldEnterFn,
self.children)
elif isinstance(t, HStream):
assert len(self.children) == 1
yield StreamTransaction(self, offset, shouldEnterFn,
self.children[0])
else:
raise TypeError(t)
|
: return: generator of generators of tuples (( startBitAddress endBitAddress ) TransTmpl instance ) for each possiblility in this transaction
|
def walkFlattenChilds(self) -> Generator[
Union[Tuple[Tuple[int, int], TransTmpl], 'OneOfTransaction'],
None, None]:
"""
:return: generator of generators of tuples
((startBitAddress, endBitAddress), TransTmpl instance)
for each possiblility in this transaction
"""
for p in self.possibleTransactions:
yield p.walkFlatten(offset=self.offset,
shouldEnterFn=self.shouldEnterFn)
|
Convert negative int to positive int which has same bits set
|
def signFix(val, width):
"""
Convert negative int to positive int which has same bits set
"""
if val > 0:
msb = 1 << (width - 1)
if val & msb:
val -= mask(width) + 1
return val
|
: attention: If other is Bool signal convert this to bool ( not ideal due VHDL event operator )
|
def bitsCmp(self, other, op, evalFn=None):
"""
:attention: If other is Bool signal convert this to bool (not ideal,
due VHDL event operator)
"""
other = toHVal(other)
t = self._dtype
ot = other._dtype
iamVal = isinstance(self, Value)
otherIsVal = isinstance(other, Value)
if evalFn is None:
evalFn = op._evalFn
if iamVal and otherIsVal:
if ot == BOOL:
self = self._auto_cast(BOOL)
elif t == ot:
pass
elif isinstance(ot, Integer):
other = other._auto_cast(t)
else:
raise TypeError("Values of types (%r, %r) are not comparable" % (
self._dtype, other._dtype))
return bitsCmp__val(self, other, op, evalFn)
else:
if ot == BOOL:
self = self._auto_cast(BOOL)
elif t == ot:
pass
elif isinstance(ot, Integer):
other = other._auto_cast(self._dtype)
else:
raise TypeError("Values of types (%r, %r) are not comparable" % (
self._dtype, other._dtype))
# try to reduce useless cmp
res = None
if otherIsVal and other._isFullVld():
res = bitsCmp_detect_useless_cmp(self, other, op)
elif iamVal and self._isFullVld():
res = bitsCmp_detect_useless_cmp(other, self, CMP_OP_REVERSE[op])
if res is None:
pass
elif isinstance(res, Value):
return res
else:
assert res == AllOps.EQ, res
op = res
return Operator.withRes(op, [self, other], BOOL)
|
: attention: If other is Bool signal convert this to bool ( not ideal due VHDL event operator )
|
def bitsBitOp(self, other, op, getVldFn, reduceCheckFn):
"""
:attention: If other is Bool signal, convert this to bool
(not ideal, due VHDL event operator)
"""
other = toHVal(other)
iamVal = isinstance(self, Value)
otherIsVal = isinstance(other, Value)
if iamVal and otherIsVal:
other = other._auto_cast(self._dtype)
return bitsBitOp__val(self, other, op, getVldFn)
else:
if other._dtype == BOOL:
self = self._auto_cast(BOOL)
return op._evalFn(self, other)
elif self._dtype == other._dtype:
pass
else:
raise TypeError("Can not apply operator %r (%r, %r)" %
(op, self._dtype, other._dtype))
if otherIsVal:
r = reduceCheckFn(self, other)
if r is not None:
return r
elif iamVal:
r = reduceCheckFn(other, self)
if r is not None:
return r
return Operator.withRes(op, [self, other], self._dtype)
|
: param val: value of python type bool or None: param typeObj: instance of HEnum: param vldMask: if is None validity is resolved from val if is 0 value is invalidated if is 1 value has to be valid
|
def fromPy(cls, val, typeObj, vldMask=None):
"""
:param val: value of python type bool or None
:param typeObj: instance of HEnum
:param vldMask: if is None validity is resolved from val
if is 0 value is invalidated
if is 1 value has to be valid
"""
if val is None:
assert vldMask is None or vldMask == 0
valid = False
val = typeObj._allValues[0]
else:
if vldMask is None or vldMask == 1:
assert isinstance(val, str)
valid = True
else:
valid = False
val = None
return cls(val, typeObj, valid)
|
Doc on parent class: meth: HdlStatement. _discover_sensitivity
|
def _discover_sensitivity(self, seen) -> None:
"""
Doc on parent class :meth:`HdlStatement._discover_sensitivity`
"""
assert self._sensitivity is None, self
ctx = self._sensitivity = SensitivityCtx()
casual_sensitivity = set()
self.switchOn._walk_sensitivity(casual_sensitivity, seen, ctx)
if ctx.contains_ev_dependency:
raise HwtSyntaxError(
"Can not switch on event operator result", self.switchOn)
ctx.extend(casual_sensitivity)
for stm in self._iter_stms():
stm._discover_sensitivity(seen)
ctx.extend(stm._sensitivity)
|
: attention: enclosure has to be discoverd first use _discover_enclosure () method
|
def _fill_enclosure(self, enclosure: Dict[RtlSignalBase, HdlStatement]) -> None:
"""
:attention: enclosure has to be discoverd first use _discover_enclosure() method
"""
select = []
outputs = self._outputs
for e in enclosure.keys():
if e in outputs:
select.append(e)
for (_, stms), e in zip(self.cases, self._case_enclosed_for):
fill_stm_list_with_enclosure(self, e, stms, select, enclosure)
e.update(select)
t = self.switchOn._dtype
default_required = len(self.cases) < t.domain_size()
if self.default is not None or default_required:
self.default = fill_stm_list_with_enclosure(
self, self._default_enclosed_for, self.default, select, enclosure)
self._default_enclosed_for.update(select)
self._enclosed_for.update(select)
|
Doc on parent class: meth: HdlStatement. _iter_stms
|
def _iter_stms(self):
"""
Doc on parent class :meth:`HdlStatement._iter_stms`
"""
for _, stms in self.cases:
yield from stms
if self.default is not None:
yield from self.default
|
: return: True if other can be merged into this statement else False
|
def _is_mergable(self, other) -> bool:
"""
:return: True if other can be merged into this statement else False
"""
if not isinstance(other, SwitchContainer):
return False
if not (self.switchOn is other.switchOn and
len(self.cases) == len(other.cases) and
self._is_mergable_statement_list(self.default, other.default)):
return False
for (vA, caseA), (vB, caseB) in zip(self.cases, other.cases):
if vA != vB or not self._is_mergable_statement_list(caseA, caseB):
return False
return True
|
Merge other statement to this statement
|
def _merge_with_other_stm(self, other: "IfContainer") -> None:
"""
Merge other statement to this statement
"""
merge = self._merge_statement_lists
newCases = []
for (c, caseA), (_, caseB) in zip(self.cases, other.cases):
newCases.append((c, merge(caseA, caseB)))
self.cases = newCases
if self.default is not None:
self.default = merge(self.default, other.default)
self._on_merge(other)
|
Doc on parent class: meth: HdlStatement. _try_reduce
|
def _try_reduce(self) -> Tuple[List["HdlStatement"], bool]:
"""
Doc on parent class :meth:`HdlStatement._try_reduce`
"""
io_change = False
new_cases = []
for val, statements in self.cases:
_statements, rank_decrease, _io_change = self._try_reduce_list(
statements)
io_change |= _io_change
self.rank -= rank_decrease
new_cases.append((val, _statements))
self.cases = new_cases
if self.default is not None:
self.default, rank_decrease, _io_change = self._try_reduce_list(
self.default)
self.rank -= rank_decrease
io_change |= _io_change
reduce_self = not self._condHasEffect()
if reduce_self:
if self.cases:
res = self.cases[0][1]
elif self.default is not None:
res = self.default
else:
res = []
else:
res = [self, ]
self._on_reduce(reduce_self, io_change, res)
if not self.default:
t = self.switchOn._dtype
if isinstance(t, HEnum):
dom_size = t.domain_size()
val_cnt = len(t._allValues)
if len(self.cases) == val_cnt and val_cnt < dom_size:
# bit representation is not fully matching enum description
# need to set last case as default to prevent latches
_, stms = self.cases.pop()
self.default = stms
return res, io_change
|
: return: True if statements in branches has different effect
|
def _condHasEffect(self) -> bool:
"""
:return: True if statements in branches has different effect
"""
if not self.cases:
return False
# [TODO]
type_domain_covered = bool(self.default) or len(
self.cases) == self.switchOn._dtype.domain_size()
stmCnt = len(self.cases[0])
if type_domain_covered and reduce(
and_,
[len(stm) == stmCnt
for _, stm in self.cases],
True) and (self.default is None
or len(self.default) == stmCnt):
stms = list(self._iter_stms())
if statementsAreSame(stms):
return False
else:
return True
return True
|
Doc on parent class: meth: HdlStatement. isSame
|
def isSame(self, other: HdlStatement) -> bool:
"""
Doc on parent class :meth:`HdlStatement.isSame`
"""
if self is other:
return True
if self.rank != other.rank:
return False
if isinstance(other, SwitchContainer) \
and isSameHVal(self.switchOn, other.switchOn)\
and len(self.cases) == len(other.cases)\
and isSameStatementList(self.default, other.default):
for (ac, astm), (bc, bstm) in zip(self.cases, other.cases):
if not isSameHVal(ac, bc)\
or not isSameStatementList(astm, bstm):
return False
return True
return False
|
: return: generator of tuples ( event operator signal )
|
def discoverEventDependency(sig):
"""
:return: generator of tuples (event operator, signal)
"""
try:
drivers = sig.drivers
except AttributeError:
return
if len(drivers) == 1:
d = drivers[0]
if isinstance(d, Operator):
if isEventDependentOp(d.operator):
yield (d.operator, d.operands[0])
else:
for op in d.operands:
yield from discoverEventDependency(op)
|
Cached indent getter function
|
def getIndent(indentNum):
"""
Cached indent getter function
"""
try:
return _indentCache[indentNum]
except KeyError:
i = "".join([_indent for _ in range(indentNum)])
_indentCache[indentNum] = i
return i
|
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