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/**
******************************************************************************
* @file stm32u5xx_hal_tsc.h
* @author MCD Application Team
* @brief Header file of TSC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_TSC_H
#define STM32U5xx_HAL_TSC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup TSC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TSC_Exported_Types TSC Exported Types
* @{
*/
/**
* @brief TSC state structure definition
*/
typedef enum
{
HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */
HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */
HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */
HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */
} HAL_TSC_StateTypeDef;
/**
* @brief TSC group status structure definition
*/
typedef enum
{
TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */
TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */
} TSC_GroupStatusTypeDef;
/**
* @brief TSC init structure definition
*/
typedef struct
{
uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length
This parameter can be a value of @ref TSC_CTPulseHL_Config */
uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length
This parameter can be a value of @ref TSC_CTPulseLL_Config */
FunctionalState SpreadSpectrum; /*!< Spread spectrum activation
This parameter can be set to ENABLE or DISABLE. */
uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
uint32_t MaxCountValue; /*!< Max count value
This parameter can be a value of @ref TSC_MaxCount_Value */
uint32_t IODefaultMode; /*!< IO default mode
This parameter can be a value of @ref TSC_IO_Default_Mode */
uint32_t SynchroPinPolarity; /*!< Synchro pin polarity
This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
uint32_t AcquisitionMode; /*!< Acquisition mode
This parameter can be a value of @ref TSC_Acquisition_Mode */
FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation
This parameter can be set to ENABLE or DISABLE. */
uint32_t ChannelIOs; /*!< Channel IOs mask */
uint32_t ShieldIOs; /*!< Shield IOs mask */
uint32_t SamplingIOs; /*!< Sampling IOs mask */
} TSC_InitTypeDef;
/**
* @brief TSC IOs configuration structure definition
*/
typedef struct
{
uint32_t ChannelIOs; /*!< Channel IOs mask */
uint32_t ShieldIOs; /*!< Shield IOs mask */
uint32_t SamplingIOs; /*!< Sampling IOs mask */
} TSC_IOConfigTypeDef;
/**
* @brief TSC handle Structure definition
*/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
typedef struct __TSC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
{
TSC_TypeDef *Instance; /*!< Register base address */
TSC_InitTypeDef Init; /*!< Initialization parameters */
__IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
HAL_LockTypeDef Lock; /*!< Lock feature */
__IO uint32_t ErrorCode; /*!< TSC Error code */
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */
void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */
void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */
void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
} TSC_HandleTypeDef;
enum
{
TSC_GROUP1_IDX = 0x00UL,
TSC_GROUP2_IDX,
TSC_GROUP3_IDX,
TSC_GROUP4_IDX,
TSC_GROUP5_IDX,
TSC_GROUP6_IDX,
TSC_GROUP7_IDX,
TSC_GROUP8_IDX,
TSC_NB_OF_GROUPS
};
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL TSC Callback ID enumeration definition
*/
typedef enum
{
HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */
HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */
HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */
HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */
} HAL_TSC_CallbackIDTypeDef;
/**
* @brief HAL TSC Callback pointer definition
*/
typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TSC_Exported_Constants TSC Exported Constants
* @{
*/
/** @defgroup TSC_Error_Code_definition TSC Error Code definition
* @brief TSC Error Code definition
* @{
*/
#define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
#define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
* @{
*/
#define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */
#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */
#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */
#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */
#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */
#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */
#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */
#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */
#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */
#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */
#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */
#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */
#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */
#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */
#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */
#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */
/**
* @}
*/
/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
* @{
*/
#define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */
#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */
#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */
#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */
#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */
#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */
#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */
#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */
#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */
#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */
#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */
#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */
#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */
#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */
#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */
#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */
/**
* @}
*/
/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
* @{
*/
#define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */
#define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */
/**
* @}
*/
/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
* @{
*/
#define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */
#define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */
#define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */
#define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */
#define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */
#define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */
#define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */
#define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */
/**
* @}
*/
/** @defgroup TSC_MaxCount_Value Max Count Value
* @{
*/
#define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */
#define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */
#define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */
#define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */
#define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */
#define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */
#define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */
/**
* @}
*/
/** @defgroup TSC_IO_Default_Mode IO Default Mode
* @{
*/
#define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */
#define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */
/**
* @}
*/
/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
* @{
*/
#define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */
#define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */
/**
* @}
*/
/** @defgroup TSC_Acquisition_Mode Acquisition Mode
* @{
*/
#define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */
/**
* @}
*/
/** @defgroup TSC_interrupts_definition Interrupts definition
* @{
*/
#define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */
#define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */
/**
* @}
*/
/** @defgroup TSC_flags_definition Flags definition
* @{
*/
#define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */
#define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */
/**
* @}
*/
/** @defgroup TSC_Group_definition Group definition
* @{
*/
#define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX)
#define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX)
#define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX)
#define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX)
#define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX)
#define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX)
#define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX)
#define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX)
#define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */
#define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */
#define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */
#define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */
#define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */
#define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */
#define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */
#define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */
#define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */
#define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */
#define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */
#define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */
#define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */
#define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */
#define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */
#define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */
#define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */
#define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */
#define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */
#define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */
#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */
#define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */
#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */
#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */
#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */
#define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */
#define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */
#define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */
#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */
#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */
#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */
#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup TSC_Exported_Macros TSC Exported Macros
* @{
*/
/** @brief Reset TSC handle state.
* @param __HANDLE__ TSC handle
* @retval None
*/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_TSC_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
#endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */
/**
* @brief Enable the TSC peripheral.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
/**
* @brief Disable the TSC peripheral.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))
/**
* @brief Start acquisition.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
/**
* @brief Stop acquisition.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))
/**
* @brief Set IO default mode to output push-pull low.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))
/**
* @brief Set IO default mode to input floating.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
/**
* @brief Set synchronization polarity to falling edge.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))
/**
* @brief Set synchronization polarity to rising edge and high level.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
/**
* @brief Enable TSC interrupt.
* @param __HANDLE__ TSC handle
* @param __INTERRUPT__ TSC interrupt
* @retval None
*/
#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disable TSC interrupt.
* @param __HANDLE__ TSC handle
* @param __INTERRUPT__ TSC interrupt
* @retval None
*/
#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Check whether the specified TSC interrupt source is enabled or not.
* @param __HANDLE__ TSC Handle
* @param __INTERRUPT__ TSC interrupt
* @retval SET or RESET
*/
#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\
RESET)
/**
* @brief Check whether the specified TSC flag is set or not.
* @param __HANDLE__ TSC handle
* @param __FLAG__ TSC flag
* @retval SET or RESET
*/
#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\
& (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/**
* @brief Clear the TSC's pending flag.
* @param __HANDLE__ TSC handle
* @param __FLAG__ TSC flag
* @retval None
*/
#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enable schmitt trigger hysteresis on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
/**
* @brief Disable schmitt trigger hysteresis on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\
&= (~(__GX_IOY_MASK__)))
/**
* @brief Open analog switch on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\
&= (~(__GX_IOY_MASK__)))
/**
* @brief Close analog switch on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
/**
* @brief Enable a group of IOs in channel mode.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
/**
* @brief Disable a group of channel IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\
&= (~(__GX_IOY_MASK__)))
/**
* @brief Enable a group of IOs in sampling mode.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
/**
* @brief Disable a group of sampling IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))
/**
* @brief Enable acquisition groups.
* @param __HANDLE__ TSC handle
* @param __GX_MASK__ Groups mask
* @retval None
*/
#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
/**
* @brief Disable acquisition groups.
* @param __HANDLE__ TSC handle
* @param __GX_MASK__ Groups mask
* @retval None
*/
#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))
/** @brief Gets acquisition group status.
* @param __HANDLE__ TSC Handle
* @param __GX_INDEX__ Group index
* @retval SET or RESET
*/
#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \
(uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup TSC_Private_Macros TSC Private Macros
* @{
*/
#define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \
((__VALUE__) == TSC_CTPH_2CYCLES) || \
((__VALUE__) == TSC_CTPH_3CYCLES) || \
((__VALUE__) == TSC_CTPH_4CYCLES) || \
((__VALUE__) == TSC_CTPH_5CYCLES) || \
((__VALUE__) == TSC_CTPH_6CYCLES) || \
((__VALUE__) == TSC_CTPH_7CYCLES) || \
((__VALUE__) == TSC_CTPH_8CYCLES) || \
((__VALUE__) == TSC_CTPH_9CYCLES) || \
((__VALUE__) == TSC_CTPH_10CYCLES) || \
((__VALUE__) == TSC_CTPH_11CYCLES) || \
((__VALUE__) == TSC_CTPH_12CYCLES) || \
((__VALUE__) == TSC_CTPH_13CYCLES) || \
((__VALUE__) == TSC_CTPH_14CYCLES) || \
((__VALUE__) == TSC_CTPH_15CYCLES) || \
((__VALUE__) == TSC_CTPH_16CYCLES))
#define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \
((__VALUE__) == TSC_CTPL_2CYCLES) || \
((__VALUE__) == TSC_CTPL_3CYCLES) || \
((__VALUE__) == TSC_CTPL_4CYCLES) || \
((__VALUE__) == TSC_CTPL_5CYCLES) || \
((__VALUE__) == TSC_CTPL_6CYCLES) || \
((__VALUE__) == TSC_CTPL_7CYCLES) || \
((__VALUE__) == TSC_CTPL_8CYCLES) || \
((__VALUE__) == TSC_CTPL_9CYCLES) || \
((__VALUE__) == TSC_CTPL_10CYCLES) || \
((__VALUE__) == TSC_CTPL_11CYCLES) || \
((__VALUE__) == TSC_CTPL_12CYCLES) || \
((__VALUE__) == TSC_CTPL_13CYCLES) || \
((__VALUE__) == TSC_CTPL_14CYCLES) || \
((__VALUE__) == TSC_CTPL_15CYCLES) || \
((__VALUE__) == TSC_CTPL_16CYCLES))
#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
|| ((FunctionalState)(__VALUE__) == ENABLE))
#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
#define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
#define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \
((__VALUE__) == TSC_PG_PRESC_DIV2) || \
((__VALUE__) == TSC_PG_PRESC_DIV4) || \
((__VALUE__) == TSC_PG_PRESC_DIV8) || \
((__VALUE__) == TSC_PG_PRESC_DIV16) || \
((__VALUE__) == TSC_PG_PRESC_DIV32) || \
((__VALUE__) == TSC_PG_PRESC_DIV64) || \
((__VALUE__) == TSC_PG_PRESC_DIV128))
#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \
((__CTPL__) > TSC_CTPL_2CYCLES)) || \
(((__PGPSC__) == TSC_PG_PRESC_DIV2) && \
((__CTPL__) > TSC_CTPL_1CYCLE)) || \
(((__PGPSC__) > TSC_PG_PRESC_DIV2) && \
(((__CTPL__) == TSC_CTPL_1CYCLE) || \
((__CTPL__) > TSC_CTPL_1CYCLE))))
#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
((__VALUE__) == TSC_MCV_511) || \
((__VALUE__) == TSC_MCV_1023) || \
((__VALUE__) == TSC_MCV_2047) || \
((__VALUE__) == TSC_MCV_4095) || \
((__VALUE__) == TSC_MCV_8191) || \
((__VALUE__) == TSC_MCV_16383))
#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\
|| ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
#define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
|| ((FunctionalState)(__VALUE__) == ENABLE))
#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\
|| (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\
(((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\
(((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\
(((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\
(((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\
(((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\
(((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\
(((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\
(((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\
(((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\
(((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\
(((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\
(((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\
(((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\
(((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\
(((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\
(((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\
(((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\
(((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\
(((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\
(((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\
(((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\
(((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\
(((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\
(((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\
(((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\
(((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\
(((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\
(((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\
(((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\
(((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\
(((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\
(((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TSC_Exported_Functions
* @{
*/
/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc);
void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
pTSC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc);
TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index);
uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index);
/**
* @}
*/
/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config);
HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice);
/**
* @}
*/
/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc);
/**
* @}
*/
/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* TSC IRQHandler and Callbacks used in Interrupt mode */
void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc);
void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc);
void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_TSC_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tsc.h
|
C
|
apache-2.0
| 37,993
|
/**
******************************************************************************
* @file stm32u5xx_hal_uart.h
* @author MCD Application Team
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_UART_H
#define STM32U5xx_HAL_UART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup UART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UART_Exported_Types UART Exported Types
* @{
*/
/**
* @brief UART Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
The baud rate register is computed using the following formula:
LPUART:
=======
Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
UART:
=====
- If oversampling is 16 or in LIN mode,
Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
- If oversampling is 8,
Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
((huart->Init.BaudRate)))[3:0]) >> 1
where uart_ker_ck_pres is the UART input clock divided by a prescaler */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref UARTEx_Word_Length. */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref UART_Stop_Bits. */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref UART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref UART_Mode. */
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control. */
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
to achieve higher speed (up to f_PCLK/8).
This parameter can be a value of @ref UART_Over_Sampling. */
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
Selecting the single sample method increases the receiver tolerance to clock
deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source.
This parameter can be a value of @ref UART_ClockPrescaler. */
} UART_InitTypeDef;
/**
* @brief UART Advanced Features initialization structure definition
*/
typedef struct
{
uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
Advanced Features may be initialized at the same time .
This parameter can be a value of
@ref UART_Advanced_Features_Initialization_Type. */
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
This parameter can be a value of @ref UART_Tx_Inv. */
uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
This parameter can be a value of @ref UART_Rx_Inv. */
uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
vs negative/inverted logic).
This parameter can be a value of @ref UART_Data_Inv. */
uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
This parameter can be a value of @ref UART_Rx_Tx_Swap. */
uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
This parameter can be a value of @ref UART_Overrun_Disable. */
uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
detection is carried out.
This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
This parameter can be a value of @ref UART_MSB_First. */
} UART_AdvFeatureInitTypeDef;
/**
* @brief HAL UART State definition
* @note HAL UART State value is a combination of 2 different substates:
* gState and RxState (see @ref UART_State_Definition).
* - gState contains UART state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef uint32_t HAL_UART_StateTypeDef;
/**
* @brief HAL UART Reception type definition
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
* It is expected to admit following values :
* HAL_UART_RECEPTION_STANDARD = 0x00U,
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
* HAL_UART_RECEPTION_TORTO = 0x02U,
* HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,
*/
typedef uint32_t HAL_UART_RxTypeTypeDef;
/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
{
USART_TypeDef *Instance; /*!< UART registers base address */
UART_InitTypeDef Init; /*!< UART communication parameters */
UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
uint16_t TxXferSize; /*!< UART Tx Transfer size */
__IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
uint16_t RxXferSize; /*!< UART Rx Transfer size */
__IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
uint16_t Mask; /*!< UART Rx RDR register mask */
uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used.
This parameter can be a value of @ref UARTEx_FIFO_mode. */
uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
and also related to Tx operations. This parameter
can be a value of @ref HAL_UART_StateTypeDef */
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This
parameter can be a value of @ref HAL_UART_StateTypeDef */
__IO uint32_t ErrorCode; /*!< UART Error code */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */
void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
} UART_HandleTypeDef;
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/**
* @brief HAL UART Callback ID enumeration definition
*/
typedef enum
{
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */
HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */
HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
} HAL_UART_CallbackIDTypeDef;
/**
* @brief HAL UART Callback pointer definition
*/
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
typedef void (*pUART_RxEventCallbackTypeDef)
(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UART_Exported_Constants UART Exported Constants
* @{
*/
/** @defgroup UART_State_Definition UART State Code Definition
* @{
*/
#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
Value is allowed for gState and RxState */
#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
Value is allowed for gState only */
#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
Value is allowed for gState only */
#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.Value is result
of combination (Or) between gState and RxState values */
#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error
Value is allowed for gState only */
/**
* @}
*/
/** @defgroup UART_Error_Definition UART Error Definition
* @{
*/
#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */
#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */
/**
* @}
*/
/** @defgroup UART_Parity UART Parity
* @{
*/
#define UART_PARITY_NONE 0x00000000U /*!< No parity */
#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
*/
#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */
#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */
#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */
#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */
/**
* @}
*/
/** @defgroup UART_Mode UART Transfer Mode
* @{
*/
#define UART_MODE_RX USART_CR1_RE /*!< RX mode */
#define UART_MODE_TX USART_CR1_TE /*!< TX mode */
#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
/** @defgroup UART_State UART State
* @{
*/
#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */
#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */
/**
* @}
*/
/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
/**
* @}
*/
/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
* @{
*/
#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */
#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */
/**
* @}
*/
/** @defgroup UART_ClockPrescaler UART Clock Prescaler
* @{
*/
#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
/**
* @}
*/
/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
* @{
*/
#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection
on start bit */
#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection
on falling edge */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection
on 0x7F frame detection */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection
on 0x55 frame detection */
/**
* @}
*/
/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
* @{
*/
#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */
#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */
/**
* @}
*/
/** @defgroup UART_LIN UART Local Interconnection Network mode
* @{
*/
#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */
#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */
/**
* @}
*/
/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
* @{
*/
#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */
#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */
/**
* @}
*/
/** @defgroup UART_DMA_Tx UART DMA Tx
* @{
*/
#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */
#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */
/**
* @}
*/
/** @defgroup UART_DMA_Rx UART DMA Rx
* @{
*/
#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */
#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */
/**
* @}
*/
/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
* @{
*/
#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */
#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */
/**
* @}
*/
/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
* @{
*/
#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */
#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */
/**
* @}
*/
/** @defgroup UART_Request_Parameters UART Request Parameters
* @{
*/
#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */
#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */
#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
* @{
*/
#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */
#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
/**
* @}
*/
/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
* @{
*/
#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */
#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */
/**
* @}
*/
/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
* @{
*/
#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */
#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */
/**
* @}
*/
/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
* @{
*/
#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */
#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */
/**
* @}
*/
/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
* @{
*/
#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */
#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */
/**
* @}
*/
/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
* @{
*/
#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */
/**
* @}
*/
/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
* @{
*/
#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */
#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */
/**
* @}
*/
/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
* @{
*/
#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */
#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */
/**
* @}
*/
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
* @{
*/
#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received
first disable */
#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received
first enable */
/**
* @}
*/
/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
* @{
*/
#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */
#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */
/**
* @}
*/
/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
* @{
*/
#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */
#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */
/**
* @}
*/
/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
* @{
*/
#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
/**
* @}
*/
/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
* @{
*/
#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
#define UART_WAKEUP_ON_READDATA_NONEMPTY 0x00000001U /*!< UART wake-up on receive data register
not empty or RXFIFO is not empty */
/**
* @}
*/
/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
* @{
*/
#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */
#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */
/**
* @}
*/
/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
* @{
*/
#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB
position in CR1 register */
/**
* @}
*/
/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
* @{
*/
#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB
position in CR1 register */
/**
* @}
*/
/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
* @{
*/
#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */
/**
* @}
*/
/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
* @{
*/
#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */
/**
* @}
*/
/** @defgroup UART_Flags UART Status Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */
#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */
#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */
#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */
#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */
#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */
#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */
#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */
#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */
#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */
#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */
#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */
#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */
#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */
#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */
#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */
#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */
#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */
#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */
#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */
#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */
#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */
#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */
/**
* @}
*/
/** @defgroup UART_Interrupt_definition UART Interrupts Definition
* Elements values convention: 000ZZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZZ : Flag position in the ISR register(5bits)
* Elements values convention: 000000000XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* Elements values convention: 0000ZZZZ00000000b
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */
#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */
#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
#define UART_IT_CM 0x112EU /*!< UART character match interruption */
#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */
#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */
#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */
#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */
#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
#define UART_IT_ERR 0x0060U /*!< UART error interruption */
#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
/**
* @}
*/
/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
* @{
*/
#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */
#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */
/**
* @}
*/
/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
* @{
*/
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */
#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup UART_Exported_Macros UART Exported Macros
* @{
*/
/** @brief Reset UART handle states.
* @param __HANDLE__ UART handle.
* @retval None
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
/** @brief Flush the UART Data registers.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
* @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
* @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
* @retval None
*/
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the UART PE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
/** @brief Clear the UART FE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
/** @brief Clear the UART NE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
/** @brief Clear the UART ORE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
/** @brief Clear the UART IDLE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
/** @brief Clear the UART TX FIFO empty clear flag.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
/** @brief Check whether the specified UART flag is set or not.
* @param __HANDLE__ specifies the UART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref UART_FLAG_TXFT TXFIFO threshold flag
* @arg @ref UART_FLAG_RXFT RXFIFO threshold flag
* @arg @ref UART_FLAG_RXFF RXFIFO Full flag
* @arg @ref UART_FLAG_TXFE TXFIFO Empty flag
* @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
* @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
* @arg @ref UART_FLAG_SBKF Send Break flag
* @arg @ref UART_FLAG_CMF Character match flag
* @arg @ref UART_FLAG_BUSY Busy flag
* @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
* @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
* @arg @ref UART_FLAG_CTS CTS Change flag
* @arg @ref UART_FLAG_LBDF LIN Break detection flag
* @arg @ref UART_FLAG_TXE Transmit data register empty flag
* @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
* @arg @ref UART_FLAG_TC Transmission Complete flag
* @arg @ref UART_FLAG_RXNE Receive data register not empty flag
* @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
* @arg @ref UART_FLAG_RTOF Receiver Timeout flag
* @arg @ref UART_FLAG_IDLE Idle Line detection flag
* @arg @ref UART_FLAG_ORE Overrun Error flag
* @arg @ref UART_FLAG_NE Noise Error flag
* @arg @ref UART_FLAG_FE Framing Error flag
* @arg @ref UART_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Enable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref UART_IT_RXFF RXFIFO Full interrupt
* @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\
((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
((__HANDLE__)->Instance->CR1 |= (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
((__HANDLE__)->Instance->CR2 |= (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U <<\
((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Disable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref UART_IT_RXFF RXFIFO Full interrupt
* @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\
((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Check whether the specified UART interrupt has occurred or not.
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt to check.
* This parameter can be one of the following values:
* @arg @ref UART_IT_RXFF RXFIFO Full interrupt
* @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
/** @brief Check whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref UART_IT_RXFF RXFIFO Full interrupt
* @arg @ref UART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref UART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref UART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref UART_IT_CM Character match interrupt
* @arg @ref UART_IT_CTS CTS change interrupt
* @arg @ref UART_IT_LBD LIN Break detection interrupt
* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref UART_IT_TC Transmission complete interrupt
* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref UART_IT_RTO Receive Timeout interrupt
* @arg @ref UART_IT_IDLE Idle line detection interrupt
* @arg @ref UART_IT_PE Parity Error interrupt
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
(__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
(__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U <<\
(((uint16_t)(__INTERRUPT__)) &\
UART_IT_MASK))) != RESET) ? SET : RESET)
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the UART Handle.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
* @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
* @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
* @retval None
*/
#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific UART request flag.
* @param __HANDLE__ specifies the UART Handle.
* @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
* @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
* @arg @ref UART_SENDBREAK_REQUEST Send Break Request
* @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
* @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
* @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
* @retval None
*/
#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the UART one bit sample method.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the UART one bit sample method.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
/** @brief Enable UART.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/** @brief Enable CTS flow control.
* @note This macro allows to enable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
do{ \
ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
} while(0U)
/** @brief Disable CTS flow control.
* @note This macro allows to disable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
do{ \
ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
} while(0U)
/** @brief Enable RTS flow control.
* @note This macro allows to enable RTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
do{ \
ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
} while(0U)
/** @brief Disable RTS flow control.
* @note This macro allows to disable RTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
do{ \
ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0U)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
/** @brief Get UART clok division factor from clock prescaler value.
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval UART clock division factor
*/
#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
(((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
/** @brief BRR division operation to set BRR register with LPUART.
* @param __PCLK__ LPUART clock.
* @param __BAUD__ Baud rate set by the user.
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
(uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \
)
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ UART clock.
* @param __BAUD__ Baud rate set by the user.
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
(((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
* @param __PCLK__ UART clock.
* @param __BAUD__ Baud rate set by the user.
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Check whether or not UART instance is Low Power UART.
* @param __HANDLE__ specifies the UART Handle.
* @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
*/
#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
/** @brief Check UART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on U5 (i.e. 160 MHz)
* divided by the smallest oversampling used on the USART (i.e. 8)
* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
*/
#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 20000000U)
/** @brief Check UART assertion time.
* @param __TIME__ 5-bit value assertion time.
* @retval Test result (TRUE or FALSE).
*/
#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
/** @brief Check UART deassertion time.
* @param __TIME__ 5-bit value deassertion time.
* @retval Test result (TRUE or FALSE).
*/
#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
/**
* @brief Ensure that UART frame number of stop bits is valid.
* @param __STOPBITS__ UART frame number of stop bits.
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
*/
#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
((__STOPBITS__) == UART_STOPBITS_1) || \
((__STOPBITS__) == UART_STOPBITS_1_5) || \
((__STOPBITS__) == UART_STOPBITS_2))
/**
* @brief Ensure that LPUART frame number of stop bits is valid.
* @param __STOPBITS__ LPUART frame number of stop bits.
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
*/
#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
((__STOPBITS__) == UART_STOPBITS_2))
/**
* @brief Ensure that UART frame parity is valid.
* @param __PARITY__ UART frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
*/
#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
((__PARITY__) == UART_PARITY_EVEN) || \
((__PARITY__) == UART_PARITY_ODD))
/**
* @brief Ensure that UART hardware flow control is valid.
* @param __CONTROL__ UART hardware flow control.
* @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
*/
#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
((__CONTROL__) == UART_HWCONTROL_RTS) || \
((__CONTROL__) == UART_HWCONTROL_CTS) || \
((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
/**
* @brief Ensure that UART communication mode is valid.
* @param __MODE__ UART communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/**
* @brief Ensure that UART state is valid.
* @param __STATE__ UART state.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
((__STATE__) == UART_STATE_ENABLE))
/**
* @brief Ensure that UART oversampling is valid.
* @param __SAMPLING__ UART oversampling.
* @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
*/
#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
((__SAMPLING__) == UART_OVERSAMPLING_8))
/**
* @brief Ensure that UART frame sampling is valid.
* @param __ONEBIT__ UART frame sampling.
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
*/
#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
/**
* @brief Ensure that UART auto Baud rate detection mode is valid.
* @param __MODE__ UART auto Baud rate detection mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
/**
* @brief Ensure that UART receiver timeout setting is valid.
* @param __TIMEOUT__ UART receiver timeout setting.
* @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
*/
#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
/** @brief Check the receiver timeout value.
* @note The maximum UART receiver timeout value is 0xFFFFFF.
* @param __TIMEOUTVALUE__ receiver timeout value.
* @retval Test result (TRUE or FALSE)
*/
#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
/**
* @brief Ensure that UART LIN state is valid.
* @param __LIN__ UART LIN state.
* @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
*/
#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
((__LIN__) == UART_LIN_ENABLE))
/**
* @brief Ensure that UART LIN break detection length is valid.
* @param __LENGTH__ UART LIN break detection length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
/**
* @brief Ensure that UART DMA TX state is valid.
* @param __DMATX__ UART DMA TX state.
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
*/
#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
((__DMATX__) == UART_DMA_TX_ENABLE))
/**
* @brief Ensure that UART DMA RX state is valid.
* @param __DMARX__ UART DMA RX state.
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
*/
#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
((__DMARX__) == UART_DMA_RX_ENABLE))
/**
* @brief Ensure that UART half-duplex state is valid.
* @param __HDSEL__ UART half-duplex state.
* @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
*/
#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
/**
* @brief Ensure that UART wake-up method is valid.
* @param __WAKEUP__ UART wake-up method .
* @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
*/
#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
/**
* @brief Ensure that UART request parameter is valid.
* @param __PARAM__ UART request parameter.
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
*/
#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
((__PARAM__) == UART_SENDBREAK_REQUEST) || \
((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
/**
* @brief Ensure that UART advanced features initialization is valid.
* @param __INIT__ UART advanced features initialization.
* @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
*/
#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
UART_ADVFEATURE_TXINVERT_INIT | \
UART_ADVFEATURE_RXINVERT_INIT | \
UART_ADVFEATURE_DATAINVERT_INIT | \
UART_ADVFEATURE_SWAP_INIT | \
UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
UART_ADVFEATURE_AUTOBAUDRATE_INIT | \
UART_ADVFEATURE_MSBFIRST_INIT))
/**
* @brief Ensure that UART frame TX inversion setting is valid.
* @param __TXINV__ UART frame TX inversion setting.
* @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
*/
#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
/**
* @brief Ensure that UART frame RX inversion setting is valid.
* @param __RXINV__ UART frame RX inversion setting.
* @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
*/
#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
/**
* @brief Ensure that UART frame data inversion setting is valid.
* @param __DATAINV__ UART frame data inversion setting.
* @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
*/
#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
/**
* @brief Ensure that UART frame RX/TX pins swap setting is valid.
* @param __SWAP__ UART frame RX/TX pins swap setting.
* @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
*/
#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
/**
* @brief Ensure that UART frame overrun setting is valid.
* @param __OVERRUN__ UART frame overrun setting.
* @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
*/
#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
/**
* @brief Ensure that UART auto Baud rate state is valid.
* @param __AUTOBAUDRATE__ UART auto Baud rate state.
* @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
*/
#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
/**
* @brief Ensure that UART DMA enabling or disabling on error setting is valid.
* @param __DMA__ UART DMA enabling or disabling on error setting.
* @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
*/
#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
/**
* @brief Ensure that UART frame MSB first setting is valid.
* @param __MSBFIRST__ UART frame MSB first setting.
* @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
*/
#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
/**
* @brief Ensure that UART stop mode state is valid.
* @param __STOPMODE__ UART stop mode state.
* @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
*/
#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
/**
* @brief Ensure that UART mute mode state is valid.
* @param __MUTE__ UART mute mode state.
* @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
*/
#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
/**
* @brief Ensure that UART wake-up selection is valid.
* @param __WAKE__ UART wake-up selection.
* @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
*/
#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
/**
* @brief Ensure that UART driver enable polarity is valid.
* @param __POLARITY__ UART driver enable polarity.
* @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
*/
#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
((__POLARITY__) == UART_DE_POLARITY_LOW))
/**
* @brief Ensure that UART Prescaler is valid.
* @param __CLOCKPRESCALER__ UART Prescaler value.
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
*/
#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
/**
* @}
*/
/* Include UART HAL Extended module */
#include "stm32u5xx_hal_uart_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{
*/
/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State and Errors functions **************************************************/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/**
* @}
*/
/**
* @}
*/
/* Private functions -----------------------------------------------------------*/
/** @addtogroup UART_Private_Functions UART Private Functions
* @{
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
/**
* @}
*/
/* Private variables -----------------------------------------------------------*/
/** @defgroup UART_Private_variables UART Private variables
* @{
*/
/* Prescaler Table used in BRR computation macros.
Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
extern const uint16_t UARTPrescTable[12];
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_UART_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h
|
C
|
apache-2.0
| 87,621
|
/**
******************************************************************************
* @file stm32u5xx_hal_uart_ex.h
* @author MCD Application Team
* @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_UART_EX_H
#define STM32U5xx_HAL_UART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup UARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
* @{
*/
/**
* @brief UART wake up from stop mode parameters
*/
typedef struct
{
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
/**
* @brief UART Autonomous mode parameters
*/
typedef struct
{
uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of
@ref UARTEx_Autonomous_mode.*/
uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically.
This parameter can be a value of @ref UARTEx_Autonomous_Trigger_selection
or @ref LPUARTEx_Autonomous_Trigger_selection.*/
uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity.
This parameter can be a value of @ref UARTEx_Autonomous_Trigger_Polarity */
uint32_t DataSize; /*!< Specifies the transmitted data size in byte */
uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled.
This parameter can be a value of @ref UARTEx_Autonomous_IDLE_FRAME. */
} UART_AutonomousModeConfTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
*/
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
/**
* @}
*/
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
* @brief UART FIFO mode
* @{
*/
#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
* @brief UART TXFIFO threshold level
* @{
*/
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
/**
* @}
*/
/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
* @brief UART RXFIFO threshold level
* @{
*/
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
/**
* @}
*/
/** @defgroup UARTEx_Autonomous_mode UARTEx Autonomous Mode
* @brief UART Autonomous mode
* @{
*/
#define UART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */
#define UART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */
/**
* @}
*/
/** @defgroup UARTEx_Autonomous_Trigger_Polarity UARTEx Autonomous Trigger Polarity
* @brief UART Trigger polarity edge selection
* @{
*/
#define UART_TRIG_POLARITY_RISING 0x00000000U /*!< UART triggered on rising edge */
#define UART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< UART triggered on falling edge */
/**
* @}
*/
/** @defgroup UARTEx_Autonomous_IDLE_FRAME UARTEx Autonomous IDLE Frame
* @brief UART IDLE frame transmission
* @{
*/
#define UART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */
#define UART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */
/**
* @}
*/
/** @defgroup UARTEx_Autonomous_Trigger_selection UARTEx Autonomous trigger selection
* @brief UART Autonomous Trigger selection
* @{
*/
#define UART_GPDMA1_CH0_TCF_TRG 0U /*!< UART GPDMA1 channel0 Internal Trigger */
#define UART_GPDMA1_CH1_TCF_TRG 1U /*!< UART GPDMA1 channel1 Internal Trigger */
#define UART_GPDMA1_CH2_TCF_TRG 2U /*!< UART GPDMA1 channel2 Internal Trigger */
#define UART_GPDMA1_CH3_TCF_TRG 3U /*!< UART GPDMA1 channel3 Internal Trigger */
#define UART_EXTI_LINE6_TRG 4U /*!< UART EXTI line 6 Internal Trigger */
#define UART_EXTI_LINE9_TRG 5U /*!< UART EXTI line 9 Internal Trigger */
#define UART_LPTIM1_OUT_TRG 6U /*!< UART LPTIM1 out Internal Trigger */
#define UART_LPTIM2_OUT_TRG 7U /*!< UART LPTIM2 out Internal Trigger */
#define UART_COMP1_OUT_TRG 8U /*!< UART COMP1 out Internal Trigger */
#define UART_COMP2_OUT_TRG 9U /*!< UART COMP2 out Internal Trigger */
#define UART_RTC_ALRA_TRG 10U /*!< UART RTC alarm Internal Trigger */
#define UART_RTC_WUT_TRG 11U /*!< UART RTC wakeup Internal Trigger */
/**
* @}
*/
/** @defgroup LPUARTEx_Autonomous_Trigger_selection LPUARTEx Autonomous trigger selection
* @brief LPUART Autonomous Trigger selection
* @{
*/
#define LPUART_LPDMA1_CH0_TCF_TRG 0U /*!< LPUART LPDMA1 channel0 Internal Trigger */
#define LPUART_LPDMA1_CH1_TCF_TRG 1U /*!< LPUART LPDMA1 channel1 Internal Trigger */
#define LPUART_LPDMA1_CH2_TCF_TRG 2U /*!< LPUART LPDMA1 channel2 Internal Trigger */
#define LPUART_LPDMA1_CH3_TCF_TRG 3U /*!< LPUART LPDMA1 channel3 Internal Trigger */
#define LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */
#define LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */
#define LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */
#define LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */
#define LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */
#define LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */
#define LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */
#define LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UARTEx_Exported_Functions
* @{
*/
/** @addtogroup UARTEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group2
* @{
*/
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
/* Autonomous Mode Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart,
UART_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(UART_HandleTypeDef *huart,
UART_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
* @{
*/
/** @brief Report the UART clock source.
* @param __HANDLE__ specifies the UART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(USART6)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \
} \
else \
{ \
(__CLOCKSOURCE__) = 0U; \
} \
} while(0U)
#else
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \
} \
else \
{ \
(__CLOCKSOURCE__) = 0U; \
} \
} while(0U)
#endif /* USART6 */
/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__ specifies the UART Handle.
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that UART frame length is valid.
* @param __LENGTH__ UART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
/**
* @brief Ensure that UART wake-up address length is valid.
* @param __ADDRESS__ UART wake-up address length.
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
*/
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
/**
* @brief Ensure that UART TXFIFO threshold level is valid.
* @param __THRESHOLD__ UART TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that UART RXFIFO threshold level is valid.
* @param __THRESHOLD__ UART RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that UART Trigger polarity state is valid.
* @param __POLARITY__ UART Trigger polarity.
* @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
*/
#define IS_UART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == UART_TRIG_POLARITY_RISING) ||\
((__POLARITY__) == UART_TRIG_POLARITY_FALLING))
/**
* @brief Ensure that UART IDLE Frame Transmit state is valid.
* @param __IDLE__ UART IDLE Frame Transmit state.
* @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid)
*/
#define IS_UART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == UART_IDLE_FRAME_ENABLE) ||\
((__IDLE__) == UART_IDLE_FRAME_DISABLE))
/**
* @brief Ensure that UART Trigger source selection is valid.
* @param __SOURCE__ UART Trigger source selection.
* @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
*/
#define IS_UART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U)
/**
* @brief Ensure that LPUART Trigger source selection is valid.
* @param __SOURCE__ LPUART Trigger source selection.
* @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
*/
#define IS_LPUART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U)
/**
* @brief Ensure that the number of transferred data is valid.
* @param __SOURCE__ UART TX data size.
* @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
*/
#define IS_UART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_UART_EX_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h
|
C
|
apache-2.0
| 24,224
|
/**
******************************************************************************
* @file stm32u5xx_hal_usart.h
* @author MCD Application Team
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_USART_H
#define STM32U5xx_HAL_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup USART_Exported_Types USART Exported Types
* @{
*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
Baud Rate Register[15:4] = ((2 * fclk_pres) /
((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
Baud Rate Register[2:0] = (((2 * fclk_pres) /
((huart->Init.BaudRate)))[3:0]) >> 1
where fclk_pres is the USART input clock frequency (fclk)
divided by a prescaler.
@note Oversampling by 8 is systematically applied to
achieve high baud rates. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USARTEx_Word_Length. */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits. */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode. */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity. */
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase. */
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit. */
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source.
This parameter can be a value of @ref USART_ClockPrescaler. */
} USART_InitTypeDef;
/**
* @brief HAL USART State structures definition
*/
typedef enum
{
HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_USART_STATE_ERROR = 0x04U /*!< Error */
} HAL_USART_StateTypeDef;
/**
* @brief USART clock sources definitions
*/
typedef enum
{
USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
} USART_ClockSourceTypeDef;
/**
* @brief USART handle Structure definition
*/
typedef struct __USART_HandleTypeDef
{
USART_TypeDef *Instance; /*!< USART registers base address */
USART_InitTypeDef Init; /*!< USART communication parameters */
const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
uint16_t TxXferSize; /*!< USART Tx Transfer size */
__IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
uint16_t RxXferSize; /*!< USART Rx Transfer size */
__IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
uint16_t Mask; /*!< USART Rx RDR register mask */
uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
of @ref USARTEx_Slave_Mode */
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
of @ref USARTEx_FIFO_mode. */
void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */
DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_USART_StateTypeDef State; /*!< USART communication state */
__IO uint32_t ErrorCode; /*!< USART Error code */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */
void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
} USART_HandleTypeDef;
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
/**
* @brief HAL USART Callback ID enumeration definition
*/
typedef enum
{
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */
HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */
HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */
} HAL_USART_CallbackIDTypeDef;
/**
* @brief HAL USART Callback pointer definition
*/
typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_Exported_Constants USART Exported Constants
* @{
*/
/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */
#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */
#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */
/**
* @}
*/
/** @defgroup USART_Parity USART Parity
* @{
*/
#define USART_PARITY_NONE 0x00000000U /*!< No parity */
#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
/** @defgroup USART_Mode USART Mode
* @{
*/
#define USART_MODE_RX USART_CR1_RE /*!< RX mode */
#define USART_MODE_TX USART_CR1_TE /*!< TX mode */
#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
/** @defgroup USART_Clock USART Clock
* @{
*/
#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */
#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */
/**
* @}
*/
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */
#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */
/**
* @}
*/
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */
#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */
/**
* @}
*/
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */
#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */
/**
* @}
*/
/** @defgroup USART_ClockPrescaler USART Clock Prescaler
* @{
*/
#define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
#define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
#define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
#define USART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
#define USART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
#define USART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
#define USART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
#define USART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
#define USART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
/**
* @}
*/
/** @defgroup USART_Request_Parameters USART Request Parameters
* @{
*/
#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
/** @defgroup USART_Flags USART Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */
#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */
#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */
#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */
#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */
#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */
#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */
#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */
#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */
/**
* @}
*/
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
* Elements values convention: 0000ZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define USART_IT_PE 0x0028U /*!< USART parity error interruption */
#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */
#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */
#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */
#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */
#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */
#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */
#define USART_IT_ERR 0x0060U /*!< USART error interruption */
#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */
#define USART_IT_NE 0x0200U /*!< USART noise error interruption */
#define USART_IT_FE 0x0100U /*!< USART frame error interruption */
#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */
#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */
#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */
#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */
/**
* @}
*/
/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
* @{
*/
#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
* @{
*/
#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */
#define USART_CR_MASK 0x00E0U /*!< USART control register mask */
#define USART_CR_POS 5U /*!< USART control register position */
#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */
#define USART_ISR_POS 8U /*!< USART ISR register position */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup USART_Exported_Macros USART Exported Macros
* @{
*/
/** @brief Reset USART handle state.
* @param __HANDLE__ USART handle.
* @retval None
*/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/** @brief Check whether the specified USART flag is set or not.
* @param __HANDLE__ specifies the USART Handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref USART_FLAG_TXFT TXFIFO threshold flag
* @arg @ref USART_FLAG_RXFT RXFIFO threshold flag
* @arg @ref USART_FLAG_RXFF RXFIFO Full flag
* @arg @ref USART_FLAG_TXFE TXFIFO Empty flag
* @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
* @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref USART_FLAG_BUSY Busy flag
* @arg @ref USART_FLAG_UDR SPI slave underrun error flag
* @arg @ref USART_FLAG_TXE Transmit data register empty flag
* @arg @ref USART_FLAG_TXFNF TXFIFO not full flag
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
* @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
* @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
* @arg @ref USART_FLAG_FE Framing Error flag
* @arg @ref USART_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified USART pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
* @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag
* @retval None
*/
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the USART PE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
/** @brief Clear the USART FE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
/** @brief Clear the USART NE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
/** @brief Clear the USART ORE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
/** @brief Clear the USART IDLE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
/** @brief Clear the USART TX FIFO empty clear flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
/** @brief Clear SPI slave underrun error flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
/** @brief Enable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref USART_IT_RXFF RXFIFO Full interrupt
* @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref USART_IT_RXFF RXFIFO Full interrupt
* @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Check whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref USART_IT_RXFF RXFIFO Full interrupt
* @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_ORE OverRun Error interrupt
* @arg @ref USART_IT_NE Noise Error interrupt
* @arg @ref USART_IT_FE Framing Error interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref USART_IT_RXFF RXFIFO Full interrupt
* @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_ORE OverRun Error interrupt
* @arg @ref USART_IT_NE Noise Error interrupt
* @arg @ref USART_IT_FE Framing Error interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
(__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
(__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (0x01U <<\
(((uint16_t)(__INTERRUPT__)) &\
USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the USART Handle.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt.
* This parameter can be one of the following values:
* @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
* @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific USART request flag.
* @param __HANDLE__ specifies the USART Handle.
* @param __REQ__ specifies the request flag to set.
* This parameter can be one of the following values:
* @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
* @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
*
* @retval None
*/
#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the USART one bit sample method.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the USART one bit sample method.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
/** @brief Enable USART.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable USART.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup USART_Private_Macros USART Private Macros
* @{
*/
/** @brief Get USART clock division factor from clock prescaler value.
* @param __CLOCKPRESCALER__ USART prescaler value.
* @retval USART clock division factor
*/
#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock.
* @param __BAUD__ Baud rate set by the user.
* @param __CLOCKPRESCALER__ USART prescaler value.
* @retval Division result
*/
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
(((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Report the USART clock source.
* @param __HANDLE__ specifies the USART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(USART6)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART6CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART6CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART6CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* USART6 */
/** @brief Check USART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on U5 (i.e. 160 MHz)
* divided by the smallest oversampling used on the USART (i.e. 8)
* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */
#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 20000000U)
/**
* @brief Ensure that USART frame number of stop bits is valid.
* @param __STOPBITS__ USART frame number of stop bits.
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
*/
#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
((__STOPBITS__) == USART_STOPBITS_1) || \
((__STOPBITS__) == USART_STOPBITS_1_5) || \
((__STOPBITS__) == USART_STOPBITS_2))
/**
* @brief Ensure that USART frame parity is valid.
* @param __PARITY__ USART frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
*/
#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
((__PARITY__) == USART_PARITY_EVEN) || \
((__PARITY__) == USART_PARITY_ODD))
/**
* @brief Ensure that USART communication mode is valid.
* @param __MODE__ USART communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/**
* @brief Ensure that USART clock state is valid.
* @param __CLOCK__ USART clock state.
* @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
*/
#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
((__CLOCK__) == USART_CLOCK_ENABLE))
/**
* @brief Ensure that USART frame polarity is valid.
* @param __CPOL__ USART frame polarity.
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
*/
#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
/**
* @brief Ensure that USART frame phase is valid.
* @param __CPHA__ USART frame phase.
* @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
*/
#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
/**
* @brief Ensure that USART frame last bit clock pulse setting is valid.
* @param __LASTBIT__ USART frame last bit clock pulse setting.
* @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
*/
#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
((__LASTBIT__) == USART_LASTBIT_ENABLE))
/**
* @brief Ensure that USART request parameter is valid.
* @param __PARAM__ USART request parameter.
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
*/
#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
/**
* @brief Ensure that USART Prescaler is valid.
* @param __CLOCKPRESCALER__ USART Prescaler value.
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
*/
#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))
/**
* @}
*/
/* Include USART HAL Extended module */
#include "stm32u5xx_hal_usart_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USART_Exported_Functions USART Exported Functions
* @{
*/
/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
/**
* @}
*/
/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_USART_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h
|
C
|
apache-2.0
| 57,726
|
/**
******************************************************************************
* @file stm32u5xx_hal_usart_ex.h
* @author MCD Application Team
* @brief Header file of USART HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_USART_EX_H
#define STM32U5xx_HAL_USART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup USARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup USARTEx_Exported_Types USARTEx Exported Types
* @{
*/
/**
* @brief USART Autonomous mode parameters
*/
typedef struct
{
uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of
@ref USARTEx_Autonomous_mode.*/
uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically.
This parameter can be a value of @ref USARTEx_Autonomous_Trigger_selection */
uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity.
This parameter can be a value of @ref USARTEx_Autonomous_Trigger_Polarity */
uint32_t DataSize; /*!< Specifies the transmitted data size in byte */
uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled.
This parameter can be a value of @ref USARTEx_Autonomous_IDLE_FRAME. */
} USART_AutonomousModeConfTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
* @{
*/
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
*/
/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management
* @{
*/
#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */
#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */
/**
* @}
*/
/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable
* @brief USART SLAVE mode
* @{
*/
#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */
#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
/**
* @}
*/
/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode
* @brief USART FIFO mode
* @{
*/
#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level
* @brief USART TXFIFO level
* @{
*/
#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
/**
* @}
*/
/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level
* @brief USART RXFIFO level
* @{
*/
#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
/**
* @}
*/
/** @defgroup USARTEx_Autonomous_mode USARTEx Autonomous Mode
* @brief USART Autonomous mode
* @{
*/
#define USART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */
#define USART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */
/**
* @}
*/
/** @defgroup USARTEx_Autonomous_Trigger_Polarity USARTEx Autonomous Trigger Polarity
* @brief USART Trigger polarity edge selection
* @{
*/
#define USART_TRIG_POLARITY_RISING 0x00000000U /*!< USART triggered on rising edge */
#define USART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< USART triggered on falling edge */
/**
* @}
*/
/** @defgroup USARTEx_Autonomous_IDLE_FRAME USARTEx Autonomous IDLE Frame
* @brief USART IDLE frame transmission
* @{
*/
#define USART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */
#define USART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */
/**
* @}
*/
/** @defgroup USARTEx_Autonomous_Trigger_selection USARTEx Autonomous trigger selection
* @brief USART Autonomous Trigger selection
* @{
*/
#define USART_GPDMA1_CH0_TCF_TRG 0U /*!< USART GPDMA1 channel0 Internal Trigger */
#define USART_GPDMA1_CH1_TCF_TRG 1U /*!< USART GPDMA1 channel1 Internal Trigger */
#define USART_GPDMA1_CH2_TCF_TRG 2U /*!< USART GPDMA1 channel2 Internal Trigger */
#define USART_GPDMA1_CH3_TCF_TRG 3U /*!< USART GPDMA1 channel3 Internal Trigger */
#define USART_EXTI_LINE6_TRG 4U /*!< USART EXTI line 6 Internal Trigger */
#define USART_EXTI_LINE9_TRG 5U /*!< USART EXTI line 9 Internal Trigger */
#define USART_LPTIM1_OUT_TRG 6U /*!< USART LPTIM1 out Internal Trigger */
#define USART_LPTIM2_OUT_TRG 7U /*!< USART LPTIM2 out Internal Trigger */
#define USART_COMP1_OUT_TRG 8U /*!< USART COMP1 out Internal Trigger */
#define USART_COMP2_OUT_TRG 9U /*!< USART COMP2 out Internal Trigger */
#define USART_RTC_ALRA_TRG 10U /*!< USART RTC alarm Internal Trigger */
#define USART_RTC_WUT_TRG 11U /*!< USART RTC wakeup Internal Trigger */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
* @{
*/
/** @brief Compute the USART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__ specifies the USART Handle.
* @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that USART frame length is valid.
* @param __LENGTH__ USART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B))
/**
* @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.
* @param __NSS__ USART Negative Slave Select pin management.
* @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
*/
#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \
((__NSS__) == USART_NSS_SOFT))
/**
* @brief Ensure that USART Slave Mode is valid.
* @param __STATE__ USART Slave Mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
((__STATE__) == USART_SLAVEMODE_ENABLE))
/**
* @brief Ensure that USART FIFO mode is valid.
* @param __STATE__ USART FIFO mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
((__STATE__) == USART_FIFOMODE_ENABLE))
/**
* @brief Ensure that USART TXFIFO threshold level is valid.
* @param __THRESHOLD__ USART TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that USART RXFIFO threshold level is valid.
* @param __THRESHOLD__ USART RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that USART Trigger polarity state is valid.
* @param __POLARITY__ USART Trigger polarity.
* @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
*/
#define IS_USART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == USART_TRIG_POLARITY_RISING) ||\
((__POLARITY__) == USART_TRIG_POLARITY_FALLING))
/**
* @brief Ensure that USART IDLE Frame Transmit state is valid.
* @param __IDLE__ USART IDLE Frame Transmit state.
* @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid)
*/
#define IS_USART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == USART_IDLE_FRAME_ENABLE) ||\
((__IDLE__) == USART_IDLE_FRAME_DISABLE))
/**
* @brief Ensure that USART Trigger source selection is valid.
* @param __SOURCE__ USART Trigger source selection.
* @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
*/
#define IS_USART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U)
/**
* @brief Ensure that the number of transferred data is valid.
* @param __SOURCE__ USART TX data size.
* @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid)
*/
#define IS_USART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USARTEx_Exported_Functions
* @{
*/
/** @addtogroup USARTEx_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);
void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);
/**
* @}
*/
/** @addtogroup USARTEx_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);
HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
HAL_StatusTypeDef HAL_USARTEx_SetConfigAutonomousMode(USART_HandleTypeDef *husart,
USART_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(USART_HandleTypeDef *husart,
USART_AutonomousModeConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_USARTEx_ClearConfigAutonomousMode(USART_HandleTypeDef *husart);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_USART_EX_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h
|
C
|
apache-2.0
| 17,468
|
/**
******************************************************************************
* @file stm32u5xx_hal_wwdg.h
* @author MCD Application Team
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_WWDG_H
#define STM32U5xx_HAL_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Types WWDG Exported Types
* @{
*/
/**
* @brief WWDG Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
This parameter can be a value of @ref WWDG_Prescaler */
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
} WWDG_InitTypeDef;
/**
* @brief WWDG handle Structure definition
*/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
} WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/**
* @brief HAL WWDG common Callback ID enumeration definition
*/
typedef enum
{
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
} HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
* @{
*/
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
/**
* @}
*/
/** @defgroup WWDG_Flag_definition WWDG Flag definition
* @brief WWDG Flag definition
* @{
*/
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
/**
* @}
*/
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
#define WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */
#define WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */
#define WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */
#define WWDG_PRESCALER_128 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/128 */
/**
* @}
*/
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
* @{
*/
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
((__PRESCALER__) == WWDG_PRESCALER_2) || \
((__PRESCALER__) == WWDG_PRESCALER_4) || \
((__PRESCALER__) == WWDG_PRESCALER_8) || \
((__PRESCALER__) == WWDG_PRESCALER_16) || \
((__PRESCALER__) == WWDG_PRESCALER_32) || \
((__PRESCALER__) == WWDG_PRESCALER_64) || \
((__PRESCALER__) == WWDG_PRESCALER_128))
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
((__MODE__) == WWDG_EWI_DISABLE))
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
* @{
*/
/**
* @brief Enable the WWDG peripheral.
* @param __HANDLE__ WWDG handle
* @retval None
*/
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
/**
* @brief Enable the WWDG early wakeup interrupt.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @retval None
*/
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
/**
* @brief Check whether the selected WWDG interrupt has occurred or not.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the it to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
/** @brief Clear the WWDG interrupt pending bits.
* bits to clear the selected interrupt pending bits.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
*/
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
/**
* @brief Check whether the specified WWDG flag is set or not.
* @param __HANDLE__ WWDG handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the WWDG's pending flags.
* @param __HANDLE__ WWDG handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval None
*/
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Check whether the specified WWDG interrupt source is enabled or not.
* @param __HANDLE__ WWDG Handle.
* @param __INTERRUPT__ specifies the WWDG interrupt source to check.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
& (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup WWDG_Exported_Functions
* @{
*/
/** @addtogroup WWDG_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup WWDG_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_WWDG_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_wwdg.h
|
C
|
apache-2.0
| 11,047
|
/**
******************************************************************************
* @file stm32u5xx_hal_xspi.h
* @author MCD Application Team
* @brief Header file of XSPI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_HAL_XSPI_H
#define STM32U5xx_HAL_XSPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
#include "stm32u5xx_ll_dlyb.h"
#if defined(HSPI) || defined(HSPI1) || defined(HSPI2)|| defined(OCTOSPI) || defined(OCTOSPI1)|| defined(OCTOSPI2)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup XSPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup XSPI_Exported_Types XSPI Exported Types
* @{
*/
#define HAL_XSPI_DLYB_CfgTypeDef LL_DLYB_CfgTypeDef
/**
* @brief XSPI Init structure definition
*/
typedef struct
{
uint32_t FifoThresholdByte; /*!< This is the threshold used by the Peripheral to generate the interrupt
indicating that data are available in reception or free place
is available in transmission. */
/*!< For OCTOSPI, this parameter can be a value between 1 and 32 */
/*!< For HSPI, this parameter can be a value between 1 and 64 */
uint32_t MemoryMode; /*!< It Specifies the memory mode.
This parameter can be a value of @ref XSPI_MemoryMode */
uint32_t MemoryType; /*!< It indicates the external device type connected to the XSPI.
This parameter can be a value of @ref XSPI_MemoryType */
uint32_t MemorySize; /*!< It defines the size of the external device connected to the XSPI,
it corresponds to the number of address bits required to access
the external device.
This parameter can be a value of @ref XSPI_MemorySize*/
uint32_t ChipSelectHighTimeCycle; /*!< It defines the minimum number of clocks which the chip select
must remain high between commands.
This parameter can be a value between 1 and 64U */
uint32_t FreeRunningClock; /*!< It enables or not the free running clock.
This parameter can be a value of @ref XSPI_FreeRunningClock */
uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released.
This parameter can be a value of @ref XSPI_ClockMode */
uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration.
This parameter can be a value of @ref XSPI_WrapSize */
uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating
the external clock based on the AHB clock.
This parameter can be a value between 0 and 255U */
uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order
to take in account external signal delays.
This parameter can be a value of @ref XSPI_SampleShifting */
uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data.
This parameter can be a value of @ref XSPI_DelayHoldQuarterCycle */
uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and
defines the boundary of bytes to release the chip select.
This parameter can be a value of @ref XSPI_ChipSelectBoundary */
uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected
by the delay block.
This parameter can be a value of @ref XSPI_DelayBlockBypass */
uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is
released every MaxTran+1 bytes when the other XSPI request the access
to the bus.
This parameter can be a value between 0 and 255U */
uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every
Refresh+1 clock cycles.
This parameter can be a value between 0 and 0xFFFFFFFF */
} XSPI_InitTypeDef;
/**
* @brief HAL XSPI Handle Structure definition
*/
#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
typedef struct __XSPI_HandleTypeDef
#else
typedef struct
#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
{
XSPI_TypeDef *Instance; /*!< XSPI registers base address */
XSPI_InitTypeDef Init; /*!< XSPI initialization parameters */
uint8_t *pBuffPtr; /*!< Address of the XSPI buffer for transfer */
__IO uint32_t XferSize; /*!< Number of data to transfer */
__IO uint32_t XferCount; /*!< Counter of data transferred */
DMA_HandleTypeDef *hdmatx; /*!< Handle of the DMA channel used for transmit */
DMA_HandleTypeDef *hdmarx; /*!< Handle of the DMA channel used for receive */
__IO uint32_t State; /*!< Internal state of the XSPI HAL driver */
__IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */
uint32_t Timeout; /*!< Timeout used for the XSPI external device access */
#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
void (* ErrorCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* AbortCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* FifoThresholdCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* CmdCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* RxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* TxCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* RxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* TxHalfCpltCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* StatusMatchCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* TimeOutCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* MspInitCallback)(struct __XSPI_HandleTypeDef *hxspi);
void (* MspDeInitCallback)(struct __XSPI_HandleTypeDef *hxspi);
#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
} XSPI_HandleTypeDef;
/**
* @brief HAL XSPI Regular Command Structure definition
*/
typedef struct
{
uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or
to the registers for the write operation (these registers are only
used for memory-mapped mode).
This parameter can be a value of @ref XSPI_OperationType */
uint32_t IOSelect; /*!< It indicates the IOs used to exchange data with external memory.
This parameter can be a value of @ref XSPI_IOSelect */
uint32_t Instruction; /*!< It contains the instruction to be sent to the device.
This parameter can be a value between 0 and 0xFFFFFFFFU */
uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
This parameter can be a value of @ref XSPI_InstructionMode */
uint32_t InstructionWidth; /*!< It indicates the width of the instruction.
This parameter can be a value of @ref XSPI_InstructionWidth */
uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase.
This parameter can be a value of @ref XSPI_InstructionDTRMode */
uint32_t Address; /*!< It contains the address to be sent to the device.
This parameter can be a value between 0 and 0xFFFFFFFF */
uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises number of lines
for address (except no address).
This parameter can be a value of @ref XSPI_AddressMode */
uint32_t AddressWidth; /*!< It indicates the width of the address.
This parameter can be a value of @ref XSPI_AddressWidth */
uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase.
This parameter can be a value of @ref XSPI_AddressDTRMode */
uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device.
This parameter can be a value between 0 and 0xFFFFFFFF */
uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
This parameter can be a value of @ref XSPI_AlternateBytesMode */
uint32_t AlternateBytesWidth; /*!< It indicates the width of the alternate bytes.
This parameter can be a value of @ref XSPI_AlternateBytesWidth */
uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes phase.
This parameter can be a value of @ref XSPI_AlternateBytesDTRMode */
uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of lines
for data exchange (except no data).
This parameter can be a value of @ref XSPI_DataMode */
uint32_t DataLength; /*!< It indicates the number of data transferred with this command.
This field is only used for indirect mode.
This parameter can be a value between 1 and 0xFFFFFFFFU */
uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase.
This parameter can be a value of @ref XSPI_DataDTRMode */
uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase.
This parameter can be a value between 0 and 31U */
uint32_t DQSMode; /*!< It enables or not the data strobe management.
This parameter can be a value of @ref XSPI_DQSMode */
uint32_t SIOOMode; /*!< It enables or not the SIOO mode. When SIOO mode enabled,
instruction will be sent only once.
This parameter can be a value of @ref XSPI_SIOOMode */
} XSPI_RegularCmdTypeDef;
/**
* @brief HAL XSPI Hyperbus Configuration Structure definition
*/
typedef struct
{
uint32_t RWRecoveryTimeCycle; /*!< It indicates the number of cycles for the device read write recovery time.
This parameter can be a value between 0 and 255U */
uint32_t AccessTimeCycle; /*!< It indicates the number of cycles for the device access time.
This parameter can be a value between 0 and 255U */
uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access.
This parameter can be a value of @ref XSPI_WriteZeroLatency */
uint32_t LatencyMode; /*!< It configures the latency mode.
This parameter can be a value of @ref XSPI_LatencyMode */
} XSPI_HyperbusCfgTypeDef;
/**
* @brief HAL XSPI Hyperbus Command Structure definition
*/
typedef struct
{
uint32_t AddressSpace; /*!< It indicates the address space accessed by the command.
This parameter can be a value of @ref XSPI_AddressSpace */
uint32_t Address; /*!< It contains the address to be sent to the device.
This parameter can be a value between 0 and 0xFFFFFFFF */
uint32_t AddressWidth; /*!< It indicates the width of the address.
This parameter can be a value of @ref XSPI_AddressWidth */
uint32_t DataLength; /*!< It indicates the number of data transferred with this command.
This field is only used for indirect mode.
This parameter can be a value between 1 and 0xFFFFFFFF
In case of autopolling mode, this parameter can be
any value between 1 and 4 */
uint32_t DQSMode; /*!< It enables or not the data strobe management.
This parameter can be a value of @ref XSPI_DQSMode */
} XSPI_HyperbusCmdTypeDef;
/**
* @brief HAL XSPI Auto Polling mode configuration structure definition
*/
typedef struct
{
uint32_t MatchValue; /*!< Specifies the value to be compared with the masked status register to get
a match.
This parameter can be any value between 0 and 0xFFFFFFFFU */
uint32_t MatchMask; /*!< Specifies the mask to be applied to the status bytes received.
This parameter can be any value between 0 and 0xFFFFFFFFU */
uint32_t MatchMode; /*!< Specifies the method used for determining a match.
This parameter can be a value of @ref XSPI_MatchMode */
uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match.
This parameter can be a value of @ref XSPI_AutomaticStop */
uint32_t IntervalTime; /*!< Specifies the number of clock cycles between two read during automatic
polling phases.
This parameter can be any value between 0 and 0xFFFF */
} XSPI_AutoPollingTypeDef;
/**
* @brief HAL XSPI Memory Mapped mode configuration structure definition
*/
typedef struct
{
uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select.
This parameter can be a value of @ref XSPI_TimeOutActivation */
uint32_t TimeoutPeriodClock; /*!< Specifies the number of clock to wait when the FIFO is full before to
release the chip select.
This parameter can be any value between 0 and 0xFFFF */
} XSPI_MemoryMappedTypeDef;
/**
* @brief HAL XSPI IO Manager Configuration structure definition
*/
typedef struct
{
uint32_t ClkPort; /*!< It indicates which port of the XSPI IO Manager is used for the CLK pins.
This parameter can be a value between 1 and 8 */
uint32_t DQSPort; /*!< It indicates which port of the XSPI IO Manager is used for the DQS pin.
This parameter can be a value between 1 and 8,
0 means that signal not used */
uint32_t NCSPort; /*!< It indicates which port of the XSPI IO Manager is used for the NCS pin.
This parameter can be a value between 1 and 8 */
uint32_t IOLowPort; /*!< It indicates which port of the XSPI IO Manager is used for the IO[3:0] pins.
This parameter can be a value of @ref XSPIM_IOPort */
uint32_t IOHighPort; /*!< It indicates which port of the XSPI IO Manager is used for the IO[7:4] pins.
This parameter can be a value of @ref XSPIM_IOPort */
uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles)
expected if some signals are multiplexed in the XSPI IO Manager with the
other XSPI.
This parameter can be a value between 1 and 256 */
} XSPIM_CfgTypeDef;
#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
/**
* @brief HAL XSPI Callback ID enumeration definition
*/
typedef enum
{
HAL_XSPI_ERROR_CB_ID = 0x00U, /*!< XSPI Error Callback ID */
HAL_XSPI_ABORT_CB_ID = 0x01U, /*!< XSPI Abort Callback ID */
HAL_XSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< XSPI FIFO Threshold Callback ID */
HAL_XSPI_CMD_CPLT_CB_ID = 0x03U, /*!< XSPI Command Complete Callback ID */
HAL_XSPI_RX_CPLT_CB_ID = 0x04U, /*!< XSPI Rx Complete Callback ID */
HAL_XSPI_TX_CPLT_CB_ID = 0x05U, /*!< XSPI Tx Complete Callback ID */
HAL_XSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< XSPI Rx Half Complete Callback ID */
HAL_XSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< XSPI Tx Half Complete Callback ID */
HAL_XSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< XSPI Status Match Callback ID */
HAL_XSPI_TIMEOUT_CB_ID = 0x09U, /*!< XSPI Timeout Callback ID */
HAL_XSPI_MSP_INIT_CB_ID = 0x0AU, /*!< XSPI MspInit Callback ID */
HAL_XSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< XSPI MspDeInit Callback ID */
} HAL_XSPI_CallbackIDTypeDef;
/**
* @brief HAL XSPI Callback pointer definition
*/
typedef void (*pXSPI_CallbackTypeDef)(XSPI_HandleTypeDef *hxspi);
#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
/**
* @brief HAL XSPI High-speed interface calibration structure definition
*/
typedef struct
{
uint32_t DelayValueType; /*!< It indicates which calibration is concerned by the configuration.
This parameter can be a value of @ref XSPI_DelayType */
uint32_t FineCalibrationUnit; /*!< It indicates the fine calibration value of the delay.
This parameter can be a value between 0 and 0x7F */
uint32_t CoarseCalibrationUnit; /*!< It indicates the coarse calibration value of the delay.
This parameter can be a value between 0 and 0x1F */
uint32_t MaxCalibration; /*!< It indicates that the calibration is outside the range of DLL master.
It applies only when the DelayValueType is HAL_XSPI_CAL_FULL_CYCLE_DELAY.
This parameter can be a value of @ref XSPI_MaxCal */
} XSPI_HSCalTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup XSPI_Exported_Constants XSPI Exported Constants
* @{
*/
/** @defgroup XSPI_State XSPI State
* @{
*/
#define HAL_XSPI_STATE_RESET (0x00000000U) /*!< Initial state */
#define HAL_XSPI_STATE_READY (0x00000002U) /*!< Driver ready to be used */
#define HAL_XSPI_STATE_HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */
#define HAL_XSPI_STATE_CMD_CFG (0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */
#define HAL_XSPI_STATE_READ_CMD_CFG (0x00000014U) /*!< Read command configuration done, not the write command configuration */
#define HAL_XSPI_STATE_WRITE_CMD_CFG (0x00000024U) /*!< Write command configuration done, not the read command configuration */
#define HAL_XSPI_STATE_BUSY_CMD (0x00000008U) /*!< Command without data on-going */
#define HAL_XSPI_STATE_BUSY_TX (0x00000018U) /*!< Indirect Tx on-going */
#define HAL_XSPI_STATE_BUSY_RX (0x00000028U) /*!< Indirect Rx on-going */
#define HAL_XSPI_STATE_BUSY_AUTO_POLLING (0x00000048U) /*!< Auto-polling on-going */
#define HAL_XSPI_STATE_BUSY_MEM_MAPPED (0x00000088U) /*!< Memory-mapped on-going */
#define HAL_XSPI_STATE_ABORT (0x00000100U) /*!< Abort on-going */
#define HAL_XSPI_STATE_ERROR (0x00000200U) /*!< Blocking error, driver should be re-initialized */
/**
* @}
*/
/** @defgroup XSPI_ErrorCode XSPI Error Code
* @{
*/
#define HAL_XSPI_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_XSPI_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
#define HAL_XSPI_ERROR_TRANSFER (0x00000002U) /*!< Transfer error */
#define HAL_XSPI_ERROR_DMA (0x00000004U) /*!< DMA transfer error */
#define HAL_XSPI_ERROR_INVALID_PARAM (0x00000008U) /*!< Invalid parameters error */
#define HAL_XSPI_ERROR_INVALID_SEQUENCE (0x00000010U) /*!< Sequence is incorrect */
#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
#define HAL_XSPI_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid callback error */
#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
/**
* @}
*/
/** @defgroup XSPI_MemoryMode XSPI Memory Mode
* @{
*/
#define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */
#define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */
/**
* @}
*/
/** @defgroup XSPI_MemoryType XSPI Memory Type
* @{
*/
#define HAL_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */
#define HAL_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */
#define HAL_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */
#define HAL_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/
#define HAL_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
#define HAL_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */
/**
* @}
*/
/** @defgroup XSPI_MemorySize XSPI Memory Size
* @{
*/
#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Byte = 2^( 0+1)) */
#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Byte = 2^( 1+1)) */
#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Byte = 2^( 2+1)) */
#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Byte = 2^( 3+1)) */
#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Byte = 2^( 4+1)) */
#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Byte = 2^( 5+1)) */
#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Byte = 2^( 6+1)) */
#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Byte = 2^( 7+1)) */
#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Byte = 2^( 8+1)) */
#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KByte = 2^( 9+1)) */
#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KByte = 2^(10+1)) */
#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KByte = 2^(11+1)) */
#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KByte = 2^(12+1)) */
#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */
#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */
#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */
#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KByte = 2^(16+1)) */
#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KByte = 2^(17+1)) */
#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KByte = 2^(18+1)) */
#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MByte = 2^(19+1)) */
#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MByte = 2^(20+1)) */
#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MByte = 2^(21+1)) */
#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MByte = 2^(22+1)) */
#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */
#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */
#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */
#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MByte = 2^(26+1)) */
#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MByte = 2^(27+1)) */
#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (256 MByte = 2^(28+1)) */
#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits (256 MByte = 2^(29+1)) */
#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits (256 MByte = 2^(30+1)) */
#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits (256 MByte = 2^(31+1)) */
/**
* @}
*/
/** @defgroup XSPI_FreeRunningClock XSPI Free Running Clock
* @{
*/
#define HAL_XSPI_FREERUNCLK_DISABLE (0x00000000U) /*!< CLK is not free running */
#define HAL_XSPI_FREERUNCLK_ENABLE ((uint32_t)XSPI_DCR1_FRCK) /*!< CLK is always provided (running) */
/**
* @}
*/
/** @defgroup XSPI_ClockMode XSPI Clock Mode
* @{
*/
#define HAL_XSPI_CLOCK_MODE_0 (0x00000000U) /*!< CLK must stay low while nCS is high */
#define HAL_XSPI_CLOCK_MODE_3 ((uint32_t)XSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */
/**
* @}
*/
/** @defgroup XSPI_WrapSize XSPI Wrap-Size
* @{
*/
#define HAL_XSPI_WRAP_NOT_SUPPORTED (0x00000000U) /*!< wrapped reads are not supported by the memory */
#define HAL_XSPI_WRAP_16_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */
#define HAL_XSPI_WRAP_32_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */
#define HAL_XSPI_WRAP_64_BYTES ((uint32_t)XSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */
#define HAL_XSPI_WRAP_128_BYTES ((uint32_t)(XSPI_DCR2_WRAPSIZE_0 | XSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */
/**
* @}
*/
/** @defgroup XSPI_SampleShifting XSPI Sample Shifting
* @{
*/
#define HAL_XSPI_SAMPLE_SHIFT_NONE (0x00000000U) /*!< No shift */
#define HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE ((uint32_t)XSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */
/**
* @}
*/
/** @defgroup XSPI_DelayHoldQuarterCycle XSPI Delay Hold Quarter Cycle
* @{
*/
#define HAL_XSPI_DHQC_DISABLE (0x00000000U) /*!< No Delay */
#define HAL_XSPI_DHQC_ENABLE ((uint32_t)XSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */
/**
* @}
*/
/** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary
* @{
*/
#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */
#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Byte = 2^(1)) */
#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Byte = 2^(2)) */
#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Byte = 2^(3)) */
#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Byte = 2^(4)) */
#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Byte = 2^(5)) */
#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Byte = 2^(6)) */
#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Byte = 2^(7)) */
#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Byte = 2^(8)) */
#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Byte = 2^(9)) */
#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KByte = 2^(10)) */
#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KByte = 2^(11)) */
#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KByte = 2^(12)) */
#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KByte = 2^(13)) */
#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KByte = 2^(14)) */
#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KByte = 2^(15)) */
#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KByte = 2^(16)) */
#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KByte = 2^(17)) */
#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KByte = 2^(18)) */
#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KByte = 2^(19)) */
#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MByte = 2^(20)) */
#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MByte = 2^(21)) */
#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MByte = 2^(22)) */
#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MByte = 2^(23)) */
#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MByte = 2^(24)) */
#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MByte = 2^(25)) */
#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MByte = 2^(26)) */
#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MByte = 2^(27)) */
#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MByte = 2^(28)) */
#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MByte = 2^(29)) */
#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GByte = 2^(30)) */
#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GByte = 2^(31)) */
/**
* @}
*/
/** @defgroup XSPI_DelayBlockBypass XSPI Delay Block Bypaas
* @{
*/
#define HAL_XSPI_DELAY_BLOCK_ON (0x00000000U) /*!< Sampling clock is delayed by the delay block */
#define HAL_XSPI_DELAY_BLOCK_BYPASS ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */
/**
* @}
*/
/** @defgroup XSPI_OperationType XSPI Operation Type
* @{
*/
#define HAL_XSPI_OPTYPE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */
#define HAL_XSPI_OPTYPE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */
#define HAL_XSPI_OPTYPE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */
#define HAL_XSPI_OPTYPE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */
/**
* @}
*/
/** @defgroup XSPI_IOSelect XSPI IO Select
* @{
*/
#define HAL_XSPI_SELECT_IO_3_0 (0x00000000U) /*!< Data exchanged over IO[3:0] */
#if defined (HSPI_CR_MSEL)
#define HAL_XSPI_SELECT_IO_7_4 ((uint32_t)HSPI_CR_MSEL_0 | OCTOSPI_CR_MSEL) /*!< Data exchanged over IO[7:4] */
#define HAL_XSPI_SELECT_IO_11_8 ((uint32_t)HSPI_CR_MSEL_1) /*!< Data exchanged over IO[11:8] */
#define HAL_XSPI_SELECT_IO_15_12 ((uint32_t)HSPI_CR_MSEL | OCTOSPI_CR_MSEL) /*!< Data exchanged over IO[15:12] */
#define HAL_XSPI_SELECT_IO_7_0 (0x00000000U) /*!< Data exchanged over IO[7:0] */
#define HAL_XSPI_SELECT_IO_15_8 ((uint32_t)HSPI_CR_MSEL_1) /*!< Data exchanged over IO[15:8] */
#else
#define HAL_XSPI_SELECT_IO_7_4 ((uint32_t)OCTOSPI_CR_MSEL) /*!< Data exchanged over IO[7:4] */
#define HAL_XSPI_SELECT_IO_7_0 (0x00000000U) /*!< Data exchanged over IO[7:0] */
#endif /* 16BITS_AVAILABILITY */
/**
* @}
*/
/** @defgroup XSPI_InstructionMode XSPI Instruction Mode
* @{
*/
#define HAL_XSPI_INSTRUCTION_NONE (0x00000000U) /*!< No instruction */
#define HAL_XSPI_INSTRUCTION_1_LINE ((uint32_t)XSPI_CCR_IMODE_0) /*!< Instruction on a single line */
#define HAL_XSPI_INSTRUCTION_2_LINES ((uint32_t)XSPI_CCR_IMODE_1) /*!< Instruction on two lines */
#define HAL_XSPI_INSTRUCTION_4_LINES ((uint32_t)(XSPI_CCR_IMODE_0 | XSPI_CCR_IMODE_1)) /*!< Instruction on four lines */
#define HAL_XSPI_INSTRUCTION_8_LINES ((uint32_t)XSPI_CCR_IMODE_2) /*!< Instruction on eight lines */
/**
* @}
*/
/** @defgroup XSPI_InstructionWidth XSPI Instruction Width
* @{
*/
#define HAL_XSPI_INSTRUCTION_8_BITS (0x00000000U) /*!< 8-bit instruction */
#define HAL_XSPI_INSTRUCTION_16_BITS ((uint32_t)XSPI_CCR_ISIZE_0) /*!< 16-bit instruction */
#define HAL_XSPI_INSTRUCTION_24_BITS ((uint32_t)XSPI_CCR_ISIZE_1) /*!< 24-bit instruction */
#define HAL_XSPI_INSTRUCTION_32_BITS ((uint32_t)XSPI_CCR_ISIZE) /*!< 32-bit instruction */
/**
* @}
*/
/** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode
* @{
*/
#define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for instruction phase */
#define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */
/**
* @}
*/
/** @defgroup XSPI_AddressMode XSPI Address Mode
* @{
*/
#define HAL_XSPI_ADDRESS_NONE (0x00000000U) /*!< No address */
#define HAL_XSPI_ADDRESS_1_LINE ((uint32_t)XSPI_CCR_ADMODE_0) /*!< Address on a single line */
#define HAL_XSPI_ADDRESS_2_LINES ((uint32_t)XSPI_CCR_ADMODE_1) /*!< Address on two lines */
#define HAL_XSPI_ADDRESS_4_LINES ((uint32_t)(XSPI_CCR_ADMODE_0 | XSPI_CCR_ADMODE_1)) /*!< Address on four lines */
#define HAL_XSPI_ADDRESS_8_LINES ((uint32_t)XSPI_CCR_ADMODE_2) /*!< Address on eight lines */
/**
* @}
*/
/** @defgroup XSPI_AddressWidth XSPI Address width
* @{
*/
#define HAL_XSPI_ADDRESS_8_BITS (0x00000000U) /*!< 8-bit address */
#define HAL_XSPI_ADDRESS_16_BITS ((uint32_t)XSPI_CCR_ADSIZE_0) /*!< 16-bit address */
#define HAL_XSPI_ADDRESS_24_BITS ((uint32_t)XSPI_CCR_ADSIZE_1) /*!< 24-bit address */
#define HAL_XSPI_ADDRESS_32_BITS ((uint32_t)XSPI_CCR_ADSIZE) /*!< 32-bit address */
/**
* @}
*/
/** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode
* @{
*/
#define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for address phase */
#define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */
/**
* @}
*/
/** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode
* @{
*/
#define HAL_XSPI_ALT_BYTES_NONE (0x00000000U) /*!< No alternate bytes */
#define HAL_XSPI_ALT_BYTES_1_LINE ((uint32_t)XSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */
#define HAL_XSPI_ALT_BYTES_2_LINES ((uint32_t)XSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */
#define HAL_XSPI_ALT_BYTES_4_LINES ((uint32_t)(XSPI_CCR_ABMODE_0 | XSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */
#define HAL_XSPI_ALT_BYTES_8_LINES ((uint32_t)XSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */
/**
* @}
*/
/** @defgroup XSPI_AlternateBytesWidth XSPI Alternate Bytes Width
* @{
*/
#define HAL_XSPI_ALT_BYTES_8_BITS (0x00000000U) /*!< 8-bit alternate bytes */
#define HAL_XSPI_ALT_BYTES_16_BITS ((uint32_t)XSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */
#define HAL_XSPI_ALT_BYTES_24_BITS ((uint32_t)XSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */
#define HAL_XSPI_ALT_BYTES_32_BITS ((uint32_t)XSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */
/**
* @}
*/
/** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode
* @{
*/
#define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for alternate bytes phase */
#define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */
/**
* @}
*/
/** @defgroup XSPI_DataMode XSPI Data Mode
* @{
*/
#define HAL_XSPI_DATA_NONE (0x00000000U) /*!< No data */
#define HAL_XSPI_DATA_1_LINE ((uint32_t)XSPI_CCR_DMODE_0) /*!< Data on a single line */
#define HAL_XSPI_DATA_2_LINES ((uint32_t)XSPI_CCR_DMODE_1) /*!< Data on two lines */
#define HAL_XSPI_DATA_4_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_1)) /*!< Data on four lines */
#define HAL_XSPI_DATA_8_LINES ((uint32_t)XSPI_CCR_DMODE_2) /*!< Data on eight lines */
#if defined (HSPI_CR_MSEL)
#define HAL_XSPI_DATA_16_LINES ((uint32_t)(XSPI_CCR_DMODE_0 | XSPI_CCR_DMODE_2)) /*!< Data on sixteen lines valid for HSPI only */
#endif /* 16BITS_AVAILABILITY */
/**
* @}
*/
/** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode
* @{
*/
#define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for data phase */
#define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */
/**
* @}
*/
/** @defgroup XSPI_DQSMode XSPI DQS Mode
* @{
*/
#define HAL_XSPI_DQS_DISABLE (0x00000000U) /*!< DQS disabled */
#define HAL_XSPI_DQS_ENABLE ((uint32_t)XSPI_CCR_DQSE) /*!< DQS enabled */
/**
* @}
*/
/** @defgroup XSPI_SIOOMode XSPI SIOO Mode
* @{
*/
#define HAL_XSPI_SIOO_INST_EVERY_CMD (0x00000000U) /*!< Send instruction on every transaction */
#define HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)XSPI_CCR_SIOO) /*!< Send instruction only for the first command */
/**
* @}
*/
/** @defgroup XSPI_WriteZeroLatency XSPI Hyperbus Write Zero Latency Activation
* @{
*/
#define HAL_XSPI_LATENCY_ON_WRITE (0x00000000U) /*!< Latency on write accesses */
#define HAL_XSPI_NO_LATENCY_ON_WRITE ((uint32_t)XSPI_HLCR_WZL) /*!< No latency on write accesses */
/**
* @}
*/
/** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode
* @{
*/
#define HAL_XSPI_VARIABLE_LATENCY (0x00000000U) /*!< Variable initial latency */
#define HAL_XSPI_FIXED_LATENCY ((uint32_t)XSPI_HLCR_LM) /*!< Fixed latency */
/**
* @}
*/
/** @defgroup XSPI_AddressSpace XSPI Hyperbus Address Space
* @{
*/
#define HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */
#define HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
/**
* @}
*/
/** @defgroup XSPI_MatchMode XSPI Match Mode
* @{
*/
#define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between unmasked bits */
#define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between unmasked bits */
/**
* @}
*/
/** @defgroup XSPI_AutomaticStop XSPI Automatic Stop
* @{
*/
#define HAL_XSPI_AUTOMATIC_STOP_DISABLE (0x00000000U) /*!< AutoPolling stops only with abort or XSPI disabling */
#define HAL_XSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)XSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */
/**
* @}
*/
/** @defgroup XSPI_TimeOutActivation XSPI Timeout Activation
* @{
*/
#define HAL_XSPI_TIMEOUT_COUNTER_DISABLE (0x00000000U) /*!< Timeout counter disabled, nCS remains active */
#define HAL_XSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)XSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */
/**
* @}
*/
/** @defgroup XSPI_Flags XSPI Flags
* @{
*/
#define HAL_XSPI_FLAG_BUSY XSPI_SR_BUSY /*!< Busy flag: operation is ongoing */
#define HAL_XSPI_FLAG_TO XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */
#define HAL_XSPI_FLAG_SM XSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */
#define HAL_XSPI_FLAG_FT XSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */
#define HAL_XSPI_FLAG_TC XSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */
#define HAL_XSPI_FLAG_TE XSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */
/**
* @}
*/
/** @defgroup XSPI_Interrupts XSPI Interrupts
* @{
*/
#define HAL_XSPI_IT_TO XSPI_CR_TOIE /*!< Interrupt on the timeout flag */
#define HAL_XSPI_IT_SM XSPI_CR_SMIE /*!< Interrupt on the status match flag */
#define HAL_XSPI_IT_FT XSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */
#define HAL_XSPI_IT_TC XSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */
#define HAL_XSPI_IT_TE XSPI_CR_TEIE /*!< Interrupt on the transfer error flag */
/**
* @}
*/
/** @defgroup XSPI_Timeout_definition XSPI Timeout definition
* @{
*/
#define HAL_XSPI_TIMEOUT_DEFAULT_VALUE (5000U) /* 5 s */
/**
* @}
*/
/** @defgroup XSPIM_IOPort XSPI IO Manager IO Port
* @{
*/
#define HAL_XSPIM_IOPORT_NONE (0x00000000U) /*!< IOs not used */
#define HAL_XSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */
#define HAL_XSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */
#define HAL_XSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */
#define HAL_XSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */
#define HAL_XSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U)) /*!< Port 3 - IO[3:0] */
#define HAL_XSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U)) /*!< Port 3 - IO[7:4] */
#define HAL_XSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U)) /*!< Port 4 - IO[3:0] */
#define HAL_XSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U)) /*!< Port 4 - IO[7:4] */
#define HAL_XSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U)) /*!< Port 5 - IO[3:0] */
#define HAL_XSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U)) /*!< Port 5 - IO[7:4] */
#define HAL_XSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U)) /*!< Port 6 - IO[3:0] */
#define HAL_XSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U)) /*!< Port 6 - IO[7:4] */
#define HAL_XSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U)) /*!< Port 7 - IO[3:0] */
#define HAL_XSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U)) /*!< Port 7 - IO[7:4] */
#define HAL_XSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U)) /*!< Port 8 - IO[3:0] */
#define HAL_XSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U)) /*!< Port 8 - IO[7:4] */
/**
* @}
*/
/** @defgroup XSPI_DelayType XSPI Calibration Delay Type
* @{
*/
#define HAL_XSPI_CAL_FULL_CYCLE_DELAY (0x00000000U) /*!< Delay value equivalent to full memory-clock cycle */
#define HAL_XSPI_CAL_FEEDBACK_CLK_DELAY (0x00000001U) /*!< Delay value for the feedback clock when reading without DQS */
#define HAL_XSPI_CAL_DATA_OUTPUT_DELAY (0x00000002U) /*!< Delay value for output data in DDR mode for write operations */
#define HAL_XSPI_CAL_DQS_INPUT_DELAY (0x00000003U) /*!< Delay value for DQS input when sampling data for read operations */
/**
* @}
*/
/** @defgroup XSPI_MaxCal XSPI Calibration Maximal Value
* @{
*/
#define HAL_XSPI_MAXCAL_NOT_REACHED (0x00000000U) /*!< Memory-clock perido inside the range of DLL master */
#define HAL_XSPI_MAXCAL_REACHED ((uint32_t)HSPI_CALFCR_CALMAX) /*!< Memory-clock period outside the range of DLL master (max delay values used) */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup XSPI_Exported_Macros XSPI Exported Macros
* @{
*/
/** @brief Reset XSPI handle state.
* @param __HANDLE__ specifies the XSPI Handle.
* @retval None
*/
#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
#define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_XSPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define HAL_XSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_XSPI_STATE_RESET)
#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
/** @brief Enable the XSPI peripheral.
* @param __HANDLE__ specifies the XSPI Handle.
* @retval None
*/
#define HAL_XSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN)
/** @brief Disable the XSPI peripheral.
* @param __HANDLE__ specifies the XSPI Handle.
* @retval None
*/
#define HAL_XSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, XSPI_CR_EN)
/** @brief Enable the specified XSPI interrupt.
* @param __HANDLE__ specifies the XSPI Handle.
* @param __INTERRUPT__ specifies the XSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt
* @arg HAL_XSPI_IT_SM: XSPI Status match interrupt
* @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt
* @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt
* @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt
* @retval None
*/
#define HAL_XSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Disable the specified XSPI interrupt.
* @param __HANDLE__ specifies the XSPI Handle.
* @param __INTERRUPT__ specifies the XSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt
* @arg HAL_XSPI_IT_SM: XSPI Status match interrupt
* @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt
* @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt
* @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt
* @retval None
*/
#define HAL_XSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified XSPI interrupt source is enabled or not.
* @param __HANDLE__ specifies the XSPI Handle.
* @param __INTERRUPT__ specifies the XSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg HAL_XSPI_IT_TO: XSPI Timeout interrupt
* @arg HAL_XSPI_IT_SM: XSPI Status match interrupt
* @arg HAL_XSPI_IT_FT: XSPI FIFO threshold interrupt
* @arg HAL_XSPI_IT_TC: XSPI Transfer complete interrupt
* @arg HAL_XSPI_IT_TE: XSPI Transfer error interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define HAL_XSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\
== (__INTERRUPT__))
/**
* @brief Check whether the selected XSPI flag is set or not.
* @param __HANDLE__ specifies the XSPI Handle.
* @param __FLAG__ specifies the XSPI flag to check.
* This parameter can be one of the following values:
* @arg HAL_XSPI_FLAG_BUSY: XSPI Busy flag
* @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag
* @arg HAL_XSPI_FLAG_SM: XSPI Status match flag
* @arg HAL_XSPI_FLAG_FT: XSPI FIFO threshold flag
* @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag
* @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag
* @retval None
*/
#define HAL_XSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \
!= 0U) ? SET : RESET)
/** @brief Clears the specified XSPI's flag status.
* @param __HANDLE__ specifies the XSPI Handle.
* @param __FLAG__ specifies the XSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg HAL_XSPI_FLAG_TO: XSPI Timeout flag
* @arg HAL_XSPI_FLAG_SM: XSPI Status match flag
* @arg HAL_XSPI_FLAG_TC: XSPI Transfer complete flag
* @arg HAL_XSPI_FLAG_TE: XSPI Transfer error flag
* @retval None
*/
#define HAL_XSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup XSPI_Exported_Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
/** @addtogroup XSPI_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi);
void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi);
HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi);
void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi);
/**
* @}
*/
/* IO operation functions *****************************************************/
/** @addtogroup XSPI_Exported_Functions_Group2
* @{
*/
/* XSPI IRQ handler function */
void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi);
/* XSPI command configuration functions */
HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd,
uint32_t Timeout);
HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd);
HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg,
uint32_t Timeout);
HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd,
uint32_t Timeout);
/* XSPI indirect mode functions */
HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData);
HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData);
HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData);
HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData);
/* XSPI status flag polling mode functions */
HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg,
uint32_t Timeout);
HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg);
/* XSPI memory-mapped mode functions */
HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg);
/* Callback functions in non-blocking modes ***********************************/
void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi);
void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi);
void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi);
/* XSPI indirect mode Callback functions */
void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi);
void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi);
void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi);
void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi);
void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi);
/* XSPI status flag polling mode functions */
void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi);
/* XSPI memory-mapped mode functions */
void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi);
#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U)
/* XSPI callback registering/unregistering */
HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID,
pXSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef CallbackID);
#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */
/**
* @}
*/
/* Peripheral Control and State functions ************************************/
/** @addtogroup XSPI_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi);
HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi);
HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold);
uint32_t HAL_XSPI_GetFifoThreshold(XSPI_HandleTypeDef *hxspi);
HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout);
uint32_t HAL_XSPI_GetError(XSPI_HandleTypeDef *hxspi);
uint32_t HAL_XSPI_GetState(XSPI_HandleTypeDef *hxspi);
/**
* @}
*/
/* XSPI IO Manager configuration function ************************************/
/** @addtogroup XSPI_Exported_Functions_Group4
* @{
*/
HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout);
/**
* @}
*/
/* XSPI Delay Block functions ************************************/
/** @addtogroup XSPI_Exported_Functions_Group5 Delay Block function
* @{
*/
HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg);
HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg);
HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi,
HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg);
/**
* @}
*/
/* XSPI high-speed interface and calibration functions ***********************/
/** @addtogroup XSPI_Exported_Functions_Group6
* @{
*/
HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg);
HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/**
@cond 0
*/
#define IS_OCTOSPI_FIFO_THRESHOLD_BYTE(THRESHOLD) (((THRESHOLD) >= 1U) &&\
((THRESHOLD) <= ((OCTOSPI_CR_FTHRES >> OCTOSPI_CR_FTHRES_Pos)+1U)))
#define IS_HSPI_FIFO_THRESHOLD_BYTE(THRESHOLD) (((THRESHOLD) >= 1U)\
&& ((THRESHOLD) <= ((HSPI_CR_FTHRES >> HSPI_CR_FTHRES_Pos)+1U)))
#define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \
((MODE) == HAL_XSPI_DUAL_MEM))
#define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \
((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \
((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \
((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \
((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \
((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS))
#define IS_XSPI_MEMORY_SIZE(SIZE) (((SIZE) == HAL_XSPI_SIZE_16B) || \
((SIZE) == HAL_XSPI_SIZE_32B) || \
((SIZE) == HAL_XSPI_SIZE_64B) || \
((SIZE) == HAL_XSPI_SIZE_128B) || \
((SIZE) == HAL_XSPI_SIZE_256B) || \
((SIZE) == HAL_XSPI_SIZE_512B) || \
((SIZE) == HAL_XSPI_SIZE_1KB) || \
((SIZE) == HAL_XSPI_SIZE_2KB) || \
((SIZE) == HAL_XSPI_SIZE_4KB) || \
((SIZE) == HAL_XSPI_SIZE_8KB) || \
((SIZE) == HAL_XSPI_SIZE_16KB) || \
((SIZE) == HAL_XSPI_SIZE_32KB) || \
((SIZE) == HAL_XSPI_SIZE_64KB) || \
((SIZE) == HAL_XSPI_SIZE_128KB) || \
((SIZE) == HAL_XSPI_SIZE_256KB) || \
((SIZE) == HAL_XSPI_SIZE_512KB) || \
((SIZE) == HAL_XSPI_SIZE_1MB) || \
((SIZE) == HAL_XSPI_SIZE_2MB) || \
((SIZE) == HAL_XSPI_SIZE_4MB) || \
((SIZE) == HAL_XSPI_SIZE_8MB) || \
((SIZE) == HAL_XSPI_SIZE_16MB) || \
((SIZE) == HAL_XSPI_SIZE_32MB) || \
((SIZE) == HAL_XSPI_SIZE_64MB) || \
((SIZE) == HAL_XSPI_SIZE_128MB) || \
((SIZE) == HAL_XSPI_SIZE_256MB) || \
((SIZE) == HAL_XSPI_SIZE_512MB) || \
((SIZE) == HAL_XSPI_SIZE_1GB) || \
((SIZE) == HAL_XSPI_SIZE_2GB) || \
((SIZE) == HAL_XSPI_SIZE_4GB) || \
((SIZE) == HAL_XSPI_SIZE_8GB) || \
((SIZE) == HAL_XSPI_SIZE_16GB) || \
((SIZE) == HAL_XSPI_SIZE_32GB))
#define IS_XSPI_CS_HIGH_TIME_CYCLE(TIME) (((TIME) >= 1U) && ((TIME) <= 64U))
#define IS_XSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_XSPI_FREERUNCLK_DISABLE) || \
((CLK) == HAL_XSPI_FREERUNCLK_ENABLE))
#define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \
((MODE) == HAL_XSPI_CLOCK_MODE_3))
#define IS_XSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_XSPI_WRAP_NOT_SUPPORTED) || \
((SIZE) == HAL_XSPI_WRAP_16_BYTES) || \
((SIZE) == HAL_XSPI_WRAP_32_BYTES) || \
((SIZE) == HAL_XSPI_WRAP_64_BYTES) || \
((SIZE) == HAL_XSPI_WRAP_128_BYTES))
#define IS_XSPI_CLK_PRESCALER(PRESCALER) ((PRESCALER) <= 255U)
#define IS_XSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_NONE) || \
((CYCLE) == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE))
#define IS_XSPI_DHQC(CYCLE) (((CYCLE) == HAL_XSPI_DHQC_DISABLE) || \
((CYCLE) == HAL_XSPI_DHQC_ENABLE))
#define IS_XSPI_CS_BOUND(SIZE) (((SIZE) == HAL_XSPI_BONDARYOF_NONE) || \
((SIZE) == HAL_XSPI_BONDARYOF_16B) || \
((SIZE) == HAL_XSPI_BONDARYOF_32B) || \
((SIZE) == HAL_XSPI_BONDARYOF_64B) || \
((SIZE) == HAL_XSPI_BONDARYOF_128B) || \
((SIZE) == HAL_XSPI_BONDARYOF_256B) || \
((SIZE) == HAL_XSPI_BONDARYOF_512B) || \
((SIZE) == HAL_XSPI_BONDARYOF_1KB) || \
((SIZE) == HAL_XSPI_BONDARYOF_2KB) || \
((SIZE) == HAL_XSPI_BONDARYOF_4KB) || \
((SIZE) == HAL_XSPI_BONDARYOF_8KB) || \
((SIZE) == HAL_XSPI_BONDARYOF_16KB) || \
((SIZE) == HAL_XSPI_BONDARYOF_32KB) || \
((SIZE) == HAL_XSPI_BONDARYOF_64KB) || \
((SIZE) == HAL_XSPI_BONDARYOF_128KB) || \
((SIZE) == HAL_XSPI_BONDARYOF_256KB) || \
((SIZE) == HAL_XSPI_BONDARYOF_512KB) || \
((SIZE) == HAL_XSPI_BONDARYOF_1MB) || \
((SIZE) == HAL_XSPI_BONDARYOF_2MB) || \
((SIZE) == HAL_XSPI_BONDARYOF_4MB) || \
((SIZE) == HAL_XSPI_BONDARYOF_8MB) || \
((SIZE) == HAL_XSPI_BONDARYOF_16MB) || \
((SIZE) == HAL_XSPI_BONDARYOF_32MB) || \
((SIZE) == HAL_XSPI_BONDARYOF_64MB) || \
((SIZE) == HAL_XSPI_BONDARYOF_128MB) || \
((SIZE) == HAL_XSPI_BONDARYOF_256MB) || \
((SIZE) == HAL_XSPI_BONDARYOF_512MB) || \
((SIZE) == HAL_XSPI_BONDARYOF_1GB) || \
((SIZE) == HAL_XSPI_BONDARYOF_2GB) || \
((SIZE) == HAL_XSPI_BONDARYOF_4GB) || \
((SIZE) == HAL_XSPI_BONDARYOF_8GB) || \
((SIZE) == HAL_XSPI_BONDARYOF_16GB))
#define IS_XSPI_DLYB_BYPASS(DLYB) (((DLYB) == HAL_XSPI_DELAY_BLOCK_ON) || \
((DLYB) == HAL_XSPI_DELAY_BLOCK_BYPASS))
#define IS_XSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U)
#define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \
((TYPE) == HAL_XSPI_OPTYPE_READ_CFG) || \
((TYPE) == HAL_XSPI_OPTYPE_WRITE_CFG) || \
((TYPE) == HAL_XSPI_OPTYPE_WRAP_CFG))
#define IS_OCTOSPI_IO_SELECT(MEMSEL) (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0) || \
((MEMSEL) == HAL_XSPI_SELECT_IO_7_4) || \
((MEMSEL) == HAL_XSPI_SELECT_IO_7_0))
#define IS_HSPI_IO_SELECT(MEMSEL) (((MEMSEL) == HAL_XSPI_SELECT_IO_3_0) || \
((MEMSEL) == HAL_XSPI_SELECT_IO_7_4) || \
((MEMSEL) == HAL_XSPI_SELECT_IO_11_8) || \
((MEMSEL) == HAL_XSPI_SELECT_IO_15_12) || \
((MEMSEL) == HAL_XSPI_SELECT_IO_7_0) || \
((MEMSEL) == HAL_XSPI_SELECT_IO_15_8))
#define IS_XSPI_INSTRUCTION(OPCODE) ((OPCODE) <= 0xFFFFFFFFU)
#define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \
((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \
((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \
((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \
((MODE) == HAL_XSPI_INSTRUCTION_8_LINES))
#define IS_XSPI_INSTRUCTION_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_INSTRUCTION_8_BITS) || \
((WIDTH) == HAL_XSPI_INSTRUCTION_16_BITS) || \
((WIDTH) == HAL_XSPI_INSTRUCTION_24_BITS) || \
((WIDTH) == HAL_XSPI_INSTRUCTION_32_BITS))
#define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \
((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE))
#define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \
((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \
((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \
((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \
((MODE) == HAL_XSPI_ADDRESS_8_LINES))
#define IS_XSPI_ADDRESS_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ADDRESS_8_BITS) || \
((WIDTH) == HAL_XSPI_ADDRESS_16_BITS) || \
((WIDTH) == HAL_XSPI_ADDRESS_24_BITS) || \
((WIDTH) == HAL_XSPI_ADDRESS_32_BITS))
#define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \
((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE))
#define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \
((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \
((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \
((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \
((MODE) == HAL_XSPI_ALT_BYTES_8_LINES))
#define IS_XSPI_ALT_BYTES_WIDTH(WIDTH) (((WIDTH) == HAL_XSPI_ALT_BYTES_8_BITS) || \
((WIDTH) == HAL_XSPI_ALT_BYTES_16_BITS) || \
((WIDTH) == HAL_XSPI_ALT_BYTES_24_BITS) || \
((WIDTH) == HAL_XSPI_ALT_BYTES_32_BITS))
#define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \
((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE))
#define IS_OCTOSPI_DATA_MODE(MODE) (((MODE) == HAL_XSPI_DATA_NONE) || \
((MODE) == HAL_XSPI_DATA_1_LINE) || \
((MODE) == HAL_XSPI_DATA_2_LINES) || \
((MODE) == HAL_XSPI_DATA_4_LINES) || \
((MODE) == HAL_XSPI_DATA_8_LINES))
#define IS_HSPI_DATA_MODE(MODE) (((MODE) == HAL_XSPI_DATA_NONE) || \
((MODE) == HAL_XSPI_DATA_1_LINE) || \
((MODE) == HAL_XSPI_DATA_2_LINES) || \
((MODE) == HAL_XSPI_DATA_4_LINES) || \
((MODE) == HAL_XSPI_DATA_8_LINES) || \
((MODE) == HAL_XSPI_DATA_16_LINES))
#define IS_XSPI_DATA_LENGTH(NUMBER) ((NUMBER) >= 1U)
#define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \
((MODE) == HAL_XSPI_DATA_DTR_ENABLE))
#define IS_XSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U)
#define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \
((MODE) == HAL_XSPI_DQS_ENABLE))
#define IS_XSPI_SIOO_MODE(MODE) (((MODE) == HAL_XSPI_SIOO_INST_EVERY_CMD) || \
((MODE) == HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD))
#define IS_XSPI_RW_RECOVERY_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U)
#define IS_XSPI_ACCESS_TIME_CYCLE(CYCLE) ((CYCLE) <= 255U)
#define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \
((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE))
#define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \
((MODE) == HAL_XSPI_FIXED_LATENCY))
#define IS_XSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_XSPI_MEMORY_ADDRESS_SPACE) || \
((SPACE) == HAL_XSPI_REGISTER_ADDRESS_SPACE))
#define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \
((MODE) == HAL_XSPI_MATCH_MODE_OR))
#define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \
((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE))
#define IS_XSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU)
#define IS_XSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
#define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \
((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE))
#define IS_XSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
#define IS_XSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
#define IS_XSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U)
#define IS_XSPIM_IO_PORT(PORT) (((PORT) == HAL_XSPIM_IOPORT_1_LOW) || \
((PORT) == HAL_XSPIM_IOPORT_1_HIGH) || \
((PORT) == HAL_XSPIM_IOPORT_2_LOW) || \
((PORT) == HAL_XSPIM_IOPORT_2_HIGH) || \
((PORT) == HAL_XSPIM_IOPORT_3_LOW) || \
((PORT) == HAL_XSPIM_IOPORT_3_HIGH) || \
((PORT) == HAL_XSPIM_IOPORT_4_LOW) || \
((PORT) == HAL_XSPIM_IOPORT_4_HIGH) || \
((PORT) == HAL_XSPIM_IOPORT_5_LOW) || \
((PORT) == HAL_XSPIM_IOPORT_5_HIGH) || \
((PORT) == HAL_XSPIM_IOPORT_6_LOW) || \
((PORT) == HAL_XSPIM_IOPORT_6_HIGH) || \
((PORT) == HAL_XSPIM_IOPORT_7_LOW) || \
((PORT) == HAL_XSPIM_IOPORT_7_HIGH) || \
((PORT) == HAL_XSPIM_IOPORT_8_LOW) || \
((PORT) == HAL_XSPIM_IOPORT_8_HIGH))
#define IS_XSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U))
#define IS_XSPI_DELAY_TYPE(TYPE) (((TYPE) == HAL_XSPI_CAL_FULL_CYCLE_DELAY) || \
((TYPE) == HAL_XSPI_CAL_FEEDBACK_CLK_DELAY) || \
((TYPE) == HAL_XSPI_CAL_DATA_OUTPUT_DELAY) || \
((TYPE) == HAL_XSPI_CAL_DQS_INPUT_DELAY))
#define IS_XSPI_FINECAL_VALUE(VALUE) ((VALUE) <= 0x7FU)
#define IS_XSPI_COARSECAL_VALUE(VALUE) ((VALUE) <= 0x1FU)
/**
@endcond
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* HSPI || HSPI1 || HSPI2 || OCTOSPI || OCTOSPI1 || OCTOSPI2 */
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_HAL_XSPI_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h
|
C
|
apache-2.0
| 79,385
|
/**
******************************************************************************
* @file stm32u5xx_ll_adc.h
* @author MCD Application Team
* @brief Header file of ADC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_ADC_H
#define STM32U5xx_LL_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (ADC1) || defined (ADC2) || defined (ADC4)
/** @defgroup ADC_LL ADC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup ADC_LL_Private_Constants ADC Private Constants
* @{
*/
/* Internal mask for ADC calibration: */
/* Internal register offset for ADC calibration factors configuration */
/* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ... */
/* the relevant bits for: */
/* (concatenation of multiple bits used in different registers) */
/* - ADC calibration configuration: configuration before calibration start */
/* - ADC calibration factors: register offset */
#define ADC_CALIB_FACTOR_OFFSET_REGOFFSET (0x00000000UL) /* Register CALFACT defined as reference register */
#define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */
#define ADC_CALIB_FACTOR_REGOFFSET_MASK (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)
#define ADC_CALIB_MODE_MASK (ADC_CR_ADCALLIN)
#define ADC_CALIB_MODE_BINARY_MASK (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of
calibration mode: 0 for offset,
1 for linearity */
/* Internal mask for ADC group regular sequencer: */
/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
/* - sequencer register offset */
/* - sequencer rank bits position into the selected register */
/* Internal register offset for ADC group regular sequencer configuration */
/* (offset placed into a spare area of literal definition) */
#define ADC_SQR1_REGOFFSET (0x00000000UL)
#define ADC_SQR2_REGOFFSET (0x00000100UL)
#define ADC_SQR3_REGOFFSET (0x00000200UL)
#define ADC_SQR4_REGOFFSET (0x00000300UL)
#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET\
| ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
/* Definition of ADC group regular sequencer bits information to be inserted */
/* into ADC group regular sequencer ranks literals definition. */
#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR1_SQ1" position in register */
#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR1_SQ2" position in register */
#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR1_SQ3" position in register */
#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR1_SQ4" position in register */
#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR2_SQ5" position in register */
#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR2_SQ6" position in register */
#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR2_SQ7" position in register */
#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR2_SQ8" position in register */
#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR2_SQ9" position in register */
#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR3_SQ10" position in register */
#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR3_SQ11" position in register */
#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_SQR3_SQ12" position in register */
#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_SQR3_SQ13" position in register */
#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_SQR3_SQ14" position in register */
#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR4_SQ15" position in register */
#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR4_SQ16" position in register */
#define ADC4_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ1" position in register */
#define ADC4_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ2" position in register */
#define ADC4_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ3" position in register */
#define ADC4_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ4" position in register */
#define ADC4_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ5" position in register */
#define ADC4_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ6" position in register */
#define ADC4_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ7" position in register */
#define ADC4_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC4_CHSELR_SQ8" position in register */
/* Internal mask for ADC group injected sequencer: */
/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
/* - data register offset */
/* - sequencer rank bits position into the selected register */
/* Internal register offset for ADC group injected data register */
/* (offset placed into a spare area of literal definition) */
#define ADC_JDR1_REGOFFSET (0x00000000UL)
#define ADC_JDR2_REGOFFSET (0x00000100UL)
#define ADC_JDR3_REGOFFSET (0x00000200UL)
#define ADC_JDR4_REGOFFSET (0x00000300UL)
#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET\
| ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
/* Definition of ADC group injected sequencer bits information to be inserted */
/* into ADC group injected sequencer ranks literals definition. */
#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_TR1_HT1" position in register */
#define ADC4_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL0" position in register */
#define ADC4_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL1" position in register */
#define ADC4_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL2" position in register */
#define ADC4_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL3" position in register */
#define ADC4_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL4" position in register */
#define ADC4_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL5" position in register */
#define ADC4_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL6" position in register */
#define ADC4_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL7" position in register */
#define ADC4_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL8" position in register */
#define ADC4_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL9" position in register */
#define ADC4_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL10" position in register */
#define ADC4_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL11" position in register */
#define ADC4_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL12" position in register */
#define ADC4_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL13" position in register */
#define ADC4_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL14" position in register */
#define ADC4_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL15" position in register */
#define ADC4_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL16" position in register */
#define ADC4_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL17" position in register */
#define ADC4_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL18" position in register */
#define ADC4_CHSELR_CHSEL19_BITOFFSET_POS (19UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL19" position in register */
#define ADC4_CHSELR_CHSEL20_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL20" position in register */
#define ADC4_CHSELR_CHSEL21_BITOFFSET_POS (21UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL21" position in register */
#define ADC4_CHSELR_CHSEL22_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL22" position in register */
#define ADC4_CHSELR_CHSEL23_BITOFFSET_POS (23UL) /* Equivalent to bitfield "ADC4_CHSELR_CHSEL23" position in register */
#define ADC4_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC4_SMPR_SMP1" position in register */
#define ADC4_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC4_SMPR_SMP2" position in register */
#define ADC4_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC4_SMPR_SMPSEL0" position in register */
/* Internal mask for ADC group regular trigger: */
/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
/* - regular trigger source */
/* - regular trigger edge */
#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting
for compatibility with some ADC on other STM32
families having this setting set by HW default value) */
/* Mask containing trigger source masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
#define ADC4_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC4_CFGR1_EXTSEL) << (4U * 0UL)) | \
((ADC4_CFGR1_EXTSEL) << (4U * 1UL)) | \
((ADC4_CFGR1_EXTSEL) << (4U * 2UL)) | \
((ADC4_CFGR1_EXTSEL) << (4U * 3UL)) )
/* Mask containing trigger edge masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
/* Definition of ADC group regular trigger bits information. */
#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTSEL"
position in register */
#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTEN"
position in register */
/* Internal mask for ADC group injected trigger: */
/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
/* - injected trigger source */
/* - injected trigger edge */
#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
compatibility with some ADC on other STM32 families
having this setting set by HW default value) */
/* Mask containing trigger source masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
/* Mask containing trigger edge masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
/* Definition of ADC group injected trigger bits information. */
#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL"
position in register */
#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN"
position in register */
/* Internal mask for ADC channel: */
/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
/* - channel identifier defined by number */
/* - channel identifier defined by bitfield */
/* - channel differentiation between external channels (connected to */
/* GPIO pins) and internal channels (connected to internal paths) */
/* - channel sampling time defined by SMPRx register offset */
/* and SMPx bits positions into SMPRx register */
#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define ADC_CHANNEL_ID_OFFSET_NUMBER_MASK (ADC_OFR1_OFFSET1_CH)
#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
position in register */
#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
| ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK
aligned on register LSB (bit 0) */
#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >>
[Position of bitfield "ADC_CHANNEL_NUMBER_MASK"
in register]) */
/* Channel differentiation between external and internal channels */
#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
/* Internal register offset for ADC channel sampling time configuration */
/* (offset placed into a spare area of literal definition) */
#define ADC_SMPR1_REGOFFSET (0x00000000UL)
#define ADC_SMPR2_REGOFFSET (0x02000000UL)
#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in
ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
#define ADC4_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
#define ADC4_SAMPLING_TIME_CH_MASK (ADC4_CHANNEL_ID_BITFIELD_MASK << ADC4_SMPR_SMPSEL0_BITOFFSET_POS)
#define ADC4_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 \
<< ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to
ADC_CHANNEL_ID_NUMBER_MASK with
reduced range: on this STM32 series,
ADC group regular sequencer, if set
to mode "fully configurable", can
contain channels with a restricted
channel number. */
/* Definition of channels ID number information to be inserted into */
/* channels literals definition. */
#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
#define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
#define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
#define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
#define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
#define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
#define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
#define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
#define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
#define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
#define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
#define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
#define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
#define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
#define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#if defined(ADC4)
#define ADC_CHANNEL_20_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 )
#define ADC_CHANNEL_21_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
#define ADC_CHANNEL_22_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
#define ADC_CHANNEL_23_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
#endif /* ADC4 */
/* Definition of channels ID bitfield information to be inserted into */
/* channels literals definition. */
#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
#define ADC_CHANNEL_19_BITFIELD (ADC_AWD2CR_AWD2CH_19)
#define ADC_CHANNEL_20_BITFIELD (ADC_AWD2CR_AWD2CH_20)
#define ADC_CHANNEL_21_BITFIELD (ADC_AWD2CR_AWD2CH_21)
#define ADC_CHANNEL_22_BITFIELD (ADC_AWD2CR_AWD2CH_22)
#define ADC_CHANNEL_23_BITFIELD (ADC_AWD2CR_AWD2CH_23)
#define ADC4_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
#define ADC4_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
#define ADC4_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
#define ADC4_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
#define ADC4_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
#define ADC4_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
#define ADC4_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
#define ADC4_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
#define ADC4_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
#define ADC4_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
#define ADC4_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
#define ADC4_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
#define ADC4_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
#define ADC4_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
#define ADC4_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
#define ADC4_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
#define ADC4_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
#define ADC4_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
#define ADC4_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
#define ADC4_CHANNEL_19_BITFIELD (ADC_CHSELR_CHSEL19)
#define ADC4_CHANNEL_20_BITFIELD (ADC_CHSELR_CHSEL20)
#define ADC4_CHANNEL_21_BITFIELD (ADC_CHSELR_CHSEL21)
#define ADC4_CHANNEL_22_BITFIELD (ADC_CHSELR_CHSEL22)
#define ADC4_CHANNEL_23_BITFIELD (ADC_CHSELR_CHSEL23)
/* Definition of channels sampling time information to be inserted into */
/* channels literals definition. */
#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP0" register */
#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP1" register */
#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP2" register */
#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP3" register */
#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP4" register */
#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP5" register */
#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP6" register */
#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP7" register */
#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP8" register */
#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET ) /* Channel is with "ADC_SMPR1_SMP9" register */
#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP10" register */
#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP11" register */
#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP12" register */
#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP13" register */
#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP14" register */
#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP15" register */
#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP16" register */
#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP17" register */
#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP18" register */
#define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP19" register */
#define ADC_CHANNEL_20_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP20" register */
#define ADC_CHANNEL_21_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP21" register */
#define ADC_CHANNEL_22_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP22" register */
#define ADC_CHANNEL_23_SMP (ADC_SMPR2_REGOFFSET ) /* Channel is with "ADC_SMPR2_SMP23" register */
/* Internal mask for ADC mode single or differential ended: */
/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
/* the relevant bits for: */
/* (concatenation of multiple bits used in different registers) */
/* - ADC calibration: calibration start, calibration factor get or set */
/* - ADC channels: set each ADC channel ending mode */
#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT2_CALFACT)
#define ADC_CALFACT2_CALFACT_S (0x0000FFFFUL)
#define ADC_CALFACT2_CALFACT_D (0xFFFF0000UL)
#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_I_APB_ADDR_4 \
| ADC_CALFACT_I_APB_ADDR_3) /* Bits chosen to perform of shift when single
mode is selected, shift value out of
channels bits range. */
#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
mask of bit */
#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode:
position of bit */
#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
ADC_SINGLEDIFF_CALIB_F_BIT_D
to position to perform a shift
of 4 ranks */
/* Internal mask for ADC analog watchdog: */
/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
/* (concatenation of multiple bits used in different analog watchdogs, */
/* (feature of several watchdogs not available on all STM32 families)). */
/* - analog watchdog 1: monitored channel defined by number, */
/* selection of ADC group (ADC groups regular and-or injected). */
/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
/* selection on groups. */
/* Internal register offset for ADC analog watchdog channel configuration */
#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define ADC_AWD_CR2_REGOFFSET (0x01000000UL)
#define ADC_AWD_CR3_REGOFFSET (0x02000000UL)
/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define ADC_AWD_CHANNEL_MASK (ADC_CHANNEL_ID_NUMBER_MASK)
#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define ADC_AWD_CRX_REGOFFSET_POS (24UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK*/
/* Internal register offset for ADC analog watchdog threshold configuration */
#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in
ADC_AWD_TRX_REGOFFSET_MASK */
#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
threshold high: mask of bit */
#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
threshold high: position of bit */
#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH
to position to perform a shift of 4 ranks */
#define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
/* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
/* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
#define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
/* Legacy literals */
#define LL_ADC_AWD1_TR LL_ADC_AWD1
#define LL_ADC_AWD2_TR LL_ADC_AWD2
#define LL_ADC_AWD3_TR LL_ADC_AWD3
/* Internal mask for ADC offset: */
/* Internal register offset for ADC offset number configuration */
#define ADC_OFR1_REGOFFSET (0x00000000UL)
#define ADC_OFR2_REGOFFSET (0x00000001UL)
#define ADC_OFR3_REGOFFSET (0x00000002UL)
#define ADC_OFR4_REGOFFSET (0x00000003UL)
#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET\
| ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
/* ADC registers bits positions */
#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR1_RES_Pos)
#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR1_AWD1SGL_Pos)
#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR1_AWD1EN_Pos)
#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR1_JAWD1EN_Pos)
/* ADC registers bits groups */
#define ADC_CR_BITS_PROPERTY_RS ( ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART \
| ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs":
Software can read as well as set this bit.
Writing '0' has no effect on the bit value. */
/* ADC internal channels related definitions */
/* Internal voltage reference VrefInt */
#define VREFINT_CAL_ADDR ((uint16_t*) (0x0BFA07A5UL)) /* Internal voltage reference, address of parameter
VREFINT_CAL: VrefInt ADC raw data acquired at
temperature 30 DegC (tolerance: +-5 DegC),
Vref+ = 3.0 V (tolerance: +-10 mV). */
#define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which
VrefInt has been calibrated in production
(tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */
#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BFA0710UL)) /* Internal temperature sensor, address of parameter
TS_CAL1: On STM32U5, temperature sensor ADC raw
data acquired at temperature 30 DegC
(tolerance: +-5 DegC),Vref+ = 3.0 V
(tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BFA0742UL)) /* Internal temperature sensor, address of parameter
TS_CAL2: On STM32U5, temperature sensor ADC raw
data acquired at temperature 110 DegC
(tolerance: +-5 DegC), Vref+ = 3.0 V
(tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which
temperature sensor has been calibrated in
production for data into TEMPSENSOR_CAL1_ADDR
(tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which
temperature sensor has been calibrated in
production for data into TEMPSENSOR_CAL2_ADDR
(tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with
which temperature sensor has been calibrated in
production (+-10 mV) (unit: mV). */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup ADC_LL_Private_Macros ADC Private Macros
* @{
*/
/**
* @brief Driver macro reserved for internal use: isolate bits with the
* selected mask and shift them to the register LSB
* (shift mask on register position bit 0).
* @param __BITS__ Bits in register 32 bits
* @param __MASK__ Mask in register 32 bits
* @retval Bits in register 32 bits
*/
#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
*/
#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of ADC common parameters
* and multimode
* (all ADC instances belonging to the same ADC common instance).
* @note The setting of these parameters by function @ref LL_ADC_CommonInit()
* is conditioned to ADC instances state (all ADC instances
* sharing the same ADC common instance):
* All ADC instances sharing the same ADC common instance must be
* disabled.
*/
typedef struct
{
uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
This feature can be modified afterwards using unitary function
@ref LL_ADC_SetCommonClock(). */
} LL_ADC_CommonInitTypeDef;
/**
* @brief Structure definition of some features of ADC instance.
* @note These parameters have an impact on ADC scope: ADC instance.
* Affects both group regular and group injected (availability
* of ADC group injected depends on STM32 families).
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Instance .
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
*/
typedef struct
{
uint32_t Resolution; /*!< Set ADC resolution.
This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
This feature can be modified afterwards using unitary function
@ref LL_ADC_SetResolution(). */
uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
This feature can be modified afterwards using unitary function
@ref LL_ADC_SetDataAlignment(). */
uint32_t LowPowerMode; /*!< Set ADC low power mode.
This parameter can be a value of @ref ADC_LL_EC_LP_MODE
This feature can be modified afterwards using unitary function
@ref LL_ADC_SetLowPowerMode(). */
} LL_ADC_InitTypeDef;
/**
* @brief Structure definition of some features of ADC group regular.
* @note These parameters have an impact on ADC scope: ADC group regular.
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
* (functions with prefix "REG").
* @note The setting of these parameters by function @ref LL_ADC_REG_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
*/
typedef struct
{
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start)
or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
@note On this STM32 series, setting trigger source to external trigger
also set trigger polarity to rising edge (default setting for
compatibility with some ADC on other STM32 families having this
setting set by HW default value).
In case of need to modify trigger edge, use function
@ref LL_ADC_REG_SetTriggerEdge().
This feature can be modified afterwards using unitary function
@ref LL_ADC_REG_SetTriggerSource(). */
uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
This feature can be modified afterwards using unitary function
@ref LL_ADC_REG_SetSequencerLength(). */
uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
and scan conversions interrupted every selected number of ranks.
This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
@note This parameter has an effect only if group regular sequencer is
enabled (scan length of 2 ranks or more).
This feature can be modified afterwards using unitary function
@ref LL_ADC_REG_SetSequencerDiscont(). */
uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular,
whether ADC conversions are performed in single mode (one conversion per
trigger) or in continuous mode (after the first trigger, following
conversions launched successively automatically).
This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
Note: It is not possible to enable both ADC group regular continuous
mode and discontinuous mode.
This feature can be modified afterwards using unitary function
@ref LL_ADC_REG_SetContinuousMode(). */
uint32_t DataTransferMode; /*!< Set ADC group regular conversion data transfer mode: no transfer,
transfer by DMA (Limited/Unlimited) or MDF.
This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE
This feature can be modified afterwards using unitary function
@ref LL_ADC_REG_SetDataTransferMode(). */
uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
by DMA, and DMA requests mode.
This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
This feature can be modified afterwards using unitary function
@ref LL_ADC_REG_SetDMATransfer(). */
uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
data preserved or overwritten.
This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
This feature can be modified afterwards using unitary function
@ref LL_ADC_REG_SetOverrun(). */
} LL_ADC_REG_InitTypeDef;
/**
* @brief Structure definition of some features of ADC group injected.
* @note These parameters have an impact on ADC scope: ADC group injected.
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
* (functions with prefix "INJ").
* @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
*/
typedef struct
{
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start)
or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
@note On this STM32 series, setting trigger source to external trigger
also set trigger polarity to rising edge (default setting for
compatibility with some ADC on other STM32 families having this
setting set by HW default value).
In case of need to modify trigger edge, use function
@ref LL_ADC_INJ_SetTriggerEdge().
This feature can be modified afterwards using unitary function
@ref LL_ADC_INJ_SetTriggerSource(). */
uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
This feature can be modified afterwards using unitary function
@ref LL_ADC_INJ_SetSequencerLength(). */
uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
and scan conversions interrupted every selected number of ranks.
This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
@note This parameter has an effect only if group injected sequencer
is enabled (scan length of 2 ranks or more).
This feature can be modified afterwards using unitary function
@ref LL_ADC_INJ_SetSequencerDiscont(). */
uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
Note: This parameter must be set to set to independent trigger if injected
trigger source is set to an external trigger.
This feature can be modified afterwards using unitary function
@ref LL_ADC_INJ_SetTrigAuto(). */
} LL_ADC_INJ_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
* @{
*/
/** @defgroup ADC_LL_EC_FLAG ADC flags
* @brief Flags defines which can be used with LL_ADC_ReadReg function
* @{
*/
#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
#define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
#define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC flag Voltage Regulator (LDO) Ready */
#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end
of unitary conversion */
#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end
of unitary conversion */
#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end
of sequence conversions */
#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end
of sequence conversions */
#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end
of sampling phase */
#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end
of sampling phase */
#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end
of unitary conversion */
#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end
of unitary conversion */
#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end
of sequence conversions */
#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end
of sequence conversions */
#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1
of the ADC master */
#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1
of the ADC slave */
#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2
of the ADC master */
#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2
of the ADC slave */
#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3
of the ADC master */
#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3
of the ADC slave */
/**
* @}
*/
/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
* @{
*/
#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of
unitary conversion */
#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of
sequence conversions */
#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of
sampling phase */
#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of
unitary conversion */
#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of
sequence conversions */
#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
#define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
#define LL_ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC interruption ADC Voltage Regulator (LDO) Ready */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
* @{
*/
/* List of ADC registers intended to be used (most commonly) with */
/* DMA transfer. */
/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
(corresponding to register DR) to be used with ADC
configured in independent mode. Without DMA transfer,
register accessed by LL function
@ref LL_ADC_REG_ReadConversionData32() and
other functions @ref LL_ADC_REG_ReadConversionDatax() */
#if defined(ADC_MULTIMODE_SUPPORT)
#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register
(corresponding to register CDR) to be used with
ADC configured in multimode (available on STM32 devices
with several ADC instances). Without DMA transfer,
register accessed by LL function
@ref LL_ADC_REG_ReadMultiConversionData32() */
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock
without prescaler */
#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
with prescaler division
by 2 */
#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
with prescaler division
by 4 */
#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
with prescaler division
by 6 */
#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock
with prescaler division
by 8 */
#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
with prescaler division
by 10 */
#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
with prescaler division
by 12 */
#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
with prescaler division
by 16 */
#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock
with prescaler division
by 32 */
#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
with prescaler division
by 64 */
#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock
with prescaler division
by 128 */
#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock
with prescaler division
by 256 */
/**
* @}
*/
/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
* @{
*/
/* Note: Other measurement paths to internal channels may be available */
/* (connections to other peripherals). */
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSEEN) /*!< ADC measurement path to internal channel
temperature sensor */
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
#define LL_ADC_PATH_INTERNAL_VCORE (LL_ADC_PATH_INTERNAL_VREFINT \
| LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE) /*!< ADC measurement path
to internal channel VCore */
/**
* @}
*/
/** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY ADC instance - Calibration mode for offset and linearity
* @{
*/
#define LL_ADC_CALIB_OFFSET (ADC_CALIB_FACTOR_OFFSET_REGOFFSET) /*!< Calibration of ADC offset.
Duration of calibration of offset
duration: 1280 ADC clock cycles.
For devices with differential mode
available: Calibration of offset
is specific to each of single-ended
and differential modes. */
#define LL_ADC_CALIB_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)/*!< Calibration of ADC linearity.
Duration of calibration of
linearity: 15104 ADC clock cycles.
For devices with differential mode
available: Calibration of linearity
is common to both single-ended and
differential modes. */
#define LL_ADC_CALIB_OFFSET_LINEARITY (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET \
| ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and
linearity. Duration of calibration
of offset and linearity: 16384 ADC
clock cycles. For devices with
differential mode available:
Calibration of offset is specific
to each of single-ended and
differential modes, calibration of
linearity is common to both
single-ended and differential modes. */
/**
* @}
*/
/** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_INDEX ADC indexes for linear calibration
* @{
*/
#define LL_ADC_CALIB_OFFSET_INDEX (0x00000000UL) /*!< Offset Calibration Index */
#define LL_ADC_CALIB_LINEARITY_INDEX1 (ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 1*/
#define LL_ADC_CALIB_LINEARITY_INDEX2 (ADC_CR_CALINDEX1) /*!< Linearity Calibration Index 2*/
#define LL_ADC_CALIB_LINEARITY_INDEX3 (ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 3*/
#define LL_ADC_CALIB_LINEARITY_INDEX4 (ADC_CR_CALINDEX2) /*!< Linearity Calibration Index 4*/
#define LL_ADC_CALIB_LINEARITY_INDEX5 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 5*/
#define LL_ADC_CALIB_LINEARITY_INDEX6 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1) /*!< Linearity Calibration Index 6*/
#define LL_ADC_CALIB_LINEARITY_INDEX7 (ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 \
| ADC_CR_CALINDEX0) /*!< Linearity Calibration Index 7*/
#define LL_ADC_CALIB_INTEROFFSET_INDEX (ADC_CR_CALINDEX3) /*!< Linearity Calibration Index 8*/
/**
* @}
*/
/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
* @{
*/
#define LL_ADC_RESOLUTION_14B (0x00000000UL) /*!< ADC resolution 14 bits */
#define LL_ADC_RESOLUTION_12B ( ADC_CFGR1_RES_0) /*!< ADC resolution 12 bits */
#define LL_ADC_RESOLUTION_10B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 10 bits */
#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 8 bits */
#define LL_ADC_RESOLUTION_6B (0x0000FFFFUL) /*!< ADC resolution 6 bits, Internal value
used to differentiate 8B to 6B resolutions
for ADC1 and ADC4 respectively */
/* Internal values only, please do not use */
#define LL_ADC_RESOLUTION_12B_ADC4 (0x00000000UL) /*!< ADC resolution 12 bits */
#define LL_ADC_RESOLUTION_10B_ADC4 ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
#define LL_ADC_RESOLUTION_8B_ADC4 (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
#define LL_ADC_RESOLUTION_6B_ADC4 (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
/**
* @}
*/
/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
* @{
*/
#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned
(alignment on data register LSB bit 0)*/
#define LL_ADC_DATA_ALIGN_LEFT (ADC4_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned
(alignment on data register MSB bit 15)*/
/**
* @}
*/
/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
* @{
*/
#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC conversion data */
#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC conversion data */
/**
* @}
*/
/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
* @{
*/
#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
/**
* @}
*/
/** @defgroup ADC_LL_EC_AUTOPOWEROFF_MODE ADC instance - Low power mode auto power-off
* @{
*/
#define LL_ADC_LP_AUTOPOWEROFF_DISABLE (0x00000000UL) /*!< ADC low power mode auto power-off disabled */
#define LL_ADC_LP_AUTOPOWEROFF_ENABLE (ADC4_PW_AUTOFF) /*!< ADC low power mode auto power-off enabled: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLPModeAutoPowerOff(). It can be combined with mode low power mode auto wait. */
/**
* @}
*/
/** @defgroup ADC_LL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE ADC instance - Autonomous deep power down mode
* @{
*/
#define LL_ADC_LP_AUTONOMOUS_DPD_DISABLE (0x00000000UL) /*!< ADC deep power down in autonomous mode disabled */
#define LL_ADC_LP_AUTONOMOUS_DPD_ENABLE (ADC4_PW_DPD) /*!< ADC deep power down in autonomous mode enabled */
/**
* @}
*/
/** @defgroup ADC_LL_EC_VREF_PROTECTION_MODE ADC instance - VREF protection mode
* @{
*/
#define LL_ADC_VREF_PROT_DISABLE (0x00000000UL) /*!< ADC Vref+ protection disabled */
#define LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE (ADC4_PW_VREFPROT) /*!< ADC Vref+ protection enabled: In case of simultaneous sampling phase of ADC4 and ADC1/2, ADC4 is put on hold during one ADC4 clock cycle to avoid noise on Vref+. */
#define LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE (ADC4_PW_VREFPROT | ADC4_PW_VREFSECSMP) /*!< ADC Vref+ protection enabled: In case of simultaneous sampling phase of ADC4 and ADC1/2, ADC4 is put on hold during two ADC4 clock cycles to avoid noise on Vref+. */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
* @{
*/
#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode
* @{
*/
#define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
#define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE (ADC_OFR1_SSAT) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OFFSET_UNSIGNED_SATURATION ADC instance - Offset unsigned saturation mode
* @{
*/
#define LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset unsigned saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
#define LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE (ADC_OFR1_USAT) /*!< ADC offset unsigned saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
* @{
*/
#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */
#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
* @{
*/
#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
/**
* @}
*/
/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
* @{
*/
#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC4_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC4_SMPR_SMP2_BITOFFSET_POS | ADC4_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
/* Internal mask for ADC channel sampling time: */
/* To select into literals LL_ADC_SAMPLINGTIME_x */
/* the relevant bits for: */
/* (concatenation of multiple bits used in register SMPR) */
/* - ADC channels sampling time: setting channel wise, to map each channel */
/* on one of the common sampling time available. */
/* - ADC channels common sampling time: set a sampling time into one of the */
/* common sampling time available. */
#define ADC4_SAMPLING_TIME_SMP_MASK (ADC4_SMPR_SMP2 | ADC4_SMPR_SMP1)
#define ADC4_SAMPLING_TIME_SMP_SHIFT_MASK (ADC4_SMPR_SMP2_BITOFFSET_POS | ADC4_SMPR_SMP1_BITOFFSET_POS)
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
* @{
*/
#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
#define LL_ADC_TRIGGER_FREQ_LOW (ADC4_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
/**
* @}
*/
/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
* @{
*/
#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
#define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER | ADC_CHANNEL_20_SMP | ADC_CHANNEL_20_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20 */
#define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER | ADC_CHANNEL_21_SMP | ADC_CHANNEL_21_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21 */
#define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER | ADC_CHANNEL_22_SMP | ADC_CHANNEL_22_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22 */
#define LL_ADC_CHANNEL_23 (ADC_CHANNEL_23_NUMBER | ADC_CHANNEL_23_SMP | ADC_CHANNEL_23_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN23 */
#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. . */
#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. */
#define LL_ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vcore. On STM32U5, ADC channel available only on ADC instance: ADC4. */
#define LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32U5, ADC channel available only on ADC instance: ADC4. */
#define LL_ADC_CHANNEL_VBAT_ADC4 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32U5, ADC channel available only on ADC instance: ADC4. */
#define LL_ADC_CHANNEL_DAC1CH1_ADC4 (LL_ADC_CHANNEL_21 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC4 */
#define LL_ADC_CHANNEL_DAC1CH2_ADC4 (LL_ADC_CHANNEL_DAC1CH1_ADC4 | LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC4 */
#define LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE (0x01000000UL) /*!< Dummy bit for driver internal usage, not used in ADC channel setting registers CHSELR or SQRx */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
* @{
*/
#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR1_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR1_EXTSEL_3 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
| ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR1_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 15 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 channel 1 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM2_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 channel 1 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM3_CH1 (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 channel 1 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM4_OUT (ADC_CFGR1_EXTSEL_4 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \
| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM4 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2_ADC4 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH4_ADC4 (ADC4_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#if defined(TIM2)
#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#endif /* TIM2 */
#if defined(TIM15)
#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_1 | ADC4_CFGR1_EXTSEL_0 \
| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#endif /* TIM5 */
#if defined(TIM6)
#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#endif /* TIM6 */
#if defined(LPTIM1)
#define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_0 \
| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM1 CH1. Trigger edge set to rising edge (default setting). */
#endif /* LPTIM1 */
#if defined(LPTIM3)
#define LL_ADC_REG_TRIG_EXT_LPTIM3_CH2_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_1 \
| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM3 CH2. Trigger edge set to rising edge (default setting). */
#endif /* LPTIM3 */
#define LL_ADC_REG_TRIG_EXT_EXTI_LINE15_ADC4 (ADC4_CFGR1_EXTSEL_2 | ADC4_CFGR1_EXTSEL_1 \
| ADC4_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
* @{
*/
#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
* @{
*/
#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE ADC group regular - Data transfer mode of ADC conversion data
* @{
*/
#define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */
#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversion data are not transferred by DMA but to DR register */
#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMNGT_1 | ADC_CFGR1_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
#define LL_ADC_REG_MDF_TRANSFER (ADC_CFGR1_DMNGT_1 ) /*!< ADC conversion data are transferred to DFSDM */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
* @{
*/
#define LL_ADC_REG_DMA_TRANSFER_NONE_ADC4 (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
#define LL_ADC_REG_DMA_TRANSFER_LIMITED_ADC4 ( ADC4_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED_ADC4 (ADC4_CFGR1_DMACFG | ADC4_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
* @{
*/
#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
* @{
*/
#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */
#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC4_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
* @{
*/
#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
* @{
*/
#define LL_ADC4_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
#define LL_ADC4_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
#define LL_ADC4_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
#define LL_ADC4_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
#define LL_ADC4_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
#define LL_ADC4_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
#define LL_ADC4_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
#define LL_ADC4_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
* @{
*/
#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
#define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
#define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
#define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 \
| ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
* @{
*/
#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC4_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
#define LL_ADC_REG_RANK_1_ADC4 (ADC4_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
#define LL_ADC_REG_RANK_2_ADC4 (ADC4_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
#define LL_ADC_REG_RANK_3_ADC4 (ADC4_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
#define LL_ADC_REG_RANK_4_ADC4 (ADC4_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
#define LL_ADC_REG_RANK_5_ADC4 (ADC4_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
#define LL_ADC_REG_RANK_6_ADC4 (ADC4_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
#define LL_ADC_REG_RANK_7_ADC4 (ADC4_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
#define LL_ADC_REG_RANK_8_ADC4 (ADC4_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
* @{
*/
#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */
#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 \
| ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 \
| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM4_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 \
| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
* @{
*/
#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
* @{
*/
#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
* @{
*/
#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME. */
#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
Note: First conversion is using minimal
sampling time (see @ref
ADC_LL_EC_CHANNEL_SAMPLINGTIME). */
#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG)/*!< ADC conversions sampling phase is controlled by trigger events:
Trigger rising edge = start sampling
Trigger falling edge = stop sampling and
start conversion. */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
* @{
*/
#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
* @{
*/
#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
* @{
*/
#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
/**
* @}
*/
/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
#define LL_ADC_SAMPLINGTIME_5CYCLES (0x00000000UL) /*!< Sampling time 5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_6CYCLES ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_12CYCLES ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_20CYCLES ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 20 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_36CYCLES (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 36 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_68CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 68 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_391CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 391 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_814CYCLES (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 814 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_5CYCLE LL_ADC_SAMPLINGTIME_5CYCLES /*!< Keep old definition for compatibility */
#define LL_ADC_SAMPLINGTIME_391CYCLES_5 LL_ADC_SAMPLINGTIME_391CYCLES /*!< Keep old definition for compatibility */
/**
* @}
*/
/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
#define LL_ADC4_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
#define LL_ADC4_SAMPLINGTIME_3CYCLES_5 (ADC4_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
#define LL_ADC4_SAMPLINGTIME_7CYCLES_5 (ADC4_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
#define LL_ADC4_SAMPLINGTIME_12CYCLES_5 (ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
#define LL_ADC4_SAMPLINGTIME_19CYCLES_5 (ADC4_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
#define LL_ADC4_SAMPLINGTIME_39CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
#define LL_ADC4_SAMPLINGTIME_79CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
#define LL_ADC4_SAMPLINGTIME_814CYCLES_5 (ADC4_SMPR_SMP1_2 | ADC4_SMPR_SMP1_1 | ADC4_SMPR_SMP1_0) /*!< Sampling time 814.5 ADC clock cycles */
#define LL_ADC4_SAMPLINGTIME_160CYCLES_5 LL_ADC4_SAMPLINGTIME_814CYCLES_5 /*!< Keep old definition for compatibility */
/**
* @}
*/
/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
* @{
*/
#define LL_ADC_SINGLE_ENDED (0x0000FFFFUL) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
#define LL_ADC_DIFFERENTIAL_ENDED (0xFFFF0000UL) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
* @{
*/
#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
/**
* @}
*/
/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
* @{
*/
#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
#define LL_ADC_AWD_ALL_CHANNELS_REG ((0x000FFFFFUL) | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
#define LL_ADC_AWD_ALL_CHANNELS_INJ ((0x000FFFFFUL) | ADC_CFGR1_JAWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ((0x000FFFFFUL) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_20_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_20_REG_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_21_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_21_REG_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_22_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_22_REG_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_23_REG ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_AWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_23_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_23_REG_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_NUMBER_MASK) | ADC_CFGR1_JAWD1EN \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */
#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */
#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */
#define LL_ADC_AWD_CH_VCORE_REG ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
#define LL_ADC_AWD_CH_VCORE_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
#define LL_ADC_AWD_CH_VCORE_REG_INJ ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
#define LL_ADC_AWD_CH_DAC1CH1_ADC4_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC4, converted by group regular only */
#define LL_ADC_AWD_CH_DAC1CH2_ADC4_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 2, channel specific to ADC4, converted by group regular only */
#define LL_ADC_AWD_CH_TEMPSENSOR_ADC4_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to emperature sensor, channel specific to ADC4, converted by group regular only */
#define LL_ADC_AWD_CH_VBAT_ADC4_REG ((LL_ADC_CHANNEL_VBAT_ADC4 & ADC_CHANNEL_ID_NUMBER_MASK) \
| ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC4, converted by group regular only */
/**
* @}
*/
/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
* @{
*/
#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */
#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */
/**
* @}
*/
/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
* @{
*/
#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_HTR_AWDFILT_1 ) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_HTR_AWDFILT_2 ) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 ) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_HTR_AWDFILT_2 | ADC_HTR_AWDFILT_1 | ADC_HTR_AWDFILT_0) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
* @{
*/
#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
*/
#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_4 ( ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_8 ( ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_16 ( ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_32 (ADC4_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_64 (ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_128 (ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_256 (ADC4_CFGR2_OVSR_2 | ADC4_CFGR2_OVSR_1 | ADC4_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
* @{
*/
#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_9 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_10 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_11 (ADC_CFGR2_OVSS_3 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */
/**
* @}
*/
#if defined(ADC_MULTIMODE_SUPPORT)
/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
* @{
*/
#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
/**
* @}
*/
/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
* @{
*/
#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
#define LL_ADC_MULTI_REG_DMA_RES_32_10B (ADC_CCR_DAMDF_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */
#define LL_ADC_MULTI_REG_DMA_RES_8B (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */
/**
* @}
*/
/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
* @{
*/
#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 |ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles for 8 bits resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2 |ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles for all resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles for 10 bits resolution */
#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3|ADC_CCR_DELAY_2|ADC_CCR_DELAY_1|ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles for all resolution */
/**
* @}
*/
/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
* @{
*/
#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
/**
* @}
*/
#endif /* ADC_MULTIMODE_SUPPORT */
/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
* @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
/* not timeout values. */
/* Timeout values for ADC operations are dependent to device clock */
/* configuration (system clock versus ADC clock), */
/* and therefore must be defined in user application. */
/* Indications for estimation of ADC timeout delays, for this */
/* STM32 series: */
/* - ADC calibration time: maximum delay is 16384/fADC. */
/* (refer to device datasheet, parameter "tCAL") */
/* - ADC enable time: maximum delay is 1 conversion cycle. */
/* (refer to device datasheet, parameter "tSTAB") */
/* - ADC disable time: maximum delay should be a few ADC clock cycles */
/* - ADC stop conversion time: maximum delay should be a few ADC clock */
/* cycles */
/* - ADC conversion time: duration depending on ADC clock and ADC */
/* configuration. */
/* (refer to device reference manual, section "Timing") */
/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tADCVREG_STUP"). */
/* Unit: us */
#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
/* Delay for internal voltage reference stabilization time. */
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "ts_vrefint"). */
/* Unit: us */
#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
/* Delay for temperature sensor stabilization time. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART_RUN"). */
/* Unit: us */
#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
/* Delay required between ADC end of calibration and ADC enable. */
/* Note: On this STM32 series, a minimum number of ADC clock cycles */
/* are required between ADC end of calibration and ADC enable. */
/* Wait time can be computed in user application by waiting for the */
/* equivalent number of CPU cycles, by taking into account */
/* ratio of CPU clock versus ADC clock prescalers. */
/* Unit: ADC clock cycles. */
#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
/* Fixed timeout value for ADC linearity word bit set/clear delay. */
/* Values defined to be higher than worst cases: low clock frequency, */
/* maximum prescalers. */
/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */
/* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB */
/* 6 / 4577 = 1,311ms */
/* At maximum CPU speed (400 MHz), this means */
/* 3.58 * 400 MHz = 524400 CPU cycles */
#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL) /*!< ADC linearity set/clear bit delay */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
* @{
*/
/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in ADC register
* @param __INSTANCE__ ADC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in ADC register
* @param __INSTANCE__ ADC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
* @{
*/
/**
* @brief Helper macro to get ADC channel number in decimal format
* from literals LL_ADC_CHANNEL_x.
* @note Example:
* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
* will return decimal number "4".
* @note The input can be a value from functions where a channel
* number is returned, either defined with number
* or with bitfield (only one bit must be set).
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VCORE (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @retval Value between Min_Data=0 and Max_Data=18
*/
#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
? ( ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ) \
: ( (uint32_t)POSITION_VAL((__CHANNEL__)) ) \
)
/**
* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
* from number in decimal format.
* @note Example:
* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
* will return a data equivalent to "LL_ADC_CHANNEL_4".
* @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VCORE (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* (1, 2) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
(((__DECIMAL_NB__) <= 9UL) \
? (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
(ADC_SMPR1_REGOFFSET)) \
: (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
(ADC_SMPR2_REGOFFSET)) \
)
/**
* @brief Helper macro to convert ADC1 resolution to ADC4 resolution bit values.
* @note Example 1:
* __LL_ADC_RESOLUTION_ADC1_TO_ADC4(LL_ADC_RESOLUTION_6B)
* will return a data equivalent to "(ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)".
* @note Example 2:
* __LL_ADC_RESOLUTION_ADC1_TO_ADC4(LL_ADC_RESOLUTION_10B)
* will return a data equivalent to "(ADC_CFGR1_RES_0)".
* @param __RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @retval Returned value can be one of the following values:
* @arg 0x00000000UL (value correspodning to ADC4 12 bits)
* @arg ADC_CFGR1_RES_0 = 0x00000004UL (value correspodning to ADC4 10 bits)
* @arg ADC_CFGR1_RES_1 = 0x00000008UL (value corresponding to ADC4 8 bits)
* @arg ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0 = 0x0000000CUL (value corresponding to ADC4 6 bits)
*/
#define __LL_ADC_RESOLUTION_ADC1_TO_ADC4(__RESOLUTION__) \
(((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
? ((LL_ADC_RESOLUTION_8B)) \
: ((((__RESOLUTION__)-1UL) & ADC_CFGR1_RES_Msk)) \
)
/**
* @brief Helper macro to convert ADC4 resolution bit values to ADC1 resolution.
* @note Example 1:
* __LL_ADC_RESOLUTION_ADC4_TO_ADC1((ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0))
* will return a data equivalent to "LL_ADC_RESOLUTION_6B".
* @note Example 2:
* __LL_ADC_RESOLUTION_ADC1_TO_ADC4((ADC_CFGR1_RES_0))
* will return a data equivalent to "LL_ADC_RESOLUTION_10B".
* @param __RESOLUTION__ This parameter can be one of the following values:
* @arg 0x00000000UL (value correspodning to ADC4 12 bits)
* @arg ADC_CFGR1_RES_0 = 0x00000004UL (value correspodning to ADC4 10 bits)
* @arg ADC_CFGR1_RES_1 = 0x00000008UL (value corresponding to ADC4 8 bits)
* @arg ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0 = 0x0000000CUL (value corresponding to ADC4 6 bits)
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
*/
#define __LL_ADC_RESOLUTION_ADC4_TO_ADC1(__RESOLUTION__) \
(((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
? ((LL_ADC_RESOLUTION_6B)) \
: ((((((__RESOLUTION__) >> ADC_CFGR1_RES_Pos) + 1UL) << ADC_CFGR1_RES_Pos) & ADC_CFGR1_RES_Msk)) \
)
/**
* @brief Helper macro to determine whether the selected channel
* corresponds to literal definitions of driver.
* @note The different literal definitions of ADC channels are:
* - ADC internal channel:
* LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
* - ADC external channel (channel connected to a GPIO pin):
* LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
* @note The channel parameter must be a value defined from literal
* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
* LL_ADC_CHANNEL_TEMPSENSOR, ...),
* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
* must not be a value from functions where a channel number is
* returned from ADC registers,
* because internal and external channels share the same channel
* number in ADC registers. The differentiation is made only with
* parameters definitions of driver.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VCORE (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
* (channel connected to a GPIO pin).
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
/**
* @brief Helper macro to convert a channel defined from parameter
* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
* LL_ADC_CHANNEL_TEMPSENSOR, ...),
* to its equivalent parameter definition of a ADC external channel
* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
* @note The channel parameter can be, additionally to a value
* defined from parameter definition of a ADC internal channel
* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
* a value defined from parameter definition of
* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
* or a value from functions where a channel number is returned
* from ADC registers.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VCORE (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
*/
#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/**
* @brief Helper macro to determine whether the internal channel
* selected is available on the ADC instance selected.
* @note The channel parameter must be a value defined from parameter
* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
* LL_ADC_CHANNEL_TEMPSENSOR, ...),
* must not be a value defined from parameter definition of
* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
* or a value from functions where a channel number is
* returned from ADC registers,
* because internal and external channels share the same channel
* number in ADC registers. The differentiation is made only with
* parameters definitions of driver.
* @param __ADC_INSTANCE__ ADC instance
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VCORE (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
* Value "1" if the internal channel selected is available on the ADC instance selected.
*/
#if defined(ADC2)
#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
((((__ADC_INSTANCE__) == ADC4) &&( ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \
((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \
((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \
) \
|| \
(((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2) \
&&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ) \
) \
)
#else
#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
((((__ADC_INSTANCE__) == ADC4) \
&&(((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC4) || \
((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC4) || \
((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC4) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT_ADC4) ) \
) \
|| \
(((__ADC_INSTANCE__) == ADC1) \
&&(((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) ) \
) \
)
#endif /* ADC2 */
/**
* @brief Helper macro to define ADC analog watchdog parameter:
* define a single channel to monitor with analog watchdog
* from sequencer channel and groups definition.
* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
* Example:
* LL_ADC_SetAnalogWDMonitChannels(
* ADC1, LL_ADC_AWD1,
* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VCORE (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/ADC2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* (1, 2) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
* @param __GROUP__ This parameter can be one of the following values:
* @arg @ref LL_ADC_GROUP_REGULAR
* @arg @ref LL_ADC_GROUP_INJECTED
* @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_AWD_DISABLE
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC4_REG (0)(2)
* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC4_REG (0)(2)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC4_REG (2)
* @arg @ref LL_ADC_AWD_CH_VBAT_ADC4_REG (2)
* @arg @ref LL_ADC_AWD_CH_VCORE_REG (2)
*
* (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
*/
#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
(((__GROUP__) == LL_ADC_GROUP_REGULAR) \
? (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) \
: \
((__GROUP__) == LL_ADC_GROUP_INJECTED) \
? (((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1SGL) \
: \
(((__CHANNEL__) & ADC_AWD_CHANNEL_MASK) | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) \
)
/**
* @brief Helper macro to set the value of ADC analog watchdog threshold high
* or low in function of ADC resolution, when ADC resolution is
* different of 14 bits in case of ADC1 and 12 bits in case of ADC4.
* @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
* Example, with a ADC resolution of 8 bits, to set the value of
* analog watchdog threshold high (on 8 bits):
* LL_ADC_SetAnalogWDThresholds
* (< ADCx param >,
* __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
* );
* @param __ADC_INSTANCE__ ADC instance
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B (1)
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B (2)
* @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 insatnce
* __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 insatnce
* @retval In case of ADC1 insatnce, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF
* In case of ADC4 insatnce, Value between Min_Data=0x000 and Max_Data=0xFFF
*
* (1): Only for ADC1 instance
* (2): Only for ADC4 insatnce
*/
#if defined (ADC2)
#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \
((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
? ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
: \
((__AWD_THRESHOLD__) << ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__)) \
>> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
)
#else
#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \
(((__ADC_INSTANCE__) == ADC1) \
? ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
: \
((__AWD_THRESHOLD__) << ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__)) \
>> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
)
#endif /* ADC2 */
/**
* @brief Helper macro to get the value of ADC analog watchdog threshold high
* or low in function of ADC resolution, when ADC resolution is
* different of 14 bits in case of ADC1 and 12 bits in case of ADC4.
* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
* Example, with a ADC resolution of 8 bits, to get the value of
* analog watchdog threshold high (on 8 bits):
* < threshold_value_8_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
* (LL_ADC_RESOLUTION_8B,
* LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
* );
* @param __ADC_INSTANCE__ ADC instance
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B (1)
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B (2)
* @param __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF, In case of ADC1 insatnce
* __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF, In case of ADC4 insatnce
* @retval In case of ADC1 insatnce, Value between Min_Data=0x000000 and Max_Data=0x1FFFFFF
* In case of ADC4 insatnce, Value between Min_Data=0x000 and Max_Data=0xFFF
*
* (1): Only for ADC1 instance
* (2): Only for ADC4 insatnce
*/
#if defined (ADC2)
#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \
((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
? ((__AWD_THRESHOLD__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
: \
((__AWD_THRESHOLD__) >> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__)) \
>> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
)
#else
#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_INSTANCE__, __ADC_RESOLUTION__, __AWD_THRESHOLD__) \
(((__ADC_INSTANCE__) == ADC1) \
? ((__AWD_THRESHOLD__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
: \
((__AWD_THRESHOLD__) >> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__)) \
>> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) \
)
#endif /* ADC2 */
/**
* @brief Helper macro to set the ADC calibration value with both single ended
* and differential modes calibration factors concatenated.
* @note To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().
* Example, to set calibration factors single ended to 0x55
* and differential ended to 0x2A:
* LL_ADC_SetCalibrationOffsetFactor(
* ADC1,
* __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
* @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
* @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
*/
#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
(((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_SINGLEDIFF_CALIB_F_BIT_D_POS) | (__CALIB_FACTOR_SINGLE_ENDED__))
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Helper macro to get the ADC multimode conversion data of ADC master
* or ADC slave from raw value with both ADC conversion data concatenated.
* @note This macro is intended to be used when multimode transfer by DMA
* is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
* In this case the transferred data need to processed with this macro
* to separate the conversion data of ADC master and ADC slave.
* @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_MASTER
* @arg @ref LL_ADC_MULTI_SLAVE
* @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
(((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Helper macro to select, from a ADC instance, to which ADC instance
* it has a dependence in multimode (ADC master of the corresponding
* ADC common instance).
* @note In case of device with multimode available and a mix of
* ADC instances compliant and not compliant with multimode feature,
* ADC instances not compliant with multimode feature are
* considered as master instances (do not depend to
* any other ADC instance).
* @param __ADCx__ ADC instance
* @retval __ADCx__ ADC instance master of the corresponding ADC common instance
*/
#if defined(ADC2)
#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
(((__ADCx__) == ADC2) ? (ADC1) : (__ADCx__))
#else
#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) (__ADCx__)
#endif /* ADC2 */
/**
* @brief Helper macro to select the ADC common instance
* to which is belonging the selected ADC instance.
* @note ADC common register instance can be used for:
* - Set parameters common to several ADC instances
* - Multimode (for devices with several ADC instances)
* Refer to functions having argument "ADCxy_COMMON" as parameter.
* @param __ADCx__ ADC instance
* @retval ADC common register instance
*/
#if defined(ADC2)
#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) ? (ADC12_COMMON) : (ADC4_COMMON))
#else
#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
(((__ADCx__) == ADC1) ? (ADC12_COMMON) : (ADC4_COMMON))
#endif /* ADC2 */
/**
* @brief Helper macro to check if all ADC instances sharing the same
* ADC common instance are disabled.
* @note This check is required by functions with setting conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* Refer to functions having argument "ADCxy_COMMON" as parameter.
* @note On devices with only 1 ADC common instance, parameter of this macro
* is useless and can be ignored (parameter kept for compatibility
* with devices featuring several ADC common instances).
* @param __ADCXY_COMMON__ ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Value "0" if all ADC instances sharing the same ADC common instance
* are disabled.
* Value "1" if at least one ADC instance sharing the same ADC common instance
* is enabled.
*/
#if defined(ADC2)
#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
(((__ADCXY_COMMON__) == ADC12_COMMON) ? (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) : (LL_ADC_IsEnabled(ADC4)))
#else
#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
(((__ADCXY_COMMON__) == ADC12_COMMON) ? (LL_ADC_IsEnabled(ADC1)) : (LL_ADC_IsEnabled(ADC4)))
#endif /* ADC2 */
/**
* @brief Helper macro to define the ADC conversion data full-scale digital
* value corresponding to the selected ADC resolution.
* @note ADC conversion data full-scale corresponds to voltage range
* determined by analog voltage references Vref+ and Vref-
* (refer to reference manual).
* @param __ADC_INSTANCE__ ADC instance
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
*/
#if defined(ADC2)
#define __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \
((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
?((0x3FFFUL) >> (((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) & 0x6UL)) \
: \
((0xFFFUL) >> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__) \
>> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) & 0x6UL)) \
)
#else
#define __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \
(((__ADC_INSTANCE__) == ADC1) \
?((0x3FFFUL) >> (((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) & 0x6UL)) \
: \
((0xFFFUL) >> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION__) \
>> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) & 0x6UL)) \
)
#endif /* ADC2 */
/**
* @brief Helper macro to convert the ADC conversion data from
* a resolution to another resolution.
* @param __ADC_INSTANCE__ ADC instance
* @param __DATA__ ADC conversion data to be converted
* @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
* This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B (1)
* @arg @ref LL_ADC_RESOLUTION_12B (2)
* @arg @ref LL_ADC_RESOLUTION_10B (2)
* @arg @ref LL_ADC_RESOLUTION_8B (2)
* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
* This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B (1)
* @arg @ref LL_ADC_RESOLUTION_12B (2)
* @arg @ref LL_ADC_RESOLUTION_10B (2)
* @arg @ref LL_ADC_RESOLUTION_8B (2)
* (1): Specific to ADC1 instance
* (2): Common to all instances but different bits positions
* @retval ADC conversion data to the requested resolution
*/
#if defined (ADC2)
#define __LL_ADC_CONVERT_DATA_RESOLUTION(__ADC_INSTANCE__, __DATA__,\
__ADC_RESOLUTION_CURRENT__,\
__ADC_RESOLUTION_TARGET__) \
((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
?((__DATA__) \
<< ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
>> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
: \
((__DATA__) \
<< ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION_CURRENT__)) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
>> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION_TARGET__)) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
)
#else
#define __LL_ADC_CONVERT_DATA_RESOLUTION(__ADC_INSTANCE__, __DATA__,\
__ADC_RESOLUTION_CURRENT__,\
__ADC_RESOLUTION_TARGET__) \
(((__ADC_INSTANCE__) == ADC1) \
?((__DATA__) \
<< ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
>> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
: \
((__DATA__) \
<< ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION_CURRENT__)) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
>> ((__LL_ADC_RESOLUTION_ADC1_TO_ADC4(__ADC_RESOLUTION_TARGET__)) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
)
#endif /* ADC2 */
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
* corresponding to a ADC conversion data (unit: digital value).
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __ADC_DATA__ ADC conversion data (resolution 16 bits)
* (unit: digital value).
* @param __ADC_INSTANCE__ ADC instance
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B (1)
* @arg @ref LL_ADC_RESOLUTION_12B (3)
* @arg @ref LL_ADC_RESOLUTION_10B (3)
* @arg @ref LL_ADC_RESOLUTION_8B (3)
* @arg @ref LL_ADC_RESOLUTION_6B (2)
* (1): Specific to ADC1 instance
* (2): Specific to ADC4 instance
* (3): Common to all instances but different bits positions
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__,\
__ADC_DATA__, \
__ADC_RESOLUTION__) \
((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
/ __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \
)
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
* (unit: mVolt) from ADC conversion data of internal voltage
* reference VrefInt.
* @note Computation is using VrefInt calibration value
* stored in system memory for each device during production.
* @note This voltage depends on user board environment: voltage level
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
* @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 16 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
* Otherwise, this macro performs the processing to scale
* ADC conversion data to 14 bits.
* @param __ADC_INSTANCE__ ADC instance
* @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)
* of internal voltage reference VrefInt (unit: digital value).
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B (1)
* @arg @ref LL_ADC_RESOLUTION_12B (3)
* @arg @ref LL_ADC_RESOLUTION_10B (3)
* @arg @ref LL_ADC_RESOLUTION_8B (3)
* @arg @ref LL_ADC_RESOLUTION_6B (2)
* (1): Specific to ADC1 instance
* (2): Specific to ADC4 instance
* (3): Common to all instances but different bits positions
* @retval Analog reference voltage (unit: mV)
*/
#if defined (ADC2)
#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__ADC_INSTANCE__, __VREFINT_ADC_DATA__, \
__ADC_RESOLUTION__) \
((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
?((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
/ __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__VREFINT_ADC_DATA__),\
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_14B) \
: \
((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
/ __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__VREFINT_ADC_DATA__),\
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_12B) \
)
#else
#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__ADC_INSTANCE__, __VREFINT_ADC_DATA__, \
__ADC_RESOLUTION__) \
(((__ADC_INSTANCE__) == ADC1) \
?((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
/ __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__VREFINT_ADC_DATA__),\
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_14B) \
: \
((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
/ __LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__VREFINT_ADC_DATA__),\
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_12B) \
)
#endif /* ADC2 */
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
* from ADC conversion data of internal temperature sensor.
* @note Computation is using temperature sensor calibration values
* stored in system memory for each device during production.
* @note Calculation formula:
* Temperature = ((TS_ADC_DATA - TS_CAL1)
* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
* with TS_ADC_DATA = temperature sensor raw data measured by ADC
* Avg_Slope = (TS_CAL2 - TS_CAL1)
* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
* TS_CAL1 = equivalent TS_ADC_DATA at temperature
* TEMP_DEGC_CAL1 (calibrated in factory)
* TS_CAL2 = equivalent TS_ADC_DATA at temperature
* TEMP_DEGC_CAL2 (calibrated in factory)
* Caution: Calculation relevancy under reserve that calibration
* parameters are correct (address and data).
* To calculate temperature using temperature sensor
* datasheet typical values (generic values less, therefore
* less accurate than calibrated values),
* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
* @note As calculation input, the analog reference voltage (Vref+) must be
* defined as it impacts the ADC LSB equivalent voltage.
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 14 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
* Otherwise, this macro performs the processing to scale
* ADC conversion data to 14 bits.
* @param __ADC_INSTANCE__ ADC instance
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
* temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
* sensor voltage has been measured.
* This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B (1)
* @arg @ref LL_ADC_RESOLUTION_12B (3)
* @arg @ref LL_ADC_RESOLUTION_10B (3)
* @arg @ref LL_ADC_RESOLUTION_8B (3)
* @arg @ref LL_ADC_RESOLUTION_6B (2)
* (1): Specific to ADC1 instance
* (2): Specific to ADC4 instance
* (3): Common to all instances but different bits positions
* @retval Temperature (unit: degree Celsius)
*/
#if defined (ADC2)
#define __LL_ADC_CALC_TEMPERATURE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__, \
__TEMPSENSOR_ADC_DATA__, \
__ADC_RESOLUTION__) \
((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
?(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__TEMPSENSOR_ADC_DATA__), \
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_14B) \
* (__VREFANALOG_VOLTAGE__)) \
/ TEMPSENSOR_CAL_VREFANALOG) \
- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
) + TEMPSENSOR_CAL1_TEMP \
) \
: \
(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__TEMPSENSOR_ADC_DATA__), \
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_12B) \
* (__VREFANALOG_VOLTAGE__)) \
/ TEMPSENSOR_CAL_VREFANALOG) \
- (int32_t) (*TEMPSENSOR_CAL1_ADDR >> 2 )) \
) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
) / (int32_t)((int32_t)(*TEMPSENSOR_CAL2_ADDR >> 2 ) - (int32_t)(*TEMPSENSOR_CAL1_ADDR >> 2) ) \
) + TEMPSENSOR_CAL1_TEMP \
) \
)
#else
#define __LL_ADC_CALC_TEMPERATURE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__, \
__TEMPSENSOR_ADC_DATA__, \
__ADC_RESOLUTION__) \
(((__ADC_INSTANCE__) == ADC1) \
?(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__TEMPSENSOR_ADC_DATA__), \
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_14B) \
* (__VREFANALOG_VOLTAGE__)) \
/ TEMPSENSOR_CAL_VREFANALOG) \
- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
) + TEMPSENSOR_CAL1_TEMP \
) \
: \
(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__ADC_INSTANCE__), (__TEMPSENSOR_ADC_DATA__), \
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_12B) \
* (__VREFANALOG_VOLTAGE__)) \
/ TEMPSENSOR_CAL_VREFANALOG) \
- (int32_t) (*TEMPSENSOR_CAL1_ADDR >> 2 )) \
) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
) / (int32_t)((int32_t)(*TEMPSENSOR_CAL2_ADDR >> 2 ) - (int32_t)(*TEMPSENSOR_CAL1_ADDR >> 2) ) \
) + TEMPSENSOR_CAL1_TEMP \
) \
)
#endif /* ADC2 */
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
* from ADC conversion data of internal temperature sensor.
* @note Computation is using temperature sensor typical values
* (refer to device datasheet).
* @note Calculation formula:
* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
* / Avg_Slope + CALx_TEMP
* with TS_ADC_DATA = temperature sensor raw data measured by ADC
* (unit: digital value)
* Avg_Slope = temperature sensor slope
* (unit: uV/Degree Celsius)
* TS_TYP_CALx_VOLT = temperature sensor digital value at
* temperature CALx_TEMP (unit: mV)
* Caution: Calculation relevancy under reserve the temperature sensor
* of the current device has characteristics in line with
* datasheet typical values.
* If temperature sensor calibration values are available on
* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
* temperature calculation will be more accurate using
* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
* @note As calculation input, the analog reference voltage (Vref+) must be
* defined as it impacts the ADC LSB equivalent voltage.
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @note ADC measurement data must correspond to a resolution of 14 bits
* (full scale digital value 4095). If not the case, the data must be
* preliminarily rescaled to an equivalent resolution of 14 bits.
* @param __ADC_INSTANCE__ ADC instance
* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
* (unit: uV/DegCelsius).
* On STM32U5, refer to device datasheet parameter "Avg_Slope".
* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
* (at temperature and Vref+ defined in parameters below) (unit: mV).
* On STM32U5, refer to device datasheet parameter "V30"
* (corresponding to TS_CAL1).
* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
* see parameter above) is corresponding (unit: mV)
* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
* This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B (1)
* @arg @ref LL_ADC_RESOLUTION_12B (3)
* @arg @ref LL_ADC_RESOLUTION_10B (3)
* @arg @ref LL_ADC_RESOLUTION_8B (3)
* @arg @ref LL_ADC_RESOLUTION_6B (2)
* (1): Specific to ADC1 instance
* (2): Specific to ADC4 instance
* (3): Common to all instances but different bits positions
* @retval Temperature (unit: degree Celsius)
*/
#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__ADC_INSTANCE__, __TEMPSENSOR_TYP_AVGSLOPE__, \
__TEMPSENSOR_TYP_CALX_V__, \
__TEMPSENSOR_CALX_TEMP__, \
__VREFANALOG_VOLTAGE__, \
__TEMPSENSOR_ADC_DATA__, \
__ADC_RESOLUTION__) \
((( ((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
/ __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) \
* 1000UL) \
- \
(int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
* 1000UL) \
) \
) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
* @{
*/
/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
* @{
*/
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Function to help to configure DMA transfer from ADC: retrieve the
* ADC register address from ADC instance and a list of ADC registers
* intended to be used (most commonly) with DMA transfer.
* @note These ADC registers are data registers:
* when ADC conversion data is available in ADC data registers,
* ADC generates a DMA transfer request.
* @note This macro is intended to be used with LL DMA driver, refer to
* function "LL_DMA_ConfigAddresses()".
* Example:
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
* (uint32_t)&< array or variable >,
* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
* @note For devices with several ADC: in multimode, some devices
* use a different data register outside of ADC instance scope
* (common data register). This macro manages this register difference,
* only ADC instance has to be set as parameter.
* @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr
* CDR RDATA_MST LL_ADC_DMA_GetRegAddr
* CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
* @param ADCx ADC instance
* @param RegisterValue This parameter can be one of the following values:
* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
*
* (1) Available on devices with several ADC instances.
* @retval ADC register address
*/
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t RegisterValue)
{
uint32_t data_reg_addr;
if (RegisterValue == LL_ADC_DMA_REG_REGULAR_DATA)
{
/* Retrieve address of register DR */
data_reg_addr = (uint32_t) &(ADCx->DR);
}
else /* (RegisterValue == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
{
/* Retrieve address of register CDR */
data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
}
return data_reg_addr;
}
#else
/**
* @brief Function to help to configure DMA transfer from ADC: retrieve the
* ADC register address from ADC instance and a list of ADC registers
* intended to be used (most commonly) with DMA transfer.
* @note These ADC registers are data registers:
* when ADC conversion data is available in ADC data registers,
* ADC generates a DMA transfer request.
* @note This macro is intended to be used with LL DMA driver, refer to
* function "LL_DMA_ConfigAddresses()".
* Example:
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
* (uint32_t)&< array or variable >,
* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
* @note For devices with several ADC: in multimode, some devices
* use a different data register outside of ADC instance scope
* (common data register). This macro manages this register difference,
* only ADC instance has to be set as parameter.
* @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr
* @param ADCx ADC instance
* @param RegisterValue This parameter can be one of the following values:
* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
* @retval ADC register address
*/
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t RegisterValue)
{
/* Prevent unused argument(s) compilation warning */
(void)(RegisterValue);
/* Retrieve address of register DR */
return (uint32_t) &(ADCx->DR);
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope:
* common to several ADC instances
* @{
*/
/**
* @brief Set parameter common to several ADC: Clock source and prescaler.
* @note On this STM32 series, if ADC group injected is used, some
* clock ratio constraints between ADC clock and AHB clock
* must be respected.
* Refer to reference manual.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
* ADC instance or by using helper macro helper macro
* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
* @rmtoll CCR CKMODE LL_ADC_SetCommonClock
* CCR PRESC LL_ADC_SetCommonClock
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param CommonClock This parameter can be one of the following values:
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
}
/**
* @brief Get parameter common to several ADC: Clock source and prescaler.
* @rmtoll CCR CKMODE LL_ADC_GetCommonClock
* CCR PRESC LL_ADC_GetCommonClock
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
}
/**
* @brief Set parameter common to several ADC: measurement path to
* internal channels (VrefInt, temperature sensor, ...).
* Add paths to the current configuration.
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
* @note Stabilization time of measurement path to internal channel:
* After enabling internal paths, before starting ADC conversion,
* a delay is required for internal voltage reference and
* temperature sensor stabilization time.
* Refer to device datasheet.
* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
* Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
* @note ADC internal channel sampling time constraint:
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
* ADC instance or by using helper macro helper macro
* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd
* CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd
* CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param PathInternal This parameter can be a combination of the following values:
* @arg @ref LL_ADC_PATH_INTERNAL_NONE
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
SET_BIT(ADCxy_COMMON->CCR, PathInternal);
}
/**
* @brief Set parameter common to several ADC: measurement path to
* internal channels (VrefInt, temperature sensor, ...).
* Remove paths to the current configuration.
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
* ADC instance or by using helper macro helper macro
* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem
* CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem
* CCR VBATEN LL_ADC_SetCommonPathInternalChRem
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param PathInternal This parameter can be a combination of the following values:
* @arg @ref LL_ADC_PATH_INTERNAL_NONE
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
}
/**
* @brief Set parameter common to several ADC: measurement path to internal
* channels (VrefInt, temperature sensor, ...).
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
* @note Stabilization time of measurement path to internal channel:
* After enabling internal paths, before starting ADC conversion,
* a delay is required for internal voltage reference and
* temperature sensor stabilization time.
* Refer to device datasheet.
* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
* @note ADC internal channel sampling time constraint:
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
* ADC instance or by using helper macro helper macro
* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh
* CCR VSENSESEL LL_ADC_SetCommonPathInternalCh
* CCR VBATEN LL_ADC_SetCommonPathInternalCh
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param PathInternal This parameter can be a combination of the following values:
* @arg @ref LL_ADC_PATH_INTERNAL_NONE
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN, PathInternal);
}
/**
* @brief Get parameter common to several ADC: measurement path to internal
* channels (VrefInt, temperature sensor, ...).
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
* @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh
* CCR VSENSESEL LL_ADC_GetCommonPathInternalCh
* CCR VBATEN LL_ADC_GetCommonPathInternalCh
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be a combination of the following values:
* @arg @ref LL_ADC_PATH_INTERNAL_NONE
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSEEN | ADC_CCR_VBATEN));
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
* @{
*/
/**
* @brief Set ADC calibration factor in the mode single-ended
* or differential (for devices with differential mode available).
* @note This function is intended to set calibration parameters
* without having to perform a new calibration using
* @ref LL_ADC_StartCalibration().
* @note For devices with differential mode available:
* Calibration of offset is specific to each of
* single-ended and differential modes
* (calibration factor must be specified for each of these
* differential modes, if used afterwards and if the application
* requires their calibration).
* Calibration of linearity is common to both
* single-ended and differential modes
* (calibration factor can be specified only once).
* @note In case of setting calibration factors of both modes single ended
* and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
* both calibration factors must be concatenated.
* To perform this processing, use helper macro
* @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled, without calibration on going, without conversion
* on going on group regular.
* @param ADCx ADC instance
* @param SingleDiff This parameter can be one of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
* @param CalibrationFactor Value between Min_Data=0x0000 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff,
uint32_t CalibrationFactor)
{
if (ADCx == ADC1)
{
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF);
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, (0UL << ADC_CR_CALINDEX0_Pos)); /* CalibIndex == 0*/
MODIFY_REG(ADCx->CALFACT2,
SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) \
>> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) \
& ~(SingleDiff & ADC_CALFACT2_CALFACT_S)));
SET_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
}
else
{
MODIFY_REG(ADCx->CALFACT, ADC4_CALFACT_CALFACT, CalibrationFactor);
}
}
/**
* @brief Get ADC calibration factor in the mode single-ended
* or differential (for devices with differential mode available).
* @note Calibration factors are set by hardware after performing
* a calibration run using function @ref LL_ADC_StartCalibration().
* @note For devices with differential mode available:
* Calibration of offset is specific to each of
* single-ended and differential modes
* Calibration of linearity is common to both
* single-ended and differential modes
* @param ADCx ADC instance
* @param SingleDiff This parameter can be one of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval Value between Min_Data=0x0000 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
{
/* Retrieve bits with position in register depending on parameter */
/* "SingleDiff". */
/* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
/* containing other bits reserved for other purpose. */
if (ADCx == ADC1)
{
uint32_t temp_CalibOffset;
MODIFY_REG(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF, ADC_CALFACT_CAPTURE_COEF);
MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, (0UL << ADC_CR_CALINDEX0_Pos)); /* CalibIndex == 0*/
temp_CalibOffset = (READ_BIT(ADCx->CALFACT2, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) \
>> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
return temp_CalibOffset;
}
else
{
return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC4_CALFACT_CALFACT));
}
}
/**
* @brief Set ADC Linear calibration factor in the mode single-ended.
* @note This function is intended to set linear calibration parameters
* without having to perform a new calibration using
* @ref LL_ADC_StartCalibration().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled, without calibration on going, without conversion
* on going on group regular.
* @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
* CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor
* @param ADCx ADC instance
* @param LinearityWord This parameter can be one of the following values:
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX1
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX2
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX3
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX4
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX5
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX6
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX7
* @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord,
uint32_t CalibrationFactor)
{
/* Before using this!
Make sure ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing).
--> This should be checked by application.
*/
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF);
MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0),
LinearityWord); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/
MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_CALFACT, CalibrationFactor);
SET_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
}
/**
* @brief Get ADC Linear calibration factor in the mode single-ended.
* @note Calibration factors are set by hardware after performing
* a calibration run using function @ref LL_ADC_StartCalibration().
* @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
* CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor
* @param ADCx ADC instance
* @param LinearityWord This parameter can be one of the following values:
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX1
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX2
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX3
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX4
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX5
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX6
* @arg @ref LL_ADC_CALIB_LINEARITY_INDEX7
* @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)
{
uint32_t temp_calib_linearity;
SET_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_LATCH_COEF);
MODIFY_REG(ADCx->CR, (ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0),
LinearityWord); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/
temp_calib_linearity = (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_CALFACT_Msk));
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CAPTURE_COEF);
return temp_calib_linearity;
}
/**
* @brief Set ADC resolution.
* Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @note if ADC4 instance __LL_ADC_RESOLUTION_ADC1_TO_ADC4() is used to
* convert ADC1 to ADC4 resolution
* @rmtoll CFGR RES LL_ADC_SetResolution
* @param ADCx ADC instance
* @param Resolution This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B (1)
* @arg @ref LL_ADC_RESOLUTION_12B (3)
* @arg @ref LL_ADC_RESOLUTION_10B (3)
* @arg @ref LL_ADC_RESOLUTION_8B (3)
* @arg @ref LL_ADC_RESOLUTION_6B (2)
* (1): Specific to ADC1 instance
* (2): Specific to ADC4 instance
* (3): Common to all instances but different bits positions
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
{
if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
}
else /* ADCx == ADC4 */
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, __LL_ADC_RESOLUTION_ADC1_TO_ADC4(Resolution));
}
}
/**
* @brief Get ADC resolution.
* Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
* @rmtoll CFGR RES LL_ADC_GetResolution
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_14B (1)
* @arg @ref LL_ADC_RESOLUTION_12B (3)
* @arg @ref LL_ADC_RESOLUTION_10B (3)
* @arg @ref LL_ADC_RESOLUTION_8B (3)
* @arg @ref LL_ADC_RESOLUTION_6B (2)
* (1): Specific to ADC1 instance
* (2): Specific to ADC4 instance
* (3): Common to all instances but different bits positions
*/
__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
{
if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
}
else /* ADCx == ADC4 */
{
uint32_t temp_Resolution;
temp_Resolution = (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
if (temp_Resolution == (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0))
{
return LL_ADC_RESOLUTION_6B;
}
else
{
return __LL_ADC_RESOLUTION_ADC4_TO_ADC1(temp_Resolution);
}
}
}
/**
* @brief Set ADC conversion data alignment.
* @note Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
* @param ADCx ADC instance
* @param DataAlignment This parameter can be one of the following values:
* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
* @arg @ref LL_ADC_DATA_ALIGN_LEFT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
{
MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_ALIGN, DataAlignment);
}
/**
* @brief Get ADC conversion data alignment.
* @note Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
* @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
* @arg @ref LL_ADC_DATA_ALIGN_LEFT
*/
__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_ALIGN));
}
/**
* @brief Set ADC low power mode.
* @note Description of ADC low power modes:
* - ADC low power mode "auto wait": Dynamic low power mode,
* ADC conversions occurrences are limited to the minimum necessary
* in order to reduce power consumption.
* New ADC conversion starts only when the previous
* unitary conversion data (for ADC group regular)
* or previous sequence conversions data (for ADC group injected)
* has been retrieved by user software.
* In the meantime, ADC remains idle: does not performs any
* other conversion.
* This mode allows to automatically adapt the ADC conversions
* triggers to the speed of the software that reads the data.
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
* - It is not recommended to use with interruption or DMA
* since these modes have to clear immediately the EOC flag
* (by CPU to free the IRQ pending event or by DMA).
* Auto wait will work but fort a very short time, discarding
* its intended benefit (except specific case of high load of CPU
* or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
* retrieve ADC conversion data. This will trig another
* ADC conversion start.
* - ADC low power mode "auto power-off" (feature available on
* this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
* the ADC automatically powers-off after a conversion and
* automatically wakes up when a new conversion is triggered
* (with startup time between trigger and start of sampling).
* This feature can be combined with low power mode "auto wait".
* @note With ADC low power mode "auto wait", the ADC conversion data read
* is corresponding to previous ADC conversion start, independently
* of delay during which ADC was idle.
* Therefore, the ADC conversion data may be outdated: does not
* correspond to the current voltage level on the selected
* ADC channel.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
* @param ADCx ADC instance
* @param LowPowerMode This parameter can be one of the following values:
* @arg @ref LL_ADC_LP_MODE_NONE
* @arg @ref LL_ADC_LP_AUTOWAIT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
{
if (ADCx != ADC4) /* ADC1 or ADC2 */
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_AUTDLY, LowPowerMode);
}
else
{
MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_WAIT, LowPowerMode);
MODIFY_REG(ADCx->PW, ADC4_PW_AUTOFF, LowPowerMode);
}
}
/**
* @brief Get ADC low power mode:
* @note Description of ADC low power modes:
* - ADC low power mode "auto wait": Dynamic low power mode,
* ADC conversions occurrences are limited to the minimum necessary
* in order to reduce power consumption.
* New ADC conversion starts only when the previous
* unitary conversion data (for ADC group regular)
* or previous sequence conversions data (for ADC group injected)
* has been retrieved by user software.
* In the meantime, ADC remains idle: does not performs any
* other conversion.
* This mode allows to automatically adapt the ADC conversions
* triggers to the speed of the software that reads the data.
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
* - It is not recommended to use with interruption or DMA
* since these modes have to clear immediately the EOC flag
* (by CPU to free the IRQ pending event or by DMA).
* Auto wait will work but fort a very short time, discarding
* its intended benefit (except specific case of high load of CPU
* or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
* retrieve ADC conversion data. This will trig another
* ADC conversion start.
* - ADC low power mode "auto power-off" (feature available on
* this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
* the ADC automatically powers-off after a conversion and
* automatically wakes up when a new conversion is triggered
* (with startup time between trigger and start of sampling).
* This feature can be combined with low power mode "auto wait".
* @note With ADC low power mode "auto wait", the ADC conversion data read
* is corresponding to previous ADC conversion start, independently
* of delay during which ADC was idle.
* Therefore, the ADC conversion data may be outdated: does not
* correspond to the current voltage level on the selected
* ADC channel.
* @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_LP_MODE_NONE
* @arg @ref LL_ADC_LP_AUTOWAIT
*/
__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
{
if (ADCx != ADC4) /* ADC1 or ADC2 */
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_AUTDLY));
}
else
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_WAIT));
}
}
/**
* @brief Set ADC selected offset number 1, 2, 3 or 4.
* @note This function set the 2 items of offset configuration:
* - ADC channel to which the offset programmed will be applied
* (independently of channel mapped on ADC group regular
* or group injected)
* - Offset level (offset to be subtracted from the raw
* converted data).
* @note Caution: Offset format is dependent to ADC resolution:
* offset has to be left-aligned on bit 11, the LSB (right bits)
* are set to 0.
* @note This function enables the offset, by default. It can be forced
* to disable state using function LL_ADC_SetOffsetState().
* @note If a channel is mapped on several offsets numbers, only the offset
* with the lowest value is considered for the subtraction.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @note On STM32U5, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
* @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset
* OFR1 OFFSET1 LL_ADC_SetOffset
* OFR1 OFFSET1_EN LL_ADC_SetOffset
* OFR2 OFFSET2_CH LL_ADC_SetOffset
* OFR2 OFFSET2 LL_ADC_SetOffset
* OFR2 OFFSET2_EN LL_ADC_SetOffset
* OFR3 OFFSET3_CH LL_ADC_SetOffset
* OFR3 OFFSET3 LL_ADC_SetOffset
* OFR3 OFFSET3_EN LL_ADC_SetOffset
* OFR4 OFFSET4_CH LL_ADC_SetOffset
* OFR4 OFFSET4 LL_ADC_SetOffset
* OFR4 OFFSET4_EN LL_ADC_SetOffset
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg,
ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) << 1UL) | OffsetLevel);
}
/**
* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
* Channel to which the offset programmed will be applied
* (independently of channel mapped on ADC group regular
* or group injected)
* @note Usage of the returned channel number:
* - To reinject this channel into another function LL_ADC_xxx:
* the returned channel number is only partly formatted on definition
* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
* with parts of literals LL_ADC_CHANNEL_x or using
* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Then the selected literal LL_ADC_CHANNEL_x can be used
* as parameter for another function.
* - To get the channel number in decimal format:
* process the returned value with the helper macro
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* @note On STM32U5, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
* @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel
* OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel
* OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel
* OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* (1, 2) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
}
/**
* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
* Offset level (offset to be subtracted from the raw
* converted data).
* @note Caution: Offset format is dependent to ADC resolution:
* offset has to be left-aligned on bit 11, the LSB (right bits)
* are set to 0.
* @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel
* OFR2 OFFSET2 LL_ADC_GetOffsetLevel
* OFR3 OFFSET3 LL_ADC_GetOffsetLevel
* OFR4 OFFSET4 LL_ADC_GetOffsetLevel
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
}
/**
* @brief Set for the ADC selected offset number 1, 2, 3 or 4:
* choose offset sign.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign
* OFR2 OFFSETPOS LL_ADC_SetOffsetSign
* OFR3 OFFSETPOS LL_ADC_SetOffsetSign
* OFR4 OFFSETPOS LL_ADC_SetOffsetSign
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @param OffsetSign This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
* @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
{
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg, ADC_OFR1_OFFSETPOS, OffsetSign);
}
/**
* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
* offset sign if positive or negative.
* @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign
* OFR2 OFFSETPOS LL_ADC_GetOffsetSign
* OFR3 OFFSETPOS LL_ADC_GetOffsetSign
* OFR4 OFFSETPOS LL_ADC_GetOffsetSign
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
* @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
}
/**
* @brief Set Signed saturation for the ADC selected offset number 1, 2, 3 or 4:
* signed offset saturation if enabled or disabled.
* @rmtoll OFR1 SSAT LL_ADC_SetOffsetSignedSaturation
* OFR2 SSAT LL_ADC_SetOffsetSignedSaturation
* OFR3 SSAT LL_ADC_SetOffsetSignedSaturation
* OFR4 SSAT LL_ADC_SetOffsetSignedSaturation
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @param OffsetSignedSaturation This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
* @retval Returned None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
uint32_t OffsetSignedSaturation)
{
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg, ADC_OFR1_SSAT, OffsetSignedSaturation);
}
/**
* @brief Get Signed saturation for the ADC selected offset number 1, 2, 3 or 4:
* signed offset saturation if enabled or disabled.
* @rmtoll OFR1 SSAT LL_ADC_GetOffsetSignedSaturation
* OFR2 SSAT LL_ADC_GetOffsetSignedSaturation
* OFR3 SSAT LL_ADC_GetOffsetSignedSaturation
* OFR4 SSAT LL_ADC_GetOffsetSignedSaturation
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSAT);
}
/**
* @brief Set Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4:
* signed offset saturation if enabled or disabled.
* @rmtoll OFR1 USAT LL_ADC_SetOffsetUnsignedSaturation
* OFR2 USAT LL_ADC_SetOffsetUnsignedSaturation
* OFR3 USAT LL_ADC_SetOffsetUnsignedSaturation
* OFR4 USAT LL_ADC_SetOffsetUnsignedSaturation
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @param OffsetUnsignedSaturation This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE
* @retval Returned None
*/
__STATIC_INLINE void LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety,
uint32_t OffsetUnsignedSaturation)
{
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg, ADC_OFR1_USAT, OffsetUnsignedSaturation);
}
/**
* @brief Get Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4:
* signed offset saturation if enabled or disabled.
* @rmtoll OFR1 USAT LL_ADC_GetOffsetUnsignedSaturation
* OFR2 USAT LL_ADC_GetOffsetUnsignedSaturation
* OFR3 USAT LL_ADC_GetOffsetUnsignedSaturation
* OFR4 USAT LL_ADC_GetOffsetUnsignedSaturation
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_UNSIGNED_SATURATION_DISABLE
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_USAT);
}
/**
* @brief Set ADC gain compensation.
* @note This function set the gain compensation coefficient
* that is applied to raw converted data using the formula:
* DATA = DATA(raw) * (gain compensation coef) / 4096
* @note This function enables the gain compensation if given
* coefficient is above 0, otherwise it disables it.
* @note Gain compensation when enabled is applied to all channels.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation
* CFGR2 GCOMP LL_ADC_SetGainCompensation
* @param ADCx ADC instance
* @param GainCompensation This parameter can be:
* 0 Gain compensation will be disabled and value set to 0
* 1 -> 16393 Gain compensation will be enabled with specified value
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
{
MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_GCOMP_GCOMP_Pos);
}
/**
* @brief Get the ADC gain compensation value
* @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation
* CFGR2 GCOMP LL_ADC_GetGainCompensation
* @param ADCx ADC instance
* @retval Returned value can be:
* 0 Gain compensation is disabled
* 1 -> 16393 Gain compensation is enabled with returned value
*/
__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMP) == ADC_GCOMP_GCOMP) \
? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
}
/**
* @}
*/
/**
* @brief Set sampling time common to a group of channels.
* @note Unit: ADC clock cycles.
* @note On this STM32 series, sampling time scope is on ADC instance:
* Sampling time common to all channels.
* (on some other STM32 families, sampling time is channel wise)
* @note In case of internal channel (VrefInt, TempSensor, ...) to be
* converted:
* sampling time constraints must be respected (sampling time can be
* adjusted in function of ADC clock frequency and sampling time
* setting).
* Refer to device datasheet for timings values (parameters TS_vrefint,
* TS_temp, ...).
* @note Conversion time is the addition of sampling time and processing time.
* On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
* - 6.5 ADC clock cycles at ADC resolution 6 bits
* @note In case of ADC conversion of internal channel (VrefInt,
* temperature sensor, ...), a sampling time minimum value
* is required.
* Refer to device datasheet.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @note Applicable only on ADC4 instance
* @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels
* @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
* @param ADCx ADC instance
* @param SamplingTimeY This parameter can be one of the following values:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
* @param SamplingTime This parameter can be one of the following values:
* @arg @ref LL_ADC4_SAMPLINGTIME_1CYCLE_5
* @arg @ref LL_ADC4_SAMPLINGTIME_3CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_7CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_12CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_19CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_39CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_79CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_160CYCLES_5
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
uint32_t SamplingTime)
{
MODIFY_REG(ADCx->SMPR1,
ADC4_SMPR_SMP1 << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK),
SamplingTime << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK));
}
/**
* @brief Get sampling time common to a group of channels.
* @note Unit: ADC clock cycles.
* @note On this STM32 series, sampling time scope is on ADC instance:
* Sampling time common to all channels.
* (on some other STM32 families, sampling time is channel wise)
* @note Conversion time is the addition of sampling time and processing time.
* Refer to reference manual for ADC processing time of
* this STM32 series.
* @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels
* @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
* @param ADCx ADC instance (ADC4 for this device)
* @param SamplingTimeY This parameter can be one of the following values:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC4_SAMPLINGTIME_1CYCLE_5
* @arg @ref LL_ADC4_SAMPLINGTIME_3CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_7CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_12CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_19CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_39CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_79CYCLES_5
* @arg @ref LL_ADC4_SAMPLINGTIME_160CYCLES_5
*/
__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
{
return (uint32_t)((READ_BIT(ADCx->SMPR1, ADC4_SMPR_SMP1 << (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK)))
>> (SamplingTimeY & ADC4_SAMPLING_TIME_SMP_SHIFT_MASK));
}
/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
* @{
*/
/**
* @brief Set ADC group regular conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
* In case of need to modify trigger edge, use
* function @ref LL_ADC_REG_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource
* CFGR EXTEN LL_ADC_REG_SetTriggerSource
* @param ADCx ADC instance
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
* @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
* @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
* @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
}
else /* ADCx == ADC4 */
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC4_CFGR1_EXTSEL, TriggerSource);
}
}
/**
* @brief Get ADC group regular conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note To determine whether group regular trigger source is
* internal (SW start) or external, without detail
* of which peripheral is selected as external trigger,
* (equivalent to
* "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
* use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource
* CFGR EXTEN LL_ADC_REG_GetTriggerSource
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
* @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1
* @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_CH1
* @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_CH1
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
{
if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
{
__IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
/* to match with triggers literals definition. */
return ((trigger_source
& (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
| ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
);
}
else /* ADCx == ADC4 */
{
__IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC4_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
/* to match with triggers literals definition. */
return ((trigger_source
& (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC4_CFGR1_EXTSEL)
| ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
);
}
}
/**
* @brief Get ADC group regular conversion trigger source internal (SW start)
* or external.
* @note In case of group regular trigger source set to external trigger,
* to determine which peripheral is selected as external trigger,
* use function @ref LL_ADC_REG_GetTriggerSource().
* @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
}
/**
* @brief Set ADC group regular conversion trigger polarity.
* @note Applicable only for trigger source set to external trigger.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
* @param ADCx ADC instance
* @param ExternalTriggerEdge This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
}
/**
* @brief Get ADC group regular conversion trigger polarity.
* @note Applicable only for trigger source set to external trigger.
* @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
}
/**
* @brief Set ADC trigger frequency mode.
* @note ADC trigger frequency mode must be set to low frequency when
* a duration is exceeded before ADC conversion start trigger event
* (between ADC enable and ADC conversion start trigger event
* or between two ADC conversion start trigger event).
* Duration value: Refer to device datasheet, parameter "tIdle".
* @note When ADC trigger frequency mode is set to low frequency,
* some rearm cycles are inserted before performing ADC conversion
* start, inducing a delay of 2 ADC clock cycles.
* @note Usage of ADC trigger frequency mode with ADC low power mode:
* - Low power mode auto wait: Only the first ADC conversion
* start trigger inserts the rearm delay.
* - Low power mode auto power-off: ADC trigger frequency mode
* is discarded.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
* @param ADCx ADC instance
* @param TriggerFrequencyMode This parameter can be one of the following values:
* @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
* @arg @ref LL_ADC_TRIGGER_FREQ_LOW
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
{
if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
{
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, (TriggerFrequencyMode >> 2U));
}
else /* ADCx == ADC4 */
{
MODIFY_REG(ADCx->CFGR2, ADC4_CFGR2_LFTRIG, TriggerFrequencyMode);
}
}
/**
* @brief Get ADC trigger frequency mode.
* @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
* @arg @ref LL_ADC_TRIGGER_FREQ_LOW
*/
__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx)
{
if (ADCx != ADC4) /* ADCx == ADC1 or ADC2 */
{
return (uint32_t)((READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)) << 2U);
}
else /* ADCx == ADC4 */
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_LFTRIG));
}
}
/**
* @brief Set ADC sampling mode.
* @note This function set the ADC conversion sampling mode
* @note This mode applies to regular group only.
* @note Set sampling mode is applied to all conversion of regular group.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode
* CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
* @param ADCx ADC instance
* @param SamplingMode This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
* @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
* @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
{
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
}
/**
* @brief Get the ADC sampling mode
* @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode
* CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
* @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
* @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
}
/**
* @brief Start ADC sampling phase for sampling time trigger mode
* @note This function is relevant only when
* - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
* using @ref LL_ADC_REG_SetSamplingMode
* - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
* without ADC disable command on going.
* @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
}
/**
* @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
* @note This function is relevant only when
* - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
* using @ref LL_ADC_REG_SetSamplingMode
* - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
* - @ref LL_ADC_REG_StartSamplingPhase has been called to start
* the sampling phase
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
* without ADC disable command on going.
* @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
}
/**
* @brief Set ADC group regular sequencer configuration flexibility.
* @note On this STM32 series, ADC group regular sequencer both modes
* "fully configurable" or "not fully configurable" are
* available:
* - sequencer configured to fully configurable:
* sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function
* @ref LL_ADC_REG_SetSequencerLength().
* - sequencer configured to not fully configurable:
* sequencer length and each rank affectation to a channel
* are fixed by channel HW number.
* Refer to description of function
* @ref LL_ADC_REG_SetSequencerChannels().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
* @param ADCx ADC instance
* @param Configurability This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_FIXED
* @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
* @retval None
* @note On this STM32U5 series, this is applicable on ADC4 only.
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
{
MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD, Configurability);
}
/**
* @brief Get ADC group regular sequencer configuration flexibility.
* @note On this STM32 series, ADC group regular sequencer both modes
* "fully configurable" or "not fully configurable" are
* available:
* - sequencer configured to fully configurable:
* sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function
* @ref LL_ADC_REG_SetSequencerLength().
* - sequencer configured to not fully configurable:
* sequencer length and each rank affectation to a channel
* are fixed by channel HW number.
* Refer to description of function
* @ref LL_ADC_REG_SetSequencerChannels().
* @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_FIXED
* @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
* @note On this STM32U5 series, this is applicable on ADC4 only.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_CHSELRMOD));
}
/**
* @brief Set ADC group regular sequencer length and scan direction.
* @note Description of ADC group regular sequencer features:
* - For devices with sequencer fully configurable
* (function "LL_ADC_REG_SetSequencerRanks()" available):
* sequencer length and each rank affectation to a channel
* are configurable.
* This function performs configuration of:
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerRanks()".
* - For devices with sequencer not fully configurable
* (function "LL_ADC_REG_SetSequencerChannels()" available):
* sequencer length and each rank affectation to a channel
* are defined by channel number.
* This function performs configuration of:
* - Sequence length: Number of ranks in the scan sequence is
* defined by number of channels set in the sequence,
* rank of each channel is fixed by channel HW number.
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from lowest channel number to
* highest channel number).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerChannels()".
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
* @param ADCx ADC instance
* @param SequencerNbRanks This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
if (ADCx != ADC4) /* ADC1 or ADC2 */
{
MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
}
else
{
SET_BIT(ADCx->CHSELR, SequencerNbRanks);
}
}
/**
* @brief Get ADC group regular sequencer length and scan direction.
* @note Description of ADC group regular sequencer features:
* - For devices with sequencer fully configurable
* (function "LL_ADC_REG_SetSequencerRanks()" available):
* sequencer length and each rank affectation to a channel
* are configurable.
* This function retrieves:
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerRanks()".
* - For devices with sequencer not fully configurable
* (function "LL_ADC_REG_SetSequencerChannels()" available):
* sequencer length and each rank affectation to a channel
* are defined by channel number.
* This function retrieves:
* - Sequence length: Number of ranks in the scan sequence is
* defined by number of channels set in the sequence,
* rank of each channel is fixed by channel HW number.
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from lowest channel number to
* highest channel number).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerChannels()".
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
* @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
{
if (ADCx != ADC4) /* ADC1 or ADC2 */
{
return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
}
else
{
uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
uint32_t rank_index;
uint32_t rank_shifted;
/* Parse register for end of sequence identifier */
/* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
(ADC_CHSELR_SQ2), value "4" to length of end of sequence
identifier (0xF)*/
for (rank_index = 0UL; rank_index <= (28U - 4U); rank_index += 4U)
{
rank_shifted = (uint32_t)(0xF0UL << rank_index);
if ((channels_ranks & rank_shifted) == rank_shifted)
{
sequencer_length = rank_shifted;
break;
}
}
return sequencer_length;
}
}
/**
* @brief Set ADC group regular sequencer discontinuous mode:
* sequence subdivided and scan conversions interrupted every selected
* number of ranks.
* @note It is not possible to enable both ADC group regular
* continuous mode and sequencer discontinuous mode.
* @note It is not possible to enable both ADC auto-injected mode
* and ADC group regular sequencer discontinuous mode.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont
* CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
* @param ADCx ADC instance
* @param SeqDiscont This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM, SeqDiscont);
}
/**
* @brief Get ADC group regular sequencer discontinuous mode:
* sequence subdivided and scan conversions interrupted every selected
* number of ranks.
* @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont
* CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM));
}
/**
* @brief Set ADC group regular sequence: channel on the selected
* scan sequence rank.
* @note This function performs configuration of:
* - Channels ordering into each rank of scan sequence:
* whatever channel can be placed into whatever rank.
* @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks
* SQR1 SQ2 LL_ADC_REG_SetSequencerRanks
* SQR1 SQ3 LL_ADC_REG_SetSequencerRanks
* SQR1 SQ4 LL_ADC_REG_SetSequencerRanks
* SQR2 SQ5 LL_ADC_REG_SetSequencerRanks
* SQR2 SQ6 LL_ADC_REG_SetSequencerRanks
* SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
* SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
* SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
* SQR3 SQ10 LL_ADC_REG_SetSequencerRanks
* SQR3 SQ11 LL_ADC_REG_SetSequencerRanks
* SQR3 SQ12 LL_ADC_REG_SetSequencerRanks
* SQR3 SQ13 LL_ADC_REG_SetSequencerRanks
* SQR3 SQ14 LL_ADC_REG_SetSequencerRanks
* SQR4 SQ15 LL_ADC_REG_SetSequencerRanks
* SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_RANK_1
* @arg @ref LL_ADC_REG_RANK_2
* @arg @ref LL_ADC_REG_RANK_3
* @arg @ref LL_ADC_REG_RANK_4
* @arg @ref LL_ADC_REG_RANK_5
* @arg @ref LL_ADC_REG_RANK_6
* @arg @ref LL_ADC_REG_RANK_7
* @arg @ref LL_ADC_REG_RANK_8
* @arg @ref LL_ADC_REG_RANK_9
* @arg @ref LL_ADC_REG_RANK_10
* @arg @ref LL_ADC_REG_RANK_11
* @arg @ref LL_ADC_REG_RANK_12
* @arg @ref LL_ADC_REG_RANK_13
* @arg @ref LL_ADC_REG_RANK_14
* @arg @ref LL_ADC_REG_RANK_15
* @arg @ref LL_ADC_REG_RANK_16
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
/* Set bits with content of parameter "Channel" with bits position */
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
if (ADCx != ADC4) /* ADC1 or ADC2 */
{
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) \
>> ADC_SQRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
<< (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
else
{
MODIFY_REG(ADCx->CHSELR,
ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
(__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)));
}
}
/**
* @brief Get ADC group regular sequence: channel on the selected
* scan sequence rank.
* @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note Usage of the returned channel number:
* - To reinject this channel into another function LL_ADC_xxx:
* the returned channel number is only partly formatted on definition
* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
* with parts of literals LL_ADC_CHANNEL_x or using
* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Then the selected literal LL_ADC_CHANNEL_x can be used
* as parameter for another function.
* - To get the channel number in decimal format:
* process the returned value with the helper macro
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks
* SQR1 SQ2 LL_ADC_REG_GetSequencerRanks
* SQR1 SQ3 LL_ADC_REG_GetSequencerRanks
* SQR1 SQ4 LL_ADC_REG_GetSequencerRanks
* SQR2 SQ5 LL_ADC_REG_GetSequencerRanks
* SQR2 SQ6 LL_ADC_REG_GetSequencerRanks
* SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
* SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
* SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
* SQR3 SQ10 LL_ADC_REG_GetSequencerRanks
* SQR3 SQ11 LL_ADC_REG_GetSequencerRanks
* SQR3 SQ12 LL_ADC_REG_GetSequencerRanks
* SQR3 SQ13 LL_ADC_REG_GetSequencerRanks
* SQR3 SQ14 LL_ADC_REG_GetSequencerRanks
* SQR4 SQ15 LL_ADC_REG_GetSequencerRanks
* SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_RANK_1
* @arg @ref LL_ADC_REG_RANK_2
* @arg @ref LL_ADC_REG_RANK_3
* @arg @ref LL_ADC_REG_RANK_4
* @arg @ref LL_ADC_REG_RANK_5
* @arg @ref LL_ADC_REG_RANK_6
* @arg @ref LL_ADC_REG_RANK_7
* @arg @ref LL_ADC_REG_RANK_8
* @arg @ref LL_ADC_REG_RANK_9
* @arg @ref LL_ADC_REG_RANK_10
* @arg @ref LL_ADC_REG_RANK_11
* @arg @ref LL_ADC_REG_RANK_12
* @arg @ref LL_ADC_REG_RANK_13
* @arg @ref LL_ADC_REG_RANK_14
* @arg @ref LL_ADC_REG_RANK_15
* @arg @ref LL_ADC_REG_RANK_16
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* (1, 2) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
if (ADCx != ADC4) /* ADC1 or ADC2 */
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) \
>> ADC_SQRX_REGOFFSET_POS));
return (uint32_t)((READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
);
}
else
{
return (uint32_t)((READ_BIT(ADCx->CHSELR,
ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
);
}
}
/**
* @brief Set ADC group regular sequencer scan direction.
* @note On this STM32 series, parameter relevant only is sequencer is set
* to mode not fully configurable,
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @note On some other STM32 families, this setting is not available and
* the default scan direction is forward.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
* @param ADCx ADC instance
* @param ScanDirection This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
{
MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_SCANDIR, ScanDirection);
}
/**
* @brief Get ADC group regular sequencer scan direction.
* @note On this STM32 series, parameter relevant only is sequencer is set
* to mode not fully configurable,
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @note On some other STM32 families, this setting is not available and
* the default scan direction is forward.
* @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_SCANDIR));
}
/**
* @brief Set ADC group regular sequence: channel on rank corresponding to
* channel number.
* @note This function performs:
* - Channels ordering into each rank of scan sequence:
* rank of each channel is fixed by channel HW number
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* - Set channels selected by overwriting the current sequencer
* configuration.
* @note On this STM32 series, ADC group regular sequencer both modes
* "fully configurable" or "not fully configurable"
* are available, they can be chosen using
* function @ref LL_ADC_REG_SetSequencerConfigurable().
* This function can be used with setting "not fully configurable".
* Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
* and @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @note One or several values can be selected.
* Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels
* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
* @param ADCx ADC instance
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15 (1)
* @arg @ref LL_ADC_CHANNEL_16 (1)
* @arg @ref LL_ADC_CHANNEL_17 (1)
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
* (1) On STM32U5, parameter can be set in ADC group sequencer
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
{
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
}
/**
* @brief Add channel to ADC group regular sequence: channel on rank corresponding to
* channel number.
* @note This function performs:
* - Channels ordering into each rank of scan sequence:
* rank of each channel is fixed by channel HW number
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* - Set channels selected by adding them to the current sequencer
* configuration.
* @note On this STM32 series, ADC group regular sequencer both modes
* "fully configurable" or "not fully configurable"
* are available, they can be chosen using
* function @ref LL_ADC_REG_SetSequencerConfigurable().
* This function can be used with setting "not fully configurable".
* Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
* and @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @note One or several values can be selected.
* Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd
* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
* @param ADCx ADC instance
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15 (1)
* @arg @ref LL_ADC_CHANNEL_16 (1)
* @arg @ref LL_ADC_CHANNEL_17 (1)
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
* (1) On STM32U5, parameter can be set in ADC group sequencer
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
{
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
SET_BIT(ADCx->CHSELR, (1UL << ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & ADC_CHSELR_CHSEL) & 0x1FUL)));
}
/**
* @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
* channel number.
* @note This function performs:
* - Channels ordering into each rank of scan sequence:
* rank of each channel is fixed by channel HW number
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* - Set channels selected by removing them to the current sequencer
* configuration.
* @note On this STM32 series, ADC group regular sequencer both modes
* "fully configurable" or "not fully configurable"
* are available, they can be chosen using
* function @ref LL_ADC_REG_SetSequencerConfigurable().
* This function can be used with setting "not fully configurable".
* Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
* and @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @note One or several values can be selected.
* Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem
* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
* @param ADCx ADC instance
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15 (1)
* @arg @ref LL_ADC_CHANNEL_16 (1)
* @arg @ref LL_ADC_CHANNEL_17 (1)
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
* (1) On STM32U5, parameter can be set in ADC group sequencer
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
{
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
CLEAR_BIT(ADCx->CHSELR, (1UL << ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)));
}
/**
* @brief Get ADC group regular sequence: channel on rank corresponding to
* channel number.
* @note This function performs:
* - Channels order reading into each rank of scan sequence:
* rank of each channel is fixed by channel HW number
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* @note On this STM32 series, ADC group regular sequencer both modes
* "fully configurable" or "not fully configurable"
* are available, they can be chosen using
* function @ref LL_ADC_REG_SetSequencerConfigurable().
* This function can be used with setting "not fully configurable".
* Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
* and @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @note One or several values can be retrieved.
* Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
* @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels
* CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
* @param ADCx ADC instance
* @retval Returned value can be a combination of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15 (1)
* @arg @ref LL_ADC_CHANNEL_16 (1)
* @arg @ref LL_ADC_CHANNEL_17 (1)
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
* (1) On STM32U5, parameter can be set in ADC group sequencer
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
{
uint32_t channels_bitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC4_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
| (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC4_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
| (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC4_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
| (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC4_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
| (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC4_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
| (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC4_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
| (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC4_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
| (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC4_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
| (((channels_bitfield & ADC_CHSELR_CHSEL8) >> ADC4_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
| (((channels_bitfield & ADC_CHSELR_CHSEL9) >> ADC4_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
| (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC4_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
| (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC4_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
| (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC4_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
| (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC4_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
| (((channels_bitfield & ADC_CHSELR_CHSEL14) >> ADC4_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
| (((channels_bitfield & ADC_CHSELR_CHSEL15) >> ADC4_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
| (((channels_bitfield & ADC_CHSELR_CHSEL16) >> ADC4_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
| (((channels_bitfield & ADC_CHSELR_CHSEL17) >> ADC4_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
| (((channels_bitfield & ADC_CHSELR_CHSEL18) >> ADC4_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
| (((channels_bitfield & ADC_CHSELR_CHSEL19) >> ADC4_CHSELR_CHSEL19_BITOFFSET_POS) * LL_ADC_CHANNEL_19)
| (((channels_bitfield & ADC_CHSELR_CHSEL20) >> ADC4_CHSELR_CHSEL20_BITOFFSET_POS) * LL_ADC_CHANNEL_20)
| (((channels_bitfield & ADC_CHSELR_CHSEL21) >> ADC4_CHSELR_CHSEL21_BITOFFSET_POS) * LL_ADC_CHANNEL_21)
| (((channels_bitfield & ADC_CHSELR_CHSEL22) >> ADC4_CHSELR_CHSEL22_BITOFFSET_POS) * LL_ADC_CHANNEL_22)
| (((channels_bitfield & ADC_CHSELR_CHSEL23) >> ADC4_CHSELR_CHSEL23_BITOFFSET_POS) * LL_ADC_CHANNEL_23)
);
}
/**
* @brief Set ADC Channel Preselection to LL_ADC_CHANNEL_x, x = 0 to 19.
* @note This function set the the value for the channel preselection register
* corresponding to ADC channel to be selected.
* @note Caution: This is not valid for ADC4.
* @param ADCx ADC instance.
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
* @arg @ref LL_ADC_CHANNEL_VBAT
*
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
{
__IO uint32_t channel_preselectione = READ_REG(ADCx->PCSEL);
WRITE_REG(ADCx->PCSEL,
channel_preselectione | (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)Channel) & 0x1FUL)));
}
/**
* @brief Get ADC Channel Preselection register value.
* @note This function set the the value for the channel preselection register
* corresponding to ADC channel to be selected.
* @note Caution: This is not valid for ADC4.
* @param ADCx ADC instance.
*
* @retval Returned decimal value that can correspend to one or multiple channels:
* @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0
* PCSEL PCSEL1 LL_ADC_CHANNEL_1
* PCSEL PCSEL2 LL_ADC_CHANNEL_2
* PCSEL PCSEL3 LL_ADC_CHANNEL_3
* PCSEL PCSEL4 LL_ADC_CHANNEL_4
* PCSEL PCSEL5 LL_ADC_CHANNEL_5
* PCSEL PCSEL6 LL_ADC_CHANNEL_6
* PCSEL PCSEL7 LL_ADC_CHANNEL_7
* PCSEL PCSEL8 LL_ADC_CHANNEL_8
* PCSEL PCSEL9 LL_ADC_CHANNEL_9
* PCSEL PCSEL10 LL_ADC_CHANNEL_10
* PCSEL PCSEL11 LL_ADC_CHANNEL_11
* PCSEL PCSEL12 LL_ADC_CHANNEL_12
* PCSEL PCSEL13 LL_ADC_CHANNEL_13
* PCSEL PCSEL14 LL_ADC_CHANNEL_14
* PCSEL PCSEL15 LL_ADC_CHANNEL_15
* PCSEL PCSEL16 LL_ADC_CHANNEL_16
* PCSEL PCSEL17 LL_ADC_CHANNEL_17
* PCSEL PCSEL18 LL_ADC_CHANNEL_18
* PCSEL PCSEL19 LL_ADC_CHANNEL_19
*
* @note User helper macro @ref __LL_ADC_DECIMAL_NB_TO_CHANNEL().
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->PCSEL, ADC_PCSEL_PCSEL));
}
/**
* @brief Set ADC low power mode.
* @note Description of ADC low power mode:
* - ADC low power mode "auto power-off":
* the ADC automatically powers-off after a conversion and
* automatically wakes up when a new conversion is triggered
* (with startup time between trigger and start of sampling).
* This feature can be combined with low power mode "auto wait".
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled.
* @rmtoll PWRR AUTOFF LL_ADC_SetLPModeAutoPowerOff
* @param ADCx ADC instance
* @param LowPowerMode This parameter can be one of the following values:
* @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
* @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
{
MODIFY_REG(ADCx->PW, ADC4_PW_AUTOFF, LowPowerMode);
}
/**
* @brief Get ADC low power mode.
* @note Description of ADC low power mode:
* - ADC low power mode "auto power-off":
* the ADC automatically powers-off after a conversion and
* automatically wakes up when a new conversion is triggered
* (with startup time between trigger and start of sampling).
* This feature can be combined with low power mode "auto wait".
* @rmtoll PW AUTOFF LL_ADC_GetLPModeAutoPowerOff
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE
* @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE
*/
__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->PW, ADC4_PW_AUTOFF));
}
/**
* @brief Set ADC low power mode: deep power down in autonomous mode
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled.
* @rmtoll PWRR DPD LL_ADC_SetLPModeAutonomousDPD
* @param ADCx ADC instance
* @param LowPowerMode This parameter can be one of the following values:
* @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
* @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
{
MODIFY_REG(ADCx->PW, ADC4_PW_DPD, LowPowerMode);
}
/**
* @brief Get ADC low power mode: deep power down in autonomous mode
* @rmtoll PWRR DPD LL_ADC_GetLPModeAutonomousDPD
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE
* @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE
*/
__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->PW, ADC4_PW_DPD));
}
/**
* @brief Set ADC VREF protection when multiple ADCs are working simultaneously
* @note In case of simultaneous sampling phase of ADC4 and ADC1/2,
* ADC4 is put on hold during one or two ADC4 clock cycles to avoid noise on Vref+.
* ADC state:
* ADC must be disabled.
* @rmtoll PWRR VREFPROT LL_ADC_SetVrefProtection
* PWRR VREFSECSMP LL_ADC_SetVrefProtection
* @param ADCx ADC instance
* @param VrefProtection This parameter can be one of the following values:
* @arg @ref LL_ADC_VREF_PROT_DISABLE
* @arg @ref LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE
* @arg @ref LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetVrefProtection(ADC_TypeDef *ADCx, uint32_t VrefProtection)
{
MODIFY_REG(ADCx->PW, ADC4_PW_VREFPROT | ADC4_PW_VREFSECSMP, VrefProtection);
}
/**
* @brief ADC VREF protection when multiple ADCs are working simultaneously
* @rmtoll PWRR VREFPROT LL_ADC_GetVrefProtection
* PWRR VREFSECSMP LL_ADC_GetVrefProtection
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_VREF_PROT_DISABLE
* @arg @ref LL_ADC_VREF_PROT_FIRST_SAMP_ENABLE
* @arg @ref LL_ADC_VREF_PROT_SECOND_SAMP_ENABLE
*/
__STATIC_INLINE uint32_t LL_ADC_GetVrefProtection(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->PW, ADC4_PW_VREFPROT | ADC4_PW_VREFSECSMP));
}
/**
* @brief Set ADC continuous conversion mode on ADC group regular.
* @note Description of ADC continuous conversion mode:
* - single mode: one conversion per trigger
* - continuous mode: after the first trigger, following
* conversions launched successively automatically.
* @note It is not possible to enable both ADC group regular
* continuous mode and sequencer discontinuous mode.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
* @param ADCx ADC instance
* @param Continuous This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_CONV_SINGLE
* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
}
/**
* @brief Get ADC continuous conversion mode on ADC group regular.
* @note Description of ADC continuous conversion mode:
* - single mode: one conversion per trigger
* - continuous mode: after the first trigger, following
* conversions launched successively automatically.
* @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_CONV_SINGLE
* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
}
/**
* @brief Set ADC data transfer mode
* @note Conversion data can be either:
* - Available in Data Register
* - Transferred by DMA in one shot mode
* - Transferred by DMA in circular mode
* - Transferred to MDF data register
* @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode
* @param ADCx ADC instance
* @param DataTransferMode Select Data Management configuration
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMNGT, DataTransferMode);
}
/**
* @brief Get ADC data transfer mode
* @note Conversion data can be either:
* - Available in Data Register
* - Transferred by DMA in one shot mode
* - Transferred by DMA in circular mode
* - Transferred to DFSDM data register
* @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_DR_TRANSFER
* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
* @arg @ref LL_ADC_REG_MDF_TRANSFER
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMNGT));
}
/**
* @brief Set ADC group regular conversion data transfer: no transfer or
* transfer by DMA, and DMA requests mode.
* @note If transfer by DMA selected, specifies the DMA requests
* mode:
* - Limited mode (One shot mode): DMA transfer requests are stopped
* when number of DMA data transfers (number of
* ADC conversions) is reached.
* This ADC mode is intended to be used with DMA mode non-circular.
* - Unlimited mode: DMA transfer requests are unlimited,
* whatever number of DMA data transfers (number of
* ADC conversions).
* This ADC mode is intended to be used with DMA mode circular.
* @note If ADC DMA requests mode is set to unlimited and DMA is set to
* mode non-circular:
* when DMA transfers size will be reached, DMA will stop transfers of
* ADC conversions data ADC will raise an overrun error
* (overrun flag and interruption if enabled).
* @note To configure DMA source address (peripheral address),
* use function @ref LL_ADC_DMA_GetRegAddr().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer
* CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
* @param ADCx ADC instance
* @param DMATransfer This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
{
MODIFY_REG(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG, DMATransfer);
}
/**
* @brief Get ADC group regular conversion data transfer: no transfer or
* transfer by DMA, and DMA requests mode.
* @note If transfer by DMA selected, specifies the DMA requests
* mode:
* - Limited mode (One shot mode): DMA transfer requests are stopped
* when number of DMA data transfers (number of
* ADC conversions) is reached.
* This ADC mode is intended to be used with DMA mode non-circular.
* - Unlimited mode: DMA transfer requests are unlimited,
* whatever number of DMA data transfers (number of
* ADC conversions).
* This ADC mode is intended to be used with DMA mode circular.
* @note If ADC DMA requests mode is set to unlimited and DMA is set to
* mode non-circular:
* when DMA transfers size will be reached, DMA will stop transfers of
* ADC conversions data ADC will raise an overrun error
* (overrun flag and interruption if enabled).
* @note To configure DMA source address (peripheral address),
* use function @ref LL_ADC_DMA_GetRegAddr().
* @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer
* CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC4_CFGR1_DMAEN | ADC4_CFGR1_DMACFG));
}
/**
* @brief Set ADC group regular behavior in case of overrun:
* data preserved or overwritten.
* @note Compatibility with devices without feature overrun:
* other devices without this feature have a behavior
* equivalent to data overwritten.
* The default setting of overrun is data preserved.
* Therefore, for compatibility with all devices, parameter
* overrun should be set to data overwritten.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
* @param ADCx ADC instance
* @param Overrun This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
}
/**
* @brief Get ADC group regular behavior in case of overrun:
* data preserved or overwritten.
* @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
* @{
*/
/**
* @brief Set ADC group injected conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
* In case of need to modify trigger edge, use
* function @ref LL_ADC_INJ_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
* @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource
* JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
* @param ADCx ADC instance
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
}
/**
* @brief Get ADC group injected conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note To determine whether group injected trigger source is
* internal (SW start) or external, without detail
* of which peripheral is selected as external trigger,
* (equivalent to
* "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
* use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource
* JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
{
__IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
/* to match with triggers literals definition. */
return ((trigger_source
& (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
| ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
);
}
/**
* @brief Get ADC group injected conversion trigger source internal (SW start)
or external
* @note In case of group injected trigger source set to external trigger,
* to determine which peripheral is selected as external trigger,
* use function @ref LL_ADC_INJ_GetTriggerSource.
* @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
}
/**
* @brief Set ADC group injected conversion trigger polarity.
* Applicable only for trigger source set to external trigger.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
* @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
* @param ADCx ADC instance
* @param ExternalTriggerEdge This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
}
/**
* @brief Get ADC group injected conversion trigger polarity.
* Applicable only for trigger source set to external trigger.
* @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
}
/**
* @brief Set ADC group injected sequencer length and scan direction.
* @note This function performs configuration of:
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
* @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
* @param ADCx ADC instance
* @param SequencerNbRanks This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
}
/**
* @brief Get ADC group injected sequencer length and scan direction.
* @note This function retrieves:
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
* @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
}
/**
* @brief Set ADC group injected sequencer discontinuous mode:
* sequence subdivided and scan conversions interrupted every selected
* number of ranks.
* @note It is not possible to enable both ADC group injected
* auto-injected mode and sequencer discontinuous mode.
* @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
* @param ADCx ADC instance
* @param SeqDiscont This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JDISCEN, SeqDiscont);
}
/**
* @brief Get ADC group injected sequencer discontinuous mode:
* sequence subdivided and scan conversions interrupted every selected
* number of ranks.
* @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JDISCEN));
}
/**
* @brief Set ADC group injected sequence: channel on the selected
* sequence rank.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32U5, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
/* Set bits with content of parameter "Channel" with bits position */
/* in register depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
MODIFY_REG(ADCx->JSQR,
(ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
<< (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
}
/**
* @brief Get ADC group injected sequence: channel on the selected
* sequence rank.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note Usage of the returned channel number:
* - To reinject this channel into another function LL_ADC_xxx:
* the returned channel number is only partly formatted on definition
* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
* with parts of literals LL_ADC_CHANNEL_x or using
* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Then the selected literal LL_ADC_CHANNEL_x can be used
* as parameter for another function.
* - To get the channel number in decimal format:
* process the returned value with the helper macro
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks
* JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks
* JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks
* JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* (1, 2) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
return (uint32_t)((READ_BIT(ADCx->JSQR,
(ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
<< (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
>> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
);
}
/**
* @brief Set ADC group injected conversion trigger:
* independent or from ADC group regular.
* @note This mode can be used to extend number of data registers
* updated after one ADC conversion trigger and with data
* permanently kept (not erased by successive conversions of scan of
* ADC sequencer ranks), up to 5 data registers:
* 1 data register on ADC group regular, 4 data registers
* on ADC group injected.
* @note If ADC group injected injected trigger source is set to an
* external trigger, this feature must be must be set to
* independent trigger.
* ADC group injected automatic trigger is compliant only with
* group injected trigger source set to SW start, without any
* further action on ADC group injected conversion start or stop:
* in this case, ADC group injected is controlled only
* from ADC group regular.
* @note It is not possible to enable both ADC group injected
* auto-injected mode and sequencer discontinuous mode.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
* @param ADCx ADC instance
* @param TrigAuto This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
{
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_JAUTO, TrigAuto);
}
/**
* @brief Get ADC group injected conversion trigger:
* independent or from ADC group regular.
* @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_JAUTO));
}
/**
* @brief Set one context on ADC group injected that will be checked in
* contexts queue.
* @note A context is a setting of group injected sequencer:
* - group injected trigger
* - sequencer length
* - sequencer ranks
* This function is intended to be used when contexts queue is enabled,
* because the sequence must be fully configured in one time
* (functions to set separately injected trigger and sequencer channels
* cannot be used):
* @note In the contexts queue, only the active context can be read.
* The parameters of this function can be read using functions:
* @arg @ref LL_ADC_INJ_GetTriggerSource()
* @arg @ref LL_ADC_INJ_GetTriggerEdge()
* @arg @ref LL_ADC_INJ_GetSequencerRanks()
* @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32U5, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
* @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext
* JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext
* JSQR JL LL_ADC_INJ_ConfigQueueContext
* JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext
* JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext
* JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext
* JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
* @param ADCx ADC instance
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1
* @param ExternalTriggerEdge This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
*
* Note: This parameter is discarded in case of SW start:
* parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
* @param SequencerNbRanks This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
* @param Rank1_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @param Rank2_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @param Rank3_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @param Rank4_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
uint32_t TriggerSource,
uint32_t ExternalTriggerEdge,
uint32_t SequencerNbRanks,
uint32_t Rank1_Channel,
uint32_t Rank2_Channel,
uint32_t Rank3_Channel,
uint32_t Rank4_Channel)
{
/* Set bits with content of parameter "Rankx_Channel" with bits position */
/* in register depending on literal "LL_ADC_INJ_RANK_x". */
/* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
/* because containing other bits reserved for other purpose. */
/* If parameter "TriggerSource" is set to SW start, then parameter */
/* "ExternalTriggerEdge" is discarded. */
/* "TriggerSource" is define dwith default edge (rising): */
/* So we need to discard the default edge else the edge will not as expected*/
uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
MODIFY_REG(ADCx->JSQR,
ADC_JSQR_JEXTSEL |
ADC_JSQR_JEXTEN |
ADC_JSQR_JSQ4 |
ADC_JSQR_JSQ3 |
ADC_JSQR_JSQ2 |
ADC_JSQR_JSQ1 |
ADC_JSQR_JL,
(TriggerSource & ADC_JSQR_JEXTSEL) |
(ExternalTriggerEdge * (is_trigger_not_sw)) |
(((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
<< (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
<< (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
<< (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
<< (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
SequencerNbRanks
);
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
* @{
*/
/**
* @brief Set sampling time of the selected ADC channel
* Unit: ADC clock cycles.
* @note On this device, sampling time is on channel scope: independently
* of channel mapped on ADC group regular or injected.
* @note In case of internal channel (VrefInt, TempSensor, ...) to be
* converted:
* sampling time constraints must be respected (sampling time can be
* adjusted in function of ADC clock frequency and sampling time
* setting).
* Refer to device datasheet for timings values (parameters TS_vrefint,
* TS_temp, ...).
* @note Conversion time is the addition of sampling time and processing time.
* On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
* - 6.5 ADC clock cycles at ADC resolution 6 bits
* @note In case of ADC conversion of internal channel (VrefInt,
* temperature sensor, ...), a sampling time minimum value
* is required.
* Refer to device datasheet.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime
* SMPR1 SMP1 LL_ADC_SetChannelSamplingTime
* SMPR1 SMP2 LL_ADC_SetChannelSamplingTime
* SMPR1 SMP3 LL_ADC_SetChannelSamplingTime
* SMPR1 SMP4 LL_ADC_SetChannelSamplingTime
* SMPR1 SMP5 LL_ADC_SetChannelSamplingTime
* SMPR1 SMP6 LL_ADC_SetChannelSamplingTime
* SMPR1 SMP7 LL_ADC_SetChannelSamplingTime
* SMPR1 SMP8 LL_ADC_SetChannelSamplingTime
* SMPR1 SMP9 LL_ADC_SetChannelSamplingTime
* SMPR2 SMP10 LL_ADC_SetChannelSamplingTime
* SMPR2 SMP11 LL_ADC_SetChannelSamplingTime
* SMPR2 SMP12 LL_ADC_SetChannelSamplingTime
* SMPR2 SMP13 LL_ADC_SetChannelSamplingTime
* SMPR2 SMP14 LL_ADC_SetChannelSamplingTime
* SMPR2 SMP15 LL_ADC_SetChannelSamplingTime
* SMPR2 SMP16 LL_ADC_SetChannelSamplingTime
* SMPR2 SMP17 LL_ADC_SetChannelSamplingTime
* SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
* @param ADCx ADC instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @param SamplingTime This parameter can be one of the following values, In case of ADC1 instance:
* @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES
* @param SamplingTime This parameter can be one of the following values, In case of ADC4 instance:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
if (ADCx != ADC4) /* ADC1 or ADC2 */
{
/* Set bits with content of parameter "SamplingTime" with bits position */
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
uint32_t shift_value = ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) - (10UL * ((Channel \
& ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
>> ADC_SMPRX_REGOFFSET_POS))) * 3UL);
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
>> ADC_SMPRX_REGOFFSET_POS));
MODIFY_REG(*preg, ADC_SMPR1_SMP0 << shift_value, SamplingTime << shift_value);
}
else
{
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. It needs to be converted to decimal */
/* to select the bit position */
MODIFY_REG(ADCx->SMPR1,
ADC4_SAMPLING_TIME_CH_MASK,
((1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel)) << ADC4_SMPR_SMPSEL0_BITOFFSET_POS) \
& (SamplingTime & ADC4_SAMPLING_TIME_CH_MASK)
);
}
}
/**
* @brief Get sampling time of the selected ADC channel
* Unit: ADC clock cycles.
* @note On this device, sampling time is on channel scope: independently
* of channel mapped on ADC group regular or injected.
* @note Conversion time is the addition of sampling time and processing time.
* On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
* - 6.5 ADC clock cycles at ADC resolution 6 bits
* @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime
* SMPR1 SMP1 LL_ADC_GetChannelSamplingTime
* SMPR1 SMP2 LL_ADC_GetChannelSamplingTime
* SMPR1 SMP3 LL_ADC_GetChannelSamplingTime
* SMPR1 SMP4 LL_ADC_GetChannelSamplingTime
* SMPR1 SMP5 LL_ADC_GetChannelSamplingTime
* SMPR1 SMP6 LL_ADC_GetChannelSamplingTime
* SMPR1 SMP7 LL_ADC_GetChannelSamplingTime
* SMPR1 SMP8 LL_ADC_GetChannelSamplingTime
* SMPR1 SMP9 LL_ADC_GetChannelSamplingTime
* SMPR2 SMP10 LL_ADC_GetChannelSamplingTime
* SMPR2 SMP11 LL_ADC_GetChannelSamplingTime
* SMPR2 SMP12 LL_ADC_GetChannelSamplingTime
* SMPR2 SMP13 LL_ADC_GetChannelSamplingTime
* SMPR2 SMP14 LL_ADC_GetChannelSamplingTime
* SMPR2 SMP15 LL_ADC_GetChannelSamplingTime
* SMPR2 SMP16 LL_ADC_GetChannelSamplingTime
* SMPR2 SMP17 LL_ADC_GetChannelSamplingTime
* SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
* @param ADCx ADC instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0 (3)
* @arg @ref LL_ADC_CHANNEL_1 (3)
* @arg @ref LL_ADC_CHANNEL_2 (3)
* @arg @ref LL_ADC_CHANNEL_3 (3)
* @arg @ref LL_ADC_CHANNEL_4 (3)
* @arg @ref LL_ADC_CHANNEL_5 (3)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2)
* @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2)
*
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @retval In case of ADC1 insatnace, Returned value can be one of the following values:
* @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_20CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_36CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_68CYCLES
* @arg @ref LL_ADC_SAMPLINGTIME_391CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES
* @retval In case of ADC4 insatnce, Returned value can be one of the following values:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
{
if (ADCx != ADC4) /* (ADCx == ADC1) || (ADCx == ADC2) */
{
uint32_t shift_value = ((__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) - (10UL * ((Channel \
& ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
>> ADC_SMPRX_REGOFFSET_POS))) * 3UL);
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) \
>> ADC_SMPRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << shift_value) >> shift_value);
}
else /* ADCx == ADC4 */
{
uint32_t smpr = READ_REG(ADCx->SMPR1);
/* Retrieve sampling time bit corresponding to the selected channel */
/* and shift it to position 0. */
uint32_t smp_channel_posbit0 = ((smpr & ADC4_SAMPLING_TIME_CH_MASK)
>> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) \
>> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+ ADC4_SMPR_SMPSEL0_BITOFFSET_POS)
& 0x1FUL));
/* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
| (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
}
}
/**
* @brief Set mode single-ended or differential input of the selected
* ADC channel.
* @note Channel ending is on channel scope: independently of channel mapped
* on ADC group regular or injected.
* In differential mode: Differential measurement is carried out
* between the selected channel 'i' (positive input) and
* channel 'i+1' (negative input). Only channel 'i' has to be
* configured, channel 'i+1' is configured automatically.
* @note Refer to Reference Manual to ensure the selected channel is
* available in differential mode.
* For example, internal channels (VrefInt, TempSensor, ...) are
* not available in differential mode.
* @note When configuring a channel 'i' in differential mode,
* the channel 'i+1' is not usable separately.
* @note On STM32U5, some channels are internally fixed to single-ended inputs
* configuration:
* - ADC1: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
* - ADC2: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
* - ADC4: None
* @note For ADC channels configured in differential mode, both inputs
* should be biased at (Vref+)/2 +/-200mV.
* (Vref+ is the analog voltage reference)
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @note One or several values can be selected.
* Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
* @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
* @param ADCx ADC instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @param SingleDiff This parameter can be a combination of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
/* Bits of channels in single or differential mode are set only for */
/* differential mode (for single mode, mask of bits allowed to be set is */
/* shifted out of range of bits of channels in single or differential mode. */
MODIFY_REG(ADCx->DIFSEL,
Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
(Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff \
& ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
}
/**
* @brief Get mode single-ended or differential input of the selected
* ADC channel.
* @note When configuring a channel 'i' in differential mode,
* the channel 'i+1' is not usable separately.
* Therefore, to ensure a channel is configured in single-ended mode,
* the configuration of channel itself and the channel 'i-1' must be
* read back (to ensure that the selected channel channel has not been
* configured in differential mode by the previous channel).
* @note Refer to Reference Manual to ensure the selected channel is
* available in differential mode.
* For example, internal channels (VrefInt, TempSensor, ...) are
* not available in differential mode.
* @note When configuring a channel 'i' in differential mode,
* the channel 'i+1' is not usable separately.
* @note On STM32U5, some channels are internally fixed to single-ended inputs
* configuration:
* - ADC1: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
* - ADC2: Channels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17
* - ADC4: None
* @note One or several values can be selected. In this case, the value
* returned is null if all channels are in single ended-mode.
* Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
* @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
* @param ADCx ADC instance
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_19
* @retval 0: channel in single-ended mode, else: channel in differential mode
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
{
return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
* @{
*/
/**
* @brief Set ADC analog watchdog monitored channels:
* a single channel, multiple channels or all channels,
* on ADC groups regular and-or injected.
* @note Once monitored channels are selected, analog watchdog
* is enabled.
* @note In case of need to define a single channel to monitor
* with analog watchdog from sequencer channel definition,
* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
* @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC groups regular and-or injected.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
* - AWD flexible (instances AWD2, AWD3):
* - channels monitored: flexible on channels monitored, selection is
* channel wise, from from 1 to all channels.
* Specificity of this analog watchdog: Multiple channels can
* be selected. For example:
* (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
* - groups monitored: not selection possible (monitoring on both
* groups regular and injected).
* Channels selected are monitored on groups regular and injected:
* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels
* CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels
* CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels
* CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels
* AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels
* AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2
* @arg @ref LL_ADC_AWD3
* @param AWDChannelGroup This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_DISABLE
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(1)
* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(1)
* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC4_REG (0)(2)
* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC4_REG (0)(2)
*
* (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
* (1) On STM32U5, parameter available only on ADC instance: ADC1/2.
* (2) On STM32U5, parameter available only on ADC instance: ADC4.
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
{
/* Set bits with content of parameter "AWDChannelGroup" with bits position */
/* in register and register position depending on parameter "AWDy". */
/* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
/* containing other bits reserved for other purpose. */
__IO uint32_t *preg;
uint32_t channel_monitored;
if (AWDy == LL_ADC_AWD1)
{
/* Set pointer to register of selected analog watchdog */
preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
/* Compute channel monitored as number */
channel_monitored = (AWDChannelGroup & ADC_AWD_CR1_CHANNEL_MASK);
}
else
{
/* Set pointer to register of selected analog watchdog */
preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CR3_REGOFFSET)) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL));
/* Compute channel monitored as bitfield */
channel_monitored = (1UL << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) \
>> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
/* Case of all channels monitored */
channel_monitored |= ((1UL - ((AWDChannelGroup & ADC_CFGR1_AWD1SGL) >> ADC_CFGR1_AWD1SGL_Pos)) * 0x00FFFFFFUL);
/* Case of no channel monitored */
channel_monitored *= ((((AWDChannelGroup & (ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)) == 0UL) ? 0UL : 1UL));
}
MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), channel_monitored);
}
/**
* @brief Get ADC analog watchdog monitored channel.
* @note Usage of the returned channel number:
* - To reinject this channel into another function LL_ADC_xxx:
* the returned channel number is only partly formatted on definition
* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
* with parts of literals LL_ADC_CHANNEL_x or using
* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Then the selected literal LL_ADC_CHANNEL_x can be used
* as parameter for another function.
* - To get the channel number in decimal format:
* process the returned value with the helper macro
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Applicable only when the analog watchdog is set to monitor
* one channel.
* @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC groups regular and-or injected.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
* - AWD flexible (instances AWD2, AWD3):
* - channels monitored: flexible on channels monitored, selection is
* channel wise, from from 1 to all channels.
* Specificity of this analog watchdog: Multiple channels can
* be selected. For example:
* (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
* - groups monitored: not selection possible (monitoring on both
* groups regular and injected).
* Channels selected are monitored on groups regular and injected:
* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels
* CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels
* CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels
* CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels
* AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels
* AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2 (1)
* @arg @ref LL_ADC_AWD3 (1)
*
* (1) On this AWD number, monitored channel can be retrieved
* if only 1 channel is programmed (or none or all channels).
* This function cannot retrieve monitored channel if
* multiple channels are programmed simultaneously
* by bitfield.
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_AWD_DISABLE
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
*
* (0) On STM32U5, parameter available only on analog watchdog number: AWD1.
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
{
const __IO uint32_t *preg;
if (AWDy == LL_ADC_AWD1)
{
/* Set pointer to register of selected analog watchdog */
preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
}
else
{
/* Set pointer to register of selected analog watchdog */
preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) \
>> (ADC_AWD_CRX_REGOFFSET_POS + 1UL));
}
uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
/* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
/* (parameter value LL_ADC_AWD_DISABLE). */
/* Else, the selected AWD is enabled and is monitoring a group of channels */
/* or a single channel. */
if (analog_wd_monit_channels != 0UL)
{
if (AWDy == LL_ADC_AWD1)
{
if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
{
/* AWD monitoring a group of channels */
analog_wd_monit_channels = ((analog_wd_monit_channels | (0x000FFFFFUL)) & (~(ADC_CFGR1_AWD1CH)));
}
else
{
/* AWD monitoring a single channel */
analog_wd_monit_channels = analog_wd_monit_channels;
}
}
else
{
if (ADCx != ADC4)
{
if ((analog_wd_monit_channels & 0x000FFFFFUL) == 0x000FFFFFUL)
{
/* AWD monitoring a group of channels */
analog_wd_monit_channels = (0x000FFFFFUL | ((ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN)));
}
else
{
/* AWD monitoring a single channel */
/* AWD monitoring a group of channels */
analog_wd_monit_channels = ((ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
| (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) \
<< ADC_CFGR1_AWD1CH_Pos));
}
}
else
{
if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
{
/* AWD monitoring a group of channels */
analog_wd_monit_channels = (0x000FFFFFUL | (ADC_CFGR1_AWD1EN));
}
else
{
/* AWD monitoring a single channel */
/* AWD monitoring a group of channels */
analog_wd_monit_channels = ((ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
| (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) \
<< ADC_CFGR1_AWD1CH_Pos));
}
}
}
}
return analog_wd_monit_channels;
}
/**
* @brief Set ADC analog watchdog threshold value of threshold
* high or low.
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
* @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC groups regular and-or injected.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
* - AWD flexible (instances AWD2, AWD3):
* - channels monitored: flexible on channels monitored, selection is
* channel wise, from from 1 to all channels.
* Specificity of this analog watchdog: Multiple channels can
* be selected. For example:
* (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
* - groups monitored: not selection possible (monitoring on both
* groups regular and injected).
* Channels selected are monitored on groups regular and injected:
* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
* @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
* impacted: the comparison of analog watchdog thresholds is done
* on oversampling intermediate computation (after ratio, before shift
* application): intermediate register bitfield [32:7]
* (26 most significant bits).
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either ADC groups regular or injected.
* @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds
* TR2 HT2 LL_ADC_SetAnalogWDThresholds
* TR3 HT3 LL_ADC_SetAnalogWDThresholds
* TR1 LT1 LL_ADC_SetAnalogWDThresholds
* TR2 LT2 LL_ADC_SetAnalogWDThresholds
* TR3 LT3 LL_ADC_SetAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2
* @arg @ref LL_ADC_AWD3
* @param AWDThresholdsHighLow This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
* @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
uint32_t AWDThresholdValue)
{
__IO uint32_t *preg;
/* Set bits with content of parameter "AWDThresholdValue" with bits */
/* position in register and register position depending on parameters */
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
if (ADCx != ADC4) /* ADCx == ADC1 or ADCx == ADC2 */
{
if (AWDy == LL_ADC_AWD1)
{
preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (AWDThresholdsHighLow));
}
else
{
preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
>> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ (AWDThresholdsHighLow));
}
MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
}
else /* ADCx == ADC4 */
{
if (AWDy == LL_ADC_AWD1)
{
preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
}
else
{
preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS))\
+ ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
}
MODIFY_REG(*preg,
ADC_AWD1TR_LT1 << (AWDThresholdsHighLow * ADC_AWD1TR_HT1_Pos),
AWDThresholdValue << (((AWDThresholdsHighLow << ADC_AWD1TR_HT1_Pos) & ADC_AWD_TRX_BIT_HIGH_MASK) \
>> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
}
}
/**
* @brief Get ADC analog watchdog threshold value of threshold high,
* threshold low or raw data with ADC thresholds high and low
* concatenated.
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
* @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds
* TR2 HT2 LL_ADC_GetAnalogWDThresholds
* TR3 HT3 LL_ADC_GetAnalogWDThresholds
* TR1 LT1 LL_ADC_GetAnalogWDThresholds
* TR2 LT2 LL_ADC_GetAnalogWDThresholds
* TR3 LT3 LL_ADC_GetAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2
* @arg @ref LL_ADC_AWD3
* @param AWDThresholdsHighLow This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
* @retval In case of ADC1 instance, Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
* @retval In case of ADC1 instance, Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
const __IO uint32_t *preg;
if (ADCx != ADC4) /* ADCx == ADC1 or ADCx == ADC2 */
{
if (AWDy == LL_ADC_AWD1)
{
preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (AWDThresholdsHighLow));
}
else
{
preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ (AWDThresholdsHighLow));
}
return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
}
else /* ADCx == ADC4 */
{
if (AWDy == LL_ADC_AWD1)
{
preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
}
else
{
preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS))\
+ ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
}
return (uint32_t)(READ_BIT(*preg,
(ADC_AWD1TR_LT1 << (AWDThresholdsHighLow * ADC_AWD1TR_HT1_Pos)))
>> (((AWDThresholdsHighLow << ADC_AWD1TR_HT1_Pos) & ADC_AWD_TRX_BIT_HIGH_MASK) \
>> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
);
}
}
/**
* @brief Set ADC analog watchdog thresholds value of both thresholds
* high and low.
* @note If value of only one threshold high or low must be set,
* use function @ref LL_ADC_SetAnalogWDThresholds().
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
* @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC group regular.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
* - AWD flexible (instances AWD2, AWD3):
* - channels monitored: flexible on channels monitored, selection is
* channel wise, from from 1 to all channels.
* Specificity of this analog watchdog: Multiple channels can
* be selected. For example:
* (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
* - groups monitored: not selection possible (monitoring on both
* groups regular and injected).
* Channels selected are monitored on groups regular and injected:
* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
* @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
* impacted: the comparison of analog watchdog thresholds is done on
* oversampling final computation (after ratio and shift application):
* ADC data register bitfield [15:4] (12 most significant bits).
* Examples:
* - Oversampling ratio and shift selected to have ADC conversion data
* on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
* ADC analog watchdog thresholds must be divided by 16.
* - Oversampling ratio and shift selected to have ADC conversion data
* on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
* ADC analog watchdog thresholds must be divided by 4.
* - Oversampling ratio and shift selected to have ADC conversion data
* on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
* ADC analog watchdog thresholds match directly to ADC data register.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds
* TR2 HT2 LL_ADC_ConfigAnalogWDThresholds
* TR3 HT3 LL_ADC_ConfigAnalogWDThresholds
* TR1 LT1 LL_ADC_ConfigAnalogWDThresholds
* TR2 LT2 LL_ADC_ConfigAnalogWDThresholds
* TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2
* @arg @ref LL_ADC_AWD3
* @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
* @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
uint32_t AWDThresholdLowValue)
{
__IO uint32_t *preg;
__IO uint32_t *preg2;
/* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
/* position in register and register position depending on parameter */
/* "AWDy". */
/* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
/* containing other bits reserved for other purpose. */
if (ADCx != ADC4) /* ADC1 or ADC2 */
{
if (AWDy == LL_ADC_AWD1)
{
preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (LL_ADC_AWD_THRESHOLD_LOW));
preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (LL_ADC_AWD_THRESHOLD_HIGH));
}
else
{
preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
>> (ADC_AWD_TRX_REGOFFSET_POS - 1UL)))
+ (LL_ADC_AWD_THRESHOLD_LOW));
preg2 = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) \
>> (ADC_AWD_TRX_REGOFFSET_POS - 1UL)))
+ (LL_ADC_AWD_THRESHOLD_HIGH));
}
MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdLowValue);
MODIFY_REG(*preg2, ADC_HTR_HT, AWDThresholdHighValue);
}
else
{
if (AWDy == LL_ADC_AWD1)
{
preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, 0UL);
}
else
{
preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_POS)) \
+ ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_POS + 1UL)));
}
MODIFY_REG(*preg,
ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
(AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
}
}
/**
* @brief Set ADC analog watchdog filtering configuration
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @note On this STM32 series, this feature is only available on first
* analog watchdog (AWD1)
* @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @param FilteringConfig This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_FILTERING_NONE
* @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
{
/* Prevent unused argument(s) compilation warning */
(void)(AWDy);
MODIFY_REG(ADCx->HTR1, ADC_HTR_AWDFILT, FilteringConfig);
}
/**
* @brief Get ADC analog watchdog filtering configuration
* @note On this STM32 series, this feature is only available on first
* analog watchdog (AWD1)
* @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @retval Returned value can be:
* @arg @ref LL_ADC_AWD_FILTERING_NONE
* @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
*/
__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
{
/* Prevent unused argument(s) compilation warning */
(void)(AWDy);
return (uint32_t)(READ_BIT(ADCx->HTR1, ADC_HTR_AWDFILT));
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
* @{
*/
/**
* @brief Set ADC oversampling scope: ADC groups regular and-or injected
* (availability of ADC group injected depends on STM32 families).
* @note If both groups regular and injected are selected,
* specify behavior of ADC group injected interrupting
* group regular: when ADC group injected is triggered,
* the oversampling on ADC group regular is either
* temporary stopped and continued, or resumed from start
* (oversampler buffer reset).
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope
* CFGR2 JOVSE LL_ADC_SetOverSamplingScope
* CFGR2 ROVSM LL_ADC_SetOverSamplingScope
* @param ADCx ADC instance
* @param OvsScope This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_DISABLE
* @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
* @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
* @arg @ref LL_ADC_OVS_GRP_INJECTED
* @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
{
if (ADCx != ADC4)
{
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
}
else
{
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE, OvsScope);
}
}
/**
* @brief Get ADC oversampling scope: ADC groups regular and-or injected
* (availability of ADC group injected depends on STM32 families).
* @note If both groups regular and injected are selected,
* specify behavior of ADC group injected interrupting
* group regular: when ADC group injected is triggered,
* the oversampling on ADC group regular is either
* temporary stopped and continued, or resumed from start
* (oversampler buffer reset).
* @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope
* CFGR2 JOVSE LL_ADC_GetOverSamplingScope
* CFGR2 ROVSM LL_ADC_GetOverSamplingScope
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OVS_DISABLE
* @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
* @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
* @arg @ref LL_ADC_OVS_GRP_INJECTED
* @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
{
if (ADCx != ADC4)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
}
else
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE));
}
}
/**
* @brief Set ADC oversampling discontinuous mode (triggered mode)
* on the selected ADC group.
* @note Number of oversampled conversions are done either in:
* - continuous mode (all conversions of oversampling ratio
* are done from 1 trigger)
* - discontinuous mode (each conversion of oversampling ratio
* needs a trigger)
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @note On this STM32 series, oversampling discontinuous mode
* (triggered mode) can be used only when oversampling is
* set on group regular only and in resumed mode.
* @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
* @param ADCx ADC instance
* @param OverSamplingDiscont This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_REG_CONT
* @arg @ref LL_ADC_OVS_REG_DISCONT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
{
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
}
/**
* @brief Get ADC oversampling discontinuous mode (triggered mode)
* on the selected ADC group.
* @note Number of oversampled conversions are done either in:
* - continuous mode (all conversions of oversampling ratio
* are done from 1 trigger)
* - discontinuous mode (each conversion of oversampling ratio
* needs a trigger)
* @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OVS_REG_CONT
* @arg @ref LL_ADC_OVS_REG_DISCONT
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
}
/**
* @brief Set ADC oversampling
* (impacting both ADC groups regular and injected)
* @note This function set the 2 items of oversampling configuration:
* - ratio
* - shift
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift
* CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
* @param ADCx ADC instance
* @param Ratio This parameter can be in the range from 1 to 1024 in case of ADC1 instance.
* @param Ratio This parameter can be one of the following values, in case of ADC4 :
* @arg @ref LL_ADC_OVS_RATIO_2
* @arg @ref LL_ADC_OVS_RATIO_4
* @arg @ref LL_ADC_OVS_RATIO_8
* @arg @ref LL_ADC_OVS_RATIO_16
* @arg @ref LL_ADC_OVS_RATIO_32
* @arg @ref LL_ADC_OVS_RATIO_64
* @arg @ref LL_ADC_OVS_RATIO_128
* @arg @ref LL_ADC_OVS_RATIO_256
* @param Shift This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_SHIFT_NONE
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 (1)
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 (1)
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 (1)
*
* (1): Only for ADC1 instance.
* @retval None
*/
__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
{
if (ADCx != ADC4)
{
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
}
else /* ADCx == ADC4 */
{
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC4_CFGR2_OVSR), (Shift | Ratio));
}
}
/**
* @brief Get ADC oversampling ratio
* (impacting both ADC groups regular and injected)
* @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
* @param ADCx ADC instance
* @retval Ratio This parameter can be a value from 1 to 1024 in the case of ADC1/2,
* In the case of ADC4 can be one of the following values:
* @arg @ref LL_ADC_OVS_RATIO_2
* @arg @ref LL_ADC_OVS_RATIO_4
* @arg @ref LL_ADC_OVS_RATIO_8
* @arg @ref LL_ADC_OVS_RATIO_16
* @arg @ref LL_ADC_OVS_RATIO_32
* @arg @ref LL_ADC_OVS_RATIO_64
* @arg @ref LL_ADC_OVS_RATIO_128
* @arg @ref LL_ADC_OVS_RATIO_256
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
{
if (ADCx != ADC4)
{
return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
}
else /* ADCx == ADC4 */
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC4_CFGR2_OVSR));
}
}
/**
* @brief Get ADC oversampling shift
* (impacting both ADC groups regular and injected)
* @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
* @param ADCx ADC instance
* @retval Shift This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_SHIFT_NONE
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 (1)
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 (1)
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 (1)
*
* (1): Only for ADC1 instance.
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
}
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Set ADC multimode configuration to operate in independent mode
* or multimode (for devices with several ADC instances).
* @note If multimode configuration: the selected ADC instance is
* either master or slave depending on hardware.
* Refer to reference manual.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
* ADC instance or by using helper macro
* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
* @rmtoll CCR DUAL LL_ADC_SetMultimode
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param Multimode This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_INDEPENDENT
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
}
/**
* @brief Get ADC multimode configuration to operate in independent mode
* or multimode (for devices with several ADC instances).
* @note If multimode configuration: the selected ADC instance is
* either master or slave depending on hardware.
* Refer to reference manual.
* @rmtoll CCR DUAL LL_ADC_GetMultimode
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_MULTI_INDEPENDENT
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
}
/**
* @brief Set ADC multimode conversion data transfer: no transfer
* or transfer by DMA.
* @note If ADC multimode transfer by DMA is not selected:
* each ADC uses its own DMA channel, with its individual
* DMA transfer settings.
* If ADC multimode transfer by DMA is selected:
* One DMA channel is used for both ADC (DMA of ADC master)
* Specifies the DMA requests mode:
* - Limited mode (One shot mode): DMA transfer requests are stopped
* when number of DMA data transfers (number of
* ADC conversions) is reached.
* This ADC mode is intended to be used with DMA mode non-circular.
* - Unlimited mode: DMA transfer requests are unlimited,
* whatever number of DMA data transfers (number of
* ADC conversions).
* This ADC mode is intended to be used with DMA mode circular.
* @note If ADC DMA requests mode is set to unlimited and DMA is set to
* mode non-circular:
* when DMA transfers size will be reached, DMA will stop transfers of
* ADC conversions data ADC will raise an overrun error
* (overrun flag and interruption if enabled).
* @note How to retrieve multimode conversion data:
* Whatever multimode transfer by DMA setting: using function
* @ref LL_ADC_REG_ReadMultiConversionData32().
* If ADC multimode transfer by DMA is selected: conversion data
* is a raw data with ADC master and slave concatenated.
* A macro is available to get the conversion data of
* ADC master or ADC slave: see helper macro
* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled
* or enabled without conversion on going on group regular.
* @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param MultiDMATransfer This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
* @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
* @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);
}
/**
* @brief Get ADC multimode conversion data transfer: no transfer
* or transfer by DMA.
* @note If ADC multimode transfer by DMA is not selected:
* each ADC uses its own DMA channel, with its individual
* DMA transfer settings.
* If ADC multimode transfer by DMA is selected:
* One DMA channel is used for both ADC (DMA of ADC master)
* Specifies the DMA requests mode:
* - Limited mode (One shot mode): DMA transfer requests are stopped
* when number of DMA data transfers (number of
* ADC conversions) is reached.
* This ADC mode is intended to be used with DMA mode non-circular.
* - Unlimited mode: DMA transfer requests are unlimited,
* whatever number of DMA data transfers (number of
* ADC conversions).
* This ADC mode is intended to be used with DMA mode circular.
* @note If ADC DMA requests mode is set to unlimited and DMA is set to
* mode non-circular:
* when DMA transfers size will be reached, DMA will stop transfers of
* ADC conversions data ADC will raise an overrun error
* (overrun flag and interruption if enabled).
* @note How to retrieve multimode conversion data:
* Whatever multimode transfer by DMA setting: using function
* @ref LL_ADC_REG_ReadMultiConversionData32().
* If ADC multimode transfer by DMA is selected: conversion data
* is a raw data with ADC master and slave concatenated.
* A macro is available to get the conversion data of
* ADC master or ADC slave: see helper macro
* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
* @rmtoll CCR DAMDF LL_ADC_GetMultiDMATransfer\n
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
* @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B
* @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));
}
/**
* @brief Set ADC multimode delay between 2 sampling phases.
* @note The sampling delay range depends on ADC resolution:
* - ADC resolution 14 bits can have maximum delay of 16 cycles.
* - ADC resolution 12 bits can have maximum delay of 16 cycles.
* - ADC resolution 10 bits can have maximum delay of 15 cycles.
* - ADC resolution 8 bits can have maximum delay of 13 cycles.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
* ADC instance or by using helper macro helper macro
* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
* @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param MultiTwoSamplingDelay This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (2)
*
* (1) Parameter available only if ADC resolution is 14, 12 or 10 bits.
* (2) Parameter available only if ADC resolution is 14 or 12 bits.
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
}
/**
* @brief Get ADC multimode delay between 2 sampling phases.
* @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES_8_BITS
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES_10_BITS
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (2)
*
* (1) Parameter available only if ADC resolution is 14, 12 or 10 bits.
* (2) Parameter available only if ADC resolution is 14 or 12 bits.
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
* @{
*/
/**
* @brief Put ADC instance in deep power down state.
* @note In case of ADC calibration necessary: When ADC is in deep-power-down
* state, the internal analog calibration is lost. After exiting from
* deep power down, calibration must be relaunched or calibration factor
* (preliminarily saved) must be set back into calibration register.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_DEEPPWD);
}
/**
* @brief Disable ADC deep power down mode.
* @note In case of ADC calibration necessary: When ADC is in deep-power-down
* state, the internal analog calibration is lost. After exiting from
* deep power down, calibration must be relaunched or calibration factor
* (preliminarily saved) must be set back into calibration register.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
}
/**
* @brief Get the selected ADC instance deep power down state.
* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
* @param ADCx ADC instance
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
}
/**
* @brief Enable ADC instance internal voltage regulator.
* @note On this STM32 series, after ADC internal voltage regulator enable,
* a delay for ADC internal voltage regulator stabilization
* is required before performing a ADC calibration or ADC enable.
* Refer to device datasheet, parameter tADCVREG_STUP.
* Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN);
}
/**
* @brief Disable ADC internal voltage regulator.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
}
/**
* @brief Get the selected ADC instance internal voltage regulator state.
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
}
/**
* @brief Enable the selected ADC instance.
* @note On this STM32 series, after ADC enable, a delay for
* ADC internal analog stabilization is required before performing a
* ADC conversion start.
* Refer to device datasheet, parameter tSTAB.
* @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled and ADC internal voltage regulator enabled.
* @rmtoll CR ADEN LL_ADC_Enable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN);
}
/**
* @brief Disable the selected ADC instance.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be not disabled. Must be enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CR ADDIS LL_ADC_Disable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS);
}
/**
* @brief Get the selected ADC instance enable state.
* @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll CR ADEN LL_ADC_IsEnabled
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
}
/**
* @brief Get the selected ADC instance disable state.
* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
* @param ADCx ADC instance
* @retval 0: no ADC disable command on going.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
}
/**
* @brief Start ADC calibration in the mode single-ended
* or differential (for devices with differential mode available).
* @note On this STM32 series, a minimum number of ADC clock cycles
* are required between ADC end of calibration and ADC enable.
* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
* @note Calibration duration:
* - Calibration of offset: 520 ADC clock cycles
* - Calibration of linearity: 131072 ADC clock cycles
* @note For devices with differential mode available:
* Calibration of offset is specific to each of
* single-ended and differential modes
* (calibration run must be performed for each of these
* differential modes, if used afterwards and if the application
* requires their calibration).
* Calibration of linearity is common to both
* single-ended and differential modes
* (calibration run can be performed only once).
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADCAL LL_ADC_StartCalibration
* CR ADCALDIF LL_ADC_StartCalibration
* CR ADCALLIN LL_ADC_StartCalibration
* @param ADCx ADC instance
* @param CalibrationMode This parameter can be one of the following values:
* @arg @ref LL_ADC_CALIB_OFFSET
* @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY
* @retval None
*/
__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
if (ADCx != ADC4) /* ADC1 or ADC2 */
{
MODIFY_REG(ADCx->CR,
ADC_CR_ADCALLIN | ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK));
}
else
{
MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCAL);
}
}
/**
* @brief Get ADC calibration state.
* @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
* @param ADCx ADC instance
* @retval 0: calibration complete, 1: calibration in progress.
*/
__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
* @{
*/
/**
* @brief Start ADC group regular conversion.
* @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
* without ADC disable command on going.
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART);
}
/**
* @brief Stop ADC group regular conversion.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group regular,
* without ADC disable command on going.
* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTP);
}
/**
* @brief Get ADC group regular conversion state.
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
}
/**
* @brief Get ADC group regular command of conversion stop state
* @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
* @param ADCx ADC instance
* @retval 0: no command of conversion stop is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
}
/**
* @brief Get ADC group regular conversion data, range fit for
* all ADC configurations: all ADC resolutions and
* all oversampling increased data width (for devices
* with feature oversampling).
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
/**
* @brief Get ADC group regular conversion data, range fit for
* ADC resolution 16 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_REG_ReadConversionData32.
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData16
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(const ADC_TypeDef *ADCx)
{
return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
/**
* @brief Get ADC group regular conversion data, range fit for
* ADC resolution 14 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_REG_ReadConversionData32.
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData14
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00 and Max_Data=0x3FF
*/
__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(const ADC_TypeDef *ADCx)
{
return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
/**
* @brief Get ADC group regular conversion data, range fit for
* ADC resolution 12 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_REG_ReadConversionData32.
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
* @param ADCx ADC instance
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
{
return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
/**
* @brief Get ADC group regular conversion data, range fit for
* ADC resolution 10 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_REG_ReadConversionData32.
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
* @param ADCx ADC instance
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
{
return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
/**
* @brief Get ADC group regular conversion data, range fit for
* ADC resolution 8 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_REG_ReadConversionData32.
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
{
return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Get ADC multimode conversion data of ADC master, ADC slave
* or raw data with ADC master and slave concatenated.
* @note If raw data with ADC master and slave concatenated is retrieved,
* a macro is available to get the conversion data of
* ADC master or ADC slave: see helper macro
* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
* (however this macro is mainly intended for multimode
* transfer by DMA, because this function can do the same
* by getting multimode conversion data of ADC master or ADC slave
* separately).
* @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32
* CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param ConversionData This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_MASTER
* @arg @ref LL_ADC_MULTI_SLAVE
* @arg @ref LL_ADC_MULTI_MASTER_SLAVE
* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) >> (POSITION_VAL(ConversionData) & 0x1FUL));
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
* @{
*/
/**
* @brief Start ADC group injected conversion.
* @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group injected,
* without conversion stop command on going on group injected,
* without ADC disable command on going.
* @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTART);
}
/**
* @brief Stop ADC group injected conversion.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group injected,
* without ADC disable command on going.
* @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP);
}
/**
* @brief Get ADC group injected conversion state.
* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
}
/**
* @brief Get ADC group injected command of conversion stop state
* @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
* @param ADCx ADC instance
* @retval 0: no command of conversion stop is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
}
/**
* @brief Get ADC group regular conversion data, range fit for
* all ADC configurations: all ADC resolutions and
* all oversampling increased data width (for devices
* with feature oversampling).
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32
* JDR2 JDATA LL_ADC_INJ_ReadConversionData32
* JDR3 JDATA LL_ADC_INJ_ReadConversionData32
* JDR4 JDATA LL_ADC_INJ_ReadConversionData32
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
>> ADC_JDRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
}
/**
* @brief Get ADC group injected conversion data, range fit for
* ADC resolution 16 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16
* JDR2 JDATA LL_ADC_INJ_ReadConversionData16
* JDR3 JDATA LL_ADC_INJ_ReadConversionData16
* JDR4 JDATA LL_ADC_INJ_ReadConversionData16
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x000 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
>> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
}
/**
* @brief Get ADC group injected conversion data, range fit for
* ADC resolution 14 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14
* JDR2 JDATA LL_ADC_INJ_ReadConversionData14
* JDR3 JDATA LL_ADC_INJ_ReadConversionData14
* JDR4 JDATA LL_ADC_INJ_ReadConversionData14
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x000 and Max_Data=0x3FFF
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
>> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
}
/**
* @brief Get ADC group injected conversion data, range fit for
* ADC resolution 12 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12
* JDR2 JDATA LL_ADC_INJ_ReadConversionData12
* JDR3 JDATA LL_ADC_INJ_ReadConversionData12
* JDR4 JDATA LL_ADC_INJ_ReadConversionData12
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
>> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
}
/**
* @brief Get ADC group injected conversion data, range fit for
* ADC resolution 10 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10
* JDR2 JDATA LL_ADC_INJ_ReadConversionData10
* JDR3 JDATA LL_ADC_INJ_ReadConversionData10
* JDR4 JDATA LL_ADC_INJ_ReadConversionData10
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
>> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
}
/**
* @brief Get ADC group injected conversion data, range fit for
* ADC resolution 8 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8
* JDR2 JDATA LL_ADC_INJ_ReadConversionData8
* JDR3 JDATA LL_ADC_INJ_ReadConversionData8
* JDR4 JDATA LL_ADC_INJ_ReadConversionData8
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) \
>> ADC_JDRX_REGOFFSET_POS));
return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA));
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
* @{
*/
/**
* @brief Get flag ADC ready.
* @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group regular end of unitary conversion.
* @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group regular end of sequence conversions.
* @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group regular overrun.
* @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group regular end of sampling phase.
* @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group injected end of unitary conversion.
* @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group injected end of sequence conversions.
* @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC analog watchdog 1 flag
* @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC analog watchdog 2.
* @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC analog watchdog 3.
* @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
}
/**
* @brief Clear flag ADC ready.
* @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
}
/**
* @brief Clear flag ADC group regular end of unitary conversion.
* @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
}
/**
* @brief Clear flag ADC group regular end of sequence conversions.
* @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
}
/**
* @brief Clear flag ADC group regular overrun.
* @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
}
/**
* @brief Clear flag ADC group regular end of sampling phase.
* @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
}
/**
* @brief Clear flag ADC group injected end of unitary conversion.
* @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
}
/**
* @brief Clear flag ADC group injected end of sequence conversions.
* @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
}
/**
* @brief Clear flag ADC analog watchdog 1.
* @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
}
/**
* @brief Clear flag ADC analog watchdog 2.
* @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
}
/**
* @brief Clear flag ADC analog watchdog 3.
* @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_IT_Management ADC IT management
* @{
*/
/**
* @brief Enable ADC ready.
* @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
}
/**
* @brief Enable interruption ADC group regular end of unitary conversion.
* @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
}
/**
* @brief Enable interruption ADC group regular end of sequence conversions.
* @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
}
/**
* @brief Enable ADC group regular interruption overrun.
* @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
}
/**
* @brief Enable interruption ADC group regular end of sampling.
* @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
}
/**
* @brief Enable interruption ADC group injected end of unitary conversion.
* @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
}
/**
* @brief Enable interruption ADC group injected end of sequence conversions.
* @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
}
/**
* @brief Enable interruption ADC analog watchdog 1.
* @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
}
/**
* @brief Enable interruption ADC analog watchdog 2.
* @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
}
/**
* @brief Enable interruption ADC analog watchdog 3.
* @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
}
/**
* @brief Enable interruption ADC end of calibration.
* @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
}
/**
* @brief Disable interruption ADC ready.
* @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
}
/**
* @brief Disable interruption ADC group regular end of unitary conversion.
* @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
}
/**
* @brief Disable interruption ADC group regular end of sequence conversions.
* @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
}
/**
* @brief Disable interruption ADC group regular overrun.
* @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
}
/**
* @brief Disable interruption ADC group regular end of sampling.
* @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
}
/**
* @brief Disable interruption ADC group regular end of unitary conversion.
* @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
}
/**
* @brief Disable interruption ADC group injected end of sequence conversions.
* @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
}
/**
* @brief Disable interruption ADC analog watchdog 1.
* @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
}
/**
* @brief Disable interruption ADC analog watchdog 2.
* @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
}
/**
* @brief Disable interruption ADC analog watchdog 3.
* @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
}
/**
* @brief Disable interruption ADC end of calibration.
* @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
}
/**
* @brief Get state of interruption ADC ready
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group regular end of unitary conversion
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group regular end of sequence conversions
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group regular overrun
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group regular end of sampling
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group injected end of unitary conversion
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group injected end of sequence conversions
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC analog watchdog 1
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption Get ADC analog watchdog 2
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption Get ADC analog watchdog 3
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC end of calibration
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
/* Initialization of some features of ADC common parameters and multimode */
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *pADCxyCOMMON);
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *pADCxyCOMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInit);
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInit);
/* De-initialization of ADC instance, ADC group regular and ADC group injected */
/* (availability of ADC group injected depends on STM32 families) */
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *pADCx);
/* Initialization of some features of ADC instance */
ErrorStatus LL_ADC_Init(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct);
void LL_ADC_StructInit(ADC_TypeDef *pADCx, LL_ADC_InitTypeDef *pADC_InitStruct);
/* Initialization of some features of ADC instance and ADC group regular */
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
void LL_ADC_REG_StructInit(ADC_TypeDef *pADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
/* Initialization of some features of ADC instance and ADC group injected */
ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *pADCx, LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* ADC1 || ADC2 || ADC3 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_ADC_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h
|
C
|
apache-2.0
| 542,904
|
/**
******************************************************************************
* @file stm32u5xx_ll_bus.h
* @author MCD Application Team
* @brief Header file of BUS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
##### RCC Limitations #####
==============================================================================
[..]
A delay between an RCC peripheral clock enable and the effective peripheral
enabling should be taken into account in order to manage the peripheral read/write
from/to registers.
(+) This delay depends on the peripheral mapping.
(++) AHB , APB peripherals, 1 dummy read is necessary
[..]
Workarounds:
(#) For AHB , APB peripherals, a dummy read to the peripheral register has been
inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_BUS_H
#define STM32U5xx_LL_BUS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(RCC)
/** @defgroup BUS_LL BUS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
* @{
*/
/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
* @{
*/
#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN
#define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
#define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
#define LL_AHB1_GRP1_PERIPH_MDF1 RCC_AHB1ENR_MDF1EN
#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
#define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN
#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
#if defined(GFXMMU)
#define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN
#endif /* defined(GFXMMU) */
#if defined(GPU2D)
#define LL_AHB1_GRP1_PERIPH_GPU2D RCC_AHB1ENR_GPU2DEN
#endif /* defined(GPU2D) */
#if defined(DCACHE2)
#define LL_AHB1_GRP1_PERIPH_DCACHE2 RCC_AHB1ENR_DCACHE2EN
#endif /* defined(DCACHE2) */
#define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_GTZC1EN
#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
#define LL_AHB1_GRP1_PERIPH_DCACHE1 RCC_AHB1ENR_DCACHE1EN
#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN
/**
* @}
*/
/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
* @{
*/
#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR1_GPIOAEN
#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR1_GPIOBEN
#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR1_GPIOCEN
#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR1_GPIODEN
#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR1_GPIOEEN
#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR1_GPIOFEN
#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR1_GPIOGEN
#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR1_GPIOHEN
#define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR1_GPIOIEN
#if defined (GPIOJ)
#define LL_AHB2_GRP1_PERIPH_GPIOJ RCC_AHB2ENR1_GPIOJEN
#endif /* defined (GPIOJ) */
#define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR1_ADC12EN
#define LL_AHB2_GRP1_PERIPH_DCMI_PSSI RCC_AHB2ENR1_DCMI_PSSIEN
#if defined(USB_OTG_FS)
#define LL_AHB2_GRP1_PERIPH_USBFS RCC_AHB2ENR1_OTGEN
#elif defined(USB_OTG_HS)
#define LL_AHB2_GRP1_PERIPH_USBHS RCC_AHB2ENR1_OTGEN
#endif /* defined(USB_OTG_HS) */
#if defined(RCC_AHB2ENR1_USBPHYCEN)
#define LL_AHB2_GRP1_PERIPH_USBPHY RCC_AHB2ENR1_USBPHYCEN
#endif /* defined(RCC_AHB2ENR1_USBPHYCEN) */
#if defined(AES)
#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR1_AESEN
#endif /* AES */
#if defined(HASH)
#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR1_HASHEN
#endif /* HASH */
#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR1_RNGEN
#define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR1_PKAEN
#if defined(SAES)
#define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR1_SAESEN
#endif /* SAES */
#define LL_AHB2_GRP1_PERIPH_OCTOSPIM RCC_AHB2ENR1_OCTOSPIMEN
#define LL_AHB2_GRP1_PERIPH_OTFDEC1 RCC_AHB2ENR1_OTFDEC1EN
#define LL_AHB2_GRP1_PERIPH_OTFDEC2 RCC_AHB2ENR1_OTFDEC2EN
#define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR1_SDMMC1EN
#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR1_SDMMC2EN
#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR1_SRAM2EN
#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2ENR1_SRAM3EN
/**
* @}
*/
/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
* @{
*/
#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_AHB3_GRP1_PERIPH_LPGPIO1 RCC_AHB3ENR_LPGPIO1EN
#define LL_AHB3_GRP1_PERIPH_PWR RCC_AHB3ENR_PWREN
#define LL_AHB3_GRP1_PERIPH_ADC4 RCC_AHB3ENR_ADC4EN
#define LL_AHB3_GRP1_PERIPH_DAC1 RCC_AHB3ENR_DAC1EN
#define LL_AHB3_GRP1_PERIPH_LPDMA1 RCC_AHB3ENR_LPDMA1EN
#define LL_AHB3_GRP1_PERIPH_ADF1 RCC_AHB3ENR_ADF1EN
#define LL_AHB3_GRP1_PERIPH_GTZC2 RCC_AHB3ENR_GTZC2EN
#define LL_AHB3_GRP1_PERIPH_SRAM4 RCC_AHB3ENR_SRAM4EN
/**
* @}
*/
/** @defgroup BUS_LL_EC_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH
* @{
*/
#define LL_AHB2_GRP2_PERIPH_ALL 0xFFFFFFFFU
#define LL_AHB2_GRP2_PERIPH_FSMC RCC_AHB2ENR2_FSMCEN
#define LL_AHB2_GRP2_PERIPH_OCTOSPI1 RCC_AHB2ENR2_OCTOSPI1EN
#define LL_AHB2_GRP2_PERIPH_OCTOSPI2 RCC_AHB2ENR2_OCTOSPI2EN
#if defined(HSPI1)
#define LL_AHB2_GRP2_PERIPH_HSPI1 RCC_AHB2ENR2_HSPI1EN
#endif /* defined(HSPI1) */
#if defined(SRAM5_SIZE)
#define LL_AHB2_GRP2_PERIPH_SRAM5 RCC_AHB2ENR2_SRAM5EN
#endif /* defined(SRAM5_SIZE) */
/**
* @}
*/
/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
* @{
*/
#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
#if defined(USART6)
#define LL_APB1_GRP1_PERIPH_USART6 RCC_APB1ENR1_USART6EN
#endif /* defined(USART6) */
/**
* @}
*/
/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
* @{
*/
#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
#define LL_APB1_GRP2_PERIPH_FDCAN1 RCC_APB1ENR2_FDCAN1EN
#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
#if defined(I2C5)
#define LL_APB1_GRP2_PERIPH_I2C5 RCC_APB1ENR2_I2C5EN
#endif /* defined(I2C5) */
#if defined(I2C6)
#define LL_APB1_GRP2_PERIPH_I2C6 RCC_APB1ENR2_I2C6EN
#endif /* defined(I2C6) */
/**
* @}
*/
/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
* @{
*/
#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
#if defined(LTDC)
#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
#endif /* defined(LTDC) */
#if defined(DSI)
#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIHOSTEN
#endif /* defined(DSI) */
/**
* @}
*/
/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH
* @{
*/
#define LL_APB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_APB3_GRP1_PERIPH_SYSCFG RCC_APB3ENR_SYSCFGEN
#define LL_APB3_GRP1_PERIPH_SPI3 RCC_APB3ENR_SPI3EN
#define LL_APB3_GRP1_PERIPH_LPUART1 RCC_APB3ENR_LPUART1EN
#define LL_APB3_GRP1_PERIPH_I2C3 RCC_APB3ENR_I2C3EN
#define LL_APB3_GRP1_PERIPH_LPTIM1 RCC_APB3ENR_LPTIM1EN
#define LL_APB3_GRP1_PERIPH_LPTIM3 RCC_APB3ENR_LPTIM3EN
#define LL_APB3_GRP1_PERIPH_LPTIM4 RCC_APB3ENR_LPTIM4EN
#define LL_APB3_GRP1_PERIPH_OPAMP RCC_APB3ENR_OPAMPEN
#define LL_APB3_GRP1_PERIPH_COMP RCC_APB3ENR_COMPEN
#define LL_APB3_GRP1_PERIPH_VREF RCC_APB3ENR_VREFEN
#define LL_APB3_GRP1_PERIPH_RTCAPB RCC_APB3ENR_RTCAPBEN
/**
* @}
*/
/** @defgroup BUS_LL_EC_SRDAMR_GRP1_PERIPH SRDAMR GRP1 PERIPH
* @{
*/
#define LL_SRDAMR_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_SRDAMR_GRP1_PERIPH_SPI3AMEN RCC_SRDAMR_SPI3AMEN
#define LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN RCC_SRDAMR_LPUART1AMEN
#define LL_SRDAMR_GRP1_PERIPH_I2C3AMEN RCC_SRDAMR_I2C3AMEN
#define LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN RCC_SRDAMR_LPTIM1AMEN
#define LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN RCC_SRDAMR_LPTIM3AMEN
#define LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN RCC_SRDAMR_LPTIM4AMEN
#define LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN RCC_SRDAMR_OPAMPAMEN
#define LL_SRDAMR_GRP1_PERIPH_COMPAMEN RCC_SRDAMR_COMPAMEN
#define LL_SRDAMR_GRP1_PERIPH_VREFAMEN RCC_SRDAMR_VREFAMEN
#define LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN RCC_SRDAMR_RTCAPBAMEN
#define LL_SRDAMR_GRP1_PERIPH_ADC4AMEN RCC_SRDAMR_ADC4AMEN
#define LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN RCC_SRDAMR_LPGPIO1AMEN
#define LL_SRDAMR_GRP1_PERIPH_DAC1AMEN RCC_SRDAMR_DAC1AMEN
#define LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN RCC_SRDAMR_LPDMA1AMEN
#define LL_SRDAMR_GRP1_PERIPH_ADF1AMEN RCC_SRDAMR_ADF1AMEN
#define LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN RCC_SRDAMR_SRAM4AMEN
/**
* @}
*/
/** @defgroup LL_RCC_Aliased_Constants LL RCC Aliased Constants maintained for legacy purpose
* @{
*/
#define LL_AHB2_GRP1_PERIPH_ADC1 LL_AHB2_GRP1_PERIPH_ADC12
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
* @{
*/
/** @defgroup BUS_LL_EF_AHB1 AHB1
* @{
*/
/**
* @brief Enable AHB1 peripherals clock.
* @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR MDF1EN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR GPU2DEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR DCACHE2EN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR GTZC1EN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR DCACHE1EN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB1ENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB1 peripheral clock is enabled or not
* @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR MDF1EN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR GPU2DEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR DCACHE2EN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR GTZC1EN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR DCACHEEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB1 peripherals clock.
* @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR MDF1EN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR GPU2DEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR DCACHE2EN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR GTZC1EN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR DCACHEEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1ENR, Periphs);
}
/**
* @brief Force AHB1 peripherals reset.
* @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR CORDICRSTR LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR FMACRSTR LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR MDF1RSTR LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR GFXMMURSTR LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR GPU2DRSTR LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR DCACHE2RSTR LL_AHB1_GRP1_ForceReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB1RSTR, Periphs);
}
/**
* @brief Release AHB1 peripherals reset.
* @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR CORDICRSTR LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR FMACRSTR LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR MDF1RSTR LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR GFXMMURSTR LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR GPU2DRSTR LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR DCACHE2RSTR LL_AHB1_GRP1_ReleaseReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1RSTR, Periphs);
}
/**
* @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR MDF1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR DCACHESMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB1SMENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not
* @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR CORDICSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR FMACSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR MDF1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR DCACHESMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB1SMENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR MDF1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR DCACHESMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_MDF1
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
* @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D
* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*)
* @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1
* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
* @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1SMENR, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
* @{
*/
/**
* @brief Enable AHB2 peripherals clock.
* @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 GPIOBEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 GPIOCEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 GPIODEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 GPIOEEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 GPIOFEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 GPIOGEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 GPIOHEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 GPIOIEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 GPIOJEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 ADC12EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 OTGEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 AESEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 HASHEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 RNGEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 PKAEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 SAESEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 OCTOSPIMEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 SRAM2EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR1 SRAM3EN LL_AHB2_GRP1_EnableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
* @arg @ref LL_AHB2_GRP1_PERIPH_USBFS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBHS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_PKA
* @arg @ref LL_AHB2_GRP1_PERIPH_SAES
* @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB2ENR1, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB2ENR1, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB2 peripheral clock is enabled or not
* @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 GPIOJEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 ADC12EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 OTGEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 AESEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 HASHEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 RNGEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 PKAEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 SAESEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 OCTOSPIMEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR1 SRAM3EN LL_AHB2_GRP1_IsEnabledClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
* @arg @ref LL_AHB2_GRP1_PERIPH_USBFS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBHS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_PKA
* @arg @ref LL_AHB2_GRP1_PERIPH_SAES
* @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB2ENR1, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB2 peripherals clock.
* @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 GPIOBEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 GPIOCEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 GPIODEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 GPIOEEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 GPIOFEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 GPIOGEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 GPIOHEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 GPIOIEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 GPIOJEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 ADC12EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 OTGEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 AESEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 HASHEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 RNGEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 PKAEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 SAESEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 OSPIMEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 SRAM2EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR1 SRAM3EN LL_AHB2_GRP1_DisableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
* @arg @ref LL_AHB2_GRP1_PERIPH_USBFS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBHS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_PKA
* @arg @ref LL_AHB2_GRP1_PERIPH_SAES
* @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2ENR1, Periphs);
}
/**
* @brief Force AHB2 peripherals reset.
* @rmtoll AHB2RSTR1 GPIOARST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 GPIOBRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 GPIOCRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 GPIODRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 GPIOJRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 ADC12RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 OTGRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 USBPHYCRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 AESRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 HASHRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 RNGRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 PKARST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 SAESRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 SDMMC1RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR1 SDMMC2RST LL_AHB2_GRP1_ForceReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
* @arg @ref LL_AHB2_GRP1_PERIPH_USBFS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBHS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_PKA
* @arg @ref LL_AHB2_GRP1_PERIPH_SAES
* @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB2RSTR1, Periphs);
}
/**
* @brief Release AHB2 peripherals reset.
* @rmtoll AHB2RSTR1 GPIOARST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 GPIODRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 GPIOJRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 ADC12RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 OTGRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 USBPHYCRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 AESRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 HASHRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 RNGRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 PKARST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 SAESRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 SDMMC1RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR1 SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
* @arg @ref LL_AHB2_GRP1_PERIPH_USBFS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBHS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_PKA
* @arg @ref LL_AHB2_GRP1_PERIPH_SAES
* @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2RSTR1, Periphs);
}
/**
* @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
* @arg @ref LL_AHB2_GRP1_PERIPH_USBFS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBHS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_PKA
* @arg @ref LL_AHB2_GRP1_PERIPH_SAES
* @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB2SMENR1, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB2SMENR1, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not
* @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 USBPHYCMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 PKASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
* @arg @ref LL_AHB2_GRP1_PERIPH_USBFS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBHS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_PKA
* @arg @ref LL_AHB2_GRP1_PERIPH_SAES
* @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB2SMENR1, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 USBPHYCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI
* @arg @ref LL_AHB2_GRP1_PERIPH_USBFS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBHS (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES
* @arg @ref LL_AHB2_GRP1_PERIPH_HASH
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
* @arg @ref LL_AHB2_GRP1_PERIPH_PKA
* @arg @ref LL_AHB2_GRP1_PERIPH_SAES
* @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1
* @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1
* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2SMENR1, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_AHB3 AHB3
* @{
*/
/**
* @brief Enable AHB3 peripherals clock.
* @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_EnableClock\n
* AHB3ENR PWREN LL_AHB3_GRP1_EnableClock\n
* AHB3ENR ADC4EN LL_AHB3_GRP1_EnableClock\n
* AHB3ENR DAC1EN LL_AHB3_GRP1_EnableClock\n
* AHB3ENR LPDMA1EN LL_AHB3_GRP1_EnableClock\n
* AHB3ENR ADF1EN LL_AHB3_GRP1_EnableClock\n
* AHB3ENR GTZC2EN LL_AHB3_GRP1_EnableClock\n
* AHB3ENR SRAM4EN LL_AHB3_GRP1_EnableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
* @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
* @arg @ref LL_AHB3_GRP1_PERIPH_PWR
* @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
* @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
* @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
* @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
* @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB3ENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB3 peripheral clock is enabled or not
* @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_IsEnabledClock\n
* AHB3ENR PWREN LL_AHB3_GRP1_IsEnabledClock\n
* AHB3ENR ADC4EN LL_AHB3_GRP1_IsEnabledClock\n
* AHB3ENR DAC1EN LL_AHB3_GRP1_IsEnabledClock\n
* AHB3ENR LPDMA1EN LL_AHB3_GRP1_IsEnabledClock\n
* AHB3ENR ADF1EN LL_AHB3_GRP1_IsEnabledClock\n
* AHB3ENR GTZC2EN LL_AHB3_GRP1_IsEnabledClock\n
* AHB3ENR SRAM4EN LL_AHB3_GRP1_IsEnabledClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
* @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
* @arg @ref LL_AHB3_GRP1_PERIPH_PWR
* @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
* @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
* @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
* @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
* @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB3 peripherals clock.
* @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_DisableClock\n
* AHB3ENR PWREN LL_AHB3_GRP1_DisableClock\n
* AHB3ENR ADC4EN LL_AHB3_GRP1_DisableClock\n
* AHB3ENR DAC1EN LL_AHB3_GRP1_DisableClock\n
* AHB3ENR LPDMA1EN LL_AHB3_GRP1_DisableClock\n
* AHB3ENR ADF1EN LL_AHB3_GRP1_DisableClock\n
* AHB3ENR GTZC2EN LL_AHB3_GRP1_DisableClock\n
* AHB3ENR SRAM4EN LL_AHB3_GRP1_DisableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
* @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
* @arg @ref LL_AHB3_GRP1_PERIPH_PWR
* @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
* @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
* @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
* @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
* @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3ENR, Periphs);
}
/**
* @brief Force AHB3 peripherals reset.
* @rmtoll AHB3RSTR LPGPIO1RST LL_AHB3_GRP1_ForceReset\n
* AHB3RSTR PWRRST LL_AHB3_GRP1_ForceReset\n
* AHB3RSTR ADC4RST LL_AHB3_GRP1_ForceReset\n
* AHB3RSTR DAC1RST LL_AHB3_GRP1_ForceReset\n
* AHB3RSTR LPDMA1RST LL_AHB3_GRP1_ForceReset\n
* AHB3RSTR ADF1RST LL_AHB3_GRP1_ForceReset\n
* AHB3RSTR GTZC2RST LL_AHB3_GRP1_ForceReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
* @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
* @arg @ref LL_AHB3_GRP1_PERIPH_PWR
* @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
* @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
* @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
* @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB3RSTR, Periphs);
}
/**
* @brief Release AHB3 peripherals reset.
* @rmtoll AHB3RSTR LPGPIO1RST LL_AHB3_GRP1_ReleaseReset\n
* AHB3RSTR PWRRST LL_AHB3_GRP1_ReleaseReset\n
* AHB3RSTR ADC4RST LL_AHB3_GRP1_ReleaseReset\n
* AHB3RSTR DAC1RST LL_AHB3_GRP1_ReleaseReset\n
* AHB3RSTR LPDMA1RST LL_AHB3_GRP1_ReleaseReset\n
* AHB3RSTR ADF1RST LL_AHB3_GRP1_ReleaseReset\n
* AHB3RSTR GTZC2RST LL_AHB3_GRP1_ReleaseReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
* @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
* @arg @ref LL_AHB3_GRP1_PERIPH_PWR
* @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
* @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
* @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
* @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3RSTR, Periphs);
}
/**
* @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
* AHB3SMENR PWRSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
* AHB3SMENR ADC4SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
* AHB3SMENR DAC1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
* AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
* AHB3SMENR ADF1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
* AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
* AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
* @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
* @arg @ref LL_AHB3_GRP1_PERIPH_PWR
* @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
* @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
* @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
* @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
* @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB3SMENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB3 peripheral clocks in Sleep and Stop modes is enabled or not
* @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
* AHB3SMENR PWRSMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
* AHB3SMENR ADC4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
* AHB3SMENR DAC1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
* AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
* AHB3SMENR ADF1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
* AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
* AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
* @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
* @arg @ref LL_AHB3_GRP1_PERIPH_PWR
* @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
* @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
* @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
* @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
* @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB3SMENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
* AHB3SMENR PWRSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
* AHB3SMENR ADC4SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
* AHB3SMENR DAC1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
* AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
* AHB3SMENR ADF1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
* AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
* AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
* @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1
* @arg @ref LL_AHB3_GRP1_PERIPH_PWR
* @arg @ref LL_AHB3_GRP1_PERIPH_ADC4
* @arg @ref LL_AHB3_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1
* @arg @ref LL_AHB3_GRP1_PERIPH_ADF1
* @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2
* @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3SMENR, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH
* @{
*/
/**
* @brief Enable AHB2 peripherals clock.
* @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_EnableClock\n
* AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_EnableClock\n
* AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_EnableClock\n
* AHB2ENR2 HSPI1EN LL_AHB2_GRP2_EnableClock\n
* AHB2ENR2 SRAM5EN LL_AHB2_GRP2_EnableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP2_PERIPH_ALL
* @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
* @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
* @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
*
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP2_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB2ENR2, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB2ENR2, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB2 peripheral clock is enabled or not
* @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_IsEnabledClock\n
* AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_IsEnabledClock\n
* AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_IsEnabledClock\n
* AHB2ENR2 HSPI1EN LL_AHB2_GRP2_IsEnabledClock\n
* AHB2ENR2 SRAM5EN LL_AHB2_GRP2_IsEnabledClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP2_PERIPH_ALL
* @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
* @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
* @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
*
* (*) value not defined in all devices.
* @retval None
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB2ENR2, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB2 peripherals clock.
* @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_DisableClock\n
* AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_DisableClock\n
* AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_DisableClock\n
* AHB2ENR2 HSPI1EN LL_AHB2_GRP2_DisableClock\n
* AHB2ENR2 SRAM5EN LL_AHB2_GRP2_DisableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP2_PERIPH_ALL
* @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
* @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
* @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP2_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2ENR2, Periphs);
}
/**
* @brief Force AHB2 peripherals reset.
* @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ForceReset\n
* AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ForceReset\n
* AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ForceReset\n
* AHB2RSTR2 HSPI1RST LL_AHB2_GRP2_ForceReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP2_PERIPH_ALL
* @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
* @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP2_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB2RSTR2, Periphs);
}
/**
* @brief Release AHB2 peripherals reset.
* @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ReleaseReset\n
* AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ReleaseReset\n
* AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ReleaseReset\n
* AHB2RSTR2 HSPI1RST LL_AHB2_GRP2_ReleaseReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP2_PERIPH_ALL
* @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
* @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP2_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2RSTR2, Periphs);
}
/**
* @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_EnableClockStopSleep\n
* AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n
* AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_EnableClockStopSleep\n
* AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n
* AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_EnableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP2_PERIPH_ALL
* @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
* @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
* @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP2_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB2SMENR2, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB2SMENR2, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not
* @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
* AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
* AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
* AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
* AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP2_PERIPH_ALL
* @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
* @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
* @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB2SMENR2, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_DisableClockStopSleep\n
* AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
* AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
* AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
* AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_DisableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP2_PERIPH_ALL
* @arg @ref LL_AHB2_GRP2_PERIPH_FSMC
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1
* @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2
* @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*)
* @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP2_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2SMENR2, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_APB1 APB1
* @{
*/
/**
* @brief Enable APB1 peripherals clock.
* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 USART6N LL_APB1_GRP1_EnableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4
* @arg @ref LL_APB1_GRP1_PERIPH_UART5
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB1ENR1, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
(void)tmpreg;
}
/**
* @brief Enable APB1 peripherals clock.
* @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
* APB1ENR2 I2C5EN LL_APB1_GRP2_EnableClock\n
* APB1ENR2 I2C6EN LL_APB1_GRP2_EnableClock\n
* APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock\n
* APB1ENR2 FDCAN1EN LL_APB1_GRP2_EnableClock\n
* APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4
* @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB1ENR2, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
(void)tmpreg;
}
/**
* @brief Check if APB1 peripheral clock is enabled or not
* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 USART6EN LL_APB1_GRP1_IsEnabledClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4
* @arg @ref LL_APB1_GRP1_PERIPH_UART5
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Check if APB1 peripheral clock is enabled or not
* @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
* APB1ENR2 I2C5EN LL_APB1_GRP2_IsEnabledClock\n
* APB1ENR2 I2C6EN LL_APB1_GRP2_IsEnabledClock\n
* APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock\n
* APB1ENR2 FDCAN1EN LL_APB1_GRP2_IsEnabledClock\n
* APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4
* @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable APB1 peripherals clock.
* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 USART6EN LL_APB1_GRP1_DisableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4
* @arg @ref LL_APB1_GRP1_PERIPH_UART5
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1ENR1, Periphs);
}
/**
* @brief Disable APB1 peripherals clock.
* @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
* APB1ENR2 I2C5EN LL_APB1_GRP2_DisableClock\n
* APB1ENR2 I2C6EN LL_APB1_GRP2_DisableClock\n
* APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock\n
* APB1ENR2 FDCAN1EN LL_APB1_GRP2_DisableClock\n
* APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4
* @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1ENR2, Periphs);
}
/**
* @brief Force APB1 peripherals reset.
* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 USART6RST LL_APB1_GRP1_ForceReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4
* @arg @ref LL_APB1_GRP1_PERIPH_UART5
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB1RSTR1, Periphs);
}
/**
* @brief Force APB1 peripherals reset.
* @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_DisableClock\n
* APB1RSTR2 I2C5RST LL_APB1_GRP2_DisableClock\n
* APB1RSTR2 I2C6RST LL_APB1_GRP2_DisableClock\n
* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_DisableClock\n
* APB1RSTR2 FDCAN1RST LL_APB1_GRP2_DisableClock\n
* APB1RSTR2 UCPDRST LL_APB1_GRP2_DisableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4
* @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB1RSTR2, Periphs);
}
/**
* @brief Release APB1 peripherals reset.
* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 USART6RST LL_APB1_GRP1_ReleaseReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4
* @arg @ref LL_APB1_GRP1_PERIPH_UART5
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1RSTR1, Periphs);
}
/**
* @brief Release APB1 peripherals reset.
* @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
* APB1RSTR2 I2C5RST LL_APB1_GRP2_ReleaseReset\n
* APB1RSTR2 I2C6RST LL_APB1_GRP2_ReleaseReset\n
* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset\n
* APB1RSTR2 FDCAN1RST LL_APB1_GRP2_ReleaseReset\n
* APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4
* @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1RSTR2, Periphs);
}
/**
* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 USART6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4
* @arg @ref LL_APB1_GRP1_PERIPH_UART5
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB1SMENR1, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
(void)tmpreg;
}
/**
* @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not
* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 USART3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 UART4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 UART5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 CRSSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* APB1SMENR1 USART6SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4
* @arg @ref LL_APB1_GRP1_PERIPH_UART5
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB1SMENR1, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 USART6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_ALL
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4
* @arg @ref LL_APB1_GRP1_PERIPH_UART5
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1SMENR1, Periphs);
}
/**
* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
* @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
* APB1SMENR2 I2C5SMEN LL_APB1_GRP2_EnableClockStopSleep\n
* APB1SMENR2 I2C6SMEN LL_APB1_GRP2_EnableClockStopSleep\n
* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep\n
* APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
* APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4
* @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB1SMENR2, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
(void)tmpreg;
}
/**
* @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not
* @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
* APB1SMENR2 I2C5SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
* APB1SMENR2 I2C6SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
* APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n
* APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4
* @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB1SMENR2, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
* @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
* APB1SMENR2 I2C5SMEN LL_APB1_GRP2_DisableClockStopSleep\n
* APB1SMENR2 I2C6SMEN LL_APB1_GRP2_DisableClockStopSleep\n
* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep\n
* APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
* APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_ALL
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4
* @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
* @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1SMENR2, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_APB2 APB2
* @{
*/
/**
* @brief Enable APB2 peripherals clock.
* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
* APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
* APB2ENR DSIHOSTEN LL_APB2_GRP1_EnableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB2ENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if APB2 peripheral clock is enabled or not
* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR DSIHOSTEN LL_APB2_GRP1_IsEnabledClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable APB2 peripherals clock.
* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
* APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
* APB2ENR DSIHOSTEN LL_APB2_GRP1_DisableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2ENR, Periphs);
}
/**
* @brief Force APB2 peripherals reset.
* @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
* APB2RSTR DSIHOSTRST LL_APB2_GRP1_ForceReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
*
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB2RSTR, Periphs);
}
/**
* @brief Release APB2 peripherals reset.
* @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
* APB2RSTR DSIHOSTRST LL_APB2_GRP1_ReleaseReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
*
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2RSTR, Periphs);
}
/**
* @brief Enable APB2 peripheral clocks in Sleep and Stop modes
* @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_EnableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB2SMENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not
* @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* APB2SMENR SPI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* APB2SMENR TIM8SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* APB2SMENR USART1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* APB2SMENR TIM15SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* APB2SMENR SAI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* APB2SMENR SAI2SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* APB2SMENR LTDCSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB2SMENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable APB2 peripheral clocks in Sleep and Stop modes
* @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_DisableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2SMENR, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_APB3 APB3
* @{
*/
/**
* @brief Enable APB3 peripherals clock.
* @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_EnableClock\n
* APB3ENR SPI3EN LL_APB3_GRP1_EnableClock\n
* APB3ENR LPUART1EN LL_APB3_GRP1_EnableClock\n
* APB3ENR I2C3EN LL_APB3_GRP1_EnableClock\n
* APB3ENR LPTIM1EN LL_APB3_GRP1_EnableClock\n
* APB3ENR LPTIM3EN LL_APB3_GRP1_EnableClock\n
* APB3ENR LPTIM4EN LL_APB3_GRP1_EnableClock\n
* APB3ENR OPAMPEN LL_APB3_GRP1_EnableClock\n
* APB3ENR COMPEN LL_APB3_GRP1_EnableClock\n
* APB3ENR VREFEN LL_APB3_GRP1_EnableClock\n
* APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_ALL
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_SPI3
* @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
* @arg @ref LL_APB3_GRP1_PERIPH_I2C3
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB3_GRP1_PERIPH_COMP
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
* @retval None
*/
__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB3ENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB3ENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if APB3 peripheral clock is enabled or not
* @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_IsEnabledClock\n
* APB3ENR SPI3EN LL_APB3_GRP1_IsEnabledClock\n
* APB3ENR LPUART1EN LL_APB3_GRP1_IsEnabledClock\n
* APB3ENR I2C3EN LL_APB3_GRP1_IsEnabledClock\n
* APB3ENR LPTIM1EN LL_APB3_GRP1_IsEnabledClock\n
* APB3ENR LPTIM3EN LL_APB3_GRP1_IsEnabledClock\n
* APB3ENR LPTIM4EN LL_APB3_GRP1_IsEnabledClock\n
* APB3ENR OPAMPEN LL_APB3_GRP1_IsEnabledClock\n
* APB3ENR COMPEN LL_APB3_GRP1_IsEnabledClock\n
* APB3ENR VREFEN LL_APB3_GRP1_IsEnabledClock\n
* APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_ALL
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_SPI3
* @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
* @arg @ref LL_APB3_GRP1_PERIPH_I2C3
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB3_GRP1_PERIPH_COMP
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable APB2 peripherals clock.
* @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_DisableClock\n
* APB3ENR SPI3EN LL_APB3_GRP1_DisableClock\n
* APB3ENR LPUART1EN LL_APB3_GRP1_DisableClock\n
* APB3ENR I2C3EN LL_APB3_GRP1_DisableClock\n
* APB3ENR LPTIM1EN LL_APB3_GRP1_DisableClock\n
* APB3ENR LPTIM3EN LL_APB3_GRP1_DisableClock\n
* APB3ENR LPTIM4EN LL_APB3_GRP1_DisableClock\n
* APB3ENR OPAMPEN LL_APB3_GRP1_DisableClock\n
* APB3ENR COMPEN LL_APB3_GRP1_DisableClock\n
* APB3ENR VREFEN LL_APB3_GRP1_DisableClock\n
* APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_ALL
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_SPI3
* @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
* @arg @ref LL_APB3_GRP1_PERIPH_I2C3
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB3_GRP1_PERIPH_COMP
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
* @retval None
*/
__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB3ENR, Periphs);
}
/**
* @brief Force APB3 peripherals reset.
* @rmtoll APB3RSTR SYSCFGRST LL_APB3_GRP1_ForceReset\n
* APB3RSTR SPI3RST LL_APB3_GRP1_ForceReset\n
* APB3RSTR LPUART1RST LL_APB3_GRP1_ForceReset\n
* APB3RSTR I2C3RST LL_APB3_GRP1_ForceReset\n
* APB3RSTR LPTIM1RST LL_APB3_GRP1_ForceReset\n
* APB3RSTR LPTIM3RST LL_APB3_GRP1_ForceReset\n
* APB3RSTR LPTIM4RST LL_APB3_GRP1_ForceReset\n
* APB3RSTR OPAMPRST LL_APB3_GRP1_ForceReset\n
* APB3RSTR COMPRST LL_APB3_GRP1_ForceReset\n
* APB3RSTR VREFRST LL_APB3_GRP1_ForceReset\n
* APB3RSTR RTCAPBRST LL_APB3_GRP1_ForceReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_ALL
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_SPI3
* @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
* @arg @ref LL_APB3_GRP1_PERIPH_I2C3
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB3_GRP1_PERIPH_COMP
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
* @retval None
*/
__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB3RSTR, Periphs);
}
/**
* @brief Release APB3 peripherals reset.
* @rmtoll APB3RSTR SYSCFGRST LL_APB3_GRP1_ReleaseReset\n
* APB3RSTR SPI3RST LL_APB3_GRP1_ReleaseReset\n
* APB3RSTR LPUART1RST LL_APB3_GRP1_ReleaseReset\n
* APB3RSTR I2C3RST LL_APB3_GRP1_ReleaseReset\n
* APB3RSTR LPTIM1RST LL_APB3_GRP1_ReleaseReset\n
* APB3RSTR LPTIM3RST LL_APB3_GRP1_ReleaseReset\n
* APB3RSTR LPTIM4RST LL_APB3_GRP1_ReleaseReset\n
* APB3RSTR OPAMPRST LL_APB3_GRP1_ReleaseReset\n
* APB3RSTR COMPRST LL_APB3_GRP1_ReleaseReset\n
* APB3RSTR VREFRST LL_APB3_GRP1_ReleaseReset\n
* APB3RSTR RTCAPBRST LL_APB3_GRP1_ReleaseReset\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_ALL
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_SPI3
* @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
* @arg @ref LL_APB3_GRP1_PERIPH_I2C3
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB3_GRP1_PERIPH_COMP
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
* @retval None
*/
__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB3RSTR, Periphs);
}
/**
* @brief Enable APB3 peripheral clocks in Sleep and Stop modes
* @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_EnableClockStopSleep\n
* APB3SMENR SPI3SMEN LL_APB3_GRP1_EnableClockStopSleep\n
* APB3SMENR LPUART1SMEN LL_APB3_GRP1_EnableClockStopSleep\n
* APB3SMENR I2C3SMEN LL_APB3_GRP1_EnableClockStopSleep\n
* APB3SMENR LPTIM1SMEN LL_APB3_GRP1_EnableClockStopSleep\n
* APB3SMENR LPTIM3SMEN LL_APB3_GRP1_EnableClockStopSleep\n
* APB3SMENR LPTIM4SMEN LL_APB3_GRP1_EnableClockStopSleep\n
* APB3SMENR OPAMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n
* APB3SMENR COMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n
* APB3SMENR VREFSMEN LL_APB3_GRP1_EnableClockStopSleep\n
* APB3SMENR RTCAPBSMEN LL_APB3_GRP1_EnableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_ALL
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_SPI3
* @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
* @arg @ref LL_APB3_GRP1_PERIPH_I2C3
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB3_GRP1_PERIPH_COMP
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
* @retval None
*/
__STATIC_INLINE void LL_APB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB3SMENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB3SMENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if APB3 peripheral clocks in Sleep and Stop modes is enabled or not
* @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* APB3SMENR SPI3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* APB3SMENR LPUART1SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* APB3SMENR I2C3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* APB3SMENR LPTIM1SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* APB3SMENR LPTIM3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* APB3SMENR LPTIM4SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* APB3SMENR OPAMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* APB3SMENR COMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* APB3SMENR VREFSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* APB3SMENR RTCAPBSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_ALL
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_SPI3
* @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
* @arg @ref LL_APB3_GRP1_PERIPH_I2C3
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB3_GRP1_PERIPH_COMP
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB3SMENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable APB3 peripheral clocks in Sleep and Stop modes
* @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_DisableClockStopSleep\n
* APB3SMENR SPI3SMEN LL_APB3_GRP1_DisableClockStopSleep\n
* APB3SMENR LPUART1SMEN LL_APB3_GRP1_DisableClockStopSleep\n
* APB3SMENR I2C3SMEN LL_APB3_GRP1_DisableClockStopSleep\n
* APB3SMENR LPTIM1SMEN LL_APB3_GRP1_DisableClockStopSleep\n
* APB3SMENR LPTIM3SMEN LL_APB3_GRP1_DisableClockStopSleep\n
* APB3SMENR LPTIM4SMEN LL_APB3_GRP1_DisableClockStopSleep\n
* APB3SMENR OPAMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n
* APB3SMENR COMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n
* APB3SMENR VREFSMEN LL_APB3_GRP1_DisableClockStopSleep\n
* APB3SMENR RTCAPBSMEN LL_APB3_GRP1_DisableClockStopSleep\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB3_GRP1_PERIPH_ALL
* @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB3_GRP1_PERIPH_SPI3
* @arg @ref LL_APB3_GRP1_PERIPH_LPUART1
* @arg @ref LL_APB3_GRP1_PERIPH_I2C3
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4
* @arg @ref LL_APB3_GRP1_PERIPH_OPAMP
* @arg @ref LL_APB3_GRP1_PERIPH_COMP
* @arg @ref LL_APB3_GRP1_PERIPH_VREF
* @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB
* @retval None
*/
__STATIC_INLINE void LL_APB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB3SMENR, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_SRDAMR SRDAMR
* @{
*/
/**
* @brief Enable SRDAMR peripheral clocks in autonomous mode
* @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR I2C3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR COMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR VREFAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR VREFRST LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR ADC4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR DAC1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR ADF1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL
* @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_COMPAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_VREFAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN
* @retval None
*/
__STATIC_INLINE void LL_SRDAMR_GRP1_EnableAutonomousClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->SRDAMR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->SRDAMR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if SRDAMR peripheral clock is enabled or not
* @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR I2C3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR COMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR VREFAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR VREFRST LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR ADC4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR DAC1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR ADF1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL
* @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_COMPAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_VREFAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SRDAMR_GRP1_IsEnabledAutonomousClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->SRDAMR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable SRDAMR peripheral clocks in Sleep and Stop modes
* @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR I2C3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR COMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR VREFAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR VREFRST LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR ADC4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR DAC1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR ADF1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL
* @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_COMPAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_VREFAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1AMEN
* @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN
* @retval None
*/
__STATIC_INLINE void LL_SRDAMR_GRP1_DisableAutonomousClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->SRDAMR, Periphs);
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RCC) */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_BUS_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_bus.h
|
C
|
apache-2.0
| 139,202
|
/**
******************************************************************************
* @file stm32u5xx_ll_comp.h
* @author MCD Application Team
* @brief Header file of COMP LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_COMP_H
#define STM32U5xx_LL_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (COMP1) || defined (COMP2)
/** @defgroup COMP_LL COMP
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup COMP_LL_Private_Constants COMP Private Constants
* @{
*/
/* Internal mask for pair of comparators instances window mode: */
/* To select into literals LL_COMP_WINDOWMODE_COMPx_INPUT_PLUS_COMMON */
/* the relevant bits for: */
/* (concatenation of multiple bits used in different registers) */
/* - Comparator instance selected as master for window mode : register offset */
/* - Window mode enable or disable: bit value */
#define LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK (0x00000000UL) /* Register of COMP instance odd (COMP1_CSR, ...)
defined as reference register */
#define LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...)
offset vs register of COMP instance odd */
#define LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK\
| LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
#define LL_COMP_WINDOWMODE_COMPX_SETTING_MASK (COMP_CSR_WINMODE)
#define LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK (COMP_CSR_WINOUT)
#define LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK (COMP_CSR_WINOUT << 1UL)
#define LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW (1UL)
/* COMP registers bits positions */
#define LL_COMP_WINDOWMODE_BITOFFSET_POS (11UL) /* Value equivalent to POSITION_VAL(COMP_CSR_WINMODE) */
#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup COMP_LL_Private_Macros COMP Private Macros
* @{
*/
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
*/
#define __COMP_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of COMP instance.
*/
typedef struct
{
uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed.
This parameter can be a value of @ref COMP_LL_EC_POWERMODE
This feature can be modified afterwards using
unitary function @ref LL_COMP_SetPowerMode(). */
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
This feature can be modified afterwards using
unitary function @ref LL_COMP_SetInputPlus(). */
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
This feature can be modified afterwards using
unitary function @ref LL_COMP_SetInputMinus(). */
uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
This feature can be modified afterwards using
unitary function @ref LL_COMP_SetInputHysteresis(). */
uint32_t OutputPolarity; /*!< Set comparator output polarity.
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
This feature can be modified afterwards using
unitary function @ref LL_COMP_SetOutputPolarity(). */
uint32_t OutputBlankingSource; /*!< Set comparator blanking source.
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
This feature can be modified afterwards using
unitary function @ref LL_COMP_SetOutputBlankingSource(). */
} LL_COMP_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
* @{
*/
/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
* @{
*/
#define LL_COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators 1 and 2 are independent */
#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
#define LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible) */
/**
* @}
*/
/** @defgroup COMP_LL_EC_COMMON_WINDOWOUTPUT Comparator common modes - Window output
* @{
*/
#define LL_COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. The same way, if both comparators output are high, then monitored signal is below window. */
#define LL_COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
#define LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */
#define LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */
/**
* @}
*/
/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
* @{
*/
#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< COMP power mode to high speed */
#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to medium speed */
#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE_1 | COMP_CSR_PWRMODE_0) /*!< COMP power mode to ultra-low power */
/**
* @}
*/
/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
* @{
*/
#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
#define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA2 for COMP1) */
/**
* @}
*/
/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
* @{
*/
#define LL_COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL ) /*!< Comparator input minus connected to 1/4 VrefInt */
#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */
#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */
#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */
#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
/**
* @}
*/
/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
* @{
*/
#define LL_COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */
#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */
#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
/**
* @}
*/
/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
* @{
*/
#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
/**
* @}
*/
/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
* @{
*/
#define LL_COMP_BLANKINGSRC_NONE ( 0x00000000UL) /*!<Comparator output without blanking */
#define LL_COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKSEL_0) /*!< Comparator output blanking source TIM1 OC5 for COMP1 Instance */
#define LL_COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKSEL_1) /*!< Comparator output blanking source TIM2 OC3 for COMP1 Instance */
#define LL_COMP_BLANKINGSRC_TIM3_OC3 (COMP_CSR_BLANKSEL_2) /*!< Comparator output blanking source TIM3 OC3 for COMP1 Instance */
#define LL_COMP_BLANKINGSRC_TIM3_OC4 (COMP_CSR_BLANKSEL_0) /*!< Comparator output blanking source TIM3 OC4 for COMP2 Instance */
#define LL_COMP_BLANKINGSRC_TIM8_OC5 (COMP_CSR_BLANKSEL_1) /*!< Comparator output blanking source TIM8 OC5 for COMP2 Instance */
#define LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKSEL_2) /*!< Comparator output blanking source TIM15 OC1 for COMP2 Instance */
/**
* @}
*/
/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
* @{
*/
#define LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
#define LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
/**
* @}
*/
/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays
* @note Only COMP peripheral HW delays are defined in COMP LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Delay for comparator startup time. */
/* Note: Delay required to reach propagation delay specification. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
#define LL_COMP_DELAY_STARTUP_US ( 80UL) /*!< Delay for COMP startup time */
/* Delay for comparator voltage scaler stabilization time. */
/* Note: Voltage scaler is used when selecting comparator input */
/* based on VrefInt: VrefInt or subdivision of VrefInt. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART_SCALER"). */
/* Unit: us */
#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL) /*!< Delay for COMP voltage scaler stabilization time */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
* @{
*/
/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
* @{
*/
/**
* @brief Write a value in COMP register
* @param __INSTANCE__ comparator instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in COMP register
* @param __INSTANCE__ comparator instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
* @{
*/
/**
* @brief Helper macro to select the COMP common instance
* to which is belonging the selected COMP instance.
* @note COMP common register instance can be used to
* set parameters common to several COMP instances.
* Refer to functions having argument "COMPxy_COMMON" as parameter.
* @param __COMPx__ COMP instance
* @retval COMP common instance or value "0" if there is no COMP common instance.
*/
#define __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
* @{
*/
/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration
* of COMP hierarchical scope: common to several COMP instances
* @{
*/
/**
* @brief Set window mode of a pair of comparators instances
* (2 consecutive COMP instances COMP<x> and COMP<x+1>).
* @rmtoll CSR WINMODE LL_COMP_SetCommonWindowMode
* @param COMPxy_COMMON Comparator common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
* @param WindowMode This parameter can be one of the following values:
* @arg @ref LL_COMP_WINDOWMODE_DISABLE
* @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
* @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (1)
*
* (1) Parameter available on all STM32U5 devices, must be used with comparator common instance COMP12_COMMON
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
{
/* Note: On this STM32 series, window mode can be set from any instance */
/* of the pair of comparator instances. */
__IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD,
(WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK));
/* Clear the potential previous setting of window mode */
__IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD,
(~(WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL)
);
CLEAR_BIT(*preg_clear, COMP_CSR_WINMODE);
/* Set window mode */
MODIFY_REG(*preg, COMP_CSR_WINMODE, (WindowMode & LL_COMP_WINDOWMODE_COMPX_SETTING_MASK));
}
/**
* @brief Get window mode of a pair of comparators instances
* (2 consecutive COMP instances COMP<x> and COMP<x+1>).
* @rmtoll CSR WINMODE LL_COMP_GetCommonWindowMode
* @param COMPxy_COMMON Comparator common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_WINDOWMODE_DISABLE
* @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (1)
* @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (1)
*
* (1) Parameter available on all STM32U5 devices, must be used with comparator common instance COMP12_COMMON
*/
__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
{
/* Note: On this STM32 series, window mode can be set from any instance */
/* of the pair of comparator instances. */
const uint32_t window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE);
const uint32_t window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
return (uint32_t)(window_mode_comp_odd
| window_mode_comp_even
| ((window_mode_comp_even >> LL_COMP_WINDOWMODE_BITOFFSET_POS)
* LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
);
}
/**
* @brief Set window output of a pair of comparators instances
* (2 consecutive COMP instances COMP<x> and COMP<x+1>).
* @rmtoll CSR WINOUT LL_COMP_SetCommonWindowOutput
* @param COMPxy_COMMON Comparator common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
* @param WindowOutput This parameter can be one of the following values:
* @arg @ref LL_COMP_WINDOWOUTPUT_EACH_COMP
* @arg @ref LL_COMP_WINDOWOUTPUT_COMP1 (1)
* @arg @ref LL_COMP_WINDOWOUTPUT_COMP2 (1)
* @arg @ref LL_COMP_WINDOWOUTPUT_BOTH
*
* (1) Parameter available on all STM32U5 devices, must be used with comparator common instance COMP12_COMMON
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput)
{
__IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD,
(WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK));
/* Clear the potential previous setting of window output on the relevant comparator instance */
/* (clear bit of window output unless specific case of setting of comparator both output selected) */
__IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD,
(~(WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) & 0x1UL)
);
MODIFY_REG(*preg_clear,
COMP_CSR_WINOUT,
((WindowOutput & LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) >> LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW)
);
/* Set window output */
MODIFY_REG(*preg,
COMP_CSR_WINOUT,
(WindowOutput & LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK)
);
}
/**
* @brief Get window output of a pair of comparators instances
* (2 consecutive COMP instances COMP<x> and COMP<x+1>).
* @rmtoll CSR WINMODE LL_COMP_GetCommonWindowOutput
* @param COMPxy_COMMON Comparator common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_WINDOWOUTPUT_EACH_COMP
* @arg @ref LL_COMP_WINDOWOUTPUT_COMP1 (1)
* @arg @ref LL_COMP_WINDOWOUTPUT_COMP2 (1)
* @arg @ref LL_COMP_WINDOWOUTPUT_BOTH
*
* (1) Parameter available on all STM32U5 devices, must be used with comparator common instance COMP12_COMMON
*/
__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON)
{
const uint32_t window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT);
const uint32_t window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
/* Construct value corresponding to LL_COMP_WINDOWOUTPUT_xxx */
return (uint32_t)(window_output_comp_odd
| window_output_comp_even
| ((window_output_comp_even >> COMP_CSR_WINOUT_Pos) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK)
| (window_output_comp_odd + window_output_comp_even));
}
/**
* @}
*/
/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes
* @{
*/
/**
* @brief Set comparator instance operating mode to adjust power and speed.
* @rmtoll CSR PWRMODE LL_COMP_SetPowerMode
* @param COMPx Comparator instance
* @param PowerMode This parameter can be one of the following values:
* @arg @ref LL_COMP_POWERMODE_HIGHSPEED
* @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
* @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_PWRMODE, PowerMode);
}
/**
* @brief Get comparator instance operating mode to adjust power and speed.
* @rmtoll CSR PWRMODE LL_COMP_GetPowerMode
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_POWERMODE_HIGHSPEED
* @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
* @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
*/
__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE));
}
/**
* @}
*/
/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
* @{
*/
/**
* @brief Set comparator inputs minus (inverting) and plus (non-inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note On this STM32 series, a voltage scaler is used
* when COMP input is based on VrefInt (VrefInt or subdivision
* of VrefInt):
* Voltage scaler requires a delay for voltage stabilization.
* Refer to device datasheet, parameter "tSTART_SCALER".
* @rmtoll CSR INMSEL LL_COMP_ConfigInputs\n
* CSR INPSEL LL_COMP_ConfigInputs\n
* @param COMPx Comparator instance
* @param InputMinus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
* @param InputPlus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
* @arg @ref LL_COMP_INPUT_PLUS_IO3
* @retval None
*/
__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_INPSEL, InputMinus | InputPlus);
}
/**
* @brief Set comparator input plus (non-inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR INPSEL LL_COMP_SetInputPlus
* @param COMPx Comparator instance
* @param InputPlus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
* @arg @ref LL_COMP_INPUT_PLUS_IO3
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
}
/**
* @brief Get comparator input plus (non-inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR INPSEL LL_COMP_GetInputPlus
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
* @arg @ref LL_COMP_INPUT_PLUS_IO3
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
}
/**
* @brief Set comparator input minus (inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note On this STM32 series, a voltage scaler is used
* when COMP input is based on VrefInt (VrefInt or subdivision
* of VrefInt):
* Voltage scaler requires a delay for voltage stabilization.
* Refer to device datasheet, parameter "tSTART_SCALER".
* @rmtoll CSR INMSEL LL_COMP_SetInputMinus
* @param COMPx Comparator instance
* @param InputMinus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL, InputMinus);
}
/**
* @brief Get comparator input minus (inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR INMSEL LL_COMP_GetInputMinus
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL));
}
/**
* @brief Set comparator instance hysteresis mode of the input minus (inverting input).
* @rmtoll CSR HYST LL_COMP_SetInputHysteresis
* @param COMPx Comparator instance
* @param InputHysteresis This parameter can be one of the following values:
* @arg @ref LL_COMP_HYSTERESIS_NONE
* @arg @ref LL_COMP_HYSTERESIS_LOW
* @arg @ref LL_COMP_HYSTERESIS_MEDIUM
* @arg @ref LL_COMP_HYSTERESIS_HIGH
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
}
/**
* @brief Get comparator instance hysteresis mode of the minus (inverting) input.
* @rmtoll CSR HYST LL_COMP_GetInputHysteresis
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_HYSTERESIS_NONE
* @arg @ref LL_COMP_HYSTERESIS_LOW
* @arg @ref LL_COMP_HYSTERESIS_MEDIUM
* @arg @ref LL_COMP_HYSTERESIS_HIGH
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
}
/**
* @}
*/
/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
* @{
*/
/**
* @brief Set comparator instance output polarity.
* @rmtoll CSR POLARITY LL_COMP_SetOutputPolarity
* @param COMPx Comparator instance
* @param OutputPolarity This parameter can be one of the following values:
* @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
* @arg @ref LL_COMP_OUTPUTPOL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
}
/**
* @brief Get comparator instance output polarity.
* @rmtoll CSR POLARITY LL_COMP_GetOutputPolarity
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
* @arg @ref LL_COMP_OUTPUTPOL_INVERTED
*/
__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
}
/**
* @brief Set comparator instance blanking source.
* @note Blanking source may be specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note Availability of parameters of blanking source from timer
* depends on timers availability on the selected device.
* @rmtoll CSR BLANKSEL LL_COMP_SetOutputBlankingSource
* @param COMPx Comparator instance
* @param BlankingSource This parameter can be one of the following values:
* @arg @ref LL_COMP_BLANKINGSRC_NONE
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKSEL, BlankingSource);
}
/**
* @brief Get comparator instance blanking source.
* @note Availability of parameters of blanking source from timer
* depends on timers availability on the selected device.
* @note Blanking source may be specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR BLANKSEL LL_COMP_GetOutputBlankingSource
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_BLANKINGSRC_NONE
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
*/
__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKSEL));
}
/**
* @}
*/
/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
* @{
*/
/**
* @brief Enable comparator instance.
* @note After enable from off state, comparator requires a delay
* to reach reach propagation delay specification.
* Refer to device datasheet, parameter "tSTART".
* @rmtoll CSR EN LL_COMP_Enable
* @param COMPx Comparator instance
* @retval None
*/
__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
{
SET_BIT(COMPx->CSR, COMP_CSR_EN);
}
/**
* @brief Disable comparator instance.
* @rmtoll CSR EN LL_COMP_Disable
* @param COMPx Comparator instance
* @retval None
*/
__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
{
CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
}
/**
* @brief Get comparator enable state
* (0: COMP is disabled, 1: COMP is enabled)
* @rmtoll CSR EN LL_COMP_IsEnabled
* @param COMPx Comparator instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
{
return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL);
}
/**
* @brief Lock comparator instance.
* @note Once locked, comparator configuration can be accessed in read-only.
* @note The only way to unlock the comparator is a device hardware reset.
* @rmtoll CSR LOCK LL_COMP_Lock
* @param COMPx Comparator instance
* @retval None
*/
__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
{
SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
}
/**
* @brief Get comparator lock state
* (0: COMP is unlocked, 1: COMP is locked).
* @note Once locked, comparator configuration can be accessed in read-only.
* @note The only way to unlock the comparator is a device hardware reset.
* @rmtoll CSR LOCK LL_COMP_IsLocked
* @param COMPx Comparator instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
{
return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL);
}
/**
* @brief Read comparator instance output level.
* @note The comparator output level depends on the selected polarity
* (Refer to function @ref LL_COMP_SetOutputPolarity()).
* If the comparator polarity is not inverted:
* - Comparator output is low when the input plus
* is at a lower voltage than the input minus
* - Comparator output is high when the input plus
* is at a higher voltage than the input minus
* If the comparator polarity is inverted:
* - Comparator output is high when the input plus
* is at a lower voltage than the input minus
* - Comparator output is low when the input plus
* is at a higher voltage than the input minus
* @rmtoll CSR VALUE LL_COMP_ReadOutputLevel
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
* @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
*/
__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
>> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* COMP1 || COMP2 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_COMP_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_comp.h
|
C
|
apache-2.0
| 39,227
|
/**
******************************************************************************
* @file stm32u5xx_ll_cordic.h
* @author MCD Application Team
* @brief Header file of CORDIC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_CORDIC_H
#define STM32U5xx_LL_CORDIC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(CORDIC)
/** @defgroup CORDIC_LL CORDIC
* @{
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORDIC_LL_Exported_Constants CORDIC Exported Constants
* @{
*/
/** @defgroup CORDIC_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_CORDIC_ReadReg function.
* @{
*/
#define LL_CORDIC_FLAG_RRDY CORDIC_CSR_RRDY
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_CORDIC_ReadReg and LL_CORDIC_WriteReg functions.
* @{
*/
#define LL_CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result Ready interrupt enable */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_FUNCTION FUNCTION
* @{
*/
#define LL_CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */
#define LL_CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */
#define LL_CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */
#define LL_CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */
#define LL_CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */
#define LL_CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */
#define LL_CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */
#define LL_CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
#define LL_CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
#define LL_CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_PRECISION PRECISION
* @{
*/
#define LL_CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
#define LL_CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
| CORDIC_CSR_PRECISION_0))
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_SCALE SCALE
* @{
*/
#define LL_CORDIC_SCALE_0 (0x00000000U)
#define LL_CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
#define LL_CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
#define LL_CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
#define LL_CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
#define LL_CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
#define LL_CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
#define LL_CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE
* @{
*/
#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
32-bit data input (Q1.31 format), or two
16-bit data input (Q1.15 format) packed
in one 32 bits Data */
#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
(Q1.31 format) */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_NBREAD NBREAD
* @{
*/
#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
32-bit data output (Q1.31 format), or two
16-bit data output (Q1.15 format) packed
in one 32 bits Data */
#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
(Q1.31 format) */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_INSIZE INSIZE
* @{
*/
#define LL_CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
#define LL_CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_OUTSIZE OUTSIZE
* @{
*/
#define LL_CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
#define LL_CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_DMA_REG_DATA DMA register data
* @{
*/
#define LL_CORDIC_DMA_REG_DATA_IN (0x00000000U) /*!< Get address of input data register */
#define LL_CORDIC_DMA_REG_DATA_OUT (0x00000001U) /*!< Get address of output data register */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CORDIC_LL_Exported_Macros CORDIC Exported Macros
* @{
*/
/** @defgroup CORDIC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CORDIC register.
* @param __INSTANCE__ CORDIC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CORDIC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in CORDIC register.
* @param __INSTANCE__ CORDIC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CORDIC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions
* @{
*/
/** @defgroup CORDIC_LL_EF_Configuration CORDIC Configuration functions
* @{
*/
/**
* @brief Configure the CORDIC processing.
* @note This function set all parameters of CORDIC processing.
* These parameters can also be set individually using
* dedicated functions:
* - @ref LL_CORDIC_SetFunction()
* - @ref LL_CORDIC_SetPrecision()
* - @ref LL_CORDIC_SetScale()
* - @ref LL_CORDIC_SetNbWrite()
* - @ref LL_CORDIC_SetNbRead()
* - @ref LL_CORDIC_SetInSize()
* - @ref LL_CORDIC_SetOutSize()
* @rmtoll CSR FUNC LL_CORDIC_Config\n
* CSR PRECISION LL_CORDIC_Config\n
* CSR SCALE LL_CORDIC_Config\n
* CSR NARGS LL_CORDIC_Config\n
* CSR NRES LL_CORDIC_Config\n
* CSR ARGSIZE LL_CORDIC_Config\n
* CSR RESIZE LL_CORDIC_Config
* @param CORDICx CORDIC instance
* @param Function parameter can be one of the following values:
* @arg @ref LL_CORDIC_FUNCTION_COSINE
* @arg @ref LL_CORDIC_FUNCTION_SINE
* @arg @ref LL_CORDIC_FUNCTION_PHASE
* @arg @ref LL_CORDIC_FUNCTION_MODULUS
* @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_HCOSINE
* @arg @ref LL_CORDIC_FUNCTION_HSINE
* @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
* @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
* @param Precision parameter can be one of the following values:
* @arg @ref LL_CORDIC_PRECISION_1CYCLE
* @arg @ref LL_CORDIC_PRECISION_2CYCLES
* @arg @ref LL_CORDIC_PRECISION_3CYCLES
* @arg @ref LL_CORDIC_PRECISION_4CYCLES
* @arg @ref LL_CORDIC_PRECISION_5CYCLES
* @arg @ref LL_CORDIC_PRECISION_6CYCLES
* @arg @ref LL_CORDIC_PRECISION_7CYCLES
* @arg @ref LL_CORDIC_PRECISION_8CYCLES
* @arg @ref LL_CORDIC_PRECISION_9CYCLES
* @arg @ref LL_CORDIC_PRECISION_10CYCLES
* @arg @ref LL_CORDIC_PRECISION_11CYCLES
* @arg @ref LL_CORDIC_PRECISION_12CYCLES
* @arg @ref LL_CORDIC_PRECISION_13CYCLES
* @arg @ref LL_CORDIC_PRECISION_14CYCLES
* @arg @ref LL_CORDIC_PRECISION_15CYCLES
* @param Scale parameter can be one of the following values:
* @arg @ref LL_CORDIC_SCALE_0
* @arg @ref LL_CORDIC_SCALE_1
* @arg @ref LL_CORDIC_SCALE_2
* @arg @ref LL_CORDIC_SCALE_3
* @arg @ref LL_CORDIC_SCALE_4
* @arg @ref LL_CORDIC_SCALE_5
* @arg @ref LL_CORDIC_SCALE_6
* @arg @ref LL_CORDIC_SCALE_7
* @param NbWrite parameter can be one of the following values:
* @arg @ref LL_CORDIC_NBWRITE_1
* @arg @ref LL_CORDIC_NBWRITE_2
* @param NbRead parameter can be one of the following values:
* @arg @ref LL_CORDIC_NBREAD_1
* @arg @ref LL_CORDIC_NBREAD_2
* @param InSize parameter can be one of the following values:
* @arg @ref LL_CORDIC_INSIZE_32BITS
* @arg @ref LL_CORDIC_INSIZE_16BITS
* @param OutSize parameter can be one of the following values:
* @arg @ref LL_CORDIC_OUTSIZE_32BITS
* @arg @ref LL_CORDIC_OUTSIZE_16BITS
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale,
uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
{
MODIFY_REG(CORDICx->CSR,
CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE |
CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE,
Function | Precision | Scale |
NbWrite | NbRead | InSize | OutSize);
}
/**
* @brief Configure function.
* @rmtoll CSR FUNC LL_CORDIC_SetFunction
* @param CORDICx CORDIC Instance
* @param Function parameter can be one of the following values:
* @arg @ref LL_CORDIC_FUNCTION_COSINE
* @arg @ref LL_CORDIC_FUNCTION_SINE
* @arg @ref LL_CORDIC_FUNCTION_PHASE
* @arg @ref LL_CORDIC_FUNCTION_MODULUS
* @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_HCOSINE
* @arg @ref LL_CORDIC_FUNCTION_HSINE
* @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
* @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Function)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_FUNC, Function);
}
/**
* @brief Return function.
* @rmtoll CSR FUNC LL_CORDIC_GetFunction
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_FUNCTION_COSINE
* @arg @ref LL_CORDIC_FUNCTION_SINE
* @arg @ref LL_CORDIC_FUNCTION_PHASE
* @arg @ref LL_CORDIC_FUNCTION_MODULUS
* @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_HCOSINE
* @arg @ref LL_CORDIC_FUNCTION_HSINE
* @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
* @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_FUNC));
}
/**
* @brief Configure precision in cycles number.
* @rmtoll CSR PRECISION LL_CORDIC_SetPrecision
* @param CORDICx CORDIC Instance
* @param Precision parameter can be one of the following values:
* @arg @ref LL_CORDIC_PRECISION_1CYCLE
* @arg @ref LL_CORDIC_PRECISION_2CYCLES
* @arg @ref LL_CORDIC_PRECISION_3CYCLES
* @arg @ref LL_CORDIC_PRECISION_4CYCLES
* @arg @ref LL_CORDIC_PRECISION_5CYCLES
* @arg @ref LL_CORDIC_PRECISION_6CYCLES
* @arg @ref LL_CORDIC_PRECISION_7CYCLES
* @arg @ref LL_CORDIC_PRECISION_8CYCLES
* @arg @ref LL_CORDIC_PRECISION_9CYCLES
* @arg @ref LL_CORDIC_PRECISION_10CYCLES
* @arg @ref LL_CORDIC_PRECISION_11CYCLES
* @arg @ref LL_CORDIC_PRECISION_12CYCLES
* @arg @ref LL_CORDIC_PRECISION_13CYCLES
* @arg @ref LL_CORDIC_PRECISION_14CYCLES
* @arg @ref LL_CORDIC_PRECISION_15CYCLES
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Precision)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_PRECISION, Precision);
}
/**
* @brief Return precision in cycles number.
* @rmtoll CSR PRECISION LL_CORDIC_GetPrecision
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_PRECISION_1CYCLE
* @arg @ref LL_CORDIC_PRECISION_2CYCLES
* @arg @ref LL_CORDIC_PRECISION_3CYCLES
* @arg @ref LL_CORDIC_PRECISION_4CYCLES
* @arg @ref LL_CORDIC_PRECISION_5CYCLES
* @arg @ref LL_CORDIC_PRECISION_6CYCLES
* @arg @ref LL_CORDIC_PRECISION_7CYCLES
* @arg @ref LL_CORDIC_PRECISION_8CYCLES
* @arg @ref LL_CORDIC_PRECISION_9CYCLES
* @arg @ref LL_CORDIC_PRECISION_10CYCLES
* @arg @ref LL_CORDIC_PRECISION_11CYCLES
* @arg @ref LL_CORDIC_PRECISION_12CYCLES
* @arg @ref LL_CORDIC_PRECISION_13CYCLES
* @arg @ref LL_CORDIC_PRECISION_14CYCLES
* @arg @ref LL_CORDIC_PRECISION_15CYCLES
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_PRECISION));
}
/**
* @brief Configure scaling factor.
* @rmtoll CSR SCALE LL_CORDIC_SetScale
* @param CORDICx CORDIC Instance
* @param Scale parameter can be one of the following values:
* @arg @ref LL_CORDIC_SCALE_0
* @arg @ref LL_CORDIC_SCALE_1
* @arg @ref LL_CORDIC_SCALE_2
* @arg @ref LL_CORDIC_SCALE_3
* @arg @ref LL_CORDIC_SCALE_4
* @arg @ref LL_CORDIC_SCALE_5
* @arg @ref LL_CORDIC_SCALE_6
* @arg @ref LL_CORDIC_SCALE_7
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_SCALE, Scale);
}
/**
* @brief Return scaling factor.
* @rmtoll CSR SCALE LL_CORDIC_GetScale
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_SCALE_0
* @arg @ref LL_CORDIC_SCALE_1
* @arg @ref LL_CORDIC_SCALE_2
* @arg @ref LL_CORDIC_SCALE_3
* @arg @ref LL_CORDIC_SCALE_4
* @arg @ref LL_CORDIC_SCALE_5
* @arg @ref LL_CORDIC_SCALE_6
* @arg @ref LL_CORDIC_SCALE_7
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetScale(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_SCALE));
}
/**
* @brief Configure number of 32-bit write expected for one calculation.
* @rmtoll CSR NARGS LL_CORDIC_SetNbWrite
* @param CORDICx CORDIC Instance
* @param NbWrite parameter can be one of the following values:
* @arg @ref LL_CORDIC_NBWRITE_1
* @arg @ref LL_CORDIC_NBWRITE_2
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWrite)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NARGS, NbWrite);
}
/**
* @brief Return number of 32-bit write expected for one calculation.
* @rmtoll CSR NARGS LL_CORDIC_GetNbWrite
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_NBWRITE_1
* @arg @ref LL_CORDIC_NBWRITE_2
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NARGS));
}
/**
* @brief Configure number of 32-bit read expected after one calculation.
* @rmtoll CSR NRES LL_CORDIC_SetNbRead
* @param CORDICx CORDIC Instance
* @param NbRead parameter can be one of the following values:
* @arg @ref LL_CORDIC_NBREAD_1
* @arg @ref LL_CORDIC_NBREAD_2
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRead)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NRES, NbRead);
}
/**
* @brief Return number of 32-bit read expected after one calculation.
* @rmtoll CSR NRES LL_CORDIC_GetNbRead
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_NBREAD_1
* @arg @ref LL_CORDIC_NBREAD_2
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NRES));
}
/**
* @brief Configure width of input data.
* @rmtoll CSR ARGSIZE LL_CORDIC_SetInSize
* @param CORDICx CORDIC Instance
* @param InSize parameter can be one of the following values:
* @arg @ref LL_CORDIC_INSIZE_32BITS
* @arg @ref LL_CORDIC_INSIZE_16BITS
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSize)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_ARGSIZE, InSize);
}
/**
* @brief Return width of input data.
* @rmtoll CSR ARGSIZE LL_CORDIC_GetInSize
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_INSIZE_32BITS
* @arg @ref LL_CORDIC_INSIZE_16BITS
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_ARGSIZE));
}
/**
* @brief Configure width of output data.
* @rmtoll CSR RESIZE LL_CORDIC_SetOutSize
* @param CORDICx CORDIC Instance
* @param OutSize parameter can be one of the following values:
* @arg @ref LL_CORDIC_OUTSIZE_32BITS
* @arg @ref LL_CORDIC_OUTSIZE_16BITS
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutSize)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_RESSIZE, OutSize);
}
/**
* @brief Return width of output data.
* @rmtoll CSR RESIZE LL_CORDIC_GetOutSize
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_OUTSIZE_32BITS
* @arg @ref LL_CORDIC_OUTSIZE_16BITS
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_RESSIZE));
}
/**
* @}
*/
/** @defgroup CORDIC_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable CORDIC result ready interrupt
* @rmtoll CSR IEN LL_CORDIC_EnableIT
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_EnableIT(CORDIC_TypeDef *CORDICx)
{
SET_BIT(CORDICx->CSR, CORDIC_CSR_IEN);
}
/**
* @brief Disable CORDIC result ready interrupt
* @rmtoll CSR IEN LL_CORDIC_DisableIT
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx)
{
CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_IEN);
}
/**
* @brief Check CORDIC result ready interrupt state.
* @rmtoll CSR IEN LL_CORDIC_IsEnabledIT
* @param CORDICx CORDIC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(CORDIC_TypeDef *CORDICx)
{
return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_IEN) == (CORDIC_CSR_IEN)) ? 1U : 0U);
}
/**
* @}
*/
/** @defgroup CORDIC_LL_EF_DMA_Management DMA_Management
* @{
*/
/**
* @brief Enable CORDIC DMA read channel request.
* @rmtoll CSR DMAREN LL_CORDIC_EnableDMAReq_RD
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_EnableDMAReq_RD(CORDIC_TypeDef *CORDICx)
{
SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN);
}
/**
* @brief Disable CORDIC DMA read channel request.
* @rmtoll CSR DMAREN LL_CORDIC_DisableDMAReq_RD
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx)
{
CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN);
}
/**
* @brief Check CORDIC DMA read channel request state.
* @rmtoll CSR DMAREN LL_CORDIC_IsEnabledDMAReq_RD
* @param CORDICx CORDIC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(CORDIC_TypeDef *CORDICx)
{
return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U);
}
/**
* @brief Enable CORDIC DMA write channel request.
* @rmtoll CSR DMAWEN LL_CORDIC_EnableDMAReq_WR
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_EnableDMAReq_WR(CORDIC_TypeDef *CORDICx)
{
SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN);
}
/**
* @brief Disable CORDIC DMA write channel request.
* @rmtoll CSR DMAWEN LL_CORDIC_DisableDMAReq_WR
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx)
{
CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN);
}
/**
* @brief Check CORDIC DMA write channel request state.
* @rmtoll CSR DMAWEN LL_CORDIC_IsEnabledDMAReq_WR
* @param CORDICx CORDIC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx)
{
return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U);
}
/**
* @brief Get the CORDIC data register address used for DMA transfer.
* @rmtoll RDATA RES LL_CORDIC_DMA_GetRegAddr\n
* @rmtoll WDATA ARG LL_CORDIC_DMA_GetRegAddr
* @param CORDICx CORDIC Instance
* @param Direction parameter can be one of the following values:
* @arg @ref LL_CORDIC_DMA_REG_DATA_IN
* @arg @ref LL_CORDIC_DMA_REG_DATA_OUT
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint32_t Direction)
{
uint32_t data_reg_addr;
if (Direction == LL_CORDIC_DMA_REG_DATA_OUT)
{
/* return address of RDATA register */
data_reg_addr = (uint32_t) &(CORDICx->RDATA);
}
else
{
/* return address of WDATA register */
data_reg_addr = (uint32_t) &(CORDICx->WDATA);
}
return data_reg_addr;
}
/**
* @}
*/
/** @defgroup CORDIC_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check CORDIC result ready flag state.
* @rmtoll CSR RRDY LL_CORDIC_IsActiveFlag_RRDY
* @param CORDICx CORDIC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(CORDIC_TypeDef *CORDICx)
{
return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U);
}
/**
* @}
*/
/** @defgroup CORDIC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write 32-bit input data for the CORDIC processing.
* @rmtoll WDATA ARG LL_CORDIC_WriteData
* @param CORDICx CORDIC Instance
* @param InData 0 .. 0xFFFFFFFF : 32-bit value to be provided as input data for CORDIC processing.
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InData)
{
WRITE_REG(CORDICx->WDATA, InData);
}
/**
* @brief Return 32-bit output data of CORDIC processing.
* @rmtoll RDATA RES LL_CORDIC_ReadData
* @param CORDICx CORDIC Instance
* @retval 32-bit output data of CORDIC processing.
*/
__STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_REG(CORDICx->RDATA));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CORDIC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_CORDIC_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h
|
C
|
apache-2.0
| 28,266
|
/**
******************************************************************************
* @file stm32u5xx_ll_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) API to access to MCU info (CPUID register)
(+) API to enable fault handler (SHCSR accesses)
(+) API to enable and disable the MPU secure and non-secure
(+) API to configure the region of MPU secure and non-secure
(+) API to configure the attributes region of MPU secure and non-secure
@endverbatim
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_CORTEX_H
#define STM32U5xx_LL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
/** @defgroup CORTEX_LL CORTEX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes
* @{
*/
/* Register MPU_RBAR (Cortex-M33) : bits [4:0] */
#define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants
* @{
*/
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
* @{
*/
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick
clock source */
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
clock source */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
* @{
*/
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
#define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
/**
* @}
*/
/** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U
#define LL_MPU_CTRL_HARDFAULT_NMI 2U
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U
#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U
/**
* @}
*/
/** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes
* @{
*/
#define LL_MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
#define LL_MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
#define LL_MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */
#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
/**
* @}
*/
/** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable
* @{
*/
#define LL_MPU_REGION_ENABLE 1U
#define LL_MPU_REGION_DISABLE 0U
/**
* @}
*/
/** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access
* @{
*/
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos)
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos)
/**
* @}
*/
/** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable
* @{
*/
#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos)
#define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos)
#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos)
/**
* @}
*/
/** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes
* @{
*/
#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos)
#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos)
#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos)
#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos)
/**
* @}
*/
/** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index
* @{
*/
#define LL_MPU_REGION_NUMBER0 0U
#define LL_MPU_REGION_NUMBER1 1U
#define LL_MPU_REGION_NUMBER2 2U
#define LL_MPU_REGION_NUMBER3 3U
#define LL_MPU_REGION_NUMBER4 4U
#define LL_MPU_REGION_NUMBER5 5U
#define LL_MPU_REGION_NUMBER6 6U
#define LL_MPU_REGION_NUMBER7 7U
/**
* @}
*/
/** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index
* @{
*/
#define LL_MPU_ATTRIBUTES_NUMBER0 0U
#define LL_MPU_ATTRIBUTES_NUMBER1 1U
#define LL_MPU_ATTRIBUTES_NUMBER2 2U
#define LL_MPU_ATTRIBUTES_NUMBER3 3U
#define LL_MPU_ATTRIBUTES_NUMBER4 4U
#define LL_MPU_ATTRIBUTES_NUMBER5 5U
#define LL_MPU_ATTRIBUTES_NUMBER6 6U
#define LL_MPU_ATTRIBUTES_NUMBER7 7U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions
* @{
*/
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
* @brief CORTEX SYSTICK LL module driver
* @{
*/
/**
* @brief This function checks if the Systick counter flag is active or not.
* @note It can be used in timeout function on application side.
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
}
/**
* @brief Configures the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
{
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
{
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
else
{
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
}
/**
* @brief Get the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
*/
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
{
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
/**
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Disable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
{
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
{
return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE
* @{
*/
/**
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Processor uses deep sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
* empty main application.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Do not sleep when returning to Thread mode.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
* processor.
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
{
/* Set SEVEONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
* excluded
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
{
/* Clear SEVEONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER
* @{
*/
/**
* @brief Enable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
* SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
* SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
* SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @arg @ref LL_HANDLER_FAULT_SECURE (*)
*
* (*) value applicable in secure when the system implements the security.
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
{
/* Enable the system handler fault */
SET_BIT(SCB->SHCSR, Fault);
}
/**
* @brief Disable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
* SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
* SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
* SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @arg @ref LL_HANDLER_FAULT_SECURE (*)
*
* (*) value applicable in secure when the system implements the security.
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
{
/* Disable the system handler fault */
CLEAR_BIT(SCB->SHCSR, Fault);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO
* @{
*/
/**
* @brief Get Implementer code
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
* @retval Value should be equal to 0x41 for ARM
*/
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}
/**
* @brief Get Variant number (The r value in the rnpn product revision identifier)
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
* @retval Value between 0 and 255 (0x0: revision 0)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}
/**
* @brief Get Architecture version
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
* @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension")
*/
__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
}
/**
* @brief Get Part number
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
* @retval Value should be equal to 0xD21 for Cortex-M33
*/
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}
/**
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
* @retval Value between 0 and 255 (0x1: patch 1)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU
* @{
*/
/**
* @brief Enable MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param MPU_Control This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU*/
MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
/* Ensure MPU settings take effects */
__DSB();
/* Sequence instruction fetches using update settings */
__ISB();
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Enable non-secure MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param MPU_Control This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
{
/* Enable the MPU*/
MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
/* Ensure MPU settings take effects */
__DSB();
/* Sequence instruction fetches using update settings */
__ISB();
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Disable MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable MPU */
WRITE_REG(MPU->CTRL, 0U);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Disable the non-secure MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable_NS(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable MPU*/
WRITE_REG(MPU_NS->CTRL, 0U);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Check if MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
{
return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Check if non-secure MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
{
return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Enable a MPU region
* @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
}
/**
* @brief Check if MPU region is enabled or not
* @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region)
{
/* Set region index */
WRITE_REG(MPU->RNR, Region);
/* Return MPU region status */
return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Enable a non-secure MPU region
* @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU_NS->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
}
/**
* @brief Check if non-secure MPU region is enabled or not
* @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region_NS
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region)
{
/* Set region index */
WRITE_REG(MPU_NS->RNR, Region);
/* Return non-secure MPU region status */
return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Disable a MPU region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
* MPU_RLAR ENABLE LL_MPU_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Disable a non-secure MPU region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
* MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU_NS->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Configure and enable a MPU region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
* MPU_RLAR ADDR LL_MPU_ConfigRegion\n
* MPU_RBAR XN LL_MPU_ConfigRegion\n
* MPU_RBAR AP LL_MPU_ConfigRegion\n
* MPU_RBAR SH LL_MPU_ConfigRegion\n
* MPU_RLAR EN LL_MPU_ConfigRegion\n
* MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
* or @ref LL_MPU_ACCESS_INNER_SHAREABLE
* @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
* or @ref LL_MPU_REGION_ALL_RO
* @param AttrIndx This parameter can be one of the following values:
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
* @param BaseAddress Value of region base address
* @param LimitAddress Value of region limit address
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
uint32_t LimitAddress)
{
/* Set region index */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
MPU->RBAR |= Attributes;
/* Set region base address and region access attributes */
WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
/* Set region limit address, memory attributes index and enable region */
WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Configure and enable a non-secure MPU region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
* MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
* MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
* MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
* MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
* MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
* MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
* or @ref LL_MPU_ACCESS_INNER_SHAREABLE
* @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
* or @ref LL_MPU_REGION_ALL_RO
* @param AttrIndx This parameter can be one of the following values:
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
* @param BaseAddress Value of region base address
* @param LimitAddress Value of region limit address
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
uint32_t BaseAddress, uint32_t LimitAddress)
{
/* Set Region number */
WRITE_REG(MPU_NS->RNR, Region);
/* Set region base address and region access attributes */
WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
/* Set region limit address, memory attributes index and enable region */
WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Configure a MPU region address range
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
* MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
* MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param BaseAddress Value of region base address
* @param LimitAddress Value of region limit address
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Modify region base address */
MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
/* Modify region limit address */
MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Configure a non-secure MPU region address range
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
* MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
* MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param BaseAddress Value of region base address
* @param LimitAddress Value of region limit address
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
{
/* Set Region number */
WRITE_REG(MPU_NS->RNR, Region);
/* Set base address */
MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
/* Set limit address */
MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Configure a MPU attributes index
* @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n
* MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n
* @param AttIndex This parameter can be one of the following values:
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
* @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
{
/* When selected index is in range [0;3] */
if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
{
/* Modify Attr<i> field of MPU_MAIR0 accordingly */
MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
}
/* When selected index is in range [4;7] */
else
{
/* Modify Attr<i> field of MPU_MAIR1 accordingly */
MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Configure a non-secure MPU attributes index
* @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n
* MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n
* @param AttIndex This parameter can be one of the following values:
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
* @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
* @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
{
/* When selected index is in range [0;3] */
if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
{
/* Modify Attr<i> field of MPU_MAIR0_NS accordingly */
MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
}
/* When selected index is in range [4;7] */
else
{
/* Modify Attr<i> field of MPU_MAIR1_NS accordingly */
MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
}
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Configure a MPU region limit address
* @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
* MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param LimitAddress Value of region limit address
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set limit address */
MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
}
/**
* @brief Get a MPU region limit address
* @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
}
/**
* @brief Configure a MPU region base address
* @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
* MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param BaseAddress Value of region base address
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
}
/**
* @brief Get a MPU region base address
* @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
}
/**
* @brief Configure a MPU region access attributes and enable a region
* @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
* MPU_RBAR XN LL_MPU_SetRegionAccess\n
* MPU_RBAR AP LL_MPU_SetRegionAccess\n
* MPU_RBAR SH LL_MPU_SetRegionAccess\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
* or @ref LL_MPU_ACCESS_INNER_SHAREABLE
* @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
* or @ref LL_MPU_REGION_ALL_RO
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
}
/**
* @brief Get a MPU region access attributes
* @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
* MPU_RBAR XN LL_MPU_GetRegionAccess\n
* MPU_RBAR AP LL_MPU_GetRegionAccess\n
* MPU_RBAR SH LL_MPU_GetRegionAccess\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Configure a non-secure MPU region limit address
* @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
* MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param LimitAddress Value of region limit address
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
{
/* Set Region number */
WRITE_REG(MPU_NS->RNR, Region);
/* Set limit address */
MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
}
/**
* @brief Get a non-secure MPU region limit address
* @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU_NS->RNR, Region);
return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
}
/**
* @brief Configure a non-secure MPU region base address
* @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
* MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param BaseAddress Value of region base address
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
{
/* Set Region number */
WRITE_REG(MPU_NS->RNR, Region);
/* Set base address */
MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
}
/**
* @brief Get a non-secure MPU region base address
* @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU_NS->RNR, Region);
return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
}
/**
* @brief Configure a non-secure MPU region access attributes and enable a region
* @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
* MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
* MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
* MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
* or @ref LL_MPU_ACCESS_INNER_SHAREABLE
* @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
* or @ref LL_MPU_REGION_ALL_RO
* @note cortex-M33 supports 8 secure and 8 non secure regions.
* @retval None
*/
__STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU_NS->RNR, Region);
/* Set base address Attributes */
MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
}
/**
* @brief Get a non-secure MPU region access attributes
* @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
* MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
* MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
* MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU_NS->RNR, Region);
return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_CORTEX_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h
|
C
|
apache-2.0
| 47,394
|
/**
******************************************************************************
* @file stm32u5xx_ll_crc.h
* @author MCD Application Team
* @brief Header file of CRC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_CRC_H
#define STM32U5xx_LL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(CRC)
/** @defgroup CRC_LL CRC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
* @{
*/
#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
/**
* @}
*/
/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
* @{
*/
#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
/**
* @}
*/
/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
* @{
*/
#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
/**
* @}
*/
/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
* @brief Normal representation of this polynomial value is
* X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
* @{
*/
#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
/**
* @}
*/
/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
* @{
*/
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/**
* @brief Read a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
* @{
*/
/**
* @brief Reset the CRC calculation unit.
* @note If Programmable Initial CRC value feature
* is available, also set the Data Register to the value stored in the
* CRC_INIT register, otherwise, reset Data Register to its default value.
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
* @param CRCx CRC Instance
* @retval None
*/
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
{
SET_BIT(CRCx->CR, CRC_CR_RESET);
}
/**
* @brief Configure size of the polynomial.
* @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
* @param CRCx CRC Instance
* @param PolySize This parameter can be one of the following values:
* @arg @ref LL_CRC_POLYLENGTH_32B
* @arg @ref LL_CRC_POLYLENGTH_16B
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
{
MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
}
/**
* @brief Return size of the polynomial.
* @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_POLYLENGTH_32B
* @arg @ref LL_CRC_POLYLENGTH_16B
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
*/
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
}
/**
* @brief Configure the reversal of the bit order of the input data
* @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
* @param CRCx CRC Instance
* @param ReverseMode This parameter can be one of the following values:
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
{
MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
}
/**
* @brief Return type of reversal for input data bit order
* @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
*/
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
}
/**
* @brief Configure the reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
* @param CRCx CRC Instance
* @param ReverseMode This parameter can be one of the following values:
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
{
MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
}
/**
* @brief Return type of reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
*/
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
}
/**
* @brief Initialize the Programmable initial CRC value.
* @note If the CRC size is less than 32 bits, the least significant bits
* are used to write the correct value
* @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
* @rmtoll INIT INIT LL_CRC_SetInitialData
* @param CRCx CRC Instance
* @param InitCrc Value to be programmed in Programmable initial CRC value register
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
{
WRITE_REG(CRCx->INIT, InitCrc);
}
/**
* @brief Return current Initial CRC value.
* @note If the CRC size is less than 32 bits, the least significant bits
* are used to read the correct value
* @rmtoll INIT INIT LL_CRC_GetInitialData
* @param CRCx CRC Instance
* @retval Value programmed in Programmable initial CRC value register
*/
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->INIT));
}
/**
* @brief Initialize the Programmable polynomial value
* (coefficients of the polynomial to be used for CRC calculation).
* @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @rmtoll POL POL LL_CRC_SetPolynomialCoef
* @param CRCx CRC Instance
* @param PolynomCoef Value to be programmed in Programmable Polynomial value register
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
{
WRITE_REG(CRCx->POL, PolynomCoef);
}
/**
* @brief Return current Programmable polynomial value
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @rmtoll POL POL LL_CRC_GetPolynomialCoef
* @param CRCx CRC Instance
* @retval Value programmed in Programmable Polynomial value register
*/
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->POL));
}
/**
* @}
*/
/** @defgroup CRC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write given 32-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData32
* @param CRCx CRC Instance
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
{
WRITE_REG(CRCx->DR, InData);
}
/**
* @brief Write given 16-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData16
* @param CRCx CRC Instance
* @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
{
__IO uint16_t *pReg;
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = InData;
}
/**
* @brief Write given 8-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData8
* @param CRCx CRC Instance
* @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
{
*(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
}
/**
* @brief Return current CRC calculation result. 32 bits value is returned.
* @rmtoll DR DR LL_CRC_ReadData32
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
*/
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->DR));
}
/**
* @brief Return current CRC calculation result. 16 bits value is returned.
* @note This function is expected to be used in a 16 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData16
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
*/
__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
{
return (uint16_t)READ_REG(CRCx->DR);
}
/**
* @brief Return current CRC calculation result. 8 bits value is returned.
* @note This function is expected to be used in a 8 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData8
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
*/
__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
{
return (uint8_t)READ_REG(CRCx->DR);
}
/**
* @brief Return current CRC calculation result. 7 bits value is returned.
* @note This function is expected to be used in a 7 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData7
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
*/
__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
{
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
}
/**
* @brief Return data stored in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one 32-bit long data.
* @rmtoll IDR IDR LL_CRC_Read_IDR
* @param CRCx CRC Instance
* @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
*/
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->IDR));
}
/**
* @brief Store data in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one 32-bit long data.
* @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance
* @param InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
{
*((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData;
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_CRC_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crc.h
|
C
|
apache-2.0
| 15,520
|
/**
******************************************************************************
* @file stm32u5xx_ll_crs.h
* @author MCD Application Team
* @brief Header file of CRS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_CRS_H
#define STM32U5xx_LL_CRS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(CRS)
/** @defgroup CRS_LL CRS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRS_LL_Private_Constants CRS Private Constants
* @{
*/
/* Defines used for the bit position in the register and perform offsets*/
#define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */
#define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */
#define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
* @{
*/
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_CRS_ReadReg function
* @{
*/
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
/**
* @}
*/
/** @defgroup CRS_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
* @{
*/
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
* @{
*/
#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
* @{
*/
#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
* @{
*/
#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
* @{
*/
/**
* @brief Reset value of the RELOAD field
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
*/
#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
/**
* @brief Reset value of Frequency error limit.
*/
#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
/**
* @brief Reset value of the HSI48 Calibration field
* @note The default value is 64, which corresponds to the middle of the trimming interval.
* The trimming step is specified in the product datasheet.
* A higher TRIM value corresponds to a higher output frequency.
*/
#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
* @{
*/
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
* @{
*/
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
* @note The RELOAD value should be selected according to the ratio between
* the target frequency and the frequency of the synchronization source after
* prescaling. It is then decreased by one in order to reach the expected
* synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param __FTARGET__ Target frequency (value in Hz)
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval Reload value (in Hz)
*/
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
* @{
*/
/** @defgroup CRS_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Frequency error counter
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
{
SET_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Disable Frequency error counter
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Check if Frequency error counter is enabled or not
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
{
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Disable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Check if Automatic trimming is enabled or not
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
}
/**
* @brief Set HSI48 oscillator smooth trimming
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
* @param Value a number between Min_Data = 0 and Max_Data = 63
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
}
/**
* @brief Get HSI48 oscillator smooth trimming
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
* @retval a number between Min_Data = 0 and Max_Data = 63
*/
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
{
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
}
/**
* @brief Set counter reload value
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
* @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
}
/**
* @brief Get counter reload value
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
* @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
}
/**
* @brief Set frequency error limit
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
* @param Value a number between Min_Data = 0 and Max_Data = 255
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
}
/**
* @brief Get frequency error limit
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
* @retval A number between Min_Data = 0 and Max_Data = 255
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
}
/**
* @brief Set division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
* @param Divider This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
}
/**
* @brief Get division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
}
/**
* @brief Set SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
}
/**
* @brief Get SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
}
/**
* @brief Set input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
}
/**
* @brief Get input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
}
/**
* @brief Configure CRS for the synchronization
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
* CFGR FELIM LL_CRS_ConfigSynchronization\n
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
* @param Settings This parameter can be a combination of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4
* or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32
* or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
uint32_t ReloadValue, uint32_t Settings)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
MODIFY_REG(CRS->CFGR,
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
* @{
*/
/**
* @brief Generate software SYNC event
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
}
/**
* @brief Get the frequency error direction latched in the time of the last
* SYNC event
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
}
/**
* @brief Get the frequency error counter value latched in the time of the last SYNC event
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if SYNC event OK signal occurred or not
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC warning signal occurred or not
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
}
/**
* @brief Check if Synchronization or trimming error signal occurred or not
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Check if Expected SYNC signal occurred or not
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC error signal occurred or not
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC missed error signal occurred or not
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
}
/**
* @brief Check if Trimming overflow or underflow occurred or not
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
}
/**
* @brief Clear the SYNC event OK flag
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
}
/**
* @brief Clear the SYNC warning flag
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
}
/**
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
* the ERR flag
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
}
/**
* @brief Clear Expected SYNC flag
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Disable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Check if SYNC event OK interrupt is enabled or not
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
}
/**
* @brief Enable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Disable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Check if SYNC warning interrupt is enabled or not
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
{
SET_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Disable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Check if Synchronization or trimming error interrupt is enabled or not
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Disable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Check if Expected SYNC interrupt is enabled or not
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRS_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRS) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_CRS_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h
|
C
|
apache-2.0
| 24,674
|
/**
******************************************************************************
* @file stm32u5xx_ll_dac.h
* @author MCD Application Team
* @brief Header file of DAC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_DAC_H
#define STM32U5xx_LL_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(DAC1)
/** @defgroup DAC_LL DAC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup DAC_LL_Private_Constants DAC Private Constants
* @{
*/
/* Internal masks for DAC channels definition */
/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
/* - channel bits position into register SWTRIG */
/* - channel register offset of data holding register DHRx */
/* - channel register offset of data output register DORx */
/* - channel register offset of sample-and-hold sample time register SHSRx */
#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
CR, MCR, CCR, SHHR, SHRR of channel 1 */
#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
CR, MCR, CCR, SHHR, SHRR of channel 2 */
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
DHR12Rx channel 1 (shifted left of 20 bits) */
#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
DHR12Rx channel 1 (shifted left of 24 bits) */
#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
DHR12Rx channel 1 (shifted left of 28 bits) */
#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
DHR12Rx channel 1 (shifted left of 20 bits) */
#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
DHR12Rx channel 1 (shifted left of 24 bits) */
#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
| DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
DORx channel 2 (shifted left of 5 bits) */
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
SHSRx channel 2 (shifted left of 6 bits) */
#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
to position 0 */
#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
to position 0 */
#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
channel 1 or 2 versus DHR12Rx channel 1
(shifted left of 28 bits) */
#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
channel 1 or 2 versus DHR12Rx channel 1
(shifted left of 20 bits) */
#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
channel 1 or 2 versus DHR12Rx channel 1
(shifted left of 24 bits) */
#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
channel 1 or 2 versus DORx channel 1
(shifted left of 5 bits) */
#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
channel 1 or 2 versus SHSRx channel 1
(shifted left of 6 bits) */
/* DAC registers bits positions */
#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
/* Miscellaneous data */
#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
bits (voltage range determined by analog voltage
references Vref+ and Vref-, refer to reference manual) */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DAC_LL_Private_Macros DAC Private Macros
* @{
*/
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
*/
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of DAC instance.
*/
typedef struct
{
uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
internal (SW start) or from external peripheral
(timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetTriggerSource(). */
uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetWaveAutoGeneration(). */
uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
If waveform automatic generation mode is set to noise, this parameter
can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
If waveform automatic generation mode is set to triangle,
this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
@note If waveform automatic generation mode is disabled,
this parameter is discarded.
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetWaveNoiseLFSR(),
@ref LL_DAC_SetWaveTriangleAmplitude()
depending on the wave automatic generation selected. */
uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetOutputBuffer(). */
uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetOutputConnection(). */
uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetOutputMode(). */
} LL_DAC_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
* @{
*/
/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
* @brief Flags defines which can be used with LL_DAC_ReadReg function
* @{
*/
/* DAC channel 1 flags */
#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
#define LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) /*!< DAC channel 1 flag ready */
#define LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1) /*!< DAC channel 1 flag output register */
/* DAC channel 2 flags */
#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
#define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /*!< DAC channel 2 flag ready */
#define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2) /*!< DAC channel 2 flag output register */
/**
* @}
*/
/** @defgroup DAC_LL_EC_IT DAC interruptions
* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
* @{
*/
#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
/**
* @}
*/
/** @defgroup DAC_LL_EC_CHANNEL DAC channels
* @{
*/
#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
/**
* @}
*/
/** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
* @brief High frequency interface mode defines that can be used
* with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
* @{
*/
#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
#define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
#define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
/**
* @}
*/
/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
* @{
*/
#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
/**
* @}
*/
/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
* @{
*/
#define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */
#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
#define LL_DAC_TRIG_EXT_LPTIM1_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 CH1. */
#define LL_DAC_TRIG_EXT_LPTIM3_CH1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 CH1. */
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
#define LL_DAC_TRIG_EXT_LPTIM1_OUT LL_DAC_TRIG_EXT_LPTIM1_CH1 /*!< Keep old definition for compatibility */
#define LL_DAC_TRIG_EXT_LPTIM3_OUT LL_DAC_TRIG_EXT_LPTIM3_CH1 /*!< Keep old definition for compatibility */
/**
* @}
*/
/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
* @{
*/
#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
/**
* @}
*/
/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
* @{
*/
#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
/**
* @}
*/
/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
* @{
*/
#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
/**
* @}
*/
/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
* @{
*/
#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
/**
* @}
*/
/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
* @{
*/
#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
/**
* @}
*/
/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
* @{
*/
#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
/**
* @}
*/
/** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
* @{
*/
#define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL /*!< The selected DAC channel data format is not signed */
#define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1) /*!< The selected DAC channel data format is signed */
/**
* @}
*/
/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
* @{
*/
#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
/**
* @}
*/
/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
* @{
*/
/* List of DAC registers intended to be used (most commonly) with */
/* DMA transfer. */
/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
/**
* @}
*/
/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
* @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Delay for DAC channel voltage settling time from DAC channel startup */
/* (transition from disable to enable). */
/* Note: DAC channel startup time depends on board application environment: */
/* impedance connected to DAC channel output. */
/* The delay below is specified under conditions: */
/* - voltage maximum transition (lowest to highest value) */
/* - until voltage reaches final value +-1LSB */
/* - DAC channel output buffer enabled */
/* - load impedance of 5kOhm (min), 50pF (max) */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
/* Delay for DAC channel voltage settling time. */
/* Note: DAC channel startup time depends on board application environment: */
/* impedance connected to DAC channel output. */
/* The delay below is specified under conditions: */
/* - voltage maximum transition (lowest to highest value) */
/* - until voltage reaches final value +-1LSB */
/* - DAC channel output buffer enabled */
/* - load impedance of 5kOhm min, 50pF max */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSETTLING"). */
/* Unit: us */
#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
* @{
*/
/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
* @{
*/
/**
* @brief Write a value in DAC register
* @param __INSTANCE__ DAC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in DAC register
* @param __INSTANCE__ DAC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
* @{
*/
/**
* @brief Helper macro to get DAC channel number in decimal format
* from literals LL_DAC_CHANNEL_x.
* Example:
* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
* will return decimal number "1".
* @note The input can be a value from functions where a channel
* number is returned.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval 1...2
*/
#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
((__CHANNEL__) & DAC_SWTR_CHX_MASK)
/**
* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
* from number in decimal format.
* Example:
* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
* will return a data equivalent to "LL_DAC_CHANNEL_1".
* @note If the input parameter does not correspond to a DAC channel,
* this macro returns value '0'.
* @param __DECIMAL_NB__ 1...2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
*/
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
(((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
/**
* @brief Helper macro to define the DAC conversion data full-scale digital
* value corresponding to the selected DAC resolution.
* @note DAC conversion data full-scale corresponds to voltage range
* determined by analog voltage references Vref+ and Vref-
* (refer to reference manual).
* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_DAC_RESOLUTION_12B
* @arg @ref LL_DAC_RESOLUTION_8B
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
/**
* @brief Helper macro to calculate the DAC conversion data (unit: digital
* value) corresponding to a voltage (unit: mVolt).
* @note This helper macro is intended to provide input data in voltage
* rather than digital value,
* to be used with LL DAC functions such as
* @ref LL_DAC_ConvertData12RightAligned().
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
* (unit: mVolt).
* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_DAC_RESOLUTION_12B
* @arg @ref LL_DAC_RESOLUTION_8B
* @retval DAC conversion data (unit: digital value)
*/
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
__DAC_VOLTAGE__,\
__DAC_RESOLUTION__) \
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
/ (__VREFANALOG_VOLTAGE__) \
)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
* @{
*/
/** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
* @{
*/
/**
* @brief Set the high frequency interface mode for the selected DAC instance
* @rmtoll MCR HFSEL LL_DAC_SetHighFrequencyMode
* @param DACx DAC instance
* @param HighFreqMode This parameter can be one of the following values:
* @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
* @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
* @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
{
MODIFY_REG(DACx->MCR, DAC_MCR_HFSEL, HighFreqMode);
}
/**
* @brief Get the high frequency interface mode for the selected DAC instance
* @rmtoll MCR HFSEL LL_DAC_GetHighFrequencyMode
* @param DACx DAC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
* @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
* @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
*/
__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx)
{
return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL));
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
* @{
*/
/**
* @brief Set the operating mode for the selected DAC channel:
* calibration or normal operating mode.
* @rmtoll CR CEN1 LL_DAC_SetMode\n
* CR CEN2 LL_DAC_SetMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param ChannelMode This parameter can be one of the following values:
* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
* @arg @ref LL_DAC_MODE_CALIBRATION
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
{
MODIFY_REG(DACx->CR,
DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the operating mode for the selected DAC channel:
* calibration or normal operating mode.
* @rmtoll CR CEN1 LL_DAC_GetMode\n
* CR CEN2 LL_DAC_GetMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
* @arg @ref LL_DAC_MODE_CALIBRATION
*/
__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the offset trimming value for the selected DAC channel.
* Trimming has an impact when output buffer is enabled
* and is intended to replace factory calibration default values.
* @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
* CCR OTRIM2 LL_DAC_SetTrimmingValue
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
{
MODIFY_REG(DACx->CCR,
DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the offset trimming value for the selected DAC channel.
* Trimming has an impact when output buffer is enabled
* and is intended to replace factory calibration default values.
* @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
* CCR OTRIM2 LL_DAC_GetTrimmingValue
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
*/
__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the conversion trigger source for the selected DAC channel.
* @note For conversion trigger source to be effective, DAC trigger
* must be enabled using function @ref LL_DAC_EnableTrigger().
* @note To set conversion trigger source, DAC channel must be disabled.
* Otherwise, the setting is discarded.
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
* CR TSEL2 LL_DAC_SetTriggerSource
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
{
MODIFY_REG(DACx->CR,
DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the conversion trigger source for the selected DAC channel.
* @note For conversion trigger source to be effective, DAC trigger
* must be enabled using function @ref LL_DAC_EnableTrigger().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
* CR TSEL2 LL_DAC_GetTriggerSource
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_LPTIM1_CH1
* @arg @ref LL_DAC_TRIG_EXT_LPTIM3_CH1
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
*/
__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the waveform automatic generation mode
* for the selected DAC channel.
* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
* CR WAVE2 LL_DAC_SetWaveAutoGeneration
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param WaveAutoGeneration This parameter can be one of the following values:
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
{
MODIFY_REG(DACx->CR,
DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the waveform automatic generation mode
* for the selected DAC channel.
* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
* CR WAVE2 LL_DAC_GetWaveAutoGeneration
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the noise waveform generation for the selected DAC channel:
* Noise mode and parameters LFSR (linear feedback shift register).
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param NoiseLFSRMask This parameter can be one of the following values:
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
{
MODIFY_REG(DACx->CR,
DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the noise waveform generation for the selected DAC channel:
* Noise mode and parameters LFSR (linear feedback shift register).
* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the triangle waveform generation for the selected DAC channel:
* triangle mode and amplitude.
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param TriangleAmplitude This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
uint32_t TriangleAmplitude)
{
MODIFY_REG(DACx->CR,
DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the triangle waveform generation for the selected DAC channel:
* triangle mode and amplitude.
* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the output for the selected DAC channel.
* @note This function set several features:
* - mode normal or sample-and-hold
* - buffer
* - connection to GPIO or internal path.
* These features can also be set individually using
* dedicated functions:
* - @ref LL_DAC_SetOutputBuffer()
* - @ref LL_DAC_SetOutputMode()
* - @ref LL_DAC_SetOutputConnection()
* @note On this STM32 series, output connection depends on output mode
* (normal or sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
* output connection is also connected to GPIO pin
* (both connections to GPIO pin and internal path).
* - if output connection is set to GPIO pin, output buffer
* is disabled, output mode set to sample and hold:
* output connection is also connected to internal path
* (both connections to GPIO pin and internal path).
* @note Mode sample-and-hold requires an external capacitor
* to be connected between DAC channel output and ground.
* Capacitor value depends on load on DAC channel output and
* sample-and-hold timings configured.
* As indication, capacitor typical value is 100nF
* (refer to device datasheet, parameter "CSH").
* @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
* CR MODE2 LL_DAC_ConfigOutput
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param OutputMode This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
* @param OutputBuffer This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
* @param OutputConnection This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
uint32_t OutputBuffer, uint32_t OutputConnection)
{
MODIFY_REG(DACx->MCR,
(DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
(OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Set the output mode normal or sample-and-hold
* for the selected DAC channel.
* @note Mode sample-and-hold requires an external capacitor
* to be connected between DAC channel output and ground.
* Capacitor value depends on load on DAC channel output and
* sample-and-hold timings configured.
* As indication, capacitor typical value is 100nF
* (refer to device datasheet, parameter "CSH").
* @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
* CR MODE2 LL_DAC_SetOutputMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param OutputMode This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
{
MODIFY_REG(DACx->MCR,
(uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
* @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
* CR MODE2 LL_DAC_GetOutputMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
*/
__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the output buffer for the selected DAC channel.
* @note On this STM32 series, when buffer is enabled, its offset can be
* trimmed: factory calibration default values can be
* replaced by user trimming values, using function
* @ref LL_DAC_SetTrimmingValue().
* @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
* CR MODE2 LL_DAC_SetOutputBuffer
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param OutputBuffer This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
{
MODIFY_REG(DACx->MCR,
(uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the output buffer state for the selected DAC channel.
* @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
* CR MODE2 LL_DAC_GetOutputBuffer
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
*/
__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the output connection for the selected DAC channel.
* @note On this STM32 series, output connection depends on output mode (normal or
* sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
* output connection is also connected to GPIO pin
* (both connections to GPIO pin and internal path).
* - if output connection is set to GPIO pin, output buffer
* is disabled, output mode set to sample and hold:
* output connection is also connected to internal path
* (both connections to GPIO pin and internal path).
* @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
* CR MODE2 LL_DAC_SetOutputConnection
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param OutputConnection This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
{
MODIFY_REG(DACx->MCR,
(uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the output connection for the selected DAC channel.
* @note On this STM32 series, output connection depends on output mode (normal or
* sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
* output connection is also connected to GPIO pin
* (both connections to GPIO pin and internal path).
* - if output connection is set to GPIO pin, output buffer
* is disabled, output mode set to sample and hold:
* output connection is also connected to internal path
* (both connections to GPIO pin and internal path).
* @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
* CR MODE2 LL_DAC_GetOutputConnection
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
*/
__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the sample-and-hold timing for the selected DAC channel:
* sample time
* @note Sample time must be set when DAC channel is disabled
* or during DAC operation when DAC channel flag BWSTx is reset,
* otherwise the setting is ignored.
* Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
* @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
* SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
}
/**
* @brief Get the sample-and-hold timing for the selected DAC channel:
* sample time
* @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
* SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
}
/**
* @brief Set the sample-and-hold timing for the selected DAC channel:
* hold time
* @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
* SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
{
MODIFY_REG(DACx->SHHR,
DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the sample-and-hold timing for the selected DAC channel:
* hold time
* @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
* SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the sample-and-hold timing for the selected DAC channel:
* refresh time
* @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
* SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
{
MODIFY_REG(DACx->SHRR,
DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the sample-and-hold timing for the selected DAC channel:
* refresh time
* @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
* SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the signed format for the selected DAC channel.
* @note On this STM32 series, signed format can be used to inject
* Q1.15, Q1.11, Q1.7 signed format data to DAC.
* Ex when using 12bits data format (Q1.11 is used):
* 0x800 will output 0v level
* 0xFFF will output mid-scale level
* 0x000 will output mid-scale level
* 0x7FF will output full-scale level
* @rmtoll MCR SINFORMAT1 LL_DAC_SetSignedFormat\n
* MCR SINFORMAT2 LL_DAC_SetSignedFormat
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param SignedFormat This parameter can be one of the following values:
* @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
* @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
{
MODIFY_REG(DACx->MCR,
DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
SignedFormat << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the signed format state for the selected DAC channel.
* @rmtoll MCR SINFORMAT1 LL_DAC_GetSignedFormat\n
* MCR SINFORMAT2 LL_DAC_GetSignedFormat
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
* @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
*/
__STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Enable DAC DMA transfer request of the selected channel.
* @note To configure DMA source address (peripheral address),
* use function @ref LL_DAC_DMA_GetRegAddr().
* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
* CR DMAEN2 LL_DAC_EnableDMAReq
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC DMA transfer request of the selected channel.
* @note To configure DMA source address (peripheral address),
* use function @ref LL_DAC_DMA_GetRegAddr().
* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
* CR DMAEN2 LL_DAC_DisableDMAReq
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC DMA transfer request state of the selected channel.
* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
* CR DMAEN2 LL_DAC_IsDMAReqEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Enable DAC DMA Double data mode of the selected channel.
* @rmtoll MCR DMADOUBLE1 LL_DAC_EnableDMADoubleDataMode\n
* MCR DMADOUBLE2 LL_DAC_EnableDMADoubleDataMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->MCR,
DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC DMA Double data mode of the selected channel.
* @rmtoll MCR DMADOUBLE1 LL_DAC_DisableDMADoubleDataMode\n
* MCR DMADOUBLE2 LL_DAC_DisableDMADoubleDataMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->MCR,
DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC DMA double data mode state of the selected channel.
* (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)
* @rmtoll MCR DMADOUBLE1 LL_DAC_IsDMADoubleDataModeEnabled\n
* MCR DMADOUBLE2 LL_DAC_IsDMADoubleDataModeEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->MCR,
DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Function to help to configure DMA transfer to DAC: retrieve the
* DAC register address from DAC instance and a list of DAC registers
* intended to be used (most commonly) with DMA transfer.
* @note These DAC registers are data holding registers:
* when DAC conversion is requested, DAC generates a DMA transfer
* request to have data available in DAC data holding registers.
* @note This macro is intended to be used with LL DMA driver, refer to
* function "LL_DMA_ConfigAddresses()".
* Example:
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* (uint32_t)&< array or variable >,
* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
* LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param Register This parameter can be one of the following values:
* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
* @retval DAC register address
*/
__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
{
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
/* DAC channel selected. */
return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
* @{
*/
/**
* @brief Enable DAC selected channel.
* @rmtoll CR EN1 LL_DAC_Enable\n
* CR EN2 LL_DAC_Enable
* @note After enable from off state, DAC channel requires a delay
* for output voltage to reach accuracy +/- 1 LSB.
* Refer to device datasheet, parameter "tWAKEUP".
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC selected channel.
* @rmtoll CR EN1 LL_DAC_Disable\n
* CR EN2 LL_DAC_Disable
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC enable state of the selected channel.
* (0: DAC channel is disabled, 1: DAC channel is enabled)
* @rmtoll CR EN1 LL_DAC_IsEnabled\n
* CR EN2 LL_DAC_IsEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Get DAC ready for conversion state of the selected channel.
* (0: DAC channel is not ready, 1: DAC channel is ready)
* @rmtoll SR DAC1RDY LL_DAC_IsReady\n
* SR DAC2RDY LL_DAC_IsReady
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsReady(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->SR,
DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Enable DAC trigger of the selected channel.
* @note - If DAC trigger is disabled, DAC conversion is performed
* automatically once the data holding register is updated,
* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
* @ref LL_DAC_ConvertData12RightAligned(), ...
* - If DAC trigger is enabled, DAC conversion is performed
* only when a hardware of software trigger event is occurring.
* Select trigger source using
* function @ref LL_DAC_SetTriggerSource().
* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
* CR TEN2 LL_DAC_EnableTrigger
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC trigger of the selected channel.
* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
* CR TEN2 LL_DAC_DisableTrigger
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC trigger state of the selected channel.
* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
* CR TEN2 LL_DAC_IsTriggerEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Trig DAC conversion by software for the selected DAC channel.
* @note Preliminarily, DAC trigger must be set to software trigger
* using function
* @ref LL_DAC_Init()
* @ref LL_DAC_SetTriggerSource()
* with parameter "LL_DAC_TRIGGER_SOFTWARE".
* and DAC trigger must be enabled using
* function @ref LL_DAC_EnableTrigger().
* @note For devices featuring DAC with 2 channels: this function
* can perform a SW start of both DAC channels simultaneously.
* Two channels can be selected as parameter.
* Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
* @param DACx DAC instance
* @param DAC_Channel This parameter can a combination of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval None
*/
__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->SWTRIGR,
(DAC_Channel & DAC_SWTR_CHX_MASK));
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (LSB aligned on bit 0),
* for the selected DAC channel.
* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (MSB aligned on bit 15),
* for the selected DAC channel.
* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 8 bits left alignment (LSB aligned on bit 0),
* for the selected DAC channel.
* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (LSB aligned on bit 0),
* for both DAC channels.
* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
* @param DACx DAC instance
* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
uint32_t DataChannel2)
{
MODIFY_REG(DACx->DHR12RD,
(DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (MSB aligned on bit 15),
* for both DAC channels.
* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
* @param DACx DAC instance
* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
uint32_t DataChannel2)
{
/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
/* the 4 LSB must be taken into account for the shift value. */
MODIFY_REG(DACx->DHR12LD,
(DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 8 bits left alignment (LSB aligned on bit 0),
* for both DAC channels.
* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
* @param DACx DAC instance
* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
uint32_t DataChannel2)
{
MODIFY_REG(DACx->DHR8RD,
(DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
}
/**
* @brief Retrieve output data currently generated for the selected DAC channel.
* @note Whatever alignment and resolution settings
* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
* @ref LL_DAC_ConvertData12RightAligned(), ...),
* output data format is 12 bits right aligned (LSB aligned on bit 0).
* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Get DAC calibration offset flag for DAC channel 1
* @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
}
/**
* @brief Get DAC calibration offset flag for DAC channel 2
* @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
}
/**
* @brief Get DAC busy writing sample time flag for DAC channel 1
* @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
}
/**
* @brief Get DAC busy writing sample time flag for DAC channel 2
* @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
}
/**
* @brief Get DAC ready status flag for DAC channel 1
* @rmtoll SR DAC1RDY LL_DAC_IsActiveFlag_DAC1RDY
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL);
}
/**
* @brief Get DAC ready status flag for DAC channel 2
* @rmtoll SR DAC2RDY LL_DAC_IsActiveFlag_DAC2RDY
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL);
}
/**
* @brief Get DAC output register status flag for DAC channel 1
* @rmtoll SR DORSTAT1 LL_DAC_IsActiveFlag_DORSTAT1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL);
}
/**
* @brief Get DAC output register status flag for DAC channel 2
* @rmtoll SR DORSTAT2 LL_DAC_IsActiveFlag_DORSTAT2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL);
}
/**
* @brief Get DAC underrun flag for DAC channel 1
* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
}
/**
* @brief Get DAC underrun flag for DAC channel 2
* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
}
/**
* @brief Clear DAC underrun flag for DAC channel 1
* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
{
WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
}
/**
* @brief Clear DAC underrun flag for DAC channel 2
* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
{
WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_IT_Management IT management
* @{
*/
/**
* @brief Enable DMA underrun interrupt for DAC channel 1
* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
{
SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
}
/**
* @brief Enable DMA underrun interrupt for DAC channel 2
* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
{
SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
}
/**
* @brief Disable DMA underrun interrupt for DAC channel 1
* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
{
CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
}
/**
* @brief Disable DMA underrun interrupt for DAC channel 2
* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
{
CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
}
/**
* @brief Get DMA underrun interrupt for DAC channel 1
* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
}
/**
* @brief Get DMA underrun interrupt for DAC channel 2
* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
}
/**
* @brief Enable DAC autonomous mode.
* @rmtoll AUTOCR AUTOMODE LL_DAC_EnableAutonomousMode
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableAutonomousMode(DAC_TypeDef *DACx)
{
SET_BIT(DACx->AUTOCR, DAC_AUTOCR_AUTOMODE);
}
/**
* @brief Disable DAC autonomous mode.
* @rmtoll AUTOCR AUTOMODE LL_DAC_DisableAutonomousMode
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableAutonomousMode(DAC_TypeDef *DACx)
{
CLEAR_BIT(DACx->AUTOCR, DAC_AUTOCR_AUTOMODE);
}
/**
* @brief Get DAC autonomous mode state.
* (0: DAC autonomous mode is disabled, 1: DAC autonomous mode is enabled)
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsAutonomousModeEnabled(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->AUTOCR, DAC_AUTOCR_AUTOMODE) == (DAC_AUTOCR_AUTOMODE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_DAC_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dac.h
|
C
|
apache-2.0
| 95,503
|
/**
******************************************************************************
* @file stm32u5xx_ll_dcache.h
* @author MCD Application Team
* @brief Header file of DCACHE LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion ------------------------------------*/
#ifndef STM32U5xx_LL_DCACHE_H
#define STM32U5xx_LL_DCACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (DCACHE1)
/** @defgroup DCACHE_LL DCACHE
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DCACHE_Private_Constants DCACHE Private Constants
* @{
*/
#define LL_DCACHE_COMMAND_NO_OPERATION (0x00000000)
#define LL_DCACHE_COMMAND_CLEAN_BY_ADDR DCACHE_CR_CACHECMD_0
#define LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR DCACHE_CR_CACHECMD_1
#define LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR (DCACHE_CR_CACHECMD_0|DCACHE_CR_CACHECMD_1)
/**
* @}
*/
/** @defgroup DCACHE_Read_Burst_Type Remapped Output burst type
* @{
*/
#define LL_DCACHE_READ_BURST_WRAP 0U /*!< WRAP */
#define LL_DCACHE_READ_BURST_INCR DCACHE_CR_HBURST /*!< INCR */
/**
* @}
*/
/** @defgroup DCACHE_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_DCACHE_ReadReg function
* @{
*/
#define LL_DCACHE_SR_ERRF DCACHE_SR_ERRF /*!< Cache error flag */
#define LL_DCACHE_SR_BUSYF DCACHE_SR_BUSYF /*!< Busy flag */
#define LL_DCACHE_SR_CMDENDF DCACHE_SR_CMDENDF /*!< Command end flag */
#define LL_DCACHE_SR_BSYENDF DCACHE_SR_BSYENDF /*!< Full invalidate busy end flag */
#define LL_DCACHE_SR_BUSYCMDF DCACHE_SR_BUSYCMDF /*!< Command busy flag */
/**
* @}
*/
/** @defgroup DCACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_DCACHE_WriteReg function
* @{
*/
#define LL_DCACHE_FCR_CERRF DCACHE_FCR_CERRF /*!< Cache error flag */
#define LL_DCACHE_FCR_CBSYENDF DCACHE_FCR_CBSYENDF /*!< Full invalidate busy end flag */
#define LL_DCACHE_FCR_CCMDENDF DCACHE_FCR_CCMDENDF /*!< Command end flag*/
/**
* @}
*/
/** @defgroup DCACHE_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_DCACHE_ReadReg and LL_DCACHE_WriteReg functions
* @{
*/
#define LL_DCACHE_IER_BSYENDIE DCACHE_IER_BSYENDIE /*!< Busy end interrupt */
#define LL_DCACHE_IER_ERRIE DCACHE_IER_ERRIE /*!< Cache error interrupt */
#define LL_DCACHE_IER_CMDENDIE DCACHE_IER_CMDENDIE /*!< Command end interrupt */
/**
* @}
*/
/** @defgroup DCACHE_Monitor_Type Monitor type
* @{
*/
#define LL_DCACHE_MONITOR_READ_HIT DCACHE_CR_RHITMEN /*!< Read Hit monitoring */
#define LL_DCACHE_MONITOR_READ_MISS DCACHE_CR_RMISSMEN /*!< Read Miss monitoring */
#define LL_DCACHE_MONITOR_WRITE_HIT DCACHE_CR_WHITMEN /*!< Write Hit monitoring */
#define LL_DCACHE_MONITOR_WRITE_MISS DCACHE_CR_WMISSMEN /*!< Write Miss monitoring */
#define LL_DCACHE_MONITOR_ALL (DCACHE_CR_RHITMEN | DCACHE_CR_RMISSMEN \
| DCACHE_CR_WHITMEN | DCACHE_CR_WMISSMEN)
/**
* @}
*/
/* Exported macros --------------------------------------------------------*/
/** @defgroup DCACHE_LL_Exported_Macros DCACHE Exported Macros
* @{
*/
/** @defgroup DCACHE_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in DCACHE register
* @param __INSTANCE__ DCACHE Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_DCACHE_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in DCACHE register
* @param __INSTANCE__ DCACHE Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_DCACHE_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DCACHE_LL_Exported_Functions DCACHE Exported Functions
* @{
*/
/** @defgroup DCACHE_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable the selected DCACHE instance.
* @rmtoll CR EN LL_DCACHE_Enable
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_Enable(DCACHE_TypeDef *DCACHEx)
{
SET_BIT(DCACHEx->CR, DCACHE_CR_EN);
}
/**
* @brief Disable the selected DCACHE instance.
* @rmtoll CR EN LL_DCACHE_Disable
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_Disable(DCACHE_TypeDef *DCACHEx)
{
CLEAR_BIT(DCACHEx->CR, DCACHE_CR_EN);
}
/**
* @brief Get the selected DCACHE instance enable state.
* @rmtoll CR EN LL_DCACHE_IsEnabled
* @param DCACHEx DCACHE instance
* @retval 0: DCACHE is disabled, 1: DCACHE is enabled.
*/
__STATIC_INLINE uint32_t LL_DCACHE_IsEnabled(DCACHE_TypeDef *DCACHEx)
{
return ((READ_BIT(DCACHEx->CR, DCACHE_CR_EN) == (DCACHE_CR_EN)) ? 1UL : 0UL);
}
/**
* @brief Set the dcache instance start command address.
* @rmtoll CR CMDRSADDRR LL_DCACHE_SetStartAddress
* @param addr dcache command start address(Clean, Invalidate or Clean and Invalidate).
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_SetStartAddress(DCACHE_TypeDef *DCACHEx, uint32_t addr)
{
WRITE_REG(DCACHEx->CMDRSADDRR, addr);
}
/**
* @brief Get the dcache command start address.
* @rmtoll CR CMDRSADDRR LL_DCACHE_GetStartAddress
* @param DCACHEx DCACHE instance
* @retval Start address of dcache command
*/
__STATIC_INLINE uint32_t LL_DCACHE_GetStartAddress(DCACHE_TypeDef *DCACHEx)
{
return (uint32_t)(READ_REG(DCACHEx->CMDRSADDRR));
}
/**
* @brief Set the dcache instance End command address.
* @rmtoll CR CMDREADDRR LL_DCACHE_SetEndAddress
* @param DCACHEx DCACHE instance
* @param addr dcache command end address(Clean, Invalidate or Clean and Invalidate).
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_SetEndAddress(DCACHE_TypeDef *DCACHEx, uint32_t addr)
{
WRITE_REG(DCACHEx->CMDREADDRR, addr);
}
/**
* @brief Get the dcache command End address.
* @rmtoll CR CMDREADDRR LL_DCACHE_GetEndAddress
* @param DCACHEx DCACHE instance
* @retval End address of dcache command
*/
__STATIC_INLINE uint32_t LL_DCACHE_GetEndAddress(DCACHE_TypeDef *DCACHEx)
{
return (uint32_t)(READ_REG(DCACHEx->CMDREADDRR));
}
/**
* @brief Set Dcache command.
* @rmtoll CR CACHECMD LL_DCACHE_SetCommand
* @param DCACHEx DCACHE instance
* @param Command command to be applied for the dcache
* LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR, LL_DCACHE_COMMAND_CLEAN_BY_ADDR,
* LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR,LL_DCACHE_COMMAND_NO_OPERATION
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_SetCommand(DCACHE_TypeDef *DCACHEx, uint32_t Command)
{
/* Set dcache command */
MODIFY_REG(DCACHEx->CR, DCACHE_CR_CACHECMD, Command);
}
/**
* @brief Set Dcache command.
* @rmtoll CR CACHECMD LL_DCACHE_GetCommand
* @param DCACHEx DCACHE instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DCACHE_COMMAND_NO_OPERATION
* @arg @ref LL_DCACHE_COMMAND_CLEAN_BY_ADDR
* @arg @ref LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR
* @arg @ref LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR
*/
__STATIC_INLINE uint32_t LL_DCACHE_GetCommand(DCACHE_TypeDef *DCACHEx)
{
/*Get Dcache Command */
return (uint32_t)(READ_BIT(DCACHEx->CR, DCACHE_CR_CACHECMD));
}
/**
* @brief Launch Dcache Command.
* @rmtoll CR CACHECMD LL_DCACHE_StartCommand
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_StartCommand(DCACHE_TypeDef *DCACHEx)
{
SET_BIT(DCACHEx->CR, DCACHE_CR_STARTCMD);
}
/**
* @brief Set requested read burst type.
* @rmtoll CR HBURST LL_DCACHE_SetReadBurstType
* @param DCACHEx DCACHE instance
* @param ReadBurstType Burst type to be applied for Data Cache
* LL_DCACHE_READ_BURST_WRAP, LL_DCACHE_READ_BURST_INCR.
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_SetReadBurstType(DCACHE_TypeDef *DCACHEx, uint32_t ReadBurstType)
{
MODIFY_REG(DCACHEx->CR, DCACHE_CR_HBURST, ReadBurstType);
}
/**
* @brief Get requested read burst type.
* @rmtoll CR HBURST LL_DCACHE_GetReadBurstType
* @param DCACHEx DCACHE instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DCACHE_READ_BURST_WRAP
* @arg @ref LL_DCACHE_READ_BURST_INCR
*/
__STATIC_INLINE uint32_t LL_DCACHE_GetReadBurstType(DCACHE_TypeDef *DCACHEx)
{
return (uint32_t)(READ_BIT(DCACHEx->CR, DCACHE_CR_HBURST));
}
/**
* @brief Invalidate the Data cache.
* @rmtoll CR CACHEINV LL_DCACHE_Invalidate
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_Invalidate(DCACHE_TypeDef *DCACHEx)
{
SET_BIT(DCACHEx->CR, DCACHE_CR_CACHEINV);
}
/**
* @}
*/
/** @defgroup DCACHE_LL_EF_Monitor Monitor
* @{
*/
/**
* @brief Enable the hit/miss monitor(s).
* @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_EnableMonitors
* @param DCACHEx DCACHE instance
* @param Monitors This parameter can be one or a combination of the following values:
* @arg LL_DCACHE_MONITOR_READ_HIT
* @arg LL_DCACHE_MONITOR_READ_MISS
* @arg LL_DCACHE_MONITOR_WRITE_HIT
* @arg LL_DCACHE_MONITOR_WRITE_MISS
* @arg LL_DCACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_EnableMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
{
SET_BIT(DCACHEx->CR, Monitors);
}
/**
* @brief Disable the hit/miss monitor(s).
* @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_DisableMonitors
* @param DCACHEx DCACHE instance
* @param Monitors This parameter can be one or a combination of the following values:
* @arg LL_DCACHE_MONITOR_READ_HIT
* @arg LL_DCACHE_MONITOR_READ_MISS
* @arg LL_DCACHE_MONITOR_WRITE_HIT
* @arg LL_DCACHE_MONITOR_WRITE_MISS
* @arg LL_DCACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_DisableMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
{
CLEAR_BIT(DCACHEx->CR, Monitors);
}
/**
* @brief Return the hit/miss monitor(s) enable state.
* @rmtoll CR (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN) LL_DCACHE_IsEnabledMonitors
* @param DCACHEx DCACHE instance
* @param Monitors This parameter can be one or a combination of the following values:
* @arg LL_DCACHE_MONITOR_READ_HIT
* @arg LL_DCACHE_MONITOR_READ_MISS
* @arg LL_DCACHE_MONITOR_WRITE_HIT
* @arg LL_DCACHE_MONITOR_WRITE_MISS
* @arg LL_DCACHE_MONITOR_ALL
* @retval State of parameter value (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
{
return (((READ_BIT(DCACHEx->CR, (DCACHE_CR_WMISSMEN | DCACHE_CR_WHITMEN | DCACHE_CR_RMISSMEN | DCACHE_CR_RHITMEN))\
& Monitors) == (Monitors)) ? 1UL : 0UL);
}
/**
* @brief Reset the Data Cache performance monitoring.
* @rmtoll CR (RHITMRST/RMISSMRST/WHITMRST/WMISSMRST) LL_DCACHE_ResetMonitors
* @param DCACHEx DCACHE instance
* @param Monitors Monitoring type
* This parameter can be a combination of the following values:
* @arg LL_DCACHE_MONITOR_READ_HIT
* @arg LL_DCACHE_MONITOR_READ_MISS
* @arg LL_DCACHE_MONITOR_WRITE_HIT
* @arg LL_DCACHE_MONITOR_WRITE_MISS
* @arg LL_DCACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_ResetMonitors(DCACHE_TypeDef *DCACHEx, uint32_t Monitors)
{
/* Reset */
SET_BIT(DCACHEx->CR, (Monitors << 2U));
/* Release reset */
CLEAR_BIT(DCACHEx->CR, (Monitors << 2U));
}
/**
* @brief Get the Read Hit monitor Value
* @rmtoll RHMONR LL_DCACHE_Monitor_GetReadHitValue
* @param DCACHEx DCACHE instance
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadHitValue(DCACHE_TypeDef *DCACHEx)
{
return DCACHEx->RHMONR;
}
/**
* @brief Get the Read Miss monitor Value
* @rmtoll RMMONR LL_DCACHE_Monitor_GetReadMissValue
* @param DCACHEx DCACHE instance
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetReadMissValue(DCACHE_TypeDef *DCACHEx)
{
return DCACHEx->RMMONR;
}
/**
* @brief Get the Write Hit monitor Value
* @rmtoll WHMONR LL_DCACHE_Monitor_GetWriteHitValue
* @param DCACHEx DCACHE instance
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteHitValue(DCACHE_TypeDef *DCACHEx)
{
return DCACHEx->WHMONR;
}
/**
* @brief Get the Write Miss monitor Value
* @rmtoll WMMONR LL_DCACHE_Monitor_GetWriteMissValue
* @param DCACHEx DCACHE instance
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DCACHE_Monitor_GetWriteMissValue(DCACHE_TypeDef *DCACHEx)
{
return DCACHEx->WMMONR;
}
/**
* @}
*/
/** @defgroup DCACHE_LL_EF_IT_Management IT-Management
* @{
*/
/**
* @brief Enable BusyEnd interrupt.
* @rmtoll IER BSYENDIE LL_DCACHE_EnableIT_BSYEND
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_EnableIT_BSYEND(DCACHE_TypeDef *DCACHEx)
{
SET_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE);
}
/**
* @brief Disable BusyEnd interrupt.
* @rmtoll IER BSYENDIE LL_DCACHE_DisableIT_BSYEND
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_DisableIT_BSYEND(DCACHE_TypeDef *DCACHEx)
{
CLEAR_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE);
}
/**
* @brief Indicates whether the Busyend interrupt is enabled.
* @rmtoll IER BSYENDIE LL_DCACHE_IsEnabledIT_BSYEND
* @param DCACHEx DCACHE instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_BSYEND(DCACHE_TypeDef *DCACHEx)
{
return ((READ_BIT(DCACHEx->IER, DCACHE_IER_BSYENDIE) == (DCACHE_IER_BSYENDIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Error interrupt.
* @rmtoll IER ERRIE LL_DCACHE_EnableIT_ERR
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_EnableIT_ERR(DCACHE_TypeDef *DCACHEx)
{
SET_BIT(DCACHEx->IER, DCACHE_IER_ERRIE);
}
/**
* @brief Disable Error interrupt.
* @rmtoll IER ERRIE LL_DCACHE_DisableIT_ERR
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_DisableIT_ERR(DCACHE_TypeDef *DCACHEx)
{
CLEAR_BIT(DCACHEx->IER, DCACHE_IER_ERRIE);
}
/**
* @brief Indicates whether the Error interrupt is enabled.
* @rmtoll IER ERRIE LL_DCACHE_IsEnabledIT_ERR
* @param DCACHEx DCACHE instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_ERR(DCACHE_TypeDef *DCACHEx)
{
return ((READ_BIT(DCACHEx->IER, DCACHE_IER_ERRIE) == (DCACHE_IER_ERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable command end interrupt.
* @rmtoll IER CMDENDIE LL_DCACHE_EnableIT_CMDEND
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_EnableIT_CMDEND(DCACHE_TypeDef *DCACHEx)
{
SET_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE);
}
/**
* @brief Disable command end interrupt.
* @rmtoll IER CMDENDIE LL_DCACHE_DisableIT_CMDEND
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_DisableIT_CMDEND(DCACHE_TypeDef *DCACHEx)
{
CLEAR_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE);
}
/**
* @brief Indicates whether the command end interrupt is enabled.
* @rmtoll IER CMDENDIE LL_DCACHE_IsEnabledIT_CMDEND
* @param DCACHEx DCACHE instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DCACHE_IsEnabledIT_CMDEND(DCACHE_TypeDef *DCACHEx)
{
return ((READ_BIT(DCACHEx->IER, DCACHE_IER_CMDENDIE) == (DCACHE_IER_CMDENDIE)) ? 1UL : 0UL);
}
/**
* @brief Clear full invalidate busy end flag.
* @rmtoll FCR CBSYENDF LL_DCACHE_ClearFlag_BSYEND
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_ClearFlag_BSYEND(DCACHE_TypeDef *DCACHEx)
{
WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CBSYENDF);
}
/**
* @brief Clear cache error flag.
* @rmtoll FCR CERRF LL_DCACHE_ClearFlag_ERR
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_ClearFlag_ERR(DCACHE_TypeDef *DCACHEx)
{
WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CERRF);
}
/**
* @brief Clear command end flag.
* @rmtoll FCR CCMDENDF LL_DCACHE_ClearFlag_CMDEND
* @param DCACHEx DCACHE instance
* @retval None
*/
__STATIC_INLINE void LL_DCACHE_ClearFlag_CMDEND(DCACHE_TypeDef *DCACHEx)
{
WRITE_REG(DCACHEx->FCR, DCACHE_FCR_CCMDENDF);
}
/**
* @brief Get flag Dcache BUSY.
* @rmtoll SR BUSYF LL_DCACHE_IsActiveFlag_BUSY
* @param DCACHEx DCACHE instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSY(DCACHE_TypeDef *DCACHEx)
{
return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BUSYF) == (DCACHE_SR_BUSYF)) ? 1UL : 0UL);
}
/**
* @brief Get flag Dcache Busyend.
* @rmtoll SR BSYENDF LL_DCACHE_IsActiveFlag_BSYEND
* @param DCACHEx DCACHE instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BSYEND(DCACHE_TypeDef *DCACHEx)
{
return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BSYENDF) == (DCACHE_SR_BSYENDF)) ? 1UL : 0UL);
}
/**
* @brief Get flag Dcache Error.
* @rmtoll SR ERRF LL_DCACHE_IsActiveFlag_ERR
* @param DCACHEx DCACHE instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_ERR(DCACHE_TypeDef *DCACHEx)
{
return ((READ_BIT(DCACHEx->SR, DCACHE_SR_ERRF) == (DCACHE_SR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Get flag Dcache Busy command.
* @rmtoll SR BUSYCMDF LL_DCACHE_IsActiveFlag_BUSYCMD
* @param DCACHEx DCACHE instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_BUSYCMD(DCACHE_TypeDef *DCACHEx)
{
return ((READ_BIT(DCACHEx->SR, DCACHE_SR_BUSYCMDF) == (DCACHE_SR_BUSYCMDF)) ? 1UL : 0UL);
}
/**
* @brief Get flag Dcache command end.
* @rmtoll SR CMDENDF LL_DCACHE_IsActiveFlag_CMDEND
* @param DCACHEx DCACHE instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DCACHE_IsActiveFlag_CMDEND(DCACHE_TypeDef *DCACHEx)
{
return ((READ_BIT(DCACHEx->SR, DCACHE_SR_CMDENDF) == (DCACHE_SR_CMDENDF)) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(DCACHE1) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_DCACHE_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dcache.h
|
C
|
apache-2.0
| 20,243
|
/**
******************************************************************************
* @file stm32u5xx_ll_dlyb.h
* @author MCD Application Team
* @brief Header file of DelayBlock module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_DLYB_H
#define STM32U5xx_LL_DLYB_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED)
/* Exported types ------------------------------------------------------------*/
/** @defgroup DLYB_LL DLYB
* @{
*/
/**
* @brief DLYB Configuration Structure definition
*/
typedef struct
{
uint32_t Units; /*!< Specifies the Delay of a unit delay cell.
This parameter can be a value between 0 and DLYB_MAX_UNIT */
uint32_t PhaseSel; /*!< Specifies the Phase for the output clock.
This parameter can be a value between 0 and DLYB_MAX_SELECT */
} LL_DLYB_CfgTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DLYB_Exported_Constants DLYB Exported Constants
* @{
*/
#define DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */
#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */
/**
* @}
*/
/** @defgroup DLYB_LL_Flags DLYB Flags
* @{
*/
#define DLYB_FLAG_LNGF DLYB_CFGR_LNGF
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DLYB_LL_Exported_Functions DLYB Exported Functions
* @{
*/
/** @defgroup DLYB_LL_Configuration Configuration functions
* @{
*/
/**
* @brief DLYB Enable
* @param DLYBx DLYB Instance
* @retval None
*/
__STATIC_INLINE void LL_DLYB_Enable(DLYB_TypeDef *DLYBx)
{
SET_BIT(DLYBx->CR, DLYB_CR_DEN);
}
/** @brief Disable the DLYB.
* @param DLYBx DLYB Instance.
* @retval None
*/
__STATIC_INLINE void LL_DLYB_Disable(DLYB_TypeDef *DLYBx)
{
CLEAR_BIT(DLYBx->CR, DLYB_CR_DEN);
}
/**
* @}
*/
/** @defgroup DLYB_Control_Functions DLYB Control functions
* @{
*/
void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg);
void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg);
uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_DLYB_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h
|
C
|
apache-2.0
| 3,316
|
/**
******************************************************************************
* @file stm32u5xx_ll_dma.h
* @author MCD Application Team
* @brief Header file of DMA LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### LL DMA driver acronyms #####
==============================================================================
[..] Acronyms table :
=========================================
|| Acronym || ||
=========================================
|| SRC || Source ||
|| DEST || Destination ||
|| ADDR || Address ||
|| ADDRS || Addresses ||
|| INC || Increment / Incremented ||
|| DEC || Decrement / Decremented ||
|| BLK || Block ||
|| RPT || Repeat / Repeated ||
|| TRIG || Trigger ||
=========================================
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_DMA_H
#define STM32U5xx_LL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if (defined (GPDMA1) || defined (LPDMA1))
/** @defgroup DMA_LL DMA
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup DMA_LL_Private_Variables DMA Private Variables
* @{
*/
#define DMA_CHANNEL0_OFFSET (0x00000050UL)
#define DMA_CHANNEL1_OFFSET (0x000000D0UL)
#define DMA_CHANNEL2_OFFSET (0x00000150UL)
#define DMA_CHANNEL3_OFFSET (0x000001D0UL)
#define DMA_CHANNEL4_OFFSET (0x00000250UL)
#define DMA_CHANNEL5_OFFSET (0x000002D0UL)
#define DMA_CHANNEL6_OFFSET (0x00000350UL)
#define DMA_CHANNEL7_OFFSET (0x000003D0UL)
#define DMA_CHANNEL8_OFFSET (0x00000450UL)
#define DMA_CHANNEL9_OFFSET (0x000004D0UL)
#define DMA_CHANNEL10_OFFSET (0x00000550UL)
#define DMA_CHANNEL11_OFFSET (0x000005D0UL)
#define DMA_CHANNEL12_OFFSET (0x00000650UL)
#define DMA_CHANNEL13_OFFSET (0x000006D0UL)
#define DMA_CHANNEL14_OFFSET (0x00000750UL)
#define DMA_CHANNEL15_OFFSET (0x000007D0UL)
/* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */
static const uint32_t LL_DMA_CH_OFFSET_TAB[] =
{
DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET,
DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET,
DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET,
DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET,
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined (USE_FULL_LL_DRIVER)
/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
* @{
*/
/**
* @brief LL DMA init structure definition.
*/
typedef struct
{
uint32_t SrcAddress; /*!< This field specify the data transfer source address.
Programming this field is mandatory for all available DMA channels.
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetSrcAddress(). */
uint32_t DestAddress; /*!< This field specify the data transfer destination address.
Programming this field is mandatory for all available DMA channels.
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDestAddress(). */
uint32_t Direction; /*!< This field specify the data transfer direction.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDataTransferDirection(). */
uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetBlkHWRequest(). */
uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDataAlignment(). */
uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
Programming this field is not mandatory for LPDMA channels.
This parameter must be a value between Min_Data = 1 and Max_Data = 64.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetSrcBurstLength(). */
uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
Programming this field is not mandatory for LPDMA channels.
This parameter must be a value between Min_Data = 1 and Max_Data = 64.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDestBurstLength(). */
uint32_t SrcDataWidth; /*!< This field specify the source data width.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetSrcDataWidth(). */
uint32_t DestDataWidth; /*!< This field specify the destination data width.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDestDataWidth(). */
uint32_t SrcIncMode; /*!< This field specify the source burst increment mode.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetSrcIncMode(). */
uint32_t DestIncMode; /*!< This field specify the destination burst increment mode.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDestIncMode(). */
uint32_t Priority; /*!< This field specify the channel priority level.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetChannelPriorityLevel(). */
uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
Programming this field is mandatory for all available DMA channels.
This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetBlkDataLength(). */
uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
Programming this field is mandatory only for 2D addressing channels.
This parameter can be a value between 1 and 2048 Min_Data = 0
and Max_Data = 0x000007FF.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetBlkRptCount(). */
uint32_t TriggerMode; /*!< This field specify the trigger mode.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetTriggerMode(). */
uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetTriggerPolarity(). */
uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetHWTrigger(). */
uint32_t Request; /*!< This field specify the peripheral request selection.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetPeriphRequest(). */
uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetTransferEventMode(). */
uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
Programming this field is not mandatory for LPDMA channels.
This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDestHWordExchange(). */
uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
Programming this field is not mandatory for LPDMA channels.
This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDestByteExchange(). */
uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
Programming this field is not mandatory for LPDMA channels.
This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetSrcByteExchange(). */
uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
Programming this field is not mandatory for LPDMA channels.
This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetSrcAllocatedPort(). */
uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
Programming this field is not mandatory for LPDMA channels.
This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDestAllocatedPort(). */
uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
Programming this field is not mandatory for LPDMA channels.
This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetLinkAllocatedPort(). */
uint32_t LinkStepMode; /*!< This field specify the link step mode.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetLinkStepMode(). */
uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode.
Programming this field is mandatory only for 2D addressing channels.
This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetSrcAddrUpdate(). */
uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode.
Programming this field is mandatory only for 2D addressing channels.
This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDestAddrUpdate(). */
uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
Programming this field is mandatory only for 2D addressing channels.
This parameter can be a value Between 0 to 0x00001FFF.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetSrcAddrUpdateValue(). */
uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
Programming this field is mandatory only for 2D addressing channels.
This parameter can be a value Between 0 to 0x00001FFF.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetDestAddrUpdateValue(). */
uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
Programming this field is mandatory only for 2D addressing channels.
This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetBlkRptSrcAddrUpdate(). */
uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
Programming this field is mandatory only for 2D addressing channels.
This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetBlkRptDestAddrUpdate(). */
uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
Programming this field is mandatory only for 2D addressing channels.
This parameter can be a value Between 0 to 0x0000FFFF.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */
uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
Programming this field is mandatory only for 2D addressing channels.
This parameter can be a value Between 0 to 0x0000FFFF.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */
uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first
bytes are always forced to 0).
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetLinkedListBaseAddr(). */
uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value Between 0 to 0x0000FFFC.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetLinkedListAddrOffset(). */
} LL_DMA_InitTypeDef;
/**
* @brief LL DMA init linked list structure definition.
*/
typedef struct
{
uint32_t Priority; /*!< This field specify the channel priority level.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetChannelPriorityLevel(). */
uint32_t LinkStepMode; /*!< This field specify the link step mode.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetLinkStepMode(). */
uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port.
Programming this field is not mandatory for LPDMA channels.
This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetLinkAllocatedPort(). */
uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
Programming this field is mandatory for all available DMA channels.
This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE.
This feature can be modified afterwards using unitary function
@ref LL_DMA_SetTransferEventMode(). */
} LL_DMA_InitLinkedListTypeDef;
/**
* @brief LL DMA node init structure definition.
*/
typedef struct
{
/* CTR1 register fields ******************************************************
If any CTR1 fields need to be updated comparing to previous node, it is
mandatory to update the new value in CTR1 register fields and enable update
CTR1 register in UpdateRegisters fields if it is not enabled in the
previous node.
If the node to be created is for LPDMA channels, there is no need to fill
the following fields for CTR1 register :
- DestAllocatedPort.
- DestHWordExchange.
- DestByteExchange.
- DestBurstLength.
- SrcAllocatedPort.
- SrcByteExchange.
- SrcBurstLength.
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
uint32_t DestSecure; /*!< This field specify the destination secure.
This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port.
This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */
uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange.
This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */
uint32_t DestByteExchange; /*!< This field specify the destination byte exchange.
This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */
uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes.
This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
uint32_t DestIncMode; /*!< This field specify the destination increment mode.
This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */
uint32_t DestDataWidth; /*!< This field specify the destination data width.
This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
uint32_t SrcSecure; /*!< This field specify the source secure.
This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port.
This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */
uint32_t SrcByteExchange; /*!< This field specify the source byte exchange.
This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */
uint32_t DataAlignment; /*!< This field specify the transfer data alignment.
This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */
uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes.
This parameter must be a value between Min_Data = 1 and Max_Data = 64. */
uint32_t SrcIncMode; /*!< This field specify the source increment mode.
This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */
uint32_t SrcDataWidth; /*!< This field specify the source data width.
This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */
/* CTR2 register fields ******************************************************
If any CTR2 fields need to be updated comparing to previous node, it is
mandatory to update the new value in CTR2 register fields and enable update
CTR2 register in UpdateRegisters fields if it is not enabled in the
previous node.
For all node created, filling all fields is mandatory.
*/
uint32_t TransferEventMode; /*!< This field specify the transfer event mode.
This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */
uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity.
This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */
uint32_t TriggerSelection; /*!< This field specify the trigger event selection.
This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */
uint32_t TriggerMode; /*!< This field specify the trigger mode.
This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */
uint32_t BlkHWRequest; /*!< This field specify the hardware request unity.
This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */
uint32_t Direction; /*!< This field specify the transfer direction.
This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */
uint32_t Request; /*!< This field specify the peripheral request selection.
This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */
/* CBR1 register fields ******************************************************
If any CBR1 fields need to be updated comparing to previous node, it is
mandatory to update the new value in CBR1 register fields and enable update
CBR1 register in UpdateRegisters fields if it is not enabled in the
previous node.
If the node to be created is not for 2D addressing channels, there is no
need to fill the following fields for CBR1 register :
- BlkReptDestAddrUpdate.
- BlkRptSrcAddrUpdate.
- DestAddrUpdate.
- SrcAddrUpdate.
- BlkRptCount.
*/
uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode.
This parameter can be a value of
@ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */
uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode.
This parameter can be a value of
@ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */
uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode.
This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */
uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode.
This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */
uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block.
This parameter can be a value between 1 and 2048 Min_Data = 0
and Max_Data = 0x000007FF. */
uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes.
This parameter must be a value between Min_Data = 0
and Max_Data = 0x0000FFFF. */
/* CSAR register fields ******************************************************
If any CSAR fields need to be updated comparing to previous node, it is
mandatory to update the new value in CSAR register fields and enable update
CSAR register in UpdateRegisters fields if it is not enabled in the
previous node.
For all node created, filling all fields is mandatory.
*/
uint32_t SrcAddress; /*!< This field specify the transfer source address.
This parameter must be a value between Min_Data = 0
and Max_Data = 0xFFFFFFFF. */
/* CDAR register fields ******************************************************
If any CDAR fields need to be updated comparing to previous node, it is
mandatory to update the new value in CDAR register fields and enable update
CDAR register in UpdateRegisters fields if it is not enabled in the
previous node.
For all node created, filling all fields is mandatory.
*/
uint32_t DestAddress; /*!< This field specify the transfer destination address.
This parameter must be a value between Min_Data = 0
and Max_Data = 0xFFFFFFFF. */
/* CTR3 register fields ******************************************************
If any CTR3 fields need to be updated comparing to previous node, it is
mandatory to update the new value in CTR3 register fields and enable update
CTR3 register in UpdateRegisters fields if it is not enabled in the
previous node.
This register is used only for 2D addressing channels.
If used channel is linear addressing, this register will be overwritten by
CLLR register in memory.
When this register is enabled on UpdateRegisters and the selected channel
is linear addressing, LL APIs will discard this register update in memory.
*/
uint32_t DestAddrOffset; /*!< This field specifies the destination address offset.
This parameter can be a value Between 0 to 0x00001FFF. */
uint32_t SrcAddrOffset; /*!< This field specifies the source address offset.
This parameter can be a value Between 0 to 0x00001FFF. */
/* CBR2 register fields ******************************************************
If any CBR2 fields need to be updated comparing to previous node, it is
mandatory to update the new value in CBR2 register fields and enable update
CBR2 register in UpdateRegisters fields if it is not enabled in the
previous node.
This register is used only for 2D addressing channels.
If used channel is linear addressing, this register will be discarded in
memory. When this register is enabled on UpdateRegisters and the selected
channel is linear addressing, LL APIs will discard this register update in
memory.
*/
uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset.
This parameter can be a value Between 0 to 0x0000FFFF. */
uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset.
This parameter can be a value Between 0 to 0x0000FFFF. */
/* CLLR register fields ******************************************************
If any CLLR fields need to be updated comparing to previous node, it is
mandatory to update the new value in CLLR register fields and enable update
CLLR register in UpdateRegisters fields if it is not enabled in the
previous node.
If used channel is linear addressing, there is no need to enable/disable
CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded
by LL APIs.
*/
uint32_t UpdateRegisters; /*!< Specifies the linked list register update.
This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */
/* DMA Node type field *******************************************************
This parameter defines node types as node size and node content varies
between channels.
Thanks to this fields, linked list queue could be created independently
from channel selection. So, one queue could be executed by all DMA channels.
*/
uint32_t NodeType; /*!< Specifies the node type to be created.
This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */
} LL_DMA_InitNodeTypeDef;
/**
* @brief LL DMA linked list node structure definition.
* @note For 2D addressing channels, the maximum node size is :
* (4 Bytes * 8 registers = 32 Bytes).
* For GPDMA linear addressing channels, the maximum node size is :
* (4 Bytes * 6 registers = 24 Bytes).
* For LPDMA linear addressing channels, the maximum node size is :
* (4 Bytes * 6 registers = 24 Bytes).
*/
typedef struct
{
__IO uint32_t LinkRegisters[8];
} LL_DMA_LinkNodeTypeDef;
/**
* @}
*/
#endif /* defined (USE_FULL_LL_DRIVER) */
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
* @{
*/
/** @defgroup DMA_LL_EC_CHANNEL Channel
* @{
*/
#define LL_DMA_CHANNEL_0 (0x00U)
#define LL_DMA_CHANNEL_1 (0x01U)
#define LL_DMA_CHANNEL_2 (0x02U)
#define LL_DMA_CHANNEL_3 (0x03U)
#define LL_DMA_CHANNEL_4 (0x04U)
#define LL_DMA_CHANNEL_5 (0x05U)
#define LL_DMA_CHANNEL_6 (0x06U)
#define LL_DMA_CHANNEL_7 (0x07U)
#define LL_DMA_CHANNEL_8 (0x08U)
#define LL_DMA_CHANNEL_9 (0x09U)
#define LL_DMA_CHANNEL_10 (0x0AU)
#define LL_DMA_CHANNEL_11 (0x0BU)
#define LL_DMA_CHANNEL_12 (0x0CU)
#define LL_DMA_CHANNEL_13 (0x0DU)
#define LL_DMA_CHANNEL_14 (0x0EU)
#define LL_DMA_CHANNEL_15 (0x0FU)
#if defined (USE_FULL_LL_DRIVER)
#define LL_DMA_CHANNEL_ALL (0x10U)
#endif /* defined (USE_FULL_LL_DRIVER) */
/**
* @}
*/
#if defined (USE_FULL_LL_DRIVER)
/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset
* @{
*/
#define LL_DMA_CLLR_OFFSET0 (0x00U)
#define LL_DMA_CLLR_OFFSET1 (0x01U)
#define LL_DMA_CLLR_OFFSET2 (0x02U)
#define LL_DMA_CLLR_OFFSET3 (0x03U)
#define LL_DMA_CLLR_OFFSET4 (0x04U)
#define LL_DMA_CLLR_OFFSET5 (0x05U)
#define LL_DMA_CLLR_OFFSET6 (0x06U)
#define LL_DMA_CLLR_OFFSET7 (0x07U)
/**
* @}
*/
#endif /* defined (USE_FULL_LL_DRIVER) */
/** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level
* @{
*/
#define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */
#define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */
#define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */
#define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */
/**
* @}
*/
/** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port
* @{
*/
#define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */
#define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */
/**
* @}
*/
/** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode
* @{
*/
#define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */
#define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */
/**
* @}
*/
/** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange
* @{
*/
#define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destinatiion Half-Word exchange when destination data width
is word */
#define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destinatiion Half-Word exchange when destination data width
is word */
/**
* @}
*/
/** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange
* @{
*/
#define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */
#define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */
/**
* @}
*/
/** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange
* @{
*/
#define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */
#define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */
/**
* @}
*/
/** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port
* @{
*/
#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */
#define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */
/**
* @}
*/
/** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port
* @{
*/
#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */
#define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */
/**
* @}
*/
/** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode
* @{
*/
#define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */
#define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */
/**
* @}
*/
/** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width
* @{
*/
#define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */
#define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */
#define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */
/**
* @}
*/
/** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment
* @{
*/
#define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width :
=> Right Aligned padded with 0 up to destination
data width.
If src data width > dest data width :
=> Right Aligned Left Truncated down to destination
data width. */
#define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width :
=> Right Aligned padded with sign extended up to destination
data width.
If src data width > dest data width :
=> Left Aligned Right Truncated down to the destination
data width */
#define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width :
=> Packed at the destination data width (Not Available
for LPDMA)
If src data width > dest data width :
=> Unpacked at the destination data width (Not Available
for LPDMA) */
/**
* @}
*/
/** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode
* @{
*/
#define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */
#define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */
/**
* @}
*/
/** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width
* @{
*/
#define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */
#define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */
#define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */
/**
* @}
*/
/** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request
* @{
*/
#define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware
request/acknowledge protocol at a burst level */
#define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware
request/acknowledge protocol at a block level */
/**
* @}
*/
/** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode
* @{
*/
#define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the
(respectively half) end of each block */
#define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the
(respectively half) end of the repeated block */
#define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the
(respectively half) end of each linked-list item */
#define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the
(respectively half) end of the last linked-list item */
/**
* @}
*/
/** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity
* @{
*/
#define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request.
Masked trigger event */
#define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising
edge of the selected trigger event input */
#define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling
edge of the selected trigger event input */
/**
* @}
*/
/** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode
* @{
*/
#define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least)
one hit trigger */
#define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least)
one hit trigger */
#define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least)
one hit trigger */
#define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least)
one hit trigger */
/**
* @}
*/
/** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction
* @{
*/
#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */
#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */
/**
* @}
*/
/** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode
* @{
*/
#define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block
transfer by source update value */
#define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block
transfer by source update value */
/**
* @}
*/
/** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode
* @{
*/
#define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block
transfer by destination update value */
#define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block
transfer by destination update value */
/**
* @}
*/
/** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode
* @{
*/
#define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst
transfer by source update value */
#define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst
transfer by source update value */
/**
* @}
*/
/** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode
* @{
*/
#define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each
burst transfer by destination update value */
#define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each
burst transfer by destination update value */
/**
* @}
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
* @{
*/
#define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */
#define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */
/**
* @}
*/
/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute
* @{
*/
#define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */
#define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */
/**
* @}
*/
/** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute
* @{
*/
#define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */
#define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */
/**
* @}
*/
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type
* @{
*/
#define LL_DMA_LPDMA_LINEAR_NODE 0x00U /*!< LPDMA node : linear addressing node */
#define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */
#define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */
/**
* @}
*/
/** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update
* @{
*/
#define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory :
available for all DMA channels */
#define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory :
available for all DMA channels */
#define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory :
available for all DMA channels */
#define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory :
available for all DMA channels */
#define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory :
available for all DMA channels */
#define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory :
available only for 2D addressing DMA channels */
#define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory :
available only for 2D addressing DMA channels */
#define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory :
available for all DMA channels */
/**
* @}
*/
/** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection
* @{
*/
/* GPDMA1 Hardware Requests */
#define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW Request is ADC1 */
#define LL_GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW Request is ADC4 */
#define LL_GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW Request is DAC1_CH1 */
#define LL_GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW Request is DAC1_CH2 */
#define LL_GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW Request is TIM6_UP */
#define LL_GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW Request is TIM7_UP */
#define LL_GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW Request is SPI1_RX */
#define LL_GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW Request is SPI1_TX */
#define LL_GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW Request is SPI2_RX */
#define LL_GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW Request is SPI2_TX */
#define LL_GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW Request is SPI3_RX */
#define LL_GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW Request is SPI3_TX */
#define LL_GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW Request is I2C1_RX */
#define LL_GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW Request is I2C1_TX */
#define LL_GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW Request is I2C1_EVC */
#define LL_GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW Request is I2C2_RX */
#define LL_GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW Request is I2C2_TX */
#define LL_GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW Request is I2C2_EVC */
#define LL_GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW Request is I2C3_RX */
#define LL_GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW Request is I2C3_TX */
#define LL_GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW Request is I2C3_EVC */
#define LL_GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW Request is I2C4_RX */
#define LL_GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW Request is I2C4_TX */
#define LL_GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW Request is I2C4_EVC */
#define LL_GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW Request is USART1_RX */
#define LL_GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW Request is USART1_TX */
#define LL_GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW Request is USART2_RX */
#define LL_GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW Request is USART2_TX */
#define LL_GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW Request is USART3_RX */
#define LL_GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW Request is USART3_TX */
#define LL_GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW Request is UART4_RX */
#define LL_GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW Request is UART4_TX */
#define LL_GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW Request is UART5_RX */
#define LL_GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW Request is UART5_TX */
#define LL_GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW Request is LPUART1_RX */
#define LL_GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW Request is LPUART1_TX */
#define LL_GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW Request is SAI1_A */
#define LL_GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW Request is SAI1_B */
#define LL_GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW Request is SAI2_A */
#define LL_GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW Request is SAI2_B */
#define LL_GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW Request is OCTOSPI1 */
#define LL_GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW Request is OCTOSPI2 */
#define LL_GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW Request is TIM1_CH1 */
#define LL_GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW Request is TIM1_CH2 */
#define LL_GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW Request is TIM1_CH3 */
#define LL_GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW Request is TIM1_CH4 */
#define LL_GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW Request is TIM1_UP */
#define LL_GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW Request is TIM1_TRIG */
#define LL_GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW Request is TIM1_COM */
#define LL_GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW Request is TIM8_CH1 */
#define LL_GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW Request is TIM8_CH2 */
#define LL_GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW Request is TIM8_CH3 */
#define LL_GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW Request is TIM8_CH4 */
#define LL_GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW Request is TIM8_UP */
#define LL_GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW Request is TIM8_TRIG */
#define LL_GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW Request is TIM8_COM */
#define LL_GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW Request is TIM2_CH1 */
#define LL_GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW Request is TIM2_CH2 */
#define LL_GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW Request is TIM2_CH3 */
#define LL_GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW Request is TIM2_CH4 */
#define LL_GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW Request is TIM2_UP */
#define LL_GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW Request is TIM3_CH1 */
#define LL_GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW Request is TIM3_CH2 */
#define LL_GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW Request is TIM3_CH3 */
#define LL_GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW Request is TIM3_CH4 */
#define LL_GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW Request is TIM3_UP */
#define LL_GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW Request is TIM3_TRIG */
#define LL_GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW Request is TIM4_CH1 */
#define LL_GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW Request is TIM4_CH2 */
#define LL_GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW Request is TIM4_CH3 */
#define LL_GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW Request is TIM4_CH4 */
#define LL_GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW Request is TIM4_UP */
#define LL_GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW Request is TIM5_CH1 */
#define LL_GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW Request is TIM5_CH2 */
#define LL_GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW Request is TIM5_CH3 */
#define LL_GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW Request is TIM5_CH4 */
#define LL_GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW Request is TIM5_UP */
#define LL_GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW Request is TIM5_TRIG */
#define LL_GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW Request is TIM15_CH1 */
#define LL_GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW Request is TIM15_UP */
#define LL_GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW Request is TIM15_TRIG */
#define LL_GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW Request is TIM15_COM */
#define LL_GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW Request is TIM16_CH1 */
#define LL_GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW Request is TIM16_UP */
#define LL_GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW Request is TIM17_CH1 */
#define LL_GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW Request is TIM17_UP */
#define LL_GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW Request is DCMI_PSSI */
#define LL_GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW Request is AES_IN */
#define LL_GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW Request is AES_OUT */
#define LL_GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW Request is HASH_IN */
#define LL_GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW Request is UCPD1_TX */
#define LL_GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW Request is UCPD1_RX */
#define LL_GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW Request is MDF1_FLT0 */
#define LL_GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW Request is MDF1_FLT1 */
#define LL_GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW Request is MDF1_FLT2 */
#define LL_GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW Request is MDF1_FLT3 */
#define LL_GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW Request is MDF1_FLT4 */
#define LL_GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW Request is MDF1_FLT5 */
#define LL_GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW Request is ADF1_FLT0 */
#define LL_GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW Request is FMAC_READ */
#define LL_GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW Request is FMAC_WRITE */
#define LL_GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW Request is CORDIC_READ */
#define LL_GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW Request is CORDIC_WRITE */
#define LL_GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW Request is SAES_IN */
#define LL_GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW Request is SAES_OUT */
#define LL_GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW Request is LPTIM1_IC1 */
#define LL_GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW Request is LPTIM1_IC2 */
#define LL_GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW Request is LPTIM1_UE */
#define LL_GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW Request is LPTIM2_IC1 */
#define LL_GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW Request is LPTIM2_IC2 */
#define LL_GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW Request is LPTIM2_UE */
#define LL_GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW Request is LPTIM3_IC1 */
#define LL_GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW Request is LPTIM3_IC2 */
#define LL_GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW Request is LPTIM3_UE */
#if defined (HSPI1_BASE)
#define LL_GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */
#endif /* defined (HSPI1_BASE) */
#if defined (I2C5)
#define LL_GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */
#define LL_GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */
#define LL_GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */
#endif /* defined (I2C5) */
#if defined (I2C6)
#define LL_GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */
#define LL_GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */
#define LL_GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */
#endif /* defined (I2C6) */
#if defined (USART6)
#define LL_GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */
#define LL_GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */
#endif /* defined (USART6) */
#if defined (ADC2)
#define LL_GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */
#endif /* defined (ADC2) */
/* GPDMA1 Hardware Requests aliases */
#define LL_GPDMA1_REQUEST_DCMI LL_GPDMA1_REQUEST_DCMI_PSSI
/* LPDMA1 Hardware Requests */
#define LL_LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW Request is LPUART1_RX */
#define LL_LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW Request is LPUART1_TX */
#define LL_LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW Request is SPI3_RX */
#define LL_LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW Request is SPI3_TX */
#define LL_LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW Request is I2C3_RX */
#define LL_LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW Request is I2C3_TX */
#define LL_LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW Request is I2C3_EVC */
#define LL_LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW Request is ADC4 */
#define LL_LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW Request is DAC1_CH1 */
#define LL_LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW Request is DAC1_CH2 */
#define LL_LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW Request is ADF1_FLT0 */
#define LL_LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW Request is LPTIM1_IC1 */
#define LL_LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW Request is LPTIM1_IC2 */
#define LL_LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW Request is LPTIM1_UE */
#define LL_LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW Request is LPTIM3_IC1 */
#define LL_LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW Request is LPTIM3_IC2 */
#define LL_LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW Request is LPTIM3_UE */
/**
* @}
*/
/** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection
* @{
*/
/* GPDMA1 Hardware Triggers */
#define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger is EXTI_LINE0 */
#define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger is EXTI_LINE1 */
#define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger is EXTI_LINE2 */
#define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger is EXTI_LINE3 */
#define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger is EXTI_LINE4 */
#define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger is EXTI_LINE5 */
#define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger is EXTI_LINE6 */
#define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger is EXTI_LINE7 */
#define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger is TAMP_TRG1 */
#define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger is TAMP_TRG2 */
#define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger is TAMP_TRG3 */
#define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger is LPTIM1_CH1 */
#define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger is LPTIM1_CH2 */
#define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger is LPTIM2_CH1 */
#define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger is LPTIM2_CH2 */
#define LL_GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger is LPTIM4_OUT */
#define LL_GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger is COMP1_OUT */
#define LL_GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger is COMP2_OUT */
#define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger is RTC_ALRA_TRG */
#define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger is RTC_ALRB_TRG */
#define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger is RTC_WUT_TRG */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger is GPDMA1_CH0_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger is GPDMA1_CH1_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger is GPDMA1_CH2_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger is GPDMA1_CH3_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger is GPDMA1_CH4_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger is GPDMA1_CH5_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger is GPDMA1_CH6_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger is GPDMA1_CH7_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger is GPDMA1_CH8_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger is GPDMA1_CH9_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger is GPDMA1_CH10_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger is GPDMA1_CH11_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger is GPDMA1_CH12_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger is GPDMA1_CH13_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger is GPDMA1_CH14_TCF */
#define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger is GPDMA1_CH15_TCF */
#define LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger is LPDMA1_CH0_TCF */
#define LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger is LPDMA1_CH1_TCF */
#define LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger is LPDMA1_CH2_TCF */
#define LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger is LPDMA1_CH3_TCF */
#define LL_GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger is TIM2_TRGO */
#define LL_GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger is TIM15_TRGO */
#define LL_GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger is ADC4_AWD1 */
#define LL_GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger is ADC1_AWD1 */
#if defined (TIM3_TRGO_TRIGGER_SUPPORT)
#define LL_GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */
#endif /* defined (TIM3_TRGO_TRIGGER_SUPPORT) */
#if defined (TIM4_TRGO_TRIGGER_SUPPORT)
#define LL_GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */
#endif /* defined (TIM4_TRGO_TRIGGER_SUPPORT) */
#if defined (TIM5_TRGO_TRIGGER_SUPPORT)
#define LL_GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */
#endif /* defined (TIM5_TRGO_TRIGGER_SUPPORT) */
#if defined (LTDC)
#define LL_GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */
#endif /* defined (LTDC) */
#if defined (DSI)
#define LL_GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */
#define LL_GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */
#endif /* defined (DSI) */
#if defined (DMA2D)
#define LL_GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */
#define LL_GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */
#define LL_GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */
#endif /* defined (DMA2D) */
#if defined (GPU2D)
#define LL_GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */
#define LL_GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */
#define LL_GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */
#define LL_GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */
#endif /* defined (GPU2D) */
/* LPDMA1 triggers */
#define LL_LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger is EXTI_LINE0 */
#define LL_LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger is EXTI_LINE1 */
#define LL_LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger is EXTI_LINE2 */
#define LL_LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger is EXTI_LINE3 */
#define LL_LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger is EXTI_LINE4 */
#define LL_LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger is TAMP_TRG1 */
#define LL_LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger is TAMP_TRG2 */
#define LL_LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger is TAMP_TRG3 */
#define LL_LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger is LPTIM1_CH1 */
#define LL_LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger is LPTIM1_CH2 */
#define LL_LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger is LPTIM3_CH1 */
#define LL_LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger is LPTIM4_OUT */
#define LL_LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger is COMP1_OUT */
#define LL_LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger is COMP2_OUT */
#define LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger is RTC_ALRA_TRG */
#define LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger is RTC_ALRB_TRG */
#define LL_LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger is RTC_WUT_TRG */
#define LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger is LPDMA1_CH0_TCF */
#define LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger is LPDMA1_CH1_TCF */
#define LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger is LPDMA1_CH2_TCF */
#define LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger is LPDMA1_CH3_TCF */
#define LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger is GPDMA1_CH0_TCF */
#define LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger is GPDMA1_CH1_TCF */
#define LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger is GPDMA1_CH4_TCF */
#define LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger is GPDMA1_CH5_TCF */
#define LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger is GPDMA1_CH6_TCF */
#define LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger is GPDMA1_CH7_TCF */
#define LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger is GPDMA1_CH12_TCF */
#define LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger is GPDMA1_CH13_TCF */
#define LL_LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger is TIM2_TRGO */
#define LL_LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger is TIM15_TRGO */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
* @{
*/
/** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros
* @{
*/
/**
* @brief Write a value in DMA register.
* @param __INSTANCE__ DMA Instance.
* @param __REG__ Register to be written.
* @param __VALUE__ Value to be written in the register.
* @retval None.
*/
#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in DMA register.
* @param __INSTANCE__ DMA Instance.
* @param __REG__ Register to be read.
* @retval Register value.
*/
#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
* @{
*/
/**
* @brief Convert DMAx_Channely into DMAx.
* @param __CHANNEL_INSTANCE__ DMAx_Channely.
* @retval DMAx.
*/
#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel15)) ? LPDMA1 : GPDMA1)
/**
* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y.
* @param __CHANNEL_INSTANCE__ DMAx_Channely.
* @retval LL_DMA_CHANNEL_y.
*/
#define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \
LL_DMA_CHANNEL_15)
/**
* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.
* @param __DMA_INSTANCE__ DMAx.
* @param __CHANNEL__ LL_DMA_CHANNEL_y.
* @retval DMAx_Channely.
*/
#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
? GPDMA1_Channel0 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \
? LPDMA1_Channel0 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
? GPDMA1_Channel1 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \
? LPDMA1_Channel1 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
? GPDMA1_Channel2 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \
? LPDMA1_Channel2 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
? GPDMA1_Channel3 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \
? LPDMA1_Channel3 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \
? GPDMA1_Channel4 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \
? GPDMA1_Channel5 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \
? GPDMA1_Channel6 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \
? GPDMA1_Channel7 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \
? GPDMA1_Channel8 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \
? GPDMA1_Channel9 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\
? GPDMA1_Channel10 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\
? GPDMA1_Channel11 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\
? GPDMA1_Channel12 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\
? GPDMA1_Channel13 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\
? GPDMA1_Channel14 : GPDMA1_Channel15)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
* @{
*/
/** @defgroup DMA_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable channel.
* @note This API is used for all available DMA channels.
* @rmtoll CCR EN LL_DMA_EnableChannel
* @param DMAx DMAx Instance.
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
}
/**
* @brief Disable channel.
* @note This API is used for all available DMA channels.
* @rmtoll CCR EN LL_DMA_DisableChannel
* @param DMAx DMAx Instance.
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
(DMA_CCR_SUSP | DMA_CCR_RESET));
}
/**
* @brief Check if channel is enabled or disabled.
* @note This API is used for all available DMA channels.
* @rmtoll CCR EN LL_DMA_IsEnabledChannel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN)
== (DMA_CCR_EN)) ? 1UL : 0UL);
}
/**
* @brief Reset channel.
* @note This API is used for all available DMA channels.
* @rmtoll CCR RESET LL_DMA_ResetChannel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ResetChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET);
}
/**
* @brief Suspend channel.
* @note This API is used for all available DMA channels.
* @rmtoll CCR SUSP LL_DMA_SuspendChannel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SuspendChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
}
/**
* @brief Resume channel.
* @note This API is used for all available DMA channels.
* @rmtoll CCR SUSP LL_DMA_ResumeChannel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ResumeChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP);
}
/**
* @brief Check if channel is suspended.
* @note This API is used for all available DMA channels.
* @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP)
== (DMA_CCR_SUSP)) ? 1UL : 0UL);
}
/**
* @brief Set linked-list base address.
* @note This API is used for all available DMA channels.
* @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes
* are always 0)
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkedListBaseAddr)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA,
(LinkedListBaseAddr & DMA_CLBAR_LBA));
}
/**
* @brief Get linked-list base address.
* @note This API is used for all available DMA channels.
* @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0)
*/
__STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA));
}
/**
* @brief Configure all parameters linked to channel control.
* @note This API is used for all available DMA channels.
* For LPDMA channels, LAP field programming is discarded.
* @rmtoll CCR PRIO LL_DMA_ConfigControl\n
* CCR LAP LL_DMA_ConfigControl\n
* CCR LSM LL_DMA_ConfigControl
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or
* @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY
* @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1
* @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION
*@retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigControl(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
(DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration);
}
/**
* @brief Set priority level.
* @note This API is used for all available DMA channels.
* @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param Priority This parameter can be one of the following values:
* @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
* @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
* @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
* @arg @ref LL_DMA_HIGH_PRIORITY
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority);
}
/**
* @brief Get Channel priority level.
* @note This API is used for all available DMA channels.
* @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT
* @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT
* @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT
* @arg @ref LL_DMA_HIGH_PRIORITY
*/
__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO));
}
/**
* @brief Set linked-list allocated port.
* @note This API is not used for LPDMA channels.
* @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param LinkAllocatedPort This parameter can be one of the following values:
* @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
* @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR,
DMA_CCR_LAP, LinkAllocatedPort);
}
/**
* @brief Get linked-list allocated port.
* @note This API is not used for LPDMA channels.
* @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_LINK_ALLOCATED_PORT0
* @arg @ref LL_DMA_LINK_ALLOCATED_PORT1
*/
__STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP));
}
/**
* @brief Set link step mode.
* @note This API is used for all available DMA channels.
* @rmtoll CCR LSM LL_DMA_SetLinkStepMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param LinkStepMode This parameter can be one of the following values:
* @arg @ref LL_DMA_LSM_FULL_EXECUTION
* @arg @ref LL_DMA_LSM_1LINK_EXECUTION
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetLinkStepMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode);
}
/**
* @brief Get Link step mode.
* @note This API is used for all available DMA channels.
* @rmtoll CCR LSM LL_DMA_GetLinkStepMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_LSM_FULL_EXECUTION
* @arg @ref LL_DMA_LSM_1LINK_EXECUTION
*/
__STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM));
}
/**
* @brief Configure data transfer.
* @note This API is used for all available DMA channels.
* For LPDMA channels DAP, DHX, DBX, SAP, SBX fields programming is
* discarded.
* @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n
* CTR1 DHX LL_DMA_ConfigTransfer\n
* CTR1 DBX LL_DMA_ConfigTransfer\n
* CTR1 DINC LL_DMA_ConfigTransfer\n
* CTR1 SAP LL_DMA_ConfigTransfer\n
* CTR1 SBX LL_DMA_ConfigTransfer\n
* CTR1 PAM LL_DMA_ConfigTransfer\n
* CTR1 SINC LL_DMA_ConfigTransfer
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1
* @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE
* @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE
* @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE
* @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT
* @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or
* @ref LL_DMA_DEST_DATAWIDTH_WORD
* @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1
* @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or
* @ref LL_DMA_DATA_PACK_UNPACK
* @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT
* @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or
* @ref LL_DMA_SRC_DATAWIDTH_WORD
*@retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \
DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration);
}
/**
* @brief Configure source and destination burst length.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n
* @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param SrcBurstLength Between 1 to 64
* @param DestBurstLength Between 1 to 64
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigBurstLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength,
uint32_t DestBurstLength)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
(DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \
(((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1));
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Configure all secure parameters linked to DMA channel.
* @note This API is used for all available DMA channels.
* @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n
* @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n
* @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC
* @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC
* @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel));
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
(DMA_CTR1_DSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC)));
}
/**
* @brief Enable security attribute of the DMA transfer to the destination.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
}
/**
* @brief Disable security attribute of the DMA transfer to the destination.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC);
}
/**
* @brief Check security attribute of the DMA transfer to the destination.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC)
== (DMA_CTR1_DSEC)) ? 1UL : 0UL);
}
/**
* @brief Enable security attribute of the DMA transfer from the source.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
}
/**
* @brief Disable security attribute of the DMA transfer from the source.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC);
}
/**
* @brief Check security attribute of the DMA transfer from the source.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC)
== (DMA_CTR1_SSEC)) ? 1UL : 0UL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief Set destination allocated port.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DestAllocatedPort This parameter can be one of the following values:
* @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
* @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDestAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP,
DestAllocatedPort);
}
/**
* @brief Get destination allocated port.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_DEST_ALLOCATED_PORT0
* @arg @ref LL_DMA_DEST_ALLOCATED_PORT1
*/
__STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP));
}
/**
* @brief Set destination half-word exchange.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DestHWordExchange This parameter can be one of the following values:
* @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
* @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDestHWordExchange(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX,
DestHWordExchange);
}
/**
* @brief Get destination half-word exchange.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE
* @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE
*/
__STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX));
}
/**
* @brief Set destination byte exchange.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DestByteExchange This parameter can be one of the following values:
* @arg @ref LL_DMA_DEST_BYTE_PRESERVE
* @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDestByteExchange(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX,
DestByteExchange);
}
/**
* @brief Get destination byte exchange.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_DEST_BYTE_PRESERVE
* @arg @ref LL_DMA_DEST_BYTE_EXCHANGE
*/
__STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX));
}
/**
* @brief Set source byte exchange.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param SrcByteExchange This parameter can be one of the following values:
* @arg @ref LL_DMA_SRC_BYTE_PRESERVE
* @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetSrcByteExchange(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX,
SrcByteExchange);
}
/**
* @brief Get source byte exchange.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_SRC_BYTE_PRESERVE
* @arg @ref LL_DMA_SRC_BYTE_EXCHANGE
*/
__STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX));
}
/**
* @brief Set destination burst length.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DestBurstLength Between 1 to 64
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDestBurstLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1,
((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1);
}
/**
* @brief Get destination burst length.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 1 to 64.
*/
__STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U);
}
/**
* @brief Set destination increment mode.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 DINC LL_DMA_SetDestIncMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DestInc This parameter can be one of the following values:
* @arg @ref LL_DMA_DEST_FIXED
* @arg @ref LL_DMA_DEST_INCREMENT
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDestIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc);
}
/**
* @brief Get destination increment mode.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 DINC LL_DMA_GetDestIncMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_DEST_FIXED
* @arg @ref LL_DMA_DEST_INCREMENT
*/
__STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC));
}
/**
* @brief Set destination data width.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DestDataWidth This parameter can be one of the following values:
* @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
* @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
* @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDestDataWidth(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2,
DestDataWidth);
}
/**
* @brief Get destination data width.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE
* @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD
* @arg @ref LL_DMA_DEST_DATAWIDTH_WORD
*/
__STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2));
}
/**
* @brief Set source allocated port.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param SrcAllocatedPort This parameter can be one of the following values:
* @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
* @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP,
SrcAllocatedPort);
}
/**
* @brief Get source allocated port.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_SRC_ALLOCATED_PORT0
* @arg @ref LL_DMA_SRC_ALLOCATED_PORT1
*/
__STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP));
}
/**
* @brief Set data alignment mode.
* @note This API is used for all available DMA channels.
* For LPDMA channels, PAM field is reduced to one bit.
* @rmtoll CTR1 PAM LL_DMA_SetDataAlignment
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DataAlignment This parameter can be one of the following values:
* @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
* @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
* @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels)
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDataAlignment(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM,
DataAlignment);
}
/**
* @brief Get data alignment mode.
* @note This API is used for all available DMA channels.
* For LPDMA channels, PAM field is reduced to one bit.
* @rmtoll CTR1 PAM LL_DMA_GetDataAlignment
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD
* @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD
* @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels)
*/
__STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM));
}
/**
* @brief Set source burst length.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param SrcBurstLength Between 1 to 64
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetSrcBurstLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1,
((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1);
}
/**
* @brief Get source burst length.
* @note This API is not used for LPDMA channels.
* @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 1 to 64
* @retval None.
*/
__STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1,
DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U);
}
/**
* @brief Set source increment mode.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param SrcInc This parameter can be one of the following values:
* @arg @ref LL_DMA_SRC_FIXED
* @arg @ref LL_DMA_SRC_INCREMENT
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetSrcIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc);
}
/**
* @brief Get source increment mode.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_SRC_FIXED
* @arg @ref LL_DMA_SRC_INCREMENT
*/
__STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC));
}
/**
* @brief Set source data width.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param SrcDataWidth This parameter can be one of the following values:
* @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
* @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
* @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetSrcDataWidth(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2,
SrcDataWidth);
}
/**
* @brief Get Source Data width.
* @note This API is used for all available DMA channels.
* @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE
* @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD
* @arg @ref LL_DMA_SRC_DATAWIDTH_WORD
*/
__STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2));
}
/**
* @brief Configure channel transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n
* CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n
* CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n
* CTR2 BREQ LL_DMA_ConfigChannelTransfer\n
* CTR2 DREQ LL_DMA_ConfigChannelTransfer\n
* CTR2 SWREQ LL_DMA_ConfigChannelTransfer
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or
* @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
* @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_HWREQUEST_BLK
* @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_TRIG_POLARITY_RISING or
* @ref LL_DMA_TRIG_POLARITY_FALLING
* @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or
* @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or
* @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
*@retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigChannelTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
(DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ),
Configuration);
}
/**
* @brief Set transfer event mode.
* @note This API is used for all available DMA channels.
* @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param TransferEventMode This parameter can be one of the following values:
* @arg @ref LL_DMA_TCEM_BLK_TRANSFER
* @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
* @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
* @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetTransferEventMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM,
TransferEventMode);
}
/**
* @brief Get transfer event mode.
* @note This API is used for all available DMA channels.
* @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_TCEM_BLK_TRANSFER
* @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER
* @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER
* @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER
*/
__STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM));
}
/**
* @brief Set trigger polarity.
* @note This API is used for all available DMA channels.
* @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param TriggerPolarity This parameter can be one of the following values:
* @arg @ref LL_DMA_TRIG_POLARITY_MASKED
* @arg @ref LL_DMA_TRIG_POLARITY_RISING
* @arg @ref LL_DMA_TRIG_POLARITY_FALLING
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetTriggerPolarity(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL,
TriggerPolarity);
}
/**
* @brief Get trigger polarity.
* @note This API is used for all available DMA channels.
* @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_TRIG_POLARITY_MASKED
* @arg @ref LL_DMA_TRIG_POLARITY_RISING
* @arg @ref LL_DMA_TRIG_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL));
}
/**
* @brief Set trigger Mode.
* @note This API is used for all available DMA channels.
* @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param TriggerMode This parameter can be one of the following values:
* @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
* @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
* @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
* @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetTriggerMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM,
TriggerMode);
}
/**
* @brief Get trigger Mode.
* @note This API is used for all available DMA channels.
* @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_TRIGM_BLK_TRANSFER
* @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels)
* @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER
* @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER
*/
__STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM));
}
/**
* @brief Set destination hardware and software transfer request.
* @note This API is used for all available DMA channels.
* @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n
* @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param Direction This parameter can be one of the following values:
* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels)
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels)
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction);
}
/**
* @brief Get destination hardware and software transfer request.
* @note This API is used for all available DMA channels.
* For LPDMA channels, DREQ fields programming is discarded.
* @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n
* @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels)
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels)
*/
__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
DMA_CTR2_DREQ | DMA_CTR2_SWREQ));
}
/**
* @brief Set block hardware request.
* @note This API is used for all available DMA channels.
* @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param BlkHWRequest This parameter can be one of the following values:
* @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
* @arg @ref LL_DMA_HWREQUEST_BLK
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ,
BlkHWRequest);
}
/**
* @brief Get block hardware request.
* @note This API is used for all available DMA channels.
* @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_HWREQUEST_SINGLEBURST
* @arg @ref LL_DMA_HWREQUEST_BLK
*/
__STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ));
}
/**
* @brief Set hardware request.
* @note This API is used for all available DMA channels.
* For LPDMA channels, REQSEL fields is reduced to 5 bits.
* @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param Request This parameter can be one of the following values:
* @arg @ref LL_GPDMA1_REQUEST_ADC1
* @arg @ref LL_GPDMA1_REQUEST_ADC4
* @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1
* @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
* @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
* @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
* @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
* @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
* @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
* @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
* @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
* @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
* @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC
* @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
* @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
* @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC
* @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
* @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
* @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC
* @arg @ref LL_GPDMA1_REQUEST_I2C4_RX
* @arg @ref LL_GPDMA1_REQUEST_I2C4_TX
* @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC
* @arg @ref LL_GPDMA1_REQUEST_USART1_RX
* @arg @ref LL_GPDMA1_REQUEST_USART1_TX
* @arg @ref LL_GPDMA1_REQUEST_USART2_RX
* @arg @ref LL_GPDMA1_REQUEST_USART2_TX
* @arg @ref LL_GPDMA1_REQUEST_USART3_RX
* @arg @ref LL_GPDMA1_REQUEST_USART3_TX
* @arg @ref LL_GPDMA1_REQUEST_UART4_RX
* @arg @ref LL_GPDMA1_REQUEST_UART4_TX
* @arg @ref LL_GPDMA1_REQUEST_UART5_RX
* @arg @ref LL_GPDMA1_REQUEST_UART5_TX
* @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
* @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
* @arg @ref LL_GPDMA1_REQUEST_SAI1_A
* @arg @ref LL_GPDMA1_REQUEST_SAI1_B
* @arg @ref LL_GPDMA1_REQUEST_SAI2_A
* @arg @ref LL_GPDMA1_REQUEST_SAI2_B
* @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1
* @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2
* @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
* @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
* @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM8_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG
* @arg @ref LL_GPDMA1_REQUEST_TIM8_COM
* @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
* @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
* @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
* @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
* @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
* @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI
* @arg @ref LL_GPDMA1_REQUEST_AES_IN
* @arg @ref LL_GPDMA1_REQUEST_AES_OUT
* @arg @ref LL_GPDMA1_REQUEST_HASH_IN
* @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX
* @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5
* @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
* @arg @ref LL_GPDMA1_REQUEST_FMAC_READ
* @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE
* @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ
* @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE
* @arg @ref LL_GPDMA1_REQUEST_SAES_IN
* @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
* @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
* @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
* @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
* @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
* @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
* @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
* @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
* @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
* @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
* @arg @ref LL_GPDMA1_REQUEST_HSPI1 (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C5_RX (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C5_TX (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C5_EVC (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C6_RX (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C6_TX (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C6_EVC (*)
* @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*)
* @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*)
* @arg @ref LL_GPDMA1_REQUEST_ADC2 (*)
*
* @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX
* @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX
* @arg @ref LL_LPDMA1_REQUEST_SPI3_RX
* @arg @ref LL_LPDMA1_REQUEST_SPI3_TX
* @arg @ref LL_LPDMA1_REQUEST_I2C3_RX
* @arg @ref LL_LPDMA1_REQUEST_I2C3_TX
* @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC
* @arg @ref LL_LPDMA1_REQUEST_ADC4
* @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1
* @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2
* @arg @ref LL_LPDMA1_REQUEST_ADF1_FLT0
* @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1
* @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2
* @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE
* @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1
* @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2
* @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE
*
* @note (*) Availability depends on devices.
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request);
}
/**
* @brief Get hardware request.
* @note This API is used for all available DMA channels.
* For LPDMA channels, REQSEL fields is reduced to 5 bits.
* @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPDMA1_REQUEST_ADC1
* @arg @ref LL_GPDMA1_REQUEST_ADC4
* @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1
* @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM6_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM7_UP
* @arg @ref LL_GPDMA1_REQUEST_SPI1_RX
* @arg @ref LL_GPDMA1_REQUEST_SPI1_TX
* @arg @ref LL_GPDMA1_REQUEST_SPI2_RX
* @arg @ref LL_GPDMA1_REQUEST_SPI2_TX
* @arg @ref LL_GPDMA1_REQUEST_SPI3_RX
* @arg @ref LL_GPDMA1_REQUEST_SPI3_TX
* @arg @ref LL_GPDMA1_REQUEST_I2C1_RX
* @arg @ref LL_GPDMA1_REQUEST_I2C1_TX
* @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC
* @arg @ref LL_GPDMA1_REQUEST_I2C2_RX
* @arg @ref LL_GPDMA1_REQUEST_I2C2_TX
* @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC
* @arg @ref LL_GPDMA1_REQUEST_I2C3_RX
* @arg @ref LL_GPDMA1_REQUEST_I2C3_TX
* @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC
* @arg @ref LL_GPDMA1_REQUEST_I2C4_RX
* @arg @ref LL_GPDMA1_REQUEST_I2C4_TX
* @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC
* @arg @ref LL_GPDMA1_REQUEST_USART1_RX
* @arg @ref LL_GPDMA1_REQUEST_USART1_TX
* @arg @ref LL_GPDMA1_REQUEST_USART2_RX
* @arg @ref LL_GPDMA1_REQUEST_USART2_TX
* @arg @ref LL_GPDMA1_REQUEST_USART3_RX
* @arg @ref LL_GPDMA1_REQUEST_USART3_TX
* @arg @ref LL_GPDMA1_REQUEST_UART4_RX
* @arg @ref LL_GPDMA1_REQUEST_UART4_TX
* @arg @ref LL_GPDMA1_REQUEST_UART5_RX
* @arg @ref LL_GPDMA1_REQUEST_UART5_TX
* @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX
* @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX
* @arg @ref LL_GPDMA1_REQUEST_SAI1_A
* @arg @ref LL_GPDMA1_REQUEST_SAI1_B
* @arg @ref LL_GPDMA1_REQUEST_SAI2_A
* @arg @ref LL_GPDMA1_REQUEST_SAI2_B
* @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1
* @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2
* @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM1_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG
* @arg @ref LL_GPDMA1_REQUEST_TIM1_COM
* @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM8_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG
* @arg @ref LL_GPDMA1_REQUEST_TIM8_COM
* @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM2_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM3_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG
* @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM4_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2
* @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3
* @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4
* @arg @ref LL_GPDMA1_REQUEST_TIM5_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG
* @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM15_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG
* @arg @ref LL_GPDMA1_REQUEST_TIM15_COM
* @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM16_UP
* @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1
* @arg @ref LL_GPDMA1_REQUEST_TIM17_UP
* @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI
* @arg @ref LL_GPDMA1_REQUEST_AES_IN
* @arg @ref LL_GPDMA1_REQUEST_AES_OUT
* @arg @ref LL_GPDMA1_REQUEST_HASH_IN
* @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX
* @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4
* @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5
* @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0
* @arg @ref LL_GPDMA1_REQUEST_FMAC_READ
* @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE
* @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ
* @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE
* @arg @ref LL_GPDMA1_REQUEST_SAES_IN
* @arg @ref LL_GPDMA1_REQUEST_SAES_OUT
* @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1
* @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2
* @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE
* @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1
* @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2
* @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE
* @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1
* @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2
* @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE
* @arg @ref LL_GPDMA1_REQUEST_HSPI1 (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C5_RX (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C5_TX (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C5_EVC (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C6_RX (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C6_TX (*)
* @arg @ref LL_GPDMA1_REQUEST_I2C6_EVC (*)
* @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*)
* @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*)
* @arg @ref LL_GPDMA1_REQUEST_ADC2 (*)
*
* @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX
* @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX
* @arg @ref LL_LPDMA1_REQUEST_SPI3_RX
* @arg @ref LL_LPDMA1_REQUEST_SPI3_TX
* @arg @ref LL_LPDMA1_REQUEST_I2C3_RX
* @arg @ref LL_LPDMA1_REQUEST_I2C3_TX
* @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC
* @arg @ref LL_LPDMA1_REQUEST_ADC4
* @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1
* @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2
* @arg @ref LL_LPDMA1_REQUEST_ADF1_FLT0
* @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1
* @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2
* @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE
* @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1
* @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2
* @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE
*
* @note (*) Availability depends on devices.
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL));
}
/**
* @brief Set hardware trigger.
* @note This API is used for all available DMA channels.
* For LPDMA channels, TRIGSEL fields is reduced to 5 bits.
* @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param Trigger This parameter can be one of the following values:
* @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
* @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
* @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
* @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
* @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
* @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
* @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3
* @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
* @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
* @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
* @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
* @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
* @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT
* @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT
* @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
* @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
* @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
* @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF
* @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF
* @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF
* @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF
* @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
* @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
* @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*)
* @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO (*)
* @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO (*)
* @arg @ref LL_GPDMA1_TRIGGER_LTDC_LI (*)
* @arg @ref LL_GPDMA1_TRIGGER_DSI_TE (*)
* @arg @ref LL_GPDMA1_TRIGGER_DSI_ER (*)
* @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC (*)
* @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC (*)
* @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW (*)
* @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG0 (*)
* @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG1 (*)
* @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG2 (*)
* @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG3 (*)
* @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1
* @arg @ref LL_GPDMA1_TRIGGER_ADC1_AWD1
*
* @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0
* @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1
* @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2
* @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3
* @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4
* @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1
* @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2
* @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3
* @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1
* @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2
* @arg @ref LL_LPDMA1_TRIGGER_LPTIM3_CH1
* @arg @ref LL_LPDMA1_TRIGGER_LPTIM4_OUT
* @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT
* @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT
* @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG
* @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG
* @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG
* @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF
* @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF
* @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF
* @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF
* @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO
* @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO
* @note (*) Availability depends on devices.
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL,
(Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
}
/**
* @brief Get hardware triggers.
* @note This API is used for all available DMA channels.
* For LPDMA channels, TRIGSEL fields is reduced to 5 bits.
* @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0
* @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1
* @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2
* @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3
* @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1
* @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2
* @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3
* @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1
* @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2
* @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1
* @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2
* @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT
* @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT
* @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT
* @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG
* @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG
* @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF
* @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF
* @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF
* @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF
* @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF
* @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF
* @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO
* @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO
* @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*)
* @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO (*)
* @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO (*)
* @arg @ref LL_GPDMA1_TRIGGER_LTDC_LI (*)
* @arg @ref LL_GPDMA1_TRIGGER_DSI_TE (*)
* @arg @ref LL_GPDMA1_TRIGGER_DSI_ER (*)
* @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC (*)
* @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC (*)
* @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW (*)
* @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG0 (*)
* @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG1 (*)
* @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG2 (*)
* @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG3 (*)
* @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1
* @arg @ref LL_GPDMA1_TRIGGER_ADC1_AWD1
*
* @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0
* @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1
* @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2
* @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3
* @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4
* @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1
* @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2
* @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3
* @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1
* @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2
* @arg @ref LL_LPDMA1_TRIGGER_LPTIM3_CH1
* @arg @ref LL_LPDMA1_TRIGGER_LPTIM4_OUT
* @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT
* @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT
* @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG
* @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG
* @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG
* @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF
* @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF
* @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF
* @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF
* @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF
* @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO
* @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO
* @note (*) Availability depends on devices.
*/
__STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2,
DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos);
}
/**
* @brief Configure addresses update.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n
* CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n
* CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n
* CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
* @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
* @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
* @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
*@retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration);
}
/**
* @brief Configure DMA Block number of data and repeat Count.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n
* CBR1 BRC LL_DMA_ConfigBlkCounters
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param BlkDataLength Between 0 to 0x0000FFFF
* @param BlkRptCount Between 0 to 0x00000EFF
*@retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigBlkCounters(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength,
uint32_t BlkRptCount)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
(DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos)));
}
/**
* @brief Set block repeat destination address update.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param BlkRptDestAddrUpdate This parameter can be one of the following values:
* @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
* @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptDestAddrUpdate)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC,
BlkRptDestAddrUpdate);
}
/**
* @brief Get block repeat destination address update.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT
* @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT
*/
__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC));
}
/**
* @brief Set block repeat source address update.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param BlkRptSrcAddrUpdate This parameter can be one of the following values:
* @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
* @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptSrcAddrUpdate)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC,
BlkRptSrcAddrUpdate);
}
/**
* @brief Get block repeat source address update.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT
* @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT
*/
__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC));
}
/**
* @brief Set destination address update.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DestAddrUpdate This parameter can be one of the following values:
* @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
* @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC,
DestAddrUpdate);
}
/**
* @brief Get destination address update.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT
* @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT
*/
__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC));
}
/**
* @brief Set source address update.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param SrcAddrUpdate This parameter can be one of the following values:
* @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
* @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC,
SrcAddrUpdate);
}
/**
* @brief Get source address update.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT
* @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT
*/
__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC));
}
/**
* @brief Set block repeat count.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param BlkRptCount Between 0 to 0x00000EFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetBlkRptCount(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC,
(BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
}
/**
* @brief Get block repeat count.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 0 to 0x00000EFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1,
DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos);
}
/**
* @brief Set block data length in bytes to transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param BlkDataLength Between 0 to 0x0000FFFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetBlkDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT,
BlkDataLength);
}
/**
* @brief Get block data length in bytes to transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 0 to 0x0000FFFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT));
}
/**
* @brief Configure the source and destination addresses.
* @note This API is used for all available DMA channels.
* @note This API must not be called when the DMA Channel is enabled.
* @rmtoll CSAR SA LL_DMA_ConfigAddresses\n
* CDAR DA LL_DMA_ConfigAddresses
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param SrcAddress Between 0 to 0xFFFFFFFF
* @param DestAddress Between 0 to 0xFFFFFFFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t
DestAddress)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
}
/**
* @brief Set source address.
* @note This API is used for all available DMA channels.
* @rmtoll CSAR SA LL_DMA_SetSrcAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param SrcAddress Between 0 to 0xFFFFFFFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);
}
/**
* @brief Get source address.
* @note This API is used for all available DMA channels.
* @rmtoll CSAR SA LL_DMA_GetSrcAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 0 to 0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR));
}
/**
* @brief Set destination address.
* @note This API is used for all available DMA channels.
* @rmtoll CDAR DA LL_DMA_SetDestAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DestAddress Between 0 to 0xFFFFFFFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDestAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);
}
/**
* @brief Get destination address.
* @note This API is used for all available DMA channels.
* @rmtoll CDAR DA LL_DMA_GetDestAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 0 to 0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetDestAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR));
}
/**
* @brief Configure source and destination addresses offset.
* @note This API is used only for 2D addressing channels.
* @note This API must not be called when the DMA Channel is enabled.
* @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n
* CTR3 SAO LL_DMA_ConfigAddrUpdateValue
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DestAddrOffset Between 0 to 0x00001FFF
* @param SrcAddrOffset Between 0 to 0x00001FFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset,
uint32_t DestAddrOffset)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
(SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
}
/**
* @brief Set destination address offset.
* @note This API is used only for 2D addressing channels.
* @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param DestAddrOffset Between 0 to 0x00001FFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO,
((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO));
}
/**
* @brief Get destination address offset.
* @note This API is used only for 2D addressing channels.
* @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 0 to 0x00001FFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3,
DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
}
/**
* @brief Set source address offset.
* @note This API is used only for 2D addressing channels.
* @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param SrcAddrOffset Between 0 to 0x00001FFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO,
SrcAddrOffset & DMA_CTR3_SAO);
}
/**
* @brief Get source address offset.
* @note This API is used only for 2D addressing channels.
* @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 0 to 0x00001FFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO));
}
/**
* @brief Configure the block repeated source and destination addresses offset.
* @note This API is used only for 2D addressing channels.
* @note This API must not be called when the DMA Channel is enabled.
* @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n
* CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
* @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel,
uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO));
}
/**
* @brief Set block repeated destination address offset.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel,
uint32_t BlkRptDestAddrOffset)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO,
((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO));
}
/**
* @brief Get block repeated destination address offset.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 0 to 0x0000FFFF.
*/
__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2,
DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
}
/**
* @brief Set block repeated source address offset.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel,
uint32_t BlkRptSrcAddrOffset)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO,
BlkRptSrcAddrOffset);
}
/**
* @brief Get block repeated source address offset.
* @note This API is used only for 2D addressing channels.
* @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 0 to 0x0000FFFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO));
}
/**
* @brief Configure registers update and node address offset during the link transfer.
* @note This API is used for all available DMA channels.
* For linear addressing channels, UT3 and UB2 fields are discarded.
* @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n
* @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n
* @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n
* @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n
* @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n
* @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n
* @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n
* @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param RegistersUpdate This parameter must be a combination of all the following values:
* @arg @ref LL_DMA_UPDATE_CTR1
* @arg @ref LL_DMA_UPDATE_CTR2
* @arg @ref LL_DMA_UPDATE_CBR1
* @arg @ref LL_DMA_UPDATE_CSAR
* @arg @ref LL_DMA_UPDATE_CDAR
* @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels)
* @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels)
* @arg @ref LL_DMA_UPDATE_CLLR
* @param LinkedListAddrOffset Between 0 to 0x0000FFFC
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ConfigLinkUpdate(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate,
uint32_t LinkedListAddrOffset)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
(DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \
DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA)));
}
/**
* @brief Enable CTR1 update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableCTR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
}
/**
* @brief Disable CTR1 update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableCTR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1);
}
/**
* @brief Check if CTR1 update during the link transfer is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1)
== (DMA_CLLR_UT1)) ? 1UL : 0UL);
}
/**
* @brief Enable CTR2 update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableCTR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
}
/**
* @brief Disable CTR2 update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableCTR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2);
}
/**
* @brief Check if CTR2 update during the link transfer is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2)
== (DMA_CLLR_UT2)) ? 1UL : 0UL);
}
/**
* @brief Enable CBR1 update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableCBR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
}
/**
* @brief Disable CBR1 update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableCBR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1);
}
/**
* @brief Check if CBR1 update during the link transfer is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1)
== (DMA_CLLR_UB1)) ? 1UL : 0UL);
}
/**
* @brief Enable CSAR update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR USA LL_DMA_EnableCSARUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableCSARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
}
/**
* @brief Disable CSAR update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR USA LL_DMA_DisableCSARUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableCSARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA);
}
/**
* @brief Check if CSAR update during the link transfer is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA)
== (DMA_CLLR_USA)) ? 1UL : 0UL);
}
/**
* @brief Enable CDAR update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableCDARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
}
/**
* @brief Disable CDAR update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableCDARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA);
}
/**
* @brief Check if CDAR update during the link transfer is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA)
== (DMA_CLLR_UDA)) ? 1UL : 0UL);
}
/**
* @brief Enable CTR3 update during the link transfer.
* @note This API is used only for 2D addressing channels.
* @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableCTR3Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
}
/**
* @brief Disable CTR3 update during the link transfer.
* @note This API is used only for 2D addressing channels.
* @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableCTR3Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3);
}
/**
* @brief Check if CTR3 update during the link transfer is enabled.
* @note This API is used only for 2D addressing channels.
* @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3)
== (DMA_CLLR_UT3)) ? 1UL : 0UL);
}
/**
* @brief Enable CBR2 update during the link transfer.
* @note This API is used only for 2D addressing channels.
* @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableCBR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
}
/**
* @brief Disable CBR2 update during the link transfer.
* @note This API is used only for 2D addressing channels.
* @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableCBR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2);
}
/**
* @brief Check if CBR2 update during the link transfer is enabled.
* @note This API is used only for 2D addressing channels.
* @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2)
== (DMA_CLLR_UB2)) ? 1UL : 0UL);
}
/**
* @brief Enable CLLR update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableCLLRUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
}
/**
* @brief Disable CLLR update during the link transfer.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableCLLRUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL);
}
/**
* @brief Check if CLLR update during the link transfer is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL)
== (DMA_CLLR_ULL)) ? 1UL : 0UL);
}
/**
* @brief Set linked list address offset.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @param LinkedListAddrOffset Between 0 to 0x0000FFFC
* @retval None.
*/
__STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkedListAddrOffset)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA,
(LinkedListAddrOffset & DMA_CLLR_LA));
}
/**
* @brief Get linked list address offset.
* @note This API is used for all available DMA channels.
* @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 0 to 0x0000FFFC.
*/
__STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR,
DMA_CLLR_LA) >> DMA_CLLR_LA_Pos);
}
/**
* @brief Get FIFO level.
* @note This API is not used for LPDMA channels.
* @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval Between 0 to 0x000000FF.
*/
__STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR,
DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Enable the DMA channel secure attribute.
* @note This API is used for all available DMA channels.
* @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
{
SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
}
/**
* @brief Disable the DMA channel secure attribute.
* @note This API is used for all available DMA channels.
* @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
{
CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)));
}
/**
* @brief Check if DMA channel secure is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
{
return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU)))
== (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief Enable the DMA channel privilege attribute.
* @note This API is used for all available DMA channels.
* @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
{
SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
}
/**
* @brief Disable the DMA channel privilege attribute.
* @note This API is used for all available DMA channels.
* @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
{
CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)));
}
/**
* @brief Check if DMA Channel privilege is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
{
return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU)))
== (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Enable the DMA channel lock attributes.
* @note This API is used for all available DMA channels.
* @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
{
SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)));
}
/**
* @brief Check if DMA channel attributes are locked.
* @note This API is used for all available DMA channels.
* @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel)
{
return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU)))
== (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @}
*/
/** @defgroup DMA_LL_EF_FLAG_Management Flag Management
* @{
*/
/**
* @brief Clear trigger overrun flag.
* @note This API is used for all available DMA channels.
* @rmtoll CFCR TOF LL_DMA_ClearFlag_TO
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TO(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF);
}
/**
* @brief Clear suspension flag.
* @note This API is used for all available DMA channels.
* @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ClearFlag_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF);
}
/**
* @brief Clear user setting error flag.
* @note This API is used for all available DMA channels.
* @rmtoll CFCR USEF LL_DMA_ClearFlag_USE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ClearFlag_USE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF);
}
/**
* @brief Clear link transfer error flag.
* @note This API is used for all available DMA channels.
* @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ClearFlag_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF);
}
/**
* @brief Clear data transfer error flag.
* @note This API is used for all available DMA channels.
* @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF);
}
/**
* @brief Clear half transfer flag.
* @note This API is used for all available DMA channels.
* @rmtoll CFCR HTF LL_DMA_ClearFlag_HT
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF);
}
/**
* @brief Clear transfer complete flag.
* @note This API is used for all available DMA channels.
* @rmtoll CFCR TCF LL_DMA_ClearFlag_TC
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF);
}
/**
* @brief Get trigger overrun flag.
* @note This API is used for all available DMA channels.
* @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF)
== (DMA_CSR_TOF)) ? 1UL : 0UL);
}
/**
* @brief Get suspension flag.
* @note This API is used for all available DMA channels.
* @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF)
== (DMA_CSR_SUSPF)) ? 1UL : 0UL);
}
/**
* @brief Get user setting error flag.
* @note This API is used for all available DMA channels.
* @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF)
== (DMA_CSR_USEF)) ? 1UL : 0UL);
}
/**
* @brief Get user setting error flag.
* @note This API is used for all available DMA channels.
* @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF)
== (DMA_CSR_ULEF)) ? 1UL : 0UL);
}
/**
* @brief Get data transfer error flag.
* @note This API is used for all available DMA channels.
* @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE
* @param DMAx DMAx Instance
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF)
== (DMA_CSR_DTEF)) ? 1UL : 0UL);
}
/**
* @brief Get half transfer flag.
* @note This API is used for all available DMA channels.
* @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF)
== (DMA_CSR_HTF)) ? 1UL : 0UL);
}
/**
* @brief Get transfer complete flag.
* @note This API is used for all available DMA channels.
* @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF)
== (DMA_CSR_TCF)) ? 1UL : 0UL);
}
/**
* @brief Get idle flag.
* @note This API is used for all available DMA channels.
* @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF)
== (DMA_CSR_IDLEF)) ? 1UL : 0UL);
}
/**
* @brief Check if nsecure masked interrupt is active.
* @note This API is used for all available DMA channels.
* @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(DMA_TypeDef *DMAx, uint32_t Channel)
{
return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU)))
== (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Check if secure masked interrupt is active.
* @note This API is used for all available DMA channels.
* @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(DMA_TypeDef *DMAx, uint32_t Channel)
{
return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU)))
== (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @}
*/
/** @defgroup DMA_LL_EF_IT_Management Interrupt Management
* @{
*/
/**
* @brief Enable trigger overrun interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR TOIE LL_DMA_EnableIT_TO
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableIT_TO(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
}
/**
* @brief Enable suspension interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableIT_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
}
/**
* @brief Enable user setting error interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR USEIE LL_DMA_EnableIT_USE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableIT_USE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
}
/**
* @brief Enable update link transfer error interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableIT_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
}
/**
* @brief Enable data transfer error interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableIT_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
}
/**
* @brief Enable half transfer complete interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
}
/**
* @brief Enable transfer complete interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
}
/**
* @brief Disable trigger overrun interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR TOIE LL_DMA_DisableIT_TO
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableIT_TO(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE);
}
/**
* @brief Disable suspension interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableIT_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE);
}
/**
* @brief Disable user setting error interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR USEIE LL_DMA_DisableIT_USE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableIT_USE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE);
}
/**
* @brief Disable update link transfer error interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableIT_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE);
}
/**
* @brief Disable data transfer error interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableIT_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE);
}
/**
* @brief Disable half transfer complete interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
}
/**
* @brief Disable transfer complete interrupt.
* @note This API is used for all available DMA channels.
* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval None.
*/
__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
}
/**
* @brief Check if trigger overrun interrupt is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE)
== DMA_CCR_TOIE) ? 1UL : 0UL);
}
/**
* @brief Check if suspension interrupt is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE)
== DMA_CCR_SUSPIE) ? 1UL : 0UL);
}
/**
* @brief Check if user setting error interrupt is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE)
== DMA_CCR_USEIE) ? 1UL : 0UL);
}
/**
* @brief Check if update link transfer error interrupt is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE)
== DMA_CCR_ULEIE) ? 1UL : 0UL);
}
/**
* @brief Check if data transfer error interrupt is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE)
== DMA_CCR_DTEIE) ? 1UL : 0UL);
}
/**
* @brief Check if half transfer complete interrupt is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE)
== DMA_CCR_HTIE) ? 1UL : 0UL);
}
/**
* @brief Check if transfer complete interrupt is enabled.
* @note This API is used for all available DMA channels.
* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_0
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @arg @ref LL_DMA_CHANNEL_8
* @arg @ref LL_DMA_CHANNEL_9
* @arg @ref LL_DMA_CHANNEL_10
* @arg @ref LL_DMA_CHANNEL_11
* @arg @ref LL_DMA_CHANNEL_12
* @arg @ref LL_DMA_CHANNEL_13
* @arg @ref LL_DMA_CHANNEL_14
* @arg @ref LL_DMA_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE)
== DMA_CCR_TCIE) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined (USE_FULL_LL_DRIVER)
/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
* @{
*/
uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct);
uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel,
LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct);
uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode);
void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx,
LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx);
void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx);
/**
* @}
*/
#endif /* defined (USE_FULL_LL_DRIVER) */
/**
* @}
*/
/**
* @}
*/
#endif /* (defined (GPDMA1) || defined (LPDMA1)) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32U5xx_LL_DMA_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h
|
C
|
apache-2.0
| 317,149
|
/**
******************************************************************************
* @file stm32u5xx_ll_dma2d.h
* @author MCD Application Team
* @brief Header file of DMA2D LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_DMA2D_H
#define STM32U5xx_LL_DMA2D_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (DMA2D)
/** @defgroup DMA2D_LL DMA2D
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
* @{
*/
/**
* @brief LL DMA2D Init Structure Definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
- This parameter can be one value of @ref DMA2D_LL_EC_MODE.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetMode(). */
uint32_t ColorMode; /*!< Specifies the color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
This parameter can be modified afterwards using,
unitary function @ref LL_DMA2D_SetOutputColorMode(). */
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
This parameter can be modified afterwards
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
This parameter can be modified afterwards
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
This parameter can be modified afterwards using,
unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
- This parameter must be a number between:
Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
- This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
uint32_t LineOffset; /*!< Specifies the output line offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetLineOffset(). */
uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
- This parameter must be a number between:
Min_Data = 0x0000 and Max_Data = 0xFFFF.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
This parameter can be modified afterwards using,
unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
- This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
- This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
} LL_DMA2D_InitTypeDef;
/**
* @brief LL DMA2D Layer Configuration Structure Definition
*/
typedef struct
{
uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
- This parameter must be a number between:
Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
- @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
- @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
- This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
- @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
- This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
- @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
- @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
- This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
- @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
- @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
- @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
uint32_t Green; /*!< Specifies the foreground or background Green color value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
- @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
uint32_t Red; /*!< Specifies the foreground or background Red color value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
- @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
- This parameter must be a number between:
Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
- @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
- This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
- @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
This parameter can be modified afterwards using unitary functions
- @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
- @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
} LL_DMA2D_LayerCfgTypeDef;
/**
* @brief LL DMA2D Output Color Structure Definition
*/
typedef struct
{
uint32_t ColorMode; /*!< Specifies the color format of the output image.
- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
This parameter can be modified afterwards using
unitary function @ref LL_DMA2D_SetOutputColorMode(). */
uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
This parameter can be modified afterwards using,
unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- This parameter must be a number between
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputRed; /*!< Specifies the Red value of the output image.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
- This parameter must be a number between:
Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
- This parameter is not considered if RGB888 or RGB565 color mode is selected.
This parameter can be modified afterwards,
using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
function @ref LL_DMA2D_ConfigOutputColor(). */
} LL_DMA2D_ColorTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
* @{
*/
/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_DMA2D_ReadReg function
* @{
*/
#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
/**
* @}
*/
/** @defgroup DMA2D_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
* @{
*/
#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
/**
* @}
*/
/** @defgroup DMA2D_LL_EC_MODE Mode
* @{
*/
#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
#define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
/**
* @}
*/
/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
* @{
*/
#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
/**
* @}
*/
/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
* @{
*/
#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
/**
* @}
*/
/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
* @{
*/
#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
programmed alpha value */
#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
programmed alpha value with,
original alpha channel value */
/**
* @}
*/
/** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
* @{
*/
#define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */
#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */
/**
* @}
*/
/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
* @{
*/
#define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
#define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
/**
* @}
*/
/** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
* @{
*/
#define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
#define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
/**
* @}
*/
/** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
* @{
*/
#define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */
#define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */
/**
* @}
*/
/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
* @{
*/
#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
* @{
*/
/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in DMA2D register.
* @param __INSTANCE__ DMA2D Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in DMA2D register.
* @param __INSTANCE__ DMA2D Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
* @{
*/
/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
* @{
*/
/**
* @brief Start a DMA2D transfer.
* @rmtoll CR START LL_DMA2D_Start
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
{
SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
}
/**
* @brief Indicate if a DMA2D transfer is ongoing.
* @rmtoll CR START LL_DMA2D_IsTransferOngoing
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
}
/**
* @brief Suspend DMA2D transfer.
* @note This API can be used to suspend automatic foreground or background CLUT loading.
* @rmtoll CR SUSP LL_DMA2D_Suspend
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
{
MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
}
/**
* @brief Resume DMA2D transfer.
* @note This API can be used to resume automatic foreground or background CLUT loading.
* @rmtoll CR SUSP LL_DMA2D_Resume
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
{
CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
}
/**
* @brief Indicate if DMA2D transfer is suspended.
* @note This API can be used to indicate whether or not automatic foreground or
* background CLUT loading is suspended.
* @rmtoll CR SUSP LL_DMA2D_IsSuspended
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
}
/**
* @brief Abort DMA2D transfer.
* @note This API can be used to abort automatic foreground or background CLUT loading.
* @rmtoll CR ABORT LL_DMA2D_Abort
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
{
MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
}
/**
* @brief Indicate if DMA2D transfer is aborted.
* @note This API can be used to indicate whether or not automatic foreground or
* background CLUT loading is aborted.
* @rmtoll CR ABORT LL_DMA2D_IsAborted
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
}
/**
* @brief Set DMA2D mode.
* @rmtoll CR MODE LL_DMA2D_SetMode
* @param DMA2Dx DMA2D Instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_MODE_M2M
* @arg @ref LL_DMA2D_MODE_M2M_PFC
* @arg @ref LL_DMA2D_MODE_M2M_BLEND
* @arg @ref LL_DMA2D_MODE_R2M
* @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
* @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
{
MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
}
/**
* @brief Return DMA2D mode
* @rmtoll CR MODE LL_DMA2D_GetMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_MODE_M2M
* @arg @ref LL_DMA2D_MODE_M2M_PFC
* @arg @ref LL_DMA2D_MODE_M2M_BLEND
* @arg @ref LL_DMA2D_MODE_R2M
* @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
* @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
}
/**
* @brief Set DMA2D output color mode.
* @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
* @param DMA2Dx DMA2D Instance
* @param ColorMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
}
/**
* @brief Return DMA2D output color mode.
* @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
}
/**
* @brief Set DMA2D output Red Blue swap mode.
* @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
* @param DMA2Dx DMA2D Instance
* @param RBSwapMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_RB_MODE_REGULAR
* @arg @ref LL_DMA2D_RB_MODE_SWAP
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
{
MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
}
/**
* @brief Return DMA2D output Red Blue swap mode.
* @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_RB_MODE_REGULAR
* @arg @ref LL_DMA2D_RB_MODE_SWAP
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
}
/**
* @brief Set DMA2D output alpha inversion mode.
* @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
* @param DMA2Dx DMA2D Instance
* @param AlphaInversionMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_ALPHA_REGULAR
* @arg @ref LL_DMA2D_ALPHA_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
{
MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
}
/**
* @brief Return DMA2D output alpha inversion mode.
* @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_ALPHA_REGULAR
* @arg @ref LL_DMA2D_ALPHA_INVERTED
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
}
/**
* @brief Set DMA2D output swap mode.
* @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode
* @param DMA2Dx DMA2D Instance
* @param OutputSwapMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
* @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
{
MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
}
/**
* @brief Return DMA2D output swap mode.
* @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
* @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
}
/**
* @brief Set DMA2D line offset mode.
* @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode
* @param DMA2Dx DMA2D Instance
* @param LineOffsetMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
* @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
{
MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
}
/**
* @brief Return DMA2D line offset mode.
* @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
* @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
}
/**
* @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
* @rmtoll OOR LO LL_DMA2D_SetLineOffset
* @param DMA2Dx DMA2D Instance
* @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
{
MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
}
/**
* @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
* @rmtoll OOR LO LL_DMA2D_GetLineOffset
* @param DMA2Dx DMA2D Instance
* @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
}
/**
* @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
* @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
* @param DMA2Dx DMA2D Instance
* @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
{
MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
}
/**
* @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
* @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
* @param DMA2Dx DMA2D Instance
* @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
}
/**
* @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
* @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
* @param DMA2Dx DMA2D Instance
* @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
{
MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
}
/**
* @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
* @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
* @param DMA2Dx DMA2D Instance
* @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
}
/**
* @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
* @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
* @param DMA2Dx DMA2D Instance
* @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
{
LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
}
/**
* @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
* @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
* @param DMA2Dx DMA2D Instance
* @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
}
/**
* @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
* @note Output color format depends on output color mode, ARGB8888, RGB888,
* RGB565, ARGB1555 or ARGB4444.
* @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
* with respect to color mode is not done by the user code.
* @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
* OCOLR GREEN LL_DMA2D_SetOutputColor\n
* OCOLR RED LL_DMA2D_SetOutputColor\n
* OCOLR ALPHA LL_DMA2D_SetOutputColor
* @param DMA2Dx DMA2D Instance
* @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
{
MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
OutputColor);
}
/**
* @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
* @note Alpha channel and red, green, blue color values must be retrieved from the returned
* value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
* as set by @ref LL_DMA2D_SetOutputColorMode.
* @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
* OCOLR GREEN LL_DMA2D_GetOutputColor\n
* OCOLR RED LL_DMA2D_GetOutputColor\n
* OCOLR ALPHA LL_DMA2D_GetOutputColor
* @param DMA2Dx DMA2D Instance
* @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
(DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
}
/**
* @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
* @rmtoll LWR LW LL_DMA2D_SetLineWatermark
* @param DMA2Dx DMA2D Instance
* @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
{
MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
}
/**
* @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
* @rmtoll LWR LW LL_DMA2D_GetLineWatermark
* @param DMA2Dx DMA2D Instance
* @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
}
/**
* @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
* @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
* @param DMA2Dx DMA2D Instance
* @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
{
MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
}
/**
* @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
* @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
* @param DMA2Dx DMA2D Instance
* @retval Dead time value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
}
/**
* @brief Enable DMA2D dead time functionality.
* @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
{
SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
}
/**
* @brief Disable DMA2D dead time functionality.
* @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
{
CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
}
/**
* @brief Indicate if DMA2D dead time functionality is enabled.
* @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
}
/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
* @{
*/
/**
* @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
* @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
* @param DMA2Dx DMA2D Instance
* @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
{
LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
}
/**
* @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
* @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
* @param DMA2Dx DMA2D Instance
* @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
}
/**
* @brief Enable DMA2D foreground CLUT loading.
* @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
{
SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
}
/**
* @brief Indicate if DMA2D foreground CLUT loading is enabled.
* @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
}
/**
* @brief Set DMA2D foreground color mode.
* @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
* @param DMA2Dx DMA2D Instance
* @param ColorMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
* @arg @ref LL_DMA2D_INPUT_MODE_RGB888
* @arg @ref LL_DMA2D_INPUT_MODE_RGB565
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
* @arg @ref LL_DMA2D_INPUT_MODE_L8
* @arg @ref LL_DMA2D_INPUT_MODE_AL44
* @arg @ref LL_DMA2D_INPUT_MODE_AL88
* @arg @ref LL_DMA2D_INPUT_MODE_L4
* @arg @ref LL_DMA2D_INPUT_MODE_A8
* @arg @ref LL_DMA2D_INPUT_MODE_A4
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
}
/**
* @brief Return DMA2D foreground color mode.
* @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
* @arg @ref LL_DMA2D_INPUT_MODE_RGB888
* @arg @ref LL_DMA2D_INPUT_MODE_RGB565
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
* @arg @ref LL_DMA2D_INPUT_MODE_L8
* @arg @ref LL_DMA2D_INPUT_MODE_AL44
* @arg @ref LL_DMA2D_INPUT_MODE_AL88
* @arg @ref LL_DMA2D_INPUT_MODE_L4
* @arg @ref LL_DMA2D_INPUT_MODE_A8
* @arg @ref LL_DMA2D_INPUT_MODE_A4
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
}
/**
* @brief Set DMA2D foreground alpha mode.
* @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
* @param DMA2Dx DMA2D Instance
* @param AphaMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
* @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
* @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
{
MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
}
/**
* @brief Return DMA2D foreground alpha mode.
* @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
* @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
* @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
}
/**
* @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
* @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
* @param DMA2Dx DMA2D Instance
* @param Alpha Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
{
MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
}
/**
* @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
* @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
* @param DMA2Dx DMA2D Instance
* @retval Alpha value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
}
/**
* @brief Set DMA2D foreground Red Blue swap mode.
* @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
* @param DMA2Dx DMA2D Instance
* @param RBSwapMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_RB_MODE_REGULAR
* @arg @ref LL_DMA2D_RB_MODE_SWAP
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
{
MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
}
/**
* @brief Return DMA2D foreground Red Blue swap mode.
* @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_RB_MODE_REGULAR
* @arg @ref LL_DMA2D_RB_MODE_SWAP
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
}
/**
* @brief Set DMA2D foreground alpha inversion mode.
* @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
* @param DMA2Dx DMA2D Instance
* @param AlphaInversionMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_ALPHA_REGULAR
* @arg @ref LL_DMA2D_ALPHA_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
{
MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
}
/**
* @brief Return DMA2D foreground alpha inversion mode.
* @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_ALPHA_REGULAR
* @arg @ref LL_DMA2D_ALPHA_INVERTED
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
}
/**
* @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
* @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
* @param DMA2Dx DMA2D Instance
* @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
{
MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
}
/**
* @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
* @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
* @param DMA2Dx DMA2D Instance
* @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
}
/**
* @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
* @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
* @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
* @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
* @param DMA2Dx DMA2D Instance
* @param Red Value between Min_Data=0 and Max_Data=0xFF
* @param Green Value between Min_Data=0 and Max_Data=0xFF
* @param Blue Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
{
MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
}
/**
* @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
* @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
* @param DMA2Dx DMA2D Instance
* @param Red Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
{
MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
}
/**
* @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
* @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
* @param DMA2Dx DMA2D Instance
* @retval Red color value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
}
/**
* @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
* @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
* @param DMA2Dx DMA2D Instance
* @param Green Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
{
MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
}
/**
* @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
* @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
* @param DMA2Dx DMA2D Instance
* @retval Green color value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
}
/**
* @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
* @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
* @param DMA2Dx DMA2D Instance
* @param Blue Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
{
MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
}
/**
* @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
* @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
* @param DMA2Dx DMA2D Instance
* @retval Blue color value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
}
/**
* @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
* @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
* @param DMA2Dx DMA2D Instance
* @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
{
LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
}
/**
* @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
* @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
* @param DMA2Dx DMA2D Instance
* @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
}
/**
* @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
* @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
* @param DMA2Dx DMA2D Instance
* @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
{
MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
}
/**
* @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
* @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
* @param DMA2Dx DMA2D Instance
* @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
}
/**
* @brief Set DMA2D foreground CLUT color mode.
* @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
* @param DMA2Dx DMA2D Instance
* @param CLUTColorMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
{
MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
}
/**
* @brief Return DMA2D foreground CLUT color mode.
* @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
*/
__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
}
/**
* @}
*/
/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
* @{
*/
/**
* @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
* @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
* @param DMA2Dx DMA2D Instance
* @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
{
LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
}
/**
* @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
* @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
* @param DMA2Dx DMA2D Instance
* @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
}
/**
* @brief Enable DMA2D background CLUT loading.
* @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
{
SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
}
/**
* @brief Indicate if DMA2D background CLUT loading is enabled.
* @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
}
/**
* @brief Set DMA2D background color mode.
* @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
* @param DMA2Dx DMA2D Instance
* @param ColorMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
* @arg @ref LL_DMA2D_INPUT_MODE_RGB888
* @arg @ref LL_DMA2D_INPUT_MODE_RGB565
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
* @arg @ref LL_DMA2D_INPUT_MODE_L8
* @arg @ref LL_DMA2D_INPUT_MODE_AL44
* @arg @ref LL_DMA2D_INPUT_MODE_AL88
* @arg @ref LL_DMA2D_INPUT_MODE_L4
* @arg @ref LL_DMA2D_INPUT_MODE_A8
* @arg @ref LL_DMA2D_INPUT_MODE_A4
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
}
/**
* @brief Return DMA2D background color mode.
* @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
* @arg @ref LL_DMA2D_INPUT_MODE_RGB888
* @arg @ref LL_DMA2D_INPUT_MODE_RGB565
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
* @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
* @arg @ref LL_DMA2D_INPUT_MODE_L8
* @arg @ref LL_DMA2D_INPUT_MODE_AL44
* @arg @ref LL_DMA2D_INPUT_MODE_AL88
* @arg @ref LL_DMA2D_INPUT_MODE_L4
* @arg @ref LL_DMA2D_INPUT_MODE_A8
* @arg @ref LL_DMA2D_INPUT_MODE_A4
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
}
/**
* @brief Set DMA2D background alpha mode.
* @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
* @param DMA2Dx DMA2D Instance
* @param AphaMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
* @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
* @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
{
MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
}
/**
* @brief Return DMA2D background alpha mode.
* @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
* @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
* @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
}
/**
* @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
* @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
* @param DMA2Dx DMA2D Instance
* @param Alpha Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
{
MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
}
/**
* @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
* @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
* @param DMA2Dx DMA2D Instance
* @retval Alpha value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
}
/**
* @brief Set DMA2D background Red Blue swap mode.
* @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
* @param DMA2Dx DMA2D Instance
* @param RBSwapMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_RB_MODE_REGULAR
* @arg @ref LL_DMA2D_RB_MODE_SWAP
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
{
MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
}
/**
* @brief Return DMA2D background Red Blue swap mode.
* @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_RB_MODE_REGULAR
* @arg @ref LL_DMA2D_RB_MODE_SWAP
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
}
/**
* @brief Set DMA2D background alpha inversion mode.
* @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
* @param DMA2Dx DMA2D Instance
* @param AlphaInversionMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_ALPHA_REGULAR
* @arg @ref LL_DMA2D_ALPHA_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
{
MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
}
/**
* @brief Return DMA2D background alpha inversion mode.
* @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_ALPHA_REGULAR
* @arg @ref LL_DMA2D_ALPHA_INVERTED
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
}
/**
* @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
* @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
* @param DMA2Dx DMA2D Instance
* @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
{
MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
}
/**
* @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
* @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
* @param DMA2Dx DMA2D Instance
* @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
}
/**
* @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
* @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
* @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
* @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
* @param DMA2Dx DMA2D Instance
* @param Red Value between Min_Data=0 and Max_Data=0xFF
* @param Green Value between Min_Data=0 and Max_Data=0xFF
* @param Blue Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
{
MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
}
/**
* @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
* @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
* @param DMA2Dx DMA2D Instance
* @param Red Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
{
MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
}
/**
* @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
* @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
* @param DMA2Dx DMA2D Instance
* @retval Red color value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
}
/**
* @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
* @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
* @param DMA2Dx DMA2D Instance
* @param Green Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
{
MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
}
/**
* @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
* @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
* @param DMA2Dx DMA2D Instance
* @retval Green color value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
}
/**
* @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
* @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
* @param DMA2Dx DMA2D Instance
* @param Blue Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
{
MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
}
/**
* @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
* @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
* @param DMA2Dx DMA2D Instance
* @retval Blue color value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
}
/**
* @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
* @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
* @param DMA2Dx DMA2D Instance
* @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
{
LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
}
/**
* @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
* @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
* @param DMA2Dx DMA2D Instance
* @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
}
/**
* @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
* @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
* @param DMA2Dx DMA2D Instance
* @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
{
MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
}
/**
* @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
* @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
* @param DMA2Dx DMA2D Instance
* @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
}
/**
* @brief Set DMA2D background CLUT color mode.
* @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
* @param DMA2Dx DMA2D Instance
* @param CLUTColorMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
{
MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
}
/**
* @brief Return DMA2D background CLUT color mode.
* @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
* @param DMA2Dx DMA2D Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
*/
__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
{
return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
* @{
*/
/**
* @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
* @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
}
/**
* @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
* @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
}
/**
* @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
* @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
}
/**
* @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
* @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
}
/**
* @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
* @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
}
/**
* @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
* @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
}
/**
* @brief Clear DMA2D Configuration Error Interrupt Flag
* @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
{
WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
}
/**
* @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
* @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
{
WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
}
/**
* @brief Clear DMA2D CLUT Access Error Interrupt Flag
* @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
{
WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
}
/**
* @brief Clear DMA2D Transfer Watermark Interrupt Flag
* @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
{
WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
}
/**
* @brief Clear DMA2D Transfer Complete Interrupt Flag
* @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
{
WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
}
/**
* @brief Clear DMA2D Transfer Error Interrupt Flag
* @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
{
WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
}
/**
* @}
*/
/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
* @{
*/
/**
* @brief Enable Configuration Error Interrupt
* @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
{
SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
}
/**
* @brief Enable CLUT Transfer Complete Interrupt
* @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
{
SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
}
/**
* @brief Enable CLUT Access Error Interrupt
* @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
{
SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
}
/**
* @brief Enable Transfer Watermark Interrupt
* @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
{
SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
}
/**
* @brief Enable Transfer Complete Interrupt
* @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
{
SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
}
/**
* @brief Enable Transfer Error Interrupt
* @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
{
SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
}
/**
* @brief Disable Configuration Error Interrupt
* @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
{
CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
}
/**
* @brief Disable CLUT Transfer Complete Interrupt
* @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
{
CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
}
/**
* @brief Disable CLUT Access Error Interrupt
* @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
{
CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
}
/**
* @brief Disable Transfer Watermark Interrupt
* @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
{
CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
}
/**
* @brief Disable Transfer Complete Interrupt
* @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
{
CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
}
/**
* @brief Disable Transfer Error Interrupt
* @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
* @param DMA2Dx DMA2D Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
{
CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
}
/**
* @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
* @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
* @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
* @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
* @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
* @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
* @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
* @param DMA2Dx DMA2D Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
{
return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
* @{
*/
ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined (DMA2D) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_DMA2D_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma2d.h
|
C
|
apache-2.0
| 88,077
|
/**
******************************************************************************
* @file stm32u5xx_ll_exti.h
* @author MCD Application Team
* @brief Header file of EXTI LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_EXTI_H
#define STM32U5xx_LL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (EXTI)
/** @defgroup EXTI_LL EXTI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */
/* Private Macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
* @{
*/
typedef struct
{
uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
This parameter can be any combination of @ref EXTI_LL_EC_LINE */
FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTI_LL_EC_MODE. */
uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
} LL_EXTI_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_LL_EC_LINE LINE
* @{
*/
#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */
#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */
#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */
#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */
#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */
#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */
#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */
#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */
#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */
#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */
#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */
#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */
#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */
#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */
#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */
#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */
#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */
#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */
#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */
#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */
#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */
#define LL_EXTI_LINE_ALL_0_31 0x007FFFFFU /*!< ALL Extended line */
#if defined(USE_FULL_LL_DRIVER)
#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */
#endif /*USE_FULL_LL_DRIVER*/
/** @defgroup SYSTEM_LL_EC_EXTI_PORT EXTI EXTI PORT
* @{
*/
#define LL_EXTI_EXTI_PORTA 0U /*!< EXTI PORT A */
#define LL_EXTI_EXTI_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */
#define LL_EXTI_EXTI_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */
#define LL_EXTI_EXTI_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */
#define LL_EXTI_EXTI_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */
#define LL_EXTI_EXTI_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */
#define LL_EXTI_EXTI_PORTG (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */
#define LL_EXTI_EXTI_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */
#define LL_EXTI_EXTI_PORTI EXTI_EXTICR1_EXTI0_3 /*!< EXTI PORT I */
#if defined(GPIOJ)
#define LL_EXTI_EXTI_PORTJ (EXTI_EXTICR1_EXTI0_3 | EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT J */
#endif /* GPIOJ */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_EXTI_LINE EXTI EXTI LINE
* @{
*/
#define LL_EXTI_EXTI_LINE0 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
#define LL_EXTI_EXTI_LINE1 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
#define LL_EXTI_EXTI_LINE2 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */
#define LL_EXTI_EXTI_LINE3 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */
#define LL_EXTI_EXTI_LINE4 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
#define LL_EXTI_EXTI_LINE5 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
#define LL_EXTI_EXTI_LINE6 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */
#define LL_EXTI_EXTI_LINE7 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */
#define LL_EXTI_EXTI_LINE8 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
#define LL_EXTI_EXTI_LINE9 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
#define LL_EXTI_EXTI_LINE10 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */
#define LL_EXTI_EXTI_LINE11 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */
#define LL_EXTI_EXTI_LINE12 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
#define LL_EXTI_EXTI_LINE13 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
#define LL_EXTI_EXTI_LINE14 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */
#define LL_EXTI_EXTI_LINE15 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */
/**
* @}
*/
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_EC_MODE Mode
* @{
*/
#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
/**
* @}
*/
/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
* @{
*/
#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
* @{
*/
/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in EXTI register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
/**
* @brief Read a value in EXTI register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->IMR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->IMR1, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Event_Management Event_Management
* @{
*/
/**
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->EMR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->EMR1, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
* @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
* @{
*/
/**
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->RTSR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->RTSR1, ExtiLine);
}
/**
* @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
* @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
* @{
*/
/**
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->FTSR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a Falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for the same interrupt line.
* In this case, both generate a trigger condition.
* @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->FTSR1, ExtiLine);
}
/**
* @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
* @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
* @{
*/
/**
* @brief Generate a software Interrupt Event for Lines in range 0 to 31
* @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
* resulting in an interrupt request generation.
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
* register (by writing a 1 into the bit)
* @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->SWIER1, ExtiLine);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
* @{
*/
/**
* @brief Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31
* @note This bit is set when the falling edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31
* @note This bit is set when the falling edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine)
{
return (uint32_t)(READ_BIT(EXTI->FPR1, ExtiLine));
}
/**
* @brief Clear ExtLine Falling Flags for Lines in range 0 to 31
* @note This bit is set when the falling edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine)
{
WRITE_REG(EXTI->FPR1, ExtiLine);
}
/**
* @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31
* @note This bit is set when the Rising edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31
* @note This bit is set when the Rising edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine)
{
return (uint32_t)(READ_BIT(EXTI->RPR1, ExtiLine));
}
/**
* @brief Clear ExtLine Rising Flags for Lines in range 0 to 31
* @note This bit is set when the Rising edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine)
{
WRITE_REG(EXTI->RPR1, ExtiLine);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Config EF configuration functions
* @{
*/
/**
* @brief Configure source input for the EXTI external interrupt.
* @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n
* EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource
* @param Port This parameter can be one of the following values:
* @arg @ref LL_EXTI_EXTI_PORTA
* @arg @ref LL_EXTI_EXTI_PORTB
* @arg @ref LL_EXTI_EXTI_PORTC
* @arg @ref LL_EXTI_EXTI_PORTD
* @arg @ref LL_EXTI_EXTI_PORTE
* @arg @ref LL_EXTI_EXTI_PORTF
* @arg @ref LL_EXTI_EXTI_PORTG
* @arg @ref LL_EXTI_EXTI_PORTH
* @arg @ref LL_EXTI_EXTI_PORTI
* @arg @ref LL_EXTI_EXTI_PORTJ
*
* (*) value not defined in all devices
* @param Line This parameter can be one of the following values:
* @arg @ref LL_EXTI_EXTI_LINE0
* @arg @ref LL_EXTI_EXTI_LINE1
* @arg @ref LL_EXTI_EXTI_LINE2
* @arg @ref LL_EXTI_EXTI_LINE3
* @arg @ref LL_EXTI_EXTI_LINE4
* @arg @ref LL_EXTI_EXTI_LINE5
* @arg @ref LL_EXTI_EXTI_LINE6
* @arg @ref LL_EXTI_EXTI_LINE7
* @arg @ref LL_EXTI_EXTI_LINE8
* @arg @ref LL_EXTI_EXTI_LINE9
* @arg @ref LL_EXTI_EXTI_LINE10
* @arg @ref LL_EXTI_EXTI_LINE11
* @arg @ref LL_EXTI_EXTI_LINE12
* @arg @ref LL_EXTI_EXTI_LINE13
* @arg @ref LL_EXTI_EXTI_LINE14
* @arg @ref LL_EXTI_EXTI_LINE15
* @retval None
*/
__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line)
{
MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), \
Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
}
/**
* @brief Get the configured defined for specific EXTI Line
* @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR1 EXTI1 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR1 EXTI2 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR1 EXTI3 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR2 EXTI4 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR2 EXTI5 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR2 EXTI6 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR2 EXTI7 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR3 EXTI8 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR3 EXTI9 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR3 EXTI10 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR3 EXTI11 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR4 EXTI12 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR4 EXTI13 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR4 EXTI14 LL_EXTI_GetEXTISource\n
* EXTI_EXTICR4 EXTI15 LL_EXTI_GetEXTISource
* @param Line This parameter can be one of the following values:
* @arg @ref LL_EXTI_EXTI_LINE0
* @arg @ref LL_EXTI_EXTI_LINE1
* @arg @ref LL_EXTI_EXTI_LINE2
* @arg @ref LL_EXTI_EXTI_LINE3
* @arg @ref LL_EXTI_EXTI_LINE4
* @arg @ref LL_EXTI_EXTI_LINE5
* @arg @ref LL_EXTI_EXTI_LINE6
* @arg @ref LL_EXTI_EXTI_LINE7
* @arg @ref LL_EXTI_EXTI_LINE8
* @arg @ref LL_EXTI_EXTI_LINE9
* @arg @ref LL_EXTI_EXTI_LINE10
* @arg @ref LL_EXTI_EXTI_LINE11
* @arg @ref LL_EXTI_EXTI_LINE12
* @arg @ref LL_EXTI_EXTI_LINE13
* @arg @ref LL_EXTI_EXTI_LINE14
* @arg @ref LL_EXTI_EXTI_LINE15
* @retval Returned value can be one of the following values:
* @arg @ref LL_EXTI_EXTI_PORTA
* @arg @ref LL_EXTI_EXTI_PORTB
* @arg @ref LL_EXTI_EXTI_PORTC
* @arg @ref LL_EXTI_EXTI_PORTD
* @arg @ref LL_EXTI_EXTI_PORTE
* @arg @ref LL_EXTI_EXTI_PORTF
* @arg @ref LL_EXTI_EXTI_PORTG
* @arg @ref LL_EXTI_EXTI_PORTH
* @arg @ref LL_EXTI_EXTI_PORTI
* @arg @ref LL_EXTI_EXTI_PORTJ
*/
__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line)
{
return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U],
(EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >>
(Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Secure_Management Secure_Management
* @{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Enable ExtiLine Secure attribute for Lines in range 0 to 31
* @rmtoll SECCFGR1 SECx LL_EXTI_EnableSecure_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->SECCFGR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Secure attribute for Lines in range 0 to 31
* @rmtoll SECCFGR1 SECx LL_EXTI_DisableSecure_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->SECCFGR1, ExtiLine);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 0 to 31
* @rmtoll SECCFGR1 SECx LL_EXTI_IsEnabledSecure_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->SECCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Privilege_Management Privilege_Management
* @{
*/
/**
* @brief Enable ExtiLine Privilege attribute for Lines in range 0 to 31
* @rmtoll PRIVCFGR1 PRIVx LL_EXTI_EnablePrivilege_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->PRIVCFGR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Privilege attribute for Lines in range 0 to 31
* @rmtoll PRIVCFGR1 PRIVx LL_EXTI_DisablePrivilege_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->PRIVCFGR1, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 0 to 31
* @rmtoll PRIVCFGR1 PRIVx LL_EXTI_IsEnabledPrivilege_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->PRIVCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
ErrorStatus LL_EXTI_DeInit(void);
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* EXTI */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_EXTI_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h
|
C
|
apache-2.0
| 53,774
|
/**
******************************************************************************
* @file stm32u5xx_ll_fmac.h
* @author MCD Application Team
* @brief Header file of FMAC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_FMAC_H
#define STM32U5xx_LL_FMAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(FMAC)
/** @defgroup FMAC_LL FMAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants
* @{
*/
/** @defgroup FMAC_LL_EC_GET_FLAG Get Flag Defines
* @brief Flag defines which can be used with LL_FMAC_ReadReg function
* @{
*/
#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */
#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */
/**
* @}
*/
/** @defgroup FMAC_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions
* @{
*/
#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */
/**
* @}
*/
/** @defgroup FMAC_LL_EC_WM FMAC watermarks
* @brief Watermark defines that can be used for buffer full (input) or buffer empty (output)
* @{
*/
#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */
#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */
#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */
#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */
/**
* @}
*/
/** @defgroup FMAC_LL_EC_FUNC FMAC functions
* @{
*/
#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
/**
* @}
*/
/** @defgroup FMAC_LL_EC_PROCESSING FMAC processing
* @{
*/
#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */
#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */
/**
* @}
*/
/**
* @}
*/
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup FMAC_LL_Exported_Macros FMAC Exported Macros
* @{
*/
/** @defgroup FMAC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in FMAC register
* @param __INSTANCE__ FMAC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_FMAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in FMAC register
* @param __INSTANCE__ FMAC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_FMAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions
* @{
*/
/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
* @{
*/
/**
* @brief Configure X1 full watermark.
* @rmtoll X1BUFCFG FULL_WM LL_FMAC_SetX1FullWatermark
* @param FMACx FMAC instance
* @param Watermark This parameter can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Watermark)
{
MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM, Watermark);
}
/**
* @brief Return X1 full watermark.
* @rmtoll X1BUFCFG FULL_WM LL_FMAC_GetX1FullWatermark
* @param FMACx FMAC instance
* @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
*/
__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx)
{
return (uint32_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM));
}
/**
* @brief Configure X1 buffer size.
* @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_SetX1BufferSize
* @param FMACx FMAC instance
* @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
}
/**
* @brief Return X1 buffer size.
* @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize
* @param FMACx FMAC instance
* @retval uint8_t Number of 16-bit words allocated to the input buffer
* (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE) >> FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
}
/**
* @brief Configure X1 base.
* @rmtoll X1BUFCFG X1_BASE LL_FMAC_SetX1Base
* @param FMACx FMAC instance
* @param Base Base address of the input buffer (X1) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base)
{
MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE, ((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos);
}
/**
* @brief Return X1 base.
* @rmtoll X1BUFCFG X1_BASE LL_FMAC_GetX1Base
* @param FMACx FMAC instance
* @retval uint8_t Base address of the input buffer (X1) within the internal memory
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE) >> FMAC_X1BUFCFG_X1_BASE_Pos);
}
/**
* @brief Configure X2 buffer size.
* @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_SetX2BufferSize
* @param FMACx FMAC instance
* @param BufferSize Number of 16-bit words allocated to the coefficient buffer.
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
}
/**
* @brief Return X2 buffer size.
* @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize
* @param FMACx FMAC instance
* @retval uint8_t Number of 16-bit words allocated to the coefficient buffer
* (value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE) >> FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
}
/**
* @brief Configure X2 base.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_SetX2Base
* @param FMACx FMAC instance
* @param Base Base address of the coefficient buffer (X2) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base)
{
MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE, ((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos);
}
/**
* @brief Return X2 base.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_GetX2Base
* @param FMACx FMAC instance
* @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE) >> FMAC_X2BUFCFG_X2_BASE_Pos);
}
/**
* @brief Configure Y empty watermark.
* @rmtoll YBUFCFG EMPTY_WM LL_FMAC_SetYEmptyWatermark
* @param FMACx FMAC instance
* @param Watermark This parameter can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Watermark)
{
MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM, Watermark);
}
/**
* @brief Return Y empty watermark.
* @rmtoll YBUFCFG EMPTY_WM LL_FMAC_GetYEmptyWatermark
* @param FMACx FMAC instance
* @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
*/
__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx)
{
return (uint32_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM));
}
/**
* @brief Configure Y buffer size.
* @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_SetYBufferSize
* @param FMACx FMAC instance
* @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
{
MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
}
/**
* @brief Return Y buffer size.
* @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize
* @param FMACx FMAC instance
* @retval uint8_t Number of 16-bit words allocated to the output buffer
* (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE) >> FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
}
/**
* @brief Configure Y base.
* @rmtoll YBUFCFG Y_BASE LL_FMAC_SetYBase
* @param FMACx FMAC instance
* @param Base Base address of the output buffer (Y) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base)
{
MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE, ((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos);
}
/**
* @brief Return Y base.
* @rmtoll YBUFCFG Y_BASE LL_FMAC_GetYBase
* @param FMACx FMAC instance
* @retval uint8_t Base address of the output buffer (Y) within the internal memory
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE) >> FMAC_YBUFCFG_Y_BASE_Pos);
}
/**
* @brief Start FMAC processing.
* @rmtoll PARAM START LL_FMAC_EnableStart
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableStart(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->PARAM, FMAC_PARAM_START);
}
/**
* @brief Stop FMAC processing.
* @rmtoll PARAM START LL_FMAC_DisableStart
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->PARAM, FMAC_PARAM_START);
}
/**
* @brief Check the state of FMAC processing.
* @rmtoll PARAM START LL_FMAC_IsEnabledStart
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL);
}
/**
* @brief Configure function.
* @rmtoll PARAM FUNC LL_FMAC_SetFunction
* @param FMACx FMAC instance
* @param Function This parameter can be one of the following values:
* @arg @ref LL_FMAC_FUNC_LOAD_X1
* @arg @ref LL_FMAC_FUNC_LOAD_X2
* @arg @ref LL_FMAC_FUNC_LOAD_Y
* @arg @ref LL_FMAC_FUNC_CONVO_FIR
* @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_FUNC, Function);
}
/**
* @brief Return function.
* @rmtoll PARAM FUNC LL_FMAC_GetFunction
* @param FMACx FMAC instance
* @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_FUNC_LOAD_X1
* @arg @ref LL_FMAC_FUNC_LOAD_X2
* @arg @ref LL_FMAC_FUNC_LOAD_Y
* @arg @ref LL_FMAC_FUNC_CONVO_FIR
* @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
*/
__STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx)
{
return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC));
}
/**
* @brief Configure input parameter R.
* @rmtoll PARAM R LL_FMAC_SetParamR
* @param FMACx FMAC instance
* @param Param Parameter R (gain, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_R, ((uint32_t)Param) << FMAC_PARAM_R_Pos);
}
/**
* @brief Return input parameter R.
* @rmtoll PARAM R LL_FMAC_GetParamR
* @param FMACx FMAC instance
* @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos);
}
/**
* @brief Configure input parameter Q.
* @rmtoll PARAM Q LL_FMAC_SetParamQ
* @param FMACx FMAC instance
* @param Param Parameter Q (vector length, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_Q, ((uint32_t)Param) << FMAC_PARAM_Q_Pos);
}
/**
* @brief Return input parameter Q.
* @rmtoll PARAM Q LL_FMAC_GetParamQ
* @param FMACx FMAC instance
* @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos);
}
/**
* @brief Configure input parameter P.
* @rmtoll PARAM P LL_FMAC_SetParamP
* @param FMACx FMAC instance
* @param Param Parameter P (vector length, number of filter taps, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param));
}
/**
* @brief Return input parameter P.
* @rmtoll PARAM P LL_FMAC_GetParamP
* @param FMACx FMAC instance
* @retval uint8_t Parameter P (vector length, number of filter taps, etc.)
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P));
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_Reset_Management Reset_Management
* @{
*/
/**
* @brief Start the FMAC reset.
* @rmtoll CR RESET LL_FMAC_EnableReset
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_RESET);
}
/**
* @brief Check the state of the FMAC reset.
* @rmtoll CR RESET LL_FMAC_IsEnabledReset
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_RESET) == (FMAC_CR_RESET)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
* @{
*/
/**
* @brief Enable Clipping.
* @rmtoll CR CLIPEN LL_FMAC_EnableClipping
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableClipping(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_CLIPEN);
}
/**
* @brief Disable Clipping.
* @rmtoll CR CLIPEN LL_FMAC_DisableClipping
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_CLIPEN);
}
/**
* @brief Check Clipping State.
* @rmtoll CR CLIPEN LL_FMAC_IsEnabledClipping
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_CLIPEN) == (FMAC_CR_CLIPEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_DMA_Management DMA_Management
* @{
*/
/**
* @brief Enable FMAC DMA write channel request.
* @rmtoll CR DMAWEN LL_FMAC_EnableDMAReq_WRITE
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableDMAReq_WRITE(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_DMAWEN);
}
/**
* @brief Disable FMAC DMA write channel request.
* @rmtoll CR DMAWEN LL_FMAC_DisableDMAReq_WRITE
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_DMAWEN);
}
/**
* @brief Check FMAC DMA write channel request state.
* @rmtoll CR DMAWEN LL_FMAC_IsEnabledDMAReq_WRITE
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_DMAWEN) == (FMAC_CR_DMAWEN)) ? 1UL : 0UL);
}
/**
* @brief Enable FMAC DMA read channel request.
* @rmtoll CR DMAREN LL_FMAC_EnableDMAReq_READ
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableDMAReq_READ(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_DMAREN);
}
/**
* @brief Disable FMAC DMA read channel request.
* @rmtoll CR DMAREN LL_FMAC_DisableDMAReq_READ
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_DMAREN);
}
/**
* @brief Check FMAC DMA read channel request state.
* @rmtoll CR DMAREN LL_FMAC_IsEnabledDMAReq_READ
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_DMAREN) == (FMAC_CR_DMAREN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable FMAC saturation error interrupt.
* @rmtoll CR SATIEN LL_FMAC_EnableIT_SAT
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableIT_SAT(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_SATIEN);
}
/**
* @brief Disable FMAC saturation error interrupt.
* @rmtoll CR SATIEN LL_FMAC_DisableIT_SAT
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_SATIEN);
}
/**
* @brief Check FMAC saturation error interrupt state.
* @rmtoll CR SATIEN LL_FMAC_IsEnabledIT_SAT
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_SATIEN) == (FMAC_CR_SATIEN)) ? 1UL : 0UL);
}
/**
* @brief Enable FMAC underflow error interrupt.
* @rmtoll CR UNFLIEN LL_FMAC_EnableIT_UNFL
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableIT_UNFL(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_UNFLIEN);
}
/**
* @brief Disable FMAC underflow error interrupt.
* @rmtoll CR UNFLIEN LL_FMAC_DisableIT_UNFL
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_UNFLIEN);
}
/**
* @brief Check FMAC underflow error interrupt state.
* @rmtoll CR UNFLIEN LL_FMAC_IsEnabledIT_UNFL
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_UNFLIEN) == (FMAC_CR_UNFLIEN)) ? 1UL : 0UL);
}
/**
* @brief Enable FMAC overflow error interrupt.
* @rmtoll CR OVFLIEN LL_FMAC_EnableIT_OVFL
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableIT_OVFL(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_OVFLIEN);
}
/**
* @brief Disable FMAC overflow error interrupt.
* @rmtoll CR OVFLIEN LL_FMAC_DisableIT_OVFL
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_OVFLIEN);
}
/**
* @brief Check FMAC overflow error interrupt state.
* @rmtoll CR OVFLIEN LL_FMAC_IsEnabledIT_OVFL
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_OVFLIEN) == (FMAC_CR_OVFLIEN)) ? 1UL : 0UL);
}
/**
* @brief Enable FMAC write interrupt.
* @rmtoll CR WIEN LL_FMAC_EnableIT_WR
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableIT_WR(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_WIEN);
}
/**
* @brief Disable FMAC write interrupt.
* @rmtoll CR WIEN LL_FMAC_DisableIT_WR
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_WIEN);
}
/**
* @brief Check FMAC write interrupt state.
* @rmtoll CR WIEN LL_FMAC_IsEnabledIT_WR
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_WIEN) == (FMAC_CR_WIEN)) ? 1UL : 0UL);
}
/**
* @brief Enable FMAC read interrupt.
* @rmtoll CR RIEN LL_FMAC_EnableIT_RD
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableIT_RD(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_RIEN);
}
/**
* @brief Disable FMAC read interrupt.
* @rmtoll CR RIEN LL_FMAC_DisableIT_RD
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_RIEN);
}
/**
* @brief Check FMAC read interrupt state.
* @rmtoll CR RIEN LL_FMAC_IsEnabledIT_RD
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_RIEN) == (FMAC_CR_RIEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check FMAC saturation error flag state.
* @rmtoll SR SAT LL_FMAC_IsActiveFlag_SAT
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_SAT) == (FMAC_SR_SAT)) ? 1UL : 0UL);
}
/**
* @brief Check FMAC underflow error flag state.
* @rmtoll SR UNFL LL_FMAC_IsActiveFlag_UNFL
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_UNFL) == (FMAC_SR_UNFL)) ? 1UL : 0UL);
}
/**
* @brief Check FMAC overflow error flag state.
* @rmtoll SR OVFL LL_FMAC_IsActiveFlag_OVFL
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_OVFL) == (FMAC_SR_OVFL)) ? 1UL : 0UL);
}
/**
* @brief Check FMAC X1 buffer full flag state.
* @rmtoll SR X1FULL LL_FMAC_IsActiveFlag_X1FULL
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_X1FULL) == (FMAC_SR_X1FULL)) ? 1UL : 0UL);
}
/**
* @brief Check FMAC Y buffer empty flag state.
* @rmtoll SR YEMPTY LL_FMAC_IsActiveFlag_YEMPTY
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_YEMPTY) == (FMAC_SR_YEMPTY)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write 16-bit input data for the FMAC processing.
* @rmtoll WDATA WDATA LL_FMAC_WriteData
* @param FMACx FMAC instance
* @param InData 16-bit value to be provided as input data for FMAC processing.
* This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData)
{
WRITE_REG(FMACx->WDATA, InData);
}
/**
* @brief Return 16-bit output data of FMAC processing.
* @rmtoll RDATA RDATA LL_FMAC_ReadData
* @param FMACx FMAC instance
* @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF).
*/
__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx)
{
return (uint16_t)(READ_REG(FMACx->RDATA));
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
* @{
*/
/**
* @brief Configure memory for X1 buffer.
* @rmtoll X1BUFCFG FULL_WM LL_FMAC_ConfigX1\n
* X1BUFCFG X1_BASE LL_FMAC_ConfigX1\n
* X1BUFCFG X1_BUF_SIZE LL_FMAC_ConfigX1
* @param FMACx FMAC instance
* @param Watermark This parameter can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
* @param Base Base address of the input buffer (X1) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM | FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE,
Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) |
(((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
}
/**
* @brief Configure memory for X2 buffer.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_ConfigX2\n
* X2BUFCFG X2_BUF_SIZE LL_FMAC_ConfigX2
* @param FMACx FMAC instance
* @param Base Base address of the coefficient buffer (X2) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @param BufferSize Number of 16-bit words allocated to the coefficient buffer.
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE,
(((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) |
(((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
}
/**
* @brief Configure memory for Y buffer.
* @rmtoll YBUFCFG EMPTY_WM LL_FMAC_ConfigY\n
* YBUFCFG Y_BASE LL_FMAC_ConfigY\n
* YBUFCFG Y_BUF_SIZE LL_FMAC_ConfigY
* @param FMACx FMAC instance
* @param Watermark This parameter can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
* @param Base Base address of the output buffer (Y) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM | FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE,
Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) |
(((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
}
/**
* @brief Configure the FMAC processing.
* @rmtoll PARAM START LL_FMAC_ConfigFunc\n
* PARAM FUNC LL_FMAC_ConfigFunc\n
* PARAM P LL_FMAC_ConfigFunc\n
* PARAM Q LL_FMAC_ConfigFunc\n
* PARAM R LL_FMAC_ConfigFunc
* @param FMACx FMAC instance
* @param Start This parameter can be one of the following values:
* @arg @ref LL_FMAC_PROCESSING_STOP
* @arg @ref LL_FMAC_PROCESSING_START
* @param Function This parameter can be one of the following values:
* @arg @ref LL_FMAC_FUNC_LOAD_X1
* @arg @ref LL_FMAC_FUNC_LOAD_X2
* @arg @ref LL_FMAC_FUNC_LOAD_Y
* @arg @ref LL_FMAC_FUNC_CONVO_FIR
* @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
* @param ParamP Parameter P (vector length, number of filter taps, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @param ParamQ Parameter Q (vector length, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @param ParamR Parameter R (gain, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP,
uint8_t ParamQ, uint8_t ParamR)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_START | FMAC_PARAM_FUNC | FMAC_PARAM_P | FMAC_PARAM_Q | FMAC_PARAM_R,
(((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) |
(((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx);
ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(FMAC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_FMAC_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h
|
C
|
apache-2.0
| 35,102
|
/**
******************************************************************************
* @file stm32u5xx_ll_fmc.h
* @author MCD Application Team
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_FMC_H
#define STM32U5xx_LL_FMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup FMC_LL
* @{
*/
/** @addtogroup FMC_LL_Private_Macros
* @{
*/
#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
((__BANK__) == FMC_NORSRAM_BANK2) || \
((__BANK__) == FMC_NORSRAM_BANK3) || \
((__BANK__) == FMC_NORSRAM_BANK4))
#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
((__SIZE__) == FMC_PAGE_SIZE_128) || \
((__SIZE__) == FMC_PAGE_SIZE_256) || \
((__SIZE__) == FMC_PAGE_SIZE_512) || \
((__SIZE__) == FMC_PAGE_SIZE_1024))
#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
((__MODE__) == FMC_ACCESS_MODE_B) || \
((__MODE__) == FMC_ACCESS_MODE_C) || \
((__MODE__) == FMC_ACCESS_MODE_D))
#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \
((__NBL__) == FMC_NBL_SETUPTIME_1) || \
((__NBL__) == FMC_NBL_SETUPTIME_2) || \
((__NBL__) == FMC_NBL_SETUPTIME_3))
#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
((__BURST__) == FMC_WRITE_BURST_ENABLE))
#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
#define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U))
#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
((__STATE__) == FMC_NAND_ECC_ENABLE))
#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
/**
* @}
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
* @{
*/
#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
#define FMC_NORSRAM_DEVICE FMC_Bank1_R
#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R
#define FMC_NAND_DEVICE FMC_Bank3_R
/**
* @brief FMC NORSRAM Configuration Structure definition
*/
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
This parameter can be a value of @ref FMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
This parameter can be a value of @ref FMC_Memory_Type */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FMC_Burst_Access_Mode */
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FMC_Wait_Timing */
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
This parameter can be a value of @ref FMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FMC_Extended_Mode */
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FMC_AsynchronousWait */
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FMC_Write_Burst */
uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
This parameter is only enabled through the FMC_BCR1 register,
and don't care through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Continous_Clock */
uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
This parameter is only enabled through the FMC_BCR1 register,
and don't care through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Write_FIFO */
uint32_t PageSize; /*!< Specifies the memory page size.
This parameter can be a value of @ref FMC_Page_Size */
uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number
This parameter can be a value of @ref FMC_Byte_Lane */
FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this
NSBank for PSRAM refresh.
This parameter can be set to ENABLE or DISABLE */
uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for
synchronous accesses and in HCLK cycles for asynchronous accesses,
valid only if MaxChipSelectPulse is ENABLE.
This parameter can be a value between Min_Data = 1 and Max_Data = 65535.
@note: This parameter is common to all NSBank. */
} FMC_NORSRAM_InitTypeDef;
/**
* @brief FMC NORSRAM Timing parameters structure definition
*/
typedef struct
{
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data hold time.
This parameter can be a value between Min_Data = 0 and Max_Data = 3.
@note This parameter is used for used in asynchronous accesses. */
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and
Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17
in NOR Flash memories with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FMC_Access_Mode */
} FMC_NORSRAM_TimingTypeDef;
/**
* @brief FMC NAND Configuration Structure definition
*/
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
This parameter can be a value of @ref FMC_NAND_Bank */
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
This parameter can be any value of @ref FMC_Wait_feature */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FMC_NAND_Data_Width */
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FMC_ECC */
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FMC_ECC_Page_Size */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
} FMC_NAND_InitTypeDef;
/**
* @brief FMC NAND Timing parameters structure definition
*/
typedef struct
{
uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
} FMC_NAND_PCC_TimingTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
* @{
*/
/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
* @{
*/
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
#define FMC_NORSRAM_BANK1 (0x00000000U)
#define FMC_NORSRAM_BANK2 (0x00000002U)
#define FMC_NORSRAM_BANK3 (0x00000004U)
#define FMC_NORSRAM_BANK4 (0x00000006U)
/**
* @}
*/
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
/**
* @}
*/
/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
#define FMC_MEMORY_TYPE_NOR (0x00000008U)
/**
* @}
*/
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
/**
* @}
*/
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
/**
* @}
*/
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
/**
* @}
*/
/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
/**
* @}
*/
/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
/**
* @}
*/
/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
/**
* @}
*/
/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
/**
* @}
*/
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
/**
* @}
*/
/** @defgroup FMC_Page_Size FMC Page Size
* @{
*/
#define FMC_PAGE_SIZE_NONE (0x00000000U)
#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0
#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1
#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\
| FMC_BCRx_CPSIZE_1)
#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2
/**
* @}
*/
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
#define FMC_WRITE_BURST_DISABLE (0x00000000U)
#define FMC_WRITE_BURST_ENABLE (0x00080000U)
/**
* @}
*/
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
/**
* @}
*/
#if defined(FMC_BCR1_WFDIS)
/** @defgroup FMC_Write_FIFO FMC Write FIFO
* @{
*/
#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
#endif /* FMC_BCR1_WFDIS */
/**
* @}
*/
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
#define FMC_ACCESS_MODE_A (0x00000000U)
#define FMC_ACCESS_MODE_B (0x10000000U)
#define FMC_ACCESS_MODE_C (0x20000000U)
#define FMC_ACCESS_MODE_D (0x30000000U)
/**
* @}
*/
/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup
* @{
*/
#define FMC_NBL_SETUPTIME_0 (0x00000000U)
#define FMC_NBL_SETUPTIME_1 (0x00400000U)
#define FMC_NBL_SETUPTIME_2 (0x00800000U)
#define FMC_NBL_SETUPTIME_3 (0x00C00000U)
/**
* @}
*/
/**
* @}
*/
/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
* @{
*/
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
#define FMC_NAND_BANK3 (0x00000100U)
/**
* @}
*/
/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U)
#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U)
/**
* @}
*/
/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
/**
* @}
*/
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U)
#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U)
/**
* @}
*/
/** @defgroup FMC_ECC FMC ECC
* @{
*/
#define FMC_NAND_ECC_DISABLE (0x00000000U)
#define FMC_NAND_ECC_ENABLE (0x00000040U)
/**
* @}
*/
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
/**
* @}
*/
/**
* @}
*/
/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
* @{
*/
#define FMC_IT_RISING_EDGE (0x00000008U)
#define FMC_IT_LEVEL (0x00000010U)
#define FMC_IT_FALLING_EDGE (0x00000020U)
/**
* @}
*/
/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
* @{
*/
#define FMC_FLAG_RISING_EDGE (0x00000001U)
#define FMC_FLAG_LEVEL (0x00000002U)
#define FMC_FLAG_FALLING_EDGE (0x00000004U)
#define FMC_FLAG_FEMPT (0x00000040U)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
* @{
*/
/**
* @brief Enable the FMC Peripheral.
* @retval None
*/
#define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)
/**
* @brief Disable the FMC Peripheral.
* @retval None
*/
#define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
* @brief macros to handle NOR device enable/disable and read/write operations
* @{
*/
/**
* @brief Enable the NORSRAM device access.
* @param __INSTANCE__ FMC_NORSRAM Instance
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|= FMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
* @param __INSTANCE__ FMC_NORSRAM Instance
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
&= ~FMC_BCRx_MBKEN)
/**
* @}
*/
/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
/**
* @brief Enable the NAND device access.
* @param __INSTANCE__ FMC_NAND Instance
* @retval None
*/
#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
/**
* @brief Disable the NAND device access.
* @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @retval None
*/
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
/**
* @}
*/
/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
* @brief macros to handle NAND interrupts
* @{
*/
/**
* @brief Enable the NAND device interrupt.
* @param __INSTANCE__ FMC_NAND instance
* @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
/**
* @brief Disable the NAND device interrupt.
* @param __INSTANCE__ FMC_NAND Instance
* @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
/**
* @brief Get flag status of the NAND device.
* @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear flag status of the NAND device.
* @param __INSTANCE__ FMC_NAND Instance
* @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
* @{
*/
/** @defgroup FMC_LL_NORSRAM NOR SRAM
* @{
*/
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
uint32_t ExtendedMode);
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
* @{
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
/**
* @}
*/
/** @defgroup FMC_LL_NAND NAND
* @{
*/
/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
* @{
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_FMC_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h
|
C
|
apache-2.0
| 34,728
|
/**
******************************************************************************
* @file stm32u5xx_ll_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_GPIO_H
#define STM32U5xx_LL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \
defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ)
/** @defgroup GPIO_LL GPIO
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
* @{
*/
/**
* @brief LL GPIO Init Structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_LL_EC_PIN */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_MODE.
GPIO HW configuration can be modified afterwards using unitary function
@ref LL_GPIO_SetPinMode().*/
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_SPEED.
GPIO HW configuration can be modified afterwards using unitary function
@ref LL_GPIO_SetPinSpeed().*/
uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
GPIO HW configuration can be modified afterwards using unitary function
@ref LL_GPIO_SetPinOutputType().*/
uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_PULL.
GPIO HW configuration can be modified afterwards using unitary function
@ref LL_GPIO_SetPinPull().*/
uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_AF.
GPIO HW configuration can be modified afterwards using unitary function
@ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
} LL_GPIO_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_LL_EC_PIN PIN
* @{
*/
#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */
#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */
#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */
#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */
#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */
#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */
#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */
#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */
#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */
#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */
#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */
#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */
#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */
#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */
#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */
#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */
#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \
GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \
GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \
GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
GPIO_BSRR_BS15) /*!< Select all pins */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_MODE Mode
* @{
*/
#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */
#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */
#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_OUTPUT Output Type
* @{
*/
#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_SPEED Output Speed
* @{
*/
#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */
#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */
/**
* @}
*/
#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
* @{
*/
#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_AF Alternate Function
* @{
*/
#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
* @{
*/
/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in GPIO register
* @param __INSTANCE__ GPIO Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in GPIO register
* @param __INSTANCE__ GPIO Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
* @{
*/
/**
* @brief Configure gpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_GPIO_SetPinMode
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_GPIO_MODE_INPUT
* @arg @ref LL_GPIO_MODE_OUTPUT
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
{
MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_GPIO_GetPinMode
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_MODE_INPUT
* @arg @ref LL_GPIO_MODE_OUTPUT
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->MODER,
(GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or
* alternate modes. Possible type are Push-pull or Open-drain.
* @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @param OutputType This parameter can be one of the following values:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
{
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
}
/**
* @brief Return gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or
* alternate modes. Possible type are Push-pull or Open-drain.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
}
/**
* @brief Configure gpio speed for a dedicated pin on dedicated port.
* @note I/O speed can be Low, Medium, Fast or High speed.
* @note Warning: only one pin can be passed as parameter.
* @note Refer to datasheet for frequency specifications and the power
* supply and load conditions for each speed.
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Speed This parameter can be one of the following values:
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
{
MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
(Speed << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio speed for a dedicated pin on dedicated port.
* @note I/O speed can be Low, Medium, Fast or High speed.
* @note Warning: only one pin can be passed as parameter.
* @note Refer to datasheet for frequency specifications and the power
* supply and load conditions for each speed.
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
(GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Pull This parameter can be one of the following values:
* @arg @ref LL_GPIO_PULL_NO
* @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
{
MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
* @note Warning: only one pin can be passed as parameter.
* @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_PULL_NO
* @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->PUPDR,
(GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @param Alternate This parameter can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
(Alternate << (POSITION_VAL(Pin) * 4U)));
}
/**
* @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
* @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
*/
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->AFR[0],
(GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
}
/**
* @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Alternate This parameter can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
(Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
}
/**
* @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
*/
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->AFR[1],
(GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
}
/**
* @brief Lock configuration of several pins for a dedicated port.
* @note When the lock sequence has been applied on a port bit, the
* value of this port bit can no longer be modified until the
* next reset.
* @note Each lock bit freezes a specific configuration register
* (control and alternate function registers).
* @rmtoll LCKR LCKK LL_GPIO_LockPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
__IO uint32_t temp;
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
WRITE_REG(GPIOx->LCKR, PinMask);
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
/* Read LCKK register. This read is mandatory to complete key lock sequence */
temp = READ_REG(GPIOx->LCKR);
(void) temp;
}
/**
* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
* @param GPIOx GPIO Port
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
{
return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup GPIO_LL_EF_Data_Access Data Access
* @{
*/
/**
* @brief Return full input data register value for a dedicated port.
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
* @param GPIOx GPIO Port
* @retval Input data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
{
return (uint32_t)(READ_REG(GPIOx->IDR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Write output data register for the port.
* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
* @param GPIOx GPIO Port
* @param PortValue Level value for each pin of the port
* @retval None
*/
__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
{
WRITE_REG(GPIOx->ODR, PortValue);
}
/**
* @brief Return full output data register value for a dedicated port.
* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
* @param GPIOx GPIO Port
* @retval Output data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
{
return (uint32_t)(READ_REG(GPIOx->ODR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Set several pins to high level on dedicated gpio port.
* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
WRITE_REG(GPIOx->BSRR, PinMask);
}
/**
* @brief Set several pins to low level on dedicated gpio port.
* @rmtoll BRR BRy LL_GPIO_ResetOutputPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
WRITE_REG(GPIOx->BRR, PinMask);
}
/**
* @brief Toggle data value for several pin of dedicated port.
* @rmtoll ODR ODy LL_GPIO_TogglePin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
uint32_t odr = READ_REG(GPIOx->ODR);
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
}
/**
* @brief Enable speed optimization for several pin of dedicated port.
* @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
* datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
* be kept at reset value.
* @note It must be used only if the I/O supply voltage is below 2.7 V.
* @rmtoll HSLVR HSLVy LL_GPIO_EnableHighSPeedLowVoltage
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
SET_BIT(GPIOx->HSLVR, PinMask);
}
/**
* @brief Disable speed optimization for several pin of dedicated port.
* @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
* datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
* be kept at reset value.
* @note It must be used only if the I/O supply voltage is below 2.7 V.
* @rmtoll HSLVR HSLVy LL_GPIO_DisableHighSPeedLowVoltage
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
CLEAR_BIT(GPIOx->HSLVR, PinMask);
}
/**
* @brief Return if speed optimization for several pin of dedicated port is enabled or not.
* @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
* datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
* be kept at reset value.
* @note It must be used only if the I/O supply voltage is below 2.7 V.
* @rmtoll HSLVR HSLVy LL_GPIO_IsEnabledHighSPeedLowVoltage
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsEnabledHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->HSLVR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Enable secure write only access for several pin of dedicated port.
* @rmtoll SECCFGR SECy LL_GPIO_EnablePinSecure
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_EnablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
SET_BIT(GPIOx->SECCFGR, PinMask);
}
/**
* @brief Disable secure write only access for several pin of dedicated port.
* @rmtoll SECCFGR SECy LL_GPIO_DisablePinSecure
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_DisablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
CLEAR_BIT(GPIOx->SECCFGR, PinMask);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Return if secure write only access for several pin of dedicated port is enabled or not.
* @rmtoll SECCFGR SECy LL_GPIO_IsEnabledPinSecure
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->SECCFGR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \
defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ)*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_GPIO_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h
|
C
|
apache-2.0
| 45,082
|
/**
******************************************************************************
* @file stm32u5xx_ll_i2c.h
* @author MCD Application Team
* @brief Header file of I2C LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_I2C_H
#define STM32U5xx_LL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
/** @defgroup I2C_LL I2C
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_LL_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_LL_Private_Macros I2C Private Macros
* @{
*/
#define IS_LL_I2C_GRP1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) ||\
((__INSTANCE__) == I2C2) ||\
((__INSTANCE__) == I2C4))
#define IS_LL_I2C_GRP2_INSTANCE(__INSTANCE__) ((__INSTANCE__) == I2C3)
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
* @{
*/
typedef struct
{
uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
This feature can be modified afterwards using unitary function
@ref LL_I2C_SetMode(). */
uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
This parameter must be set by referring to the STM32CubeMX Tool and
the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
This feature can be modified afterwards using unitary function
@ref LL_I2C_SetTiming(). */
uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
This feature can be modified afterwards using unitary functions
@ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
uint32_t DigitalFilter; /*!< Configures the digital noise filter.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
This feature can be modified afterwards using unitary function
@ref LL_I2C_SetDigitalFilter(). */
uint32_t OwnAddress1; /*!< Specifies the device own address 1.
This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
This feature can be modified afterwards using unitary function
@ref LL_I2C_SetOwnAddress1(). */
uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
match code or next received byte.
This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
This feature can be modified afterwards using unitary function
@ref LL_I2C_AcknowledgeNextData(). */
uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
This feature can be modified afterwards using unitary function
@ref LL_I2C_SetOwnAddress1(). */
} LL_I2C_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_I2C_WriteReg function
* @{
*/
#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
/**
* @}
*/
/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_I2C_ReadReg function
* @{
*/
#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
/**
* @}
*/
/** @defgroup I2C_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
* @{
*/
#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
/**
* @}
*/
/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
* @{
*/
#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
(Default address not acknowledge) */
#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
/**
* @}
*/
/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
* @{
*/
#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
/**
* @}
*/
/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
* @{
*/
#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
* @{
*/
#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
* @{
*/
#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
All Address2 are acknowledged. */
/**
* @}
*/
/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
* @{
*/
#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
* @{
*/
#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
* @{
*/
#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
/**
* @}
*/
/** @defgroup I2C_LL_EC_MODE Transfer End Mode
* @{
*/
#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
with no HW PEC comparison. */
#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
with no HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
with HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
with HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
with HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
/*!< Enable SMBUS Software end mode with HW PEC comparison. */
/**
* @}
*/
/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
* @{
*/
#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
/*!< Don't Generate Stop and Start condition. */
#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
/*!< Generate Stop condition (Size should be set to 0). */
#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
/*!< Generate Start for read request. */
#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/*!< Generate Start for write request. */
#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
/*!< Generate Restart for read request, slave 7Bit address. */
#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/*!< Generate Restart for write request, slave 7Bit address. */
#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
/*!< Generate Restart for read request, slave 10Bit address. */
#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/*!< Generate Restart for write request, slave 10Bit address.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
* @{
*/
#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
slave enters receiver mode. */
#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
slave enters transmitter mode.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
transmission */
#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
reception */
/**
* @}
*/
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
* @{
*/
#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
SCL low level timeout. */
#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
both SCL and SDA high level timeout.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
* @{
*/
#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
enable bit */
#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
(extended clock) enable bits */
/**
* @}
*/
/** @defgroup I2C_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
* @brief I2C Autonomous Trigger selection
* @{
*/
#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2 and I2C4 */
#define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */
#define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U))
/*!< HW Trigger signal is GPDMA_CH0_TRG */
#define LL_I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH1_TRG */
#define LL_I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH2_TRG */
#define LL_I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH3_TRG */
#define LL_I2C_GRP1_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI5_TRG */
#define LL_I2C_GRP1_EXTI9_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI9_TRG */
#define LL_I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM1_CH1_TRG */
#define LL_I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM2_CH1_TRG */
#define LL_I2C_GRP1_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP1_TRG */
#define LL_I2C_GRP1_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP2_TRG */
#define LL_I2C_GRP1_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_ALRA_TRG */
#define LL_I2C_GRP1_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_WUT_TRG */
#define LL_I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x00000000U))
/*!< HW Trigger signal is LPDMA_CH0_TRG */
#define LL_I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPDMA_CH1_TRG */
#define LL_I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPDMA_CH2_TRG */
#define LL_I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPDMA_CH3_TRG */
#define LL_I2C_GRP2_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI5_TRG */
#define LL_I2C_GRP2_EXTI8_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI8_TRG */
#define LL_I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM1_CH1_TRG */
#define LL_I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM3_CH1_TRG */
#define LL_I2C_GRP2_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP1_TRG */
#define LL_I2C_GRP2_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP2_TRG */
#define LL_I2C_GRP2_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_ALRA_TRG */
#define LL_I2C_GRP2_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_WUT_TRG */
/**
* @}
*/
/** @defgroup I2C_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
* @brief I2C Autonomous Trigger Polarity
* @{
*/
#define LL_I2C_TRIG_POLARITY_RISING 0x00000000U /*!< I2C triggered on rising edge */
#define LL_I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C triggered on falling edge */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
* @{
*/
/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in I2C register
* @param __INSTANCE__ I2C Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in I2C register
* @param __INSTANCE__ I2C Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
* @{
*/
/**
* @brief Configure the SDA setup, hold time and the SCL high, low period.
* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
* @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
(tscldel = (SCLDEL+1)xtpresc)
* @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
(tsdadel = SDADELxtpresc)
* @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
(tsclh = (SCLH+1)xtpresc)
* @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
(tscll = (SCLL+1)xtpresc)
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
(((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
(((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
(((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
(((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
* @{
*/
/** @defgroup I2C_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable I2C peripheral (PE = 1).
* @rmtoll CR1 PE LL_I2C_Enable
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_PE);
}
/**
* @brief Disable I2C peripheral (PE = 0).
* @note When PE = 0, the I2C SCL and SDA lines are released.
* Internal state machines and status bits are put back to their reset value.
* When cleared, PE must be kept low for at least 3 APB clock cycles.
* @rmtoll CR1 PE LL_I2C_Disable
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
}
/**
* @brief Check if the I2C peripheral is enabled or disabled.
* @rmtoll CR1 PE LL_I2C_IsEnabled
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
}
/**
* @brief Configure Noise Filters (Analog and Digital).
* @note If the analog filter is also enabled, the digital filter is added to analog filter.
* The filters can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
* CR1 DNF LL_I2C_ConfigFilters
* @param I2Cx I2C Instance.
* @param AnalogFilter This parameter can be one of the following values:
* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
* This parameter is used to configure the digital noise filter on SDA and SCL input.
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
{
MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
}
/**
* @brief Configure Digital Noise Filter.
* @note If the analog filter is also enabled, the digital filter is added to analog filter.
* This filter can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
* @param I2Cx I2C Instance.
* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
* This parameter is used to configure the digital noise filter on SDA and SCL input.
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
{
MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
}
/**
* @brief Get the current Digital Noise Filter configuration.
* @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
}
/**
* @brief Enable Analog Noise Filter.
* @note This filter can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
}
/**
* @brief Disable Analog Noise Filter.
* @note This filter can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
}
/**
* @brief Check if Analog Noise Filter is enabled or disabled.
* @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA transmission requests.
* @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
}
/**
* @brief Disable DMA transmission requests.
* @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
}
/**
* @brief Check if DMA transmission requests are enabled or disabled.
* @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA reception requests.
* @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
}
/**
* @brief Disable DMA reception requests.
* @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
}
/**
* @brief Check if DMA reception requests are enabled or disabled.
* @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Get the data register address used for DMA transfer
* @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
* RXDR RXDATA LL_I2C_DMA_GetRegAddr
* @param I2Cx I2C Instance
* @param Direction This parameter can be one of the following values:
* @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
{
uint32_t data_reg_addr;
if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
{
/* return address of TXDR register */
data_reg_addr = (uint32_t) &(I2Cx->TXDR);
}
else
{
/* return address of RXDR register */
data_reg_addr = (uint32_t) &(I2Cx->RXDR);
}
return data_reg_addr;
}
/**
* @brief Enable Clock stretching.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
}
/**
* @brief Disable Clock stretching.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
}
/**
* @brief Check if Clock stretching is enabled or disabled.
* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
}
/**
* @brief Enable hardware byte control in slave mode.
* @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
}
/**
* @brief Disable hardware byte control in slave mode.
* @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
}
/**
* @brief Check if hardware byte control in slave mode is enabled or disabled.
* @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
}
/**
* @brief Enable Wakeup from STOP.
* @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when Digital Filter is disabled.
* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
}
/**
* @brief Disable Wakeup from STOP.
* @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
}
/**
* @brief Check if Wakeup from STOP is enabled or disabled.
* @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
}
/**
* @brief Enable General Call.
* @note When enabled the Address 0x00 is ACKed.
* @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
}
/**
* @brief Disable General Call.
* @note When disabled the Address 0x00 is NACKed.
* @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
}
/**
* @brief Check if General Call is enabled or disabled.
* @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
}
/**
* @brief Enable I2C Fast Mode Plus (FMP = 1).
* @note 20mA I/O drive enable
* @rmtoll CR1 FMP LL_I2C_EnableFastModePlus
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_FMP);
}
/**
* @brief Disable I2C Fast Mode Plus (FMP = 0).
* @note 20mA I/O drive disable
* @rmtoll CR1 FMP LL_I2C_DisableFastModePlus
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP);
}
/**
* @brief Check if the I2C Fast Mode Plus is enabled or disabled.
* @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL);
}
/**
* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
* @note Changing this bit is not allowed, when the START bit is set.
* @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
* @param I2Cx I2C Instance.
* @param AddressingMode This parameter can be one of the following values:
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
}
/**
* @brief Get the Master addressing mode.
* @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
*/
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
}
/**
* @brief Set the Own Address1.
* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
* OAR1 OA1MODE LL_I2C_SetOwnAddress1
* @param I2Cx I2C Instance.
* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
* @param OwnAddrSize This parameter can be one of the following values:
* @arg @ref LL_I2C_OWNADDRESS1_7BIT
* @arg @ref LL_I2C_OWNADDRESS1_10BIT
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
{
MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
}
/**
* @brief Enable acknowledge on Own Address1 match address.
* @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
}
/**
* @brief Disable acknowledge on Own Address1 match address.
* @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
}
/**
* @brief Check if Own Address1 acknowledge is enabled or disabled.
* @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
}
/**
* @brief Set the 7bits Own Address2.
* @note This action has no effect if own address2 is enabled.
* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
* OAR2 OA2MSK LL_I2C_SetOwnAddress2
* @param I2Cx I2C Instance.
* @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
* @param OwnAddrMask This parameter can be one of the following values:
* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
* @arg @ref LL_I2C_OWNADDRESS2_MASK01
* @arg @ref LL_I2C_OWNADDRESS2_MASK02
* @arg @ref LL_I2C_OWNADDRESS2_MASK03
* @arg @ref LL_I2C_OWNADDRESS2_MASK04
* @arg @ref LL_I2C_OWNADDRESS2_MASK05
* @arg @ref LL_I2C_OWNADDRESS2_MASK06
* @arg @ref LL_I2C_OWNADDRESS2_MASK07
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
{
MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
}
/**
* @brief Enable acknowledge on Own Address2 match address.
* @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
}
/**
* @brief Disable acknowledge on Own Address2 match address.
* @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
}
/**
* @brief Check if Own Address1 acknowledge is enabled or disabled.
* @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
}
/**
* @brief Configure the SDA setup, hold time and the SCL high, low period.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
* @param I2Cx I2C Instance.
* @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
* @note This parameter is computed with the STM32CubeMX Tool.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
{
WRITE_REG(I2Cx->TIMINGR, Timing);
}
/**
* @brief Get the Timing Prescaler setting.
* @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
}
/**
* @brief Get the SCL low period setting.
* @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
}
/**
* @brief Get the SCL high period setting.
* @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
}
/**
* @brief Get the SDA hold time.
* @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
}
/**
* @brief Get the SDA setup time.
* @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
}
/**
* @brief Configure peripheral mode.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
* CR1 SMBDEN LL_I2C_SetMode
* @param I2Cx I2C Instance.
* @param PeripheralMode This parameter can be one of the following values:
* @arg @ref LL_I2C_MODE_I2C
* @arg @ref LL_I2C_MODE_SMBUS_HOST
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
{
MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
}
/**
* @brief Get peripheral mode.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
* CR1 SMBDEN LL_I2C_GetMode
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_MODE_I2C
* @arg @ref LL_I2C_MODE_SMBUS_HOST
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
*/
__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
}
/**
* @brief Enable SMBus alert (Host or Device mode)
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is drived low and
* Alert Response Address Header acknowledge is enabled.
* SMBus Host mode:
* - SMBus Alert pin management is supported.
* @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
}
/**
* @brief Disable SMBus alert (Host or Device mode)
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
* Alert Response Address Header acknowledge is disabled.
* SMBus Host mode:
* - SMBus Alert pin management is not supported.
* @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
}
/**
* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
}
/**
* @brief Enable SMBus Packet Error Calculation (PEC).
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
}
/**
* @brief Disable SMBus Packet Error Calculation (PEC).
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
}
/**
* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
}
/**
* @brief Configure the SMBus Clock Timeout.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
* TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
* TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
* @param I2Cx I2C Instance.
* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
* @param TimeoutAMode This parameter can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
* @param TimeoutB
* @retval None
*/
__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
uint32_t TimeoutB)
{
MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
}
/**
* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
* @param I2Cx I2C Instance.
* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
{
WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
}
/**
* @brief Get the SMBus Clock TimeoutA setting.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
}
/**
* @brief Set the SMBus Clock TimeoutA mode.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
* @param I2Cx I2C Instance.
* @param TimeoutAMode This parameter can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
{
WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
}
/**
* @brief Get the SMBus Clock TimeoutA mode.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
*/
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
}
/**
* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutB is disabled.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
* @param I2Cx I2C Instance.
* @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
{
WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
}
/**
* @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
}
/**
* @brief Enable the SMBus Clock Timeout.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
* @param I2Cx I2C Instance.
* @param ClockTimeout This parameter can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA
* @arg @ref LL_I2C_SMBUS_TIMEOUTB
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
}
/**
* @brief Disable the SMBus Clock Timeout.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
* @param I2Cx I2C Instance.
* @param ClockTimeout This parameter can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA
* @arg @ref LL_I2C_SMBUS_TIMEOUTB
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
}
/**
* @brief Check if the SMBus Clock Timeout is enabled or disabled.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
* @param I2Cx I2C Instance.
* @param ClockTimeout This parameter can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA
* @arg @ref LL_I2C_SMBUS_TIMEOUTB
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
(ClockTimeout)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup I2C_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable TXIS interrupt.
* @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
}
/**
* @brief Disable TXIS interrupt.
* @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
}
/**
* @brief Check if the TXIS Interrupt is enabled or disabled.
* @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
}
/**
* @brief Enable RXNE interrupt.
* @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
}
/**
* @brief Disable RXNE interrupt.
* @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
}
/**
* @brief Check if the RXNE Interrupt is enabled or disabled.
* @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Address match interrupt (slave mode only).
* @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
}
/**
* @brief Disable Address match interrupt (slave mode only).
* @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
}
/**
* @brief Check if Address match interrupt is enabled or disabled.
* @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Not acknowledge received interrupt.
* @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
}
/**
* @brief Disable Not acknowledge received interrupt.
* @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
}
/**
* @brief Check if Not acknowledge received interrupt is enabled or disabled.
* @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
}
/**
* @brief Enable STOP detection interrupt.
* @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
}
/**
* @brief Disable STOP detection interrupt.
* @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
}
/**
* @brief Check if STOP detection interrupt is enabled or disabled.
* @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Transfer Complete interrupt.
* @note Any of these events will generate interrupt :
* Transfer Complete (TC)
* Transfer Complete Reload (TCR)
* @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
}
/**
* @brief Disable Transfer Complete interrupt.
* @note Any of these events will generate interrupt :
* Transfer Complete (TC)
* Transfer Complete Reload (TCR)
* @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
}
/**
* @brief Check if Transfer Complete interrupt is enabled or disabled.
* @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Error interrupts.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
* Bus Error detection (BERR)
* Overrun/Underrun (OVR)
* SMBus Timeout detection (TIMEOUT)
* SMBus PEC error detection (PECERR)
* SMBus Alert pin event detection (ALERT)
* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
}
/**
* @brief Disable Error interrupts.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
* Bus Error detection (BERR)
* Overrun/Underrun (OVR)
* SMBus Timeout detection (TIMEOUT)
* SMBus PEC error detection (PECERR)
* SMBus Alert pin event detection (ALERT)
* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
}
/**
* @brief Check if Error interrupts are enabled or disabled.
* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
* @{
*/
/**
* @brief Indicate the status of Transmit data register empty flag.
* @note RESET: When next data is written in Transmit data register.
* SET: When Transmit data register is empty.
* @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Transmit interrupt flag.
* @note RESET: When next data is written in Transmit data register.
* SET: When Transmit data register is empty.
* @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Receive data register not empty flag.
* @note RESET: When Receive data register is read.
* SET: When the received data is copied in Receive data register.
* @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Address matched flag (slave mode).
* @note RESET: Clear default value.
* SET: When the received slave address matched with one of the enabled slave address.
* @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Not Acknowledge received flag.
* @note RESET: Clear default value.
* SET: When a NACK is received after a byte transmission.
* @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Stop detection flag.
* @note RESET: Clear default value.
* SET: When a Stop condition is detected.
* @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Transfer complete flag (master mode).
* @note RESET: Clear default value.
* SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
* @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Transfer complete flag (master mode).
* @note RESET: Clear default value.
* SET: When RELOAD=1 and NBYTES date have been transferred.
* @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Bus error flag.
* @note RESET: Clear default value.
* SET: When a misplaced Start or Stop condition is detected.
* @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Arbitration lost flag.
* @note RESET: Clear default value.
* SET: When arbitration lost.
* @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Overrun/Underrun flag (slave mode).
* @note RESET: Clear default value.
* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
* @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of SMBus PEC error flag in reception.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When the received PEC does not match with the PEC register content.
* @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of SMBus Timeout detection flag.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When a timeout or extended clock timeout occurs.
* @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of SMBus alert flag.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When SMBus host configuration, SMBus alert enabled and
* a falling edge event occurs on SMBA pin.
* @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Bus Busy flag.
* @note RESET: Clear default value.
* SET: When a Start condition is detected.
* @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
}
/**
* @brief Clear Address Matched flag.
* @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
}
/**
* @brief Clear Not Acknowledge flag.
* @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
}
/**
* @brief Clear Stop detection flag.
* @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
}
/**
* @brief Clear Transmit data register empty flag (TXE).
* @note This bit can be clear by software in order to flush the transmit data register (TXDR).
* @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
{
WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
}
/**
* @brief Clear Bus error flag.
* @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
}
/**
* @brief Clear Arbitration lost flag.
* @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
}
/**
* @brief Clear Overrun/Underrun flag.
* @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
}
/**
* @brief Clear SMBus PEC error flag.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
}
/**
* @brief Clear SMBus Timeout detection flag.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
}
/**
* @brief Clear SMBus Alert flag.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
}
/**
* @}
*/
/** @defgroup I2C_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Enable automatic STOP condition generation (master mode).
* @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
* This bit has no effect in slave mode or when RELOAD bit is set.
* @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
}
/**
* @brief Disable automatic STOP condition generation (master mode).
* @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
* @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
}
/**
* @brief Check if automatic STOP condition is enabled or disabled.
* @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
}
/**
* @brief Enable reload mode (master mode).
* @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
* @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
}
/**
* @brief Disable reload mode (master mode).
* @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
* @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
}
/**
* @brief Check if reload mode is enabled or disabled.
* @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
}
/**
* @brief Configure the number of bytes for transfer.
* @note Changing these bits when START bit is set is not allowed.
* @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
* @param I2Cx I2C Instance.
* @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
}
/**
* @brief Get the number of bytes configured for transfer.
* @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
}
/**
* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
or next received byte.
* @note Usage in Slave mode only.
* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
* @param I2Cx I2C Instance.
* @param TypeAcknowledge This parameter can be one of the following values:
* @arg @ref LL_I2C_ACK
* @arg @ref LL_I2C_NACK
* @retval None
*/
__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
}
/**
* @brief Generate a START or RESTART condition
* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
* This action has no effect when RELOAD is set.
* @rmtoll CR2 START LL_I2C_GenerateStartCondition
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_START);
}
/**
* @brief Generate a STOP condition after the current byte transfer (master mode).
* @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
}
/**
* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
* @note The master sends the complete 10bit slave address read sequence :
* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
in Read direction.
* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
}
/**
* @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
* @note The master only sends the first 7 bits of 10bit address in Read direction.
* @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
}
/**
* @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
* @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
}
/**
* @brief Configure the transfer direction (master mode).
* @note Changing these bits when START bit is set is not allowed.
* @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
* @param I2Cx I2C Instance.
* @param TransferRequest This parameter can be one of the following values:
* @arg @ref LL_I2C_REQUEST_WRITE
* @arg @ref LL_I2C_REQUEST_READ
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
}
/**
* @brief Get the transfer direction requested (master mode).
* @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_REQUEST_WRITE
* @arg @ref LL_I2C_REQUEST_READ
*/
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
}
/**
* @brief Configure the slave address for transfer (master mode).
* @note Changing these bits when START bit is set is not allowed.
* @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
* @param I2Cx I2C Instance.
* @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
}
/**
* @brief Get the slave address programmed for transfer.
* @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0x3F
*/
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
}
/**
* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
* @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
* CR2 ADD10 LL_I2C_HandleTransfer\n
* CR2 RD_WRN LL_I2C_HandleTransfer\n
* CR2 START LL_I2C_HandleTransfer\n
* CR2 STOP LL_I2C_HandleTransfer\n
* CR2 RELOAD LL_I2C_HandleTransfer\n
* CR2 NBYTES LL_I2C_HandleTransfer\n
* CR2 AUTOEND LL_I2C_HandleTransfer\n
* CR2 HEAD10R LL_I2C_HandleTransfer
* @param I2Cx I2C Instance.
* @param SlaveAddr Specifies the slave address to be programmed.
* @param SlaveAddrSize This parameter can be one of the following values:
* @arg @ref LL_I2C_ADDRSLAVE_7BIT
* @arg @ref LL_I2C_ADDRSLAVE_10BIT
* @param TransferSize Specifies the number of bytes to be programmed.
* This parameter must be a value between Min_Data=0 and Max_Data=255.
* @param EndMode This parameter can be one of the following values:
* @arg @ref LL_I2C_MODE_RELOAD
* @arg @ref LL_I2C_MODE_AUTOEND
* @arg @ref LL_I2C_MODE_SOFTEND
* @arg @ref LL_I2C_MODE_SMBUS_RELOAD
* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
* @param Request This parameter can be one of the following values:
* @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
* @arg @ref LL_I2C_GENERATE_STOP
* @arg @ref LL_I2C_GENERATE_START_READ
* @arg @ref LL_I2C_GENERATE_START_WRITE
* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
* @retval None
*/
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
}
/**
* @brief Indicate the value of transfer direction (slave mode).
* @note RESET: Write transfer, Slave enters in receiver mode.
* SET: Read transfer, Slave enters in transmitter mode.
* @rmtoll ISR DIR LL_I2C_GetTransferDirection
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_DIRECTION_WRITE
* @arg @ref LL_I2C_DIRECTION_READ
*/
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
}
/**
* @brief Return the slave matched address.
* @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
*/
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
}
/**
* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
or an Address Matched is received.
* This bit has no effect when RELOAD bit is set.
* This bit has no effect in device mode when SBC bit is not set.
* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
}
/**
* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
}
/**
* @brief Get the SMBus Packet Error byte calculated.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
}
/**
* @brief Read Receive Data register.
* @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
{
return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
}
/**
* @brief Write in Transmit Data Register .
* @rmtoll TXDR TXDATA LL_I2C_TransmitData8
* @param I2Cx I2C Instance.
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
{
WRITE_REG(I2Cx->TXDR, Data);
}
/**
* @}
*/
/** @defgroup I2C_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature
* @{
*/
/**
* @brief Enable Selected Trigger
* @rmtoll AUTOCR TRIGEN LL_I2C_Enable_SelectedTrigger
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_Enable_SelectedTrigger(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN);
}
/**
* @brief Disable Selected Trigger
* @rmtoll AUTOCR TRIGEN LL_I2C_Disable_SelectedTrigger
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_Disable_SelectedTrigger(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN);
}
/**
* @brief Indicate if selected Trigger is disabled or enabled
* @rmtoll AUTOCR TRIGEN LL_I2C_IsEnabled_SelectedTrigger
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabled_SelectedTrigger(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN) == (I2C_AUTOCR_TRIGEN)) ? 1UL : 0UL);
}
/**
* @brief Set the trigger polarity
* @rmtoll AUTOCR TRIGPOL LL_I2C_SetTriggerPolarity
* @param I2Cx I2C Instance.
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_I2C_TRIG_POLARITY_RISING
* @arg @ref LL_I2C_TRIG_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetTriggerPolarity(I2C_TypeDef *I2Cx, uint32_t Polarity)
{
MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL, Polarity);
}
/**
* @brief Get the trigger polarity
* @rmtoll AUTOCR TRIGPOL LL_I2C_GetTriggerPolarity
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_TRIG_POLARITY_RISING
* @arg @ref LL_I2C_TRIG_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_I2C_GetTriggerPolarity(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL));
}
/**
* @brief Set the selected trigger
* @rmtoll AUTOCR TRIGSEL LL_I2C_SetSelectedTrigger
* @param I2Cx I2C Instance.
* @param Trigger This parameter can be one of the following values:
* @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG
* @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG
* @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG
* @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG
* @arg @ref LL_I2C_GRP1_EXTI5_TRG
* @arg @ref LL_I2C_GRP1_EXTI9_TRG
* @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG
* @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG
* @arg @ref LL_I2C_GRP1_COMP1_TRG
* @arg @ref LL_I2C_GRP1_COMP2_TRG
* @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG
* @arg @ref LL_I2C_GRP1_RTC_WUT_TRG
* @arg @ref LL_I2C_GRP2_LPDMA_CH0_TCF_TRG
* @arg @ref LL_I2C_GRP2_LPDMA_CH1_TCF_TRG
* @arg @ref LL_I2C_GRP2_LPDMA_CH2_TCF_TRG
* @arg @ref LL_I2C_GRP2_LPDMA_CH3_TCF_TRG
* @arg @ref LL_I2C_GRP2_EXTI5_TRG
* @arg @ref LL_I2C_GRP2_EXTI8_TRG
* @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG
* @arg @ref LL_I2C_GRP2_LPTIM3_CH1_TRG
* @arg @ref LL_I2C_GRP2_COMP1_TRG
* @arg @ref LL_I2C_GRP2_COMP2_TRG
* @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG
* @arg @ref LL_I2C_GRP2_RTC_WUT_TRG
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetSelectedTrigger(I2C_TypeDef *I2Cx, uint32_t Trigger)
{
MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL, (Trigger & I2C_AUTOCR_TRIGSEL_Msk));
}
/**
* @brief Get the selected trigger
* @rmtoll AUTOCR TRIGSEL LL_I2C_GetSelectedTrigger
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG
* @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG
* @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG
* @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG
* @arg @ref LL_I2C_GRP1_EXTI5_TRG
* @arg @ref LL_I2C_GRP1_EXTI9_TRG
* @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG
* @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG
* @arg @ref LL_I2C_GRP1_COMP1_TRG
* @arg @ref LL_I2C_GRP1_COMP2_TRG
* @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG
* @arg @ref LL_I2C_GRP1_RTC_WUT_TRG
* @arg @ref LL_I2C_GRP2_LPDMA_CH0_TCF_TRG
* @arg @ref LL_I2C_GRP2_LPDMA_CH1_TCF_TRG
* @arg @ref LL_I2C_GRP2_LPDMA_CH2_TCF_TRG
* @arg @ref LL_I2C_GRP2_LPDMA_CH3_TCF_TRG
* @arg @ref LL_I2C_GRP2_EXTI5_TRG
* @arg @ref LL_I2C_GRP2_EXTI8_TRG
* @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG
* @arg @ref LL_I2C_GRP2_LPTIM3_CH1_TRG
* @arg @ref LL_I2C_GRP2_COMP1_TRG
* @arg @ref LL_I2C_GRP2_COMP2_TRG
* @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG
* @arg @ref LL_I2C_GRP2_RTC_WUT_TRG
*/
__STATIC_INLINE uint32_t LL_I2C_GetSelectedTrigger(I2C_TypeDef *I2Cx)
{
if (IS_LL_I2C_GRP2_INSTANCE(I2Cx))
{
return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP2));
}
else
{
return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP1));
}
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_I2C_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h
|
C
|
apache-2.0
| 94,755
|
/**
******************************************************************************
* @file stm32u5xx_ll_icache.h
* @author MCD Application Team
* @brief Header file of ICACHE LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion ------------------------------------*/
#ifndef STM32U5xx_LL_ICACHE_H
#define STM32U5xx_LL_ICACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(ICACHE)
/** @defgroup ICACHE_LL ICACHE
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure
* @{
*/
/**
* @brief LL ICACHE region configuration structure definition
*/
typedef struct
{
uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */
uint32_t RemapAddress; /*!< Configures the remap address to be remapped */
uint32_t Size; /*!< Configures the region size.
This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */
uint32_t TrafficRoute; /*!< Selects the traffic route.
This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */
uint32_t OutputBurstType; /*!< Selects the output burst type.
This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */
} LL_ICACHE_RegionTypeDef;
/**
* @}
*/
/* Exported constants -------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
* @{
*/
/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
* @{
*/
#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
* @{
*/
#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */
#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */
#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_ICACHE_ReadReg function
* @{
*/
#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */
#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */
#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_ICACHE_WriteReg function
* @{
*/
#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */
#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions
* @{
*/
#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Region Remapped Region number
* @{
*/
#define LL_ICACHE_REGION_0 0U /*!< Region 0 */
#define LL_ICACHE_REGION_1 1U /*!< Region 1 */
#define LL_ICACHE_REGION_2 2U /*!< Region 2 */
#define LL_ICACHE_REGION_3 3U /*!< Region 3 */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size
* @{
*/
#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route
* @{
*/
#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */
#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type
* @{
*/
#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ----------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
* @{
*/
/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in ICACHE register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
/**
* @brief Read a value in ICACHE register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
* @{
*/
/** @defgroup ICACHE_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable the ICACHE.
* @rmtoll CR EN LL_ICACHE_Enable
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Enable(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_EN);
}
/**
* @brief Disable the ICACHE.
* @rmtoll CR EN LL_ICACHE_Disable
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Disable(void)
{
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
}
/**
* @brief Return if ICACHE is enabled or not.
* @rmtoll CR EN LL_ICACHE_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
{
return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
}
/**
* @brief Select the ICACHE operating mode.
* @rmtoll CR WAYSEL LL_ICACHE_SetMode
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_ICACHE_1WAY
* @arg @ref LL_ICACHE_2WAYS
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
{
MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
}
/**
* @brief Get the selected ICACHE operating mode.
* @rmtoll CR WAYSEL LL_ICACHE_GetMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_1WAY
* @arg @ref LL_ICACHE_2WAYS
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
{
return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
}
/**
* @brief Invalidate the ICACHE.
* @note Until the BSYEND flag is set, the cache is bypassed.
* @rmtoll CR CACHEINV LL_ICACHE_Invalidate
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Invalidate(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_Monitors Monitors
* @{
*/
/**
* @brief Enable the hit/miss monitor(s).
* @rmtoll CR HITMEN LL_ICACHE_EnableMonitors
* @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
{
SET_BIT(ICACHE->CR, Monitors);
}
/**
* @brief Disable the hit/miss monitor(s).
* @rmtoll CR HITMEN LL_ICACHE_DisableMonitors
* @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
{
CLEAR_BIT(ICACHE->CR, Monitors);
}
/**
* @brief Check if the monitor(s) is(are) enabled or disabled.
* @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors
* @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval State of parameter value (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
{
return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
}
/**
* @brief Reset the hit/miss monitor(s).
* @rmtoll CR HITMRST LL_ICACHE_ResetMonitors
* @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
{
/* Reset */
SET_BIT(ICACHE->CR, (Monitors << 2U));
/* Release reset */
CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
}
/**
* @brief Get the Hit monitor.
* @note Upon reaching the 32-bit maximum value, hit monitor does not wrap.
* @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
{
return (ICACHE->HMONR);
}
/**
* @brief Get the Miss monitor.
* @note Upon reaching the 16-bit maximum value, miss monitor does not wrap.
* @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
{
return (ICACHE->MMONR);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable BSYEND interrupt.
* @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
{
SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
}
/**
* @brief Disable BSYEND interrupt.
* @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
{
CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
}
/**
* @brief Check if the BSYEND Interrupt is enabled or disabled.
* @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
{
return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
}
/**
* @brief Enable ERR interrupt.
* @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
{
SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
}
/**
* @brief Disable ERR interrupt.
* @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
{
CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
}
/**
* @brief Check if the ERR Interrupt is enabled or disabled.
* @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
{
return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Indicate the status of an ongoing operation flag.
* @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of an operation end flag.
* @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of an error flag.
* @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Clear busy end of operation flag.
* @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
{
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
}
/**
* @brief Clear error flag.
* @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
{
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management
* @{
*/
/**
* @brief Enable the remapped memory region.
* @note The region must have been already configured.
* @rmtoll CRRx REN LL_ICACHE_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region)
{
SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN);
}
/**
* @brief Disable the remapped memory region.
* @rmtoll CRRx REN LL_ICACHE_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region)
{
CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN);
}
/**
* @brief Return if remapped memory region is enabled or not.
* @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region)
{
return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL);
}
/**
* @brief Select the memory remapped region base address.
* @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Address Alias address in the Code region
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_BASEADDR, (((Address & 0x1FFFFFFFU) >> 21U) & ICACHE_CRRx_BASEADDR));
}
/**
* @brief Get the memory remapped region base address.
* @note The base address is the alias in the Code region.
* @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Address Alias address in the Code region
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_BASEADDR));
}
/**
* @brief Select the memory remapped region remap address.
* @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Address External memory address
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos));
}
/**
* @brief Get the memory remapped region base address.
* @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Address External memory address
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region)
{
return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U);
}
/**
* @brief Select the memory remapped region size.
* @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Size This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGIONSIZE_2MB
* @arg @ref LL_ICACHE_REGIONSIZE_4MB
* @arg @ref LL_ICACHE_REGIONSIZE_8MB
* @arg @ref LL_ICACHE_REGIONSIZE_16MB
* @arg @ref LL_ICACHE_REGIONSIZE_32MB
* @arg @ref LL_ICACHE_REGIONSIZE_64MB
* @arg @ref LL_ICACHE_REGIONSIZE_128MB
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos));
}
/**
* @brief Get the selected the memory remapped region size.
* @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_REGIONSIZE_2MB
* @arg @ref LL_ICACHE_REGIONSIZE_4MB
* @arg @ref LL_ICACHE_REGIONSIZE_8MB
* @arg @ref LL_ICACHE_REGIONSIZE_16MB
* @arg @ref LL_ICACHE_REGIONSIZE_32MB
* @arg @ref LL_ICACHE_REGIONSIZE_64MB
* @arg @ref LL_ICACHE_REGIONSIZE_128MB
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos);
}
/**
* @brief Select the memory remapped region output burst type.
* @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Type This parameter can be one of the following values:
* @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
* @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_HBURST, Type);
}
/**
* @brief Get the selected the memory remapped region output burst type.
* @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
* @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_HBURST));
}
/**
* @brief Select the memory remapped region cache master port.
* @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Port This parameter can be one of the following values:
* @arg @ref LL_ICACHE_MASTER1_PORT
* @arg @ref LL_ICACHE_MASTER2_PORT
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_MSTSEL, Port);
}
/**
* @brief Get the selected the memory remapped region cache master port.
* @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_MASTER1_PORT
* @arg @ref LL_ICACHE_MASTER2_PORT
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_MSTSEL));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions
* @{
*/
void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_ICACHE_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h
|
C
|
apache-2.0
| 24,584
|
/**
******************************************************************************
* @file stm32u5xx_ll_iwdg.h
* @author MCD Application Team
* @brief Header file of IWDG LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_IWDG_H
#define STM32U5xx_LL_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(IWDG)
/** @defgroup IWDG_LL IWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
* @{
*/
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
* @{
*/
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
/**
* @}
*/
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
* @{
*/
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
#define LL_IWDG_PRESCALER_512 (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 512 */
#define LL_IWDG_PRESCALER_1024 IWDG_PR_PR_3 /*!< Divider by 1024 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
* @{
*/
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Start the Independent Watchdog
* @note Except if the hardware watchdog option is selected
* @rmtoll KR KEY LL_IWDG_Enable
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* @rmtoll KR KEY LL_IWDG_ReloadCounter
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
}
/**
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
}
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
}
/**
* @brief Select the prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_SetPrescaler
* @param IWDGx IWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
* @arg @ref LL_IWDG_PRESCALER_512
* @arg @ref LL_IWDG_PRESCALER_1024
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
{
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
}
/**
* @brief Get the selected prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_GetPrescaler
* @param IWDGx IWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
* @arg @ref LL_IWDG_PRESCALER_512
* @arg @ref LL_IWDG_PRESCALER_1024
*/
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->PR));
}
/**
* @brief Specify the IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
* @param IWDGx IWDG Instance
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
{
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
}
/**
* @brief Get the specified IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->RLR));
}
/**
* @brief Specify high limit of the window value to be compared to the down-counter.
* @rmtoll WINR WIN LL_IWDG_SetWindow
* @param IWDGx IWDG Instance
* @param Window Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
{
WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
}
/**
* @brief Get the high limit of the window value specified.
* @rmtoll WINR WIN LL_IWDG_GetWindow
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->WINR));
}
/**
* @}
*/
/** @defgroup IWDG_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Specify comparator value that will be used to trig Early Wakeup interrupt
* @rmtoll EWCR EWIT LL_IWDG_SetEwiTime
* @param IWDGx IWDG Instance
* @param Time Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetEwiTime(IWDG_TypeDef *IWDGx, uint32_t Time)
{
MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time);
}
/**
* @brief Get the Early Wakeup interrupt comparator value
* @rmtoll EWCR EWIT LL_IWDG_GetEwiTime
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetEwiTime(IWDG_TypeDef *IWDGx)
{
return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT));
}
/**
* @brief Enable Early wakeup interrupt
* @rmtoll EWCR EWIE LL_IWDG_EnableIT_EWI
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_EnableIT_EWI(IWDG_TypeDef *IWDGx)
{
SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE);
}
/**
* @brief Disable Early wakeup interrupt
* @rmtoll EWCR EWIE LL_IWDG_DisableIT_EWI
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_DisableIT_EWI(IWDG_TypeDef *IWDGx)
{
CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE);
}
/**
* @brief Indicates whether Early wakeup interrupt is enable
* @rmtoll EWCR EWIE LL_IWDG_IsEnabledIT_EWI
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_IWDG_IsEnabledIT_EWI(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if flag Prescaler Value Update is set or not
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flag Reload Value Update is set or not
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flag Window Value Update is set or not
* @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flag EWI Value Update is set or not
* @rmtoll SR EVU LL_IWDG_IsActiveFlag_EWU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWU(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_EWU) == (IWDG_SR_EWU)) ? 1UL : 0UL);
}
/**
* @brief Check if all flags Prescaler, Reload, Window & Early Interrupt Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
* SR RVU LL_IWDG_IsReady\n
* SR WVU LL_IWDG_IsReady\n
* SR EWU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | IWDG_SR_EWU) == 0U) ? 1UL : 0UL);
}
/**
* @brief Check if Early Wakeup interrupt flag is set or not
* @rmtoll SR EWIF LL_IWDG_IsActiveFlag_EWIF
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWIF(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_EWIF) == (IWDG_SR_EWIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Early Wakeup interrupt flag
* @rmtoll EWCR EWIC LL_IWDG_ClearFlag_EWIF
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_ClearFlag_EWIF(IWDG_TypeDef *IWDGx)
{
SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* IWDG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_IWDG_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_iwdg.h
|
C
|
apache-2.0
| 13,587
|
/**
******************************************************************************
* @file stm32u5xx_ll_lpgpio.h
* @author MCD Application Team
* @brief Header file of LPGPIO LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_LPGPIO_H
#define STM32U5xx_LL_LPGPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (LPGPIO1)
/** @defgroup LPGPIO_LL LPGPIO
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPGPIO_LL_Private_Macros LPGPIO Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPGPIO_LL_ES_INIT LPGPIO Exported Init structures
* @{
*/
/**
* @brief LL LPGPIO Init Structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the LPGPIO pins to be configured.
This parameter can be any value of @ref LPGPIO_LL_EC_PIN */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref LPGPIO_LL_EC_MODE.*/
} LL_LPGPIO_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup LPGPIO_LL_Exported_Constants LPGPIO Exported Constants
* @{
*/
/** @defgroup LPGPIO_LL_EC_PIN PIN
* @{
*/
#define LL_LPGPIO_PIN_0 LPGPIO_BSRR_BS0 /*!< Select pin 0 */
#define LL_LPGPIO_PIN_1 LPGPIO_BSRR_BS1 /*!< Select pin 1 */
#define LL_LPGPIO_PIN_2 LPGPIO_BSRR_BS2 /*!< Select pin 2 */
#define LL_LPGPIO_PIN_3 LPGPIO_BSRR_BS3 /*!< Select pin 3 */
#define LL_LPGPIO_PIN_4 LPGPIO_BSRR_BS4 /*!< Select pin 4 */
#define LL_LPGPIO_PIN_5 LPGPIO_BSRR_BS5 /*!< Select pin 5 */
#define LL_LPGPIO_PIN_6 LPGPIO_BSRR_BS6 /*!< Select pin 6 */
#define LL_LPGPIO_PIN_7 LPGPIO_BSRR_BS7 /*!< Select pin 7 */
#define LL_LPGPIO_PIN_8 LPGPIO_BSRR_BS8 /*!< Select pin 8 */
#define LL_LPGPIO_PIN_9 LPGPIO_BSRR_BS9 /*!< Select pin 9 */
#define LL_LPGPIO_PIN_10 LPGPIO_BSRR_BS10 /*!< Select pin 10 */
#define LL_LPGPIO_PIN_11 LPGPIO_BSRR_BS11 /*!< Select pin 11 */
#define LL_LPGPIO_PIN_12 LPGPIO_BSRR_BS12 /*!< Select pin 12 */
#define LL_LPGPIO_PIN_13 LPGPIO_BSRR_BS13 /*!< Select pin 13 */
#define LL_LPGPIO_PIN_14 LPGPIO_BSRR_BS14 /*!< Select pin 14 */
#define LL_LPGPIO_PIN_15 LPGPIO_BSRR_BS15 /*!< Select pin 15 */
#define LL_LPGPIO_PIN_ALL (LPGPIO_BSRR_BS0 | LPGPIO_BSRR_BS1 | LPGPIO_BSRR_BS2 | \
LPGPIO_BSRR_BS3 | LPGPIO_BSRR_BS4 | LPGPIO_BSRR_BS5 | \
LPGPIO_BSRR_BS6 | LPGPIO_BSRR_BS7 | LPGPIO_BSRR_BS8 | \
LPGPIO_BSRR_BS9 | LPGPIO_BSRR_BS10 | LPGPIO_BSRR_BS11 | \
LPGPIO_BSRR_BS12 | LPGPIO_BSRR_BS13 | LPGPIO_BSRR_BS14 | \
LPGPIO_BSRR_BS15) /*!< Select all pins */
/**
* @}
*/
/** @defgroup LPGPIO_LL_EC_MODE Mode
* @{
*/
#define LL_LPGPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
#define LL_LPGPIO_MODE_OUTPUT LPGPIO_MODER_MOD0 /*!< Select output mode */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LPGPIO_LL_Exported_Macros LPGPIO Exported Macros
* @{
*/
/** @defgroup LPGPIO_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in LPGPIO register
* @param __INSTANCE__ LPGPIO Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_LPGPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in LPGPIO register
* @param __INSTANCE__ LPGPIO Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_LPGPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPGPIO_LL_Exported_Functions LPGPIO Exported Functions
* @{
*/
/** @defgroup LPGPIO_LL_EF_Port_Configuration Port Configuration
* @{
*/
/**
* @brief Configure lpgpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_LPGPIO_SetPinMode
* @param LPGPIOx LPGPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_LPGPIO_PIN_0
* @arg @ref LL_LPGPIO_PIN_1
* @arg @ref LL_LPGPIO_PIN_2
* @arg @ref LL_LPGPIO_PIN_3
* @arg @ref LL_LPGPIO_PIN_4
* @arg @ref LL_LPGPIO_PIN_5
* @arg @ref LL_LPGPIO_PIN_6
* @arg @ref LL_LPGPIO_PIN_7
* @arg @ref LL_LPGPIO_PIN_8
* @arg @ref LL_LPGPIO_PIN_9
* @arg @ref LL_LPGPIO_PIN_10
* @arg @ref LL_LPGPIO_PIN_11
* @arg @ref LL_LPGPIO_PIN_12
* @arg @ref LL_LPGPIO_PIN_13
* @arg @ref LL_LPGPIO_PIN_14
* @arg @ref LL_LPGPIO_PIN_15
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_LPGPIO_MODE_INPUT
* @arg @ref LL_LPGPIO_MODE_OUTPUT
* @retval None
*/
__STATIC_INLINE void LL_LPGPIO_SetPinMode(GPIO_TypeDef *LPGPIOx, uint32_t Pin, uint32_t Mode)
{
MODIFY_REG(LPGPIOx->MODER, (LPGPIO_MODER_MOD0 << (POSITION_VAL(Pin))), (Mode << (POSITION_VAL(Pin))));
}
/**
* @brief Return lpgpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_LPGPIO_GetPinMode
* @param LPGPIOx LPGPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_LPGPIO_PIN_0
* @arg @ref LL_LPGPIO_PIN_1
* @arg @ref LL_LPGPIO_PIN_2
* @arg @ref LL_LPGPIO_PIN_3
* @arg @ref LL_LPGPIO_PIN_4
* @arg @ref LL_LPGPIO_PIN_5
* @arg @ref LL_LPGPIO_PIN_6
* @arg @ref LL_LPGPIO_PIN_7
* @arg @ref LL_LPGPIO_PIN_8
* @arg @ref LL_LPGPIO_PIN_9
* @arg @ref LL_LPGPIO_PIN_10
* @arg @ref LL_LPGPIO_PIN_11
* @arg @ref LL_LPGPIO_PIN_12
* @arg @ref LL_LPGPIO_PIN_13
* @arg @ref LL_LPGPIO_PIN_14
* @arg @ref LL_LPGPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPGPIO_MODE_INPUT
* @arg @ref LL_LPGPIO_MODE_OUTPUT
*/
__STATIC_INLINE uint32_t LL_LPGPIO_GetPinMode(GPIO_TypeDef *LPGPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(LPGPIOx->MODER,
(LPGPIO_MODER_MOD0 << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin)));
}
/**
* @}
*/
/** @defgroup LPGPIO_LL_EF_Data_Access Data Access
* @{
*/
/**
* @brief Return full input data register value for a dedicated port.
* @rmtoll IDR IDy LL_LPGPIO_ReadInputPort
* @param LPGPIOx LPGPIO Port
* @retval Input data register value of port
*/
__STATIC_INLINE uint32_t LL_LPGPIO_ReadInputPort(GPIO_TypeDef *LPGPIOx)
{
return (uint32_t)(READ_REG(LPGPIOx->IDR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll IDR IDy LL_LPGPIO_IsInputPinSet
* @param LPGPIOx LPGPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_LPGPIO_PIN_0
* @arg @ref LL_LPGPIO_PIN_1
* @arg @ref LL_LPGPIO_PIN_2
* @arg @ref LL_LPGPIO_PIN_3
* @arg @ref LL_LPGPIO_PIN_4
* @arg @ref LL_LPGPIO_PIN_5
* @arg @ref LL_LPGPIO_PIN_6
* @arg @ref LL_LPGPIO_PIN_7
* @arg @ref LL_LPGPIO_PIN_8
* @arg @ref LL_LPGPIO_PIN_9
* @arg @ref LL_LPGPIO_PIN_10
* @arg @ref LL_LPGPIO_PIN_11
* @arg @ref LL_LPGPIO_PIN_12
* @arg @ref LL_LPGPIO_PIN_13
* @arg @ref LL_LPGPIO_PIN_14
* @arg @ref LL_LPGPIO_PIN_15
* @arg @ref LL_LPGPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPGPIO_IsInputPinSet(GPIO_TypeDef *LPGPIOx, uint32_t PinMask)
{
return ((READ_BIT(LPGPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Write output data register for the port.
* @rmtoll ODR ODy LL_LPGPIO_WriteOutputPort
* @param LPGPIOx LPGPIO Port
* @param PortValue Level value for each pin of the port
* @retval None
*/
__STATIC_INLINE void LL_LPGPIO_WriteOutputPort(GPIO_TypeDef *LPGPIOx, uint32_t PortValue)
{
WRITE_REG(LPGPIOx->ODR, PortValue);
}
/**
* @brief Return full output data register value for a dedicated port.
* @rmtoll ODR ODy LL_LPGPIO_ReadOutputPort
* @param LPGPIOx LPGPIO Port
* @retval Output data register value of port
*/
__STATIC_INLINE uint32_t LL_LPGPIO_ReadOutputPort(GPIO_TypeDef *LPGPIOx)
{
return (uint32_t)(READ_REG(LPGPIOx->ODR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll ODR ODy LL_LPGPIO_IsOutputPinSet
* @param LPGPIOx LPGPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_LPGPIO_PIN_0
* @arg @ref LL_LPGPIO_PIN_1
* @arg @ref LL_LPGPIO_PIN_2
* @arg @ref LL_LPGPIO_PIN_3
* @arg @ref LL_LPGPIO_PIN_4
* @arg @ref LL_LPGPIO_PIN_5
* @arg @ref LL_LPGPIO_PIN_6
* @arg @ref LL_LPGPIO_PIN_7
* @arg @ref LL_LPGPIO_PIN_8
* @arg @ref LL_LPGPIO_PIN_9
* @arg @ref LL_LPGPIO_PIN_10
* @arg @ref LL_LPGPIO_PIN_11
* @arg @ref LL_LPGPIO_PIN_12
* @arg @ref LL_LPGPIO_PIN_13
* @arg @ref LL_LPGPIO_PIN_14
* @arg @ref LL_LPGPIO_PIN_15
* @arg @ref LL_LPGPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPGPIO_IsOutputPinSet(GPIO_TypeDef *LPGPIOx, uint32_t PinMask)
{
return ((READ_BIT(LPGPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Set several pins to high level on dedicated gpio port.
* @rmtoll BSRR BSy LL_LPGPIO_SetOutputPin
* @param LPGPIOx LPGPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_LPGPIO_PIN_0
* @arg @ref LL_LPGPIO_PIN_1
* @arg @ref LL_LPGPIO_PIN_2
* @arg @ref LL_LPGPIO_PIN_3
* @arg @ref LL_LPGPIO_PIN_4
* @arg @ref LL_LPGPIO_PIN_5
* @arg @ref LL_LPGPIO_PIN_6
* @arg @ref LL_LPGPIO_PIN_7
* @arg @ref LL_LPGPIO_PIN_8
* @arg @ref LL_LPGPIO_PIN_9
* @arg @ref LL_LPGPIO_PIN_10
* @arg @ref LL_LPGPIO_PIN_11
* @arg @ref LL_LPGPIO_PIN_12
* @arg @ref LL_LPGPIO_PIN_13
* @arg @ref LL_LPGPIO_PIN_14
* @arg @ref LL_LPGPIO_PIN_15
* @arg @ref LL_LPGPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_LPGPIO_SetOutputPin(GPIO_TypeDef *LPGPIOx, uint32_t PinMask)
{
WRITE_REG(LPGPIOx->BSRR, PinMask);
}
/**
* @brief Set several pins to low level on dedicated gpio port.
* @rmtoll BRR BRy LL_LPGPIO_ResetOutputPin
* @param LPGPIOx LPGPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_LPGPIO_PIN_0
* @arg @ref LL_LPGPIO_PIN_1
* @arg @ref LL_LPGPIO_PIN_2
* @arg @ref LL_LPGPIO_PIN_3
* @arg @ref LL_LPGPIO_PIN_4
* @arg @ref LL_LPGPIO_PIN_5
* @arg @ref LL_LPGPIO_PIN_6
* @arg @ref LL_LPGPIO_PIN_7
* @arg @ref LL_LPGPIO_PIN_8
* @arg @ref LL_LPGPIO_PIN_9
* @arg @ref LL_LPGPIO_PIN_10
* @arg @ref LL_LPGPIO_PIN_11
* @arg @ref LL_LPGPIO_PIN_12
* @arg @ref LL_LPGPIO_PIN_13
* @arg @ref LL_LPGPIO_PIN_14
* @arg @ref LL_LPGPIO_PIN_15
* @arg @ref LL_LPGPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_LPGPIO_ResetOutputPin(GPIO_TypeDef *LPGPIOx, uint32_t PinMask)
{
WRITE_REG(LPGPIOx->BRR, PinMask);
}
/**
* @brief Toggle data value for several pin of dedicated port.
* @rmtoll ODR ODy LL_LPGPIO_TogglePin
* @param LPGPIOx LPGPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_LPGPIO_PIN_0
* @arg @ref LL_LPGPIO_PIN_1
* @arg @ref LL_LPGPIO_PIN_2
* @arg @ref LL_LPGPIO_PIN_3
* @arg @ref LL_LPGPIO_PIN_4
* @arg @ref LL_LPGPIO_PIN_5
* @arg @ref LL_LPGPIO_PIN_6
* @arg @ref LL_LPGPIO_PIN_7
* @arg @ref LL_LPGPIO_PIN_8
* @arg @ref LL_LPGPIO_PIN_9
* @arg @ref LL_LPGPIO_PIN_10
* @arg @ref LL_LPGPIO_PIN_11
* @arg @ref LL_LPGPIO_PIN_12
* @arg @ref LL_LPGPIO_PIN_13
* @arg @ref LL_LPGPIO_PIN_14
* @arg @ref LL_LPGPIO_PIN_15
* @arg @ref LL_LPGPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_LPGPIO_TogglePin(GPIO_TypeDef *LPGPIOx, uint32_t PinMask)
{
WRITE_REG(LPGPIOx->ODR, READ_REG(LPGPIOx->ODR) ^ PinMask);
}
/**
* @}
*/
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_LPGPIO_DeInit(GPIO_TypeDef *LPGPIOx);
ErrorStatus LL_LPGPIO_Init(GPIO_TypeDef *LPGPIOx, const LL_LPGPIO_InitTypeDef *const LPGPIO_InitStruct);
void LL_LPGPIO_StructInit(LL_LPGPIO_InitTypeDef *LPGPIO_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
#endif /* defined (LPGPIO1) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_LPGPIO_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpgpio.h
|
C
|
apache-2.0
| 15,589
|
/**
******************************************************************************
* @file stm32u5xx_ll_lptim.h
* @author MCD Application Team
* @brief Header file of LPTIM LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_LPTIM_H
#define STM32U5xx_LL_LPTIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4)
/** @defgroup LPTIM_LL LPTIM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup LPTIM_LL_Private_variables LPTIM Private variables
* @{
*/
static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] =
{
0U, /* CC1P */
16U /* CC2P */
};
static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] =
{
0U, /* IC1F */
16U /* IC2F */
};
static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] =
{
0U, /* IC1PSC */
16U /* IC2PSC */
};
static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] =
{
0U, /* CC1SEL */
16U /* CC2SEL */
};
static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] =
{
LPTIM_CCMR1_CC1E_Pos, /* CC1E */
LPTIM_CCMR1_CC2E_Pos /* CC2E */
};
static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] =
{
{2, 7, 9, 13},
{3, 5, 6, 8},
{2, 3, 4, 5},
{2, 2, 3, 3},
{2, 2, 2, 2},
{2, 2, 2, 2},
{2, 2, 2, 2},
{2, 2, 2, 2}
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** Legacy definitions for compatibility purpose
@cond 0
*/
#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1
#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2
#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1
#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2
/**
@endcond
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
* @{
*/
/**
* @brief LPTIM Init structure definition
*/
typedef struct
{
uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
This feature can be modified afterwards using unitary
function @ref LL_LPTIM_SetClockSource().*/
uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
This feature can be modified afterwards using using unitary
function @ref LL_LPTIM_SetPrescaler().*/
uint32_t Waveform; /*!< Specifies the waveform shape.
This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
This feature can be modified afterwards using unitary
function @ref LL_LPTIM_SetWaveform().*/
} LL_LPTIM_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
* @{
*/
/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_LPTIM_ReadReg function
* @{
*/
#define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */
#define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */
#define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */
#define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */
#define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */
#define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */
#define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */
#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
#define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
#define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
* @{
*/
#define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */
#define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */
#define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */
#define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */
#define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */
#define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */
#define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */
#define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */
#define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */
#define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */
#define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */
#define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */
#define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
* @{
*/
#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
* @{
*/
#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
* @{
*/
#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
* @{
*/
#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
* @{
*/
#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CCRx registers*/
#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CCMR1_CC1P_0 /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CCx registers*/
/**
* @}
*/
/** @defgroup TIM_LL_EC_CHANNEL Channel
* @{
*/
#define LL_LPTIM_CHANNEL_CH1 0x00000000U /*!< LPTIM input/output channel 1 */
#define LL_LPTIM_CHANNEL_CH2 0x00000001U /*!< LPTIM input/output channel 2 */
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_LPTIM_IC_PRESCALER Input Capture Prescaler
* @{
*/
#define LL_LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */
#define LL_LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
#define LL_LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
#define LL_LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_LPTIM_IC_FILTER Input Capture Filter
* @{
*/
#define LL_LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */
#define LL_LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */
#define LL_LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */
#define LL_LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_LPTIM_IC_POLARITY Input Capture Polarity
* @{
*/
#define LL_LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */
#define LL_LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */
#define LL_LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_LPTIM_IC_Selection Input Capture selection
* @{
*/
#define LL_LPTIM_CCMODE_OUTPUT_PWM 0x00000000UL /*!< Select PWM mode */
#define LL_LPTIM_CCMODE_INPUTCAPTURE LPTIM_CCMR1_CC1SEL /*!< Select Input Capture mode*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
* @{
*/
#define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
* @{
*/
#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
#define LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPDMA CH0 transfer complete */
#define LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to LPDMA CH1 transfer complete */
#define LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPDMA CH2 transfer complete */
#define LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to GPDMA CH0 transfer complete */
#define LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to GPDMA CH4 transfer complete */
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
* @{
*/
#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
* @{
*/
#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
* @{
*/
#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
* @{
*/
#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
* @{
*/
#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
* @{
*/
#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
/**
* @}
*/
/** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
* @{
*/
#define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000UL /*!< For LPTIM1, LPTIM2, LPTIM3 and LPTIM4 */
#define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1, LPTIM2, LPTIM3 and LPTIM4 */
#define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM1 and LPTIM2 */
/**
* @}
*/
/** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
* @{
*/
#define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */
#define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 and LPTIM2 */
/**
* @}
*/
/** @defgroup LPTIM_EC_LPTIM1_IC1_RMP LPTIM1 Input Ch1 Remap
* @{
*/
#define LL_LPTIM_LPTIM1_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
#define LL_LPTIM_LPTIM1_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
#define LL_LPTIM_LPTIM1_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
/**
* @}
*/
/** @defgroup LPTIM_EC_LPTIM1_IC2_RMP LPTIM1 Input Ch2 Remap
* @{
*/
#define LL_LPTIM_LPTIM1_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
#define LL_LPTIM_LPTIM1_IC2_RMP_LSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to LSI */
#define LL_LPTIM_LPTIM1_IC2_RMP_LSE LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to LSE */
/**
* @}
*/
/** @defgroup LPTIM_EC_LPTIM2_IC1_RMP LPTIM2 Input Ch1 Remap
* @{
*/
#define LL_LPTIM_LPTIM2_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
#define LL_LPTIM_LPTIM2_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
#define LL_LPTIM_LPTIM2_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
/**
* @}
*/
/** @defgroup LPTIM_EC_LPTIM2_IC2_RMP LPTIM2 Input Ch2 Remap
* @{
*/
#define LL_LPTIM_LPTIM2_IC2_RMP_GPIO 0x00000000UL /*!< IC2 connected to GPIO */
#define LL_LPTIM_LPTIM2_IC2_RMP_HSI LPTIM_CFGR2_IC2SEL_0 /*!< IC2 connected to HSI */
#define LL_LPTIM_LPTIM2_IC2_RMP_MSIS_1024 LPTIM_CFGR2_IC2SEL_1 /*!< IC2 connected to MSIS/1024 */
#define LL_LPTIM_LPTIM2_IC2_RMP_MSIS_4 (LPTIM_CFGR2_IC2SEL_1|LPTIM_CFGR2_IC2SEL_0) /*!< IC2 connected to MSIS/4 */
/**
* @}
*/
/** @defgroup LPTIM_EC_LPTIM3_IC1_RMP LPTIM3 Input Ch1 Remap
* @{
*/
#define LL_LPTIM_LPTIM3_IC1_RMP_GPIO 0x00000000UL /*!< IC1 connected to GPIO */
#define LL_LPTIM_LPTIM3_IC1_RMP_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< IC1 connected to COMP1 */
#define LL_LPTIM_LPTIM3_IC1_RMP_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< IC1 connected to COMP2 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
* @{
*/
/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in LPTIM register
* @param __INSTANCE__ LPTIM Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in LPTIM register
* @param __INSTANCE__ LPTIM Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @brief LPTimer Input Capture Get Offset(in counter step unit)
* @note The real capture value corresponding to the input capture trigger can be calculated using
* the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
* The Offset value is depending on the glitch filter value for the channel
* and the value of the prescaler for the kernel clock.
* Please check Errata Sheet V1_8 for more details under "variable latency
* on input capture channel" section.
* @param __PSC__ This parameter can be one of the following values:
* @arg @ref LL_LPTIM_PRESCALER_DIV1
* @arg @ref LL_LPTIM_PRESCALER_DIV2
* @arg @ref LL_LPTIM_PRESCALER_DIV4
* @arg @ref LL_LPTIM_PRESCALER_DIV8
* @arg @ref LL_LPTIM_PRESCALER_DIV16
* @arg @ref LL_LPTIM_PRESCALER_DIV32
* @arg @ref LL_LPTIM_PRESCALER_DIV64
* @arg @ref LL_LPTIM_PRESCALER_DIV128
* @param __FLT__ This parameter can be one of the following values:
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
* @retval offset value
*/
#define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\
[((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\
[((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos]
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
* @{
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
* @{
*/
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
* @{
*/
/**
* @brief Enable the LPTIM instance
* @note After setting the ENABLE bit, a delay of two counter clock is needed
* before the LPTIM instance is actually enabled.
* @rmtoll CR ENABLE LL_LPTIM_Enable
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
}
/**
* @brief Disable the LPTIM instance
* @rmtoll CR ENABLE LL_LPTIM_Disable
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
}
/**
* @brief Indicates whether the LPTIM instance is enabled.
* @rmtoll CR ENABLE LL_LPTIM_IsEnabled
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
* @brief Starts the LPTIM counter in the desired mode.
* @note LPTIM instance must be enabled before starting the counter.
* @note It is possible to change on the fly from One Shot mode to
* Continuous mode.
* @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
* CR SNGSTRT LL_LPTIM_StartCounter
* @param LPTIMx Low-Power Timer instance
* @param OperatingMode This parameter can be one of the following values:
* @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
* @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
{
MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
}
/**
* @brief Enable reset after read.
* @note After calling this function any read access to LPTIM_CNT
* register will asynchronously reset the LPTIM_CNT register content.
* @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
}
/**
* @brief Disable reset after read.
* @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
}
/**
* @brief Indicate whether the reset after read feature is enabled.
* @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
}
/**
* @brief Reset of the LPTIM_CNT counter register (synchronous).
* @note Due to the synchronous nature of this reset, it only takes
* place after a synchronization delay of 3 LPTIM core clock cycles
* (LPTIM core clock may be different from APB clock).
* @note COUNTRST is automatically cleared by hardware
* @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
}
/**
* @brief Set the LPTIM registers update mode (enable/disable register preload)
* @note This function must be called when the LPTIM instance is disabled.
* @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
* @param LPTIMx Low-Power Timer instance
* @param UpdateMode This parameter can be one of the following values:
* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
}
/**
* @brief Get the LPTIM registers update mode
* @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
}
/**
* @brief Set the auto reload value
* @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
* @note After a write to the LPTIMx_ARR register a new write operation to the
* same register can only be performed when the previous write operation
* is completed. Any successive write before the ARROK flag is set, will
* lead to unpredictable results.
* @note autoreload value be strictly greater than the compare value.
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
* @param LPTIMx Low-Power Timer instance
* @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
{
MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
}
/**
* @brief Get actual auto reload value
* @rmtoll ARR ARR LL_LPTIM_GetAutoReload
* @param LPTIMx Low-Power Timer instance
* @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
}
/**
* @brief Set the repetition value
* @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
* @rmtoll RCR REP LL_LPTIM_SetRepetition
* @param LPTIMx Low-Power Timer instance
* @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
{
MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
}
/**
* @brief Get the repetition value
* @rmtoll RCR REP LL_LPTIM_GetRepetition
* @param LPTIMx Low-Power Timer instance
* @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
}
/**
* @brief Enable capture/compare channel.
* @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n
* CCMR1 CC2E LL_LPTIM_CC_EnableChannel
* @param LPTIMx LPTimer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
{
SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
}
/**
* @brief Disable capture/compare channel.
* @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n
* CCMR1 CC2E LL_LPTIM_CC_DisableChannel
* @param LPTIMx LPTimer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel)
{
CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]);
}
/**
* @brief Indicate whether channel is enabled.
* @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n
* CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel
* @param LPTIMx LPTimer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *const LPTIMx, uint32_t Channel)
{
return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \
(0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL);
}
/**
* @brief Set the compare value
* @note After a write to the LPTIMx_CCR1 register a new write operation to the
* same register can only be performed when the previous write operation
* is completed. Any successive write before the CMP1OK flag is set, will
* lead to unpredictable results.
* @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1
* @param LPTIMx Low-Power Timer instance
* @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
{
MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue);
}
/**
* @brief Get actual compare value
* @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1
* @param LPTIMx Low-Power Timer instance
* @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
}
/**
* @brief Set the compare value
* @note After a write to the LPTIMx_CCR2 register a new write operation to the
* same register can only be performed when the previous write operation
* is completed. Any successive write before the CMP2OK flag is set, will
* lead to unpredictable results.
* @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2
* @param LPTIMx Low-Power Timer instance
* @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
{
MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue);
}
/**
* @brief Get actual compare value
* @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2
* @param LPTIMx Low-Power Timer instance
* @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
}
/**
* @brief Get actual counter value
* @note When the LPTIM instance is running with an asynchronous clock, reading
* the LPTIMx_CNT register may return unreliable values. So in this case
* it is necessary to perform two consecutive read accesses and verify
* that the two returned values are identical.
* @rmtoll CNT CNT LL_LPTIM_GetCounter
* @param LPTIMx Low-Power Timer instance
* @retval Counter value
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
}
/**
* @brief Set the counter mode (selection of the LPTIM counter clock source).
* @note The counter mode can be set only when the LPTIM instance is disabled.
* @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
* @param LPTIMx Low-Power Timer instance
* @param CounterMode This parameter can be one of the following values:
* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
}
/**
* @brief Get the counter mode
* @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
}
/**
* @brief Set waveform shape
* @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
* @param LPTIMx Low-Power Timer instance
* @param Waveform This parameter can be one of the following values:
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
}
/**
* @brief Get actual waveform shape
* @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
}
/**
* @brief Set the polarity of an output channel.
* @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n
* @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n
* @param LPTIMx Low-Power Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
{
if (LPTIMx == LPTIM4)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, ((Polarity >> LPTIM_CCMR1_CC1P_Pos) << LPTIM_CFGR_WAVPOL_Pos));
}
else
{
MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]),
(Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]));
}
}
/**
* @brief Get the polarity of an output channel.
* @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n
* @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n
* @param LPTIMx Low-Power Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
*/
__STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *const LPTIMx, uint32_t Channel)
{
if (LPTIMx == LPTIM4)
{
return (uint32_t)((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL) >> LPTIM_CFGR_WAVPOL_Pos) << LPTIM_CCMR1_CC1P_Pos);
}
else
{
return (uint32_t)(READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]) >> \
LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
}
}
/**
* @brief Set actual prescaler division ratio.
* @note This function must be called when the LPTIM instance is disabled.
* @note When the LPTIM is configured to be clocked by an internal clock source
* and the LPTIM counter is configured to be updated by active edges
* detected on the LPTIM external Input1, the internal clock provided to
* the LPTIM must be not be prescaled.
* @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
* @param LPTIMx Low-Power Timer instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_LPTIM_PRESCALER_DIV1
* @arg @ref LL_LPTIM_PRESCALER_DIV2
* @arg @ref LL_LPTIM_PRESCALER_DIV4
* @arg @ref LL_LPTIM_PRESCALER_DIV8
* @arg @ref LL_LPTIM_PRESCALER_DIV16
* @arg @ref LL_LPTIM_PRESCALER_DIV32
* @arg @ref LL_LPTIM_PRESCALER_DIV64
* @arg @ref LL_LPTIM_PRESCALER_DIV128
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
}
/**
* @brief Get actual prescaler division ratio.
* @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_PRESCALER_DIV1
* @arg @ref LL_LPTIM_PRESCALER_DIV2
* @arg @ref LL_LPTIM_PRESCALER_DIV4
* @arg @ref LL_LPTIM_PRESCALER_DIV8
* @arg @ref LL_LPTIM_PRESCALER_DIV16
* @arg @ref LL_LPTIM_PRESCALER_DIV32
* @arg @ref LL_LPTIM_PRESCALER_DIV64
* @arg @ref LL_LPTIM_PRESCALER_DIV128
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
}
/**
* @brief Set LPTIM input 1 source (default GPIO).
* @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
* @param LPTIMx Low-Power Timer instance
* @param Src This parameter can be one of the following values:
* @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
* @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
* @arg @ref LL_LPTIM_INPUT1_SRC_COMP2 (*)
* (*) Value not defined for all devices
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
{
MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
}
/**
* @brief Set LPTIM input 2 source (default GPIO).
* @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
* @param LPTIMx Low-Power Timer instance
* @param Src This parameter can be one of the following values:
* @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
* @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
{
MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
}
/**
* @brief Set LPTIM input source (default GPIO).
* @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap
* @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap
* @param LPTIMx Low-Power Timer instance
* @param Src This parameter can be one of the following values:
* @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO
* @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1
* @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP2
* @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO
* @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI
* @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE
* @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO
* @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1
* @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP2
* @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO
* @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI
* @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSIS_1024
* @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_MSIS_4
* @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_GPIO
* @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP1
* @arg @ref LL_LPTIM_LPTIM3_IC1_RMP_COMP2
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src)
{
MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src);
}
/**
* @brief Set the polarity of IC channel 1.
* @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n
* @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n
* @param LPTIMx Low-Power Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_LPTIM_ICPOLARITY_RISING
* @arg @ref LL_LPTIM_ICPOLARITY_FALLING
* @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity)
{
MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel],
Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
}
/**
* @brief Get the polarity of IC channels.
* @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n
* @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n
* @param LPTIMx Low-Power Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_ICPOLARITY_RISING
* @arg @ref LL_LPTIM_ICPOLARITY_FALLING
* @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING
*/
__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *const LPTIMx, uint32_t Channel)
{
return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \
LL_LPTIM_SHIFT_TAB_CCxP[Channel]);
}
/**
* @brief Set the filter of IC channels.
* @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n
* @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n
* @param LPTIMx Low-Power Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @param Filter This parameter can be one of the following values:
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter)
{
MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel],
Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
}
/**
* @brief Get the filter of IC channels.
* @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n
* @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n
* @param LPTIMx Low-Power Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4
* @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8
*/
__STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *const LPTIMx, uint32_t Channel)
{
return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \
LL_LPTIM_SHIFT_TAB_ICxF[Channel]);
}
/**
* @brief Set the prescaler of IC channels.
* @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n
* @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n
* @param LPTIMx Low-Power Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_LPTIM_ICPSC_DIV1
* @arg @ref LL_LPTIM_ICPSC_DIV2
* @arg @ref LL_LPTIM_ICPSC_DIV4
* @arg @ref LL_LPTIM_ICPSC_DIV8
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler)
{
MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel],
Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
}
/**
* @brief Get the prescaler of IC channels.
* @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n
* @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n
* @param LPTIMx Low-Power Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_ICPSC_DIV1
* @arg @ref LL_LPTIM_ICPSC_DIV2
* @arg @ref LL_LPTIM_ICPSC_DIV4
* @arg @ref LL_LPTIM_ICPSC_DIV8
*/
__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *const LPTIMx, uint32_t Channel)
{
return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \
LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]);
}
/**
* @brief Set the Channel Mode.
* @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n
* CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode
* @param LPTIMx Low-Power Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @param CCMode This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
* @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode)
{
SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
}
/**
* @brief Get the Channel Mode.
* @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n
* CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode
* @param LPTIMx Low-Power Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CHANNEL_CH1
* @arg @ref LL_LPTIM_CHANNEL_CH2
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM
* @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE
*/
__STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *const LPTIMx, uint32_t Channel)
{
return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \
LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]);
}
/**
* @brief Get captured value for input channel 1.
* @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1
* @note The real capture value corresponding to the input capture trigger can be calculated using
* the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
* where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
* @param LPTIMx Low-Power Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1));
}
/**
* @brief Get captured value for input channel 2.
* @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2
* @note The real capture value corresponding to the input capture trigger can be calculated using
* the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
* where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET
* @param LPTIMx Low-Power Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2));
}
/**
* @}
*/
/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
* @{
*/
/**
* @brief Enable the timeout function
* @note This function must be called when the LPTIM instance is disabled.
* @note The first trigger event will start the timer, any successive trigger
* event will reset the counter and the timer will restart.
* @note The timeout value corresponds to the compare value; if no trigger
* occurs within the expected time frame, the MCU is waked-up by the
* compare match event.
* @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
}
/**
* @brief Disable the timeout function
* @note This function must be called when the LPTIM instance is disabled.
* @note A trigger event arriving when the timer is already started will be
* ignored.
* @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
}
/**
* @brief Indicate whether the timeout function is enabled.
* @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
* @brief Start the LPTIM counter
* @note This function must be called when the LPTIM instance is disabled.
* @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
}
/**
* @brief Configure the external trigger used as a trigger event for the LPTIM.
* @note This function must be called when the LPTIM instance is disabled.
* @note An internal clock source must be present when a digital filter is
* required for the trigger.
* @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
* CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
* CFGR TRIGEN LL_LPTIM_ConfigTrigger
* @param LPTIMx Low-Power Timer instance
* @param Source This parameter can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
* @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF
* @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF
* @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF
* @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF
* @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF
* @param Filter This parameter can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_FILTER_NONE
* @arg @ref LL_LPTIM_TRIG_FILTER_2
* @arg @ref LL_LPTIM_TRIG_FILTER_4
* @arg @ref LL_LPTIM_TRIG_FILTER_8
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
}
/**
* @brief Get actual external trigger source.
* @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
* @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH0_TCF
* @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH1_TCF
* @arg @ref LL_LPTIM_TRIG_SOURCE_LPDMA_CH2_TCF
* @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH0_TCF
* @arg @ref LL_LPTIM_TRIG_SOURCE_GPDMA_CH4_TCF
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
}
/**
* @brief Get actual external trigger filter.
* @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_FILTER_NONE
* @arg @ref LL_LPTIM_TRIG_FILTER_2
* @arg @ref LL_LPTIM_TRIG_FILTER_4
* @arg @ref LL_LPTIM_TRIG_FILTER_8
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
}
/**
* @brief Get actual external trigger polarity.
* @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
}
/**
* @}
*/
/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
* @{
*/
/**
* @brief Set the source of the clock used by the LPTIM instance.
* @note This function must be called when the LPTIM instance is disabled.
* @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
* @param LPTIMx Low-Power Timer instance
* @param ClockSource This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
* @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
}
/**
* @brief Get actual LPTIM instance clock source.
* @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
* @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
}
/**
* @brief Configure the active edge or edges used by the counter when
the LPTIM is clocked by an external clock source.
* @note This function must be called when the LPTIM instance is disabled.
* @note When both external clock signal edges are considered active ones,
* the LPTIM must also be clocked by an internal clock source with a
* frequency equal to at least four times the external clock frequency.
* @note An internal clock source must be present when a digital filter is
* required for external clock.
* @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
* CFGR CKPOL LL_LPTIM_ConfigClock
* @param LPTIMx Low-Power Timer instance
* @param ClockFilter This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CLK_FILTER_NONE
* @arg @ref LL_LPTIM_CLK_FILTER_2
* @arg @ref LL_LPTIM_CLK_FILTER_4
* @arg @ref LL_LPTIM_CLK_FILTER_8
* @param ClockPolarity This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CLK_POLARITY_RISING
* @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
* @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
}
/**
* @brief Get actual clock polarity
* @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_CLK_POLARITY_RISING
* @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
* @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
}
/**
* @brief Get actual clock digital filter
* @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_CLK_FILTER_NONE
* @arg @ref LL_LPTIM_CLK_FILTER_2
* @arg @ref LL_LPTIM_CLK_FILTER_4
* @arg @ref LL_LPTIM_CLK_FILTER_8
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
}
/**
* @}
*/
/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
* @{
*/
/**
* @brief Configure the encoder mode.
* @note This function must be called when the LPTIM instance is disabled.
* @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
* @param LPTIMx Low-Power Timer instance
* @param EncoderMode This parameter can be one of the following values:
* @arg @ref LL_LPTIM_ENCODER_MODE_RISING
* @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
* @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
}
/**
* @brief Get actual encoder mode.
* @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_ENCODER_MODE_RISING
* @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
* @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *const LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
}
/**
* @brief Enable the encoder mode
* @note This function must be called when the LPTIM instance is disabled.
* @note In this mode the LPTIM instance must be clocked by an internal clock
* source. Also, the prescaler division ratio must be equal to 1.
* @note LPTIM instance must be configured in continuous mode prior enabling
* the encoder mode.
* @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
}
/**
* @brief Disable the encoder mode
* @note This function must be called when the LPTIM instance is disabled.
* @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
}
/**
* @brief Indicates whether the LPTIM operates in encoder mode.
* @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
* @}
*/
/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Clear the compare match flag for channel 1 (CC1CF)
* @rmtoll ICR CC1CF LL_LPTIM_ClearFLAG_CC1
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC1(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF);
}
/**
* @brief Inform application whether a capture/compare interrupt has occurred for channel 1.
* @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL));
}
/**
* @brief Clear the compare match flag for channel 2 (CC2CF)
* @rmtoll ICR CC2CF LL_LPTIM_ClearFLAG_CC2
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC2(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF);
}
/**
* @brief Inform application whether a capture/compare interrupt has occurred for channel 2.
* @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL));
}
/**
* @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF)
* @rmtoll ICR CC1OCF LL_LPTIM_ClearFLAG_CC1O
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC1O(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF);
}
/**
* @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1.
* @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL));
}
/**
* @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF)
* @rmtoll ICR CC2OCF LL_LPTIM_ClearFLAG_CC2O
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFLAG_CC2O(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF);
}
/**
* @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2.
* @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL));
}
/**
* @brief Clear the autoreload match flag (ARRMCF)
* @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
}
/**
* @brief Inform application whether a autoreload match interrupt has occurred.
* @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
* @brief Clear the external trigger valid edge flag(EXTTRIGCF).
* @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
}
/**
* @brief Inform application whether a valid edge on the selected external trigger input has occurred.
* @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
* @brief Clear the compare register update interrupt flag (CMP1OKCF).
* @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF);
}
/**
* @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully
completed. If so, a new one can be initiated.
* @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL));
}
/**
* @brief Clear the compare register update interrupt flag (CMP2OKCF).
* @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF);
}
/**
* @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully
completed. If so, a new one can be initiated.
* @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL));
}
/**
* @brief Clear the interrupt register update interrupt flag (DIEROKCF).
* @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF);
}
/**
* @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully
completed. If so, a new one can be initiated.
* @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *const LPTIMx)
{
return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL);
}
/**
* @brief Clear the autoreload register update interrupt flag (ARROKCF).
* @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
}
/**
* @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
completed. If so, a new one can be initiated.
* @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
* @brief Clear the counter direction change to up interrupt flag (UPCF).
* @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
}
/**
* @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
operates in encoder mode).
* @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
* @brief Clear the counter direction change to down interrupt flag (DOWNCF).
* @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
}
/**
* @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
operates in encoder mode).
* @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
* @brief Clear the repetition register update interrupt flag (REPOKCF).
* @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
}
/**
* @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
completed; If so, a new one can be initiated.
* @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *const LPTIMx)
{
return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
}
/**
* @brief Clear the update event flag (UECF).
* @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
}
/**
* @brief Informs application whether the LPTIMx update event has occurred.
* @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *const LPTIMx)
{
return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
* @{
*/
/**
* @brief Enable capture/compare 1 interrupt (CC1IE).
* @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
}
/**
* @brief Disable capture/compare 1 interrupt (CC1IE).
* @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE);
}
/**
* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
* @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL));
}
/**
* @brief Enable capture/compare 1 interrupt (CC2IE).
* @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
}
/**
* @brief Disable capture/compare 2 interrupt (CC2IE).
* @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE);
}
/**
* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
* @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL));
}
/**
* @brief Enable capture/compare 1 over-capture interrupt (CC1OIE).
* @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
}
/**
* @brief Disable capture/compare 1 over-capture interrupt (CC1OIE).
* @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE);
}
/**
* @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled.
* @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL));
}
/**
* @brief Enable capture/compare 1 over-capture interrupt (CC2OIE).
* @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
}
/**
* @brief Disable capture/compare 1 over-capture interrupt (CC2OIE).
* @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE);
}
/**
* @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled.
* @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL));
}
/**
* @brief Enable autoreload match interrupt (ARRMIE).
* @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
}
/**
* @brief Disable autoreload match interrupt (ARRMIE).
* @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE);
}
/**
* @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
* @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL));
}
/**
* @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
* @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
}
/**
* @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
* @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE);
}
/**
* @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
* @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
* @brief Enable compare register write completed interrupt (CMP1OKIE).
* @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
}
/**
* @brief Disable compare register write completed interrupt (CMP1OKIE).
* @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE);
}
/**
* @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled.
* @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL));
}
/**
* @brief Enable compare register write completed interrupt (CMP2OKIE).
* @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
}
/**
* @brief Disable compare register write completed interrupt (CMP2OKIE).
* @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE);
}
/**
* @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled.
* @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL));
}
/**
* @brief Enable autoreload register write completed interrupt (ARROKIE).
* @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
}
/**
* @brief Disable autoreload register write completed interrupt (ARROKIE).
* @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE);
}
/**
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL));
}
/**
* @brief Enable direction change to up interrupt (UPIE).
* @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
}
/**
* @brief Disable direction change to up interrupt (UPIE).
* @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE);
}
/**
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *const LPTIMx)
{
return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL));
}
/**
* @brief Enable direction change to down interrupt (DOWNIE).
* @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
}
/**
* @brief Disable direction change to down interrupt (DOWNIE).
* @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE);
}
/**
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *const LPTIMx)
{
return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL);
}
/**
* @brief Enable repetition register update successfully completed interrupt (REPOKIE).
* @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
}
/**
* @brief Disable repetition register update successfully completed interrupt (REPOKIE).
* @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE);
}
/**
* @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
* @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *const LPTIMx)
{
return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL);
}
/**
* @brief Enable update event interrupt (UEIE).
* @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
}
/**
* @brief Disable update event interrupt (UEIE).
* @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE);
}
/**
* @brief Indicates whether the update event interrupt (UEIE) is enabled.
* @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE
* @param LPTIMx Low-Power Timer instance
*@ retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *const LPTIMx)
{
return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Enable update DMA request.
* @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
}
/**
* @brief Disable update DMA request.
* @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE);
}
/**
* @brief Indicates whether the update DMA request is enabled.
* @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *const LPTIMx)
{
return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 1 DMA request (CC1DE).
* @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
}
/**
* @brief Disable capture/compare 1 DMA request (CC1DE).
* @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE);
}
/**
* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
* @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *const LPTIMx)
{
return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 2 DMA request (CC2DE).
* @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
}
/**
* @brief Disable capture/compare 2 DMA request (CC2DE).
* @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE);
}
/**
* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
* @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *const LPTIMx)
{
return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_LPTIM_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h
|
C
|
apache-2.0
| 93,898
|
/**
******************************************************************************
* @file stm32u5xx_ll_lpuart.h
* @author MCD Application Team
* @brief Header file of LPUART LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_LPUART_H
#define STM32U5xx_LL_LPUART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (LPUART1)
/** @defgroup LPUART_LL LPUART
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
* @{
*/
/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
static const uint16_t LPUART_PRESCALER_TAB[] =
{
(uint16_t)1,
(uint16_t)2,
(uint16_t)4,
(uint16_t)6,
(uint16_t)8,
(uint16_t)10,
(uint16_t)12,
(uint16_t)16,
(uint16_t)32,
(uint16_t)64,
(uint16_t)128,
(uint16_t)256
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
* @{
*/
/* Defines used in Baud Rate related macros and corresponding register setting computation */
#define LPUART_LPUARTDIV_FREQ_MUL 256U
#define LPUART_BRR_MASK 0x000FFFFFU
#define LPUART_BRR_MIN_VALUE 0x00000300U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
* @{
*/
/**
* @brief LL LPUART Init Structure definition
*/
typedef struct
{
uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetPrescaler().*/
uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref LPUART_LL_EC_PARITY.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetHWFlowCtrl().*/
} LL_LPUART_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
* @{
*/
/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_LPUART_WriteReg function
* @{
*/
#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_LPUART_ReadReg function
* @{
*/
#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
* @{
*/
#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
interrupt enable */
#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
not full interrupt enable */
#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
* @{
*/
#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_DIRECTION Direction
* @{
*/
#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_PARITY Parity Control
* @{
*/
#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
* @{
*/
#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
* @{
*/
#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
USART_PRESC_PRESCALER_1 |\
USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
USART_PRESC_PRESCALER_1 |\
USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
* @{
*/
#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
* @{
*/
#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
* @{
*/
#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
* @{
*/
#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
* @{
*/
#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
in positive/direct logic. (1=H, 0=L) */
#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
in negative/inverse logic. (1=L, 0=H).
The parity bit is also inverted. */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_BITORDER Bit Order
* @{
*/
#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
following the start bit */
#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
following the start bit */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
* @{
*/
#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
* @{
*/
#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
when there is space in the receive buffer */
#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
when the nCTS input is asserted (tied to 0)*/
#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
* @{
*/
#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
* @brief LPUART Autonomous Trigger selection
* @{
*/
#define LL_LPUART_LPDMA1_CH0_TCF_TRG 0U /*!< LPUART LPDMA1 channel0 Internal Trigger */
#define LL_LPUART_LPDMA1_CH1_TCF_TRG 1U /*!< LPUART LPDMA1 channel1 Internal Trigger */
#define LL_LPUART_LPDMA1_CH2_TCF_TRG 2U /*!< LPUART LPDMA1 channel2 Internal Trigger */
#define LL_LPUART_LPDMA1_CH3_TCF_TRG 3U /*!< LPUART LPDMA1 channel3 Internal Trigger */
#define LL_LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */
#define LL_LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */
#define LL_LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */
#define LL_LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */
#define LL_LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */
#define LL_LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */
#define LL_LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */
#define LL_LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
* @brief LPUART Autonomous Trigger Polarity
* @{
*/
#define LL_LPUART_TRIG_POLARITY_RISING 0x00000000U /*!< LPUART triggered on rising edge */
#define LL_LPUART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< LPUART triggered on falling edge */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
* @{
*/
/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in LPUART register
* @param __INSTANCE__ LPUART Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in LPUART register
* @param __INSTANCE__ LPUART Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
* @{
*/
/**
* @brief Compute LPUARTDIV value according to Peripheral Clock and
* expected Baud Rate (20-bit value of LPUARTDIV is returned)
* @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
* @param __PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_LPUART_PRESCALER_DIV1
* @arg @ref LL_LPUART_PRESCALER_DIV2
* @arg @ref LL_LPUART_PRESCALER_DIV4
* @arg @ref LL_LPUART_PRESCALER_DIV6
* @arg @ref LL_LPUART_PRESCALER_DIV8
* @arg @ref LL_LPUART_PRESCALER_DIV10
* @arg @ref LL_LPUART_PRESCALER_DIV12
* @arg @ref LL_LPUART_PRESCALER_DIV16
* @arg @ref LL_LPUART_PRESCALER_DIV32
* @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
* @param __BAUDRATE__ Baud Rate value to achieve
* @retval LPUARTDIV value to be used for BRR register filling
*/
#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
* LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
* @{
*/
/** @defgroup LPUART_LL_EF_Configuration Configuration functions
* @{
*/
/**
* @brief LPUART Enable
* @rmtoll CR1 UE LL_LPUART_Enable
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR1, USART_CR1_UE);
}
/**
* @brief LPUART Disable
* @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
* and current operations are discarded. The configuration of the LPUART is kept, but all the status
* flags, in the LPUARTx_ISR are set to their default values.
* @note In order to go into low-power mode without generating errors on the line,
* the TE bit must be reset before and the software must wait
* for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
* The DMA requests are also reset when UE = 0 so the DMA channel must
* be disabled before resetting the UE bit.
* @rmtoll CR1 UE LL_LPUART_Disable
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
}
/**
* @brief Indicate if LPUART is enabled
* @rmtoll CR1 UE LL_LPUART_IsEnabled
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
/**
* @brief FIFO Mode Enable
* @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
}
/**
* @brief FIFO Mode Disable
* @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
}
/**
* @brief Indicate if FIFO Mode is enabled
* @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
}
/**
* @brief Configure TX FIFO Threshold
* @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
* @param LPUARTx LPUART Instance
* @param Threshold This parameter can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
{
ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
}
/**
* @brief Return TX FIFO Threshold Configuration
* @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
}
/**
* @brief Configure RX FIFO Threshold
* @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
* @param LPUARTx LPUART Instance
* @param Threshold This parameter can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
{
ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
}
/**
* @brief Return RX FIFO Threshold Configuration
* @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
*/
__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
}
/**
* @brief Configure TX and RX FIFOs Threshold
* @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
* CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
* @param LPUARTx LPUART Instance
* @param TXThreshold This parameter can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
* @param RXThreshold This parameter can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
(RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
* @brief LPUART enabled in STOP Mode
* @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
* LPUART clock selection is HSI or LSE in RCC.
* @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
}
/**
* @brief LPUART disabled in STOP Mode
* @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
* @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
}
/**
* @brief Indicate if LPUART is enabled in STOP Mode
* (able to wake up MCU from Stop mode or not)
* @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
}
/**
* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
* @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
}
/**
* @brief Receiver Disable
* @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
}
/**
* @brief Transmitter Enable
* @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
}
/**
* @brief Transmitter Disable
* @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
}
/**
* @brief Configure simultaneously enabled/disabled states
* of Transmitter and Receiver
* @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
* CR1 TE LL_LPUART_SetTransferDirection
* @param LPUARTx LPUART Instance
* @param TransferDirection This parameter can be one of the following values:
* @arg @ref LL_LPUART_DIRECTION_NONE
* @arg @ref LL_LPUART_DIRECTION_RX
* @arg @ref LL_LPUART_DIRECTION_TX
* @arg @ref LL_LPUART_DIRECTION_TX_RX
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
{
ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
}
/**
* @brief Return enabled/disabled states of Transmitter and Receiver
* @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
* CR1 TE LL_LPUART_GetTransferDirection
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_DIRECTION_NONE
* @arg @ref LL_LPUART_DIRECTION_RX
* @arg @ref LL_LPUART_DIRECTION_TX
* @arg @ref LL_LPUART_DIRECTION_TX_RX
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
}
/**
* @brief Configure Parity (enabled/disabled and parity mode if enabled)
* @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
* When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
* (depending on data width) and parity is checked on the received data.
* @rmtoll CR1 PS LL_LPUART_SetParity\n
* CR1 PCE LL_LPUART_SetParity
* @param LPUARTx LPUART Instance
* @param Parity This parameter can be one of the following values:
* @arg @ref LL_LPUART_PARITY_NONE
* @arg @ref LL_LPUART_PARITY_EVEN
* @arg @ref LL_LPUART_PARITY_ODD
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
}
/**
* @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
* @rmtoll CR1 PS LL_LPUART_GetParity\n
* CR1 PCE LL_LPUART_GetParity
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_PARITY_NONE
* @arg @ref LL_LPUART_PARITY_EVEN
* @arg @ref LL_LPUART_PARITY_ODD
*/
__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
}
/**
* @brief Set Receiver Wake Up method from Mute mode.
* @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
* @param LPUARTx LPUART Instance
* @param Method This parameter can be one of the following values:
* @arg @ref LL_LPUART_WAKEUP_IDLELINE
* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
}
/**
* @brief Return Receiver Wake Up method from Mute mode
* @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_WAKEUP_IDLELINE
* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
*/
__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
}
/**
* @brief Set Word length (nb of data bits, excluding start and stop bits)
* @rmtoll CR1 M LL_LPUART_SetDataWidth
* @param LPUARTx LPUART Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_LPUART_DATAWIDTH_7B
* @arg @ref LL_LPUART_DATAWIDTH_8B
* @arg @ref LL_LPUART_DATAWIDTH_9B
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
}
/**
* @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
* @rmtoll CR1 M LL_LPUART_GetDataWidth
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_DATAWIDTH_7B
* @arg @ref LL_LPUART_DATAWIDTH_8B
* @arg @ref LL_LPUART_DATAWIDTH_9B
*/
__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
}
/**
* @brief Allow switch between Mute Mode and Active mode
* @rmtoll CR1 MME LL_LPUART_EnableMuteMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
}
/**
* @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
* @rmtoll CR1 MME LL_LPUART_DisableMuteMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
}
/**
* @brief Indicate if switch between Mute Mode and Active mode is allowed
* @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
}
/**
* @brief Configure Clock source prescaler for baudrate generator and oversampling
* @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
* @param LPUARTx LPUART Instance
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_LPUART_PRESCALER_DIV1
* @arg @ref LL_LPUART_PRESCALER_DIV2
* @arg @ref LL_LPUART_PRESCALER_DIV4
* @arg @ref LL_LPUART_PRESCALER_DIV6
* @arg @ref LL_LPUART_PRESCALER_DIV8
* @arg @ref LL_LPUART_PRESCALER_DIV10
* @arg @ref LL_LPUART_PRESCALER_DIV12
* @arg @ref LL_LPUART_PRESCALER_DIV16
* @arg @ref LL_LPUART_PRESCALER_DIV32
* @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
{
MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
}
/**
* @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
* @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_PRESCALER_DIV1
* @arg @ref LL_LPUART_PRESCALER_DIV2
* @arg @ref LL_LPUART_PRESCALER_DIV4
* @arg @ref LL_LPUART_PRESCALER_DIV6
* @arg @ref LL_LPUART_PRESCALER_DIV8
* @arg @ref LL_LPUART_PRESCALER_DIV10
* @arg @ref LL_LPUART_PRESCALER_DIV12
* @arg @ref LL_LPUART_PRESCALER_DIV16
* @arg @ref LL_LPUART_PRESCALER_DIV32
* @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
*/
__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
}
/**
* @brief Set the length of the stop bits
* @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
* @param LPUARTx LPUART Instance
* @param StopBits This parameter can be one of the following values:
* @arg @ref LL_LPUART_STOPBITS_1
* @arg @ref LL_LPUART_STOPBITS_2
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
}
/**
* @brief Retrieve the length of the stop bits
* @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_STOPBITS_1
* @arg @ref LL_LPUART_STOPBITS_2
*/
__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
}
/**
* @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
* @note Call of this function is equivalent to following function call sequence :
* - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
* - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
* - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
* @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
* CR1 PCE LL_LPUART_ConfigCharacter\n
* CR1 M LL_LPUART_ConfigCharacter\n
* CR2 STOP LL_LPUART_ConfigCharacter
* @param LPUARTx LPUART Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_LPUART_DATAWIDTH_7B
* @arg @ref LL_LPUART_DATAWIDTH_8B
* @arg @ref LL_LPUART_DATAWIDTH_9B
* @param Parity This parameter can be one of the following values:
* @arg @ref LL_LPUART_PARITY_NONE
* @arg @ref LL_LPUART_PARITY_EVEN
* @arg @ref LL_LPUART_PARITY_ODD
* @param StopBits This parameter can be one of the following values:
* @arg @ref LL_LPUART_STOPBITS_1
* @arg @ref LL_LPUART_STOPBITS_2
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
uint32_t StopBits)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
}
/**
* @brief Configure TX/RX pins swapping setting.
* @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
* @param LPUARTx LPUART Instance
* @param SwapConfig This parameter can be one of the following values:
* @arg @ref LL_LPUART_TXRX_STANDARD
* @arg @ref LL_LPUART_TXRX_SWAPPED
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
}
/**
* @brief Retrieve TX/RX pins swapping configuration.
* @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_TXRX_STANDARD
* @arg @ref LL_LPUART_TXRX_SWAPPED
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
}
/**
* @brief Configure RX pin active level logic
* @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
* @param LPUARTx LPUART Instance
* @param PinInvMethod This parameter can be one of the following values:
* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
}
/**
* @brief Retrieve RX pin active level logic configuration
* @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
*/
__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
}
/**
* @brief Configure TX pin active level logic
* @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
* @param LPUARTx LPUART Instance
* @param PinInvMethod This parameter can be one of the following values:
* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
}
/**
* @brief Retrieve TX pin active level logic configuration
* @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
}
/**
* @brief Configure Binary data logic.
*
* @note Allow to define how Logical data from the data register are send/received :
* either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
* @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
* @param LPUARTx LPUART Instance
* @param DataLogic This parameter can be one of the following values:
* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
}
/**
* @brief Retrieve Binary data configuration
* @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
*/
__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
}
/**
* @brief Configure transfer bit order (either Less or Most Significant Bit First)
* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
* @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
* @param LPUARTx LPUART Instance
* @param BitOrder This parameter can be one of the following values:
* @arg @ref LL_LPUART_BITORDER_LSBFIRST
* @arg @ref LL_LPUART_BITORDER_MSBFIRST
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
}
/**
* @brief Return transfer bit order (either Less or Most Significant Bit First)
* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
* @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_BITORDER_LSBFIRST
* @arg @ref LL_LPUART_BITORDER_MSBFIRST
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
}
/**
* @brief Set Address of the LPUART node.
* @note This is used in multiprocessor communication during Mute mode or Stop mode,
* for wake up with address mark detection.
* @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
* (b7-b4 should be set to 0)
* 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
* (This is used in multiprocessor communication during Mute mode or Stop mode,
* for wake up with 7-bit address mark detection.
* The MSB of the character sent by the transmitter should be equal to 1.
* It may also be used for character detection during normal reception,
* Mute mode inactive (for example, end of block detection in ModBus protocol).
* In this case, the whole received character (8-bit) is compared to the ADD[7:0]
* value and CMF flag is set on match)
* @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
* CR2 ADDM7 LL_LPUART_ConfigNodeAddress
* @param LPUARTx LPUART Instance
* @param AddressLen This parameter can be one of the following values:
* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
* @param NodeAddress 4 or 7 bit Address of the LPUART node.
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
(uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
}
/**
* @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
* @note If 4-bit Address Detection is selected in ADDM7,
* only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
* If 7-bit Address Detection is selected in ADDM7,
* only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
* @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
* @param LPUARTx LPUART Instance
* @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
*/
__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
}
/**
* @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
* @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
*/
__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
}
/**
* @brief Enable RTS HW Flow Control
* @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
}
/**
* @brief Disable RTS HW Flow Control
* @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
}
/**
* @brief Enable CTS HW Flow Control
* @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
}
/**
* @brief Disable CTS HW Flow Control
* @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
}
/**
* @brief Configure HW Flow Control mode (both CTS and RTS)
* @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
* CR3 CTSE LL_LPUART_SetHWFlowCtrl
* @param LPUARTx LPUART Instance
* @param HardwareFlowControl This parameter can be one of the following values:
* @arg @ref LL_LPUART_HWCONTROL_NONE
* @arg @ref LL_LPUART_HWCONTROL_RTS
* @arg @ref LL_LPUART_HWCONTROL_CTS
* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
{
MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
}
/**
* @brief Return HW Flow Control configuration (both CTS and RTS)
* @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
* CR3 CTSE LL_LPUART_GetHWFlowCtrl
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_HWCONTROL_NONE
* @arg @ref LL_LPUART_HWCONTROL_RTS
* @arg @ref LL_LPUART_HWCONTROL_CTS
* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
*/
__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
}
/**
* @brief Enable Overrun detection
* @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
}
/**
* @brief Disable Overrun detection
* @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
}
/**
* @brief Indicate if Overrun detection is enabled
* @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
/**
* @brief Configure LPUART BRR register for achieving expected Baud Rate value.
*
* @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
* according to used Peripheral Clock and expected Baud Rate values
* @note Peripheral clock and Baud Rate values provided as function parameters should be valid
* (Baud rate value != 0).
* @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
* a care should be taken when generating high baud rates using high PeriphClk
* values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
* @rmtoll BRR BRR LL_LPUART_SetBaudRate
* @param LPUARTx LPUART Instance
* @param PeriphClk Peripheral Clock
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_LPUART_PRESCALER_DIV1
* @arg @ref LL_LPUART_PRESCALER_DIV2
* @arg @ref LL_LPUART_PRESCALER_DIV4
* @arg @ref LL_LPUART_PRESCALER_DIV6
* @arg @ref LL_LPUART_PRESCALER_DIV8
* @arg @ref LL_LPUART_PRESCALER_DIV10
* @arg @ref LL_LPUART_PRESCALER_DIV12
* @arg @ref LL_LPUART_PRESCALER_DIV16
* @arg @ref LL_LPUART_PRESCALER_DIV32
* @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
* @param BaudRate Baud Rate
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t BaudRate)
{
if (BaudRate != 0U)
{
LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
}
}
/**
* @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
* (full BRR content), and to used Peripheral Clock values
* @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
* @rmtoll BRR BRR LL_LPUART_GetBaudRate
* @param LPUARTx LPUART Instance
* @param PeriphClk Peripheral Clock
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_LPUART_PRESCALER_DIV1
* @arg @ref LL_LPUART_PRESCALER_DIV2
* @arg @ref LL_LPUART_PRESCALER_DIV4
* @arg @ref LL_LPUART_PRESCALER_DIV6
* @arg @ref LL_LPUART_PRESCALER_DIV8
* @arg @ref LL_LPUART_PRESCALER_DIV10
* @arg @ref LL_LPUART_PRESCALER_DIV12
* @arg @ref LL_LPUART_PRESCALER_DIV16
* @arg @ref LL_LPUART_PRESCALER_DIV32
* @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
* @retval Baud Rate
*/
__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
{
uint32_t lpuartdiv;
uint32_t brrresult;
uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
{
brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
}
else
{
brrresult = 0x0UL;
}
return (brrresult);
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
* @{
*/
/**
* @brief Enable Single Wire Half-Duplex mode
* @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
}
/**
* @brief Disable Single Wire Half-Duplex mode
* @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
}
/**
* @brief Indicate if Single Wire Half-Duplex mode is enabled
* @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
* @{
*/
/**
* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
* @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
* @param LPUARTx LPUART Instance
* @param Time Value between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
}
/**
* @brief Return DEDT (Driver Enable De-Assertion Time)
* @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
* @param LPUARTx LPUART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : c
*/
__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
}
/**
* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
* @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
* @param LPUARTx LPUART Instance
* @param Time Value between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
}
/**
* @brief Return DEAT (Driver Enable Assertion Time)
* @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
* @param LPUARTx LPUART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
*/
__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
}
/**
* @brief Enable Driver Enable (DE) Mode
* @rmtoll CR3 DEM LL_LPUART_EnableDEMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
}
/**
* @brief Disable Driver Enable (DE) Mode
* @rmtoll CR3 DEM LL_LPUART_DisableDEMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
}
/**
* @brief Indicate if Driver Enable (DE) Mode is enabled
* @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
}
/**
* @brief Select Driver Enable Polarity
* @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
* @param LPUARTx LPUART Instance
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_LPUART_DE_POLARITY_HIGH
* @arg @ref LL_LPUART_DE_POLARITY_LOW
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
{
MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
}
/**
* @brief Return Driver Enable Polarity
* @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_DE_POLARITY_HIGH
* @arg @ref LL_LPUART_DE_POLARITY_LOW
*/
__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if the LPUART Parity Error Flag is set or not
* @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Framing Error Flag is set or not
* @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Noise error detected Flag is set or not
* @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART OverRun Error Flag is set or not
* @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART IDLE line detected Flag is set or not
* @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
/**
* @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
* @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Transmission Complete Flag is set or not
* @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
/**
* @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
* @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART CTS interrupt Flag is set or not
* @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART CTS Flag is set or not
* @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Busy Flag is set or not
* @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Character Match Flag is set or not
* @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Send Break Flag is set or not
* @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
* @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
* @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
* @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART TX FIFO Empty Flag is set or not
* @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART RX FIFO Full Flag is set or not
* @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART TX FIFO Threshold Flag is set or not
* @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART RX FIFO Threshold Flag is set or not
* @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
}
/**
* @brief Clear Parity Error Flag
* @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
}
/**
* @brief Clear Framing Error Flag
* @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
}
/**
* @brief Clear Noise detected Flag
* @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
}
/**
* @brief Clear OverRun Error Flag
* @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
}
/**
* @brief Clear IDLE line detected Flag
* @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
}
/**
* @brief Clear Transmission Complete Flag
* @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
}
/**
* @brief Clear CTS Interrupt Flag
* @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
}
/**
* @brief Clear Character Match Flag
* @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable IDLE Interrupt
* @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
/**
* @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
* @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
* @brief Enable Transmission Complete Interrupt
* @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
/**
* @brief Enable TX Empty and TX FIFO Not Full Interrupt
* @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
* @brief Enable Parity Error Interrupt
* @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
}
/**
* @brief Enable Character Match Interrupt
* @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
}
/**
* @brief Enable TX FIFO Empty Interrupt
* @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
}
/**
* @brief Enable RX FIFO Full Interrupt
* @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
}
/**
* @brief Enable Error Interrupt
* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
* - 0: Interrupt is inhibited
* - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
* @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
}
/**
* @brief Enable CTS Interrupt
* @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
}
/**
* @brief Enable TX FIFO Threshold Interrupt
* @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
}
/**
* @brief Enable RX FIFO Threshold Interrupt
* @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
}
/**
* @brief Disable IDLE Interrupt
* @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
/**
* @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
* @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
* @brief Disable Transmission Complete Interrupt
* @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
/**
* @brief Disable TX Empty and TX FIFO Not Full Interrupt
* @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
* @brief Disable Parity Error Interrupt
* @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
}
/**
* @brief Disable Character Match Interrupt
* @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
}
/**
* @brief Disable TX FIFO Empty Interrupt
* @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
}
/**
* @brief Disable RX FIFO Full Interrupt
* @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
}
/**
* @brief Disable Error Interrupt
* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
* - 0: Interrupt is inhibited
* - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
* @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
}
/**
* @brief Disable CTS Interrupt
* @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
}
/**
* @brief Disable TX FIFO Threshold Interrupt
* @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
}
/**
* @brief Disable RX FIFO Threshold Interrupt
* @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
}
/**
* @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
* @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
/**
* @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
* @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
/**
* @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
* @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
* @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
* @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
* @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
* @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Error Interrupt is enabled or disabled.
* @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART CTS Interrupt is enabled or disabled.
* @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
/**
* @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
* @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
}
/**
* @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
* @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
* @{
*/
/**
* @brief Enable DMA Mode for reception
* @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
}
/**
* @brief Disable DMA Mode for reception
* @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
}
/**
* @brief Check if DMA Mode is enabled for reception
* @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Mode for transmission
* @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
}
/**
* @brief Disable DMA Mode for transmission
* @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
}
/**
* @brief Check if DMA Mode is enabled for transmission
* @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Disabling on Reception Error
* @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
}
/**
* @brief Disable DMA Disabling on Reception Error
* @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
}
/**
* @brief Indicate if DMA Disabling on Reception Error is disabled
* @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
}
/**
* @brief Get the LPUART data register address used for DMA transfer
* @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
* @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
* @param LPUARTx LPUART Instance
* @param Direction This parameter can be one of the following values:
* @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
* @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
{
uint32_t data_reg_addr;
if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
{
/* return address of TDR register */
data_reg_addr = (uint32_t) &(LPUARTx->TDR);
}
else
{
/* return address of RDR register */
data_reg_addr = (uint32_t) &(LPUARTx->RDR);
}
return data_reg_addr;
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Read Receiver Data register (Receive Data value, 8 bits)
* @rmtoll RDR RDR LL_LPUART_ReceiveData8
* @param LPUARTx LPUART Instance
* @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
{
return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**
* @brief Read Receiver Data register (Receive Data value, 9 bits)
* @rmtoll RDR RDR LL_LPUART_ReceiveData9
* @param LPUARTx LPUART Instance
* @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
*/
__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
{
return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
}
/**
* @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
* @rmtoll TDR TDR LL_LPUART_TransmitData8
* @param LPUARTx LPUART Instance
* @param Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
{
LPUARTx->TDR = Value;
}
/**
* @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
* @rmtoll TDR TDR LL_LPUART_TransmitData9
* @param LPUARTx LPUART Instance
* @param Value between Min_Data=0x00 and Max_Data=0x1FF
* @retval None
*/
__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
{
LPUARTx->TDR = Value & 0x1FFUL;
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_Execution Execution
* @{
*/
/**
* @brief Request Break sending
* @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
}
/**
* @brief Put LPUART in mute mode and set the RWU flag
* @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
}
/**
* @brief Request a Receive Data and FIFO flush
* @note Allows to discard the received data without reading them, and avoid an overrun
* condition.
* @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature
* @{
*/
/**
* @brief Enable Selected Trigger
* @rmtoll AUTOCR TRIGEN LL_LPUART_Enable_SelectedTrigger
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_Enable_SelectedTrigger(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN);
}
/**
* @brief Disable Selected Trigger
* @rmtoll AUTOCR TRIGEN LL_LPUART_Disable_SelectedTrigger
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_Disable_SelectedTrigger(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN);
}
/**
* @brief Indicate if selected Trigger is disabled or enabled
* @rmtoll AUTOCR TRIGEN LL_LPUART_IsEnabled_SelectedTrigger
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_SelectedTrigger(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Autonomous Send Idle Frame feature
* @rmtoll AUTOCR IDLEDIS LL_LPUART_Enable_AutonomousSendIdleFrame
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_Enable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
}
/**
* @brief Disable Autonomous Send Idle Frame feature
* @rmtoll AUTOCR IDLEDIS LL_LPUART_Disable_AutonomousSendIdleFrame
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_Disable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
}
/**
* @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled
* @rmtoll AUTOCR IDLEDIS LL_LPUART_IsEnabled_AutonomousSendIdleFrame
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL);
}
/**
* @brief Configure the Number of transferred data in bytes
* @rmtoll AUTOCR TDN LL_LPUART_SetNbTxData
* @param LPUARTx LPUART Instance
* @param Nbdata This parameter can be a value between 0 and 0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetNbTxData(USART_TypeDef *LPUARTx, uint32_t Nbdata)
{
MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata);
}
/**
* @brief Retrieve the Number of transferred data in bytes
* @rmtoll AUTOCR TDN LL_LPUART_GetNbTxData
* @param LPUARTx LPUART Instance
* @retval Returned value can be a value between 0 and 0xFFFF
*/
__STATIC_INLINE uint32_t LL_LPUART_GetNbTxData(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TDN));
}
/**
* @brief Set the trigger polarity
* @rmtoll AUTOCR TRIGPOL LL_LPUART_SetTriggerPolarity
* @param LPUARTx LPUART Instance
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_LPUART_TRIG_POLARITY_RISING
* @arg @ref LL_LPUART_TRIG_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTriggerPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
{
MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity);
}
/**
* @brief Get the trigger polarity
* @rmtoll AUTOCR TRIGPOL LL_LPUART_GetTriggerPolarity
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_TRIG_POLARITY_RISING
* @arg @ref LL_LPUART_TRIG_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTriggerPolarity(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL));
}
/**
* @brief Set the selected trigger
* @rmtoll AUTOCR TRIGSEL LL_LPUART_SetSelectedTrigger
* @param LPUARTx LPUART Instance
* @param Trigger This parameter can be one of the following values:
* @arg @ref LL_LPUART_LPDMA1_CH0_TCF_TRG
* @arg @ref LL_LPUART_LPDMA1_CH1_TCF_TRG
* @arg @ref LL_LPUART_LPDMA1_CH2_TCF_TRG
* @arg @ref LL_LPUART_LPDMA1_CH3_TCF_TRG
* @arg @ref LL_LPUART_EXTI_LINE6_TRG
* @arg @ref LL_LPUART_EXTI_LINE8_TRG
* @arg @ref LL_LPUART_LPTIM1_OUT_TRG
* @arg @ref LL_LPUART_LPTIM3_OUT_TRG
* @arg @ref LL_LPUART_COMP1_OUT_TRG
* @arg @ref LL_LPUART_COMP2_OUT_TRG
* @arg @ref LL_LPUART_RTC_ALRA_TRG
* @arg @ref LL_LPUART_RTC_WUT_TRG
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetSelectedTrigger(USART_TypeDef *LPUARTx, uint32_t Trigger)
{
MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos));
}
/**
* @brief Get the selected trigger
* @rmtoll AUTOCR TRIGSEL LL_LPUART_GetSelectedTrigger
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_LPDMA1_CH0_TCF_TRG
* @arg @ref LL_LPUART_LPDMA1_CH1_TCF_TRG
* @arg @ref LL_LPUART_LPDMA1_CH2_TCF_TRG
* @arg @ref LL_LPUART_LPDMA1_CH3_TCF_TRG
* @arg @ref LL_LPUART_EXTI_LINE6_TRG
* @arg @ref LL_LPUART_EXTI_LINE8_TRG
* @arg @ref LL_LPUART_LPTIM1_OUT_TRG
* @arg @ref LL_LPUART_LPTIM3_OUT_TRG
* @arg @ref LL_LPUART_COMP1_OUT_TRG
* @arg @ref LL_LPUART_COMP2_OUT_TRG
* @arg @ref LL_LPUART_RTC_ALRA_TRG
* @arg @ref LL_LPUART_RTC_WUT_TRG
*/
__STATIC_INLINE uint32_t LL_LPUART_GetSelectedTrigger(USART_TypeDef *LPUARTx)
{
return (uint32_t)((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* LPUART1 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_LPUART_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h
|
C
|
apache-2.0
| 98,909
|
/**
******************************************************************************
* @file stm32u5xx_ll_opamp.h
* @author MCD Application Team
* @brief Header file of OPAMP LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_OPAMP_H
#define STM32U5xx_LL_OPAMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (OPAMP1) || defined (OPAMP2)
/** @defgroup OPAMP_LL OPAMP
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
* @{
*/
/* Internal mask for OPAMP power mode: */
/* To select into literal LL_OPAMP_POWERMODE_x the relevant bits for: */
/* - OPAMP power mode into control register */
/* - OPAMP trimming register offset */
/* Internal register offset for OPAMP trimming configuration */
#define OPAMP_POWERMODE_OTR_REGOFFSET 0x00000000U
#define OPAMP_POWERMODE_LPOTR_REGOFFSET 0x00000002U
#define OPAMP_POWERMODE_OTR_REGOFFSET_MASK (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET)
/* Mask for OPAMP power mode into control register */
#define OPAMP_POWERMODE_CSR_BIT_MASK (OPAMP_CSR_OPALPM | OPAMP_CSR_HSM)
/* Internal mask for OPAMP trimming of transistors differential pair NMOS */
/* or PMOS. */
/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for: */
/* - OPAMP trimming selection of transistors differential pair */
/* - OPAMP trimming values of transistors differential pair */
#define OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL)
#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
* @{
*/
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFSET__ Offset to be applied (unit: number of registers).
* @retval Register address
*/
#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) \
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 1U))))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of OPAMP instance.
*/
typedef struct
{
uint32_t PowerMode; /*!< Set the power mode Normal or Low-Power and the speed mode Normal or High.
This parameter can be a value of @ref OPAMP_LL_EC_POWERMODE
This feature can be modified afterwards using
unitary function @ref LL_OPAMP_SetPowerMode(). */
uint32_t FunctionalMode; /*!< Set OPAMP functional mode by setting internal connections:
OPAMP operation in standalone, follower, ...
This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
@note If OPAMP is configured in mode PGA, the gain can be configured
using function @ref LL_OPAMP_SetPGAGain().
This feature can be modified afterwards using unitary
function @ref LL_OPAMP_SetFunctionalMode(). */
uint32_t InputNonInverting; /*!< Set OPAMP input non-inverting connection.
This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
This feature can be modified afterwards using
unitary function @ref LL_OPAMP_SetInputNonInverting(). */
uint32_t InputInverting; /*!< Set OPAMP inverting input connection.
This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
@note OPAMP inverting input is used with OPAMP in mode
standalone or PGA with external capacitors for filtering circuit.
Otherwise (OPAMP in mode follower), OPAMP inverting input is not used
(not connected to GPIO pin), this parameter is discarded.
This feature can be modified afterwards using
unitary function @ref LL_OPAMP_SetInputInverting(). */
} LL_OPAMP_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
* @{
*/
/** @defgroup OPAMP_LL_EC_POWERSUPPLY_RANGE OPAMP power supply range
* @{
*/
#define LL_OPAMP_POWERSUPPLY_RANGE_LOW 0x00000000U /*!< Power supply range low */
#define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP_CSR_OPARANGE) /*!< Power supply range high - recommended for performance purpose */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_POWERMODE OPAMP power mode
* @{
*/
#define LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED 0x00000000U /*!< OPAMP power mode normal speed normal */
#define LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED OPAMP_CSR_HSM /*!< OPAMP power mode normal speed high */
#define LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED OPAMP_CSR_OPALPM /*!< OPAMP power mode low-power speed normal */
#define LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED (OPAMP_CSR_OPALPM | OPAMP_CSR_HSM) /*!< OPAMP power mode low-power speed high */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
* @{
*/
#define LL_OPAMP_MODE_FUNCTIONAL 0x00000000U /*!< OPAMP functional mode */
#define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) /*!< OPAMP calibration mode */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
* @{
*/
#define LL_OPAMP_MODE_STANDALONE 0x00000000U /*!< OPAMP functional mode, OPAMP operation in standalone */
#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_OPAMODE_1 | OPAMP_CSR_OPAMODE_0) /*!< OPAMP functional mode, OPAMP operation in follower */
#define LL_OPAMP_MODE_PGA (OPAMP_CSR_OPAMODE_1) /*!< OPAMP functional mode, OPAMP operation in PGA */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
* @{
*/
#define LL_OPAMP_PGA_GAIN_2 0x00000000U /*!< OPAMP PGA gain 2 */
#define LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGA_GAIN_0) /*!< OPAMP PGA gain 4 */
#define LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGA_GAIN_1) /*!< OPAMP PGA gain 8 */
#define LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGA_GAIN_1 | OPAMP_CSR_PGA_GAIN_0) /*!< OPAMP PGA gain 16 */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
* @{
*/
#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */
#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (OPAMP_CSR_VP_SEL) /*!< OPAMP non inverting input connected to DAC1 channel output(channel1 for OPAMP1, channel2 for OPAMP2) */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
* @{
*/
#define LL_OPAMP_INPUT_INVERT_IO0 0x00000000U /*!< OPAMP inverting input connected to GPIO pin (valid also in PGA mode for filtering). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
#define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VM_SEL_0) /*!< OPAMP inverting input (low leakage input) connected to GPIO pin (available only on package BGA132). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VM_SEL_1) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering) */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_LEGACY OPAMP inputs legacy literals name
* @{
*/
#define LL_OPAMP_NONINVERTINGINPUT_IO0 LL_OPAMP_INPUT_NONINVERT_IO0
#define LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINV_DAC1_CH1
#define LL_OPAMP_INVERTINGINPUT_IO0 LL_OPAMP_INPUT_INVERT_IO0
#define LL_OPAMP_INVERTINGINPUT_IO1 LL_OPAMP_INPUT_INVERT_IO1
#define LL_OPAMP_INVERTINGINPUT_CONNECT_NO LL_OPAMP_INPUT_INVERT_CONNECT_NO
#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 LL_OPAMP_INPUT_NONINV_DAC1_CH1
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
* @{
*/
#define LL_OPAMP_TRIMMING_FACTORY 0x00000000U /*!< OPAMP trimming factors set to factory values */
#define LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM) /*!< OPAMP trimming factors set to user values */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
* @{
*/
#define LL_OPAMP_TRIMMING_NMOS (OPAMP_OTR_TRIMOFFSETN) /*!< OPAMP trimming of transistors differential pair NMOS */
#define LL_OPAMP_TRIMMING_PMOS (OPAMP_OTR_TRIMOFFSETP | OPAMP_CSR_CALSEL) /*!< OPAMP trimming of transistors differential pair PMOS */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays
* @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Delay for OPAMP startup time (transition from state disable to enable). */
/* Note: OPAMP startup time depends on board application environment: */
/* impedance connected to OPAMP output. */
/* The delay below is specified under conditions: */
/* - OPAMP in mode low power */
/* - OPAMP in functional mode follower */
/* - load impedance of 4kOhm (min), 50pF (max) */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
#define LL_OPAMP_DELAY_STARTUP_US ((uint32_t) 30U) /*!< Delay for OPAMP startup time */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
* @{
*/
/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
* @{
*/
/**
* @brief Write a value in OPAMP register
* @param __INSTANCE__ OPAMP Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in OPAMP register
* @param __INSTANCE__ OPAMP Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/** @defgroup OPAMP_LL_EM_HELPER_MACRO OPAMP helper macro
* @{
*/
/**
* @brief Helper macro to select the OPAMP common instance
* to which is belonging the selected OPAMP instance.
* @note OPAMP common register instance can be used to
* set parameters common to several OPAMP instances.
* Refer to functions having argument "OPAMPxy_COMMON" as parameter.
* @param __OPAMPx__ OPAMP instance
* @retval OPAMP common instance
*/
#if defined(OPAMP1) && defined(OPAMP2)
#define __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__) (OPAMP12_COMMON)
#endif /* defined(OPAMP1) && defined(OPAMP2) */
/**
* @brief Helper macro to check if all OPAMP instances sharing the same
* OPAMP common instance are disabled.
* @note This check is required by functions with setting conditioned to
* OPAMP state:
* All OPAMP instances of the OPAMP common group must be disabled.
* Refer to functions having argument "OPAMPxy_COMMON" as parameter.
* @retval 0: All OPAMP instances sharing the same OPAMP common instance
* are disabled.
* 1: At least one OPAMP instance sharing the same OPAMP common instance
* is enabled
*/
#if defined(OPAMP1) && defined(OPAMP2)
#define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE() \
(LL_OPAMP_IsEnabled(OPAMP1) | \
LL_OPAMP_IsEnabled(OPAMP2) )
#endif /* defined(OPAMP1) && defined(OPAMP2) */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
* @{
*/
/** @defgroup OPAMP_LL_EF_Configuration_opamp_common Configuration of OPAMP hierarchical scope: common OPAMP instances
* @{
*/
/**
* @brief Set OPAMP power range.
* @note The OPAMP power range applies to several OPAMP instances
* (if several OPAMP instances available on the selected device).
* It is mandatory to set already the power range to high for performance purpose.
* @note On this STM32 series, setting of this feature is conditioned to
* OPAMP state:
* All OPAMP instances of the OPAMP common group must be disabled.
* This check can be done with function @ref LL_OPAMP_IsEnabled() for each
* OPAMP instance.
* @note LL_OPAMP_POWERSUPPLY_RANGE_HIGH parameter is highly recommended for performance purpose.
* @rmtoll CSR OPARANGE LL_OPAMP_SetCommonPowerRange
* @param OPAMPxy_COMMON OPAMP common instance
* @param PowerRange This parameter can be one of the following values:
* @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW
* @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange)
{
/* Prevent unused parameter warning */
(void)(*OPAMPxy_COMMON);
MODIFY_REG(OPAMP1->CSR, OPAMP_CSR_OPARANGE, PowerRange);
}
/**
* @brief Get OPAMP power range.
* @note The OPAMP power range applies to several OPAMP instances
* (if several OPAMP instances available on the selected device).
* @rmtoll CSR OPARANGE LL_OPAMP_GetCommonPowerRange
* @param OPAMPxy_COMMON OPAMP common instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW
* @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON)
{
/* Prevent unused parameter warning */
(void)(*OPAMPxy_COMMON);
return (uint32_t)(READ_BIT(OPAMP1->CSR, OPAMP_CSR_OPARANGE));
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
* @{
*/
/**
* @brief Set OPAMP power mode.
* @note The OPAMP must be disabled to change this configuration.
* @rmtoll CSR OPALPM LL_OPAMP_SetPowerMode
* @param OPAMPx OPAMP instance
* @param PowerMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED
* @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_POWERMODE_CSR_BIT_MASK, PowerMode);
}
/**
* @brief Get OPAMP power mode.
* @rmtoll CSR OPALPM & HSM LL_OPAMP_GetPowerMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED
* @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
{
uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_POWERMODE_CSR_BIT_MASK));
return (uint32_t)(power_mode);
}
/**
* @brief Set OPAMP mode calibration or functional.
* @note OPAMP mode corresponds to functional or calibration mode:
* - functional mode: OPAMP operation in standalone, follower, ...
* Set functional mode using function
* @ref LL_OPAMP_SetFunctionalMode().
* - calibration mode: offset calibration of the selected
* transistors differential pair NMOS or PMOS.
* @note On this STM32 series, during calibration, OPAMP functional
* mode must be set to standalone or follower mode
* (in order to open internal connections to resistors
* of PGA mode).
* Refer to function @ref LL_OPAMP_SetFunctionalMode().
* @rmtoll CSR CALON LL_OPAMP_SetMode
* @param OPAMPx OPAMP instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_MODE_FUNCTIONAL
* @arg @ref LL_OPAMP_MODE_CALIBRATION
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
}
/**
* @brief Get OPAMP mode calibration or functional.
* @note OPAMP mode corresponds to functional or calibration mode:
* - functional mode: OPAMP operation in standalone, follower, ...
* Set functional mode using function
* @ref LL_OPAMP_SetFunctionalMode().
* - calibration mode: offset calibration of the selected
* transistors differential pair NMOS or PMOS.
* @rmtoll CSR CALON LL_OPAMP_GetMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_MODE_FUNCTIONAL
* @arg @ref LL_OPAMP_MODE_CALIBRATION
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
}
/**
* @brief Set OPAMP functional mode by setting internal connections.
* OPAMP operation in standalone, follower, ...
* @note This function reset bit of calibration mode to ensure
* to be in functional mode, in order to have OPAMP parameters
* (inputs selection, ...) set with the corresponding OPAMP mode
* to be effective.
* @rmtoll CSR OPAMODE LL_OPAMP_SetFunctionalMode
* @param OPAMPx OPAMP instance
* @param FunctionalMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_MODE_STANDALONE
* @arg @ref LL_OPAMP_MODE_FOLLOWER
* @arg @ref LL_OPAMP_MODE_PGA
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
{
/* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPAMODE | OPAMP_CSR_CALON, FunctionalMode);
}
/**
* @brief Get OPAMP functional mode from setting of internal connections.
* OPAMP operation in standalone, follower, ...
* @rmtoll CSR OPAMODE LL_OPAMP_GetFunctionalMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_MODE_STANDALONE
* @arg @ref LL_OPAMP_MODE_FOLLOWER
* @arg @ref LL_OPAMP_MODE_PGA
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMODE));
}
/**
* @brief Set OPAMP PGA gain.
* @note Preliminarily, OPAMP must be set in mode PGA
* using function @ref LL_OPAMP_SetFunctionalMode().
* @rmtoll CSR PGGAIN LL_OPAMP_SetPGAGain
* @param OPAMPx OPAMP instance
* @param PGAGain This parameter can be one of the following values:
* @arg @ref LL_OPAMP_PGA_GAIN_2
* @arg @ref LL_OPAMP_PGA_GAIN_4
* @arg @ref LL_OPAMP_PGA_GAIN_8
* @arg @ref LL_OPAMP_PGA_GAIN_16
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGA_GAIN, PGAGain);
}
/**
* @brief Get OPAMP PGA gain.
* @note Preliminarily, OPAMP must be set in mode PGA
* using function @ref LL_OPAMP_SetFunctionalMode().
* @rmtoll CSR PGGAIN LL_OPAMP_GetPGAGain
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_PGA_GAIN_2
* @arg @ref LL_OPAMP_PGA_GAIN_4
* @arg @ref LL_OPAMP_PGA_GAIN_8
* @arg @ref LL_OPAMP_PGA_GAIN_16
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGA_GAIN));
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
* @{
*/
/**
* @brief Set OPAMP non-inverting input connection.
* @rmtoll CSR VPSEL LL_OPAMP_SetInputNonInverting
* @param OPAMPx OPAMP instance
* @param InputNonInverting This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
* @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VP_SEL, InputNonInverting);
}
/**
* @brief Get OPAMP non-inverting input connection.
* @rmtoll CSR VPSEL LL_OPAMP_GetInputNonInverting
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
* @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VP_SEL));
}
/**
* @brief Set OPAMP inverting input connection.
* @note OPAMP inverting input is used with OPAMP in mode standalone
* or PGA with external capacitors for filtering circuit.
* Otherwise (OPAMP in mode follower), OPAMP inverting input
* is not used (not connected to GPIO pin).
* @rmtoll CSR VMSEL LL_OPAMP_SetInputInverting
* @param OPAMPx OPAMP instance
* @param InputInverting This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_INVERT_IO0
* @arg @ref LL_OPAMP_INPUT_INVERT_IO1
* @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VM_SEL, InputInverting);
}
/**
* @brief Get OPAMP inverting input connection.
* @rmtoll CSR VMSEL LL_OPAMP_GetInputInverting
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_INVERT_IO0
* @arg @ref LL_OPAMP_INPUT_INVERT_IO1
* @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VM_SEL));
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_Configuration_Legacy_Functions Configuration of OPAMP, legacy functions name
* @{
*/
/* Old functions name kept for legacy purpose, to be replaced by the */
/* current functions name. */
__STATIC_INLINE void LL_OPAMP_SetNonInvertingInput(OPAMP_TypeDef *OPAMPx, uint32_t NonInvertingInput)
{
LL_OPAMP_SetInputNonInverting(OPAMPx, NonInvertingInput);
}
__STATIC_INLINE void LL_OPAMP_SetInvertingInput(OPAMP_TypeDef *OPAMPx, uint32_t InvertingInput)
{
LL_OPAMP_SetInputInverting(OPAMPx, InvertingInput);
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
* @{
*/
/**
* @brief Set OPAMP trimming mode.
* @rmtoll CSR USERTRIM LL_OPAMP_SetTrimmingMode
* @param OPAMPx OPAMP instance
* @param TrimmingMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_FACTORY
* @arg @ref LL_OPAMP_TRIMMING_USER
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
}
/**
* @brief Get OPAMP trimming mode.
* @rmtoll CSR USERTRIM LL_OPAMP_GetTrimmingMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_FACTORY
* @arg @ref LL_OPAMP_TRIMMING_USER
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
}
/**
* @brief Set OPAMP offset to calibrate the selected transistors
* differential pair NMOS or PMOS.
* @note Preliminarily, OPAMP must be set in mode calibration
* using function @ref LL_OPAMP_SetMode().
* @rmtoll CSR CALSEL LL_OPAMP_SetCalibrationSelection
* @param OPAMPx OPAMP instance
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS
* @arg @ref LL_OPAMP_TRIMMING_PMOS
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
{
/* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because */
/* containing other bits reserved for other purpose. */
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
}
/**
* @brief Get OPAMP offset to calibrate the selected transistors
* differential pair NMOS or PMOS.
* @note Preliminarily, OPAMP must be set in mode calibration
* using function @ref LL_OPAMP_SetMode().
* @rmtoll CSR CALSEL LL_OPAMP_GetCalibrationSelection
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS
* @arg @ref LL_OPAMP_TRIMMING_PMOS
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
{
uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
return (CalibrationSelection |
(((CalibrationSelection & OPAMP_CSR_CALSEL) == 0UL) ? OPAMP_OTR_TRIMOFFSETN : OPAMP_OTR_TRIMOFFSETP));
}
/**
* @brief Get OPAMP calibration result of toggling output.
* @note This functions returns:
* 0 if OPAMP calibration output is reset
* 1 if OPAMP calibration output is set
* @rmtoll CSR CALOUT LL_OPAMP_IsCalibrationOutputSet
* @param OPAMPx OPAMP instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
{
return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT) ? 1UL : 0UL);
}
/**
* @brief Set OPAMP trimming factor for the selected transistors
* differential pair NMOS or PMOS, corresponding to the selected
* power mode.
* @rmtoll OTR TRIMOFFSETN LL_OPAMP_SetTrimmingValue
* OTR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
* LPOTR TRIMLPOFFSETN LL_OPAMP_SetTrimmingValue
* LPOTR TRIMLPOFFSETP LL_OPAMP_SetTrimmingValue
* @param OPAMPx OPAMP instance
* @param PowerMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED
* @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS
* @arg @ref LL_OPAMP_TRIMMING_PMOS
* @param TrimmingValue 0x00...0x1F
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair,
uint32_t TrimmingValue)
{
__IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
/* Set bits with position in register depending on parameter */
/* "TransistorsDiffPair". */
/* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */
/* containing other bits reserved for other purpose. */
MODIFY_REG(*preg,
(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
TrimmingValue << (
(TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos)
);
}
/**
* @brief Get OPAMP trimming factor for the selected transistors
* differential pair NMOS or PMOS, corresponding to the selected
* power mode.
* @rmtoll OTR TRIMOFFSETN LL_OPAMP_GetTrimmingValue
* OTR TRIMOFFSETP LL_OPAMP_GetTrimmingValue
* LPOTR TRIMLPOFFSETN LL_OPAMP_GetTrimmingValue
* LPOTR TRIMLPOFFSETP LL_OPAMP_GetTrimmingValue
* @param OPAMPx OPAMP instance
* @param PowerMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED
* @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_NORMALSPEED
* @arg @ref LL_OPAMP_POWERMODE_LOWPOWER_HIGHSPEED
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS
* @arg @ref LL_OPAMP_TRIMMING_PMOS
* @retval 0x0...0x1F
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode,
uint32_t TransistorsDiffPair)
{
const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
/* Retrieve bits with position in register depending on parameter */
/* "TransistorsDiffPair". */
/* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because */
/* containing other bits reserved for other purpose. */
return (uint32_t)(
READ_BIT(*preg, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK)) >>
(
(TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos));
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
* @{
*/
/**
* @brief Enable OPAMP instance.
* @note After enable from off state, OPAMP requires a delay
* to fulfill wake up time specification.
* Refer to device datasheet, parameter "tWAKEUP".
* @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
* @param OPAMPx OPAMP instance
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
{
SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAEN);
}
/**
* @brief Disable OPAMP instance.
* @rmtoll CSR OPAMPXEN LL_OPAMP_Disable
* @param OPAMPx OPAMP instance
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
{
CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAEN);
}
/**
* @brief Get OPAMP instance enable state
* (0: OPAMP is disabled, 1: OPAMP is enabled)
* @rmtoll CSR OPAMPXEN LL_OPAMP_IsEnabled
* @param OPAMPx OPAMP instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
{
return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAEN) == (OPAMP_CSR_OPAEN)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* OPAMP1 || OPAMP2 */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_OPAMP_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h
|
C
|
apache-2.0
| 35,601
|
/**
******************************************************************************
* @file stm32u5xx_ll_pka.h
* @author MCD Application Team
* @brief Header file of PKA LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_PKA_H
#define STM32U5xx_LL_PKA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(PKA)
/** @defgroup PKA_LL PKA
* @{
*/
/* Private variables ---------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup PKA_LL_ES_INIT PKA Exported Init structure
* @{
*/
/**
* @brief PKA Init structures definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the PKA operation mode.
This parameter can be a value of @ref PKA_LL_EC_MODE.
This feature can be modified afterwards using unitary function @ref LL_PKA_SetMode(). */
} LL_PKA_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup PKA_LL_Exported_Constants PKA Exported Constants
* @{
*/
/** @defgroup PKA_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_PKA_ReadReg function
* @{
*/
#define LL_PKA_SR_ADDRERRF PKA_SR_ADDRERRF
#define LL_PKA_SR_RAMERRF PKA_SR_RAMERRF
#define LL_PKA_SR_PROCENDF PKA_SR_PROCENDF
#define LL_PKA_SR_BUSY PKA_SR_BUSY
#define LL_PKA_SR_INITOK PKA_SR_INITOK
#define LL_PKA_SR_OPERRF PKA_SR_OPERRF
/**
* @}
*/
/** @defgroup PKA_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_PKA_ReadReg and LL_PKA_WriteReg functions
* @{
*/
#define LL_PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE
#define LL_PKA_CR_RAMERRIE PKA_CR_RAMERRIE
#define LL_PKA_CR_PROCENDIE PKA_CR_PROCENDIE
#define LL_PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC
#define LL_PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC
#define LL_PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC
#define LL_PKA_CR_OPERRIE PKA_CR_OPERRIE
#define LL_PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC
/**
* @}
*/
/** @defgroup PKA_LL_EC_MODE Operation Mode
* @brief List of operation mode.
* @{
*/
#define LL_PKA_MODE_MODULAR_EXP ((uint32_t)0x00000000U) /*!< modular exponentiation */
#define LL_PKA_MODE_MONTGOMERY_PARAM ((uint32_t)0x00000001U) /*!< Compute Montgomery parameter only */
#define LL_PKA_MODE_MODULAR_EXP_FAST ((uint32_t)0x00000002U) /*!< modular exponentiation fast mode */
#define LL_PKA_MODE_MODULAR_EXP_PROTECT ((uint32_t)0x00000003U) /*!< modular exponentiation protect mode */
#define LL_PKA_MODE_ECC_MUL ((uint32_t)0x00000020U) /*!< compute ECC kP operation */
#define LL_PKA_MODE_ECC_COMPLETE_ADD ((uint32_t)0x00000023U) /*!< ECC complete addition */
#define LL_PKA_MODE_ECDSA_SIGNATURE ((uint32_t)0x00000024U) /*!< ECDSA signature */
#define LL_PKA_MODE_ECDSA_VERIFICATION ((uint32_t)0x00000026U) /*!< ECDSA verification */
#define LL_PKA_MODE_POINT_CHECK ((uint32_t)0x00000028U) /*!< Point check */
#define LL_PKA_MODE_RSA_CRT_EXP ((uint32_t)0x00000007U) /*!< RSA CRT exponentiation */
#define LL_PKA_MODE_MODULAR_INV ((uint32_t)0x00000008U) /*!< Modular inversion */
#define LL_PKA_MODE_ARITHMETIC_ADD ((uint32_t)0x00000009U) /*!< Arithmetic addition */
#define LL_PKA_MODE_ARITHMETIC_SUB ((uint32_t)0x0000000AU) /*!< Arithmetic subtraction */
#define LL_PKA_MODE_ARITHMETIC_MUL ((uint32_t)0x0000000BU) /*!< Arithmetic multiplication */
#define LL_PKA_MODE_COMPARISON ((uint32_t)0x0000000CU) /*!< Comparison */
#define LL_PKA_MODE_MODULAR_REDUC ((uint32_t)0x0000000DU) /*!< Modular reduction */
#define LL_PKA_MODE_MODULAR_ADD ((uint32_t)0x0000000EU) /*!< Modular addition */
#define LL_PKA_MODE_MODULAR_SUB ((uint32_t)0x0000000FU) /*!< Modular subtraction */
#define LL_PKA_MODE_MONTGOMERY_MUL ((uint32_t)0x00000010U) /*!< Montgomery multiplication */
#define LL_PKA_MODE_DOUBLE_BASE_LADDER ((uint32_t)0x00000027U) /*!< Double base ladder */
#define LL_PKA_MODE_ECC_PROJECTIVE_AFF ((uint32_t)0x0000002FU) /*!< ECC projective to affine */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PKA_LL_Exported_Macros PKA Exported Macros
* @{
*/
/** @defgroup PKA_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in PKA register
* @param __INSTANCE__ PKA Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_PKA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in PKA register
* @param __INSTANCE__ PKA Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_PKA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PKA_LL_Exported_Functions PKA Exported Functions
* @{
*/
/** @defgroup PKA_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Configure PKA peripheral.
* @brief Set PKA operating mode.
* @rmtoll CR MODE LL_PKA_Config
* @param PKAx PKA Instance.
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
* @arg @ref LL_PKA_MODE_MODULAR_EXP
* @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
* @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
* @arg @ref LL_PKA_MODE_POINT_CHECK
* @arg @ref LL_PKA_MODE_RSA_CRT_EXP
* @arg @ref LL_PKA_MODE_MODULAR_INV
* @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
* @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
* @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
* @arg @ref LL_PKA_MODE_COMPARISON
* @arg @ref LL_PKA_MODE_MODULAR_REDUC
* @arg @ref LL_PKA_MODE_MODULAR_ADD
* @arg @ref LL_PKA_MODE_MODULAR_SUB
* @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
* @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT
* @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER
* @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF
* @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD
* @arg @ref LL_PKA_MODE_ECC_MUL
* @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST
*/
__STATIC_INLINE void LL_PKA_Config(PKA_TypeDef *PKAx, uint32_t Mode)
{
MODIFY_REG(PKAx->CR, (PKA_CR_MODE), (Mode << PKA_CR_MODE_Pos));
}
/**
* @brief Enable PKA peripheral.
* @rmtoll CR EN LL_PKA_Enable
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_Enable(PKA_TypeDef *PKAx)
{
SET_BIT(PKAx->CR, PKA_CR_EN);
}
/**
* @brief Disable PKA peripheral.
* @rmtoll CR EN LL_PKA_Disable
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *PKAx)
{
CLEAR_BIT(PKAx->CR, PKA_CR_EN);
}
/**
* @brief Check if the PKA peripheral is enabled or disabled.
* @rmtoll CR EN LL_PKA_IsEnabled
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PKA_IsEnabled(PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL);
}
/**
* @brief Set PKA operating mode.
* @rmtoll CR MODE LL_PKA_SetMode
* @param PKAx PKA Instance.
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
* @arg @ref LL_PKA_MODE_MODULAR_EXP
* @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
* @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
* @arg @ref LL_PKA_MODE_POINT_CHECK
* @arg @ref LL_PKA_MODE_RSA_CRT_EXP
* @arg @ref LL_PKA_MODE_MODULAR_INV
* @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
* @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
* @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
* @arg @ref LL_PKA_MODE_COMPARISON
* @arg @ref LL_PKA_MODE_MODULAR_REDUC
* @arg @ref LL_PKA_MODE_MODULAR_ADD
* @arg @ref LL_PKA_MODE_MODULAR_SUB
* @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
* @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT
* @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER
* @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF
* @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD
* @arg @ref LL_PKA_MODE_ECC_MUL
* @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST
* @retval None
*/
__STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode)
{
MODIFY_REG(PKAx->CR, PKA_CR_MODE, Mode << PKA_CR_MODE_Pos);
}
/**
* @brief Get PKA operating mode.
* @rmtoll CR MODE LL_PKA_GetMode
* @param PKAx PKA Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM
* @arg @ref LL_PKA_MODE_MODULAR_EXP
* @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE
* @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION
* @arg @ref LL_PKA_MODE_POINT_CHECK
* @arg @ref LL_PKA_MODE_RSA_CRT_EXP
* @arg @ref LL_PKA_MODE_MODULAR_INV
* @arg @ref LL_PKA_MODE_ARITHMETIC_ADD
* @arg @ref LL_PKA_MODE_ARITHMETIC_SUB
* @arg @ref LL_PKA_MODE_ARITHMETIC_MUL
* @arg @ref LL_PKA_MODE_COMPARISON
* @arg @ref LL_PKA_MODE_MODULAR_REDUC
* @arg @ref LL_PKA_MODE_MODULAR_ADD
* @arg @ref LL_PKA_MODE_MODULAR_SUB
* @arg @ref LL_PKA_MODE_MONTGOMERY_MUL
* @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT
* @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER
* @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF
* @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD
* @arg @ref LL_PKA_MODE_ECC_MUL
* @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST
*/
__STATIC_INLINE uint32_t LL_PKA_GetMode(PKA_TypeDef *PKAx)
{
return (uint32_t)(READ_BIT(PKAx->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
}
/**
* @brief Start the operation selected using LL_PKA_SetMode.
* @rmtoll CR START LL_PKA_Start
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_Start(PKA_TypeDef *PKAx)
{
SET_BIT(PKAx->CR, PKA_CR_START);
}
/**
* @}
*/
/** @defgroup PKA_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable address error interrupt.
* @rmtoll CR ADDRERRIE LL_PKA_EnableIT_ADDRERR
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_EnableIT_ADDRERR(PKA_TypeDef *PKAx)
{
SET_BIT(PKAx->CR, PKA_CR_ADDRERRIE);
}
/**
* @brief Enable RAM error interrupt.
* @rmtoll CR RAMERRIE LL_PKA_EnableIT_RAMERR
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_EnableIT_RAMERR(PKA_TypeDef *PKAx)
{
SET_BIT(PKAx->CR, PKA_CR_RAMERRIE);
}
/**
* @brief Enable OPERATION error interrupt.
* @rmtoll CR OPERRIE LL_PKA_EnableIT_OPERR
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_EnableIT_OPERR(PKA_TypeDef *PKAx)
{
SET_BIT(PKAx->CR, PKA_CR_OPERRIE);
}
/**
* @brief Enable end of operation interrupt.
* @rmtoll CR PROCENDIE LL_PKA_EnableIT_PROCEND
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_EnableIT_PROCEND(PKA_TypeDef *PKAx)
{
SET_BIT(PKAx->CR, PKA_CR_PROCENDIE);
}
/**
* @brief Disable address error interrupt.
* @rmtoll CR ADDRERRIE LL_PKA_DisableIT_ADDERR
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_DisableIT_ADDERR(PKA_TypeDef *PKAx)
{
CLEAR_BIT(PKAx->CR, PKA_CR_ADDRERRIE);
}
/**
* @brief Disable RAM error interrupt.
* @rmtoll CR RAMERRIE LL_PKA_DisableIT_RAMERR
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_DisableIT_RAMERR(PKA_TypeDef *PKAx)
{
CLEAR_BIT(PKAx->CR, PKA_CR_RAMERRIE);
}
/**
* @brief Disable End of operation interrupt.
* @rmtoll CR PROCENDIE LL_PKA_DisableIT_PROCEND
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_DisableIT_PROCEND(PKA_TypeDef *PKAx)
{
CLEAR_BIT(PKAx->CR, PKA_CR_PROCENDIE);
}
/**
* @brief Disable OPERATION error interrupt.
* @rmtoll CR OPERRIE LL_PKA_EnableIT_OPERR
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_DisableIT_OPERR(PKA_TypeDef *PKAx)
{
CLEAR_BIT(PKAx->CR, PKA_CR_OPERRIE);
}
/**
* @brief Check if address error interrupt is enabled.
* @rmtoll CR ADDRERRIE LL_PKA_IsEnabledIT_ADDRERR
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL);
}
/**
* @brief Check if RAM error interrupt is enabled.
* @rmtoll CR RAMERRIE LL_PKA_IsEnabledIT_RAMERR
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL);
}
/**
* @brief Check if OPERATION error interrupt is enabled.
* @rmtoll CR OPERRIE LL_PKA_IsEnabledIT_OPERR
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_OPERR(PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->CR, PKA_CR_OPERRIE) == (PKA_CR_OPERRIE)) ? 1UL : 0UL);
}
/**
* @brief Check if end of operation interrupt is enabled.
* @rmtoll CR PROCENDIE LL_PKA_IsEnabledIT_PROCEND
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup PKA_LL_EF_FLAG_Management PKA flag management
* @{
*/
/**
* @brief Get PKA address error flag.
* @rmtoll SR ADDRERRF LL_PKA_IsActiveFlag_ADDRERR
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL);
}
/**
* @brief Get PKA RAM error flag.
* @rmtoll SR RAMERRF LL_PKA_IsActiveFlag_RAMERR
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL);
}
/**
* @brief Get PKA OPERATION error flag.
* @rmtoll SR OPERRF LL_PKA_IsActiveFlag_OPERR
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_OPERR(PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->SR, PKA_SR_OPERRF) == (PKA_SR_OPERRF)) ? 1UL : 0UL);
}
/**
* @brief Get PKA end of operation flag.
* @rmtoll SR PROCENDF LL_PKA_IsActiveFlag_PROCEND
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL);
}
/**
* @brief Get PKA busy flag.
* @rmtoll SR BUSY LL_PKA_IsActiveFlag_BUSY
* @param PKAx PKA Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(PKA_TypeDef *PKAx)
{
return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL);
}
/**
* @brief Clear PKA address error flag.
* @rmtoll CLRFR ADDRERRFC LL_PKA_ClearFlag_ADDERR
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_ClearFlag_ADDERR(PKA_TypeDef *PKAx)
{
SET_BIT(PKAx->CLRFR, PKA_CLRFR_ADDRERRFC);
}
/**
* @brief Clear PKA RAM error flag.
* @rmtoll CLRFR RAMERRFC LL_PKA_ClearFlag_RAMERR
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_ClearFlag_RAMERR(PKA_TypeDef *PKAx)
{
SET_BIT(PKAx->CLRFR, PKA_CLRFR_RAMERRFC);
}
/**
* @brief Clear PKA OPERATION error flag.
* @rmtoll CLRFR OPERRFC LL_PKA_ClearFlag_OPERR
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_ClearFlag_OPERR(PKA_TypeDef *PKAx)
{
SET_BIT(PKAx->CLRFR, PKA_CLRFR_OPERRFC);
}
/**
* @brief Clear PKA end of operation flag.
* @rmtoll CLRFR PROCENDFC LL_PKA_ClearFlag_PROCEND
* @param PKAx PKA Instance.
* @retval None
*/
__STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *PKAx)
{
SET_BIT(PKAx->CLRFR, PKA_CLRFR_PROCENDFC);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup PKA_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx);
ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct);
void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PKA) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_PKA_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pka.h
|
C
|
apache-2.0
| 18,583
|
/**
******************************************************************************
* @file stm32u5xx_ll_pwr.h
* @author MCD Application Team
* @brief Header file of PWR LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_PWR_H
#define STM32U5xx_LL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (PWR)
/** @defgroup PWR_LL PWR
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_PWR_WriteReg function
* @{
*/
#define LL_PWR_SR_CSSF PWR_SR_CSSF /*!< Clear Stop and Standby flags */
#define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */
#define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */
#define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */
#define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */
#define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */
#define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */
#define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */
#define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */
#define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */
/**
* @}
*/
/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_PWR_ReadReg function
* @{
*/
#define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */
#define LL_PWR_FLAG_BOOSTRDY PWR_VOSR_BOOSTRDY /*!< VOS EPOD booster ready flag */
#if defined (PWR_VOSR_USBBOOSTRDY)
#define LL_PWR_FLAG_USBBOOSTRDY PWR_VOSR_USBBOOSTRDY /*!< USB EPOD booster ready flag */
#endif /* defined (PWR_VOSR_USBBOOSTRDY) */
#define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */
#define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */
#define LL_PWR_FLAG_VDDA2RDY PWR_SVMSR_VDDA2RDY /*!< VDDA ready flag (versus 1.8 V threshold) */
#define LL_PWR_FLAG_VDDA1RDY PWR_SVMSR_VDDA1RDY /*!< VDDA ready flag (versus 1.6 V threshold) */
#define LL_PWR_FLAG_VDDIO2RDY PWR_SVMSR_VDDIO2RDY /*!< VDDIO2 ready flag */
#define LL_PWR_FLAG_VDDUSBRDY PWR_SVMSR_VDDUSBRDY /*!< VDDUSB ready flag */
#define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */
#define LL_PWR_FLAG_PVDO PWR_SR2_PVDO /*!< VDD voltage detector output flag */
#define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */
#define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */
#define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */
#define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< Backup domain voltage level flag (versus high threshold) */
#define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */
#define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */
#define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */
#define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */
#define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */
#define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */
#define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */
#define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */
/**
* @}
*/
/** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELCTION Low Power Mode Selection
* @{
*/
#define LL_PWR_STOP0_MODE (0U) /*!< Stop 0 mode */
#define LL_PWR_STOP1_MODE PWR_CR1_LPMS_0 /*!< Stop 1 mode */
#define LL_PWR_STOP2_MODE PWR_CR1_LPMS_1 /*!< Stop 2 mode */
#define LL_PWR_STOP3_MODE (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Stop 3 mode */
#define LL_PWR_STANDBY_MODE PWR_CR1_LPMS_2 /*!< Standby mode */
#define LL_PWR_SHUTDOWN_MODE (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1) /*!< Shutdown mode */
/**
* @}
*/
/** @defgroup PWR_LL_EC_SRAM2_SB_CONTENTS_RETENTION PWR SRAM2 Content Retention in Standby Mode
* @note For some products of the U5 family (please see the Reference Manual),
* the SRAM2 content is preserved based on the same defines in Stop 3 mode.
* @{
*/
#define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Stop 3 and Standby mode */
#define LL_PWR_SRAM2_SB_PAGE1_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby mode */
#define LL_PWR_SRAM2_SB_PAGE2_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby mode */
#define LL_PWR_SRAM2_SB_FULL_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby mode */
/**
* @}
*/
/** @defgroup PWR_LL_EC_SRAM1_STOP_CONTENTS_RETENTION PWR SRAM1 Content Retention in Stop Mode
* @{
*/
#define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE1_RETENTION (PWR_CR2_SRAM1PDS1) /*!< SRAM1 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE2_RETENTION (PWR_CR2_SRAM1PDS2) /*!< SRAM1 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE3_RETENTION (PWR_CR2_SRAM1PDS3) /*!< SRAM1 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#if defined (PWR_CR4_SRAM1PDS4)
#define LL_PWR_SRAM1_STOP_PAGE4_RETENTION (PWR_CR4_SRAM1PDS4) /*!< SRAM1 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE5_RETENTION (PWR_CR4_SRAM1PDS5) /*!< SRAM1 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE6_RETENTION (PWR_CR4_SRAM1PDS6) /*!< SRAM1 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE7_RETENTION (PWR_CR4_SRAM1PDS7) /*!< SRAM1 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE8_RETENTION (PWR_CR4_SRAM1PDS8) /*!< SRAM1 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE9_RETENTION (PWR_CR4_SRAM1PDS9) /*!< SRAM1 page 9 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE10_RETENTION (PWR_CR4_SRAM1PDS10) /*!< SRAM1 page 10 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE11_RETENTION (PWR_CR4_SRAM1PDS11) /*!< SRAM1 page 11 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM1_STOP_PAGE12_RETENTION (PWR_CR4_SRAM1PDS12) /*!< SRAM1 page 12 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#endif /* defined (PWR_CR4_SRAM1PDS4) */
#define LL_PWR_SRAM1_STOP_1_3_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | \
PWR_CR2_SRAM1PDS3) /*!< SRAM1 pages (1 to 3) retention in Stop mode (Stop 0, 1, 2, 3) */
#if defined (PWR_CR4_SRAM1PDS4)
#define LL_PWR_SRAM1_STOP_4_12_RETENTION (PWR_CR4_SRAM1PDS4 | PWR_CR4_SRAM1PDS5 | \
PWR_CR4_SRAM1PDS6 | PWR_CR4_SRAM1PDS7 | \
PWR_CR4_SRAM1PDS8 | PWR_CR4_SRAM1PDS9 | \
PWR_CR4_SRAM1PDS10 | PWR_CR4_SRAM1PDS11 | \
PWR_CR4_SRAM1PDS12) /*!< SRAM1 pages (4 to 12) retention in Stop mode (Stop 0, 1, 2, 3) */
#endif /* defined (PWR_CR4_SRAM1PDS4) */
/**
* @}
*/
/** @defgroup PWR_LL_EC_SRAM2_STOP_CONTENTS_RETENTION PWR SRAM2 Content Retention in Stop Mode
* @{
*/
#define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_SRAM2_STOP_PAGE1_RETENTION (PWR_CR2_SRAM2PDS1) /*!< SRAM2 page 1 (8 KB) retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_SRAM2_STOP_PAGE2_RETENTION (PWR_CR2_SRAM2PDS2) /*!< SRAM2 page 2 (54 KB) retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_SRAM2_STOP_FULL_RETENTION (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2) /*!< SRAM2 all pages retention in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
/** @defgroup PWR_LL_EC_SRAM3_STOP_CONTENTS_RETENTION PWR SRAM3 Content Retention in Stop Mode
* @{
*/
#define LL_PWR_SRAM3_STOP_NO_RETENTION 0U /*!< SRAM3 no retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE1_RETENTION (PWR_CR2_SRAM3PDS1) /*!< SRAM3 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE2_RETENTION (PWR_CR2_SRAM3PDS2) /*!< SRAM3 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE3_RETENTION (PWR_CR2_SRAM3PDS3) /*!< SRAM3 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE4_RETENTION (PWR_CR2_SRAM3PDS4) /*!< SRAM3 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE5_RETENTION (PWR_CR2_SRAM3PDS5) /*!< SRAM3 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE6_RETENTION (PWR_CR2_SRAM3PDS6) /*!< SRAM3 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE7_RETENTION (PWR_CR2_SRAM3PDS7) /*!< SRAM3 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE8_RETENTION (PWR_CR2_SRAM3PDS8) /*!< SRAM3 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#if defined (PWR_CR4_SRAM3PDS9)
#define LL_PWR_SRAM3_STOP_PAGE9_RETENTION (PWR_CR4_SRAM3PDS9) /*!< SRAM3 page 9 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE10_RETENTION (PWR_CR4_SRAM3PDS10) /*!< SRAM3 page 10 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE11_RETENTION (PWR_CR4_SRAM3PDS11) /*!< SRAM3 page 11 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE12_RETENTION (PWR_CR4_SRAM3PDS12) /*!< SRAM3 page 12 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM3_STOP_PAGE13_RETENTION (PWR_CR4_SRAM3PDS13) /*!< SRAM3 page 13 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#endif /* defined (PWR_CR4_SRAM3PDS9) */
#define LL_PWR_SRAM3_STOP_1_8_RETENTION (PWR_CR2_SRAM3PDS1 | PWR_CR2_SRAM3PDS2 | PWR_CR2_SRAM3PDS3 | \
PWR_CR2_SRAM3PDS4 | PWR_CR2_SRAM3PDS5 | PWR_CR2_SRAM3PDS6 | \
PWR_CR2_SRAM3PDS7 | PWR_CR2_SRAM3PDS8) /*!< SRAM3 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */
#if defined (PWR_CR4_SRAM3PDS9)
#define LL_PWR_SRAM3_STOP_9_13_RETENTION (PWR_CR4_SRAM3PDS9 | PWR_CR4_SRAM3PDS10 | PWR_CR4_SRAM3PDS11 | \
PWR_CR4_SRAM3PDS12 | PWR_CR4_SRAM3PDS13) /*!< SRAM3 pages (9 to 13) retention in Stop modes (Stop 0, 1, 2, 3) */
#endif /* defined (PWR_CR4_SRAM3PDS9) */
/**
* @}
*/
/** @defgroup PWR_LL_EC_SRAM4_STOP_CONTENTS_RETENTION PWR SRAM4 Content Retention in Stop Mode
* @{
*/
#define LL_PWR_SRAM4_STOP_NO_RETENTION 0U /*!< SRAM4 no retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_SRAM4_STOP_FULL_RETENTION PWR_CR2_SRAM4PDS /*!< SRAM4 retention in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
#if defined (PWR_CR4_SRAM5PDS1)
/** @defgroup PWR_LL_EC_SRAM5_STOP_CONTENTS_RETENTION PWR SRAM5 Content Retention in Stop Mode
* @{
*/
#define LL_PWR_SRAM5_STOP_NO_RETENTION 0U /*!< SRAM5 no retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE1_RETENTION (PWR_CR4_SRAM5PDS1) /*!< SRAM5 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE2_RETENTION (PWR_CR4_SRAM5PDS2) /*!< SRAM5 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE3_RETENTION (PWR_CR4_SRAM5PDS3) /*!< SRAM5 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE4_RETENTION (PWR_CR4_SRAM5PDS4) /*!< SRAM5 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE5_RETENTION (PWR_CR4_SRAM5PDS5) /*!< SRAM5 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE6_RETENTION (PWR_CR4_SRAM5PDS6) /*!< SRAM5 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE7_RETENTION (PWR_CR4_SRAM5PDS7) /*!< SRAM5 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE8_RETENTION (PWR_CR4_SRAM5PDS8) /*!< SRAM5 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE9_RETENTION (PWR_CR4_SRAM5PDS9) /*!< SRAM5 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE10_RETENTION (PWR_CR4_SRAM5PDS10) /*!< SRAM5 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE11_RETENTION (PWR_CR4_SRAM5PDS11) /*!< SRAM5 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE12_RETENTION (PWR_CR4_SRAM5PDS12) /*!< SRAM5 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_PAGE13_RETENTION (PWR_CR4_SRAM5PDS13) /*!< SRAM5 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */
#define LL_PWR_SRAM5_STOP_FULL_RETENTION (PWR_CR4_SRAM5PDS1 | PWR_CR4_SRAM5PDS2 | PWR_CR4_SRAM5PDS3 | \
PWR_CR4_SRAM5PDS4 | PWR_CR4_SRAM5PDS5 | PWR_CR4_SRAM5PDS6 | \
PWR_CR4_SRAM5PDS7 | PWR_CR4_SRAM5PDS8 | PWR_CR4_SRAM5PDS9 | \
PWR_CR4_SRAM5PDS10 | PWR_CR4_SRAM5PDS11 | PWR_CR4_SRAM5PDS12 | \
PWR_CR4_SRAM5PDS13) /*!< SRAM5 pages (1 to 13) retention in Stop modes (Stop 0, 1, 2, 3) */
/**
* @}
*/
#endif /* defined (PWR_CR4_SRAM5PDS1) */
/** @defgroup PWR_LL_EC_ICACHERAM_STOP_CONTENTS_RETENTION PWR ICACHE Content Retention in Stop Mode
* @{
*/
#define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
/** @defgroup PWR_LL_EC_DCACHE1RAM_STOP_CONTENTS_RETENTION PWR DCACHE1 Content Retention in Stop Mode
* @{
*/
#define LL_PWR_DCACHE1RAM_STOP_NO_RETENTION 0U /*!< DCACHE1 SRAM no retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION PWR_CR2_DC1RAMPDS /*!< DCACHE1 SRAM retention in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
#if defined (PWR_CR2_DC2RAMPDS)
/** @defgroup PWR_LL_EC_DCACHE2RAM_STOP_CONTENTS_RETENTION PWR DCACHE2 Content Retention in Stop Mode
* @{
*/
#define LL_PWR_DCACHE2RAM_STOP_NO_RETENTION 0U /*!< DCACHE2 SRAM no retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION PWR_CR2_DC2RAMPDS /*!< DCACHE2 SRAM retention in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
#endif /* defined (PWR_CR2_DC2RAMPDS) */
/** @defgroup PWR_LL_EC_DMA2DRAM_STOP_CONTENTS_RETENTION PWR DMA2DRAM Content Retention in Stop Mode
* @{
*/
#define LL_PWR_DMA2DRAM_STOP_NO_RETENTION 0U /*!< DMA2D SRAM no retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_DMA2DRAM_STOP_FULL_RETENTION PWR_CR2_DMA2DRAMPDS /*!< DMA2D SRAM retention in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
/** @defgroup PWR_LL_EC_PERIPHRAM_STOP_CONTENTS_RETENTION PWR PERIPHRAM Content Retention in Stop Mode
* @{
*/
#define LL_PWR_PERIPHRAM_STOP_NO_RETENTION 0U /*!< FMAC, FDCAN and USB SRAM no retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_PERIPHRAM_STOP_FULL_RETENTION PWR_CR2_PRAMPDS /*!< FMAC, FDCAN and USB SRAM retention in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
/** @defgroup PWR_LL_EC_PKARAM_STOP_CONTENTS_RETENTION PWR PKARAM Content Retention in Stop Mode
* @{
*/
#define LL_PWR_PKARAM_STOP_NO_RETENTION 0U /*!< PKA32 SRAM no retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_PKARAM_STOP_FULL_RETENTION PWR_CR2_PKARAMPDS /*!< PKA32 SRAM retention in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
#if defined (PWR_CR2_GPRAMPDS)
/** @defgroup PWR_LL_EC_GPRAM_STOP_CONTENTS_RETENTION PWR GPRAM Content Retention in Stop Mode
* @{
*/
#define LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION 0U /*!< Graphic peripherals (LTDC, GFXMMU) SRAM no retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION PWR_CR2_GPRAMPDS /*!< Graphic peripherals (LTDC, GFXMMU) SRAM retention in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
#endif /* defined (PWR_CR2_GPRAMPDS) */
#if defined (PWR_CR2_DSIRAMPDS)
/** @defgroup PWR_LL_EC_DSIRAM_STOP_CONTENTS_RETENTION PWRDSI RAM Content Retention in Stop Mode
* @{
*/
#define LL_PWR_DSIRAM_STOP_NO_RETENTION 0U /*!< DSI SRAM no retention in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_DSIRAM_STOP_FULL_RETENTION PWR_CR2_DSIRAMPDS /*!< DSI SRAM retention in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
#endif /* defined (PWR_CR2_DSIRAMPDS) */
/** @defgroup PWR_LL_EC_SRAM1_RUN_CONTENTS_RETENTION PWR SRAM1 Content Retention in Run Mode
* @{
*/
#define LL_PWR_SRAM1_RUN_NO_RETENTION 0U /*!< SRAM1 no retention in Run mode */
#define LL_PWR_SRAM1_RUN_FULL_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 retention in Run mode */
/**
* @}
*/
/** @defgroup PWR_LL_EC_SRAM2_RUN_CONTENTS_RETENTION PWR SRAM2 Content Retention in Run Mode
* @{
*/
#define LL_PWR_SRAM2_RUN_NO_RETENTION 0U /*!< SRAM2 no retention in Run mode */
#define LL_PWR_SRAM2_RUN_FULL_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 retention in Run mode */
/**
* @}
*/
/** @defgroup PWR_LL_EC_SRAM3_RUN_CONTENTS_RETENTION PWR SRAM3 Content Retention in Run Mode
* @{
*/
#define LL_PWR_SRAM3_RUN_NO_RETENTION 0U /*!< SRAM3 no retention in Run mode */
#define LL_PWR_SRAM3_RUN_FULL_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 retention in Run mode */
/**
* @}
*/
/** @defgroup PWR_LL_EC_SRAM4_RUN_CONTENTS_RETENTION PWR SRAM4 Content Retention in Run Mode
* @{
*/
#define LL_PWR_SRAM4_RUN_NO_RETENTION 0U /*!< SRAM4 no retention in Run mode */
#define LL_PWR_SRAM4_RUN_FULL_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 retention in Run mode */
/**
* @}
*/
#if defined (PWR_CR1_SRAM5PD)
/** @defgroup PWR_LL_EC_SRAM5_RUN_CONTENTS_RETENTION PWR SRAM5 Content Retention in Run Mode
* @{
*/
#define LL_PWR_SRAM5_RUN_NO_RETENTION 0U /*!< SRAM5 no retention in Run mode */
#define LL_PWR_SRAM5_RUN_FULL_RETENTION PWR_CR1_SRAM5PD /*!< SRAM5 retention in Run mode */
/**
* @}
*/
#endif /* defined (PWR_CR1_SRAM5PD) */
/** @defgroup PWR_LL_EC_SRD_MODE PWR Smart Run Domain Mode
* @{
*/
#define LL_PWR_SRD_STOP_MODE 0U /*!< SmartRun domain AHB3 and APB3 clocks disabled by default in Stop mode (Stop 0, 1, 2) */
#define LL_PWR_SRD_RUN_MODE PWR_CR2_SRDRUN /*!< SmartRun domain AHB3 and APB3 clocks kept enabled in Stop mode (Stop 0, 1, 2) */
/**
* @}
*/
/** @defgroup PWR_LL_EC_REGULATOR_SUPPLY_SELECTION PWR Regulator Supply Selection
* @{
*/
#define LL_PWR_LDO_SUPPLY 0U /*!< LDO regulator supply */
#define LL_PWR_SMPS_SUPPLY PWR_CR3_REGSEL /*!< SMPS regulator supply */
/**
* @}
*/
/** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection
* @{
*/
#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 */
#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */
#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */
#define LL_PWR_REGU_VOLTAGE_SCALE4 0x00000000U /*!< Voltage scaling range 4 */
/**
* @}
*/
/** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection
* @{
*/
#define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 2.0 V */
#define LL_PWR_PVDLEVEL_1 PWR_SVMCR_PVDLS_0 /*!< Voltage threshold detected by PVD 2.2 V */
#define LL_PWR_PVDLEVEL_2 PWR_SVMCR_PVDLS_1 /*!< Voltage threshold detected by PVD 2.4 V */
#define LL_PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< Voltage threshold detected by PVD 2.5 V */
#define LL_PWR_PVDLEVEL_4 PWR_SVMCR_PVDLS_2 /*!< Voltage threshold detected by PVD 2.6 V */
#define LL_PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.8 V */
#define LL_PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.9 V */
#define LL_PWR_PVDLEVEL_7 PWR_SVMCR_PVDLS /*!< External input analog voltage on PVD_IN
pin, compared to internal VREFINT level */
/**
* @}
*/
/** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin
* @{
*/
#define LL_PWR_WAKEUP_PIN1 PWR_WUCR1_WUPEN1 /*!< Wakeup pin 1 enable */
#define LL_PWR_WAKEUP_PIN2 PWR_WUCR1_WUPEN2 /*!< Wakeup pin 2 enable */
#define LL_PWR_WAKEUP_PIN3 PWR_WUCR1_WUPEN3 /*!< Wakeup pin 3 enable */
#define LL_PWR_WAKEUP_PIN4 PWR_WUCR1_WUPEN4 /*!< Wakeup pin 4 enable */
#define LL_PWR_WAKEUP_PIN5 PWR_WUCR1_WUPEN5 /*!< Wakeup pin 5 enable */
#define LL_PWR_WAKEUP_PIN6 PWR_WUCR1_WUPEN6 /*!< Wakeup pin 6 enable */
#define LL_PWR_WAKEUP_PIN7 PWR_WUCR1_WUPEN7 /*!< Wakeup pin 7 enable */
#define LL_PWR_WAKEUP_PIN8 PWR_WUCR1_WUPEN8 /*!< Wakeup pin 8 enable */
/**
* @}
*/
/** @defgroup PWR_LL_EC_WAKEUP_PIN_SELECTION PWR Wakeup Pin Selection
* @{
*/
#define LL_PWR_WAKEUP_PIN_SELECTION_0 0UL /*!< Wakeup pin selection 0 */
#define LL_PWR_WAKEUP_PIN_SELECTION_1 PWR_WUCR3_WUSEL1_0 /*!< Wakeup pin selection 1 */
#define LL_PWR_WAKEUP_PIN_SELECTION_2 PWR_WUCR3_WUSEL1_1 /*!< Wakeup pin selection 2 */
#define LL_PWR_WAKEUP_PIN_SELECTION_3 PWR_WUCR3_WUSEL1 /*!< Wakeup pin selection 3 */
/**
* @}
*/
/** @defgroup PWR_LL_EC_CHARGING_RESISTOR_SELECTION PWR VBAT Charging Resistor Selection
* @{
*/
#define LL_PWR_BATT_CHARG_RESISTOR_5K 0U /*!< Charge the battery through a 5 kO resistor */
#define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_BDCR2_VBRS /*!< Charge the battery through a 1.5 kO resistor */
/**
* @}
*/
/** @defgroup PWR_LL_EC_GPIO_PORT_SELECTION PWR GPIO Port Selection
* @{
*/
#define LL_PWR_GPIO_PORTA (&(PWR->PUCRA)) /*!< GPIO port A */
#define LL_PWR_GPIO_PORTB (&(PWR->PUCRB)) /*!< GPIO port B */
#define LL_PWR_GPIO_PORTC (&(PWR->PUCRC)) /*!< GPIO port C */
#define LL_PWR_GPIO_PORTD (&(PWR->PUCRD)) /*!< GPIO port D */
#define LL_PWR_GPIO_PORTE (&(PWR->PUCRE)) /*!< GPIO port E */
#define LL_PWR_GPIO_PORTF (&(PWR->PUCRF)) /*!< GPIO port F */
#define LL_PWR_GPIO_PORTG (&(PWR->PUCRG)) /*!< GPIO port G */
#define LL_PWR_GPIO_PORTH (&(PWR->PUCRH)) /*!< GPIO port H */
#define LL_PWR_GPIO_PORTI (&(PWR->PUCRI)) /*!< GPIO port I */
#if defined (PWR_PUCRJ_PU0)
#define LL_PWR_GPIO_PORTJ (&(PWR->PUCRJ)) /*!< GPIO port J */
#endif /* defined (PWR_PUCRJ_PU0) */
/**
* @}
*/
/** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask
* @{
*/
#define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */
#define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */
#define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */
#define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */
#define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */
#define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */
#define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */
#define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */
#define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */
#define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */
#define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */
#define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */
#define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */
#define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */
#define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */
#define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */
/**
* @}
*/
/** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute
* @{
*/
#define LL_PWR_WAKEUP_PIN1_NSEC 0U /*!< Wake up pin 1 nsecure mode */
#define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /*!< Wake up pin 1 secure mode */
#define LL_PWR_WAKEUP_PIN2_NSEC 0U /*!< Wake up pin 2 nsecure mode */
#define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /*!< Wake up pin 2 secure mode */
#define LL_PWR_WAKEUP_PIN3_NSEC 0U /*!< Wake up pin 3 nsecure mode */
#define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /*!< Wake up pin 3 secure mode */
#define LL_PWR_WAKEUP_PIN4_NSEC 0U /*!< Wake up pin 4 nsecure mode */
#define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /*!< Wake up pin 4 secure mode */
#define LL_PWR_WAKEUP_PIN5_NSEC 0U /*!< Wake up pin 5 nsecure mode */
#define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /*!< Wake up pin 5 secure mode */
#define LL_PWR_WAKEUP_PIN6_NSEC 0U /*!< Wake up pin 6 nsecure mode */
#define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /*!< Wake up pin 6 secure mode */
#define LL_PWR_WAKEUP_PIN7_NSEC 0U /*!< Wake up pin 7 nsecure mode */
#define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /*!< Wake up pin 7 secure mode */
#define LL_PWR_WAKEUP_PIN8_NSEC 0U /*!< Wake up pin 8 nsecure mode */
#define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /*!< Wake up pin 8 secure mode */
#define LL_PWR_LPM_NSEC 0U /*!< Low-power modes nsecure mode */
#define LL_PWR_LPM_SEC PWR_SECCFGR_WUP8SEC /*!< Low-power modes secure mode */
#define LL_PWR_VDM_NSEC 0U /*!< Voltage detection and monitoring nsecure mode */
#define LL_PWR_VDM_SEC PWR_SECCFGR_WUP8SEC /*!< Voltage detection and monitoring secure mode */
#define LL_PWR_VB_NSEC 0U /*!< Backup domain nsecure mode */
#define LL_PWR_VB_SEC PWR_SECCFGR_WUP8SEC /*!< Backup domain secure mode */
#define LL_PWR_APC_NSEC 0U /*!< Pull-up/pull-down nsecure mode */
#define LL_PWR_APC_SEC PWR_SECCFGR_WUP8SEC /*!< Pull-up/pull-down secure mode */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
* @{
*/
/** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros
* @{
*/
/**
* @brief Write a value in PWR register.
* @param __REG__ Register to be written.
* @param __VALUE__ Value to be written in the register.
* @retval None.
*/
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
/**
* @brief Read a value in PWR register.
* @param __REG__ Register to be read.
* @retval Register value.
*/
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration
* @{
*/
/**
* @brief Set system power mode.
* @rmtoll CR1 LPMS LL_PWR_SetPowerMode
* @param Mode : This parameter can be one of the following values:
* @arg @ref LL_PWR_STOP0_MODE
* @arg @ref LL_PWR_STOP1_MODE
* @arg @ref LL_PWR_STOP2_MODE
* @arg @ref LL_PWR_STOP3_MODE
* @arg @ref LL_PWR_STANDBY_MODE
* @arg @ref LL_PWR_SHUTDOWN_MODE
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode)
{
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode);
}
/**
* @brief Get system power mode.
* @rmtoll CR1 LPMS LL_PWR_GetPowerMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_STOP0_MODE
* @arg @ref LL_PWR_STOP1_MODE
* @arg @ref LL_PWR_STOP2_MODE
* @arg @ref LL_PWR_STOP3_MODE
* @arg @ref LL_PWR_STANDBY_MODE
* @arg @ref LL_PWR_SHUTDOWN_MODE
*/
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
{
return (READ_BIT(PWR->CR1, PWR_CR1_LPMS));
}
/**
* @brief Set the SRAM2 page(s) retention in Standby mode.
* @rmtoll CR1 RRSB1 LL_PWR_SetSRAM2SBRetention\n
* @rmtoll CR1 RRSB2 LL_PWR_SetSRAM2SBRetention
* @param SRAM2PageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
* @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION
* @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION
* @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention)
{
MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_SB_FULL_RETENTION, SRAM2PageRetention);
}
/**
* @brief Get the SRAM2 page(s) retention in Standby mode.
* @rmtoll CR1 RRSB1 LL_PWR_GetSRAM2SBRetention\n
* @rmtoll CR1 RRSB2 LL_PWR_GetSRAM2SBRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION
* @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION
* @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION
* @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void)
{
return (READ_BIT(PWR->CR1, (PWR_CR1_RRSB1 | PWR_CR1_RRSB2)));
}
/**
* @brief Enable BOR ultra low power mode.
* @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void)
{
SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
}
/**
* @brief Disable BOR ultra low-power mode.
* @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void)
{
CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
}
/**
* @brief Check if BOR ultra low power mode is enabled.
* @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void)
{
return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL);
}
/**
* @brief Set the SRAM1 retention in Run mode.
* @rmtoll CR1 SRAM1PD LL_PWR_SetSRAM1RunRetention\n
* @param SRAM1Retention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION
* @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM1RunRetention(uint32_t SRAM1Retention)
{
MODIFY_REG(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION, ((~SRAM1Retention) & LL_PWR_SRAM1_RUN_FULL_RETENTION));
}
/**
* @brief Get the SRAM1 retention in Run mode.
* @rmtoll CR1 SRAM1PD LL_PWR_GetSRAM1RunRetention\n
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION
* @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM1RunRetention(void)
{
return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION))) & LL_PWR_SRAM1_RUN_FULL_RETENTION);
}
/**
* @brief Set the SRAM2 retention in Run mode.
* @rmtoll CR1 SRAM2PD LL_PWR_SetSRAM2RunRetention\n
* @param SRAM2Retention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION
* @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM2RunRetention(uint32_t SRAM2Retention)
{
MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION, ((~SRAM2Retention) & LL_PWR_SRAM2_RUN_FULL_RETENTION));
}
/**
* @brief Get the SRAM2 retention in Run mode.
* @rmtoll CR1 SRAM2PD LL_PWR_GetSRAM2RunRetention\n
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION
* @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM2RunRetention(void)
{
return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION))) & LL_PWR_SRAM2_RUN_FULL_RETENTION);
}
/**
* @brief Set the SRAM3 retention in Run mode.
* @rmtoll CR1 SRAM3PD LL_PWR_SetSRAM3RunRetention\n
* @param SRAM3Retention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION
* @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM3RunRetention(uint32_t SRAM3Retention)
{
MODIFY_REG(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION, ((~SRAM3Retention) & LL_PWR_SRAM3_RUN_FULL_RETENTION));
}
/**
* @brief Get the SRAM3 retention in Run mode.
* @rmtoll CR1 SRAM3PD LL_PWR_GetSRAM3RunRetention\n
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION
* @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM3RunRetention(void)
{
return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION))) & LL_PWR_SRAM3_RUN_FULL_RETENTION);
}
/**
* @brief Set the SRAM4 retention in Run mode.
* @rmtoll CR1 SRAM4PD LL_PWR_SetSRAM4RunRetention\n
* @param SRAM4Retention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION
* @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM4RunRetention(uint32_t SRAM4Retention)
{
MODIFY_REG(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION, ((~SRAM4Retention) & LL_PWR_SRAM4_RUN_FULL_RETENTION));
}
/**
* @brief Get the SRAM4 retention in Run mode.
* @rmtoll CR1 SRAM4PD LL_PWR_GetSRAM4RunRetention\n
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION
* @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM4RunRetention(void)
{
return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION))) & LL_PWR_SRAM4_RUN_FULL_RETENTION);
}
#if defined (PWR_CR1_SRAM5PD)
/**
* @brief Set the SRAM5 retention in Run mode.
* @rmtoll CR1 SRAM5PD LL_PWR_SetSRAM5RunRetention\n
* @param SRAM5Retention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM5_RUN_NO_RETENTION
* @arg @ref LL_PWR_SRAM5_RUN_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM5RunRetention(uint32_t SRAM5Retention)
{
MODIFY_REG(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION, ((~SRAM5Retention) & LL_PWR_SRAM5_RUN_FULL_RETENTION));
}
/**
* @brief Get the SRAM5 retention in Run mode.
* @rmtoll CR1 SRAM5PD LL_PWR_GetSRAM5RunRetention\n
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM5_RUN_NO_RETENTION
* @arg @ref LL_PWR_SRAM5_RUN_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM5RunRetention(void)
{
return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION))) & LL_PWR_SRAM5_RUN_FULL_RETENTION);
}
#endif /* defined (PWR_CR1_SRAM5PD) */
/**
* @brief Set the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode.
* @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention_1_3\n
* @rmtoll CR2 SRAM1PDS2 LL_PWR_SetSRAM1StopRetention_1_3\n
* @rmtoll CR2 SRAM1PDS3 LL_PWR_SetSRAM1StopRetention_1_3
* @param SRAM1PageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION
* Or can be a combination of the following values:
* @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_1_3(uint32_t SRAM1PageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_1_3_RETENTION));
}
#if defined (PWR_CR4_SRAM1PDS4)
/**
* @brief Set the SRAM1 page(s) (From page 4 to page 12) retention in Stop mode.
* @rmtoll CR2 SRAM1PDS4 LL_PWR_SetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS5 LL_PWR_SetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS6 LL_PWR_SetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS7 LL_PWR_SetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS8 LL_PWR_SetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS9 LL_PWR_SetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS10 LL_PWR_SetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS11 LL_PWR_SetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS12 LL_PWR_SetSRAM1StopRetention_4_12
* @param SRAM1PageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_4_12_RETENTION
* Or can be a combination of the following values:
* @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE5_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE6_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE7_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE8_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE9_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE10_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE11_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE12_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_4_12(uint32_t SRAM1PageRetention)
{
MODIFY_REG(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_4_12_RETENTION));
}
#endif /* defined (PWR_CR4_SRAM1PDS4) */
/**
* @brief Get the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode.
* @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention_1_3\n
* @rmtoll CR2 SRAM1PDS2 LL_PWR_GetSRAM1StopRetention_1_3\n
* @rmtoll CR2 SRAM1PDS3 LL_PWR_GetSRAM1StopRetention_1_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION
* Or a combination of the following values:
* @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_1_3(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION))) & LL_PWR_SRAM1_STOP_1_3_RETENTION);
}
#if defined (PWR_CR4_SRAM1PDS4)
/**
* @brief Get the SRAM1 page(s) (From page 4 to page 12) retention in Stop mode.
* @rmtoll CR2 SRAM1PDS4 LL_PWR_GetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS5 LL_PWR_GetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS6 LL_PWR_GetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS7 LL_PWR_GetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS8 LL_PWR_GetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS9 LL_PWR_GetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS10 LL_PWR_GetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS11 LL_PWR_GetSRAM1StopRetention_4_12\n
* @rmtoll CR2 SRAM1PDS12 LL_PWR_GetSRAM1StopRetention_4_12
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_4_12_RETENTION
* Or a combination of the following values:
* @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE5_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE6_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE7_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE8_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE9_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE10_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE11_RETENTION
* @arg @ref LL_PWR_SRAM1_STOP_PAGE12_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_4_12(void)
{
return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION))) & LL_PWR_SRAM1_STOP_4_12_RETENTION);
}
#endif /* defined (PWR_CR4_SRAM1PDS4) */
/**
* @brief Set the SRAM2 page(s) retention in Stop mode.
* @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention\n
* @rmtoll CR2 SRAM2PDS2 LL_PWR_SetSRAM2StopRetention
* @param SRAM2PageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION
* @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION
* @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION, ((~SRAM2PageRetention) & LL_PWR_SRAM2_STOP_FULL_RETENTION));
}
/**
* @brief Get the SRAM2 page(s) retention in Stop mode.
* @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention\n
* @rmtoll CR2 SRAM2PDS2 LL_PWR_GetSRAM2StopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION
* @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION
* @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION))) & LL_PWR_SRAM2_STOP_FULL_RETENTION);
}
/**
* @brief Set the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode.
* @rmtoll CR2 SRAM3PDS1 LL_PWR_SetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS2 LL_PWR_SetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS3 LL_PWR_SetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS4 LL_PWR_SetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS5 LL_PWR_SetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS6 LL_PWR_SetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS7 LL_PWR_SetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS8 LL_PWR_SetSRAM3StopRetention_1_8
* @param SRAM3PageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION
* Or can be a combination of the following values:
* @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_1_8(uint32_t SRAM3PageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_1_8_RETENTION));
}
#if defined (PWR_CR4_SRAM3PDS9)
/**
* @brief Set the SRAM3 page(s) (From page 9 to page 13) retention in Stop mode.
* @rmtoll CR2 SRAM3PDS9 LL_PWR_SetSRAM3StopRetention_9_13\n
* @rmtoll CR2 SRAM3PDS10 LL_PWR_SetSRAM3StopRetention_9_13\n
* @rmtoll CR2 SRAM3PDS11 LL_PWR_SetSRAM3StopRetention_9_13\n
* @rmtoll CR2 SRAM3PDS12 LL_PWR_SetSRAM3StopRetention_9_13\n
* @rmtoll CR2 SRAM3PDS13 LL_PWR_SetSRAM3StopRetention_9_13
* @param SRAM3PageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_9_13_RETENTION
* Or can be a combination of the following values:
* @arg @ref LL_PWR_SRAM3_STOP_PAGE9_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE10_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE11_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE12_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE13_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_9_13(uint32_t SRAM3PageRetention)
{
MODIFY_REG(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_9_13_RETENTION));
}
#endif /* defined (PWR_CR4_SRAM3PDS9) */
/**
* @brief Get the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode.
* @rmtoll CR2 SRAM3PDS1 LL_PWR_GetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS2 LL_PWR_GetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS3 LL_PWR_GetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS4 LL_PWR_GetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS5 LL_PWR_GetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS6 LL_PWR_GetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS7 LL_PWR_GetSRAM3StopRetention_1_8\n
* @rmtoll CR2 SRAM3PDS8 LL_PWR_GetSRAM3StopRetention_1_8
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION
* Or can be a combination of the following values:
* @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_1_8(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION))) & LL_PWR_SRAM3_STOP_1_8_RETENTION);
}
#if defined (PWR_CR4_SRAM3PDS9)
/**
* @brief Get the SRAM3 page(s) (From page 9 to page 13) retention in Stop mode.
* @rmtoll CR2 SRAM3PDS9 LL_PWR_SetSRAM3StopRetention_9_13\n
* @rmtoll CR2 SRAM3PDS10 LL_PWR_SetSRAM3StopRetention_9_13\n
* @rmtoll CR2 SRAM3PDS11 LL_PWR_SetSRAM3StopRetention_9_13\n
* @rmtoll CR2 SRAM3PDS12 LL_PWR_SetSRAM3StopRetention_9_13\n
* @rmtoll CR2 SRAM3PDS13 LL_PWR_SetSRAM3StopRetention_9_13
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_9_13_RETENTION
* Or can be a combination of the following values:
* @arg @ref LL_PWR_SRAM3_STOP_PAGE9_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE10_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE11_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE12_RETENTION
* @arg @ref LL_PWR_SRAM3_STOP_PAGE13_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_9_13(void)
{
return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION))) & LL_PWR_SRAM3_STOP_9_13_RETENTION);
}
#endif /* defined (PWR_CR4_SRAM3PDS9) */
/**
* @brief Set the SRAM4 page retention in Stop mode.
* @rmtoll CR2 SRAM4PDS LL_PWR_SetSRAM4StopRetention\n
* @param SRAM4PageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM4StopRetention(uint32_t SRAM4PageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION, ((~SRAM4PageRetention) & LL_PWR_SRAM4_STOP_FULL_RETENTION));
}
/**
* @brief Get the SRAM4 page retention in Stop mode.
* @rmtoll CR2 SRAM4PDS LL_PWR_GetSRAM4StopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM4StopRetention(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION))) & LL_PWR_SRAM4_STOP_FULL_RETENTION);
}
#if defined (PWR_CR4_SRAM5PDS1)
/**
* @brief Set the SRAM5 page(s) retention in Stop mode.
* @rmtoll CR2 SRAM5PDS1 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS2 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS3 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS4 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS5 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS6 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS7 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS8 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS9 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS10 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS11 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS12 LL_PWR_SetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS13 LL_PWR_SetSRAM5StopRetention
* @param SRAM5PageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRAM5_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_FULL_RETENTION
* Or can be a combination of the following values:
* @arg @ref LL_PWR_SRAM5_STOP_PAGE1_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE2_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE3_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE4_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE5_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE6_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE7_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE8_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE9_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE10_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE11_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE12_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE13_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSRAM5StopRetention(uint32_t SRAM5PageRetention)
{
MODIFY_REG(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION, ((~SRAM5PageRetention) & LL_PWR_SRAM5_STOP_FULL_RETENTION));
}
/**
* @brief Get the SRAM5 page(s) retention in Stop mode.
* @rmtoll CR2 SRAM5PDS1 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS2 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS3 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS4 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS5 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS6 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS7 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS8 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS9 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS10 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS11 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS12 LL_PWR_GetSRAM5StopRetention\n
* @rmtoll CR2 SRAM5PDS13 LL_PWR_GetSRAM5StopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRAM5_STOP_NO_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_FULL_RETENTION
* Or can be a combination of the following values:
* @arg @ref LL_PWR_SRAM5_STOP_PAGE1_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE2_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE3_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE4_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE5_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE6_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE7_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE8_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE9_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE10_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE11_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE12_RETENTION
* @arg @ref LL_PWR_SRAM5_STOP_PAGE13_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetSRAM5StopRetention(void)
{
return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION))) & LL_PWR_SRAM5_STOP_FULL_RETENTION);
}
#endif /* defined (PWR_CR4_SRAM5PDS1) */
/**
* @brief Set the ICACHE SRAM page retention in Stop mode.
* @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention\n
* @param ICachePageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICachePageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION,
((~ICachePageRetention) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION));
}
/**
* @brief Get the ICACHE SRAM page retention in Stop mode.
* @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION))) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION);
}
/**
* @brief Set the DCACHE1 SRAM page retention in Stop mode.
* @rmtoll CR2 DC1RAMPDS LL_PWR_SetDCache1RAMStopRetention\n
* @param DCache1PageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetDCache1RAMStopRetention(uint32_t DCache1PageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION,
((~DCache1PageRetention) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION));
}
/**
* @brief Get the DCACHE1 SRAM page retention in Stop mode.
* @rmtoll CR2 DC1RAMPDS LL_PWR_GetDCache1RAMStopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetDCache1RAMStopRetention(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION);
}
#if defined (PWR_CR2_DC2RAMPDS)
/**
* @brief Set the DCACHE2 SRAM page retention in Stop mode.
* @rmtoll CR2 DC2RAMPDS LL_PWR_SetDCache2RAMStopRetention\n
* @param DCache2PageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_DCACHE2RAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetDCache2RAMStopRetention(uint32_t DCache2PageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION,
((~DCache2PageRetention) & LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION));
}
/**
* @brief Get the DCACHE2 SRAM page retention in Stop mode.
* @rmtoll CR2 DC2RAMPDS LL_PWR_GetDCache2RAMStopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_DCACHE2RAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetDCache2RAMStopRetention(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION);
}
#endif /* defined (PWR_CR2_DC2RAMPDS) */
/**
* @brief Set the DMA2D SRAM page retention in Stop mode.
* @rmtoll CR2 DMA2DRAMPDS LL_PWR_SetDMA2DRAMStopRetention\n
* @param DMA2DRAMPageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetDMA2DRAMStopRetention(uint32_t DMA2DRAMPageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION,
((~DMA2DRAMPageRetention) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION));
}
/**
* @brief Get the DMA2D SRAM page retention in Stop mode.
* @rmtoll CR2 DMA2DRAMPDS LL_PWR_GetDMA2DRAMStopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetDMA2DRAMStopRetention(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION))) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION);
}
/**
* @brief Set the FMAC, FDCAN and USB SRAMs pages retention in Stop mode.
* @rmtoll CR2 PRAMPDS LL_PWR_SetPeriphRAMStopRetention\n
* @param PriphRAMPageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPeriphRAMStopRetention(uint32_t PriphRAMPageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION,
((~PriphRAMPageRetention) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION));
}
/**
* @brief Get the FMAC, FDCAN and USB SRAMs pages retention in Stop mode.
* @rmtoll CR2 PRAMPDS LL_PWR_GetPeriphRAMStopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetPeriphRAMStopRetention(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION))) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION);
}
/**
* @brief Set the PKA32 SRAM page retention in Stop mode.
* @rmtoll CR2 PKARAMPDS LL_PWR_SetPKARAMStopRetention
* @param PKARAMPageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPKARAMStopRetention(uint32_t PKARAMPageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION, ((~PKARAMPageRetention) & LL_PWR_PKARAM_STOP_FULL_RETENTION));
}
/**
* @brief Get the PKA32 SRAM page retention in Stop mode.
* @rmtoll CR2 PKARAMPDS LL_PWR_GetPKARAMStopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetPKARAMStopRetention(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION))) & LL_PWR_PKARAM_STOP_FULL_RETENTION);
}
#if defined (PWR_CR2_GPRAMPDS)
/**
* @brief Set the Graphic peripherals (LTDC, GFXMMU) SRAM page retention in Stop mode.
* @rmtoll CR2 GPRAMPDS LL_PWR_SetGraphicPeriphRAMStopRetention
* @param GraphicPeriphRAMPageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetGraphicPeriphRAMStopRetention(uint32_t GraphicPeriphRAMPageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION,
((~GraphicPeriphRAMPageRetention) & LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION));
}
/**
* @brief Get the Graphic peripherals (LTDC, GFXMMU) SRAM page retention in Stop mode.
* @rmtoll CR2 GPRAMPDS LL_PWR_GetGraphicPeriphRAMStopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetGraphicPeriphRAMStopRetention(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION))) &
LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION);
}
#endif /* defined (PWR_CR2_GPRAMPDS) */
#if defined (PWR_CR2_DSIRAMPDS)
/**
* @brief Set the DSI SRAM page retention in Stop mode.
* @rmtoll CR2 DSIRAMPDS LL_PWR_SetDSIRAMStopRetention
* @param DSIRAMPageRetention : This parameter can be one of the following values:
* @arg @ref LL_PWR_DSIRAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_DSIRAM_STOP_FULL_RETENTION
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetDSIRAMStopRetention(uint32_t DSIRAMPageRetention)
{
MODIFY_REG(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION, ((~DSIRAMPageRetention) & LL_PWR_DSIRAM_STOP_FULL_RETENTION));
}
/**
* @brief Get the DSI SRAM page retention in Stop mode.
* @rmtoll CR2 DSIRAMPDS LL_PWR_GetDSIRAMStopRetention
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_DSIRAM_STOP_NO_RETENTION
* @arg @ref LL_PWR_DSIRAM_STOP_FULL_RETENTION
*/
__STATIC_INLINE uint32_t LL_PWR_GetDSIRAMStopRetention(void)
{
return ((~(READ_BIT(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION))) & LL_PWR_DSIRAM_STOP_FULL_RETENTION);
}
#endif /* defined (PWR_CR2_DSIRAMPDS) */
/**
* @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1).
* @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void)
{
SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
}
/**
* @brief Disable the flash memory fast wakeup from Stop mode (Stop 0, 1).
* @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
}
/**
* @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1)
* is enabled.
* @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashFastWakeUp
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void)
{
return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL);
}
/**
* @brief Enable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
* @rmtoll CR2 SRAM4FWU LL_PWR_EnableSRAM4FastWakeUp
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableSRAM4FastWakeUp(void)
{
SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
}
/**
* @brief Disable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
* @rmtoll CR2 SRAM4FWU LL_PWR_DisableSRAM4FastWakeUp
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableSRAM4FastWakeUp(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
}
/**
* @brief Check if the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2).
* is enabled.
* @rmtoll CR2 SRAM4FWU LL_PWR_IsEnabledSRAM4FastWakeUp
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM4FastWakeUp(void)
{
return ((READ_BIT(PWR->CR2, PWR_CR2_SRAM4FWU) == (PWR_CR2_SRAM4FWU)) ? 1UL : 0UL);
}
/**
* @brief Set the smart run domain mode.
* @rmtoll CR2 SRDRUN LL_PWR_SetSmartRunDomainMode
* @param SRDMode : This parameter can be one of the following values:
* @arg @ref LL_PWR_SRD_RUN_MODE
* @arg @ref LL_PWR_SRD_STOP_MODE
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetSmartRunDomainMode(uint32_t SRDMode)
{
MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDMode);
}
/**
* @brief Get the smart run domain mode.
* @rmtoll CR2 SRDRUN LL_PWR_GetSmartRunDomainMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_SRD_RUN_MODE
* @arg @ref LL_PWR_SRD_STOP_MODE
*/
__STATIC_INLINE uint32_t LL_PWR_GetSmartRunDomainMode(void)
{
return (READ_BIT(PWR->CR2, PWR_CR2_SRDRUN));
}
/**
* @brief Set the VCore regulator supply.
* @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply
* @param RegulatorSupply : This parameter can be one of the following values:
* @arg @ref LL_PWR_LDO_SUPPLY
* @arg @ref LL_PWR_SMPS_SUPPLY
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply)
{
MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply);
}
/**
* @brief Get the VCore regulator supply.
* @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_LDO_SUPPLY
* @arg @ref LL_PWR_SMPS_SUPPLY
*/
__STATIC_INLINE uint32_t LL_PWR_GetRegulatorSupply(void)
{
return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL));
}
/**
* @brief Enable the fast soft start for selected regulator.
* @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableFastSoftStart(void)
{
SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
}
/**
* @brief Disable the fast soft start for selected regulator.
* @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableFastSoftStart(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
}
/**
* @brief Check if the fast soft start for selected regulator is enabled.
* @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void)
{
return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL);
}
/**
* @brief Set the regulator supply output voltage.
* @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling
* @param VoltageScaling This parameter can be one of the following values:
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
{
MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling);
}
/**
* @brief Get the regulator supply output voltage.
* @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
*/
__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
{
return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS));
}
/**
* @brief Enable the EPOD (Embedded Power Distribution) booster.
* @rmtoll VOSR BOOSTEN LL_PWR_EnableEPODBooster
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableEPODBooster(void)
{
SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
}
/**
* @brief Disable the EPOD (Embedded Power Distribution) booster.
* @rmtoll VOSR BOOSTEN LL_PWR_DisableEPODBooster
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableEPODBooster(void)
{
CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
}
/**
* @brief Check if the EPOD (Embedded Power Distribution) booster is enabled.
* @rmtoll VOSR BOOSTEN LL_PWR_IsEnabledEPODBooster
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledEPODBooster(void)
{
return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == (PWR_VOSR_BOOSTEN)) ? 1UL : 0UL);
}
#if defined (PWR_VOSR_USBPWREN)
/**
* @brief Enable the USB power supply.
* @rmtoll VOSR USBPWREN LL_PWR_EnableUSBPowerSupply
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableUSBPowerSupply(void)
{
SET_BIT(PWR->VOSR, PWR_VOSR_USBPWREN);
}
/**
* @brief Disable the USB power supply.
* @rmtoll VOSR USBPWREN LL_PWR_DisableUSBPowerSupply
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableUSBPowerSupply(void)
{
CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBPWREN);
}
/**
* @brief Check if the USB power supply is enabled.
* @rmtoll VOSR USBPWREN LL_PWR_IsEnabledUSBPowerSupply
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBPowerSupply(void)
{
return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBPWREN) == (PWR_VOSR_USBPWREN)) ? 1UL : 0UL);
}
#endif /* defined (PWR_VOSR_USBPWREN) */
#if defined (PWR_VOSR_USBBOOSTEN)
/**
* @brief Enable the USB EPOD (Embedded Power Distribution) booster.
* @rmtoll VOSR USBBOOSTEN LL_PWR_EnableUSBEPODBooster
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableUSBEPODBooster(void)
{
SET_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN);
}
/**
* @brief Disable the USB EPOD (Embedded Power Distribution) booster.
* @rmtoll VOSR USBBOOSTEN LL_PWR_DisableUSBEPODBooster
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableUSBEPODBooster(void)
{
CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN);
}
/**
* @brief Check if the USB EPOD (Embedded Power Distribution) booster is enabled.
* @rmtoll VOSR USBBOOSTEN LL_PWR_IsEnabledUSBEPODBooster
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBEPODBooster(void)
{
return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN) == (PWR_VOSR_USBBOOSTEN)) ? 1UL : 0UL);
}
#endif /* defined (PWR_VOSR_USBBOOSTEN) */
/**
* @brief Set the Power voltage detector level.
* @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel
* @param PVDLevel This parameter can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
{
MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel);
}
/**
* @brief Get the Power voltage detector level.
* @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
*/
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
{
return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS));
}
/**
* @brief Enable the power voltage detector.
* @rmtoll SVMCR PVDE LL_PWR_EnablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePVD(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
}
/**
* @brief Disable the power voltage detector.
* @rmtoll SVMCR PVDE LL_PWR_DisablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
}
/**
* @brief Check if the power voltage detector is enabled.
* @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
{
return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL);
}
/**
* @brief Enable the independent USB supply.
* @rmtoll SVMCR USV LL_PWR_EnableVDDUSB
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableVDDUSB(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_USV);
}
/**
* @brief Disable the independent USB supply.
* @rmtoll SVMCR USV LL_PWR_DisableVDDUSB
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableVDDUSB(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV);
}
/**
* @brief Check if the independent USB supply is enabled.
* @rmtoll SVMCR USV LL_PWR_IsEnabledVDDUSB
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDUSB(void)
{
return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL);
}
/**
* @brief Enable the independent I/Os supply.
* @rmtoll SVMCR IO2SV LL_PWR_EnableVDDIO2
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableVDDIO2(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
}
/**
* @brief Disable the independent I/Os supply.
* @rmtoll SVMCR IO2SV LL_PWR_DisableVDDIO2
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableVDDIO2(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
}
/**
* @brief Check if the independent I/Os supply is enabled.
* @rmtoll SVMCR IO2SV LL_PWR_IsEnabledVDDIO2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDIO2(void)
{
return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV) == (PWR_SVMCR_IO2SV)) ? 1UL : 0UL);
}
/**
* @brief Enable the independent analog supply.
* @rmtoll SVMCR ASV LL_PWR_EnableVDDA
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableVDDA(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
}
/**
* @brief Disable the independent analog supply.
* @rmtoll SVMCR ASV LL_PWR_DisableVDDA
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableVDDA(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
}
/**
* @brief Check if the independent analog supply is enabled.
* @rmtoll SVMCR ASV LL_PWR_IsEnabledVDDA
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDA(void)
{
return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_ASV) == (PWR_SVMCR_ASV)) ? 1UL : 0UL);
}
/**
* @brief Enable the independent USB supply monitor.
* @rmtoll SVMCR UVMEN LL_PWR_EnableVDDUSBMonitor
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableVDDUSBMonitor(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
}
/**
* @brief Disable the independent USB supply monitor.
* @rmtoll SVMCR UVMEN LL_PWR_DisableVDDUSBMonitor
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableVDDUSBMonitor(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
}
/**
* @brief Check if the independent USB supply monitor is enabled.
* @rmtoll SVMCR UVMEN LL_PWR_IsEnabledVDDUSBMonitor
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDUSBMonitor(void)
{
return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN) == (PWR_SVMCR_UVMEN)) ? 1UL : 0UL);
}
/**
* @brief Enable the independent I/Os supply monitor.
* @rmtoll SVMCR IO2VMEN LL_PWR_EnableVDDIO2Monitor
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableVDDIO2Monitor(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
}
/**
* @brief Disable the independent I/Os supply monitor.
* @rmtoll SVMCR IO2VMEN LL_PWR_DisableVDDIO2Monitor
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableVDDIO2Monitor(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
}
/**
* @brief Check if the independent I/Os supply monitor is enabled.
* @rmtoll SVMCR IO2VMEN LL_PWR_IsEnabledVDDIO2Monitor
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDIO2Monitor(void)
{
return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN) == (PWR_SVMCR_IO2VMEN)) ? 1UL : 0UL);
}
/**
* @brief Enable the independent analog supply monitor 1.
* @rmtoll SVMCR AVM1EN LL_PWR_EnableVDDAMonitor1
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableVDDAMonitor1(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
}
/**
* @brief Disable the independent analog supply monitor 1.
* @rmtoll SVMCR AVM1EN LL_PWR_DisableVDDAMonitor1
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableVDDAMonitor1(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
}
/**
* @brief Check if the independent analog supply monitor 1 is enabled.
* @rmtoll SVMCR AVM1EN LL_PWR_IsEnabledVDDAMonitor1
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDAMonitor1(void)
{
return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN) == (PWR_SVMCR_AVM1EN)) ? 1UL : 0UL);
}
/**
* @brief Enable the independent analog supply monitor 2.
* @rmtoll SVMCR AVM2EN LL_PWR_EnableVDDAMonitor2
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableVDDAMonitor2(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
}
/**
* @brief Disable the independent analog supply monitor 2.
* @rmtoll SVMCR AVM2EN LL_PWR_DisableVDDAMonitor2
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableVDDAMonitor2(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
}
/**
* @brief Check if the independent analog supply monitor 2 is enabled.
* @rmtoll SVMCR AVM2EN LL_PWR_IsEnabledVDDAMonitor2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDDAMonitor2(void)
{
return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN) == (PWR_SVMCR_AVM2EN)) ? 1UL : 0UL);
}
/**
* @brief Enable the wake up pin_x.
* @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin
* @param WakeUpPin This parameter can be a combination of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
{
SET_BIT(PWR->WUCR1, WakeUpPin);
}
/**
* @brief Disable the wake up pin_x.
* @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin
* @param WakeUpPin This parameter can be a combination of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
{
CLEAR_BIT(PWR->WUCR1, WakeUpPin);
}
/**
* @brief Check if the wake up pin_x is enabled.
* @rmtoll WUCR1 WUPENx LL_PWR_IsEnabledWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
{
return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
}
/**
* @brief Set the wake up pin polarity low for the event detection.
* @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow
* @param WakeUpPin This parameter can be a combination of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
{
SET_BIT(PWR->WUCR2, WakeUpPin);
}
/**
* @brief Set the wake up pin polarity high for the event detection.
* @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh
* @param WakeUpPin This parameter can be a combination of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
{
CLEAR_BIT(PWR->WUCR2, WakeUpPin);
}
/**
* @brief Get the wake up pin polarity for the event detection.
* @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
* @retval State of bit (1 : polarity or 0 : polarity high).
*/
__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin)
{
return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL);
}
/**
* @brief Set the wakeup pin_x selection 0.
* @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin)
{
MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
(LL_PWR_WAKEUP_PIN_SELECTION_0 << (POSITION_VAL(WakeUpPin) * 2U)));
}
/**
* @brief Set the wakeup pin_x selection 1.
* @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin)
{
MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
(LL_PWR_WAKEUP_PIN_SELECTION_1 << (POSITION_VAL(WakeUpPin) * 2U)));
}
/**
* @brief Set the wakeup pin_x selection 2.
* @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin)
{
MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
(LL_PWR_WAKEUP_PIN_SELECTION_2 << (POSITION_VAL(WakeUpPin) * 2U)));
}
/**
* @brief Set the wakeup pin_x selection 3.
* @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin)
{
MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)),
(LL_PWR_WAKEUP_PIN_SELECTION_3 << (POSITION_VAL(WakeUpPin) * 2U)));
}
/**
* @brief Get the wakeup pin_x selection.
* @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @arg @ref LL_PWR_WAKEUP_PIN6
* @arg @ref LL_PWR_WAKEUP_PIN7
* @arg @ref LL_PWR_WAKEUP_PIN8
*/
__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin)
{
return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U))));
}
/**
* @brief Enable backup regulator.
* @rmtoll BDCR1 BREN LL_PWR_EnableBkUpRegulator
* @note When this bit is set, the backup RAM content is kept in Standby and
* VBAT modes. If BREN is reset, the backup RAM can still be used in
* Run, Sleep and Stop modes. However, its content is lost in Standby,
* Shutdown and VBAT modes. This bit can be written only when the
* regulator is LDO, which must be configured before switching to SMPS.
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
{
SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
}
/**
* @brief Disable backup regulator
* @rmtoll BDCR1 BREN LL_PWR_DisableBkUpRegulator
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
{
CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
}
/**
* @brief Check if the backup regulator is enabled
* @rmtoll BDCR1 BREN LL_PWR_IsEnabledBkUpRegulator
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
{
return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_BREN) == (PWR_BDCR1_BREN)) ? 1UL : 0UL);
}
/**
* @brief Enable the backup domain voltage and temperature monitoring.
* @rmtoll BDCR1 MONEN LL_PWR_EnableMonitoring
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableMonitoring(void)
{
SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
}
/**
* @brief Disable the backup domain voltage and temperature monitoring.
* @rmtoll BDCR1 MONEN LL_PWR_DisableMonitoring
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableMonitoring(void)
{
CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
}
/**
* @brief Check if the backup domain voltage and temperature monitoring is
* enabled.
* @rmtoll BDCR1 MONEN LL_PWR_IsEnabledMonitoring
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
{
return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL);
}
/**
* @brief Enable battery charging.
* @rmtoll BDCR2 VBE LL_PWR_EnableBatteryCharging
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
{
SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
}
/**
* @brief Disable battery charging.
* @rmtoll BDCR2 VBE LL_PWR_DisableBatteryCharging
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
{
CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
}
/**
* @brief Check if battery charging is enabled.
* @rmtoll BDCR2 VBE LL_PWR_IsEnabledBatteryCharging
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
{
return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_VBE) == (PWR_BDCR2_VBE)) ? 1UL : 0UL);
}
/**
* @brief Set the Battery charge resistor impedance
* @rmtoll BDCR2 VBRS LL_PWR_SetBattChargResistor
* @param Resistor This parameter can be one of the following values:
* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
{
MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, Resistor);
}
/**
* @brief Get the Battery charge resistor impedance
* @rmtoll BDCR2 VBRS LL_PWR_GetBattChargResistor
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K
*/
__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
{
return (uint32_t)(READ_BIT(PWR->BDCR2, PWR_BDCR2_VBRS));
}
/**
* @brief Enable access to the backup domain.
* @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
}
/**
* @brief Disable access to the backup domain.
* @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP);
}
/**
* @brief Check if the access to backup domain is enabled.
* @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
{
return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL);
}
/**
* @brief Enable the USB Type-C and Power Delivery memorization in Standby mode.
* @note This function must be called just before entering Standby mode.
* @rmtoll UCPDR UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
{
SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
}
/**
* @brief Disable the USB Type-C and Power Delivery memorization in Standby mode.
* @note This function must be called after exiting Standby mode and before any
* UCPD configuration update.
* @rmtoll UCPDR UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
{
CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
}
/**
* @brief Check the USB Type-C and Power Delivery Standby mode memorization state.
* @rmtoll UCPDR UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
{
return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY) == (PWR_UCPDR_UCPD_STDBY)) ? 1UL : 0UL);
}
/**
* @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
* on UCPD CC1 and CC2 pins.
* @note After exiting reset, the USB Type-C dead battery behavior is enabled,
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended
* to disable it in all cases, either to stop this pull-down or to hand over
* control to the UCPD (which should therefore be initialized before doing the disable).
* @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
{
CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
}
/**
* @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
* on UCPD CC1 and CC2 pins.
* @note After exiting reset, the USB Type-C dead battery behavior is enabled,
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended
* to disable it in all cases, either to stop this pull-down or to hand over
* control to the UCPD (which should therefore be initialized before doing the disable).
* @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
{
SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
}
/**
* @brief Check the USB Type-C and power delivery dead battery pull-down behavior
* on UCPD CC1 and CC2 pins.
* @note After exiting reset, the USB Type-C dead battery behavior is enabled,
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended
* to disable it in all cases, either to stop this pull-down or to hand over
* control to the UCPD (which should therefore be initialized before doing the disable).
* @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
* @retval State of feature (1 : enabled; 0 : disabled).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
{
return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL);
}
/**
* @brief Enable the pull-up and pull-down configuration.
* @rmtoll APCR APC LL_PWR_EnablePUPDConfig
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePUPDConfig(void)
{
SET_BIT(PWR->APCR, PWR_APCR_APC);
}
/**
* @brief Disable the pull-up and pull-down configuration.
* @rmtoll APCR APC LL_PWR_DisablePUPDConfig
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePUPDConfig(void)
{
CLEAR_BIT(PWR->APCR, PWR_APCR_APC);
}
/**
* @brief Check if the pull-up and pull-down configuration is enabled.
* @rmtoll APCR APC LL_PWR_IsEnabledPUPDConfig
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDConfig(void)
{
return ((READ_BIT(PWR->APCR, PWR_APCR_APC) == (PWR_APCR_APC)) ? 1UL : 0UL);
}
/**
* @brief Enable GPIO pull-up in Standby and Shutdown modes
* @rmtoll PUCRx PUx LL_PWR_EnableGPIOPullUp
* @param GPIOPort This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_PORTA
* @arg @ref LL_PWR_GPIO_PORTB
* @arg @ref LL_PWR_GPIO_PORTC
* @arg @ref LL_PWR_GPIO_PORTD
* @arg @ref LL_PWR_GPIO_PORTE
* @arg @ref LL_PWR_GPIO_PORTF
* @arg @ref LL_PWR_GPIO_PORTG
* @arg @ref LL_PWR_GPIO_PORTH
* @arg @ref LL_PWR_GPIO_PORTI
* @arg @ref LL_PWR_GPIO_PORTJ (*)
* (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
* @param GPIOPin This parameter can be a combination of the following values:
* @arg @ref LL_PWR_GPIO_PIN_0
* @arg @ref LL_PWR_GPIO_PIN_1
* @arg @ref LL_PWR_GPIO_PIN_2
* @arg @ref LL_PWR_GPIO_PIN_3
* @arg @ref LL_PWR_GPIO_PIN_4
* @arg @ref LL_PWR_GPIO_PIN_5
* @arg @ref LL_PWR_GPIO_PIN_6
* @arg @ref LL_PWR_GPIO_PIN_7
* @arg @ref LL_PWR_GPIO_PIN_8
* @arg @ref LL_PWR_GPIO_PIN_9
* @arg @ref LL_PWR_GPIO_PIN_10
* @arg @ref LL_PWR_GPIO_PIN_11
* @arg @ref LL_PWR_GPIO_PIN_12
* @arg @ref LL_PWR_GPIO_PIN_13
* @arg @ref LL_PWR_GPIO_PIN_14
* @arg @ref LL_PWR_GPIO_PIN_15
* @retval None.
*/
__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
{
SET_BIT(*((uint32_t *)GPIOPort), GPIOPin);
}
/**
* @brief Disable GPIO pull-up in Standby and Shutdown modes
* @rmtoll PUCRx PUx LL_PWR_DisableGPIOPullUp
* @param GPIOPort This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_PORTA
* @arg @ref LL_PWR_GPIO_PORTB
* @arg @ref LL_PWR_GPIO_PORTC
* @arg @ref LL_PWR_GPIO_PORTD
* @arg @ref LL_PWR_GPIO_PORTE
* @arg @ref LL_PWR_GPIO_PORTF
* @arg @ref LL_PWR_GPIO_PORTG
* @arg @ref LL_PWR_GPIO_PORTH
* @arg @ref LL_PWR_GPIO_PORTI
* @arg @ref LL_PWR_GPIO_PORTJ (*)
* (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
* @param GPIOPin This parameter can be a combination of the following values:
* @arg @ref LL_PWR_GPIO_PIN_0
* @arg @ref LL_PWR_GPIO_PIN_1
* @arg @ref LL_PWR_GPIO_PIN_2
* @arg @ref LL_PWR_GPIO_PIN_3
* @arg @ref LL_PWR_GPIO_PIN_4
* @arg @ref LL_PWR_GPIO_PIN_5
* @arg @ref LL_PWR_GPIO_PIN_6
* @arg @ref LL_PWR_GPIO_PIN_7
* @arg @ref LL_PWR_GPIO_PIN_8
* @arg @ref LL_PWR_GPIO_PIN_9
* @arg @ref LL_PWR_GPIO_PIN_10
* @arg @ref LL_PWR_GPIO_PIN_11
* @arg @ref LL_PWR_GPIO_PIN_12
* @arg @ref LL_PWR_GPIO_PIN_13
* @arg @ref LL_PWR_GPIO_PIN_14
* @arg @ref LL_PWR_GPIO_PIN_15
* @retval None.
*/
__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
{
CLEAR_BIT(*((uint32_t *)GPIOPort), GPIOPin);
}
/**
* @brief Check if GPIO pull-up in Standby and Shutdown modes is enabled
* @rmtoll PUCRx PUx LL_PWR_IsEnabledGPIOPullUp
* @param GPIOPort This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_PORTA
* @arg @ref LL_PWR_GPIO_PORTB
* @arg @ref LL_PWR_GPIO_PORTC
* @arg @ref LL_PWR_GPIO_PORTD
* @arg @ref LL_PWR_GPIO_PORTE
* @arg @ref LL_PWR_GPIO_PORTF
* @arg @ref LL_PWR_GPIO_PORTG
* @arg @ref LL_PWR_GPIO_PORTH
* @arg @ref LL_PWR_GPIO_PORTI
* @arg @ref LL_PWR_GPIO_PORTJ (*)
* (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
* @param GPIOPin This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_PIN_0
* @arg @ref LL_PWR_GPIO_PIN_1
* @arg @ref LL_PWR_GPIO_PIN_2
* @arg @ref LL_PWR_GPIO_PIN_3
* @arg @ref LL_PWR_GPIO_PIN_4
* @arg @ref LL_PWR_GPIO_PIN_5
* @arg @ref LL_PWR_GPIO_PIN_6
* @arg @ref LL_PWR_GPIO_PIN_7
* @arg @ref LL_PWR_GPIO_PIN_8
* @arg @ref LL_PWR_GPIO_PIN_9
* @arg @ref LL_PWR_GPIO_PIN_10
* @arg @ref LL_PWR_GPIO_PIN_11
* @arg @ref LL_PWR_GPIO_PIN_12
* @arg @ref LL_PWR_GPIO_PIN_13
* @arg @ref LL_PWR_GPIO_PIN_14
* @arg @ref LL_PWR_GPIO_PIN_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin)
{
return ((READ_BIT(*((uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
}
/**
* @brief Enable GPIO pull-down in Standby and Shutdown modes.
* @rmtoll PDCRx PDx LL_PWR_EnableGPIOPullDown
* @param GPIOPort This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_PORTA
* @arg @ref LL_PWR_GPIO_PORTB
* @arg @ref LL_PWR_GPIO_PORTC
* @arg @ref LL_PWR_GPIO_PORTD
* @arg @ref LL_PWR_GPIO_PORTE
* @arg @ref LL_PWR_GPIO_PORTF
* @arg @ref LL_PWR_GPIO_PORTG
* @arg @ref LL_PWR_GPIO_PORTH
* @arg @ref LL_PWR_GPIO_PORTI
* @arg @ref LL_PWR_GPIO_PORTJ (*)
* (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
* @param GPIOPin This parameter can be a combination of the following values:
* @arg @ref LL_PWR_GPIO_PIN_0
* @arg @ref LL_PWR_GPIO_PIN_1
* @arg @ref LL_PWR_GPIO_PIN_2
* @arg @ref LL_PWR_GPIO_PIN_3
* @arg @ref LL_PWR_GPIO_PIN_4
* @arg @ref LL_PWR_GPIO_PIN_5
* @arg @ref LL_PWR_GPIO_PIN_6
* @arg @ref LL_PWR_GPIO_PIN_7
* @arg @ref LL_PWR_GPIO_PIN_8
* @arg @ref LL_PWR_GPIO_PIN_9
* @arg @ref LL_PWR_GPIO_PIN_10
* @arg @ref LL_PWR_GPIO_PIN_11
* @arg @ref LL_PWR_GPIO_PIN_12
* @arg @ref LL_PWR_GPIO_PIN_13
* @arg @ref LL_PWR_GPIO_PIN_14
* @arg @ref LL_PWR_GPIO_PIN_15
* @retval None.
*/
__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
{
SET_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin);
}
/**
* @brief Disable GPIO pull-down in Standby and Shutdown modes.
* @rmtoll PDCRx PDx LL_PWR_DisableGPIOPullDown
* @param GPIOPort This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_PORTA
* @arg @ref LL_PWR_GPIO_PORTB
* @arg @ref LL_PWR_GPIO_PORTC
* @arg @ref LL_PWR_GPIO_PORTD
* @arg @ref LL_PWR_GPIO_PORTE
* @arg @ref LL_PWR_GPIO_PORTF
* @arg @ref LL_PWR_GPIO_PORTG
* @arg @ref LL_PWR_GPIO_PORTH
* @arg @ref LL_PWR_GPIO_PORTI
* @arg @ref LL_PWR_GPIO_PORTJ (*)
* (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
* @param GPIOPin This parameter can be a combination of the following values:
* @arg @ref LL_PWR_GPIO_PIN_0
* @arg @ref LL_PWR_GPIO_PIN_1
* @arg @ref LL_PWR_GPIO_PIN_2
* @arg @ref LL_PWR_GPIO_PIN_3
* @arg @ref LL_PWR_GPIO_PIN_4
* @arg @ref LL_PWR_GPIO_PIN_5
* @arg @ref LL_PWR_GPIO_PIN_6
* @arg @ref LL_PWR_GPIO_PIN_7
* @arg @ref LL_PWR_GPIO_PIN_8
* @arg @ref LL_PWR_GPIO_PIN_9
* @arg @ref LL_PWR_GPIO_PIN_10
* @arg @ref LL_PWR_GPIO_PIN_11
* @arg @ref LL_PWR_GPIO_PIN_12
* @arg @ref LL_PWR_GPIO_PIN_13
* @arg @ref LL_PWR_GPIO_PIN_14
* @arg @ref LL_PWR_GPIO_PIN_15
* @retval None.
*/
__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
{
CLEAR_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin);
}
/**
* @brief Check if GPIO pull-down in Standby and Shutdown modes is enabled
* @rmtoll PDCRx PDx LL_PWR_IsEnabledGPIOPullUp
* @param GPIOPort This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_PORTA
* @arg @ref LL_PWR_GPIO_PORTB
* @arg @ref LL_PWR_GPIO_PORTC
* @arg @ref LL_PWR_GPIO_PORTD
* @arg @ref LL_PWR_GPIO_PORTE
* @arg @ref LL_PWR_GPIO_PORTF
* @arg @ref LL_PWR_GPIO_PORTG
* @arg @ref LL_PWR_GPIO_PORTH
* @arg @ref LL_PWR_GPIO_PORTI
* @arg @ref LL_PWR_GPIO_PORTJ (*)
* (*) value can be used only for STM32U59xxx and STM32U5A9xx devices.
* @param GPIOPin This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_PIN_0
* @arg @ref LL_PWR_GPIO_PIN_1
* @arg @ref LL_PWR_GPIO_PIN_2
* @arg @ref LL_PWR_GPIO_PIN_3
* @arg @ref LL_PWR_GPIO_PIN_4
* @arg @ref LL_PWR_GPIO_PIN_5
* @arg @ref LL_PWR_GPIO_PIN_6
* @arg @ref LL_PWR_GPIO_PIN_7
* @arg @ref LL_PWR_GPIO_PIN_8
* @arg @ref LL_PWR_GPIO_PIN_9
* @arg @ref LL_PWR_GPIO_PIN_10
* @arg @ref LL_PWR_GPIO_PIN_11
* @arg @ref LL_PWR_GPIO_PIN_12
* @arg @ref LL_PWR_GPIO_PIN_13
* @arg @ref LL_PWR_GPIO_PIN_14
* @arg @ref LL_PWR_GPIO_PIN_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin)
{
return ((READ_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL);
}
/**
* @brief Get currently voltage scaling applied to VCORE.
* @rmtoll SVMSR ACTVOS[1:0] LL_PWR_GetRegulCurrentVOS
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4
*/
__STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void)
{
return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS));
}
/**
* @}
*/
/** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management
* @{
*/
/**
* @brief Indicate whether the EPOD (Embedded Power Distribution) booster is
* ready OR not.
* @rmtoll VOSR BOOSTRDY LL_PWR_IsActiveFlag_BOOST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BOOST(void)
{
return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == (PWR_VOSR_BOOSTRDY)) ? 1UL : 0UL);
}
#if defined (PWR_VOSR_USBBOOSTRDY)
/**
* @brief Indicate whether the USB EPOD (Embedded Power Distribution) booster is
* ready OR not.
* @rmtoll VOSR USBBOOSTRDY LL_PWR_IsActiveFlag_USBBOOST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USBBOOST(void)
{
return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == (PWR_VOSR_USBBOOSTRDY)) ? 1UL : 0UL);
}
#endif /* defined (PWR_VOSR_USBBOOSTRDY) */
/**
* @brief Indicate whether the regulator voltage output is above voltage
* scaling range or not.
* @rmtoll VOSR VOSRDY LL_PWR_IsActiveFlag_VOS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
{
return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the system was in standby mode or not.
* @rmtoll SR SBF LL_PWR_IsActiveFlag_SB
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
{
return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the system was in stop mode or not.
* @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void)
{
return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the regulator supply is LDO or SMPS.
* @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void)
{
return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the VDD voltage is below the threshold or not.
* @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
{
return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the regulator voltage output is equal to current
* used voltage scaling range or not.
* @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
{
return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the VDDUSB is below the threshold of monitor or not.
* @rmtoll SVMSR VDDUSBRDY LL_PWR_IsActiveFlag_VDDUSB
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDUSB(void)
{
return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == (PWR_SVMSR_VDDUSBRDY)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the VDDIO2 is below the threshold of monitor or not.
* @rmtoll SVMSR VDDIO2RDY LL_PWR_IsActiveFlag_VDDIO2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2(void)
{
return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == (PWR_SVMSR_VDDIO2RDY)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the VDDA1 is below the threshold of monitor 1 or
* not.
* @rmtoll SVMSR VDDA1RDY LL_PWR_IsActiveFlag_VDDA1
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA1(void)
{
return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == (PWR_SVMSR_VDDA1RDY)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the VDDA2 is below the threshold of monitor 2 or
* not.
* @rmtoll SVMSR VDDA2RDY LL_PWR_IsActiveFlag_VDDA2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA2(void)
{
return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == (PWR_SVMSR_VDDA2RDY)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the VBAT level is below high threshold or not.
* @rmtoll BDSR VBATH LL_PWR_IsActiveFlag_VBATH
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
{
return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the CPU temperature level is above low threshold or
* not.
* @rmtoll BDSR TEMPL LL_PWR_IsActiveFlag_TEMPL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
{
return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether the CPU temperature level is below high threshold
* or not.
* @rmtoll BDSR TEMPH LL_PWR_IsActiveFlag_TEMPH
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
{
return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether a wakeup event is detected on wake up pin 1.
* @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
{
return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether a wakeup event is detected on wake up pin 2.
* @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
{
return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether a wakeup event is detected on wake up pin 3.
* @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
{
return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether a wakeup event is detected on wake up pin 4.
* @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
{
return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether a wakeup event is detected on wake up pin 5.
* @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
{
return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether a wakeup event is detected on wake up pin 6.
* @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
{
return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether a wakeup event is detected on wake up pin 7.
* @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void)
{
return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL);
}
/**
* @brief Indicate whether a wakeup event is detected on wake up pin 8.
* @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void)
{
return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL);
}
/**
* @brief Clear stop flag.
* @rmtoll SR CSSF LL_PWR_ClearFlag_STOP
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_STOP(void)
{
WRITE_REG(PWR->SR, PWR_SR_CSSF);
}
/**
* @brief Clear standby flag.
* @rmtoll SR CSSF LL_PWR_ClearFlag_SB
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
{
WRITE_REG(PWR->SR, PWR_SR_CSSF);
}
/**
* @brief Clear wake up flag 1.
* @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
{
WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1);
}
/**
* @brief Clear wake up flag 2.
* @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
{
WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2);
}
/**
* @brief Clear wake up flag 3.
* @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
{
WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3);
}
/**
* @brief Clear wake up flag 4.
* @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
{
WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4);
}
/**
* @brief Clear wake up flag 5.
* @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
{
WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5);
}
/**
* @brief Clear wake up flag 6.
* @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
{
WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6);
}
/**
* @brief Clear wake up flag 7.
* @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU7(void)
{
WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7);
}
/**
* @brief Clear wake up flag 8.
* @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU8(void)
{
WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8);
}
/**
* @brief Clear all wake up flags.
* @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
{
WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF);
}
/**
* @}
*/
/** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management
* @{
*/
/**
* @brief Enable privileged mode for nsecure items.
* @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void)
{
SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
}
/**
* @brief Disable privileged mode for nsecure items.
* @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void)
{
CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
}
/**
* @brief Check if privileged mode for nsecure items is enabled.
* @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void)
{
return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Enable privileged mode for secure items.
* @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void)
{
SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
}
/**
* @brief Disable privileged mode for secure items.
* @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void)
{
CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief Check if privileged mode for secure items is enabled.
* @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void)
{
return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Configure secure attribute mode.
* @note This API can be executed only by CPU in secure mode.
* @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n
* SECCFGR WUP2SEC LL_PWR_ConfigSecure\n
* SECCFGR WUP3SEC LL_PWR_ConfigSecure\n
* SECCFGR WUP4SEC LL_PWR_ConfigSecure\n
* SECCFGR WUP5SEC LL_PWR_ConfigSecure\n
* SECCFGR WUP6SEC LL_PWR_ConfigSecure\n
* SECCFGR WUP7SEC LL_PWR_ConfigSecure\n
* SECCFGR WUP8SEC LL_PWR_ConfigSecure\n
* SECCFGR LPMSEC LL_PWR_ConfigSecure\n
* SECCFGR VDMSEC LL_PWR_ConfigSecure\n
* SECCFGR VBSEC LL_PWR_ConfigSecure\n
* SECCFGR APCSEC LL_PWR_ConfigSecure
* @param SecureConfig This parameter can be the full combination
* of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
* @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
* @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
* @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
* @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
* @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
* @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
* @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
* @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
* @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
* @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
* @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
* @retval None.
*/
__STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig)
{
WRITE_REG(PWR->SECCFGR, SecureConfig);
}
/**
* @brief Get secure attribute configuration.
* @note This API can be executed only by CPU in secure mode.
* @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n
* SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n
* SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n
* SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n
* SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n
* SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n
* SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n
* SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n
* SECCFGR LPMSEC LL_PWR_GetConfigSecure\n
* SECCFGR VDMSEC LL_PWR_GetConfigSecure\n
* SECCFGR VBSEC LL_PWR_GetConfigSecure\n
* SECCFGR APCSEC LL_PWR_GetConfigSecure
* @retval Returned value is the combination of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC
* @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC
* @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC
* @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC
* @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC
* @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC
* @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC
* @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC
* @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC
* @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC
* @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC
* @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC
*/
__STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
{
return (READ_REG(PWR->SECCFGR));
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @}
*/
#if defined (USE_FULL_LL_DRIVER)
/** @defgroup PWR_LL_EF_Init De-initialization function
* @{
*/
ErrorStatus LL_PWR_DeInit(void);
/**
* @}
*/
#endif /* defined (USE_FULL_LL_DRIVER) */
/**
* @}
*/
/**
* @}
*/
#endif /* defined (PWR) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32U5xx_LL_PWR_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h
|
C
|
apache-2.0
| 123,488
|
/**
******************************************************************************
* @file stm32u5xx_ll_rcc.h
* @author MCD Application Team
* @brief Header file of RCC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_RCC_H
#define STM32U5xx_LL_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(RCC)
/** @defgroup RCC_LL RCC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RCC_LL_Private_Constants RCC Private Constants
* @{
*/
/* Defines used to perform offsets*/
/* Offset used to access to RCC_CCIPR1 and RCC_CCIPR2 registers */
#define RCC_OFFSET_CCIPR1 0U
#define RCC_OFFSET_CCIPR2 0x04U
#define RCC_OFFSET_CCIPR3 0x08U
/* Defines used for security configuration extension */
#define RCC_SECURE_MASK 0x1FFFU
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_Exported_Types RCC Exported Types
* @{
*/
/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
* @{
*/
/**
* @brief RCC Clocks Frequency Structure
*/
typedef struct
{
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
uint32_t PCLK3_Frequency; /*!< PCLK3 clock frequency */
} LL_RCC_ClocksTypeDef;
/**
* @}
*/
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
* @{
*/
/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
* @brief Defines used to adapt values of different oscillators
* @note These values could be modified in the user environment according to
* HW set-up.
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
#endif /* HSI_VALUE */
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
#endif /* LSI_VALUE */
#if !defined (HSI48_VALUE)
#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
#endif /* HSI48_VALUE */
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */
#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LSIPRE LSI prescaler
* @{
*/
#define LL_RCC_LSI_DIV_1 0x00000000U /*!< LSI divided by 1 */
#define LL_RCC_LSI_DIV_128 RCC_BDCR_LSIPREDIV /*!< LSI divided by 128 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
* @{
*/
#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MSI_OSCILLATOR MSI clock Trimming
* @{
*/
#define LL_RCC_MSI_OSCILLATOR_0 0x00000000U /*!< MSI clock trimming for ranges 0 to 3 */
#define LL_RCC_MSI_OSCILLATOR_1 0x00000005U /*!< MSI clock trimming for ranges 4 to 7 */
#define LL_RCC_MSI_OSCILLATOR_2 0x0000000AU /*!< MSI clock trimming for ranges 8 to 11 */
#define LL_RCC_MSI_OSCILLATOR_3 0x0000000FU /*!< MSI clock trimming for ranges 12 to 15 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MSISRANGE MSIS Clock Range
* @{
*/
#define LL_RCC_MSISRANGE_0 0x00000000U /*!< MSIS = 48 MHz */
#define LL_RCC_MSISRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSIS = 24 MHz */
#define LL_RCC_MSISRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSIS = 16 MHz */
#define LL_RCC_MSISRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSIS = 12 MHz */
#define LL_RCC_MSISRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSIS = 4 MHz */
#define LL_RCC_MSISRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 2 MHz */
#define LL_RCC_MSISRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 1.5 MHz */
#define LL_RCC_MSISRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 1 MHz */
#define LL_RCC_MSISRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSIS = 3.072 MHz */
#define LL_RCC_MSISRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 1.536 MHz */
#define LL_RCC_MSISRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 1.024 MHz */
#define LL_RCC_MSISRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 768 KHz */
#define LL_RCC_MSISRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 400 KHz */
#define LL_RCC_MSISRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 200 KHz */
#define LL_RCC_MSISRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 150 KHz */
#define LL_RCC_MSISRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 | \
RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 100 KHz */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MSIKRANGE MSIK Clock Range
* @{
*/
#define LL_RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */
#define LL_RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */
#define LL_RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */
#define LL_RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */
#define LL_RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */
#define LL_RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */
#define LL_RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.5 MHz */
#define LL_RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */
#define LL_RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */
#define LL_RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */
#define LL_RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */
#define LL_RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */
#define LL_RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */
#define LL_RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */
#define LL_RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 150 KHz */
#define LL_RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | \
RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MSISSRANGE MSIS range after Standby mode
* @{
*/
#define LL_RCC_MSISSRANGE_4 RCC_CSR_MSISSRANGE_2 /*!< MSIS = 4 MHz */
#define LL_RCC_MSISSRANGE_5 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_0) /*!< MSIS = 2 MHz */
#define LL_RCC_MSISSRANGE_6 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1) /*!< MSIS = 1.5 MHz */
#define LL_RCC_MSISSRANGE_7 (RCC_CSR_MSISSRANGE_0 | RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1) /*!< MSIS = 1 MHz */
#define LL_RCC_MSISSRANGE_8 RCC_CSR_MSISSRANGE_3 /*!< MSIS = 3.072 MHz*/
/**
* @}
*/
/** @defgroup RCC_LL_EC_MSIKSRANGE MSIK range after Standby mode
* @{
*/
#define LL_RCC_MSIKSRANGE_4 RCC_CSR_MSIKSRANGE_2 /*!< MSIK = 4 MHz */
#define LL_RCC_MSIKSRANGE_5 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 2 MHz */
#define LL_RCC_MSIKSRANGE_6 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1) /*!< MSIK = 1.5 MHz */
#define LL_RCC_MSIKSRANGE_7 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 1 MHz */
#define LL_RCC_MSIKSRANGE_8 RCC_CSR_MSIKSRANGE_3 /*!< MSIK = 3.072 MHz*/
/**
* @}
*/
/** @defgroup RCC_LL_EC_MSIPLLMODE MSIS/MSIK Pll Mode
* @{
*/
#define LL_RCC_PLLMODE_MSIS RCC_CR_MSIPLLSEL /*!< MSIS selection for Pll Mode */
#define LL_RCC_PLLMODE_MSIK 0U /*!< MSIK selection for Pll Mode */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MSIBIASMODE MSI BIAS Mode
* @{
*/
#define LL_RCC_MSIBIASMODE_SAMPLING RCC_ICSCR1_MSIBIAS /*!< Sampling mode selection for MSI*/
#define LL_RCC_MSIBIASMODE_CONTINUOUS 0U /*!< Continuous mode selection for MSI*/
/**
* @}
*/
/** @defgroup RCC_LL_EC_HSEEXT EXTERNAL HSE Mode
* @{
*/
#define LL_RCC_HSE_ANALOG_MODE 0U /*!< HSE clock used as ANALOG clock source */
#define LL_RCC_HSE_DIGITAL_MODE RCC_CR_HSEEXT /*!< HSE clock used as DIGITAL clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
* @{
*/
#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLL1MBOOST_DIV EPOD prescaler
* @{
*/
#define LL_RCC_PLL1MBOOST_DIV_1 0x00000000U /*!< PLL1CLK not divided */
#define LL_RCC_PLL1MBOOST_DIV_2 RCC_PLL1CFGR_PLL1MBOOST_0 /*!< PLL1CLK divided by 2 */
#define LL_RCC_PLL1MBOOST_DIV_4 RCC_PLL1CFGR_PLL1MBOOST_1 /*!< PLL1CLK divided by 4 */
#define LL_RCC_PLL1MBOOST_DIV_6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 6 */
#define LL_RCC_PLL1MBOOST_DIV_8 RCC_PLL1CFGR_PLL1MBOOST_2 /*!< PLL1CLK divided by 8 */
#define LL_RCC_PLL1MBOOST_DIV_10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 10 */
#define LL_RCC_PLL1MBOOST_DIV_12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) /*!< PLL1CLK divided by 12 */
#define LL_RCC_PLL1MBOOST_DIV_14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1 | \
RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 14 */
#define LL_RCC_PLL1MBOOST_DIV_16 RCC_PLL1CFGR_PLL1MBOOST_3 /*!< PLL1CLK divided by 16 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
* @{
*/
#define LL_RCC_SYS_CLKSOURCE_MSIS 0x00000000U /*!< MSIS selection as system clock */
#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI oscillator selection as system clock */
#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */
#define LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL selection as system clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
* @{
*/
#define LL_RCC_SYS_CLKSOURCE_STATUS_MSIS 0x00000000U /*!< MSIS used as system clock */
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */
#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1 used as system clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
* @{
*/
#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */
#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */
#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */
#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */
#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2) /*!< SYSCLK divided by 64 */
#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 128 */
#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 256 */
#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | \
RCC_CFGR2_HPRE_0)/*!< SYSCLK divided by 512 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection
* @{
*/
#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0x00000000U /*!< HCLKDIV8 clock used as SYSTICK clock source */
#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */
#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
* @{
*/
#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */
#define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */
#define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */
#define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */
#define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
* @{
*/
#define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK not divided */
#define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */
#define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */
#define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */
#define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_APB3_DIV APB high-speed prescaler (APB3)
* @{
*/
#define LL_RCC_APB3_DIV_1 0x00000000U /*!< HCLK not divided */
#define LL_RCC_APB3_DIV_2 RCC_CFGR3_PPRE3_2 /*!< HCLK divided by 2 */
#define LL_RCC_APB3_DIV_4 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_0) /*!< HCLK divided by 4 */
#define LL_RCC_APB3_DIV_8 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1) /*!< HCLK divided by 8 */
#define LL_RCC_APB3_DIV_16 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1 | RCC_CFGR3_PPRE3_0) /*!< HCLK divided by 16 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
* @{
*/
#define LL_RCC_STOP_WAKEUPCLOCK_MSIS 0x00000000U /*!< MSIS selection after wake-up from STOP */
#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
* @{
*/
#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_MSIS RCC_CFGR1_MCOSEL_1 /*!< MSIS selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1| RCC_CFGR1_MCOSEL_2)/*!< LSE selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
* @{
*/
#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */
#define LL_RCC_MCO1_DIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO divided by 2 */
#define LL_RCC_MCO1_DIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO divided by 4 */
#define LL_RCC_MCO1_DIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO divided by 8 */
#define LL_RCC_MCO1_DIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO divided by 16 */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
* @{
*/
#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
* @{
*/
#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection
* @{
*/
#define LL_RCC_USART1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U)| (RCC_CCIPR1_USART1SEL_Pos << 16U)) /*!< PCLK2 clock used as USART1 clock source */
#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_0 >> RCC_CCIPR1_USART1SEL_Pos)) /*!< SYSCLK clock used as USART1 clock source */
#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_1 >> RCC_CCIPR1_USART1SEL_Pos)) /*!< HSI clock used as USART1 clock source */
#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< LSE clock used as USART1 clock source */
#define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U)) /*!< PCLK1 clock used as USART2 clock source */
#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_0 >> RCC_CCIPR1_USART2SEL_Pos)) /*!< SYSCLK clock used as USART2 clock source */
#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_1 >> RCC_CCIPR1_USART2SEL_Pos)) /*!< HSI clock used as USART2 clock source */
#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< LSE clock used as USART2 clock source */
#define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U)) /*!< PCLK3 clock used as USART3 clock source */
#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_0 >> RCC_CCIPR1_USART3SEL_Pos)) /*!< SYSCLK clock used as USART3 clock source */
#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_1 >> RCC_CCIPR1_USART3SEL_Pos)) /*!< HSI clock used as USART3 clock source */
#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos)) /*!< LSE clock used as USART3 clock source */
#if defined (RCC_CCIPR2_USART6SEL)
#define LL_RCC_USART6_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U)) /*!< PCLK1 clock used as USART6 clock source */
#define LL_RCC_USART6_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_0 >> RCC_CCIPR2_USART6SEL_Pos)) /*!< SYSCLK clock used as USART6 clock source */
#define LL_RCC_USART6_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_1 >> RCC_CCIPR2_USART6SEL_Pos)) /*!< HSI clock used as USART6 clock source */
#define LL_RCC_USART6_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos)) /*!< LSE clock used as USART6 clock source */
/* Legacy define */
#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_RCC_USART6_CLKSOURCE_PCLK1
#endif /* RCC_CCIPR2_USART6SEL */
/**
* @}
*/
/** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UARTx clock source selection
* @{
*/
#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL) /*!< LSE clock used as UART4 clock source */
#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL) /*!< LSE clock used as UART5 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection
* @{
*/
#define LL_RCC_LPUART1_CLKSOURCE_PCLK3 0x00000000U /*!< PCLK3 clock used as LPUART1 clock source */
#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< LSE clock used as LPUART1 clock source */
#define LL_RCC_LPUART1_CLKSOURCE_MSIK RCC_CCIPR3_LPUART1SEL_2 /*!< MSIK clock used as LPUART1 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection
* @{
*/
#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
#define LL_RCC_I2C1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< MSIK clock used as I2C1 clock source */
#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
#define LL_RCC_I2C2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< MSIK clock used as I2C2 clock source */
#define LL_RCC_I2C3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK3 clock used as I2C3 clock source */
#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \
(RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \
(RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
#define LL_RCC_I2C3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \
(RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< MSIK clock used as I2C3 clock source */
#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C4SEL_0 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C4SEL_1 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
#define LL_RCC_I2C4_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< MSIK clock used as I2C4 clock source */
#if defined (RCC_CCIPR2_I2C5SEL)
#define LL_RCC_I2C5_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C5 clock source */
#define LL_RCC_I2C5_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \
(RCC_CCIPR2_I2C5SEL_0 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< SYSCLK clock used as I2C5 clock source */
#define LL_RCC_I2C5_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \
(RCC_CCIPR2_I2C5SEL_1 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< HSI clock used as I2C5 clock source */
#define LL_RCC_I2C5_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \
(RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< MSIK clock used as I2C5 clock source */
#endif /* RCC_CCIPR2_I2C5SEL */
#if defined (RCC_CCIPR2_I2C6SEL)
#define LL_RCC_I2C6_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C6 clock source */
#define LL_RCC_I2C6_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \
(RCC_CCIPR2_I2C6SEL_0 >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< SYSCLK clock used as I2C6 clock source */
#define LL_RCC_I2C6_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \
(RCC_CCIPR2_I2C6SEL_1 >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< HSI clock used as I2C6 clock source */
#define LL_RCC_I2C6_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \
(RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< MSIK clock used as I2C6 clock source */
#endif /* RCC_CCIPR2_I2C6SEL */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection
* @{
*/
#define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U)) /*!< PCLK2 clock used as SPI1 clock source */
#define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \
(RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */
#define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \
(RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */
#define LL_RCC_SPI1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \
(RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< MSIK clock used as SPI1 clock source */
#define LL_RCC_SPI2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U)) /*!< PCLK1 clock used as SPI2 clock source */
#define LL_RCC_SPI2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \
(RCC_CCIPR1_SPI2SEL_0 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SYSCLK clock used as SPI2 clock source */
#define LL_RCC_SPI2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \
(RCC_CCIPR1_SPI2SEL_1 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< HSI clock used as SPI2 clock source */
#define LL_RCC_SPI2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \
(RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< MSIK clock used as SPI2 clock source */
#define LL_RCC_SPI3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK3 clock used as SPI3 clock source */
#define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \
(RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */
#define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \
(RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */
#define LL_RCC_SPI3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \
(RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< MSIK clock used as SPI3 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection
* @{
*/
#define LL_RCC_LPTIM1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U)) /*!< MSIK clock used as LPTIM1 clock source */
#define LL_RCC_LPTIM1_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \
(RCC_CCIPR3_LPTIM1SEL_0 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSI clock used as LPTIM1 clock source */
#define LL_RCC_LPTIM1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \
(RCC_CCIPR3_LPTIM1SEL_1 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< HSI clock used as LPTIM1 clock source */
#define LL_RCC_LPTIM1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \
(RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSE clock used as LPTIM1 clock source */
#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U)) /*!< PCLK1 clock used as LPTIM2 clock source */
#define LL_RCC_LPTIM2_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \
(RCC_CCIPR1_LPTIM2SEL_0 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSI clock used as LPTIM2 clock source */
#define LL_RCC_LPTIM2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \
(RCC_CCIPR1_LPTIM2SEL_1 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< HSI clock used as LPTIM2 clock source */
#define LL_RCC_LPTIM2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \
(RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSE clock used as LPTIM2 clock source */
#define LL_RCC_LPTIM34_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U)) /*!< MSIK clock used as LPTIM34 clock source*/
#define LL_RCC_LPTIM34_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \
(RCC_CCIPR3_LPTIM34SEL_0 >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LSI clock used as LPTIM34 clock source */
#define LL_RCC_LPTIM34_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \
(RCC_CCIPR3_LPTIM34SEL_1 >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< HSI clock used as LPTIM34 clock source */
#define LL_RCC_LPTIM34_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \
(RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LSE clock used as LPTIM34 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN kernel clock source selection
* @{
*/
#define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN kernel clock source */
#define LL_RCC_FDCAN_CLKSOURCE_PLL1 RCC_CCIPR1_FDCANSEL_0 /*!< PLL1 Q clock used as FDCAN kernel clock source */
#define LL_RCC_FDCAN_CLKSOURCE_PLL2 RCC_CCIPR1_FDCANSEL_1 /*!< PLL2 P clock used as FDCAN kernel clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection
* @{
*/
#define LL_RCC_SAI1_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL2 clock used as SAI1 clock source */
#define LL_RCC_SAI1_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLL3 clock used as SAI1 clock source */
#define LL_RCC_SAI1_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLL1 clock used as SAI1 clock source */
#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */
#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | \
RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */
#define LL_RCC_SAI2_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL2 clock used as SAI2 clock source */
#define LL_RCC_SAI2_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLL3 clock used as SAI2 clock source */
#define LL_RCC_SAI2_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL1clock used as SAI2 clock source */
#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */
#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | \
RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SDMMC_KERNELCLKSOURCE Peripheral SDMMC1/2 kernel clock source selection
* @{
*/
#define LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1/2 clock source */
#define LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 RCC_CCIPR2_SDMMCSEL /*!< PLL1 "P" used as SDMMC1/2 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SDMMC12_CLKSOURCE Peripheral SDMMC clock source selection
* @{
*/
#define LL_RCC_SDMMC12_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1/2 clock source */
#define LL_RCC_SDMMC12_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 /*!< PLL2 "Q" clock used as SDMMC1/2 clock source */
#define LL_RCC_SDMMC12_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 /*!< PLL1 "Q" clock used as SDMMC1/2 clock source */
#define LL_RCC_SDMMC12_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL /*!< MSIK clock used as SDMMC1/2 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
* @{
*/
#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
#define LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 RCC_CCIPR2_RNGSEL_0 /*!< HSI48/2 clock used as RNG clock source */
#define LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 /*!< HSI clock used as RNG clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
* @{
*/
#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
#define LL_RCC_USB_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 /*!< PLL2 "Q" clock used as USB clock source */
#define LL_RCC_USB_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 /*!< PLL1 "Q" clock used as USB clock source */
#define LL_RCC_USB_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL /*!< MSIK clock used as USB clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_ADCDAC_CLKSOURCE Peripheral ADCx and DAC1 clock source selection
* @{
*/
#define LL_RCC_ADCDAC_CLKSOURCE_HCLK 0x00000000U /*!< No clock used as ADCx/DAC1 clock source */
#define LL_RCC_ADCDAC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCDACSEL_0 /*!< SYSCLK clock used as ADCx/DAC1 clock source */
#define LL_RCC_ADCDAC_CLKSOURCE_PLL2 RCC_CCIPR3_ADCDACSEL_1 /*!< PLL2 clock used as ADCx/DAC1 clock source */
#define LL_RCC_ADCDAC_CLKSOURCE_HSI RCC_CCIPR3_ADCDACSEL_2 /*!< HSI clock used as ADCx/DAC1 clock source */
#define LL_RCC_ADCDAC_CLKSOURCE_HSE (RCC_CCIPR3_ADCDACSEL_1 | RCC_CCIPR3_ADCDACSEL_0) /*!< HSE clock used as ADCx/DAC1 clock source */
#define LL_RCC_ADCDAC_CLKSOURCE_MSIK (RCC_CCIPR3_ADCDACSEL_2 | RCC_CCIPR3_ADCDACSEL_0) /*!< MSIK clock used as ADCx/DAC1 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_DAC1_CLKSOURCE Peripheral DAC1 clock source selection
* @{
*/
#define LL_RCC_DAC1_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as DAC1 clock */
#define LL_RCC_DAC1_CLKSOURCE_LSI RCC_CCIPR3_DAC1SEL /*!< LSI clock used as DAC1 clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_ADF1_CLKSOURCE Peripheral ADF1 clock source selection
* @{
*/
#define LL_RCC_ADF1_CLKSOURCE_HCLK 0x00000000U /*!< HCLK clock used as ADF1 clock */
#define LL_RCC_ADF1_CLKSOURCE_PLL1 RCC_CCIPR3_ADF1SEL_0 /*!< PLL1 clock used as ADF1 clock */
#define LL_RCC_ADF1_CLKSOURCE_PLL3 RCC_CCIPR3_ADF1SEL_1 /*!< PLL3 clock used as ADF1 clock */
#define LL_RCC_ADF1_CLKSOURCE_MSIK RCC_CCIPR3_ADF1SEL_2 /*!< MSIK clock used as ADF1 clock */
#define LL_RCC_ADF1_CLKSOURCE_PIN (RCC_CCIPR3_ADF1SEL_1 | RCC_CCIPR3_ADF1SEL_0) /*!< PIN SAI1_EXTCLK clock used as ADF1 clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MDF1_CLKSOURCE Peripheral MDF1 clock source selection
* @{
*/
#define LL_RCC_MDF1_CLKSOURCE_HCLK 0x00000000U /*!< HCLK clock used as MDF1 clock */
#define LL_RCC_MDF1_CLKSOURCE_PLL1 RCC_CCIPR2_MDF1SEL_0 /*!< PLL1 clock used as MDF1 clock */
#define LL_RCC_MDF1_CLKSOURCE_PLL3 RCC_CCIPR2_MDF1SEL_1 /*!< PLL3 clock used as MDF1 clock */
#define LL_RCC_MDF1_CLKSOURCE_MSIK RCC_CCIPR2_MDF1SEL_2 /*!< MSIK clock used as MDF1 clock */
#define LL_RCC_MDF1_CLKSOURCE_PIN (RCC_CCIPR2_MDF1SEL_1 | RCC_CCIPR2_MDF1SEL_0) /*!< PIN SAI1_EXTCLK clock used as MDF1 clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_OCTOSPI_CLKSOURCE Peripheral OCTOSPI kernel clock source selection
* @{
*/
#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as OctoSPI kernel clock source */
#define LL_RCC_OCTOSPI_CLKSOURCE_MSIK RCC_CCIPR2_OCTOSPISEL_0 /*!< MSIK clock used as OctoSPI kernel clock source */
#define LL_RCC_OCTOSPI_CLKSOURCE_PLL1 RCC_CCIPR2_OCTOSPISEL_1 /*!< PLL1 "Q" clock used as OctoSPI kernel clock source */
#define LL_RCC_OCTOSPI_CLKSOURCE_PLL2 (RCC_CCIPR2_OCTOSPISEL_1|RCC_CCIPR2_OCTOSPISEL_0) /*!< PLL2 "Q" clock used as OctoSPI kernel clock source */
/**
* @}
*/
#if defined (HSPI1)
/** @defgroup RCC_LL_EC_HSPI1_CLKSOURCE Peripheral HSPI1 kernel clock source selection
* @{
*/
#define LL_RCC_HSPI_CLKSOURCE_SYSCLK (0x00000000U)
#define LL_RCC_HSPI_CLKSOURCE_PLL1 RCC_CCIPR2_HSPISEL_0
#define LL_RCC_HSPI_CLKSOURCE_PLL2 RCC_CCIPR2_HSPISEL_1
#define LL_RCC_HSPI_CLKSOURCE_PLL3 RCC_CCIPR2_HSPISEL
/**
* @}
*/
#endif /* HSPI1 */
/** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection
* @{
*/
#define LL_RCC_TIMIC_CLKSOURCE_NONE 0x00000000U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */
#define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL_2 /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */
#define LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 RCC_CCIPR1_TIMICSEL_2 /*!< MSIS/1024 selected for TIM16/TIM17 and LPTIM2 input capture */
#define LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1) /*!< MSIS/4 selected for TIM16/TIM17 and LPTIM2 input capture */
#define LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_0) /*!< MSIK/4 selected for TIM16/TIM17 and LPTIM2 input capture */
#define LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1 | \
RCC_CCIPR1_TIMICSEL_0) /*!< MSIK/1024 selected for TIM16/TIM17 and LPTIM2 input capture */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SAES_CLKSOURCE Peripheral SAES clock source selection
* @{
*/
#define LL_RCC_SAES_CLKSOURCE_SHSI 0x00000000U /*!< SHSI clock used as SAES clock source */
#define LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 RCC_CCIPR2_SAESSEL /*!< SHSI_DIV2 clock used as SAES clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source
* @{
*/
#define LL_RCC_USART1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART1SEL_Pos << 16U) | \
(RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< USART1 Clock source selection */
#define LL_RCC_USART2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART2SEL_Pos << 16U) | \
(RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< USART2 Clock source selection */
#define LL_RCC_USART3_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART3SEL_Pos << 16U) | \
(RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos)) /*!< USART3 Clock source selection */
#if defined (RCC_CCIPR2_USART6SEL)
#define LL_RCC_USART6_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | \
(RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos)) /*!< USART6 Clock source selection */
#endif /* RCC_CCIPR2_USART6SEL */
/**
* @}
*/
/** @defgroup RCC_LL_EC_UART Peripheral UARTx get clock source
* @{
*/
#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR1_UART4SEL /*!< UART4 Clock source selection */
#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR1_UART5SEL /*!< UART5 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source
* @{
*/
#define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \
(RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */
#define LL_RCC_SPI2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \
(RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SPI2 Clock source selection */
#define LL_RCC_SPI3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \
(RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SPI3 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source
* @{
*/
#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */
/**
* @}
*/
#if defined(DSI)
/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
* @{
*/
#define LL_RCC_DSI_CLKSOURCE_PHY (RCC_CCIPR2_DSIHOSTSEL)
#define LL_RCC_DSI_CLKSOURCE_PLL3 (0x00000000U)
/**
* @}
*/
#endif /* DSI */
#if defined(LTDC)
/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection
* @{
*/
#define LL_RCC_LTDC_CLKSOURCE_PLL2 (RCC_CCIPR2_LTDCSEL)
#define LL_RCC_LTDC_CLKSOURCE_PLL3 (0x00000000U)
/**
* @}
*/
#endif /* LTDC */
#if defined (RCC_CCIPR2_USBPHYCSEL)
/** @defgroup RCC_LL_EC_USBPHY_CLKSOURCE Peripheral USBPHY clock source selection
* @{
*/
#define LL_RCC_USBPHYCLKSOURCE_HSE (0x00000000U) /*!< HSE clock selected as USBPHYC clock */
#define LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 RCC_CCIPR2_USBPHYCSEL_1 /*!< HSE clock divided by 2 selected as USBPHYC clock */
#define LL_RCC_USBPHYCLKSOURCE_PLL1 RCC_CCIPR2_USBPHYCSEL_0 /*!< PLL1 divider P selected as USBPHYC clock */
#define LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 (RCC_CCIPR2_USBPHYCSEL_1 | RCC_CCIPR2_USBPHYCSEL_0) /*!< PLL1 divider P divided by 2 selected as USBPHYC clock */
/**
* @}
*/
#endif /* RCC_CCIPR2_USBPHYCSEL */
/** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source
* @{
*/
#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \
(RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \
(RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
#if defined (RCC_CCIPR2_I2C5SEL)
#define LL_RCC_I2C5_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \
(RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< I2C1 Clock source selection */
#endif /* RCC_CCIPR2_I2C5SEL */
#if defined (RCC_CCIPR2_I2C6SEL)
#define LL_RCC_I2C6_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \
(RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< I2C1 Clock source selection */
#endif /* RCC_CCIPR2_I2C6SEL */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source
* @{
*/
#define LL_RCC_LPTIM1_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \
(RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LPTIM1 Clock source selection */
#define LL_RCC_LPTIM2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \
(RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LPTIM2 Clock source selection */
#define LL_RCC_LPTIM34_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \
(RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LPTIM3 and LPTIM4 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source
* @{
*/
#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */
#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SDMMC_KERNEL Peripheral SDMMC get kernel clock source
* @{
*/
#define LL_RCC_SDMMC_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1/2 Kernel Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SDMMC1/2 Peripheral SDMMC get clock source
* @{
*/
#define LL_RCC_SDMMC_CLKSOURCE RCC_CCIPR1_ICLKSEL /*!< SDMMC1/2 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
* @{
*/
#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR2_RNGSEL /*!< RNG Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
* @{
*/
#define LL_RCC_USB_CLKSOURCE RCC_CCIPR1_ICLKSEL /*!< USB Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_ADCDAC Peripheral ADCDAC get clock source
* @{
*/
#define LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR3_ADCDACSEL /*!< ADCDACs Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MDF1 Peripheral MDF1 get clock source
* @{
*/
#define LL_RCC_MDF1_CLKSOURCE RCC_CCIPR2_MDF1SEL /* MDF1 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_DAC1 Peripheral DAC1 get clock source
* @{
*/
#define LL_RCC_DAC1_CLKSOURCE RCC_CCIPR3_DAC1SEL /* DAC1 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_ADF1 Peripheral ADF1 get clock source
* @{
*/
#define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR3_ADF1SEL /*!< ADF1 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get kernel clock source
* @{
*/
#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR1_FDCANSEL /*!< FDCAN Kernel Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
* @{
*/
#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OCTOSPISEL /*!< OctoSPI Clock source selection */
/**
* @}
*/
#if defined (HSPI1)
/** @defgroup RCC_LL_EC_HSPI Peripheral HSPI get clock source
* @{
*/
#define LL_RCC_HSPI_CLKSOURCE RCC_CCIPR2_HSPISEL /*!< HSPI Clock source selection */
/**
* @}
*/
#endif /* HSPI */
/** @defgroup RCC_LL_EC_SAES Peripheral SAES get clock source
* @{
*/
#define LL_RCC_SAES_CLKSOURCE RCC_CCIPR2_SAESSEL /*!< SAES Clock source selection */
/**
* @}
*/
#if defined(DSI)
/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
* @{
*/
#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSIHOSTSEL
/**
* @}
*/
#endif /* DSI */
#if defined(LTDC)
/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
* @{
*/
#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_LTDCSEL
/**
* @}
*/
#endif /* LTDC */
#if defined (RCC_CCIPR2_USBPHYCSEL)
/** @defgroup RCC_LL_EC_USBPHY Peripheral USBPHY get clock source
* @{
*/
#define LL_RCC_USBPHY_CLKSOURCE RCC_CCIPR2_USBPHYCSEL
/**
* @}
*/
#endif /* RCC_CCIPR2_USBPHYCSEL */
/** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source
* @{
*/
#define LL_RCC_PLL1SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL1 entry clock source */
#define LL_RCC_PLL1SOURCE_MSIS RCC_PLL1CFGR_PLL1SRC_0 /*!< MSIS clock selected as main PLL1 entry clock source */
#define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 /*!< HSI clock selected as main PLL1 entry clock source */
#define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as main PLL1 entry clock source */
#define LL_RCC_PLLSOURCE_NONE LL_RCC_PLL1SOURCE_NONE /*!< alias define for compatibility with legacy code */
#define LL_RCC_PLLSOURCE_MSIS LL_RCC_PLL1SOURCE_MSIS /*!< alias define for compatibility with legacy code */
#define LL_RCC_PLLSOURCE_HSI LL_RCC_PLL1SOURCE_HSI /*!< alias define for compatibility with legacy code */
#define LL_RCC_PLLSOURCE_HSE LL_RCC_PLL1SOURCE_HSE /*!< alias define for compatibility with legacy code */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges
* @{
*/
#define LL_RCC_PLLINPUTRANGE_4_8 0x00000002U /*!< VCO input range: 4 to 8 MHz */
#define LL_RCC_PLLINPUTRANGE_8_16 0x00000003U /*!< VCO input range: 8 to 16 MHz */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLL2SOURCE PLL2 entry clock source
* @{
*/
#define LL_RCC_PLL2SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL2 entry clock source */
#define LL_RCC_PLL2SOURCE_MSIS RCC_PLL2CFGR_PLL2SRC_0 /*!< MSIS clock selected as main PLL2 entry clock source */
#define LL_RCC_PLL2SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_1 /*!< HSI clock selected as main PLL2 entry clock source */
#define LL_RCC_PLL2SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) /*!< HSE clock selected as main PLL2 entry clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLL3SOURCE PLL3 entry clock source
* @{
*/
#define LL_RCC_PLL3SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL3 entry clock source */
#define LL_RCC_PLL3SOURCE_MSIS RCC_PLL3CFGR_PLL3SRC_0 /*!< MSIS clock selected as main PLL3 entry clock source */
#define LL_RCC_PLL3SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_1 /*!< HSI clock selected as main PLL3 entry clock source */
#define LL_RCC_PLL3SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) /*!< HSE clock selected as main PLL3 entry clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
* @{
*/
#define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */
#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSISRANGE */
/**
* @}
*/
/** @defgroup RCC_LL_EF_Security_Services Security Services
* @note Only available when system implements security (TZEN=1)
* @{
*/
#define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */
#define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */
#define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration security */
#define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */
#define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration security */
#define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */
#define LL_RCC_MSI_SEC RCC_SECCFGR_MSISEC /*!< MSI clock configuration security */
#define LL_RCC_MSI_NSEC 0U /*!< MSI clock configuration secure/non-secure access */
#define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration security */
#define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */
#define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration security */
#define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */
#define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration security */
#define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */
#define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration security */
#define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */
#define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< PLL1 clock configuration security */
#define LL_RCC_PLL1_NSEC 0U /*!< main PLL1 clock configuration secure/non-secure access */
#define LL_RCC_PLL2_SEC RCC_SECCFGR_PLL2SEC /*!< PLL2 clock configuration security */
#define LL_RCC_PLL2_NSEC 0U /*!< main PLL2 clock configuration secure/non-secure access */
#define LL_RCC_PLL3_SEC RCC_SECCFGR_PLL3SEC /*!< PLL3 clock configuration security */
#define LL_RCC_PLL3_NSEC 0U /*!< main PLL3 clock configuration secure/non-secure access */
#define LL_RCC_CLK48M_SEC RCC_SECCFGR_CLK48MSEC /*!< 48MHz clock source selection security */
#define LL_RCC_CLK48M_NSEC 0U /*!< 48MHz clock source selection secure/non-secure access */
#define LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration security */
#define LL_RCC_HSI48_NSEC 0U /*!< HSI48 clock configuration secure/non-secure access */
#define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag security */
#define LL_RCC_RESET_FLAGS_NSEC 0U
#define LL_RCC_PLL_SEC LL_RCC_PLL1_NSEC /*!< alias define for compatibility with legacy code */
#define LL_RCC_PLL_NSEC LL_RCC_PLL1_NSEC /*!< alias define for compatibility with legacy code */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
* @{
*/
/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in RCC register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
/**
* @brief Read a value in RCC register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
/**
* @}
*/
/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
* @{
*/
/**
* @brief Helper macro to calculate the PLL1CLK frequency on system domain
* @note ex: @ref __LL_RCC_CALC_PLL1CLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
* @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetR ());
* @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI)
* @param __PLL1M__ parameter can be a value between 1 and 16
* @param __PLL1N__ parameter can be a value between 4 and 512
* @param __PLL1R__ parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed)
* @retval PLL1 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLL1CLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) ((((__INPUTFREQ__) /(__PLL1M__)) * \
(__PLL1N__)) / (__PLL1R__))
#define __LL_RCC_CALC_PLLCLK_FREQ __LL_RCC_CALC_PLL1CLK_FREQ /*!< alias for compatibility with legacy code */
/**
* @brief Helper macro to calculate the PLL1CLK frequency used on SAI domain
* @note ex: @ref __LL_RCC_CALC_PLL1CLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
* @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ());
* @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI)
* @param __PLL1M__ parameter can be a value between 1 and 16
* @param __PLL1N__ parameter can be a value between 4 and 512
* @param __PLL1P__ parameter can be a value between 1 and 128
* @retval PLL1 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLL1CLK_SAI_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) ((((__INPUTFREQ__) \
/(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__))
#define __LL_RCC_CALC_PLLCLK_SAI_FREQ __LL_RCC_CALC_PLL1CLK_SAI_FREQ /*!< alias for compatibility with legacy code */
/**
* @brief Helper macro to calculate the PLL1CLK frequency used on 48M domain
* @note ex: @ref __LL_RCC_CALC_PLL1CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (),
* @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ());
* @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI)
* @param __PLL1M__ parameter can be a value between 1 and 16
* @param __PLL1N__ parameter can be a value between 4 and 512
* @param __PLL1Q__ parameter can be a value between 1 and 128
* @retval PLL clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLL1CLK_48M_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) ((((__INPUTFREQ__) \
/(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__))
#define __LL_RCC_CALC_PLLCLK_48M_FREQ __LL_RCC_CALC_PLL1CLK_48M_FREQ /*!< alias for compatibility with legacy code */
/**
* @brief Helper macro to calculate the PLL2 frequency used for SAI domain
* @note ex: @ref __LL_RCC_CALC_PLL2CLK_SAI_FREQ (HSE_ALUE,@ref LL_RCC_PLL2_GetDivider (),
* @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetP ());
* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
* @param __PLL2M__ parameter can be a value between 1 and 16
* @param __PLL2N__ parameter can be a value between 4 and 512
* @param __PLL2P__ parameter can be a value between 1 and 128
* @retval PLL2 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLL2CLK_SAI_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2P__) ((((__INPUTFREQ__) \
/(__PLL2M__)) * (__PLL2N__)) / (__PLL2P__))
/**
* @brief Helper macro to calculate the PLL2 frequency used on 48M domain
* @note ex: @ref __LL_RCC_CALC_PLL2CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetDivider (),
* @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetQ ());
* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
* @param __PLL2M__ parameter can be a value between 1 and 16
* @param __PLL2N__ parameter can be a value between 4 and 512
* @param __PLL2Q__ parameter can be a value between 1 and 128
* @retval PLL2 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLL2CLK_48M_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2Q__) ((((__INPUTFREQ__) \
/(__PLL2M__)) * (__PLL2N__)) / (__PLL2Q__))
/**
* @brief Helper macro to calculate the PLL2 frequency used on ADC domain
* @note ex: @ref __LL_RCC_CALC_PLL2CLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetDivider (),
* @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetR ());
* @param __INPUTFREQ__ PLL2 Input frequency (based on MSI/HSE/HSI)
* @param __PLL2M__ parameter can be a value between 1 and 16
* @param __PLL2N__ parameter can be a value between 4 and 512
* @param __PLL2R__ parameter can be a value between 1 and 128
* @retval PLL2 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLL2CLK_ADC_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2R__) ((((__INPUTFREQ__) \
/(__PLL2M__)) * (__PLL2N__)) / (__PLL2R__))
/**
* @brief Helper macro to calculate the PLL3 frequency used for SAI domain
* @note ex: @ref __LL_RCC_CALC_PLL3CLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (),
* @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetP ());
* @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI)
* @param __PLL3M__ parameter can be a value between 1 and 16
* @param __PLL3N__ parameter can be a value between 4 and 512
* @param __PLL3P__ parameter can be a value between 1 and 128
* @retval PLL3 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLL3CLK_SAI_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3P__)((((__INPUTFREQ__) \
/(__PLL3M__)) * (__PLL3N__)) / (__PLL3P__))
/**
* @brief Helper macro to calculate the PLL2 frequency used on 48M domain
* @note ex: @ref __LL_RCC_CALC_PLL3CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (),
* @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ());
* @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI)
* @param __PLL3M__ parameter can be a value between 1 and 16
* @param __PLL3N__ parameter can be a value between 4 and 512
* @param __PLL3Q__ parameter can be a value between 1 and 128
* @retval PLL3 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLL3CLK_48M_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3Q__) ((((__INPUTFREQ__) \
/(__PLL3M__)) * (__PLL3N__)) / (__PLL3Q__))
#if defined(HSPI1) || defined(LTDC)
/**
* @brief Helper macro to calculate the PLL3 frequency used on HSPI domain
* @note ex: @ref __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (),
* @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ());
* @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI)
* @param __PLL3M__ parameter can be a value between 1 and 16
* @param __PLL3N__ parameter can be a value between 4 and 512
* @param __PLL3R__ parameter can be a value between 1 and 128
* @retval PLL3 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3R__) ((((__INPUTFREQ__) \
/(__PLL3M__)) * (__PLL3N__)) / (__PLL3R__))
/* Legacy define */
#define __LL_RCC_CALC_PLL3CLK_HSPI_FREQ __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ
#endif /* HSPI1 || LTDC */
/**
* @brief Helper macro to calculate the HCLK frequency
* @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
* @param __AHBPRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_RCC_SYSCLK_DIV_1
* @arg @ref LL_RCC_SYSCLK_DIV_2
* @arg @ref LL_RCC_SYSCLK_DIV_4
* @arg @ref LL_RCC_SYSCLK_DIV_8
* @arg @ref LL_RCC_SYSCLK_DIV_16
* @arg @ref LL_RCC_SYSCLK_DIV_64
* @arg @ref LL_RCC_SYSCLK_DIV_128
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval HCLK clock frequency (in Hz)
*/
#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> \
AHBPrescTable[((__AHBPRESCALER__)& RCC_CFGR2_HPRE) \
>> RCC_CFGR2_HPRE_Pos])
/**
* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
* @param __HCLKFREQ__ HCLK frequency
* @param __APB1PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_RCC_APB1_DIV_1
* @arg @ref LL_RCC_APB1_DIV_2
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval PCLK1 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> \
(APBPrescTable[((__APB1PRESCALER__)& \
RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]))
/**
* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
* @param __HCLKFREQ__ HCLK frequency
* @param __APB2PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_RCC_APB2_DIV_1
* @arg @ref LL_RCC_APB2_DIV_2
* @arg @ref LL_RCC_APB2_DIV_4
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
* @retval PCLK2 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >>\
APBPrescTable[(__APB2PRESCALER__) >> \
RCC_CFGR2_PPRE2_Pos])
/**
* @brief Helper macro to calculate the PCLK3 frequency (ABP3)
* @param __HCLKFREQ__ HCLK frequency
* @param __APB3PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_RCC_APB3_DIV_1
* @arg @ref LL_RCC_APB3_DIV_2
* @arg @ref LL_RCC_APB3_DIV_4
* @arg @ref LL_RCC_APB3_DIV_8
* @arg @ref LL_RCC_APB3_DIV_16
* @retval PCLK3 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> \
APBPrescTable[(__APB3PRESCALER__) >> \
RCC_CFGR3_PPRE3_Pos])
/**
* @brief Helper macro to calculate the MSIS frequency (in Hz)
* @note __MSISSEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
* @note if __MSISSEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
* __MSISRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
* else by LL_RCC_MSI_GetRange()
* ex: __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
* (LL_RCC_MSI_IsEnabledRangeSelect()?
* LL_RCC_MSI_GetRange():
* LL_RCC_MSI_GetRangeAfterStandby()))
* @param __MSISSEL__ This parameter can be one of the following values:
* @arg @ref LL_RCC_MSIRANGESEL_STANDBY
* @arg @ref LL_RCC_MSIRANGESEL_RUN
* @param __MSISRANGE__ This parameter can be one of the following values:
* @arg @ref LL_RCC_MSISRANGE_0
* @arg @ref LL_RCC_MSISRANGE_1
* @arg @ref LL_RCC_MSISRANGE_2
* @arg @ref LL_RCC_MSISRANGE_3
* @arg @ref LL_RCC_MSISRANGE_4
* @arg @ref LL_RCC_MSISRANGE_5
* @arg @ref LL_RCC_MSISRANGE_6
* @arg @ref LL_RCC_MSISRANGE_7
* @arg @ref LL_RCC_MSISRANGE_8
* @arg @ref LL_RCC_MSISRANGE_9
* @arg @ref LL_RCC_MSISRANGE_10
* @arg @ref LL_RCC_MSISRANGE_11
* @arg @ref LL_RCC_MSISRANGE_12
* @arg @ref LL_RCC_MSISRANGE_13
* @arg @ref LL_RCC_MSISRANGE_14
* @arg @ref LL_RCC_MSISRANGE_15
* @retval MSI clock frequency (in Hz)
*/
#define __LL_RCC_CALC_MSIS_FREQ(__MSISSEL__, __MSISRANGE__) (((__MSISSEL__) == LL_RCC_MSIRANGESEL_RUN) ? \
(MSIRangeTable[((__MSISRANGE__) >> 28U) & 0x0FU]) : \
(MSIRangeTable[((__MSISRANGE__) >> 12U) & 0x0FU]))
/**
* @brief Helper macro to calculate the MSIK frequency (in Hz)
* @note __MSIKSEL__ can be retrieved thanks to function LL_RCC_MSIK_IsEnabledRangeSelect()
* @note if __MSIKSEL__ is equal to LL_RCC_MSIKRANGESEL_STANDBY,
* __MSIKRANGE__can be retrieved by LL_RCC_MSIK_GetRangeAfterStandby()
* else by LL_RCC_MSIK_GetRange()
* ex: __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSIK_IsEnabledRangeSelect(),
* (LL_RCC_MSIK_IsEnabledRangeSelect()?
* LL_RCC_MSIK_GetRange():
* LL_RCC_MSIK_GetRangeAfterStandby()))
* @param __MSIKSEL__ This parameter can be one of the following values:
* @arg @ref LL_RCC_MSIRANGESEL_STANDBY
* @arg @ref LL_RCC_MSIRANGESEL_RUN
* @param __MSIKRANGE__ This parameter can be one of the following values:
* @arg @ref LL_RCC_MSIKRANGE_0
* @arg @ref LL_RCC_MSIKRANGE_1
* @arg @ref LL_RCC_MSIKRANGE_2
* @arg @ref LL_RCC_MSIKRANGE_3
* @arg @ref LL_RCC_MSIKRANGE_4
* @arg @ref LL_RCC_MSIKRANGE_5
* @arg @ref LL_RCC_MSIKRANGE_6
* @arg @ref LL_RCC_MSIKRANGE_7
* @arg @ref LL_RCC_MSIKRANGE_8
* @arg @ref LL_RCC_MSIKRANGE_9
* @arg @ref LL_RCC_MSIKRANGE_10
* @arg @ref LL_RCC_MSIKRANGE_11
* @arg @ref LL_RCC_MSIKRANGE_12
* @arg @ref LL_RCC_MSIKRANGE_13
* @arg @ref LL_RCC_MSIKRANGE_14
* @arg @ref LL_RCC_MSIKRANGE_15
* @retval MSIK clock frequency (in Hz)
*/
#define __LL_RCC_CALC_MSIK_FREQ(__MSIKSEL__, __MSIKRANGE__) (((__MSIKSEL__) == LL_RCC_MSIRANGESEL_RUN) ? \
(MSIRangeTable[((__MSIKRANGE__) >> 24U) & 0x0FU]) : \
(MSIRangeTable[((__MSIKRANGE__) >> 8U) & 0x0FU]))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
* @{
*/
/** @defgroup RCC_LL_EF_HSE HSE
* @{
*/
/**
* @brief Enable the Clock Security System.
* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
{
SET_BIT(RCC->CR, RCC_CR_CSSON);
}
/**
* @brief Enable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
{
SET_BIT(RCC->CR, RCC_CR_HSEBYP);
}
/**
* @brief Disable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
}
/**
* @brief Enable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_HSEON);
}
/**
* @brief Disable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
}
/**
* @brief Check if HSE oscillator Ready
* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
}
/**
* @brief Set external HSE clock mode
* @note This bit can be written only if the HSE oscillator is disabled
* @rmtoll CR HSEEXT LL_RCC_HSE_SetClockMode
* @param HSEMode This parameter can be one of the following values:
* @arg @ref LL_RCC_HSE_ANALOG_MODE
* @arg @ref LL_RCC_HSE_DIGITAL_MODE
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_SetClockMode(uint32_t HSEMode)
{
MODIFY_REG(RCC->CR, RCC_CR_HSEEXT, HSEMode);
}
/**
* @brief Get External HSE clock mode
* @rmtoll CR HSEEXT LL_RCC_HSE_GetClockMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_HSE_ANALOG_MODE
* @arg @ref LL_RCC_HSE_DIGITAL_MODE
*/
__STATIC_INLINE uint32_t LL_RCC_HSE_GetClockMode(void)
{
return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSEEXT));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_HSI HSI
* @{
*/
/**
* @brief Enable HSI even in stop mode
* @note HSI oscillator is forced ON even in Stop mode
* @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
{
SET_BIT(RCC->CR, RCC_CR_HSIKERON);
}
/**
* @brief Disable HSI in stop mode
* @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
}
/**
* @brief Check if HSI is enabled in stop mode
* @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL);
}
/**
* @brief Enable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_HSION);
}
/**
* @brief Disable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSION);
}
/**
* @brief Check if HSI clock is ready
* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
}
/**
* @brief Get HSI Calibration value
* @note When HSITRIM is written, HSICAL is updated with the sum of
* HSITRIM and the factory trim value
* @rmtoll ICSCR3 HSICAL LL_RCC_HSI_GetCalibration
* @retval Between Min_Data = 0 and Max_Data = 127
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
{
return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSICAL) >> RCC_ICSCR3_HSICAL_Pos);
}
/**
* @brief Set HSI Calibration trimming
* @note user-programmable trimming value that is added to the HSICAL
* @note Default value is 64, which, when added to the HSICAL value,
* should trim the HSI to 16 MHz +/- 1 %
* @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_SetCalibTrimming
* @param Value Between Min_Data = 0 and Max_Data = 127
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
{
MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, Value << RCC_ICSCR3_HSITRIM_Pos);
}
/**
* @brief Get HSI Calibration trimming
* @rmtoll ICSC3R HSITRIM LL_RCC_HSI_GetCalibTrimming
* @retval Between Min_Data = 0 and Max_Data = 127
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
{
return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_HSI48 HSI48
* @{
*/
/**
* @brief Enable HSI48
* @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_HSI48ON);
}
/**
* @brief Disable HSI48
* @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
}
/**
* @brief Check if HSI48 oscillator Ready
* @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL);
}
/**
* @brief Get HSI48 Calibration value
* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
* @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
*/
__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
{
return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_LSE LSE
* @{
*/
/**
* @brief Enable Low Speed External (LSE) crystal.
* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
}
/**
* @brief Disable Low Speed External (LSE) crystal.
* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_Disable(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
}
/**
* @brief Enable external clock source (LSE bypass).
* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
/**
* @brief Disable external clock source (LSE bypass).
* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
/**
* @brief Set LSE oscillator drive capability
* @note The oscillator is in Xtal mode when it is not in bypass mode.
* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
* @param LSEDrive This parameter can be one of the following values:
* @arg @ref LL_RCC_LSEDRIVE_LOW
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
* @arg @ref LL_RCC_LSEDRIVE_HIGH
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
{
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
}
/**
* @brief Get LSE oscillator drive capability
* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_LSEDRIVE_LOW
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
* @arg @ref LL_RCC_LSEDRIVE_HIGH
*/
__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
{
return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
}
/**
* @brief Enable Clock security system on LSE.
* @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
}
/**
* @brief Disable Clock security system on LSE.
* @note Clock security system can be disabled only after a LSE
* failure detection. In that case it MUST be disabled by software.
* @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
}
/**
* @brief Check if LSE oscillator Ready
* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
{
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
}
/**
* @brief Enable LSE oscillator propagation for system clock
* @rmtoll BDCR LSESYSEN LL_RCC_LSE_EnablePropagation
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
}
/**
* @brief Check if LSESYS oscillator Ready
* @rmtoll BDCR LSESYSRDY LL_RCC_LSESYS_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSESYS_IsReady(void)
{
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL);
}
/**
* @brief Disable LSE oscillator propagation for system clock
* @rmtoll BDCR LSESYSEN LL_RCC_LSE_DisablePropagation
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
}
/**
* @brief Check if LSE oscillator propagation for system clock Ready
* @rmtoll BDCR LSESYSRDY LL_RCC_LSE_IsPropagationReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void)
{
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL);
}
/**
* @brief Check if CSS on LSE failure Detection
* @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
{
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_LSI LSI
* @{
*/
/**
* @brief Enable LSI Oscillator
* @rmtoll BDCR LSION LL_RCC_LSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSI_Enable(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSION);
}
/**
* @brief Disable LSI Oscillator
* @rmtoll BDCR LSION LL_RCC_LSI_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSI_Disable(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION);
}
/**
* @brief Check if LSI is Ready
* @rmtoll BDCR LSIRDY LL_RCC_LSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
{
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) ? 1UL : 0UL);
}
/**
* @brief Set LSI prescaler
* @rmtoll BDCR LSIPREDIV LL_RCC_LSI_SetPrescaler
* @param LSIPrescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_LSI_DIV_1
* @arg @ref LL_RCC_LSI_DIV_128
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSI_SetPrescaler(uint32_t LSIPrescaler)
{
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSIPREDIV, LSIPrescaler);
}
/**
* @brief Get LSI prescaler
* @rmtoll BDCR LSIPREDIV LL_RCC_LSI_GetPrescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_LSI_DIV_1
* @arg @ref LL_RCC_LSI_DIV_128
*/
__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrescaler(void)
{
return (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_MSIK MSIK
* @{
*/
/**
* @brief Enable MSIK oscillator
* @rmtoll CR MSIKON LL_RCC_MSIK_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSIK_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_MSIKON);
}
/**
* @brief Disable MSIK oscillator
* @rmtoll CR MSIKON LL_RCC_MSIK_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSIK_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_MSIKON);
}
/**
* @brief Check if MSIK oscillator Ready
* @rmtoll CR MSIKRDY LL_RCC_MSIK_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_MSIK_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_MSIKRDY) == RCC_CR_MSIKRDY) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_SHSI SHSI
* @{
*/
/**
* @brief Enable SHSI oscillator
* @rmtoll CR SHSION LL_RCC_SHSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_SHSI_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_SHSION);
}
/**
* @brief Disable SHSI oscillator
* @rmtoll CR SHSION LL_RCC_SHSI_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_SHSI_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_SHSION);
}
/**
* @brief Check if SHSI oscillator Ready
* @rmtoll CR SHSIRDY LL_RCC_SHSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_SHSI_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_SHSIRDY) == RCC_CR_SHSIRDY) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup RCC_LL_EF_MSI MSI
* @{
*/
/**
* @brief Enable MSIS oscillator
* @rmtoll CR MSISON LL_RCC_MSIS_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSIS_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_MSISON);
}
#define LL_RCC_MSI_Enable LL_RCC_MSIS_Enable /*!< alias define for compatibility with legacy code */
/**
* @brief Disable MSIS oscillator
* @rmtoll CR MSISON LL_RCC_MSIS_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSIS_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_MSISON);
}
#define LL_RCC_MSI_Disable LL_RCC_MSIS_Disable /*!< alias define for compatibility with legacy code */
/**
* @brief Check if MSIS oscillator Ready
* @rmtoll CR MSISRDY LL_RCC_MSIS_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_MSIS_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) == RCC_CR_MSISRDY) ? 1UL : 0UL);
}
#define LL_RCC_MSI_IsReady LL_RCC_MSIS_IsReady /*!< alias define for compatibility with legacy code */
/**
* @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
* @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
* and ready (LSERDY set by hardware)
* @note hardware protection to avoid enabling MSIPLLEN if LSE is not
* ready
* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
{
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
}
/**
* @brief Disable MSI-PLL mode
* @note cleared by hardware when LSE is disabled (LSEON = 0) or when
* the Clock Security System on LSE detects a LSE failure
* @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
}
/**
* @brief Set clock source in PLL mode
* @rmtoll CR MSIPLLSEL LL_RCC_SetMSIPLLMode
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLMODE_MSIS
* @arg @ref LL_RCC_PLLMODE_MSIK
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetMSIPLLMode(uint32_t Source)
{
MODIFY_REG(RCC->CR, RCC_CR_MSIPLLSEL, Source);
}
/**
* @brief Get Clock source in PLL Mode
* @rmtoll CR MSIPLLSEL LL_RCC_GetMSIPLLMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLMODE_MSIS
* @arg @ref LL_RCC_PLLMODE_MSIK
*/
__STATIC_INLINE uint32_t LL_RCC_GetMSIPLLMode(void)
{
return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIPLLSEL));
}
/**
* @brief Enable MSI fast mode
* @rmtoll CR MSIPLLFAST LL_RCC_Enable_MSIPLLFAST
* @note This bit is used only if PLL mode is selected.
*/
__STATIC_INLINE void LL_RCC_Enable_MSIPLLFAST(void)
{
SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
}
/**
* @brief Disable MSI fast mode
* @rmtoll CR MSIPLLFAST LL_RCC_Disable_MSIPLLFAST
* @note This bit is used only if PLL mode is selected.
*/
__STATIC_INLINE void LL_RCC_Disable_MSIPLLFAST(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
}
/**
* @brief Check if MSI PLL Fast Mode is enable
* @rmtoll CR MSIPLLFAST LL_RCC_MSI_IsEnabledMSIPLLFAST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledMSIPLLFAST(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_MSIPLLFAST) == RCC_CR_MSIPLLFAST) ? 1UL : 0UL);
}
/**
* @brief Set MSI Bias mode
* @rmtoll ICSCR1 MSIBIAS LL_RCC_MSI_SetMSIBiasMode
* @param BiasMode This parameter can be one of the following values:
* @arg @ref LL_RCC_MSIBIASMODE_CONTINUOUS
* @arg @ref LL_RCC_MSIBIASMODE_SAMPLING
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_SetMSIBiasMode(uint32_t BiasMode)
{
MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS, BiasMode);
}
/**
* @brief Get MSI Bias mode
* @rmtoll ICSCR1 MSIBIAS LL_RCC_MSI_GetMSIBiasMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_MSIBIASMODE_CONTINUOUS
* @arg @ref LL_RCC_MSIBIASMODE_SAMPLING
*/
__STATIC_INLINE uint32_t LL_RCC_MSI_GetMSIBiasMode(void)
{
return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS));
}
/**
* @brief Enable MSIK even in stop mode
* @note MSIK oscillator is forced ON even in Stop mode
* @rmtoll CR MSIKERON LL_RCC_MSIK_EnableInStopMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSIK_EnableInStopMode(void)
{
SET_BIT(RCC->CR, RCC_CR_MSIKERON);
}
/**
* @brief Disable MSIK in stop mode
* @rmtoll CR MSIKERON LL_RCC_MSIK_DisableInStopMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSIK_DisableInStopMode(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON);
}
/**
* @brief Check if MSIK is enabled in stop mode
* @rmtoll CR MSIKERON LL_RCC_MSIK_IsEnabledInStopMode
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_MSIK_IsEnabledInStopMode(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_MSIKERON) == RCC_CR_MSIKERON) ? 1UL : 0UL);
}
/**
* @brief Enable MSI clock range selection with MSIRANGE register
* @note Write 0 has no effect. After a standby or a reset
* MSIRGSEL is at 0 and the MSI range value is provided by
* MSISRANGE
* @rmtoll ICSCR1 MSIRGSEL LL_RCC_MSI_EnableRangeSelection
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
{
SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL);
}
/**
* @brief Check if MSI clock range is selected with MSIRANGE register
* @rmtoll ICSCR1 MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
{
return ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == RCC_ICSCR1_MSIRGSEL) ? 1UL : 0UL);
}
/**
* @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
* @rmtoll ICSCR1 MSISRANGE LL_RCC_MSIS_SetRange
* @param Range This parameter can be one of the following values:
* @arg @ref LL_RCC_MSISRANGE_0
* @arg @ref LL_RCC_MSISRANGE_1
* @arg @ref LL_RCC_MSISRANGE_2
* @arg @ref LL_RCC_MSISRANGE_3
* @arg @ref LL_RCC_MSISRANGE_4
* @arg @ref LL_RCC_MSISRANGE_5
* @arg @ref LL_RCC_MSISRANGE_6
* @arg @ref LL_RCC_MSISRANGE_7
* @arg @ref LL_RCC_MSISRANGE_8
* @arg @ref LL_RCC_MSISRANGE_9
* @arg @ref LL_RCC_MSISRANGE_10
* @arg @ref LL_RCC_MSISRANGE_11
* @arg @ref LL_RCC_MSISRANGE_12
* @arg @ref LL_RCC_MSISRANGE_13
* @arg @ref LL_RCC_MSISRANGE_14
* @arg @ref LL_RCC_MSISRANGE_15
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSIS_SetRange(uint32_t Range)
{
MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, Range);
}
#define LL_RCC_MSI_SetRange LL_RCC_MSIS_SetRange /*!< alias define for compatibility with legacy code */
/**
* @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
* @rmtoll ICSCR1 MSISRANGE LL_RCC_MSIS_GetRange
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_MSISRANGE_0
* @arg @ref LL_RCC_MSISRANGE_1
* @arg @ref LL_RCC_MSISRANGE_2
* @arg @ref LL_RCC_MSISRANGE_3
* @arg @ref LL_RCC_MSISRANGE_4
* @arg @ref LL_RCC_MSISRANGE_5
* @arg @ref LL_RCC_MSISRANGE_6
* @arg @ref LL_RCC_MSISRANGE_7
* @arg @ref LL_RCC_MSISRANGE_8
* @arg @ref LL_RCC_MSISRANGE_9
* @arg @ref LL_RCC_MSISRANGE_10
* @arg @ref LL_RCC_MSISRANGE_11
* @arg @ref LL_RCC_MSISRANGE_12
* @arg @ref LL_RCC_MSISRANGE_13
* @arg @ref LL_RCC_MSISRANGE_14
* @arg @ref LL_RCC_MSISRANGE_15
*/
__STATIC_INLINE uint32_t LL_RCC_MSIS_GetRange(void)
{
return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE));
}
#define LL_RCC_MSI_GetRange LL_RCC_MSIS_GetRange /*!< alias define for compatibility with legacy code */
/**
* @brief Configure MSIS range used after standby
* @rmtoll CSR MSISSRANGE LL_RCC_MSIS_SetRangeAfterStandby
* @param Range This parameter can be one of the following values:
* @arg @ref LL_RCC_MSISRANGE_4
* @arg @ref LL_RCC_MSISRANGE_5
* @arg @ref LL_RCC_MSISRANGE_6
* @arg @ref LL_RCC_MSISRANGE_7
* @arg @ref LL_RCC_MSISRANGE_8
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSIS_SetRangeAfterStandby(uint32_t Range)
{
MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE, Range);
}
#define LL_RCC_MSI_SetRangeAfterStandby LL_RCC_MSIS_SetRangeAfterStandby /*!< alias define for compatibility with legacy code */
/**
* @brief Get MSIS range used after standby
* @rmtoll CSR MSISSRANGE LL_RCC_MSIS_GetRangeAfterStandby
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_MSISSRANGE_4
* @arg @ref LL_RCC_MSISSRANGE_5
* @arg @ref LL_RCC_MSISSRANGE_6
* @arg @ref LL_RCC_MSISSRANGE_7
* @arg @ref LL_RCC_MSISSRANGE_8
*/
__STATIC_INLINE uint32_t LL_RCC_MSIS_GetRangeAfterStandby(void)
{
return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE));
}
#define LL_RCC_MSI_GetRangeAfterStandby LL_RCC_MSIS_GetRangeAfterStandby /*!< alias define for compatibility with legacy code */
/**
* @brief Set MSI OSCILLATORx Calibration trimming
* @note user-programmable trimming value that is added to the MSICALx
* @rmtoll ICSCR2 MSITRIMx LL_RCC_MSI_SetCalibTrimming
* @param Value Between Min_Data = 0 and Max_Data = 31
* @param Oscillator This parameter can be one of the following values:
* @arg @ref LL_RCC_MSI_OSCILLATOR_0
* @arg @ref LL_RCC_MSI_OSCILLATOR_1
* @arg @ref LL_RCC_MSI_OSCILLATOR_2
* @arg @ref LL_RCC_MSI_OSCILLATOR_3
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value, uint32_t Oscillator)
{
MODIFY_REG(RCC->ICSCR2, (RCC_ICSCR2_MSITRIM0 >> Oscillator), Value << (RCC_ICSCR2_MSITRIM0_Pos - Oscillator));
}
/**
* @brief Get MSI OSCILLATORx Calibration trimming
* @rmtoll ICSCR2 MSITRIMx LL_RCC_MSI_GetCalibTrimming
* @retval Between 0 and 31
* @param Oscillator This parameter can be one of the following values:
* @arg @ref LL_RCC_MSI_OSCILLATOR_0
* @arg @ref LL_RCC_MSI_OSCILLATOR_1
* @arg @ref LL_RCC_MSI_OSCILLATOR_2
* @arg @ref LL_RCC_MSI_OSCILLATOR_3
*/
__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(uint32_t Oscillator)
{
return (uint32_t)(READ_BIT(RCC->ICSCR2,
(RCC_ICSCR2_MSITRIM0 >> Oscillator)) >> (RCC_ICSCR2_MSITRIM0_Pos - Oscillator));
}
/**
* @brief Get MSI OSCILLATORx Calibration value
* @note When MSITRIMx is written, MSICALx is updated with the sum of
* MSITRIMx and the factory trim value
* @rmtoll ICSCR1 MSICALx LL_RCC_MSI_GetCalibration
* @param Oscillator This parameter can be one of the following values:
* @arg @ref LL_RCC_MSI_OSCILLATOR_0
* @arg @ref LL_RCC_MSI_OSCILLATOR_1
* @arg @ref LL_RCC_MSI_OSCILLATOR_2
* @arg @ref LL_RCC_MSI_OSCILLATOR_3
* @retval Between Min_Data = 0 and Max_Data = 31
*/
__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(uint32_t Oscillator)
{
return (uint32_t)(READ_BIT(RCC->ICSCR1, (RCC_ICSCR1_MSICAL0 >> Oscillator)) >> (RCC_ICSCR1_MSICAL0_Pos - Oscillator));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_MSIK MSIK
* @{
*/
/**
* @brief Configure the Internal Multi Speed oscillator (MSIK) clock range in run mode.
* @rmtoll ICSCR1 MSIKRANGE LL_RCC_MSIK_SetRange
* @param Range This parameter can be one of the following values:
* @arg @ref LL_RCC_MSIKRANGE_0
* @arg @ref LL_RCC_MSIKRANGE_1
* @arg @ref LL_RCC_MSIKRANGE_2
* @arg @ref LL_RCC_MSIKRANGE_3
* @arg @ref LL_RCC_MSIKRANGE_4
* @arg @ref LL_RCC_MSIKRANGE_5
* @arg @ref LL_RCC_MSIKRANGE_6
* @arg @ref LL_RCC_MSIKRANGE_7
* @arg @ref LL_RCC_MSIKRANGE_8
* @arg @ref LL_RCC_MSIKRANGE_9
* @arg @ref LL_RCC_MSIKRANGE_10
* @arg @ref LL_RCC_MSIKRANGE_11
* @arg @ref LL_RCC_MSIKRANGE_12
* @arg @ref LL_RCC_MSIKRANGE_13
* @arg @ref LL_RCC_MSIKRANGE_14
* @arg @ref LL_RCC_MSIKRANGE_15
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSIK_SetRange(uint32_t Range)
{
MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, Range);
}
/**
* @brief Get the Internal Multi Speed oscillator (MSIK) clock range in run mode.
* @rmtoll ICSCR1 MSIKRANGE LL_RCC_MSIK_GetRange
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_MSIKRANGE_0
* @arg @ref LL_RCC_MSIKRANGE_1
* @arg @ref LL_RCC_MSIKRANGE_2
* @arg @ref LL_RCC_MSIKRANGE_3
* @arg @ref LL_RCC_MSIKRANGE_4
* @arg @ref LL_RCC_MSIKRANGE_5
* @arg @ref LL_RCC_MSIKRANGE_6
* @arg @ref LL_RCC_MSIKRANGE_7
* @arg @ref LL_RCC_MSIKRANGE_8
* @arg @ref LL_RCC_MSIKRANGE_9
* @arg @ref LL_RCC_MSIKRANGE_10
* @arg @ref LL_RCC_MSIKRANGE_11
* @arg @ref LL_RCC_MSIKRANGE_12
* @arg @ref LL_RCC_MSIKRANGE_13
* @arg @ref LL_RCC_MSIKRANGE_14
* @arg @ref LL_RCC_MSIKRANGE_15
*/
__STATIC_INLINE uint32_t LL_RCC_MSIK_GetRange(void)
{
return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE));
}
/**
* @brief Configure MSIK range used after standby
* @rmtoll CSR MSIKSRANGE LL_RCC_MSIK_SetRangeAfterStandby
* @param Range This parameter can be one of the following values:
* @arg @ref LL_RCC_MSIKSRANGE_4
* @arg @ref LL_RCC_MSIKSRANGE_5
* @arg @ref LL_RCC_MSIKSRANGE_6
* @arg @ref LL_RCC_MSIKSRANGE_7
* @arg @ref LL_RCC_MSIKSRANGE_8
* @retval None
*/
__STATIC_INLINE void LL_RCC_MSIK_SetRangeAfterStandby(uint32_t Range)
{
MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, Range);
}
/**
* @brief Get MSIK range used after standby
* @rmtoll CSR MSIKSRANGE LL_RCC_MSIK_GetRangeAfterStandby
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_MSIKSRANGE_4
* @arg @ref LL_RCC_MSIKSRANGE_5
* @arg @ref LL_RCC_MSIKSRANGE_6
* @arg @ref LL_RCC_MSIKSRANGE_7
* @arg @ref LL_RCC_MSIKSRANGE_8
*/
__STATIC_INLINE uint32_t LL_RCC_MSIK_GetRangeAfterStandby(void)
{
return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_LSCO LSCO
* @{
*/
/**
* @brief Enable Low speed clock
* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
}
/**
* @brief Disable Low speed clock
* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
}
/**
* @brief Configure Low speed clock selection
* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
{
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
}
/**
* @brief Get Low speed clock selection
* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
*/
__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
{
return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_System System
* @{
*/
/**
* @brief Configure the system clock source
* @rmtoll CFGR1 SW LL_RCC_SetSysClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_SYS_CLKSOURCE_MSIS
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source);
}
/**
* @brief Get the system clock source
* @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSIS
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
*/
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS));
}
/**
* @brief Set AHB prescaler
* @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_SYSCLK_DIV_1
* @arg @ref LL_RCC_SYSCLK_DIV_2
* @arg @ref LL_RCC_SYSCLK_DIV_4
* @arg @ref LL_RCC_SYSCLK_DIV_8
* @arg @ref LL_RCC_SYSCLK_DIV_16
* @arg @ref LL_RCC_SYSCLK_DIV_64
* @arg @ref LL_RCC_SYSCLK_DIV_128
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler);
}
/**
* @brief Set Systick clock source
* @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource
* @param SystickSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
* @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
* @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource)
{
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, SystickSource);
}
/**
* @brief Set APB1 prescaler
* @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_APB1_DIV_1
* @arg @ref LL_RCC_APB1_DIV_2
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler);
}
/**
* @brief Set APB2 prescaler
* @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_APB2_DIV_1
* @arg @ref LL_RCC_APB2_DIV_2
* @arg @ref LL_RCC_APB2_DIV_4
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler);
}
/**
* @brief Set APB3 prescaler
* @rmtoll CFGR3 PPRE3 LL_RCC_SetAPB3Prescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_APB3_DIV_1
* @arg @ref LL_RCC_APB3_DIV_2
* @arg @ref LL_RCC_APB3_DIV_4
* @arg @ref LL_RCC_APB3_DIV_8
* @arg @ref LL_RCC_APB3_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, Prescaler);
}
/**
* @brief Get AHB prescaler
* @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SYSCLK_DIV_1
* @arg @ref LL_RCC_SYSCLK_DIV_2
* @arg @ref LL_RCC_SYSCLK_DIV_4
* @arg @ref LL_RCC_SYSCLK_DIV_8
* @arg @ref LL_RCC_SYSCLK_DIV_16
* @arg @ref LL_RCC_SYSCLK_DIV_64
* @arg @ref LL_RCC_SYSCLK_DIV_128
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
*/
__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE));
}
/**
* @brief Get Sysctick clock source
* @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI
* @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE
* @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8
*/
__STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void)
{
return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL));
}
/**
* @brief Get APB1 prescaler
* @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_APB1_DIV_1
* @arg @ref LL_RCC_APB1_DIV_2
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1));
}
/**
* @brief Get APB2 prescaler
* @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_APB2_DIV_1
* @arg @ref LL_RCC_APB2_DIV_2
* @arg @ref LL_RCC_APB2_DIV_4
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2));
}
/**
* @brief Get APB3 prescaler
* @rmtoll CFGR3 PPRE3 LL_RCC_GetAPB2Prescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_APB3_DIV_1
* @arg @ref LL_RCC_APB3_DIV_2
* @arg @ref LL_RCC_APB3_DIV_4
* @arg @ref LL_RCC_APB3_DIV_8
* @arg @ref LL_RCC_APB3_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_PPRE3));
}
/**
* @brief Set Clock After Wake-Up From Stop mode
* @rmtoll CFGR1 STOPWUCK LL_RCC_SetClkAfterWakeFromStop
* @param Clock This parameter can be one of the following values:
* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSIS
* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
{
MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Clock);
}
/**
* @brief Get Clock After Wake-Up From Stop mode
* @rmtoll CFGR1 STOPWUCK LL_RCC_GetClkAfterWakeFromStop
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSIS
* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
*/
__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_MCO MCO
* @{
*/
/**
* @brief Configure MCOx
* @rmtoll CFGR1 MCOSEL LL_RCC_ConfigMCO\n
* CFGR1 MCOPRE LL_RCC_ConfigMCO
* @param MCOxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
* @arg @ref LL_RCC_MCO1SOURCE_MSIS
* @arg @ref LL_RCC_MCO1SOURCE_HSI
* @arg @ref LL_RCC_MCO1SOURCE_HSE
* @arg @ref LL_RCC_MCO1SOURCE_HSI48
* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
* @arg @ref LL_RCC_MCO1SOURCE_LSI
* @arg @ref LL_RCC_MCO1SOURCE_LSE
* @param MCOxPrescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_MCO1_DIV_1
* @arg @ref LL_RCC_MCO1_DIV_2
* @arg @ref LL_RCC_MCO1_DIV_4
* @arg @ref LL_RCC_MCO1_DIV_8
* @arg @ref LL_RCC_MCO1_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
{
MODIFY_REG(RCC->CFGR1, RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE, MCOxSource | MCOxPrescaler);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
* @{
*/
/**
* @brief Configure USARTx clock source
* @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n
* CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n
* CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource
* @param USARTxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
{
__IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTxSource >> 24U));
MODIFY_REG(*reg, 3UL << ((USARTxSource & 0x001F0000U) >> 16U), ((USARTxSource & 0x000000FFU) << \
((USARTxSource & 0x001F0000U) >> 16U)));
}
/**
* @brief Configure UARTx clock source
* @rmtoll CCIPR1 UART4SEL LL_RCC_SetUARTClockSource\n
* CCIPR1 UART5SEL LL_RCC_SetUARTClockSource
* @param UARTxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
{
MODIFY_REG(RCC->CCIPR1, UARTxSource >> 16U, (UARTxSource & 0x0000FFFFU));
}
/**
* @brief Configure LPUARTx clock source
* @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource
* @param LPUARTxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSIK
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
{
MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource);
}
/**
* @brief Configure I2Cx clock source
* @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n
* CCIPR1 I2C2SEL LL_RCC_SetI2CClockSource\n
* CCIPR3 I2C3SEL LL_RCC_SetI2CClockSource\n
* CCIPR1 I2C4SEL LL_RCC_SetI2CClockSource
* @param I2CxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C1_CLKSOURCE_MSIK
* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C2_CLKSOURCE_MSIK
* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3
* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C3_CLKSOURCE_MSIK
* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C4_CLKSOURCE_MSIK
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
{
__IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U));
MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << \
(((I2CxSource & 0x00FF0000U) >> 16U) & \
0x1FU)));
}
/**
* @brief Configure SPIx clock source
* @rmtoll CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n
* CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n
* CCIPR1 SPI2SEL LL_RCC_SetSPIClockSource\n
* CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource
* @param SPIxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
* @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
* @arg @ref LL_RCC_SPI1_CLKSOURCE_MSIK
* @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
* @arg @ref LL_RCC_SPI2_CLKSOURCE_MSIK
* @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK3
* @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
* @arg @ref LL_RCC_SPI3_CLKSOURCE_MSIK
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource)
{
__IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U));
MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << \
(((SPIxSource & 0x00FF0000U) >> 16U) & \
0x1FU)));
}
/**
* @brief Configure LPTIMx clock source
* @rmtoll CCIPR1 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
* CCIPR3 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
* CCIPR3 LPTIM34SEL LL_RCC_SetLPTIMClockSource
* @param LPTIMxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_MSIK
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
* @arg @ref LL_RCC_LPTIM34_CLKSOURCE_MSIK
* @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSI
* @arg @ref LL_RCC_LPTIM34_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
{
__IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U));
MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << \
(((LPTIMxSource & 0x00FF0000U) >> 16U) & \
0x1FU)));
}
/**
* @brief Configure FDCAN kernel clock source
* @rmtoll CCIPR1 FDCANSEL LL_RCC_SetFDCANClockSource
* @param FDCANxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
{
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, FDCANxSource);
}
/**
* @brief Configure SAIx clock source
* @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n
* CCIPR2 SAI2SEL LL_RCC_SetSAIClockSource
* @param SAIxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
* @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1
* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2
* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3
* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
* @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
{
MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
}
/**
* @brief Configure SDMMC1/2 kernel clock source
* @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
* @param SDMMCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK
* @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 "P"
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
}
/**
* @brief Configure SDMMC1/2 clock source
* @rmtoll CCIPR1 ICLKSEL LL_RCC_SetSDMMCClockSource
* @param SDMMCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48
* @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1
* @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL2
* @arg @ref LL_RCC_SDMMC12_CLKSOURCE_MSIK
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
{
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, SDMMCxSource);
}
/**
* @brief Configure RNG clock source
* @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource
* @param RNGxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48_DIV2
* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, RNGxSource);
}
#if defined(RCC_CCIPR2_USBPHYCSEL)
/**
* @brief Configure USBPHY clock source
* @rmtoll CCIPR2 USBPHYCSEL LL_RCC_SetUSBPHYClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE
* @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE_DIV2
* @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1
* @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetUSBPHYClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, Source);
}
#endif /* RCC_CCIPR2_USBPHYCSEL */
/**
* @brief Configure USB clock source
* @rmtoll CCIPR1 ICLKSEL LL_RCC_SetUSBClockSource
* @param USBxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
* @arg @ref LL_RCC_USB_CLKSOURCE_PLL1
* @arg @ref LL_RCC_USB_CLKSOURCE_PLL2
* @arg @ref LL_RCC_USB_CLKSOURCE_MSIK
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
{
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, USBxSource);
}
/**
* @brief Configure ADC clock source
* @rmtoll CCIPR3 ADCDACSEL LL_RCC_SetADCDACClockSource
* @param ADCxDAC1Source This parameter can be one of the following values:
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_MSIK
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetADCDACClockSource(uint32_t ADCxDAC1Source)
{
MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL, ADCxDAC1Source);
}
/**
* @brief Configure DAC1 clock source
* @rmtoll CCIPR3 DAC1SEL LL_RCC_SetDAC1ClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_DAC1_CLKSOURCE_LSE
* @arg @ref LL_RCC_DAC1_CLKSOURCE_LSI
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetDAC1ClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL, Source);
}
/**
* @brief Configure ADF1 clock source
* @rmtoll CCIPR3 ADF1SEL LL_RCC_SetADF1ClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK
* @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1
* @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3
* @arg @ref LL_RCC_ADF1_CLKSOURCE_MSIK
* @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetADF1ClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL, Source);
}
/**
* @brief Configure MDF1 clock source
* @rmtoll CCIPR3 MDF1SEL LL_RCC_SetMDF1ClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK
* @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1
* @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3
* @arg @ref LL_RCC_MDF1_CLKSOURCE_MSIK
* @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetMDF1ClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL, Source);
}
/**
* @brief Configure OCTOSPI kernel clock source
* @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSIK
* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL1
* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL2
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, Source);
}
#if defined (HSPI1)
/**
* @brief Configure HSPI kernel clock source
* @rmtoll CCIPR2 HSPISEL LL_RCC_SetHSPIClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_HSPI_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL1
* @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL2
* @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL3
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetHSPIClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, Source);
}
#endif /* HSPI1 */
/**
* @brief Configure SAES clock source
* @rmtoll CCIPR2 SAESSEL LL_RCC_SetSAESClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI
* @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI_DIV2
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSAESClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, Source);
}
#if defined(DSI)
/**
* @brief Configure DSIx clock source
* @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL3
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, Source);
}
#endif /* DSI */
#if defined(LTDC)
/**
* @brief Configure LTDCx clock source
* @rmtoll CCIPR2 LTDCSEL LL_RCC_SetLTDCClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2
* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, Source);
}
#endif /* LTDC */
/**
* @brief Get USARTx clock source
* @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n
* CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n
* CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource
* @param USARTx This parameter can be one of the following values:
* @arg @ref LL_RCC_USART1_CLKSOURCE
* @arg @ref LL_RCC_USART2_CLKSOURCE
* @arg @ref LL_RCC_USART3_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
*/
__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
{
__IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTx >> 24U));
return (uint32_t)((READ_BIT(*reg, 3UL << ((USARTx & 0x001F0000U) >> 16U)) >> \
((USARTx & 0x001F0000U) >> 16U)) | (USARTx & 0xFFFF0000U));
}
/**
* @brief Get UARTx clock source
* @rmtoll CCIPR1 UART4SEL LL_RCC_GetUARTClockSource\n
* CCIPR1 UART5SEL LL_RCC_GetUARTClockSource
* @param UARTx This parameter can be one of the following values:
* @arg @ref LL_RCC_UART4_CLKSOURCE
* @arg @ref LL_RCC_UART5_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
*/
__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR1, UARTx) | (UARTx << 16U));
}
/**
* @brief Get LPUARTx clock source
* @rmtoll CCIPR1 LPUART1SEL LL_RCC_GetLPUARTClockSource
* @param LPUARTx This parameter can be one of the following values:
* @arg @ref LL_RCC_LPUART1_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
*/
__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx));
}
/**
* @brief Get I2Cx clock source
* @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n
* CCIPR1 I2C2SEL LL_RCC_GetI2CClockSource\n
* CCIPR3 I2C3SEL LL_RCC_GetI2CClockSource\n
* CCIPR1 I2C4SEL LL_RCC_GetI2CClockSource
* @param I2Cx This parameter can be one of the following values:
* @arg @ref LL_RCC_I2C1_CLKSOURCE
* @arg @ref LL_RCC_I2C2_CLKSOURCE
* @arg @ref LL_RCC_I2C3_CLKSOURCE
* @arg @ref LL_RCC_I2C4_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3
* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
*/
__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
{
__IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U));
return (uint32_t)((READ_BIT(*reg, (3UL << (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \
(((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (I2Cx & 0xFFFF0000UL));
}
/**
* @brief Get SPIx clock source
* @rmtoll CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource\n
* CCIPR1 SPI2SEL LL_RCC_GetSPIClockSource\n
* CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource
* @param SPIx This parameter can be one of the following values:
* @arg @ref LL_RCC_SPI1_CLKSOURCE
* @arg @ref LL_RCC_SPI2_CLKSOURCE
* @arg @ref LL_RCC_SPI3_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2
* @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI
* @arg @ref LL_RCC_SPI1_CLKSOURCE_MSIK
* @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI
* @arg @ref LL_RCC_SPI2_CLKSOURCE_MSIK
* @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK3
* @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI
* @arg @ref LL_RCC_SPI3_CLKSOURCE_MSIK
*/
__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx)
{
__IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U));
return (uint32_t)((READ_BIT(*reg, (3UL << (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \
(((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (SPIx & 0xFFFF0000UL));
}
/**
* @brief Get LPTIMx clock source
* @rmtoll CCIPR1 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
* CCIPR3 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
* CCIPR3 LPTIM34SEL LL_RCC_GetLPTIMClockSource
* @param LPTIMx This parameter can be one of the following values:
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
* @arg @ref LL_RCC_LPTIM2_CLKSOURCE
* @arg @ref LL_RCC_LPTIM34_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_MSIK
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
* @arg @ref LL_RCC_LPTIM34_CLKSOURCE_MSIK
* @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSI
* @arg @ref LL_RCC_LPTIM34_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSE
*/
__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
{
__IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U));
return (uint32_t)((READ_BIT(*reg, (3UL << (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \
(((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (LPTIMx & 0xFFFF0000UL));
}
/**
* @brief Set Tim Input capture clock source
* @rmtoll CCIPR1 TIMICSEL LL_RCC_SetTIMICClockSource
* @param TIMICSource This parameter can be one of the following combined values:
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024
* @note HSI, MSI and MSIK clocks without division are also available when TIMICSEL[2] is 1.
* @note combination to be avoided :
* LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 and LL_RCC_CLKSOURCE_TIMIC_MSIK_DIV1024
* LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 and LL_RCC_CLKSOURCE_TIMIC_MSIK_DIV4
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetTIMICClockSource(uint32_t TIMICSource)
{
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, TIMICSource);
}
/**
* @brief Get Tim Input capture clock source
* @rmtoll CCIPR1 TIMICSEL LL_RCC_GetTIMICClockSource
* @retval Returned value can be one of the following combined values:
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4
* @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024
*/
__STATIC_INLINE uint32_t LL_RCC_GetTIMICClockSource(void)
{
return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL));
}
/**
* @brief Get FDCAN kernel clock source
* @rmtoll CCIPR1 FDCANSEL LL_RCC_GetFDCANClockSource
* @param FDCANx This parameter can be one of the following values:
* @arg @ref LL_RCC_FDCAN_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2
*/
__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR1, FDCANx));
}
/**
* @brief Get SAIx clock source
* @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n
* CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource
* @param SAIx This parameter can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE
* @arg @ref LL_RCC_SAI2_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
* @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1
* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2
* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3
* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
* @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI
*/
__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));
}
/**
* @brief Get SDMMCx kernel clock source
* @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
* @param SDMMCx This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC_KERNELCLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK
* @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 "P"
*/
__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
}
/**
* @brief Get SDMMC1/2 clock source
* @rmtoll CCIPR1 ICLKSEL LL_RCC_GetSDMMCClockSource
* @param SDMMCx This parameter can be one of the following values:
* @arg @ref LL_RCC_SDMMC_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48
* @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1
* @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL2
* @arg @ref LL_RCC_SDMMC12_CLKSOURCE_MSIK
*/
__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR1, SDMMCx));
}
/**
* @brief Get RNGx clock source
* @rmtoll CCIPR2 RNGSEL LL_RCC_GetRNGClockSource
* @param RNGx This parameter can be one of the following values:
* @arg @ref LL_RCC_RNG_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48_DIV2
* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI
*/
__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, RNGx));
}
/**
* @brief Get USBx clock source
* @rmtoll CCIPR1 ICLKSEL LL_RCC_GetUSBClockSource
* @param USBx This parameter can be one of the following values:
* @arg @ref LL_RCC_USB_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
* @arg @ref LL_RCC_USB_CLKSOURCE_PLL1
* @arg @ref LL_RCC_USB_CLKSOURCE_PLL2
* @arg @ref LL_RCC_USB_CLKSOURCE_MSIK
*/
__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR1, USBx));
}
/**
* @brief Get ADCx clock source
* @rmtoll CCIPR3 ADCDACSEL LL_RCC_SetADCDACClockSource
* @param ADCxDAC1 This parameter can be one of the following values:
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_MSIK
* @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE
*/
__STATIC_INLINE uint32_t LL_RCC_GetADCDACClockSource(uint32_t ADCxDAC1)
{
return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCxDAC1));
}
/**
* @brief Get DFSDM Audio Clock Source
* @rmtoll CCIPR3 ADF1SEL LL_RCC_GetADF1ClockSource
* @param ADF1x This parameter can be one of the following values:
* @arg @ref LL_RCC_ADF1_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK
* @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1
* @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3
* @arg @ref LL_RCC_ADF1_CLKSOURCE_MSIK
* @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN
*/
__STATIC_INLINE uint32_t LL_RCC_GetADF1ClockSource(uint32_t ADF1x)
{
return (uint32_t)(READ_BIT(RCC->CCIPR3, ADF1x));
}
/**
* @brief Get DAC1 Clock Source
* @rmtoll CCIPR3 DAC1SEL LL_RCC_GetDAC1ClockSource
* @param DAC1x This parameter can be one of the following values:
* @arg @ref LL_RCC_DAC1_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_DAC1_CLKSOURCE_LSE
* @arg @ref LL_RCC_DAC1_CLKSOURCE_LSI
*/
__STATIC_INLINE uint32_t LL_RCC_GetDAC1ClockSource(uint32_t DAC1x)
{
return (uint32_t)(READ_BIT(RCC->CCIPR3, DAC1x));
}
/**
* @brief Get MDF1 Clock Source
* @rmtoll CCIPR2 MDF1SEL LL_RCC_GetMDF1ClockSource
* @param MDF1x This parameter can be one of the following values:
* @arg @ref LL_RCC_MDF1_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK
* @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1
* @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3
* @arg @ref LL_RCC_MDF1_CLKSOURCE_MSIK
* @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN
*/
__STATIC_INLINE uint32_t LL_RCC_GetMDF1ClockSource(uint32_t MDF1x)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, MDF1x));
}
/**
* @brief Get OCTOSPI clock source
* @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource
* @param OCTOSPIx This parameter can be one of the following values:
* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSIK
* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL1
* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL2
*/
__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
}
#if defined (HSPI1)
/**
* @brief Get HSPI clock source
* @rmtoll CCIPR2 HSPISEL LL_RCC_GetHSPIClockSource
* @param HSPIx This parameter can be one of the following values:
* @arg @ref LL_RCC_HSPI_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_HSPI_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL1
* @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL2
* @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL3
*/
__STATIC_INLINE uint32_t LL_RCC_GetHSPIClockSource(uint32_t HSPIx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, HSPIx));
}
#endif /* HSPI1 */
/**
* @}
*/
/**
* @brief Get SAES kernel clock source
* @rmtoll CCIPR2 SAESSEL LL_RCC_GetSAESClockSource
* @param SAESx This parameter can be one of the following values:
* @arg @ref LL_RCC_SAES_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI
* @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI_DIV2
*/
__STATIC_INLINE uint32_t LL_RCC_GetSAESClockSource(uint32_t SAESx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, SAESx));
}
#if defined(DSI)
/**
* @brief Get DSI clock source
* @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource
* @param DSIx This parameter can be one of the following values:
* @arg @ref LL_RCC_DSI_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL3
*/
__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx));
}
#endif /* DSI */
#if defined(LTDC)
/**
* @brief Get LTDC clock source
* @rmtoll CCIPR2 LTDCSEL LL_RCC_GetLTDCClockSource
* @param LTDCx This parameter can be one of the following values:
* @arg @ref LL_RCC_LTDC_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2
* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3
*/
__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx));
}
#endif /* LTDC */
/** @defgroup RCC_LL_EF_RTC RTC
* @{
*/
/**
* @brief Set RTC Clock Source
* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
* set). The BDRST bit can be used to reset them.
* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
{
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
}
/**
* @brief Get RTC Clock Source
* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
*/
__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
{
return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
}
/**
* @brief Enable RTC
* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableRTC(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
}
/**
* @brief Disable RTC
* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableRTC(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
}
/**
* @brief Check if RTC has been enabled or not
* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
{
return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL);
}
/**
* @brief Force the Backup domain reset
* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
* @retval None
*/
__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
}
/**
* @brief Release the Backup domain reset
* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
* @retval None
*/
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_PLL1 PLL1
* @{
*/
/**
* @brief Enable PLL1
* @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_PLL1ON);
}
#define LL_RCC_PLL_Enable LL_RCC_PLL1_Enable /*!< alias for compatibility with legacy code */
/**
* @brief Disable PLL1
* @note Cannot be disabled if the PLL1 clock is used as the system clock
* @rmtoll CR PLLON LL_RCC_PLL1_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
}
#define LL_RCC_PLL_Disable LL_RCC_PLL1_Disable /*!< alias for compatibility with legacy code */
/**
* @brief Check if PLL1 Ready
* @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL);
}
#define LL_RCC_PLL_IsReady LL_RCC_PLL1_IsReady /*!< alias for compatibility with legacy code */
/**
* @brief Configure PLL1 used for SYSCLK Domain
* @note PLL1 Source, PLLM, PLLN and PLLR can be written only when PLL1 is disabled.
* @note PLLN/PLLR can be written only when PLL is disabled.
* @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SYS\n
* PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_SYS\n
* PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_SYS\n
* PLL1CFGR PLL1R LL_RCC_PLL1_ConfigDomain_SYS
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL1SOURCE_NONE
* @arg @ref LL_RCC_PLL1SOURCE_MSIS
* @arg @ref LL_RCC_PLL1SOURCE_HSI
* @arg @ref LL_RCC_PLL1SOURCE_HSE
* @param PLLM parameter can be a value between 1 and 16
* @param PLLR parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed)
* @param PLLN parameter can be a value between 4 and 512
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \
((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1R, ((PLLN - 1UL) << \
RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << \
RCC_PLL1DIVR_PLL1R_Pos));
}
#define LL_RCC_PLL_ConfigDomain_SYS LL_RCC_PLL1_ConfigDomain_SYS /*!< alias for compatibility with legacy code */
/**
* @brief Configure PLL1 used for SAI domain clock
* @note PLL1 Source, PLLM, PLLN and PLLPDIV can be written only when PLL1 is disabled.
* @note This can be selected for SAI1 or SAI2
* @rmtoll PLLC1FGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SAI\n
* PLLC1FGR PLL1M LL_RCC_PLL1_ConfigDomain_SAI\n
* PLLC1FGR PLL1N LL_RCC_PLL1_ConfigDomain_SAI\n
* PLLC1FGR PLL1P LL_RCC_PLL1_ConfigDomain_SAI
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL1SOURCE_NONE
* @arg @ref LL_RCC_PLL1SOURCE_MSIS
* @arg @ref LL_RCC_PLL1SOURCE_HSI
* @arg @ref LL_RCC_PLL1SOURCE_HSE
* @param PLLM parameter can be a value between 1 and 16
* @param PLLN parameter can be a value between 4 and 512
* @param PLLP parameter can be a value between 1 and 128
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
{
MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \
((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, ((PLLN - 1UL) << \
RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << \
RCC_PLL1DIVR_PLL1P_Pos));
}
#define LL_RCC_PLL_ConfigDomain_SAI LL_RCC_PLL1_ConfigDomain_SAI /*!< alias for compatibility with legacy code */
/**
* @brief Configure PLL1 used for 48Mhz domain clock
* @note PLL1 Source, PLLM, PLLN and PLLQ can be written only when PLL1 is disabled.
* @note This can be selected for USB, SDMMC
* @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_48M\n
* PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_48M\n
* PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_48M\n
* PLL1CFGR PLL1Q LL_RCC_PLL1_ConfigDomain_48M
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL1SOURCE_NONE
* @arg @ref LL_RCC_PLL1SOURCE_MSIS
* @arg @ref LL_RCC_PLL1SOURCE_HSI
* @arg @ref LL_RCC_PLL1SOURCE_HSE
* @param PLLM parameter can be a value between 1 and 16
* @param PLLN parameter can be a value between 4 and 512
* @param PLLQ parameter can be a value between 1 and 128
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
{
MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \
((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos));
MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1Q, ((PLLN - 1UL) << \
RCC_PLL1DIVR_PLL1N_Pos) | ((PLLQ - 1UL) << \
RCC_PLL1DIVR_PLL1Q_Pos));
}
#define LL_RCC_PLL_ConfigDomain_48M LL_RCC_PLL1_ConfigDomain_48M /*!< alias for compatibility with legacy code */
/**
* @brief Configure PLL clock source
* @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetMainSource
* @param PLL1Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL1SOURCE_NONE
* @arg @ref LL_RCC_PLL1SOURCE_MSIS
* @arg @ref LL_RCC_PLL1SOURCE_HSI
* @arg @ref LL_RCC_PLL1SOURCE_HSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source)
{
MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source);
}
#define LL_RCC_PLL_SetMainSource LL_RCC_PLL1_SetMainSource /*!< alias for compatibility with legacy code */
/**
* @brief Get the oscillator used as PLL1 clock source.
* @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetMainSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLL1SOURCE_NONE
* @arg @ref LL_RCC_PLL1SOURCE_MSIS
* @arg @ref LL_RCC_PLL1SOURCE_HSI
* @arg @ref LL_RCC_PLL1SOURCE_HSE
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_GetMainSource(void)
{
return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC));
}
#define LL_RCC_PLL_GetMainSource LL_RCC_PLL1_GetMainSource /*!< alias for compatibility with legacy code */
/**
* @brief Set Main PLL1 multiplication factor for VCO
* @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_SetN
* @param PLL1N parameter can be a value between 4 and 512
*/
__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N)
{
MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos);
}
#define LL_RCC_PLL_SetN LL_RCC_PLL1_SetN /*!< alias for compatibility with legacy code */
/**
* @brief Get Main PLL1 multiplication factor for VCO
* @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_GetN
* @retval Between 4 and 512
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
{
return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL);
}
#define LL_RCC_PLL_GetN LL_RCC_PLL1_GetN /*!< alias for compatibility with legacy code */
/**
* @brief Set Main PLL1 division factor for PLL1P
* @note Used for SAI1 and SAI2 clock
* @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_SetP
* @param PLL1P parameter can be a value between 1 and 128
*/
__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P)
{
MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos);
}
#define LL_RCC_PLL_SetP LL_RCC_PLL1_SetP /*!< alias for compatibility with legacy code */
/**
* @brief Get Main PLL1 division factor for PLL1P
* @note Used for SAI1 and SAI2 clock
* @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_GetP
* @retval Between 1 and 128
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
{
return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL);
}
#define LL_RCC_PLL_GetP LL_RCC_PLL1_GetP /*!< alias for compatibility with legacy code */
/**
* @brief Set Main PLL division factor for PLLQ
* @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
* @rmtoll PLLCFGR PLL1Q LL_RCC_PLL1_SetQ
* @param PLL1Q parameter can be a value between 1 and 128
*/
__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q)
{
MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos);
}
#define LL_RCC_PLL_SetQ LL_RCC_PLL1_SetQ /*!< alias for compatibility with legacy code */
/**
* @brief Get Main PLL division factor for PLLQ
* @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
* @rmtoll PLL1CFGR PLL1Q LL_RCC_PLL1_GetQ
* @retval Between 1 and 128
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
{
return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL);
}
#define LL_RCC_PLL_GetQ LL_RCC_PLL1_GetQ /*!< alias for compatibility with legacy code */
/**
* @brief Set Main PLL division factor for PLL1R
* @note Used for PLL1CLK selected for USB, SDMMC (48 MHz clock)
* @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR
* @param PLL1R parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed)
*/
__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R)
{
MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos);
}
#define LL_RCC_PLL_SetR LL_RCC_PLL1_SetR /*!< alias for compatibility with legacy code */
/**
* @brief Get Main PLL1 division factor for PLL1R
* @note Used for PLL1CLK (system clock)
* @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR
* @retval Between 1 and 128
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
{
return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL);
}
#define LL_RCC_PLL_GetR LL_RCC_PLL1_GetR /*!< alias for compatibility with legacy code */
/**
* @brief Set Division factor for the main PLL and other PLL
* @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetDivider
* @param PLL1M parameter can be a value between 1 and 16
*/
__STATIC_INLINE void LL_RCC_PLL1_SetDivider(uint32_t PLL1M)
{
MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos);
}
#define LL_RCC_PLL_SetDivider LL_RCC_PLL1_SetDivider /*!< alias for compatibility with legacy code */
/**
* @brief Get Division factor for the main PLL and other PLL
* @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetDivider
* @retval Between 1 and 16
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_GetDivider(void)
{
return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL);
}
#define LL_RCC_PLL_GetDivider LL_RCC_PLL1_GetDivider /*!< alias for compatibility with legacy code */
/**
* @brief Enable PLL1 output mapped on SAI domain clock
* @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_EnableDomain_SAI
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SAI(void)
{
SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
}
#define LL_RCC_PLL_EnableDomain_SAI LL_RCC_PLL1_EnableDomain_SAI /*!< alias for compatibility with legacy code */
/**
* @brief Disable PLL1 output mapped on SAI domain clock
* @note Cannot be disabled if the PLL1 clock is used as the system
* clock
* @note In order to save power, when the PLL1CLK of the PLL1 is
* not used, should be 0
* @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_DisableDomain_SAI
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SAI(void)
{
CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN);
}
#define LL_RCC_PLL_DisableDomain_SAI LL_RCC_PLL1_DisableDomain_SAI /*!< alias for compatibility with legacy code */
/**
* @brief Check if PLL1 output mapped on SAI domain clock is enabled
* @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_IsEnabledDomain_SAI
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_SAI(void)
{
return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == (RCC_PLL1CFGR_PLL1PEN)) ? 1UL : 0UL);
}
#define LL_RCC_PLL_IsEnabledDomain_SAI LL_RCC_PLL1_IsEnabledDomain_SAI /*!< alias for compatibility with legacy code */
/**
* @brief Enable PLL output mapped on 48MHz domain clock
* @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_EnableDomain_48M
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_48M(void)
{
SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
}
/**
* @brief Disable PLL1 output mapped on 48MHz domain clock
* @note Cannot be disabled if the PLL clock is used as the system
* clock
* @note In order to save power, when the PLL1CLK of the PLL1 is
* not used, should be 0
* @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_DisableDomain_48M
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_48M(void)
{
CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN);
}
#define LL_RCC_PLL_DisableDomain_48M LL_RCC_PLL1_DisableDomain_48M /*!< alias for compatibility with legacy code */
/**
* @brief Check if PLL1 output mapped on 48M domain clock is enabled
* @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_IsEnabledDomain_48M
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_48M(void)
{
return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == (RCC_PLL1CFGR_PLL1QEN)) ? 1UL : 0UL);
}
#define LL_RCC_PLL_IsEnabledDomain_48M LL_RCC_PLL1_IsEnabledDomain_48M /*!< alias for compatibility with legacy code */
/**
* @brief Enable PLL1 output mapped on SYSCLK domain
* @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_EnableDomain_SYS
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SYS(void)
{
SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
}
#define LL_RCC_PLL_EnableDomain_SYS LL_RCC_PLL1_EnableDomain_SYS /*!< alias for compatibility with legacy code */
/**
* @brief Disable PLL1 output mapped on SYSCLK domain
* @note Cannot be disabled if the PLL1 clock is used as the system
* clock
* @note In order to save power, when the PLL1CLK of the PLL1 is
* not used, Main PLL1 should be 0
* @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_DisableDomain_SYS
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SYS(void)
{
CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN);
}
#define LL_RCC_PLL_DisableDomain_SYS LL_RCC_PLL1_DisableDomain_SYS /*!< alias for compatibility with legacy code */
/**
* @brief Check if PLL1 output mapped on SYS domain clock is enabled
* @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_IsEnabledDomain_SYS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_SYS(void)
{
return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == (RCC_PLL1CFGR_PLL1REN)) ? 1UL : 0UL);
}
#define LL_RCC_PLL_IsEnabledDomain_SYS LL_RCC_PLL1_IsEnabledDomain_SYS /*!< alias for compatibility with legacy code */
/**
* @brief Enable PLL1 FRACN
* @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
{
SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
}
#define LL_RCC_PLLFRACN_Enable LL_RCC_PLL1FRACN_Enable /*!< alias for compatibility with legacy code */
/**
* @brief Check if PLL1 FRACN is enabled
* @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
{
return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL);
}
#define LL_RCC_PLLFRACN_IsEnabled LL_RCC_PLL1FRACN_IsEnabled /*!< alias for compatibility with legacy code */
/**
* @brief Disable PLL1 FRACN
* @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
{
CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN);
}
#define LL_RCC_PLLFRACN_Disable LL_RCC_PLL1FRACN_Disable /*!< alias for compatibility with legacy code */
/**
* @brief Set PLL1 FRACN Coefficient
* @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN
* @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
*/
__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
{
MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos);
}
#define LL_RCC_PLL_SetFRACN LL_RCC_PLL1_SetFRACN /*!< alias for compatibility with legacy code */
/**
* @brief Get PLL1 FRACN Coefficient
* @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN
* @retval A value between 0 and 8191 (0x1FFF)
*/
__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
{
return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos);
}
#define LL_RCC_PLL_GetFRACN LL_RCC_PLL1_GetFRACN /*!< alias for compatibility with legacy code */
/**
* @brief Set PLL1 VCO Input Range
* @note This API shall be called only when PLL1 is disabled.
* @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
* @param InputRange This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLINPUTRANGE_4_8
* @arg @ref LL_RCC_PLLINPUTRANGE_8_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
{
MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange << RCC_PLL1CFGR_PLL1RGE_Pos);
}
#define LL_RCC_PLL_SetVCOInputRange LL_RCC_PLL1_SetVCOInputRange /*!< alias for compatibility with legacy code */
/**
* @brief Set PLL1 EPOD Prescaler booster input clock
* @rmtoll PLL1CFGR PLL1MBOOST LL_RCC_SetPll1EPodPrescaler
* @param BoostDiv This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL1MBOOST_DIV_1
* @arg @ref LL_RCC_PLL1MBOOST_DIV_2
* @arg @ref LL_RCC_PLL1MBOOST_DIV_4
* @arg @ref LL_RCC_PLL1MBOOST_DIV_6
* @arg @ref LL_RCC_PLL1MBOOST_DIV_8
* @arg @ref LL_RCC_PLL1MBOOST_DIV_10
* @arg @ref LL_RCC_PLL1MBOOST_DIV_12
* @arg @ref LL_RCC_PLL1MBOOST_DIV_14
* @arg @ref LL_RCC_PLL1MBOOST_DIV_16
*/
__STATIC_INLINE void LL_RCC_SetPll1EPodPrescaler(uint32_t BoostDiv)
{
MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1MBOOST, BoostDiv);
}
/**
* @brief Get PLL1 EPOD Prescaler booster input clock
* @rmtoll PLL1CFGR PLL1MBOOST LL_RCC_GetPll1EPodPrescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLL1MBOOST_DIV_1
* @arg @ref LL_RCC_PLL1MBOOST_DIV_2
* @arg @ref LL_RCC_PLL1MBOOST_DIV_4
* @arg @ref LL_RCC_PLL1MBOOST_DIV_6
* @arg @ref LL_RCC_PLL1MBOOST_DIV_8
* @arg @ref LL_RCC_PLL1MBOOST_DIV_10
* @arg @ref LL_RCC_PLL1MBOOST_DIV_12
* @arg @ref LL_RCC_PLL1MBOOST_DIV_14
* @arg @ref LL_RCC_PLL1MBOOST_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetPll1EPodPrescaler(void)
{
return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1MBOOST));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_PLL2 PLL2
* @{
*/
/**
* @brief Enable PLL2
* @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_PLL2ON);
}
/**
* @brief Disable PLL2
* @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
}
/**
* @brief Check if PLL2 Ready
* @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY) ? 1UL : 0UL);
}
/**
* @brief Configure PLL2 used for 48Mhz domain clock
* @note PLL2 Source, PLLM, PLLN and PLLQ can be written only when PLL2 is disabled.
* @note This can be selected for USB, SDMMC
* @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_ConfigDomain_48M\n
* PLL2CFGR PLL2M LL_RCC_PLL2_ConfigDomain_48M\n
* PLL2CFGR PLL2N LL_RCC_PLL2_ConfigDomain_48M\n
* PLL2CFGR PLL2Q LL_RCC_PLL2_ConfigDomain_48M
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL2SOURCE_NONE
* @arg @ref LL_RCC_PLL2SOURCE_MSIS
* @arg @ref LL_RCC_PLL2SOURCE_HSI
* @arg @ref LL_RCC_PLL2SOURCE_HSE
* @param PLLM parameter can be a value between 1 and 16
* @param PLLN parameter can be a value between 4 and 512
* @param PLLQ parameter can be a value between 1 and 128
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
{
MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \
((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos));
MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2Q, ((PLLN - 1UL) << \
RCC_PLL2DIVR_PLL2N_Pos) | ((PLLQ - 1UL) << \
RCC_PLL2DIVR_PLL2Q_Pos));
}
/**
* @brief Configure PLL2 used for SAI domain clock
* @note PLL1 Source, PLLM, PLLN and PLL2P can be written only when PLL1 is disabled.
* @note This can be selected for SAI1 or SAI2
* @rmtoll PLLC2FGR PLL2SRC LL_RCC_PLL2_ConfigDomain_SAI\n
* PLLC2FGR PLL2M LL_RCC_PLL2_ConfigDomain_SAI\n
* PLLC2FGR PLL2N LL_RCC_PLL2_ConfigDomain_SAI\n
* PLLC2FGR PLL2P LL_RCC_PLL2_ConfigDomain_SAI
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL2SOURCE_NONE
* @arg @ref LL_RCC_PLL2SOURCE_MSIS
* @arg @ref LL_RCC_PLL2SOURCE_HSI
* @arg @ref LL_RCC_PLL2SOURCE_HSE
* @param PLLM parameter can be a value between 1 and 16
* @param PLLN parameter can be a value between 4 and 512
* @param PLLP parameter can be a value between 1 and 128
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
{
MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \
((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos));
MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2P, ((PLLN - 1UL) << \
RCC_PLL2DIVR_PLL2N_Pos) | ((PLLP - 1UL) << \
RCC_PLL2DIVR_PLL2P_Pos));
}
/**
* @brief Configure PLL2 used for ADC domain clock
* @note PLL2SRC/PLL2M/PLL2N/PLL2R can be written only when PLL2 is disabled.
* @note This can be selected for ADC
* @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_ConfigDomain_ADC\n
* PLL2CFGR PLL2M LL_RCC_PLL2_ConfigDomain_ADC\n
* PLL2CFGR PLL2N LL_RCC_PLL2_ConfigDomain_ADC\n
* PLL2CFGR PLL2R LL_RCC_PLL2_ConfigDomain_ADC
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL2SOURCE_NONE
* @arg @ref LL_RCC_PLL2SOURCE_MSIS
* @arg @ref LL_RCC_PLL2SOURCE_HSI
* @arg @ref LL_RCC_PLL2SOURCE_HSE
* @param PLLM parameter can be a value between 1 and 16
* @param PLLR parameter can be a value between 1 and 128
* @param PLLN parameter can be a value between 4 and 512
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \
((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos));
MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2R, ((PLLN - 1UL) << \
RCC_PLL2DIVR_PLL2N_Pos) | ((PLLR - 1UL) << \
RCC_PLL2DIVR_PLL2R_Pos));
}
/**
* @brief Configure PLL2 clock source
* @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_SetSource
* @param PLL2Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL2SOURCE_NONE
* @arg @ref LL_RCC_PLL2SOURCE_MSIS
* @arg @ref LL_RCC_PLL2SOURCE_HSI
* @arg @ref LL_RCC_PLL2SOURCE_HSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLL2Source)
{
MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, PLL2Source);
}
/**
* @brief Get the oscillator used as PLL2 clock source.
* @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_GetSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLL2SOURCE_NONE
* @arg @ref LL_RCC_PLL2SOURCE_MSIS
* @arg @ref LL_RCC_PLL2SOURCE_HSI
* @arg @ref LL_RCC_PLL2SOURCE_HSE
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void)
{
return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC));
}
/**
* @brief Set Main PLL2 multiplication factor for VCO
* @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_SetN
* @param PLL2N parameter can be a value between 4 and 512
*/
__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t PLL2N)
{
MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N, (PLL2N - 1UL) << RCC_PLL2DIVR_PLL2N_Pos);
}
/**
* @brief Get Main PLL2 multiplication factor for VCO
* @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_GetN
* @retval Between 4 and 512
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
{
return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1UL);
}
/**
* @brief Set Main PLL2 division factor for PLL2P
* @note Used for SAI1 and SAI2 clock
* @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_SetP
* @param PLL2P parameter can be a value between 1 and 128
*/
__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t PLL2P)
{
MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P, (PLL2P - 1UL) << RCC_PLL2DIVR_PLL2P_Pos);
}
/**
* @brief Get Main PLL2 division factor for PLL2P
* @note Used for SAI1 and SAI2 clock
* @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_GetP
* @retval Between 1 and 128
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
{
return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1UL);
}
/**
* @brief Set Main PLL division factor for PLLQ
* @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
* @rmtoll PLLCFGR PLL2Q LL_RCC_PLL2_SetQ
* @param PLL2Q parameter can be a value between 1 and 128
*/
__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t PLL2Q)
{
MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q, (PLL2Q - 1UL) << RCC_PLL2DIVR_PLL2Q_Pos);
}
/**
* @brief Get Main PLL division factor for PLLQ
* @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
* @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_GetQ
* @retval Between 1 and 128
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
{
return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL);
}
/**
* @brief Set Main PLL division factor for PLLQ
* @note Used for PLL2CLK selected for USB, SDMMC (48 MHz clock)
* @rmtoll PLL2CFGR PLL2R LL_RCC_PLL2_SetR
* @param PLL2R parameter can be a value between 1 and 128
*/
__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t PLL2R)
{
MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R, (PLL2R - 1UL) << RCC_PLL2DIVR_PLL2R_Pos);
}
/**
* @brief Get Main PLL2 division factor for PLL2R
* @note Used for PLL2CLK (system clock)
* @rmtoll PLL2DIVR PLL2R LL_RCC_PLL2_GetR
* @retval Between 1 and 128
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
{
return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL);
}
/**
* @brief Set Division factor for the main PLL and other PLL
* @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_SetDivider
* @param PLL2M parameter can be a value between 1 and 16
*/
__STATIC_INLINE void LL_RCC_PLL2_SetDivider(uint32_t PLL2M)
{
MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M, (PLL2M - 1UL) << RCC_PLL2CFGR_PLL2M_Pos);
}
/**
* @brief Get Division factor for the main PLL and other PLL
* @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_GetDivider
* @retval Between 1 and 16
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_GetDivider(void)
{
return (uint32_t)((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1UL);
}
/**
* @brief Enable PLL2 output mapped on SAI domain clock
* @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_EnableDomain_SAI
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_SAI(void)
{
SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
}
/**
* @brief Disable PLL2 output mapped on SAI domain clock
* @note In order to save power, when of the PLL2 is
* not used, should be 0
* @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_DisableDomain_SAI
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_SAI(void)
{
CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN);
}
/**
* @brief Check if PLL2 output mapped on SAI domain clock is enabled
* @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_IsEnabledDomain_SAI
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_SAI(void)
{
return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN) == (RCC_PLL2CFGR_PLL2PEN)) ? 1UL : 0UL);
}
/**
* @brief Enable PLL2 output mapped on 48MHz domain clock
* @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_EnableDomain_48M
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_48M(void)
{
SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
}
/**
* @brief Disable PLL2 output mapped on 48MHz domain clock
* @note In order to save power, when of the PLL2 48M is
* not used, should be 0
* @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_DisableDomain_48M
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_48M(void)
{
CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN);
}
/**
* @brief Check if PLL2 output mapped on 48M domain clock is enabled
* @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_IsEnabledDomain_48M
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_48M(void)
{
return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN) == (RCC_PLL2CFGR_PLL2QEN)) ? 1UL : 0UL);
}
/**
* @brief Enable PLL2 output mapped on ADC domain clock
* @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_EnableDomain_ADC
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_ADC(void)
{
SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
}
/**
* @brief Disable PLL2 output mapped on ADC domain clock
* @note In order to save power, when of the PLL2 ADC is
* not used, Main PLL2ADC should be 0
* @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_DisableDomain_ADC
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_ADC(void)
{
CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN);
}
/**
* @brief Check if PLL2 output mapped on ADC domain clock is enabled
* @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_IsEnabledDomain_ADC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_ADC(void)
{
return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN) == (RCC_PLL2CFGR_PLL2REN)) ? 1UL : 0UL);
}
/**
* @brief Enable PLL2 FRACN
* @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
{
SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN);
}
/**
* @brief Check if PLL2 FRACN is enabled
* @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
{
return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) == RCC_PLL2CFGR_PLL2FRACEN) ? 1UL : 0UL);
}
/**
* @brief Disable PLL2 FRACN
* @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
{
CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN);
}
/**
* @brief Set PLL2 FRACN Coefficient
* @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_SetFRACN
* @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
*/
__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
{
MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, FRACN << RCC_PLL2FRACR_PLL2FRACN_Pos);
}
/**
* @brief Get PLL2 FRACN Coefficient
* @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_GetFRACN
* @retval A value between 0 and 8191 (0x1FFF)
*/
__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
{
return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN) >> RCC_PLL2FRACR_PLL2FRACN_Pos);
}
/**
* @brief Set PLL2 VCO Input Range
* @note This API shall be called only when PLL2 is disabled.
* @rmtoll PLL2CFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange
* @param InputRange This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLINPUTRANGE_4_8
* @arg @ref LL_RCC_PLLINPUTRANGE_8_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
{
MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange << RCC_PLL2CFGR_PLL2RGE_Pos);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_PLL3 PLL3
* @{
*/
/**
* @brief Enable PLL3
* @rmtoll CR PLL3ON LL_RCC_PLL3_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_PLL3ON);
}
/**
* @brief Disable PLL3
* @rmtoll CR PLL3ON LL_RCC_PLL3_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
}
/**
* @brief Check if PLL3 Ready
* @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == RCC_CR_PLL3RDY) ? 1UL : 0UL);
}
/**
* @brief Configure PLL3 used for SAI domain clock
* @note PLL3SRC/PLL3M/PLL3N/PLL3PDIV can be written only when PLL3 is disabled.
* @note This can be selected for SAI1 or SAI2
* @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_SAI\n
* PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_SAI\n
* PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_SAI\n
* PLL3DIVR PLL3P LL_RCC_PLL3_ConfigDomain_SAI
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL3SOURCE_NONE
* @arg @ref LL_RCC_PLL3SOURCE_MSIS
* @arg @ref LL_RCC_PLL3SOURCE_HSI
* @arg @ref LL_RCC_PLL3SOURCE_HSE
* @param PLLM parameter can be a value between 1 and 16
* @param PLLN parameter can be a value between 4 and 512
* @param PLLP parameter can be a value between 1 and 128
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
{
MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \
((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos));
MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3P, ((PLLN - 1UL) << \
RCC_PLL3DIVR_PLL3N_Pos) | ((PLLP - 1UL) << \
RCC_PLL3DIVR_PLL3P_Pos));
}
/**
* @brief Configure PLL3 used for 48Mhz domain clock
* @note PLL3 Source, PLLM, PLLN and PLLQ can be written only when PLL3 is disabled.
* @note This can be selected for USB, SDMMC
* @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_48M\n
* PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_48M\n
* PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_48M\n
* PLL3CFGR PLL3Q LL_RCC_PLL3_ConfigDomain_48M
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL3SOURCE_NONE
* @arg @ref LL_RCC_PLL3SOURCE_MSIS
* @arg @ref LL_RCC_PLL3SOURCE_HSI
* @arg @ref LL_RCC_PLL3SOURCE_HSE
* @param PLLM parameter can be a value between 1 and 16
* @param PLLN parameter can be a value between 4 and 512
* @param PLLQ parameter can be a value between 1 and 128
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
{
MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \
((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos));
MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3Q, ((PLLN - 1UL) << \
RCC_PLL3DIVR_PLL3N_Pos) | ((PLLQ - 1UL) << \
RCC_PLL3DIVR_PLL3Q_Pos));
}
#if defined(LTDC) || defined(HSPI1)
/**
* @brief Configure PLL3 used for HSPI_LTDC domain clock
* @note PLL3 Source, PLLM, PLLN and PLLR can be written only when PLL3 is disabled.
* @note This can be selected for HSPI and LTDC
* @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n
* PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n
* PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n
* PLL3CFGR PLL3R LL_RCC_PLL3_ConfigDomain_HSPI_LTDC
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL3SOURCE_NONE
* @arg @ref LL_RCC_PLL3SOURCE_MSIS
* @arg @ref LL_RCC_PLL3SOURCE_HSI
* @arg @ref LL_RCC_PLL3SOURCE_HSE
* @param PLLM parameter can be a value between 1 and 16
* @param PLLN parameter can be a value between 4 and 512
* @param PLLR parameter can be a value between 1 and 128
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_HSPI_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \
((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos));
MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3R, ((PLLN - 1UL) << \
RCC_PLL3DIVR_PLL3N_Pos) | ((PLLR - 1UL) << \
RCC_PLL3DIVR_PLL3R_Pos));
}
#endif /* LTDC || HSPI1 */
/**
* @brief Configure PLL3 clock source
* @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_SetSource
* @param PLLSource This parameter can be one of the following values:
* @arg @ref LL_RCC_PLL3SOURCE_NONE
* @arg @ref LL_RCC_PLL3SOURCE_MSIS
* @arg @ref LL_RCC_PLL3SOURCE_HSI
* @arg @ref LL_RCC_PLL3SOURCE_HSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource)
{
MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, PLLSource);
}
/**
* @brief Get the oscillator used as PLL3 clock source.
* @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_GetSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLL3SOURCE_NONE
* @arg @ref LL_RCC_PLL3SOURCE_MSIS
* @arg @ref LL_RCC_PLL3SOURCE_HSI
* @arg @ref LL_RCC_PLL3SOURCE_HSE
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void)
{
return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC));
}
/**
* @brief Set Main PLL3 multiplication factor for VCO
* @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_SetN
* @param PLL3N parameter can be a value between 4 and 512
*/
__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t PLL3N)
{
MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N, (PLL3N - 1UL) << RCC_PLL3DIVR_PLL3N_Pos);
}
/**
* @brief Get Main PLL3 multiplication factor for VCO
* @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_GetN
* @retval Between 4 and 512
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
{
return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1UL);
}
/**
* @brief Set Main PLL3 division factor for PLL3P
* @note Used for SAI1 and SAI2 clock
* @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_SetP
* @param PLL3P parameter can be a value between 1 and 128
*/
__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t PLL3P)
{
MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P, (PLL3P - 1UL) << RCC_PLL3DIVR_PLL3P_Pos);
}
/**
* @brief Get Main PLL3 division factor for PLL3P
* @note Used for SAI1 and SAI2 clock
* @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_GetP
* @retval Between 1 and 128
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
{
return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1UL);
}
/**
* @brief Set Main PLL division factor for PLLQ
* @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
* @rmtoll PLLCFGR PLL3Q LL_RCC_PLL3_SetQ
* @param PLL3Q parameter can be a value between 1 and 128
*/
__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t PLL3Q)
{
MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q, (PLL3Q - 1UL) << RCC_PLL3DIVR_PLL3Q_Pos);
}
/**
* @brief Get Main PLL division factor for PLLQ
* @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock)
* @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_GetQ
* @retval Between 1 and 128
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
{
return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1UL);
}
/**
* @brief Set Main PLL division factor for PLLQ
* @note Used for PLL3CLK selected for USB, SDMMC (48 MHz clock)
* @rmtoll PLL3CFGR PLL3R LL_RCC_PLL3_SetR
* @param PLL3R parameter can be a value between 1 and 128
*/
__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t PLL3R)
{
MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R, (PLL3R - 1UL) << RCC_PLL3DIVR_PLL3R_Pos);
}
/**
* @brief Get Main PLL3 division factor for PLL3R
* @note Used for PLL3CLK (system clock)
* @rmtoll PLL3DIVR PLL3R LL_RCC_PLL3_GetR
* @retval Between 1 and 128
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
{
return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1UL);
}
/**
* @brief Set Division factor for the main PLL and other PLL
* @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_SetDivider
* @param PLL3M parameter can be a value between 1 and 16
*/
__STATIC_INLINE void LL_RCC_PLL3_SetDivider(uint32_t PLL3M)
{
MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M, (PLL3M - 1UL) << RCC_PLL3CFGR_PLL3M_Pos);
}
/**
* @brief Get Division factor for the main PLL and other PLL
* @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_GetDivider
* @retval Between 1 and 16
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_GetDivider(void)
{
return (uint32_t)((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1UL);
}
/**
* @brief Enable PLL3 output mapped on SAI domain clock
* @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_EnableDomain_SAI
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_SAI(void)
{
SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
}
/**
* @brief Disable PLL3 output mapped on SAI domain clock
* @note In order to save power, when of the PLLSAI2 is
* not used, should be 0
* @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_DisableDomain_SAI
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_SAI(void)
{
CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN);
}
/**
* @brief Check if PLL3 output mapped on SAI domain clock is enabled
* @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_IsEnabledDomain_SAI
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_SAI(void)
{
return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN) == (RCC_PLL3CFGR_PLL3PEN)) ? 1UL : 0UL);
}
/**
* @brief Enable PLL2 output mapped on 48MHz domain clock
* @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_EnableDomain_48M
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_48M(void)
{
SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
}
/**
* @brief Disable PLL3 output mapped on 48MHz domain clock
* @note In order to save power, when of the PLL3 is
* not used, should be 0
* @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_DisableDomain_48M
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_48M(void)
{
CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN);
}
/**
* @brief Check if PLL3 output mapped on 48M domain clock is enabled
* @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_IsEnabledDomain_48M
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_48M(void)
{
return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN) == (RCC_PLL3CFGR_PLL3QEN)) ? 1UL : 0UL);
}
#if defined(LTDC) || defined(HSPI1)
/**
* @brief Enable PLL3 output mapped on HSPI_LTDC domain clock
* @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_EnableDomain_HSPI_LTDC
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_HSPI_LTDC(void)
{
SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);
}
/**
* @brief Disable PLL3 output mapped on HSPI_LTDC domain clock
* @note In order to save power, when of the PLL3 is
* not used, should be 0
* @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_DisableDomain_HSPI_LTDC
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_HSPI_LTDC(void)
{
CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN);
}
/**
* @brief Check if PLL3 output mapped on HSPI_LTDC domain clock is enabled
* @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC(void)
{
return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN) == (RCC_PLL3CFGR_PLL3REN)) ? 1UL : 0UL);
}
#endif /* LTDC || HSPI1 */
/**
* @brief Enable PLL3 FRACN
* @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
{
SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN);
}
/**
* @brief Check if PLL3 FRACN is enabled
* @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
{
return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) == RCC_PLL3CFGR_PLL3FRACEN) ? 1UL : 0UL);
}
/**
* @brief Disable PLL3 FRACN
* @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
{
CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN);
}
/**
* @brief Set PLL3 FRACN Coefficient
* @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_SetFRACN
* @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
*/
__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
{
MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, FRACN << RCC_PLL3FRACR_PLL3FRACN_Pos);
}
/**
* @brief Get PLL3 FRACN Coefficient
* @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_GetFRACN
* @retval A value between 0 and 8191 (0x1FFF)
*/
__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
{
return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN) >> RCC_PLL3FRACR_PLL3FRACN_Pos);
}
/**
* @brief Set PLL3 VCO Input Range
* @note This API shall be called only when PLL3 is disabled.
* @rmtoll PLL3CFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange
* @param InputRange This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLINPUTRANGE_4_8
* @arg @ref LL_RCC_PLLINPUTRANGE_8_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
{
MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange << RCC_PLL3CFGR_PLL3RGE_Pos);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_PRIV Privileged mode
* @{
*/
/**
* @brief Enable privileged mode
* @rmtoll PRIVCFGR SPRIV LL_RCC_EnablePrivilegedMode
* @rmtoll PRIVCFGR NSPRIV LL_RCC_EnablePrivilegedMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnablePrivilegedMode(void)
{
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
#else
SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
}
/**
* @brief Disable Privileged mode
* @rmtoll CR PRIV LL_RCC_DisablePrivilegedMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisablePrivilegedMode(void)
{
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV);
#else
CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV);
#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
}
/**
* @brief Check if Privileged mode has been enabled or not
* @rmtoll CR PRIV LL_RCC_IsEnabledPrivilegedMode
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledPrivilegedMode(void)
{
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL);
#else
return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL);
#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Clear LSI ready interrupt flag
* @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
}
/**
* @brief Clear LSE ready interrupt flag
* @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
}
/**
* @brief Clear MSI ready interrupt flag
* @rmtoll CICR MSISRDYC LL_RCC_ClearFlag_MSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_MSISRDYC);
}
/**
* @brief Clear HSI ready interrupt flag
* @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
}
/**
* @brief Clear HSE ready interrupt flag
* @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
}
/**
* @brief Clear HSI48 ready interrupt flag
* @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
}
/**
* @brief Clear PLL1 ready interrupt flag
* @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC);
}
/**
* @brief Clear PLL2 ready interrupt flag
* @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
}
/**
* @brief Clear PLL3 ready interrupt flag
* @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
}
/**
* @brief Clear Clock security system interrupt flag
* @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
{
SET_BIT(RCC->CICR, RCC_CICR_CSSC);
}
/**
* @brief Clear MSIK ready interrupt flag
* @rmtoll CICR MSIKRDYC LL_RCC_ClearFlag_MSIKRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_MSIKRDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_MSIKRDYC);
}
/**
* @brief Clear SHSI ready interrupt flag
* @rmtoll CICR SHSIRDYC LL_RCC_ClearFlag_SHSIRDY
* @retval None
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__STATIC_INLINE void LL_RCC_ClearFlag_SHSIRDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_SHSIRDYC);
}
#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/
/**
* @brief Check if LSI ready interrupt occurred or not
* @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
}
/**
* @brief Check if LSE ready interrupt occurred or not
* @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
}
/**
* @brief Check if MSI ready interrupt occurred or not
* @rmtoll CIFR MSISRDYF LL_RCC_IsActiveFlag_MSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSISRDYF) == RCC_CIFR_MSISRDYF) ? 1UL : 0UL);
}
/**
* @brief Check if HSI ready interrupt occurred or not
* @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
}
/**
* @brief Check if HSE ready interrupt occurred or not
* @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
}
/**
* @brief Check if HSI48 ready interrupt occurred or not
* @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
}
/**
* @brief Check if PLL1 ready interrupt occurred or not
* @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL);
}
/**
* @brief Check if PLL2 ready interrupt occurred or not
* @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL);
}
/**
* @brief Check if PLL3 ready interrupt occurred or not
* @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL);
}
/**
* @brief Check if Clock security system interrupt occurred or not
* @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL);
}
/**
* @brief Check if Clock security system interrupt occurred or not
* @rmtoll CIFR MSIKRDYF LL_RCC_IsActiveFlag_MSIKRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIKRDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIKRDYF) == RCC_CIFR_MSIKRDYF) ? 1UL : 0UL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Check if Clock security system interrupt occurred or not
* @rmtoll CIFR SHSIRDYF LL_RCC_IsActiveFlag_SHSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHSIRDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_SHSIRDYF) == RCC_CIFR_SHSIRDYF) ? 1UL : 0UL);
}
#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/
/**
* @brief Check if RCC flag Independent Watchdog reset is set or not.
* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag Low Power reset is set or not.
* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag is set or not.
* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag Pin reset is set or not.
* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag Software reset is set or not.
* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag Window Watchdog reset is set or not.
* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag BOR reset is set or not.
* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL);
}
/**
* @brief Set RMVF bit to clear the reset flags.
* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
{
SET_BIT(RCC->CSR, RCC_CSR_RMVF);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_IT_Management IT Management
* @{
*/
/**
* @brief Enable LSI ready interrupt
* @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
}
/**
* @brief Enable LSE ready interrupt
* @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
}
/**
* @brief Enable MSI ready interrupt
* @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_MSISRDYIE);
}
/**
* @brief Enable HSI ready interrupt
* @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
}
/**
* @brief Enable HSE ready interrupt
* @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
}
/**
* @brief Enable HSI48 ready interrupt
* @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
}
/**
* @brief Enable PLL1 ready interrupt
* @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
}
/**
* @brief Enable PLL2 ready interrupt
* @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
}
/**
* @brief Enable PLL3 ready interrupt
* @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
}
/**
* @brief Enable MSIKRDYIE ready interrupt
* @rmtoll CIER MSIKRDYIE LL_RCC_EnableIT_MSIKRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_MSIKRDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Enable SHSIRDYIE ready interrupt
* @rmtoll CIER SHSIRDYIE LL_RCC_EnableIT_SHSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_SHSIRDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE);
}
#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/
/**
* @brief Disable LSI ready interrupt
* @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
}
/**
* @brief Disable LSE ready interrupt
* @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
}
/**
* @brief Disable MSI ready interrupt
* @rmtoll CIER MSISRDYIE LL_RCC_DisableIT_MSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_MSISRDYIE);
}
/**
* @brief Disable HSI ready interrupt
* @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
}
/**
* @brief Disable HSE ready interrupt
* @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
}
/**
* @brief Disable HSI48 ready interrupt
* @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
}
/**
* @brief Disable PLL1 ready interrupt
* @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
}
/**
* @brief Disable PLL2 ready interrupt
* @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
}
/**
* @brief Disable PLL3 ready interrupt
* @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
}
/**
* @brief Disable MSIKRDYIE ready interrupt
* @rmtoll CIER MSIKRDYIE LL_RCC_DisableIT_MSIKRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_MSIKRDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Disable SHSIRDYIE ready interrupt
* @rmtoll CIER SHSIRDYIE LL_RCC_DisableIT_SHSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_SHSIRDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE);
}
#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/
/**
* @brief Checks if LSI ready interrupt source is enabled or disabled.
* @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
}
/**
* @brief Checks if LSE ready interrupt source is enabled or disabled.
* @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
}
/**
* @brief Checks if MSI ready interrupt source is enabled or disabled.
* @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_MSISRDYIE) == RCC_CIER_MSISRDYIE) ? 1UL : 0UL);
}
/**
* @brief Checks if HSI ready interrupt source is enabled or disabled.
* @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
}
/**
* @brief Checks if HSE ready interrupt source is enabled or disabled.
* @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
}
/**
* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
* @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
}
/**
* @brief Checks if PLL1 ready interrupt source is enabled or disabled.
* @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
}
/**
* @brief Checks if PLL2 ready interrupt source is enabled or disabled.
* @rmtoll CIER PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);
}
/**
* @brief Checks if PLL3 ready interrupt source is enabled or disabled.
* @rmtoll CIER PLL3RDYIE LL_RCC_IsEnabledIT_PLL3RDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);
}
/**
* @brief Checks if MSIK ready interrupt source is enabled or disabled.
* @rmtoll CIER MSIKRDYIE LL_RCC_IsEnabledIT_MSIKRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIKRDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE) == RCC_CIER_MSIKRDYIE) ? 1UL : 0UL);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Checks if SHSI ready interrupt source is enabled or disabled.
* @rmtoll CIER SHSIRDYIE LL_RCC_IsEnabledIT_SHSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_SHSIRDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE) == RCC_CIER_SHSIRDYIE) ? 1UL : 0UL);
}
#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/
/**
* @}
*/
/** @defgroup RCC_LL_EF_Security_Services Security Services
* @{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Configure RCC resources security
* @note Only available from secure state when system implements security (TZEN=1)
* @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n
* SECCFGR HSESEC LL_RCC_ConfigSecure\n
* SECCFGR MSISEC LL_RCC_ConfigSecure\n
* SECCFGR LSISEC LL_RCC_ConfigSecure\n
* SECCFGR LSESEC LL_RCC_ConfigSecure\n
* SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n
* SECCFGR PRESCSEC LL_RCC_ConfigSecure\n
* SECCFGR PLL1SEC LL_RCC_ConfigSecure\n
* SECCFGR PLL2SEC LL_RCC_ConfigSecure\n
* SECCFGR PLL3SEC LL_RCC_ConfigSecure\n
* SECCFGR CLK48MSEC LL_RCC_ConfigSecure\n
* SECCFGR HSI48SEC LL_RCC_ConfigSecure\n
* SECCFGR RMVFSEC LL_RCC_ConfigSecure
* @param SecureConfig This parameter can be one or a combination of the following values:
* @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC
* @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC
* @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC
* @arg @ref LL_RCC_MSI_SEC & LL_RCC_MSI_NSEC
* @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC
* @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC
* @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC
* @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC
* @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC
* @arg @ref LL_RCC_PLL2_SEC & LL_RCC_PLL2_NSEC
* @arg @ref LL_RCC_PLL3_SEC & LL_RCC_PLL3_NSEC
* @arg @ref LL_RCC_CLK48M_SEC & LL_RCC_CLK48M_NSEC
* @arg @ref LL_RCC_HSI48_SEC & LL_RCC_HSI48_NSEC
* @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC
* @retval None
*/
__STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t SecureConfig)
{
WRITE_REG(RCC->SECCFGR, SecureConfig);
}
#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief Get RCC resources security status
* @note Only available from secure state when system implements security (TZEN=1)
* @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n
* SECCFGR HSESEC LL_RCC_GetConfigSecure\n
* SECCFGR MSISEC LL_RCC_GetConfigSecure\n
* SECCFGR LSISEC LL_RCC_GetConfigSecure\n
* SECCFGR LSESEC LL_RCC_GetConfigSecure\n
* SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n
* SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n
* SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n
* SECCFGR PLL2SEC LL_RCC_GetConfigSecure\n
* SECCFGR PLL3SEC LL_RCC_GetConfigSecure\n
* SECCFGR CLK48MSEC LL_RCC_GetConfigSecure\n
* SECCFGR HSI48SEC LL_RCC_GetConfigSecure\n
* SECCFGR RMVFSEC LL_RCC_GetConfigSecure
* @retval Returned value can be one or a combination of the following values:
* @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC
* @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC
* @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC
* @arg @ref LL_RCC_MSI_SEC & LL_RCC_MSI_NSEC
* @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC
* @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC
* @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC
* @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC
* @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC
* @arg @ref LL_RCC_PLL2_SEC & LL_RCC_PLL2_NSEC
* @arg @ref LL_RCC_PLL3_SEC & LL_RCC_PLL3_NSEC
* @arg @ref LL_RCC_CLK48M_SEC & LL_RCC_CLK48M_NSEC
* @arg @ref LL_RCC_HSI48_SEC & LL_RCC_HSI48_NSEC
* @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC
* @retval None
*/
__STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void)
{
return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_EF_Init De-initialization function
* @{
*/
ErrorStatus LL_RCC_DeInit(void);
/**
* @}
*/
/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
* @{
*/
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCxSource);
uint32_t LL_RCC_GetADF1ClockFreq(uint32_t ADF1Source);
uint32_t LL_RCC_GetMDF1ClockFreq(uint32_t MDF1Source);
uint32_t LL_RCC_GetDAC1ClockFreq(uint32_t DAC1Source);
uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
uint32_t LL_RCC_GetSAESClockFreq(uint32_t SAESxSource);
uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
#if defined(DSI)
uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
#endif /* DSI */
#if defined(HSPI1)
uint32_t LL_RCC_GetHSPIClockFreq(uint32_t HSPIxSource);
#endif /* HSPI1 */
#if defined(LTDC)
uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
#endif /* defined(LTDC) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RCC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32u5xx_LL_RCC_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h
|
C
|
apache-2.0
| 233,781
|
/**
******************************************************************************
* @file stm32u5xx_ll_rng.h
* @author MCD Application Team
* @brief Header file of RNG LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_RNG_H
#define STM32U5xx_LL_RNG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (RNG)
/** @defgroup RNG_LL RNG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
* @{
*/
/**
* @brief LL RNG Init Structure Definition
*/
typedef struct
{
uint32_t ClockErrorDetection; /*!< Clock error detection.
This parameter can be one value of @ref RNG_LL_CED.
This parameter can be modified using unitary
functions @ref LL_RNG_EnableClkErrorDetect(). */
} LL_RNG_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
* @{
*/
/** @defgroup RNG_LL_CED Clock Error Detection
* @{
*/
#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
/**
* @}
*/
/** @defgroup RNG_LL_ARDIS Auto reset disable
* @{
*/
#define LL_RNG_ARDIS_ENABLE 0x00000000U /*!< ARDIS enabled automatic reset to clear SECS bit*/
#define LL_RNG_ARDIS_DISABLE RNG_CR_ARDIS /*!< ARDIS disabled no automatic reset to clear SECS bit*/
/**
* @}
*/
/** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
* programmable divider acting on the incoming RNG clock
* @{
*/
#define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */
#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */
/**
* @}
*/
/** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration
* @{
*/
#define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/
#define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */
/**
* @}
*/
/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RNG_ReadReg function
* @{
*/
#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
/**
* @}
*/
/** @defgroup RNG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
* @{
*/
#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
* @{
*/
/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in RNG register
* @param __INSTANCE__ RNG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in RNG register
* @param __INSTANCE__ RNG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
* @{
*/
/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
* @{
*/
/**
* @brief Enable Random Number Generation
* @rmtoll CR RNGEN LL_RNG_Enable
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_RNGEN);
}
/**
* @brief Disable Random Number Generation
* @rmtoll CR RNGEN LL_RNG_Disable
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
{
CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
}
/**
* @brief Check if Random Number Generator is enabled
* @rmtoll CR RNGEN LL_RNG_IsEnabled
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Clock Error Detection
* @rmtoll CR CED LL_RNG_EnableClkErrorDetect
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
{
CLEAR_BIT(RNGx->CR, RNG_CR_CED);
}
/**
* @brief Disable RNG Clock Error Detection
* @rmtoll CR CED LL_RNG_DisableClkErrorDetect
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_CED);
}
/**
* @brief Check if RNG Clock Error Detection is enabled
* @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
}
/**
* @brief Set RNG Conditioning Soft Reset bit
* @rmtoll CR CONDRST LL_RNG_EnableCondReset
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
* @brief Reset RNG Conditioning Soft Reset bit
* @rmtoll CR CONDRST LL_RNG_DisableCondReset
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
{
CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
* @brief Check if RNG Conditioning Soft Reset bit is set
* @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
}
/**
* @brief Enable RNG Config Lock
* @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
}
/**
* @brief Check if RNG Config Lock is enabled
* @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
}
/**
* @brief Enable NIST Compliance
* @rmtoll CR NISTC LL_RNG_EnableNistCompliance
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
{
CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
}
/**
* @brief Disable NIST Compliance
* @rmtoll CR NISTC LL_RNG_DisableNistCompliance
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_NISTC);
}
/**
* @brief Check if NIST Compliance is enabled
* @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
}
/**
* @brief Set RNG Config1 Configuration field value
* @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1
* @param RNGx RNG Instance
* @param Config1 Value between 0 and 0x3F
* @retval None
*/
__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
{
MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
}
/**
* @brief Get RNG Config1 Configuration field value
* @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1
* @param RNGx RNG Instance
* @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
*/
__STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
}
/**
* @brief Set RNG Config2 Configuration field value
* @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2
* @param RNGx RNG Instance
* @param Config2 Value between 0 and 0x7
* @retval None
*/
__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
{
MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
}
/**
* @brief Get RNG Config2 Configuration field value
* @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2
* @param RNGx RNG Instance
* @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
*/
__STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
}
/**
* @brief Set RNG Config3 Configuration field value
* @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3
* @param RNGx RNG Instance
* @param Config3 Value between 0 and 0xF
* @retval None
*/
__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
{
MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
}
/**
* @brief Get RNG Config3 Configuration field value
* @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3
* @param RNGx RNG Instance
* @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
*/
__STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
}
/**
* @brief Set RNG Clock divider factor
* @rmtoll CR CLKDIV LL_RNG_SetClockDivider
* @param RNGx RNG Instance
* @param Divider can be one of the following values:
* @arg @ref LL_RNG_CLKDIV_BY_1
* @arg @ref LL_RNG_CLKDIV_BY_2
* @arg @ref LL_RNG_CLKDIV_BY_4
* @arg @ref LL_RNG_CLKDIV_BY_8
* @arg @ref LL_RNG_CLKDIV_BY_16
* @arg @ref LL_RNG_CLKDIV_BY_32
* @arg @ref LL_RNG_CLKDIV_BY_64
* @arg @ref LL_RNG_CLKDIV_BY_128
* @arg @ref LL_RNG_CLKDIV_BY_256
* @arg @ref LL_RNG_CLKDIV_BY_512
* @arg @ref LL_RNG_CLKDIV_BY_1024
* @arg @ref LL_RNG_CLKDIV_BY_2048
* @arg @ref LL_RNG_CLKDIV_BY_4096
* @arg @ref LL_RNG_CLKDIV_BY_8192
* @arg @ref LL_RNG_CLKDIV_BY_16384
* @arg @ref LL_RNG_CLKDIV_BY_32768
* @retval None
*/
__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
{
MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
}
/**
* @brief Get RNG Clock divider factor
* @rmtoll CR CLKDIV LL_RNG_GetClockDivider
* @param RNGx RNG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RNG_CLKDIV_BY_1
* @arg @ref LL_RNG_CLKDIV_BY_2
* @arg @ref LL_RNG_CLKDIV_BY_4
* @arg @ref LL_RNG_CLKDIV_BY_8
* @arg @ref LL_RNG_CLKDIV_BY_16
* @arg @ref LL_RNG_CLKDIV_BY_32
* @arg @ref LL_RNG_CLKDIV_BY_64
* @arg @ref LL_RNG_CLKDIV_BY_128
* @arg @ref LL_RNG_CLKDIV_BY_256
* @arg @ref LL_RNG_CLKDIV_BY_512
* @arg @ref LL_RNG_CLKDIV_BY_1024
* @arg @ref LL_RNG_CLKDIV_BY_2048
* @arg @ref LL_RNG_CLKDIV_BY_4096
* @arg @ref LL_RNG_CLKDIV_BY_8192
* @arg @ref LL_RNG_CLKDIV_BY_16384
* @arg @ref LL_RNG_CLKDIV_BY_32768
*/
__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
{
return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
}
/**
* @}
*/
/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Indicate if the RNG Data ready Flag is set or not
* @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
}
/**
* @brief Indicate if the Clock Error Current Status Flag is set or not
* @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
}
/**
* @brief Indicate if the Seed Error Current Status Flag is set or not
* @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
}
/**
* @brief Indicate if the Clock Error Interrupt Status Flag is set or not
* @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
}
/**
* @brief Indicate if the Seed Error Interrupt Status Flag is set or not
* @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
}
/**
* @brief Clear Clock Error interrupt Status (CEIS) Flag
* @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
{
WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
}
/**
* @brief Clear Seed Error interrupt Status (SEIS) Flag
* @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
{
WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
}
/**
* @}
*/
/** @defgroup RNG_LL_EF_IT_Management IT Management
* @{
*/
/**
* @brief Enable Random Number Generator Interrupt
* (applies for either Seed error, Clock Error or Data ready interrupts)
* @rmtoll CR IE LL_RNG_EnableIT
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_IE);
}
/**
* @brief Disable Random Number Generator Interrupt
* (applies for either Seed error, Clock Error or Data ready interrupts)
* @rmtoll CR IE LL_RNG_DisableIT
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
{
CLEAR_BIT(RNGx->CR, RNG_CR_IE);
}
/**
* @brief Check if Random Number Generator Interrupt is enabled
* (applies for either Seed error, Clock Error or Data ready interrupts)
* @rmtoll CR IE LL_RNG_IsEnabledIT
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup RNG_LL_EF_Data_Management Data Management
* @{
*/
/**
* @brief Return32-bit Random Number value
* @rmtoll DR RNDATA LL_RNG_ReadRandData32
* @param RNGx RNG Instance
* @retval Generated 32-bit random value
*/
__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_REG(RNGx->DR));
}
/**
* @}
*/
/**
* @brief Enable Auto reset
* @rmtoll CR ARDIS LL_RNG_EnableArdis
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx)
{
CLEAR_BIT(RNGx->CR, RNG_CR_ARDIS);
}
/**
* @brief Disable Auto reset
* @rmtoll CR ARDIS LL_RNG_DisableArdis
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_ARDIS);
}
/**
* @brief Check if RNG Auto reset is enabled
* @rmtoll CR ARDIS LL_RNG_IsEnabledArdis
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL);
}
/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
* @{
*/
/**
* @brief Set RNG Health Test Control
* @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig
* @param RNGx RNG Instance
* @param HTCFG can be values of 32 bits
* @retval None
*/
__STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
{
WRITE_REG(RNGx->HTCR, HTCFG);
}
/**
* @brief Get RNG Health Test Control
* @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig
* @param RNGx RNG Instance
* @retval Return 32-bit RNG Health Test configuration
*/
__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
{
return (uint32_t)READ_REG(RNGx->HTCR);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* RNG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32U5xx_LL_RNG_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h
|
C
|
apache-2.0
| 22,153
|
/**
******************************************************************************
* @file stm32u5xx_ll_rtc.h
* @author MCD Application Team
* @brief Header file of RTC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_RTC_H
#define STM32U5xx_LL_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(RTC)
/** @defgroup RTC_LL RTC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTC_LL_Private_Constants RTC Private Constants
* @{
*/
/* Masks Definition */
#define RTC_LL_INIT_MASK 0xFFFFFFFFU
#define RTC_LL_RSF_MASK 0xFFFFFF5FU
/* Write protection defines */
#define RTC_WRITE_PROTECTION_DISABLE (uint8_t)0xFF
#define RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA
#define RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53
/* Defines used to combine date & time */
#define RTC_OFFSET_WEEKDAY 24U
#define RTC_OFFSET_DAY 16U
#define RTC_OFFSET_MONTH 8U
#define RTC_OFFSET_HOUR 16U
#define RTC_OFFSET_MINUTE 8U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_Private_Macros RTC Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
#if !defined (UNUSED)
#define UNUSED(x) ((void)(x))
#endif /* !defined (UNUSED) */
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
* @{
*/
/**
* @brief RTC Init structures definition
*/
typedef struct
{
uint32_t HourFormat; /*!< Specifies the RTC Hours Format.
This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetHourFormat(). */
uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetAsynchPrescaler(). */
uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetSynchPrescaler(). */
} LL_RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
This feature can be modified afterwards using unitary function
@ref LL_RTC_TIME_SetFormat(). */
uint8_t Hours; /*!< Specifies the RTC Time Hours.
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the
@ref LL_RTC_TIME_FORMAT_PM is selected.
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the
@ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
This feature can be modified afterwards using unitary function
@ref LL_RTC_TIME_SetHour(). */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59
This feature can be modified afterwards using unitary function
@ref LL_RTC_TIME_SetMinute(). */
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59
This feature can be modified afterwards using unitary function
@ref LL_RTC_TIME_SetSecond(). */
} LL_RTC_TimeTypeDef;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
This feature can be modified afterwards using unitary function
@ref LL_RTC_DATE_SetWeekDay(). */
uint8_t Month; /*!< Specifies the RTC Date Month.
This parameter can be a value of @ref RTC_LL_EC_MONTH
This feature can be modified afterwards using unitary function
@ref LL_RTC_DATE_SetMonth(). */
uint8_t Day; /*!< Specifies the RTC Date Day.
This parameter must be a number between Min_Data = 1 and Max_Data = 31
This feature can be modified afterwards using unitary function
@ref LL_RTC_DATE_SetDay(). */
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99
This feature can be modified afterwards using unitary function
@ref LL_RTC_DATE_SetYear(). */
} LL_RTC_DateTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or
@ref RTC_LL_EC_ALMB_MASK for ALARM B.
This feature can be modified afterwards using unitary function
@ref LL_RTC_ALMA_SetMask() for ALARM A
or @ref LL_RTC_ALMB_SetMask() for ALARM B
*/
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION
for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
This feature can be modified afterwards using unitary function
@ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or
@ref LL_RTC_ALMB_DisableWeekday() for ALARM B
*/
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay.
If AlarmDateWeekDaySel set to day, this parameter must be a number
between Min_Data = 1 and Max_Data = 31.
This feature can be modified afterwards using unitary function
@ref LL_RTC_ALMA_SetDay()
for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of
@ref RTC_LL_EC_WEEKDAY.
This feature can be modified afterwards using unitary function
@ref LL_RTC_ALMA_SetWeekDay()
for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
*/
} LL_RTC_AlarmTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
* @{
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_EC_FORMAT FORMAT
* @{
*/
#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */
#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
* @{
*/
#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */
#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
* @{
*/
#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */
#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RTC_ReadReg function
* @{
*/
#define LL_RTC_SCR_SSRUF RTC_SCR_CSSRUF
#define LL_RTC_SCR_ITSF RTC_SCR_CITSF
#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
#define LL_RTC_SCR_TSF RTC_SCR_CTSF
#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF
#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF
#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
#define LL_RTC_ICSR_BCDU_2 RTC_ICSR_BCDU_2
#define LL_RTC_ICSR_BCDU_1 RTC_ICSR_BCDU_1
#define LL_RTC_ICSR_BCDU_0 RTC_ICSR_BCDU_0
#define LL_RTC_ICSR_BIN_1 RTC_ICSR_BIN_1
#define LL_RTC_ICSR_BIN_0 RTC_ICSR_BIN_0
#define LL_RTC_ICSR_INITF RTC_ICSR_INITF
#define LL_RTC_ICSR_RSF RTC_ICSR_RSF
#define LL_RTC_ICSR_INITS RTC_ICSR_INITS
#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
/**
* @}
*/
/** @defgroup RTC_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions
* @{
*/
#define LL_RTC_CR_TSIE RTC_CR_TSIE
#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
/**
* @}
*/
/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY
* @{
*/
#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01 /*!< Monday */
#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02 /*!< Tuesday */
#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03 /*!< Wednesday */
#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04 /*!< Thrusday */
#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05 /*!< Friday */
#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06 /*!< Saturday */
#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07 /*!< Sunday */
/**
* @}
*/
/** @defgroup RTC_LL_EC_MONTH MONTH
* @{
*/
#define LL_RTC_MONTH_JANUARY (uint8_t)0x01 /*!< January */
#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02 /*!< February */
#define LL_RTC_MONTH_MARCH (uint8_t)0x03 /*!< March */
#define LL_RTC_MONTH_APRIL (uint8_t)0x04 /*!< April */
#define LL_RTC_MONTH_MAY (uint8_t)0x05 /*!< May */
#define LL_RTC_MONTH_JUNE (uint8_t)0x06 /*!< June */
#define LL_RTC_MONTH_JULY (uint8_t)0x07 /*!< July */
#define LL_RTC_MONTH_AUGUST (uint8_t)0x08 /*!< August */
#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09 /*!< September */
#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10 /*!< October */
#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11 /*!< November */
#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12 /*!< December */
/**
* @}
*/
/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT
* @{
*/
#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */
#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT
* @{
*/
#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */
#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */
#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */
#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
* @{
*/
#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM is open-drain output */
#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is push-pull output */
/**
* @}
*/
/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN
* @{
*/
#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
* @{
*/
#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */
#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */
/**
* @}
*/
/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND
* @{
*/
#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK
* @{
*/
#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/
#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */
#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */
#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */
#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */
#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT
* @{
*/
#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMA_SUBSECONDBIN_AUTOCLR RTC Alarm Sub Seconds with binary mode auto clear Definitions
* @{
*/
#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */
#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMASSR_SSCLR /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR -> SS[31:0]. */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK
* @{
*/
#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/
#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */
#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */
#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */
#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */
#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT
* @{
*/
#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMB_SUBSECONDBIN_AUTOCLR Alarm Sub Seconds with binary mode auto clear Definitions
* @{
*/
#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */
#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMBSSR_SSCLR /*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR -> SS[31:0]. */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
* @{
*/
#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT
* @{
*/
#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER TAMPER
* @{
*/
#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */
#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */
#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */
#define LL_RTC_TAMPER_4 TAMP_CR1_TAMP4E /*!< Tamper 4 input detection */
#define LL_RTC_TAMPER_5 TAMP_CR1_TAMP5E /*!< Tamper 5 input detection */
#define LL_RTC_TAMPER_6 TAMP_CR1_TAMP6E /*!< Tamper 6 input detection */
#define LL_RTC_TAMPER_7 TAMP_CR1_TAMP7E /*!< Tamper 7 input detection */
#define LL_RTC_TAMPER_8 TAMP_CR1_TAMP8E /*!< Tamper 8 input detection */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
* @{
*/
#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
* @{
*/
#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER4 TAMP_CR2_TAMP4NOERASE /*!< Tamper 4 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER5 TAMP_CR2_TAMP5NOERASE /*!< Tamper 5 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER6 TAMP_CR2_TAMP6NOERASE /*!< Tamper 6 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER7 TAMP_CR2_TAMP7NOERASE /*!< Tamper 7 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER8 TAMP_CR2_TAMP8NOERASE /*!< Tamper 8 event does not erase the backup registers. */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
* @{
*/
#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
* @{
*/
#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */
#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */
#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
* @{
*/
#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
* @{
*/
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP4 TAMP_CR2_TAMP4TRG /*!< Tamper 4 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP5 TAMP_CR2_TAMP5TRG /*!< Tamper 5 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP6 TAMP_CR2_TAMP6TRG /*!< Tamper 6 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP7 TAMP_CR2_TAMP7TRG /*!< Tamper 7 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP8 TAMP_CR2_TAMP8TRG /*!< Tamper 8 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
/**
* @}
*/
/** @defgroup RTC_LL_EC_INTERNAL INTERNAL TAMPER
* @{
*/
#define LL_RTC_TAMPER_ITAMP1 TAMP_CR1_ITAMP1E /*!< Internal tamper 1: RTC supply voltage monitoring */
#define LL_RTC_TAMPER_ITAMP2 TAMP_CR1_ITAMP2E /*!< Internal tamper 2: Temperature monitoring */
#define LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E /*!< Internal tamper 3: LSE monitoring */
#define LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E /*!< Internal tamper 5: RTC calendar overflow */
#define LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E /*!< Internal tamper 6: JTAG/SWD access when RDP > 0 */
#define LL_RTC_TAMPER_ITAMP7 TAMP_CR1_ITAMP7E /*!< Internal tamper 7: ADC4 analog watchdog monitoring 1 */
#define LL_RTC_TAMPER_ITAMP8 TAMP_CR1_ITAMP8E /*!< Internal tamper 8: Monotonic counter overflow */
#define LL_RTC_TAMPER_ITAMP9 TAMP_CR1_ITAMP9E /*!< Internal tamper 9: Cryptographic IPs fault*/
#define LL_RTC_TAMPER_ITAMP11 TAMP_CR1_ITAMP11E /*!< Internal tamper 11: IWDG reset when tamper flag is set */
#define LL_RTC_TAMPER_ITAMP12 TAMP_CR1_ITAMP12E /*!< Internal tamper 12: ADC4 analog watchdog monitoring 2*/
#define LL_RTC_TAMPER_ITAMP13 TAMP_CR1_ITAMP13E /*!< Internal tamper 13: ADC4 analog watchdog monitoring 3 */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ACTIVE_MODE ACTIVE TAMPER MODE
* @{
*/
#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM /*!< tamper 1 is active */
#define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM /*!< tamper 2 is active */
#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM /*!< tamper 3 is active */
#define LL_RTC_TAMPER_ATAMP_TAMP4AM TAMP_ATCR1_TAMP4AM /*!< tamper 4 is active */
#define LL_RTC_TAMPER_ATAMP_TAMP5AM TAMP_ATCR1_TAMP5AM /*!< tamper 5 is active */
#define LL_RTC_TAMPER_ATAMP_TAMP6AM TAMP_ATCR1_TAMP6AM /*!< tamper 6 is active */
#define LL_RTC_TAMPER_ATAMP_TAMP7AM TAMP_ATCR1_TAMP7AM /*!< tamper 7 is active */
#define LL_RTC_TAMPER_ATAMP_TAMP8AM TAMP_ATCR1_TAMP8AM /*!< tamper 8 is active */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK
* @{
*/
#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0u /*!< RTCCLK */
#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */
#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */
#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */
#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */
#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */
#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */
#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION ACTIVE TAMPER OUTPUT SELECTION
* @{
*/
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL1_Pos)
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL1_Pos)
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL1_Pos)
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL1_Pos)
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL1_Pos)
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL1_Pos)
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL1_Pos)
#define LL_RTC_TAMPER_ATAMP1IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL1_Pos)
#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL2_Pos)
#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL2_Pos)
#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL2_Pos)
#define LL_RTC_TAMPER_ATAMP2IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL2_Pos)
#define LL_RTC_TAMPER_ATAMP2IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL2_Pos)
#define LL_RTC_TAMPER_ATAMP2IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL2_Pos)
#define LL_RTC_TAMPER_ATAMP2IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL2_Pos)
#define LL_RTC_TAMPER_ATAMP2IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL2_Pos)
#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL3_Pos)
#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL3_Pos)
#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL3_Pos)
#define LL_RTC_TAMPER_ATAMP3IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL3_Pos)
#define LL_RTC_TAMPER_ATAMP3IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL3_Pos)
#define LL_RTC_TAMPER_ATAMP3IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL3_Pos)
#define LL_RTC_TAMPER_ATAMP3IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL3_Pos)
#define LL_RTC_TAMPER_ATAMP3IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL3_Pos)
#define LL_RTC_TAMPER_ATAMP4IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL4_Pos)
#define LL_RTC_TAMPER_ATAMP4IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL4_Pos)
#define LL_RTC_TAMPER_ATAMP4IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL4_Pos)
#define LL_RTC_TAMPER_ATAMP4IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL4_Pos)
#define LL_RTC_TAMPER_ATAMP4IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL4_Pos)
#define LL_RTC_TAMPER_ATAMP4IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL4_Pos)
#define LL_RTC_TAMPER_ATAMP4IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL4_Pos)
#define LL_RTC_TAMPER_ATAMP4IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL4_Pos)
#define LL_RTC_TAMPER_ATAMP5IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL5_Pos)
#define LL_RTC_TAMPER_ATAMP5IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL5_Pos)
#define LL_RTC_TAMPER_ATAMP5IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL5_Pos)
#define LL_RTC_TAMPER_ATAMP5IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL5_Pos)
#define LL_RTC_TAMPER_ATAMP5IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL5_Pos)
#define LL_RTC_TAMPER_ATAMP5IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL5_Pos)
#define LL_RTC_TAMPER_ATAMP5IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL5_Pos)
#define LL_RTC_TAMPER_ATAMP5IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL5_Pos)
#define LL_RTC_TAMPER_ATAMP6IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL6_Pos)
#define LL_RTC_TAMPER_ATAMP6IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL6_Pos)
#define LL_RTC_TAMPER_ATAMP6IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL6_Pos)
#define LL_RTC_TAMPER_ATAMP6IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL6_Pos)
#define LL_RTC_TAMPER_ATAMP6IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL6_Pos)
#define LL_RTC_TAMPER_ATAMP6IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL6_Pos)
#define LL_RTC_TAMPER_ATAMP6IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL6_Pos)
#define LL_RTC_TAMPER_ATAMP6IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL6_Pos)
#define LL_RTC_TAMPER_ATAMP7IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL7_Pos)
#define LL_RTC_TAMPER_ATAMP7IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL7_Pos)
#define LL_RTC_TAMPER_ATAMP7IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL7_Pos)
#define LL_RTC_TAMPER_ATAMP7IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL7_Pos)
#define LL_RTC_TAMPER_ATAMP7IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL7_Pos)
#define LL_RTC_TAMPER_ATAMP7IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL7_Pos)
#define LL_RTC_TAMPER_ATAMP7IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL7_Pos)
#define LL_RTC_TAMPER_ATAMP7IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL7_Pos)
#define LL_RTC_TAMPER_ATAMP8IN_ATAMP1OUT (0u << TAMP_ATCR2_ATOSEL8_Pos)
#define LL_RTC_TAMPER_ATAMP8IN_ATAMP2OUT (1u << TAMP_ATCR2_ATOSEL8_Pos)
#define LL_RTC_TAMPER_ATAMP8IN_ATAMP3OUT (2u << TAMP_ATCR2_ATOSEL8_Pos)
#define LL_RTC_TAMPER_ATAMP8IN_ATAMP4OUT (3u << TAMP_ATCR2_ATOSEL8_Pos)
#define LL_RTC_TAMPER_ATAMP8IN_ATAMP5OUT (4u << TAMP_ATCR2_ATOSEL8_Pos)
#define LL_RTC_TAMPER_ATAMP8IN_ATAMP6OUT (5u << TAMP_ATCR2_ATOSEL8_Pos)
#define LL_RTC_TAMPER_ATAMP8IN_ATAMP7OUT (6u << TAMP_ATCR2_ATOSEL8_Pos)
#define LL_RTC_TAMPER_ATAMP8IN_ATAMP8OUT (7u << TAMP_ATCR2_ATOSEL8_Pos)
/**
* @}
*/
/** @defgroup RTC_LL_EC_BKP BACKUP
* @{
*/
#define LL_RTC_BKP_NUMBER RTC_BACKUP_NB
#define LL_RTC_BKP_DR0 0U
#define LL_RTC_BKP_DR1 1U
#define LL_RTC_BKP_DR2 2U
#define LL_RTC_BKP_DR3 3U
#define LL_RTC_BKP_DR4 4U
#define LL_RTC_BKP_DR5 5U
#define LL_RTC_BKP_DR6 6U
#define LL_RTC_BKP_DR7 7U
#define LL_RTC_BKP_DR8 8U
#define LL_RTC_BKP_DR9 9U
#define LL_RTC_BKP_DR10 10U
#define LL_RTC_BKP_DR11 11U
#define LL_RTC_BKP_DR12 12U
#define LL_RTC_BKP_DR13 13U
#define LL_RTC_BKP_DR14 14U
#define LL_RTC_BKP_DR15 15U
#define LL_RTC_BKP_DR16 16U
#define LL_RTC_BKP_DR17 17U
#define LL_RTC_BKP_DR18 18U
#define LL_RTC_BKP_DR19 19U
#define LL_RTC_BKP_DR20 20U
#define LL_RTC_BKP_DR21 21U
#define LL_RTC_BKP_DR22 22U
#define LL_RTC_BKP_DR23 23U
#define LL_RTC_BKP_DR24 24U
#define LL_RTC_BKP_DR25 25U
#define LL_RTC_BKP_DR26 26U
#define LL_RTC_BKP_DR27 27U
#define LL_RTC_BKP_DR28 28U
#define LL_RTC_BKP_DR29 29U
#define LL_RTC_BKP_DR30 30U
#define LL_RTC_BKP_DR31 31U
/**
* @}
*/
/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV
* @{
*/
#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */
#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */
#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */
#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is selected */
#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
/**
* @}
*/
/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output
* @{
*/
#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */
#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */
/**
* @}
*/
/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion
* @{
*/
#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */
#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period
* @{
*/
#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */
#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */
#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */
/**
* @}
*/
/** @defgroup RTC_LL_EC_CALIB_LOWPOWER Calibration low power
* @{
*/
#define LL_RTC_CALIB_LOWPOWER_NONE 0x00000000U /*!< High conso mode */
#define LL_RTC_CALIB_LOWPOWER_SET RTC_CALR_LPCAL /*!< low power mode */
/**
* @}
*/
/** @defgroup RTC_LL_EC_BINARY_MODE Binary mode (Sub Second Register)
* @{
*/
#define LL_RTC_BINARY_NONE 0x00000000U /*!< Free running BCD calendar mode (Binary mode disabled). */
#define LL_RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */
#define LL_RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary mode enable */
/**
* @}
*/
/** @defgroup RTC_LL_EC_BINARY_MIX_BCDU Calendar second incrementation in Binary mix mode
* @{
*/
#define LL_RTC_BINARY_MIX_BCDU_0 0x00000000u /*!< 1s calendar increment is generated each time SS[7:0] = 0 */
#define LL_RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[8:0] = 0 */
#define LL_RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[9:0] = 0 */
#define LL_RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[10:0] = 0 */
#define LL_RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[11:0] = 0 */
#define LL_RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[12:0] = 0 */
#define LL_RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[13:0] = 0 */
#define LL_RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[14:0] = 0 */
/**
* @}
*/
/** @defgroup RTC_LL_EC_SECURE_RTC_FULL Secure full rtc
* @{
*/
#define LL_RTC_SECURE_FULL_YES RTC_SECCFGR_SEC /*!< RTC full secure */
#define LL_RTC_SECURE_FULL_NO 0U /*!< RTC is not full secure, features can be secure. See RTC_LL_EC_SECURE_RTC_FEATURE */
/**
* @}
*/
/** @defgroup RTC_LL_EC_UNSECURE_RTC_FEATURE UnSecure features rtc in case of LL_RTC_SECURE_FULL_NO.
* @{
*/
#define LL_RTC_UNSECURE_FEATURE_INIT ~RTC_SECCFGR_INITSEC /*!< Initialization feature is not secure */
#define LL_RTC_UNSECURE_FEATURE_CAL ~RTC_SECCFGR_CALSEC /*!< Calibration feature is not secure */
#define LL_RTC_UNSECURE_FEATURE_TS ~RTC_SECCFGR_TSSEC /*!< Time stamp feature is not secure */
#define LL_RTC_UNSECURE_FEATURE_WUT ~RTC_SECCFGR_WUTSEC /*!< Wake up timer feature is not secure */
#define LL_RTC_UNSECURE_FEATURE_ALRA ~RTC_SECCFGR_ALRASEC /*!< Alarm A feature is not secure */
#define LL_RTC_UNSECURE_FEATURE_ALRB ~RTC_SECCFGR_ALRBSEC /*!< Alarm B feature is not secure */
/**
* @}
*/
/** @defgroup RTC_LL_EC_SECURE_TAMP Secure tamp
* @{
*/
#define LL_TAMP_SECURE_FULL_YES TAMP_SECCFGR_TAMPSEC /*!< TAMP full secure */
#define LL_TAMP_SECURE_FULL_NO 0U /*!< TAMP is not secure */
/**
* @}
*/
/** @defgroup RTC_LL_EC_PRIVILEGE_RTC_FULL Privilege full rtc
* @{
*/
#define LL_RTC_PRIVILEGE_FULL_YES RTC_PRIVCFGR_PRIV /*!< RTC full privilege */
#define LL_RTC_PRIVILEGE_FULL_NO 0U /*!< RTC is not full privilege, features can be unprivilege. See RTC_LL_EC_PRIVILEGE_RTC_FEATURE */
/**
* @}
*/
/** @defgroup RTC_LL_EC_PRIVILEGE_RTC_FEATURE Privilege rtc features in case of LL_RTC_PRIVILEGE_FULL_NO.
* @{
*/
#define LL_RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCFGR_INITPRIV /*!< Initialization feature is privilege*/
#define LL_RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCFGR_CALPRIV /*!< Calibration feature is privilege */
#define LL_RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCFGR_TSPRIV /*!< Time stamp feature is privilege */
#define LL_RTC_PRIVILEGE_FEATURE_WUT RTC_PRIVCFGR_WUTPRIV /*!< Wake up timer feature is privilege */
#define LL_RTC_PRIVILEGE_FEATURE_ALRA RTC_PRIVCFGR_ALRAPRIV /*!< Alarm A feature is privilege */
#define LL_RTC_PRIVILEGE_FEATURE_ALRB RTC_PRIVCFGR_ALRBPRIV /*!< Alarm B feature is privilege */
/**
* @}
*/
/** @defgroup RTC_LL_EC_PRIVILEGE_TAMP_FULL Privilege full tamp
* @{
*/
#define LL_TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCFGR_TAMPPRIV /*!< TAMP full privilege */
#define LL_TAMP_PRIVILEGE_FULL_NO 0U /*!< TAMP is not privilege */
/**
* @}
*/
/** @defgroup RTC_LL_EC_PRIVILEGE_BACKUP_REG_ZONE Privilege Backup register privilege zone
* @{
*/
#define LL_RTC_PRIVILEGE_BKUP_ZONE_NONE 0U
#define LL_RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCFGR_BKPRWPRIV
#define LL_RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCFGR_BKPWPRIV
#define LL_RTC_PRIVILEGE_BKUP_ZONE_ALL (LL_RTC_PRIVILEGE_BKUP_ZONE_1 | LL_RTC_PRIVILEGE_BKUP_ZONE_2)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
* @{
*/
/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in RTC register
* @param __INSTANCE__ RTC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in RTC register
* @param __INSTANCE__ RTC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup RTC_LL_EM_Convert Convert helper Macros
* @{
*/
/**
* @brief Helper macro to convert a value from 2 digit decimal format to BCD format
* @param __VALUE__ Byte to be converted
* @retval Converted byte
*/
#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) ((uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)))
/**
* @brief Helper macro to convert a value from BCD format to 2 digit decimal format
* @param __VALUE__ BCD value to be converted
* @retval Converted byte
*/
#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> \
(uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU)))
/**
* @}
*/
/** @defgroup RTC_LL_EM_Date Date helper Macros
* @{
*/
/**
* @brief Helper macro to retrieve weekday.
* @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function.
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
*/
#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
/**
* @brief Helper macro to retrieve Year in BCD format
* @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
* @retval Year in BCD format (0x00 . . . 0x99)
*/
#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
/**
* @brief Helper macro to retrieve Month in BCD format
* @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_MONTH_JANUARY
* @arg @ref LL_RTC_MONTH_FEBRUARY
* @arg @ref LL_RTC_MONTH_MARCH
* @arg @ref LL_RTC_MONTH_APRIL
* @arg @ref LL_RTC_MONTH_MAY
* @arg @ref LL_RTC_MONTH_JUNE
* @arg @ref LL_RTC_MONTH_JULY
* @arg @ref LL_RTC_MONTH_AUGUST
* @arg @ref LL_RTC_MONTH_SEPTEMBER
* @arg @ref LL_RTC_MONTH_OCTOBER
* @arg @ref LL_RTC_MONTH_NOVEMBER
* @arg @ref LL_RTC_MONTH_DECEMBER
*/
#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
/**
* @brief Helper macro to retrieve Day in BCD format
* @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
* @retval Day in BCD format (0x01 . . . 0x31)
*/
#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
/**
* @}
*/
/** @defgroup RTC_LL_EM_Time Time helper Macros
* @{
*/
/**
* @brief Helper macro to retrieve hour in BCD format
* @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
* @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
*/
#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
/**
* @brief Helper macro to retrieve minute in BCD format
* @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
* @retval Minutes in BCD format (0x00. . .0x59)
*/
#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
/**
* @brief Helper macro to retrieve second in BCD format
* @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
* @retval Seconds in format (0x00. . .0x59)
*/
#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
* @{
*/
/** @defgroup RTC_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Set Hours format (24 hour/day or AM/PM hour format)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @rmtoll RTC_CR FMT LL_RTC_SetHourFormat
* @param RTCx RTC Instance
* @param HourFormat This parameter can be one of the following values:
* @arg @ref LL_RTC_HOURFORMAT_24HOUR
* @arg @ref LL_RTC_HOURFORMAT_AMPM
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
{
MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
}
/**
* @brief Get Hours format (24 hour/day or AM/PM hour format)
* @rmtoll RTC_CR FMT LL_RTC_GetHourFormat
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_HOURFORMAT_24HOUR
* @arg @ref LL_RTC_HOURFORMAT_AMPM
*/
__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
}
/**
* @brief Select the flag to be routed to RTC_ALARM output
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR OSEL LL_RTC_SetAlarmOutEvent
* @param RTCx RTC Instance
* @param AlarmOutput This parameter can be one of the following values:
* @arg @ref LL_RTC_ALARMOUT_DISABLE
* @arg @ref LL_RTC_ALARMOUT_ALMA
* @arg @ref LL_RTC_ALARMOUT_ALMB
* @arg @ref LL_RTC_ALARMOUT_WAKEUP
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
{
MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
}
/**
* @brief Get the flag to be routed to RTC_ALARM output
* @rmtoll RTC_CR OSEL LL_RTC_GetAlarmOutEvent
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_ALARMOUT_DISABLE
* @arg @ref LL_RTC_ALARMOUT_ALMA
* @arg @ref LL_RTC_ALARMOUT_ALMB
* @arg @ref LL_RTC_ALARMOUT_WAKEUP
*/
__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
}
/**
* @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
* @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
* @param RTCx RTC Instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
* @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
{
MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output);
}
/**
* @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
* @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
* @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
*/
__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));
}
/**
* @brief Enable initialization mode
* @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
* and prescaler register (RTC_PRER).
* Counters are stopped and start counting from the new value when INIT is reset.
* @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
{
/* Set the Initialization mode */
SET_BIT(RTCx->ICSR, RTC_ICSR_INIT);
}
/**
* @brief Disable initialization mode (Free running mode)
* @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
{
/* Exit Initialization mode */
CLEAR_BIT(RTCx->ICSR, RTC_ICSR_INIT);
}
/**
* @brief Set Binary mode (Sub Second Register)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function).
* @rmtoll RTC_ICSR BIN LL_RTC_SetBinaryMode
* @param RTCx RTC Instance
* @param BinaryMode can be one of the following values:
* @arg @ref LL_RTC_BINARY_NONE
* @arg @ref LL_RTC_BINARY_ONLY
* @arg @ref LL_RTC_BINARY_MIX
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetBinaryMode(RTC_TypeDef *RTCx, uint32_t BinaryMode)
{
MODIFY_REG(RTCx->ICSR, RTC_ICSR_BIN, BinaryMode);
}
/**
* @brief Get Binary mode (Sub Second Register)
* @rmtoll RTC_ICSR BIN LL_RTC_GetBinaryMode
* @param RTCx RTC Instance
* @retval This parameter can be one of the following values:
* @arg @ref LL_RTC_BINARY_NONE
* @arg @ref LL_RTC_BINARY_ONLY
* @arg @ref LL_RTC_BINARY_MIX
* @retval None
*/
__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BIN));
}
/**
* @brief Set Binary Mix mode BCDU
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function).
* @rmtoll RTC_ICSR BCDU LL_RTC_SetBinMixBCDU
* @param RTCx RTC Instance
* @param BinMixBcdU can be one of the following values:
* @arg @ref LL_RTC_BINARY_MIX_BCDU_0
* @arg @ref LL_RTC_BINARY_MIX_BCDU_1
* @arg @ref LL_RTC_BINARY_MIX_BCDU_2
* @arg @ref LL_RTC_BINARY_MIX_BCDU_3
* @arg @ref LL_RTC_BINARY_MIX_BCDU_4
* @arg @ref LL_RTC_BINARY_MIX_BCDU_5
* @arg @ref LL_RTC_BINARY_MIX_BCDU_6
* @arg @ref LL_RTC_BINARY_MIX_BCDU_7
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU)
{
MODIFY_REG(RTCx->ICSR, RTC_ICSR_BCDU, BinMixBcdU);
}
/**
* @brief Get Binary Mix mode BCDU
* @rmtoll RTC_ICSR BCDU LL_RTC_GetBinMixBCDU
* @param RTCx RTC Instance
* @retval This parameter can be one of the following values:
* @arg @ref LL_RTC_BINARY_MIX_BCDU_0
* @arg @ref LL_RTC_BINARY_MIX_BCDU_1
* @arg @ref LL_RTC_BINARY_MIX_BCDU_2
* @arg @ref LL_RTC_BINARY_MIX_BCDU_3
* @arg @ref LL_RTC_BINARY_MIX_BCDU_4
* @arg @ref LL_RTC_BINARY_MIX_BCDU_5
* @arg @ref LL_RTC_BINARY_MIX_BCDU_6
* @arg @ref LL_RTC_BINARY_MIX_BCDU_7
* @retval None
*/
__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BCDU));
}
/**
* @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR POL LL_RTC_SetOutputPolarity
* @param RTCx RTC Instance
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
* @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
{
MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
}
/**
* @brief Get Output polarity
* @rmtoll RTC_CR POL LL_RTC_GetOutputPolarity
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
* @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
*/
__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
}
/**
* @brief Enable Bypass the shadow registers
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
}
/**
* @brief Disable Bypass the shadow registers
* @rmtoll RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
}
/**
* @brief Check if Shadow registers bypass is enabled or not.
* @rmtoll RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U);
}
/**
* @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @rmtoll RTC_CR REFCKON LL_RTC_EnableRefClock
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_REFCKON);
}
/**
* @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @rmtoll RTC_CR REFCKON LL_RTC_DisableRefClock
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
}
/**
* @brief Set Asynchronous prescaler factor
* @rmtoll RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler
* @param RTCx RTC Instance
* @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
{
MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
}
/**
* @brief Set Synchronous prescaler factor
* @rmtoll RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler
* @param RTCx RTC Instance
* @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
{
MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
}
/**
* @brief Get Asynchronous prescaler factor
* @rmtoll RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler
* @param RTCx RTC Instance
* @retval Value between Min_Data = 0 and Max_Data = 0x7F
*/
__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
}
/**
* @brief Get Synchronous prescaler factor
* @rmtoll RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler
* @param RTCx RTC Instance
* @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
*/
__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
}
/**
* @brief Enable the write protection for RTC registers.
* @rmtoll RTC_WPR KEY LL_RTC_EnableWriteProtection
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
{
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
}
/**
* @brief Disable the write protection for RTC registers.
* @rmtoll RTC_WPR KEY LL_RTC_DisableWriteProtection
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
{
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
}
/**
* @brief Enable tamper output.
* @note When the tamper output is enabled, all external and internal tamper flags
* are ORed and routed to the TAMPALRM output.
* @rmtoll RTC_CR TAMPOE LL_RTC_EnableTamperOutput
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_TAMPOE);
}
/**
* @brief Disable tamper output.
* @rmtoll RTC_CR TAMPOE LL_RTC_DisableTamperOutput
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE);
}
/**
* @brief Check if tamper output is enabled or not.
* @rmtoll RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U);
}
/**
* @brief Enable internal pull-up in output mode.
* @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
}
/**
* @brief Disable internal pull-up in output mode.
* @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
}
/**
* @brief Check if internal pull-up in output mode is enabled or not.
* @rmtoll RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U);
}
/**
* @brief Enable RTC_OUT2 output
* @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent)
* and COE (@ref LL_RTC_CAL_SetOutputFreq) settings.
* @note RTC_OUT2 is not available ins VBAT mode.
* @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_OUT2EN);
}
/**
* @brief Disable RTC_OUT2 output
* @rmtoll RTC_CR OUT2EN LL_RTC_DisableOutput2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN);
}
/**
* @brief Check if RTC_OUT2 output is enabled or not.
* @rmtoll RTC_CR OUT2EN LL_RTC_IsOutput2Enabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Time Time
* @{
*/
/**
* @brief Set time format (AM/24-hour or PM notation)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @rmtoll RTC_TR PM LL_RTC_TIME_SetFormat
* @param RTCx RTC Instance
* @param TimeFormat This parameter can be one of the following values:
* @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
* @arg @ref LL_RTC_TIME_FORMAT_PM
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
{
MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
}
/**
* @brief Get time format (AM or PM notation)
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
* @rmtoll RTC_TR PM LL_RTC_TIME_GetFormat
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
* @arg @ref LL_RTC_TIME_FORMAT_PM
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
}
/**
* @brief Set Hours in BCD format
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
* @rmtoll RTC_TR HT LL_RTC_TIME_SetHour\n
* RTC_TR HU LL_RTC_TIME_SetHour
* @param RTCx RTC Instance
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
{
MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
(((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
}
/**
* @brief Get Hours in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
* Binary format
* @rmtoll RTC_TR HT LL_RTC_TIME_GetHour\n
* RTC_TR HU LL_RTC_TIME_GetHour
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
}
/**
* @brief Set Minutes in BCD format
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
* @rmtoll RTC_TR MNT LL_RTC_TIME_SetMinute\n
* RTC_TR MNU LL_RTC_TIME_SetMinute
* @param RTCx RTC Instance
* @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
{
MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
(((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
}
/**
* @brief Get Minutes in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
* to Binary format
* @rmtoll RTC_TR MNT LL_RTC_TIME_GetMinute\n
* RTC_TR MNU LL_RTC_TIME_GetMinute
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
}
/**
* @brief Set Seconds in BCD format
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
* @rmtoll RTC_TR ST LL_RTC_TIME_SetSecond\n
* RTC_TR SU LL_RTC_TIME_SetSecond
* @param RTCx RTC Instance
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
{
MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
(((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
}
/**
* @brief Get Seconds in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
* to Binary format
* @rmtoll RTC_TR ST LL_RTC_TIME_GetSecond\n
* RTC_TR SU LL_RTC_TIME_GetSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
}
/**
* @brief Set time (hour, minute and second) in BCD format
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @note TimeFormat and Hours should follow the same format
* @rmtoll RTC_TR PM LL_RTC_TIME_Config\n
* RTC_TR HT LL_RTC_TIME_Config\n
* RTC_TR HU LL_RTC_TIME_Config\n
* RTC_TR MNT LL_RTC_TIME_Config\n
* RTC_TR MNU LL_RTC_TIME_Config\n
* RTC_TR ST LL_RTC_TIME_Config\n
* RTC_TR SU LL_RTC_TIME_Config
* @param RTCx RTC Instance
* @param Format12_24 This parameter can be one of the following values:
* @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
* @arg @ref LL_RTC_TIME_FORMAT_PM
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
uint32_t Seconds)
{
uint32_t temp;
temp = Format12_24 | \
(((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
(((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
}
/**
* @brief Get time (hour, minute and second) in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
* @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
* are available to get independently each parameter.
* @rmtoll RTC_TR HT LL_RTC_TIME_Get\n
* RTC_TR HU LL_RTC_TIME_Get\n
* RTC_TR MNT LL_RTC_TIME_Get\n
* RTC_TR MNU LL_RTC_TIME_Get\n
* RTC_TR ST LL_RTC_TIME_Get\n
* RTC_TR SU LL_RTC_TIME_Get
* @param RTCx RTC Instance
* @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
{
uint32_t temp;
temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) \
<< RTC_OFFSET_HOUR) | (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | \
((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
}
/**
* @brief Memorize whether the daylight saving time change has been performed
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR BKP LL_RTC_TIME_EnableDayLightStore
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_BKP);
}
/**
* @brief Disable memorization whether the daylight saving time change has been performed.
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR BKP LL_RTC_TIME_DisableDayLightStore
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
}
/**
* @brief Check if RTC Day Light Saving stored operation has been enabled or not
* @rmtoll RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U);
}
/**
* @brief Subtract 1 hour (winter time change)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR SUB1H LL_RTC_TIME_DecHour
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_SUB1H);
}
/**
* @brief Add 1 hour (summer time change)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ADD1H LL_RTC_TIME_IncHour
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ADD1H);
}
/**
* @brief Get Sub second value in the synchronous prescaler counter.
* @note You can use both SubSeconds value and SecondFraction (PREDIV_S through
* LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
* SubSeconds value in second fraction ratio with time unit following
* generic formula:
* ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
* This conversion can be performed only if no shift operation is pending
* (ie. SHFP=0) when PREDIV_S >= SS.
* @rmtoll RTC_SSR SS LL_RTC_TIME_GetSubSecond
* @param RTCx RTC Instance
* @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
* else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
}
/**
* @brief Synchronize to a remote clock with a high degree of precision.
* @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note When REFCKON is set, firmware must not write to Shift control register.
* @rmtoll RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize\n
* RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize
* @param RTCx RTC Instance
* @param ShiftSecond This parameter can be one of the following values:
* @arg @ref LL_RTC_SHIFT_SECOND_DELAY
* @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
* @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
{
WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Date Date
* @{
*/
/**
* @brief Set Year in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
* @rmtoll RTC_DR YT LL_RTC_DATE_SetYear\n
* RTC_DR YU LL_RTC_DATE_SetYear
* @param RTCx RTC Instance
* @param Year Value between Min_Data=0x00 and Max_Data=0x99
* @retval None
*/
__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
{
MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
(((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
}
/**
* @brief Get Year in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
* @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n
* RTC_DR YU LL_RTC_DATE_GetYear
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x99
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
}
/**
* @brief Set Week day
* @rmtoll RTC_DR WDU LL_RTC_DATE_SetWeekDay
* @param RTCx RTC Instance
* @param WeekDay This parameter can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
* @retval None
*/
__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
{
MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
}
/**
* @brief Get Week day
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
}
/**
* @brief Set Month in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
* @rmtoll RTC_DR MT LL_RTC_DATE_SetMonth\n
* RTC_DR MU LL_RTC_DATE_SetMonth
* @param RTCx RTC Instance
* @param Month This parameter can be one of the following values:
* @arg @ref LL_RTC_MONTH_JANUARY
* @arg @ref LL_RTC_MONTH_FEBRUARY
* @arg @ref LL_RTC_MONTH_MARCH
* @arg @ref LL_RTC_MONTH_APRIL
* @arg @ref LL_RTC_MONTH_MAY
* @arg @ref LL_RTC_MONTH_JUNE
* @arg @ref LL_RTC_MONTH_JULY
* @arg @ref LL_RTC_MONTH_AUGUST
* @arg @ref LL_RTC_MONTH_SEPTEMBER
* @arg @ref LL_RTC_MONTH_OCTOBER
* @arg @ref LL_RTC_MONTH_NOVEMBER
* @arg @ref LL_RTC_MONTH_DECEMBER
* @retval None
*/
__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
{
MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
(((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
}
/**
* @brief Get Month in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
* @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n
* RTC_DR MU LL_RTC_DATE_GetMonth
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_MONTH_JANUARY
* @arg @ref LL_RTC_MONTH_FEBRUARY
* @arg @ref LL_RTC_MONTH_MARCH
* @arg @ref LL_RTC_MONTH_APRIL
* @arg @ref LL_RTC_MONTH_MAY
* @arg @ref LL_RTC_MONTH_JUNE
* @arg @ref LL_RTC_MONTH_JULY
* @arg @ref LL_RTC_MONTH_AUGUST
* @arg @ref LL_RTC_MONTH_SEPTEMBER
* @arg @ref LL_RTC_MONTH_OCTOBER
* @arg @ref LL_RTC_MONTH_NOVEMBER
* @arg @ref LL_RTC_MONTH_DECEMBER
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
}
/**
* @brief Set Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
* @rmtoll RTC_DR DT LL_RTC_DATE_SetDay\n
* RTC_DR DU LL_RTC_DATE_SetDay
* @param RTCx RTC Instance
* @param Day Value between Min_Data=0x01 and Max_Data=0x31
* @retval None
*/
__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
{
MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
(((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
}
/**
* @brief Get Day in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n
* RTC_DR DU LL_RTC_DATE_GetDay
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x31
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
}
/**
* @brief Set date (WeekDay, Day, Month and Year) in BCD format
* @rmtoll RTC_DR WDU LL_RTC_DATE_Config\n
* RTC_DR MT LL_RTC_DATE_Config\n
* RTC_DR MU LL_RTC_DATE_Config\n
* RTC_DR DT LL_RTC_DATE_Config\n
* RTC_DR DU LL_RTC_DATE_Config\n
* RTC_DR YT LL_RTC_DATE_Config\n
* RTC_DR YU LL_RTC_DATE_Config
* @param RTCx RTC Instance
* @param WeekDay This parameter can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
* @param Day Value between Min_Data=0x01 and Max_Data=0x31
* @param Month This parameter can be one of the following values:
* @arg @ref LL_RTC_MONTH_JANUARY
* @arg @ref LL_RTC_MONTH_FEBRUARY
* @arg @ref LL_RTC_MONTH_MARCH
* @arg @ref LL_RTC_MONTH_APRIL
* @arg @ref LL_RTC_MONTH_MAY
* @arg @ref LL_RTC_MONTH_JUNE
* @arg @ref LL_RTC_MONTH_JULY
* @arg @ref LL_RTC_MONTH_AUGUST
* @arg @ref LL_RTC_MONTH_SEPTEMBER
* @arg @ref LL_RTC_MONTH_OCTOBER
* @arg @ref LL_RTC_MONTH_NOVEMBER
* @arg @ref LL_RTC_MONTH_DECEMBER
* @param Year Value between Min_Data=0x00 and Max_Data=0x99
* @retval None
*/
__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month,
uint32_t Year)
{
uint32_t temp;
temp = (WeekDay << RTC_DR_WDU_Pos) | \
(((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
(((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
(((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
}
/**
* @brief Get date (WeekDay, Day, Month and Year) in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
* and __LL_RTC_GET_DAY are available to get independently each parameter.
* @rmtoll RTC_DR WDU LL_RTC_DATE_Get\n
* RTC_DR MT LL_RTC_DATE_Get\n
* RTC_DR MU LL_RTC_DATE_Get\n
* RTC_DR DT LL_RTC_DATE_Get\n
* RTC_DR DU LL_RTC_DATE_Get\n
* RTC_DR YT LL_RTC_DATE_Get\n
* RTC_DR YU LL_RTC_DATE_Get
* @param RTCx RTC Instance
* @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
{
uint32_t temp;
temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
(((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) \
<< RTC_OFFSET_DAY) | (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | \
((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_ALARMA ALARMA
* @{
*/
/**
* @brief Enable Alarm A
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Enable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ALRAE);
}
/**
* @brief Disable Alarm A
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Disable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
}
/**
* @brief Specify the Alarm A masks.
* @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask\n
* RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask\n
* RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask\n
* RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask
* @param RTCx RTC Instance
* @param Mask This parameter can be a combination of the following values:
* @arg @ref LL_RTC_ALMA_MASK_NONE
* @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
* @arg @ref LL_RTC_ALMA_MASK_HOURS
* @arg @ref LL_RTC_ALMA_MASK_MINUTES
* @arg @ref LL_RTC_ALMA_MASK_SECONDS
* @arg @ref LL_RTC_ALMA_MASK_ALL
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
}
/**
* @brief Get the Alarm A masks.
* @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask\n
* RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask\n
* RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask\n
* RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask
* @param RTCx RTC Instance
* @retval Returned value can be can be a combination of the following values:
* @arg @ref LL_RTC_ALMA_MASK_NONE
* @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
* @arg @ref LL_RTC_ALMA_MASK_HOURS
* @arg @ref LL_RTC_ALMA_MASK_MINUTES
* @arg @ref LL_RTC_ALMA_MASK_SECONDS
* @arg @ref LL_RTC_ALMA_MASK_ALL
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
}
/**
* @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
* @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
}
/**
* @brief Disable AlarmA Week day selection (DU[3:0] represents the date )
* @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
}
/**
* @brief Set ALARM A Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
* @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_SetDay\n
* RTC_ALRMAR DU LL_RTC_ALMA_SetDay
* @param RTCx RTC Instance
* @param Day Value between Min_Data=0x01 and Max_Data=0x31
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
{
MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
(((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
}
/**
* @brief Get ALARM A Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_GetDay\n
* RTC_ALRMAR DU LL_RTC_ALMA_GetDay
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x31
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
}
/**
* @brief Set ALARM A Weekday
* @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay
* @param RTCx RTC Instance
* @param WeekDay This parameter can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
{
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
}
/**
* @brief Get ALARM A Weekday
* @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
}
/**
* @brief Set Alarm A time format (AM/24-hour or PM notation)
* @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat
* @param RTCx RTC Instance
* @param TimeFormat This parameter can be one of the following values:
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
{
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
}
/**
* @brief Get Alarm A time format (AM or PM notation)
* @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
}
/**
* @brief Set ALARM A Hours in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
* @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_SetHour\n
* RTC_ALRMAR HU LL_RTC_ALMA_SetHour
* @param RTCx RTC Instance
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
{
MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
(((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
}
/**
* @brief Get ALARM A Hours in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
* @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetHour\n
* RTC_ALRMAR HU LL_RTC_ALMA_GetHour
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
}
/**
* @brief Set ALARM A Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
* @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute\n
* RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute
* @param RTCx RTC Instance
* @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
{
MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
}
/**
* @brief Get ALARM A Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
* @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute\n
* RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
}
/**
* @brief Set ALARM A Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
* @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_SetSecond\n
* RTC_ALRMAR SU LL_RTC_ALMA_SetSecond
* @param RTCx RTC Instance
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
{
MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
(((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
}
/**
* @brief Get ALARM A Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
* @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_GetSecond\n
* RTC_ALRMAR SU LL_RTC_ALMA_GetSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
}
/**
* @brief Set Alarm A Time (hour, minute and second) in BCD format
* @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime
* @param RTCx RTC Instance
* @param Format12_24 This parameter can be one of the following values:
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
uint32_t Seconds)
{
uint32_t temp;
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
(((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | \
RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
}
/**
* @brief Get Alarm B Time (hour, minute and second) in BCD format
* @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
* are available to get independently each parameter.
* @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetTime\n
* RTC_ALRMAR HU LL_RTC_ALMA_GetTime\n
* RTC_ALRMAR MNT LL_RTC_ALMA_GetTime\n
* RTC_ALRMAR MNU LL_RTC_ALMA_GetTime\n
* RTC_ALRMAR ST LL_RTC_ALMA_GetTime\n
* RTC_ALRMAR SU LL_RTC_ALMA_GetTime
* @param RTCx RTC Instance
* @retval Combination of hours, minutes and seconds.
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
{
return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << \
RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
}
/**
* @brief Set Alarm A Mask the most-significant bits starting at this bit
* @note This register can be written only when ALRAE is reset in RTC_CR register,
* or in initialization mode.
* @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
* @param RTCx RTC Instance
* @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
* else Value between Min_Data=0x0 and Max_Data=0x3F
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
}
/**
* @brief Get Alarm A Mask the most-significant bits starting at this bit
* @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
* @param RTCx RTC Instance
* @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
* else Value between Min_Data=0x0 and Max_Data=0x3F
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
}
/**
* @brief Set Alarm A Binary mode auto clear
* @note This register can be written only when ALRAE is reset in RTC_CR register,
* or in initialization mode.
* @rmtoll RTC_ALRABINR SSCLR LL_RTC_ALMA_SetBinAutoClr
* @param RTCx RTC Instance
* @param BinaryAutoClr This parameter can be one of the following values:
* @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO
* @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr)
{
MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR, BinaryAutoClr);
}
/**
* @brief Get Alarm A Binary mode auto clear
* @rmtoll RTC_ALRABINR SSCLR LL_RTC_ALMA_GetBinAutoClr
* @param RTCx RTC Instance
* @retval It can be one of the following values:
* @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO
* @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR));
}
/**
* @brief Set Alarm A Sub seconds value
* @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond
* @param RTCx RTC Instance
* @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
* else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
{
MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
}
/**
* @brief Get Alarm A Sub seconds value
* @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond
* @param RTCx RTC Instance
* @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
* else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_ALARMB ALARMB
* @{
*/
/**
* @brief Enable Alarm B
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Enable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ALRBE);
}
/**
* @brief Disable Alarm B
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Disable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
}
/**
* @brief Specify the Alarm B masks.
* @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask\n
* RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask\n
* RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask\n
* RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask
* @param RTCx RTC Instance
* @param Mask This parameter can be a combination of the following values:
* @arg @ref LL_RTC_ALMB_MASK_NONE
* @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
* @arg @ref LL_RTC_ALMB_MASK_HOURS
* @arg @ref LL_RTC_ALMB_MASK_MINUTES
* @arg @ref LL_RTC_ALMB_MASK_SECONDS
* @arg @ref LL_RTC_ALMB_MASK_ALL
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
}
/**
* @brief Get the Alarm B masks.
* @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask\n
* RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask\n
* RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask\n
* RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask
* @param RTCx RTC Instance
* @retval Returned value can be can be a combination of the following values:
* @arg @ref LL_RTC_ALMB_MASK_NONE
* @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
* @arg @ref LL_RTC_ALMB_MASK_HOURS
* @arg @ref LL_RTC_ALMB_MASK_MINUTES
* @arg @ref LL_RTC_ALMB_MASK_SECONDS
* @arg @ref LL_RTC_ALMB_MASK_ALL
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
}
/**
* @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
* @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
}
/**
* @brief Disable AlarmB Week day selection (DU[3:0] represents the date )
* @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
}
/**
* @brief Set ALARM B Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
* @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_SetDay\n
* RTC_ALRMBR DU LL_RTC_ALMB_SetDay
* @param RTCx RTC Instance
* @param Day Value between Min_Data=0x01 and Max_Data=0x31
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
{
MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
(((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
}
/**
* @brief Get ALARM B Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_GetDay\n
* RTC_ALRMBR DU LL_RTC_ALMB_GetDay
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x31
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
}
/**
* @brief Set ALARM B Weekday
* @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay
* @param RTCx RTC Instance
* @param WeekDay This parameter can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
{
MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
}
/**
* @brief Get ALARM B Weekday
* @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
}
/**
* @brief Set ALARM B time format (AM/24-hour or PM notation)
* @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat
* @param RTCx RTC Instance
* @param TimeFormat This parameter can be one of the following values:
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
{
MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
}
/**
* @brief Get ALARM B time format (AM or PM notation)
* @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
}
/**
* @brief Set ALARM B Hours in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
* @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_SetHour\n
* RTC_ALRMBR HU LL_RTC_ALMB_SetHour
* @param RTCx RTC Instance
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
{
MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
(((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
}
/**
* @brief Get ALARM B Hours in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
* @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetHour\n
* RTC_ALRMBR HU LL_RTC_ALMB_GetHour
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
}
/**
* @brief Set ALARM B Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
* @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute\n
* RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute
* @param RTCx RTC Instance
* @param Minutes between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
{
MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
(((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
}
/**
* @brief Get ALARM B Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
* @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute\n
* RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
}
/**
* @brief Set ALARM B Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
* @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_SetSecond\n
* RTC_ALRMBR SU LL_RTC_ALMB_SetSecond
* @param RTCx RTC Instance
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
{
MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
(((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
}
/**
* @brief Get ALARM B Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
* @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_GetSecond\n
* RTC_ALRMBR SU LL_RTC_ALMB_GetSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
}
/**
* @brief Set Alarm B Time (hour, minute and second) in BCD format
* @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime
* @param RTCx RTC Instance
* @param Format12_24 This parameter can be one of the following values:
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
uint32_t Seconds)
{
uint32_t temp;
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
(((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | \
RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
}
/**
* @brief Get Alarm B Time (hour, minute and second) in BCD format
* @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
* are available to get independently each parameter.
* @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetTime\n
* RTC_ALRMBR HU LL_RTC_ALMB_GetTime\n
* RTC_ALRMBR MNT LL_RTC_ALMB_GetTime\n
* RTC_ALRMBR MNU LL_RTC_ALMB_GetTime\n
* RTC_ALRMBR ST LL_RTC_ALMB_GetTime\n
* RTC_ALRMBR SU LL_RTC_ALMB_GetTime
* @param RTCx RTC Instance
* @retval Combination of hours, minutes and seconds.
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
{
return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << \
RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
}
/**
* @brief Set Alarm B Mask the most-significant bits starting at this bit
* @note This register can be written only when ALRBE is reset in RTC_CR register,
* or in initialization mode.
* @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
* @param RTCx RTC Instance
* @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
* else Value between Min_Data=0x0 and Max_Data=0x3F
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
}
/**
* @brief Get Alarm B Mask the most-significant bits starting at this bit
* @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
* @param RTCx RTC Instance
* @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF
* else Value between Min_Data=0x0 and Max_Data=0x3F
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos);
}
/**
* @brief Set Alarm B Binary mode auto clear
* @note This register can be written only when ALRBE is reset in RTC_CR register,
* or in initialization mode.
* @rmtoll RTC_ALRBBINR SSCLR LL_RTC_ALMB_SetBinAutoClr
* @param RTCx RTC Instance
* @param BinaryAutoClr This parameter can be one of the following values:
* @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO
* @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr)
{
MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR, BinaryAutoClr);
}
/**
* @brief Get Alarm B Binary mode auto clear
* @rmtoll RTC_ALRBBINR SSCLR LL_RTC_ALMB_GetBinAutoClr
* @param RTCx RTC Instance
* @retval It can be one of the following values:
* @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO
* @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR));
}
/**
* @brief Set Alarm B Sub seconds value
* @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
* @param RTCx RTC Instance
* @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
* else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
{
MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
}
/**
* @brief Get Alarm B Sub seconds value
* @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
* @param RTCx RTC Instance
* @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
* else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Timestamp Timestamp
* @{
*/
/**
* @brief Enable internal event timestamp
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ITSE LL_RTC_TS_EnableInternalEvent
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ITSE);
}
/**
* @brief Disable internal event timestamp
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ITSE LL_RTC_TS_DisableInternalEvent
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
}
/**
* @brief Enable Timestamp
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR TSE LL_RTC_TS_Enable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_TSE);
}
/**
* @brief Disable Timestamp
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR TSE LL_RTC_TS_Disable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
}
/**
* @brief Set Time-stamp event active edge
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
* @rmtoll RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge
* @param RTCx RTC Instance
* @param Edge This parameter can be one of the following values:
* @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
* @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
{
MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
}
/**
* @brief Get Time-stamp event active edge
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
* @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
}
/**
* @brief Get Timestamp AM/PM notation (AM or 24-hour format)
* @rmtoll RTC_TSTR PM LL_RTC_TS_GetTimeFormat
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TS_TIME_FORMAT_AM
* @arg @ref LL_RTC_TS_TIME_FORMAT_PM
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
}
/**
* @brief Get Timestamp Hours in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
* @rmtoll RTC_TSTR HT LL_RTC_TS_GetHour\n
* RTC_TSTR HU LL_RTC_TS_GetHour
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
}
/**
* @brief Get Timestamp Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
* @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n
* RTC_TSTR MNU LL_RTC_TS_GetMinute
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
}
/**
* @brief Get Timestamp Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
* @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n
* RTC_TSTR SU LL_RTC_TS_GetSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
}
/**
* @brief Get Timestamp time (hour, minute and second) in BCD format
* @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
* are available to get independently each parameter.
* @rmtoll RTC_TSTR HT LL_RTC_TS_GetTime\n
* RTC_TSTR HU LL_RTC_TS_GetTime\n
* RTC_TSTR MNT LL_RTC_TS_GetTime\n
* RTC_TSTR MNU LL_RTC_TS_GetTime\n
* RTC_TSTR ST LL_RTC_TS_GetTime\n
* RTC_TSTR SU LL_RTC_TS_GetTime
* @param RTCx RTC Instance
* @retval Combination of hours, minutes and seconds.
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSTR,
RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
}
/**
* @brief Get Timestamp Week day
* @rmtoll RTC_TSDR WDU LL_RTC_TS_GetWeekDay
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
}
/**
* @brief Get Timestamp Month in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
* @rmtoll RTC_TSDR MT LL_RTC_TS_GetMonth\n
* RTC_TSDR MU LL_RTC_TS_GetMonth
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_MONTH_JANUARY
* @arg @ref LL_RTC_MONTH_FEBRUARY
* @arg @ref LL_RTC_MONTH_MARCH
* @arg @ref LL_RTC_MONTH_APRIL
* @arg @ref LL_RTC_MONTH_MAY
* @arg @ref LL_RTC_MONTH_JUNE
* @arg @ref LL_RTC_MONTH_JULY
* @arg @ref LL_RTC_MONTH_AUGUST
* @arg @ref LL_RTC_MONTH_SEPTEMBER
* @arg @ref LL_RTC_MONTH_OCTOBER
* @arg @ref LL_RTC_MONTH_NOVEMBER
* @arg @ref LL_RTC_MONTH_DECEMBER
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
}
/**
* @brief Get Timestamp Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll RTC_TSDR DT LL_RTC_TS_GetDay\n
* RTC_TSDR DU LL_RTC_TS_GetDay
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x31
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
}
/**
* @brief Get Timestamp date (WeekDay, Day and Month) in BCD format
* @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
* and __LL_RTC_GET_DAY are available to get independently each parameter.
* @rmtoll RTC_TSDR WDU LL_RTC_TS_GetDate\n
* RTC_TSDR MT LL_RTC_TS_GetDate\n
* RTC_TSDR MU LL_RTC_TS_GetDate\n
* RTC_TSDR DT LL_RTC_TS_GetDate\n
* RTC_TSDR DU LL_RTC_TS_GetDate
* @param RTCx RTC Instance
* @retval Combination of Weekday, Day and Month
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
}
/**
* @brief Get time-stamp sub second value
* @rmtoll RTC_TSDR SS LL_RTC_TS_GetSubSecond
* @param RTCx RTC Instance
* @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF
* else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
}
/**
* @brief Activate timestamp on tamper detection event
* @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_TAMPTS);
}
/**
* @brief Disable timestamp on tamper detection event
* @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Tamper Tamper
* @{
*/
/**
* @brief Enable TAMPx input detection
* @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable\n
* TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Enable\n
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_TAMPER
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
SET_BIT(TAMP->CR1, Tamper);
}
/**
* @brief Clear TAMPx input detection
* @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable\n
* TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Disable
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_TAMPER
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->CR1, Tamper);
}
/**
* @brief Enable Tamper mask flag
* @note Associated Tamper IT must not enabled when tamper mask is set.
* @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask\n
* TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_EnableMask
* @param RTCx RTC Instance
* @param Mask This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_TAMPER_MASK
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
UNUSED(RTCx);
SET_BIT(TAMP->CR2, Mask);
}
/**
* @brief Disable Tamper mask flag
* @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask\n
* TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_DisableMask
* @param RTCx RTC Instance
* @param Mask This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_TAMPER_MASK
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->CR2, Mask);
}
/**
* @brief Enable backup register erase after Tamper event detection
* @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP\n
* TAMP_CR2 TAMP2NOERASE... LL_RTC_TAMPER_EnableEraseBKP
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_TAMPER_NOERASE
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->CR2, Tamper);
}
/**
* @brief Disable backup register erase after Tamper event detection
* @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP\n
* TAMP_CR2 TAMP2NOERASE... LL_RTC_TAMPER_DisableEraseBKP
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_TAMPER_NOERASE
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
SET_BIT(TAMP->CR2, Tamper);
}
/**
* @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
* @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS);
}
/**
* @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
* @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS);
}
/**
* @brief Set RTC_TAMPx precharge duration
* @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
* @param RTCx RTC Instance
* @param Duration This parameter can be one of the following values:
* @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
{
UNUSED(RTCx);
MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);
}
/**
* @brief Get RTC_TAMPx precharge duration
* @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
*/
__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH));
}
/**
* @brief Set RTC_TAMPx filter count
* @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
* @param RTCx RTC Instance
* @param FilterCount This parameter can be one of the following values:
* @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
* @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
* @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
* @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
{
UNUSED(RTCx);
MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);
}
/**
* @brief Get RTC_TAMPx filter count
* @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
* @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
* @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
* @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
*/
__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT));
}
/**
* @brief Set Tamper sampling frequency
* @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
* @param RTCx RTC Instance
* @param SamplingFreq This parameter can be one of the following values:
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
{
UNUSED(RTCx);
MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);
}
/**
* @brief Get Tamper sampling frequency
* @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
*/
__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ));
}
/**
* @brief Enable Active level for Tamper input
* @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n
* TAMP_CR2 TAMP2TRG... LL_RTC_TAMPER_EnableActiveLevel
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
SET_BIT(TAMP->CR2, Tamper);
}
/**
* @brief Disable Active level for Tamper input
* @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n
* TAMP_CR2 TAMP2TRG... LL_RTC_TAMPER_DisableActiveLevel
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->CR2, Tamper);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Internal_Tamper Internal Tamper
* @{
*/
/**
* @brief Enable internal tamper detection.
* @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Enable\n
* TAMP_CR1 ITAMP2E.. LL_RTC_TAMPER_ITAMP_Enable\n
* @param RTCx RTC Instance
* @param InternalTamper This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_INTERNAL
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t InternalTamper)
{
UNUSED(RTCx);
SET_BIT(TAMP->CR1, InternalTamper);
}
/**
* @brief Disable internal tamper detection.
* @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Disable\n
* TAMP_CR1 ITAMP2E LL_RTC_TAMPER_ITAMP_Disable\n
* TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Disable\n
* TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Disable\n
* TAMP_CR1 ITAMP8E LL_RTC_TAMPER_ITAMP_Disable
* @param RTCx RTC Instance
* @param InternalTamper This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_INTERNAL
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef *RTCx, uint32_t InternalTamper)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->CR1, InternalTamper);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Active_Tamper Active Tamper
* @{
*/
/**
* @brief Enable tamper active mode.
* @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n
* @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n
* @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n
* @param Tamper to configure as active. This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_ACTIVE_MODE
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper)
{
SET_BIT(TAMP->ATCR1, Tamper);
}
/**
* @brief Disable tamper active mode.
* @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n
* @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n
* @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n
* @param Tamper to configure as active. This parameter can be a combination of the following values:
* @arg @ref RTC_LL_EC_ACTIVE_MODE
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper)
{
CLEAR_BIT(TAMP->ATCR1, Tamper);
}
/**
* @brief Enable active tamper filter.
* @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_EnableFilter\n
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter(void)
{
SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
}
/**
* @brief Disable active tamper filter.
* @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_DisableFilter\n
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter(void)
{
CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);
}
/**
* @brief Set Active tamper output change period.
* @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod\n
* @param ActiveOutputChangePeriod This parameter can be a value from 0 to 7
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod)
{
MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos));
}
/**
* @brief Get Active tamper output change period.
* @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod\n
* @retval Output change period. This parameter can be a value from 0 to 7.
*/
__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(void)
{
return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos);
}
/**
* @brief Set Active tamper asynchronous prescaler clock selection.
* @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler\n
* @param ActiveAsynvPrescaler Specifies the Active Tamper asynchronous Prescaler clock.
This parameter can be a value of the following values:
* @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler)
{
MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler);
}
/**
* @brief Get Active tamper asynchronous prescaler clock selection.
* @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler\n
* @retval One of @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER
*/
__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(void)
{
return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL));
}
/**
* @brief Enable active tamper output sharing.
* @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_EnableOutputSharing\n
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(void)
{
SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
}
/**
* @brief Disable active tamper output sharing.
* @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_DisableOutputSharing\n
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(void)
{
CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);
}
/**
* @brief Set Active tamper output selection.
* @rmtoll TAMP_ATCR2 ATCKSEL LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection\n
* @param OutputSelection Specifies all the output selection of the Active Tamper.
This parameter is a combinasation of the following values:
* One of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection)
{
MODIFY_REG(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 | \
TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6 | TAMP_ATCR2_ATOSEL7 | TAMP_ATCR2_ATOSEL8), \
OutputSelection);
}
/**
* @brief Get Active tamper asynchronous prescaler clock selection.
* @rmtoll TAMP_ATCR2 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler\n
* @retval A combination of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION
*/
__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void)
{
return (READ_BIT(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 | \
TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6 | TAMP_ATCR2_ATOSEL7 | TAMP_ATCR2_ATOSEL8)));
}
/**
* @brief Write active tamper seed.
* @rmtoll TAMP_ATSEEDR SEED LL_RTC_TAMPER_ATAMP_WriteSeed\n
* @param Seed
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed)
{
WRITE_REG(TAMP->ATSEEDR, Seed);
}
/**
* @brief Get active tamper initialization status flag.
* @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(void)
{
return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U);
}
/**
* @brief Get active tamper seed running status flag.
* @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void)
{
return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Wakeup Wakeup
* @{
*/
/**
* @brief Enable Wakeup timer
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Enable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_WUTE);
}
/**
* @brief Disable Wakeup timer
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Disable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
}
/**
* @brief Check if Wakeup timer is enabled or not
* @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U);
}
/**
* @brief Select Wakeup clock
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1
* @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock
* @param RTCx RTC Instance
* @param WakeupClock This parameter can be one of the following values:
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
* @retval None
*/
__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
{
MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
}
/**
* @brief Get Wakeup clock
* @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
*/
__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
}
/**
* @brief Set Wakeup auto-reload value
* @note Bit can be written only when WUTWF is set to 1 in RTC_ICSR
* @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload
* @param RTCx RTC Instance
* @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
{
MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
}
/**
* @brief Get Wakeup auto-reload value
* @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
* @{
*/
/**
* @brief Writes a data in a specified Backup data register.
* @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister
* @param RTCx RTC Instance
* @param BackupRegister This parameter can be one of the following values:
* @arg @ref LL_RTC_BKP_DR0
* @arg @ref LL_RTC_BKP_DR1
* @arg @ref LL_RTC_BKP_DR2
* @arg @ref LL_RTC_BKP_DR3
* @arg @ref LL_RTC_BKP_DR4 ...
* @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
{
__IO uint32_t tmp;
UNUSED(RTCx);
tmp = (uint32_t)(&(TAMP->BKP0R));
tmp += (BackupRegister * 4U);
/* Write the specified register */
*(__IO uint32_t *)tmp = (uint32_t)Data;
}
/**
* @brief Reads data from the specified RTC Backup data Register.
* @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_GetRegister
* @param RTCx RTC Instance
* @param BackupRegister This parameter can be one of the following values:
* @arg @ref LL_RTC_BKP_DR0
* @arg @ref LL_RTC_BKP_DR1
* @arg @ref LL_RTC_BKP_DR2
* @arg @ref LL_RTC_BKP_DR3
* @arg @ref LL_RTC_BKP_DR4 ...
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
{
uint32_t tmp;
UNUSED(RTCx);
tmp = (uint32_t)(&(TAMP->BKP0R));
tmp += (BackupRegister * 4U);
/* Read the specified register */
return (*(__IO uint32_t *)tmp);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Calibration Calibration
* @{
*/
/**
* @brief Set Calibration output frequency (1 Hz or 512 Hz)
* @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR COE LL_RTC_CAL_SetOutputFreq\n
* RTC_CR COSEL LL_RTC_CAL_SetOutputFreq
* @param RTCx RTC Instance
* @param Frequency This parameter can be one of the following values:
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
* @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
* @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
{
MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
}
/**
* @brief Get Calibration output frequency (1 Hz or 512 Hz)
* @rmtoll RTC_CR COE LL_RTC_CAL_GetOutputFreq\n
* RTC_CR COSEL LL_RTC_CAL_GetOutputFreq
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
* @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
* @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
}
/**
* @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
* @rmtoll RTC_CALR CALP LL_RTC_CAL_SetPulse
* @param RTCx RTC Instance
* @param Pulse This parameter can be one of the following values:
* @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
* @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
{
MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
}
/**
* @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
* @rmtoll RTC_CALR CALP LL_RTC_CAL_IsPulseInserted
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U);
}
/**
* @brief Set the calibration cycle period
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
* @rmtoll RTC_CALR CALW8 LL_RTC_CAL_SetPeriod\n
* RTC_CALR CALW16 LL_RTC_CAL_SetPeriod
* @param RTCx RTC Instance
* @param Period This parameter can be one of the following values:
* @arg @ref LL_RTC_CALIB_PERIOD_32SEC
* @arg @ref LL_RTC_CALIB_PERIOD_16SEC
* @arg @ref LL_RTC_CALIB_PERIOD_8SEC
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
{
MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
}
/**
* @brief Get the calibration cycle period
* @rmtoll RTC_CALR CALW8 LL_RTC_CAL_GetPeriod\n
* RTC_CALR CALW16 LL_RTC_CAL_GetPeriod
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_CALIB_PERIOD_32SEC
* @arg @ref LL_RTC_CALIB_PERIOD_16SEC
* @arg @ref LL_RTC_CALIB_PERIOD_8SEC
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
}
/**
* @brief Set Calibration minus
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
* @rmtoll RTC_CALR CALM LL_RTC_CAL_SetMinus
* @param RTCx RTC Instance
* @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
{
MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
}
/**
* @brief Get Calibration minus
* @rmtoll RTC_CALR CALM LL_RTC_CAL_GetMinus
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
}
/**
* @brief Enable Calibration Low Power
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0
* @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Enable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_LowPower_Enable(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CALR, RTC_CALR_LPCAL);
}
/**
* @brief Disable Calibration Low Power
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0
* @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Disable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CALR, RTC_CALR_LPCAL);
}
/**
* @brief Check if Calibration Low Power is enabled or not
* @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_IsEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)) ? 1U : 0U);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Get Internal Time-stamp flag
* @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U);
}
/**
* @brief Get Recalibration pending Flag
* @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U);
}
/**
* @brief Get Time-stamp overflow flag
* @rmtoll RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U);
}
/**
* @brief Get Time-stamp flag
* @rmtoll RTC_SR TSF LL_RTC_IsActiveFlag_TS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U);
}
/**
* @brief Get Wakeup timer flag
* @rmtoll RTC_SR WUTF LL_RTC_IsActiveFlag_WUT
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U);
}
/**
* @brief Get Alarm B flag
* @rmtoll RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U);
}
/**
* @brief Get Alarm A flag
* @rmtoll RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U);
}
/**
* @brief Get SSR Underflow flag
* @rmtoll RTC_SR SSRUF LL_RTC_IsActiveFlag_SSRU
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_SSRUF) == (RTC_SR_SSRUF)) ? 1U : 0U);
}
/**
* @brief Clear Internal Time-stamp flag
* @rmtoll RTC_SCR CITSF LL_RTC_ClearFlag_ITS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
{
WRITE_REG(RTCx->SCR, RTC_SCR_CITSF);
}
/**
* @brief Clear Time-stamp overflow flag
* @rmtoll RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF);
}
/**
* @brief Clear Time-stamp flag
* @rmtoll RTC_SCR CTSF LL_RTC_ClearFlag_TS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->SCR, RTC_SCR_CTSF);
}
/**
* @brief Clear Wakeup timer flag
* @rmtoll RTC_SCR CWUTF LL_RTC_ClearFlag_WUT
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->SCR, RTC_SCR_CWUTF);
}
/**
* @brief Clear Alarm B flag
* @rmtoll RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->SCR, RTC_SCR_CALRBF);
}
/**
* @brief Clear Alarm A flag
* @rmtoll RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
{
WRITE_REG(RTCx->SCR, RTC_SCR_CALRAF);
}
/**
* @brief Clear SSR Underflow flag
* @rmtoll RTC_SCR CSSRUF LL_RTC_ClearFlag_SSRU
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_SSRU(RTC_TypeDef *RTCx)
{
WRITE_REG(RTCx->SCR, RTC_SCR_CSSRUF);
}
/**
* @brief Get Initialization flag
* @rmtoll RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U);
}
/**
* @brief Get Registers synchronization flag
* @rmtoll RTC_ICSR RSF LL_RTC_IsActiveFlag_RS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U);
}
/**
* @brief Clear Registers synchronization flag
* @rmtoll RTC_ICSR RSF LL_RTC_ClearFlag_RS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
{
WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT)));
}
/**
* @brief Get Initialization status flag
* @rmtoll RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U);
}
/**
* @brief Get Shift operation pending flag
* @rmtoll RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U);
}
/**
* @brief Get Wakeup timer write flag
* @rmtoll RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U);
}
/**
* @brief Get Alarm A masked flag.
* @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U);
}
/**
* @brief Get SSR Underflow masked flag.
* @rmtoll RTC_MISR SSRUMF LL_RTC_IsActiveFlag_SSRUM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_SSRUMF) == (RTC_MISR_SSRUMF)) ? 1U : 0U);
}
/**
* @brief Get Alarm B masked flag.
* @rmtoll RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U);
}
/**
* @brief Get Wakeup timer masked flag.
* @rmtoll RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U);
}
/**
* @brief Get Time-stamp masked flag.
* @rmtoll RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U);
}
/**
* @brief Get Time-stamp overflow masked flag.
* @rmtoll RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U);
}
/**
* @brief Get Internal Time-stamp masked flag.
* @rmtoll RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U);
}
/**
* @brief Get tamper 1 detection flag.
* @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U);
}
/**
* @brief Get tamper 2 detection flag.
* @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U);
}
/**
* @brief Get tamper 3 detection flag.
* @rmtoll TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U);
}
/**
* @brief Get tamper 4 detection flag.
* @rmtoll TAMP_SR TAMP4F LL_RTC_IsActiveFlag_TAMP4
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U);
}
/**
* @brief Get tamper 5 detection flag.
* @rmtoll TAMP_SR TAMP5F LL_RTC_IsActiveFlag_TAMP5
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U);
}
/**
* @brief Get tamper 6 detection flag.
* @rmtoll TAMP_SR TAMP6F LL_RTC_IsActiveFlag_TAMP6
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U);
}
/**
* @brief Get tamper 7 detection flag.
* @rmtoll TAMP_SR TAMP7F LL_RTC_IsActiveFlag_TAMP7
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP7F) == (TAMP_SR_TAMP7F)) ? 1U : 0U);
}
/**
* @brief Get tamper 8 detection flag.
* @rmtoll TAMP_SR TAMP8F LL_RTC_IsActiveFlag_TAMP8
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP8F) == (TAMP_SR_TAMP8F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 1 detection flag.
* @rmtoll TAMP_SR ITAMP1F LL_RTC_IsActiveFlag_ITAMP1
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP1F) == (TAMP_SR_ITAMP1F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 2 detection flag.
* @rmtoll TAMP_SR ITAMP2F LL_RTC_IsActiveFlag_ITAMP2
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP2F) == (TAMP_SR_ITAMP2F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 3 detection flag.
* @rmtoll TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP3
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 5 detection flag.
* @rmtoll TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP5
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 6 detection flag.
* @rmtoll TAMP_SR ITAMP6F LL_RTC_IsActiveFlag_ITAMP6
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 7 detection flag.
* @rmtoll TAMP_SR ITAMP7F LL_RTC_IsActiveFlag_ITAMP7
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP7F) == (TAMP_SR_ITAMP7F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 8 detection flag.
* @rmtoll TAMP_SR ITAMP8F LL_RTC_IsActiveFlag_ITAMP8
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 9 detection flag.
* @rmtoll TAMP_SR ITAMP9F LL_RTC_IsActiveFlag_ITAMP9
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP9F) == (TAMP_SR_ITAMP9F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 11 detection flag.
* @rmtoll TAMP_SR ITAMP11F LL_RTC_IsActiveFlag_ITAMP11
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP11F) == (TAMP_SR_ITAMP11F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 12 detection flag.
* @rmtoll TAMP_SR ITAMP12F LL_RTC_IsActiveFlag_ITAMP12
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP12(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP12F) == (TAMP_SR_ITAMP12F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 13 detection flag.
* @rmtoll TAMP_SR ITAMP13F LL_RTC_IsActiveFlag_ITAMP13
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP13(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP13F) == (TAMP_SR_ITAMP13F)) ? 1U : 0U);
}
/**
* @brief Get tamper 1 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 2 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 3 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 4 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP4MF LL_RTC_IsActiveFlag_TAMP4M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 5 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP5MF LL_RTC_IsActiveFlag_TAMP5M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 6 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP6M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 7 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP7MF LL_RTC_IsActiveFlag_TAMP7M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP7MF) == (TAMP_MISR_TAMP7MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 8 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP8MF LL_RTC_IsActiveFlag_TAMP8M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP8MF) == (TAMP_MISR_TAMP8MF)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 1 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP1MF LL_RTC_IsActiveFlag_ITAMP1M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP1MF) == (TAMP_MISR_ITAMP1MF)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 2 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP2MF LL_RTC_IsActiveFlag_ITAMP2M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP2MF) == (TAMP_MISR_ITAMP2MF)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 3 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP3MF LL_RTC_IsActiveFlag_ITAMP3M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 5 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP5MF LL_RTC_IsActiveFlag_ITAMP5M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 8 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP8MF LL_RTC_IsActiveFlag_ITAMP8M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U);
}
/**
* @brief Clear tamper 1 detection flag.
* @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP1F);
}
/**
* @brief Clear tamper 2 detection flag.
* @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP2F);
}
/**
* @brief Clear tamper 3 detection flag.
* @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP3F);
}
/**
* @brief Clear tamper 4 detection flag.
* @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP4
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP4F);
}
/**
* @brief Clear tamper 5 detection flag.
* @rmtoll TAMP_SCR CTAMP5F LL_RTC_ClearFlag_TAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP5F);
}
/**
* @brief Clear tamper 6 detection flag.
* @rmtoll TAMP_SCR CTAMP6F LL_RTC_ClearFlag_TAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP6F);
}
/**
* @brief Clear tamper 7 detection flag.
* @rmtoll TAMP_SCR CTAMP7F LL_RTC_ClearFlag_TAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP7F);
}
/**
* @brief Clear tamper 8 detection flag.
* @rmtoll TAMP_SCR CTAMP8F LL_RTC_ClearFlag_TAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP8F);
}
/**
* @brief Clear internal tamper 1 detection flag.
* @rmtoll TAMP_SCR CITAMP1F LL_RTC_ClearFlag_ITAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP1F);
}
/**
* @brief Clear internal tamper 2 detection flag.
* @rmtoll TAMP_SCR CITAMP2F LL_RTC_ClearFlag_ITAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP2F);
}
/**
* @brief Clear internal tamper 3 detection flag.
* @rmtoll TAMP_SCR CITAMP3F LL_RTC_ClearFlag_ITAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP3F);
}
/**
* @brief Clear internal tamper 5 detection flag.
* @rmtoll TAMP_SCR CITAMP5F LL_RTC_ClearFlag_ITAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP5F);
}
/**
* @brief Clear internal tamper 8 detection flag.
* @rmtoll TAMP_SCR CITAMP8F LL_RTC_ClearFlag_ITAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP8F);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_SECURITY SECURITY_Management
* @{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Set RTC secure level.
* @note secure features are relevant if LL_RTC_SECURE_FULL_NO.
* @rmtoll RTC_SECCFGR SEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR INITSEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR CALSEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR TSSEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR WUTSEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR ALRASEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR ALRBSEC LL_RTC_SetRtcSecure
* @param RTCx RTC Instance
* @param rtcSecure This parameter can be a combination of the following values:
* @arg @ref LL_RTC_SECURE_FULL_YES
* @arg @ref LL_RTC_SECURE_FULL_NO
* @arg @ref LL_RTC_UNSECURE_FEATURE_INIT
* @arg @ref LL_RTC_UNSECURE_FEATURE_CAL
* @arg @ref LL_RTC_UNSECURE_FEATURE_TS
* @arg @ref LL_RTC_UNSECURE_FEATURE_WUT
* @arg @ref LL_RTC_UNSECURE_FEATURE_ALRA
* @arg @ref LL_RTC_UNSECURE_FEATURE_ALRB
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetRtcSecure(RTC_TypeDef *RTCx, uint32_t rtcSecure)
{
MODIFY_REG(RTCx->SECCFGR, RTC_SECCFGR_SEC | RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | RTC_SECCFGR_TSSEC | \
RTC_SECCFGR_WUTSEC | RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC, rtcSecure);
}
#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief Get RTC secure level.
* @note Secure features is relevant if LL_RTC_SECURE_FULL_YES.
* @rmtoll RTC_SECCFGR SEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR INISEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR CALSEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR TSSEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR WUTSEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR ALRASEC LL_RTC_SetRtcSecure
* @rmtoll RTC_SECCFGR ALRBSEC LL_RTC_SetRtcSecure
* @param RTCx RTC Instance
* @retval Combination of the following values:
* @arg @ref LL_RTC_SECURE_FULL_YES
* @arg @ref LL_RTC_SECURE_FULL_NO
* @arg @ref LL_RTC_UNSECURE_FEATURE_INIT
* @arg @ref LL_RTC_UNSECURE_FEATURE_CAL
* @arg @ref LL_RTC_UNSECURE_FEATURE_TS
* @arg @ref LL_RTC_UNSECURE_FEATURE_WUT
* @arg @ref LL_RTC_UNSECURE_FEATURE_ALRA
* @arg @ref LL_RTC_UNSECURE_FEATURE_ALRB
*/
__STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(RTC_TypeDef *RTCx)
{
return READ_BIT(RTCx->SECCFGR, RTC_SECCFGR_SEC | RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | RTC_SECCFGR_TSSEC | \
RTC_SECCFGR_WUTSEC | RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Set TAMPER secure level.
* @rmtoll TAMP_SECCFGR TAMPSEC LL_RTC_SetTampSecure
* @param RTCx RTC Instance
* @param tampSecure This parameter can be one of the following values:
* @arg @ref LL_TAMP_SECURE_FULL_YES
* @arg @ref LL_TAMP_SECURE_FULL_NO
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetTampSecure(RTC_TypeDef *RTCx, uint32_t tampSecure)
{
UNUSED(RTCx);
MODIFY_REG(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC, tampSecure);
}
#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief Get TAMPER secure level.
* @rmtoll TAMP_SECCFGR TAMPSEC LL_RTC_GetTampSecure
* @param RTCx RTC Instance
* @retval This parameter can be one of the following values:
* @arg @ref LL_TAMP_SECURE_FULL_YES
* @arg @ref LL_TAMP_SECURE_FULL_NO
*/
__STATIC_INLINE uint32_t LL_RTC_GetTampSecure(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_PRIVILEGE PRIVILEGE_Management
* @{
*/
/**
* @brief Set RTC privilege level.
* @note Privilege features are relevant if LL_RTC_PRIVILEGE_FULL_NO.
* @rmtoll RTC_PRIVCFGR PRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR INITPRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR CALPRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR TSPRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR WUTPRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR ALRAPRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR ALRBPRIV LL_RTC_SetRtcPrivilege
* @param RTCx RTC Instance
* @param rtcPrivilege This parameter can be a combination of the following values:
* @arg @ref LL_RTC_PRIVILEGE_FULL_YES
* @arg @ref LL_RTC_PRIVILEGE_FULL_NO
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_INIT
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_CAL
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_TS
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_WUT
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetRtcPrivilege(RTC_TypeDef *RTCx, uint32_t rtcPrivilege)
{
MODIFY_REG(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | RTC_PRIVCFGR_TSPRIV | \
RTC_PRIVCFGR_WUTPRIV | RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV, rtcPrivilege);
}
/**
* @brief Get RTC privilege level.
* @note Privilege features are relevant if LL_RTC_PRIVILEGE_FULL_NO.
* @rmtoll RTC_PRIVCFGR PRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR INITPRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR CALPRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR TSPRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR WUTPRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR ALRAPRIV LL_RTC_SetRtcPrivilege
* @rmtoll RTC_PRIVCFGR ALRBPRIV LL_RTC_SetRtcPrivilege
* @param RTCx RTC Instance
* @retval Combination of the following values:
* @arg @ref LL_RTC_PRIVILEGE_FULL_YES
* @arg @ref LL_RTC_PRIVILEGE_FULL_NO
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_INIT
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_CAL
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_TS
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_WUT
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA
* @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB
*/
__STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(RTC_TypeDef *RTCx)
{
return READ_BIT(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | \
RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_WUTPRIV | RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV);
}
/**
* @brief Set TAMPER privilege level.
* @rmtoll TAMP_SECCFGR TAMPPRIV LL_RTC_SetTampPrivilege
* @param RTCx RTC Instance
* @param tampPrivilege This parameter can be one of the following values:
* @arg @ref LL_TAMP_PRIVILEGE_FULL_YES
* @arg @ref LL_TAMP_PRIVILEGE_FULL_NO
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetTampPrivilege(RTC_TypeDef *RTCx, uint32_t tampPrivilege)
{
UNUSED(RTCx);
MODIFY_REG(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV, tampPrivilege);
}
/**
* @brief Get TAMPER privilege level.
* @rmtoll TAMP_SECCFGR TAMPSEC LL_RTC_GetTampPrivilege
* @param RTCx RTC Instance
* @retval This parameter can be one of the following values:
* @arg @ref LL_TAMP_PRIVILEGE_FULL_YES
* @arg @ref LL_TAMP_PRIVILEGE_FULL_NO
*/
__STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return READ_BIT(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV);
}
/**
* @brief Set Backup Registers privilege level.
* @note bckupRegisterPrivilege is only writable in secure mode or if trustzone is disabled
* @rmtoll TAMP_PRIVCFGR BKPWPRIV LL_RTC_SetTampPrivilege
* @rmtoll TAMP_PRIVCFGR BKPRWPRIV LL_RTC_SetTampPrivilege
* @param RTCx RTC Instance
* @param bckupRegisterPrivilege This parameter can be one of the following values:
* @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_NONE
* @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_1
* @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2
* @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(RTC_TypeDef *RTCx, uint32_t bckupRegisterPrivilege)
{
UNUSED(RTCx);
MODIFY_REG(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV), bckupRegisterPrivilege);
}
/**
* @brief Get Backup Registers privilege level.
* @rmtoll TAMP_PRIVCFGR BKPWPRIV LL_RTC_SetTampPrivilege
* @rmtoll TAMP_PRIVCFGR BKPRWPRIV LL_RTC_SetTampPrivilege
* @param RTCx RTC Instance
* @retval This parameter can be one of the following values:
* @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_NONE
* @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_1
* @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2
* @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL
*/
__STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return READ_BIT(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_BACKUP_REG_PROTECTION PROTECTION_BACKUP_REG_Management
* @brief Backup register protection is common to security and privilege.
* @{
*/
/**
* @brief Set Backup registers protection level.
* @note Zone 1 : read protection write protection
* @note Zone 2 : read non-protection write protection
* @note Zone 3 : read non-protection write non-protection
* @note zone 1 : start from 0 to startZone2 start value
* @note zone 2 : start from startZone2 start value to startZone3 start value
* @note zone 3 : start from to startZone3 to the end of BACKUPREG
* @note Warning : this parameter is only writable in secure mode or if trustzone is disabled
* @rmtoll TAMP_SECCFGR BKPWSEC LL_RTC_SetBackupRegProtection
* @rmtoll TAMP_SECCFGR BKPRWSEC LL_RTC_SetBackupRegProtection
* @param RTCx RTC Instance
* @param startZone2 This parameter can be one of the following values:
* @arg @ref LL_RTC_BKP_DR0
* @arg @ref LL_RTC_BKP_DR1
* @arg @ref LL_RTC_BKP_DR2
* @arg @ref LL_RTC_BKP_DR3
* @arg @ref LL_RTC_BKP_DR4 ...
* @param startZone3 This parameter can be one of the following values:
* @arg @ref LL_RTC_BKP_DR0
* @arg @ref LL_RTC_BKP_DR1
* @arg @ref LL_RTC_BKP_DR2
* @arg @ref LL_RTC_BKP_DR3
* @arg @ref LL_RTC_BKP_DR4 ...
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetBackupRegProtection(RTC_TypeDef *RTCx, uint32_t startZone2, uint32_t startZone3)
{
UNUSED(RTCx);
MODIFY_REG(TAMP->SECCFGR, (TAMP_SECCFGR_BKPRWSEC_Msk | TAMP_SECCFGR_BKPWSEC_Msk), (startZone2 << \
TAMP_SECCFGR_BKPRWSEC_Pos) | (startZone3 << TAMP_SECCFGR_BKPWSEC_Pos));
}
/**
* @brief Get Backup registers protection level start zone 2.
* @note Zone 1 : read protection write protection
* @note Zone 2 : read non-protection/non-privile write protection
* @note Zone 3 : read non-protection write non-protection
* @rmtoll TAMP_SECCFGR BKPRWSEC LL_RTC_GetBackupRegProtectionStartZone2
* @param RTCx RTC Instance
* @retval Start zone 2
*/
__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BKPRWSEC_Msk) >> TAMP_SECCFGR_BKPRWSEC_Pos;
}
/**
* @brief Get Backup registers protection level start zone 3.
* @note Zone 1 : read protection write protection
* @note Zone 2 : read non-protection write protection
* @note Zone 3 : read non-protection write non-protection
* @rmtoll TAMP_SECCFGR BKPWSEC LL_RTC_GetBackupRegProtectionStartZone3
* @param RTCx RTC Instance
* @retval Start zone 2
*/
__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BKPWSEC_Msk) >> TAMP_SECCFGR_BKPWSEC_Pos;
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable Time-stamp interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_TSIE);
}
/**
* @brief Disable Time-stamp interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
}
/**
* @brief Enable Wakeup timer interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_WUTIE);
}
/**
* @brief Disable Wakeup timer interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
}
/**
* @brief Enable Alarm B interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
}
/**
* @brief Disable Alarm B interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
}
/**
* @brief Enable Alarm A interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
}
/**
* @brief Disable Alarm A interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
}
/**
* @brief Enable SSR Underflow interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR SSRUIE LL_RTC_EnableIT_SSRU
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_SSRU(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_SSRUIE);
}
/**
* @brief Disable SSR Underflow interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR SSRUIE LL_RTC_DisableIT_SSRU
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_SSRU(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_SSRUIE);
}
/**
* @brief Check if Time-stamp interrupt is enabled or not
* @rmtoll RTC_CR TSIE LL_RTC_IsEnabledIT_TS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U);
}
/**
* @brief Check if Wakeup timer interrupt is enabled or not
* @rmtoll RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U);
}
/**
* @brief Check if Alarm B interrupt is enabled or not
* @rmtoll RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U);
}
/**
* @brief Check if Alarm A interrupt is enabled or not
* @rmtoll RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U);
}
/**
* @brief Check if SSR Underflow interrupt is enabled or not
* @rmtoll RTC_CR SSRUIE LL_RTC_IsEnabledIT_SSRU
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_SSRUIE) == (RTC_CR_SSRUIE)) ? 1U : 0U);
}
/**
* @brief Enable tamper 1 interrupt.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE);
}
/**
* @brief Disable tamper 1 interrupt.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE);
}
/**
* @brief Enable tamper 2 interrupt.
* @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE);
}
/**
* @brief Disable tamper 2 interrupt.
* @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE);
}
/**
* @brief Enable tamper 3 interrupt.
* @rmtoll TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
}
/**
* @brief Disable tamper 3 interrupt.
* @rmtoll TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
}
/**
* @brief Enable tamper 4 interrupt.
* @rmtoll TAMP_IER TAMP4IE LL_RTC_EnableIT_TAMP4
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP4IE);
}
/**
* @brief Disable tamper 4 interrupt.
* @rmtoll TAMP_IER TAMP4IE LL_RTC_DisableIT_TAMP4
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE);
}
/**
* @brief Enable tamper 5 interrupt.
* @rmtoll TAMP_IER TAMP5IE LL_RTC_EnableIT_TAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP5IE);
}
/**
* @brief Disable tamper 5 interrupt.
* @rmtoll TAMP_IER TAMP5IE LL_RTC_DisableIT_TAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE);
}
/**
* @brief Enable tamper 6 interrupt.
* @rmtoll TAMP_IER TAMP6IE LL_RTC_EnableIT_TAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP6IE);
}
/**
* @brief Disable tamper 6 interrupt.
* @rmtoll TAMP_IER TAMP6IE LL_RTC_DisableIT_TAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE);
}
/**
* @brief Enable tamper 7 interrupt.
* @rmtoll TAMP_IER TAMP7IE LL_RTC_EnableIT_TAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP7IE);
}
/**
* @brief Disable tamper 7 interrupt.
* @rmtoll TAMP_IER TAMP7IE LL_RTC_DisableIT_TAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP7IE);
}
/**
* @brief Enable tamper 8 interrupt.
* @rmtoll TAMP_IER TAMP8IE LL_RTC_EnableIT_TAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP8IE);
}
/**
* @brief Disable tamper 8 interrupt.
* @rmtoll TAMP_IER TAMP8IE LL_RTC_DisableIT_TAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP8IE);
}
/**
* @brief Enable internal tamper 1 interrupt.
* @rmtoll TAMP_IER ITAMP1IE LL_RTC_EnableIT_ITAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP1IE);
}
/**
* @brief Disable internal tamper 1 interrupt.
* @rmtoll TAMP_IER ITAMP1IE LL_RTC_DisableIT_ITAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP1IE);
}
/**
* @brief Enable internal tamper 2 interrupt.
* @rmtoll TAMP_IER ITAMP2IE LL_RTC_EnableIT_ITAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP2IE);
}
/**
* @brief Disable internal tamper 2 interrupt.
* @rmtoll TAMP_IER ITAMP2IE LL_RTC_DisableIT_ITAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP2IE);
}
/**
* @brief Enable internal tamper 3 interrupt.
* @rmtoll TAMP_IER ITAMP3IE LL_RTC_EnableIT_ITAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE);
}
/**
* @brief Disable internal tamper 3 interrupt.
* @rmtoll TAMP_IER ITAMP3IE LL_RTC_DisableIT_ITAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE);
}
/**
* @brief Enable internal tamper 5 interrupt.
* @rmtoll TAMP_IER ITAMP5IE LL_RTC_EnableIT_ITAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE);
}
/**
* @brief Disable internal tamper 5 interrupt.
* @rmtoll TAMP_IER ITAMP5IE LL_RTC_DisableIT_ITAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE);
}
/**
* @brief Enable internal tamper 6 interrupt.
* @rmtoll TAMP_IER ITAMP6IE LL_RTC_EnableIT_ITAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP6IE);
}
/**
* @brief Disable internal tamper 6 interrupt.
* @rmtoll TAMP_IER ITAMP6IE LL_RTC_DisableIT_ITAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP6IE);
}
/**
* @brief Enable internal tamper 7 interrupt.
* @rmtoll TAMP_IER ITAMP7IE LL_RTC_EnableIT_ITAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP7IE);
}
/**
* @brief Disable internal tamper 7 interrupt.
* @rmtoll TAMP_IER ITAMP7IE LL_RTC_DisableIT_ITAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP7IE);
}
/**
* @brief Enable internal tamper 8 interrupt.
* @rmtoll TAMP_IER ITAMP8IE LL_RTC_EnableIT_ITAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE);
}
/**
* @brief Disable internal tamper 8 interrupt.
* @rmtoll TAMP_IER TAMP8IE LL_RTC_DisableIT_ITAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE);
}
/**
* @brief Enable internal tamper 9 interrupt.
* @rmtoll TAMP_IER ITAMP9IE LL_RTC_EnableIT_ITAMP9
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP9(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP9IE);
}
/**
* @brief Disable internal tamper 9 interrupt.
* @rmtoll TAMP_IER ITAMP9IE LL_RTC_DisableIT_ITAMP9
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP9(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP9IE);
}
/**
* @brief Enable internal tamper 11 interrupt.
* @rmtoll TAMP_IER ITAMP11IE LL_RTC_EnableIT_ITAMP11
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP11(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP11IE);
}
/**
* @brief Disable internal tamper 11 interrupt.
* @rmtoll TAMP_IER ITAMP11IE LL_RTC_DisableIT_ITAMP11
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP11(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP11IE);
}
/**
* @brief Enable internal tamper 12 interrupt.
* @rmtoll TAMP_IER ITAMP12IE LL_RTC_EnableIT_ITAMP12
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP12(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP12IE);
}
/**
* @brief Disable internal tamper 12 interrupt.
* @rmtoll TAMP_IER TAMP12IE LL_RTC_DisableIT_ITAMP12
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP12(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP12IE);
}
/**
* @brief Enable internal tamper 13 interrupt.
* @rmtoll TAMP_IER ITAMP13IE LL_RTC_EnableIT_ITAMP13
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP13(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP13IE);
}
/**
* @brief Disable internal tamper 13 interrupt.
* @rmtoll TAMP_IER TAMP13IE LL_RTC_DisableIT_ITAMP13
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP13(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP13IE);
}
/**
* @brief Check if tamper 1 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 2 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 3 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 4 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP4IE LL_RTC_IsEnabledIT_TAMP4
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 5 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP5
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 6 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP6IE LL_RTC_IsEnabledIT_TAMP6
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 7 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP7
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP7IE) == (TAMP_IER_TAMP7IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 8 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP8IE LL_RTC_IsEnabledIT_TAMP8
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP8IE) == (TAMP_IER_TAMP8IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 1 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP1IE LL_RTC_IsEnabledIT_ITAMP1
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP1IE) == (TAMP_IER_ITAMP1IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 2 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP2IE LL_RTC_IsEnabledIT_ITAMP2
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP2IE) == (TAMP_IER_ITAMP2IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 3 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP3IE LL_RTC_IsEnabledIT_ITAMP3
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 5 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP5IE LL_RTC_IsEnabledIT_ITAMP5
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 6 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP6IE LL_RTC_IsEnabledIT_ITAMP6
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 7 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP7IE LL_RTC_IsEnabledIT_ITAMP7
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP7IE) == (TAMP_IER_ITAMP7IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 8 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP8IE LL_RTC_IsEnabledIT_ITAMP8
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP8IE) == (TAMP_IER_ITAMP8IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 9 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP9IE LL_RTC_IsEnabledIT_ITAMP9
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP9(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP9IE) == (TAMP_IER_ITAMP9IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 11 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP11IE LL_RTC_IsEnabledIT_ITAMP11
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP11(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP11IE) == (TAMP_IER_ITAMP11IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 12 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP12IE LL_RTC_IsEnabledIT_ITAMP12
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP12(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP12IE) == (TAMP_IER_ITAMP12IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 13 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP13IE LL_RTC_IsEnabledIT_ITAMP13
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP13(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP13IE) == (TAMP_IER_ITAMP13IE)) ? 1U : 0U);
}
/**
* @brief Increment Monotonic counter.
* @rmtoll TAMP_COUNTR COUNT LL_RTC_IncrementMonotonicCounter
* @param RTCx RTC Instance
* @retval None.
*/
__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
WRITE_REG(TAMP->COUNTR, 0u);
}
/**
* @brief Increment Monotonic counter.
* @rmtoll TAMP_COUNTR COUNT LL_RTC_GetMonotonicCounter
* @param RTCx RTC Instance
* @retval Monotonic counter value.
*/
__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return READ_REG(TAMP->COUNTR);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RTC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_RTC_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rtc.h
|
C
|
apache-2.0
| 220,225
|
/**
******************************************************************************
* @file stm32u5xx_ll_sdmmc.h
* @author MCD Application Team
* @brief Header file of SDMMC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_SDMMC_H
#define STM32U5xx_LL_SDMMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
/** @addtogroup STM32U5xx_Driver
* @{
*/
/** @addtogroup SDMMC_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
* @{
*/
/**
* @brief SDMMC Configuration Structure definition
*/
typedef struct
{
uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change.
This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
disabled when the bus is idle.
This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
uint32_t BusWide; /*!< Specifies the SDMMC bus width.
This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */
#if (USE_SD_TRANSCEIVER != 0U)
uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher.
This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */
#endif /* USE_SD_TRANSCEIVER */
} SDMMC_InitTypeDef;
/**
* @brief SDMMC Command Control structure
*/
typedef struct
{
uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
to a card as part of a command message. If a command
contains an argument, it must be loaded into this register
before writing the command to the command register. */
uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
Max_Data = 64 */
uint32_t Response; /*!< Specifies the SDMMC response type.
This parameter can be a value of @ref SDMMC_LL_Response_Type */
uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_CPSM_State */
} SDMMC_CmdInitTypeDef;
/**
* @brief SDMMC Data Control structure
*/
typedef struct
{
uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
is a read or write.
This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
is enabled or disabled.
This parameter can be a value of @ref SDMMC_LL_DPSM_State */
} SDMMC_DataInitTypeDef;
/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
* @{
*/
typedef struct
{
__IO uint32_t IDMALAR; /*!< SDMMC DMA linked list configuration register */
__IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register */
__IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register */
} SDMMC_DMALinkNodeTypeDef;
typedef struct
{
uint32_t BufferAddress; /*!< Node Buffer address */
uint32_t BufferSize ; /*!< Node Buffer size */
} SDMMC_DMALinkNodeConfTypeDef;
typedef struct
{
SDMMC_DMALinkNodeTypeDef *pHeadNode; /*!< Linked List Node Head */
SDMMC_DMALinkNodeTypeDef *pTailNode; /*!< Linked List Node Head */
uint32_t NodesCounter ; /*!< Node is ready for execution */
} SDMMC_DMALinkedListTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
/**
* @brief SDMMC Commands Index
*/
#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/
#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */
#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */
#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */
/*!< for SDHS and SDXC. */
#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */
#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */
#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */
#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */
#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */
#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */
#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */
#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */
#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
/**
* @brief Following commands are SD Card Specific commands.
* SDMMC_APP_CMD should be sent before sending these commands.
*/
#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */
#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */
#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */
#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
/**
* @brief Following commands are MMC Specific commands.
*/
#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */
/**
* @brief Following commands are SD Card Specific security commands.
* SDMMC_CMD_APP_CMD should be sent before sending these commands.
*/
#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
/**
* @brief Masks for errors Card Status R1 (OCR Register)
*/
#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
/**
* @brief Masks for R6 Response
*/
#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
#define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U)
#define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U)
#define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U)
#define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U)
#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
#ifndef SDMMC_DATATIMEOUT
#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
#endif /* SDMMC_DATATIMEOUT */
#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
/**
* @brief Command Class supported
*/
#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
#define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
* @{
*/
#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
/**
* @}
*/
/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
* @{
*/
#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
/**
* @}
*/
/** @defgroup SDMMC_LL_Bus_Wide Bus Width
* @{
*/
#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
((WIDE) == SDMMC_BUS_WIDE_4B) || \
((WIDE) == SDMMC_BUS_WIDE_8B))
/**
* @}
*/
/** @defgroup SDMMC_LL_Speed_Mode
* @{
*/
#define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U)
#define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U)
#define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U)
#define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U)
#define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U)
#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \
((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
((MODE) == SDMMC_SPEED_MODE_HIGH) || \
((MODE) == SDMMC_SPEED_MODE_ULTRA) || \
((MODE) == SDMMC_SPEED_MODE_DDR))
/**
* @}
*/
/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
* @{
*/
#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
/**
* @}
*/
/** @defgroup SDMMC_LL_Clock_Division Clock Division
* @{
*/
/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U)
/**
* @}
*/
/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present
* @{
*/
#define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U)
#define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U)
#define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U)
/**
* @}
*/
/** @defgroup SDMMC_LL_Command_Index Command Index
* @{
*/
#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
/**
* @}
*/
/** @defgroup SDMMC_LL_Response_Type Response Type
* @{
*/
#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
((RESPONSE) == SDMMC_RESPONSE_LONG))
/**
* @}
*/
/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
* @{
*/
#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
((WAIT) == SDMMC_WAIT_IT) || \
((WAIT) == SDMMC_WAIT_PEND))
/**
* @}
*/
/** @defgroup SDMMC_LL_CPSM_State CPSM State
* @{
*/
#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
((CPSM) == SDMMC_CPSM_ENABLE))
/**
* @}
*/
/** @defgroup SDMMC_LL_Response_Registers Response Register
* @{
*/
#define SDMMC_RESP1 ((uint32_t)0x00000000U)
#define SDMMC_RESP2 ((uint32_t)0x00000004U)
#define SDMMC_RESP3 ((uint32_t)0x00000008U)
#define SDMMC_RESP4 ((uint32_t)0x0000000CU)
#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
((RESP) == SDMMC_RESP2) || \
((RESP) == SDMMC_RESP3) || \
((RESP) == SDMMC_RESP4))
/** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode
* @{
*/
#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
#define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN)
#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE)
#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT)
/**
* @}
*/
/** @defgroup SDMMC_LL_Data_Length Data Length
* @{
*/
#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
/**
* @}
*/
/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
* @{
*/
#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \
SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \
SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \
SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \
SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
/**
* @}
*/
/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
* @{
*/
#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
/**
* @}
*/
/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
* @{
*/
#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
((MODE) == SDMMC_TRANSFER_MODE_STREAM))
/**
* @}
*/
/** @defgroup SDMMC_LL_DPSM_State DPSM State
* @{
*/
#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
((DPSM) == SDMMC_DPSM_ENABLE))
/**
* @}
*/
/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
* @{
*/
#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
/**
* @}
*/
/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
* @{
*/
#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE
#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE
#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE
#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE
#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE
#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE
#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE
#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
/**
* @}
*/
/** @defgroup SDMMC_LL_Flags Flags
* @{
*/
#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD
#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT
#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT
#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT
#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
#define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0
#define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END
#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
#define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL
#define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT
#define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND
#define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP
#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\
SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
SDMMC_FLAG_IDMABTC))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
* @{
*/
/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
* @brief SDMMC_LL registers bit address in the alias region
* @{
*/
/* ---------------------- SDMMC registers bit mask --------------------------- */
/* --- CLKCR Register ---*/
/* CLKCR register clear mask */
#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
SDMMC_CLKCR_WIDBUS |\
SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\
SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\
SDMMC_CLKCR_SELCLKRX))
/* --- DCTRL Register ---*/
/* SDMMC DCTRL Clear Mask */
#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
/* --- CMD Register ---*/
/* CMD Register clear mask */
#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND))
/* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/
#define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA)
/* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/
#define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4)
/* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/
#define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2)
/**
* @}
*/
/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/**
* @brief Enable the SDMMC device interrupt.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
/**
* @brief Disable the SDMMC device interrupt.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified SDMMC flag is set or not.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
* @arg SDMMC_FLAG_DPSMACT: Data path state machine active
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
* @retval The new state of SDMMC_FLAG (SET or RESET).
*/
#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
/**
* @brief Clears the SDMMC pending flags.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
* @retval None
*/
#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
/**
* @brief Checks whether the specified SDMMC interrupt has occurred or not.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INTERRUPT__ specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval The new state of SDMMC_IT (SET or RESET).
*/
#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clears the SDMMC's interrupt pending bits.
* @param __INSTANCE__ Pointer to SDMMC register base
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
/**
* @brief Enable Start the SD I/O Read Wait operation.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
/**
* @brief Disable Start the SD I/O Read Wait operations.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
/**
* @brief Enable Start the SD I/O Read Wait operation.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
/**
* @brief Enable the SD I/O Mode Operation.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
/**
* @brief Disable the SD I/O Mode Operation.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
/**
* @brief Enable the SD I/O Suspend command sending.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)
/**
* @brief Disable the SD I/O Suspend command sending.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
/**
* @brief Enable the CMDTRANS mode.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)
/**
* @brief Disable the CMDTRANS mode.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
/**
* @brief Enable the CMDSTOP mode.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP)
/**
* @brief Disable the CMDSTOP mode.
* @param __INSTANCE__ Pointer to SDMMC register base
* @retval None
*/
#define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SDMMC_LL_Exported_Functions
* @{
*/
/* Initialization/de-initialization functions **********************************/
/** @addtogroup HAL_SDMMC_LL_Group1
* @{
*/
HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
/**
* @}
*/
/* I/O operation functions *****************************************************/
/** @addtogroup HAL_SDMMC_LL_Group2
* @{
*/
uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup HAL_SDMMC_LL_Group3
* @{
*/
HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
/* Command path state machine (CPSM) management functions */
HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
/* Data path state machine (DPSM) management functions */
HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data);
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
/* SDMMC Cards mode management functions */
HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
/**
* @}
*/
/* SDMMC Commands management functions ******************************************/
/** @addtogroup HAL_SDMMC_LL_Group4
* @{
*/
uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType);
uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr);
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA);
uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
/**
* @}
*/
/* SDMMC Responses management functions *****************************************/
/** @addtogroup HAL_SDMMC_LL_Group5
* @{
*/
uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
/**
* @}
*/
/* Linked List functions *******************************************************/
/** @addtogroup HAL_SDMMC_LL_Group6
* @{
*/
uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf);
uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode,
SDMMC_DMALinkNodeTypeDef *pNode);
uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode);
uint32_t SDMMC_DMALinkedList_LockNode(SDMMC_DMALinkNodeTypeDef *pNode);
uint32_t SDMMC_DMALinkedList_UnlockNode(SDMMC_DMALinkNodeTypeDef *pNode);
uint32_t SDMMC_DMALinkedList_EnableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList);
uint32_t SDMMC_DMALinkedList_DisableCircularMode(SDMMC_DMALinkedListTypeDef *pLinkedList);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_SDMMC_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h
|
C
|
apache-2.0
| 63,854
|
/**
******************************************************************************
* @file stm32u5xx_ll_spi.h
* @author MCD Application Team
* @brief Header file of SPI LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_SPI_H
#define STM32U5xx_LL_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined(SPI1) || defined(SPI2) || defined(SPI3)
/** @defgroup SPI_LL SPI
* @{
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** Legacy definitions for compatibility purpose
@cond 0
*/
#define LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED LL_SPI_UDR_CONFIG_LAST_RECEIVED
/**
@endcond
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
* @{
*/
#define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) ||\
((__INSTANCE__) == SPI2)
#define IS_LL_SPI_GRP2_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPI3)
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup SPI_LL_Exported_Types SPI Exported Types
* @{
*/
/**
* @brief SPI Init structures definition
*/
typedef struct
{
uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
This feature can be modified afterwards using unitary function
@ref LL_SPI_SetTransferDirection().*/
uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
This parameter can be a value of @ref SPI_LL_EC_MODE.
This feature can be modified afterwards using unitary function
@ref LL_SPI_SetMode().*/
uint32_t DataWidth; /*!< Specifies the SPI data width.
This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
This feature can be modified afterwards using unitary function
@ref LL_SPI_SetDataWidth().*/
uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_LL_EC_POLARITY.
This feature can be modified afterwards using unitary function
@ref LL_SPI_SetClockPolarity().*/
uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_LL_EC_PHASE.
This feature can be modified afterwards using unitary function
@ref LL_SPI_SetClockPhase().*/
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
or by software using the SSI bit.
This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
This feature can be modified afterwards using unitary function
@ref LL_SPI_SetNSSMode().*/
uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure
the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
@note The communication clock is derived from the master clock.
The slave clock does not need to be set.
This feature can be modified afterwards using unitary function
@ref LL_SPI_SetBaudRatePrescaler().*/
uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
This feature can be modified afterwards using unitary function
@ref LL_SPI_SetTransferBitOrder().*/
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
This feature can be modified afterwards using unitary functions
@ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be a number between Min_Data = 0x00
and Max_Data = 0xFFFFFFFF.
This feature can be modified afterwards using unitary function
@ref LL_SPI_SetCRCPolynomial().*/
} LL_SPI_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
* @{
*/
/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_SPI_ReadReg function
* @{
*/
#define LL_SPI_SR_RXP (SPI_SR_RXP)
#define LL_SPI_SR_TXP (SPI_SR_TXP)
#define LL_SPI_SR_DXP (SPI_SR_DXP)
#define LL_SPI_SR_EOT (SPI_SR_EOT)
#define LL_SPI_SR_TXTF (SPI_SR_TXTF)
#define LL_SPI_SR_UDR (SPI_SR_UDR)
#define LL_SPI_SR_CRCE (SPI_SR_CRCE)
#define LL_SPI_SR_MODF (SPI_SR_MODF)
#define LL_SPI_SR_OVR (SPI_SR_OVR)
#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
#define LL_SPI_SR_SUSP (SPI_SR_SUSP)
#define LL_SPI_SR_TXC (SPI_SR_TXC)
#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
/**
* @}
*/
/** @defgroup SPI_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
* @{
*/
#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
/**
* @}
*/
/** @defgroup SPI_LL_EC_MODE Mode
* @{
*/
#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
#define LL_SPI_MODE_SLAVE (0x00000000UL)
/**
* @}
*/
/** @defgroup SPI_LL_EC_SS_LEVEL SS Level
* @{
*/
#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
#define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
/**
* @}
*/
/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
* @{
*/
#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
| SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
/**
* @}
*/
/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
* @{
*/
#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
| SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
/**
* @}
*/
/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
* @{
*/
#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
/**
* @}
*/
/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
* @{
*/
#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
/**
* @}
*/
/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
* @{
*/
#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG)
/**
* @}
*/
/** @defgroup SPI_LL_EC_PROTOCOL Protocol
* @{
*/
#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
/**
* @}
*/
/** @defgroup SPI_LL_EC_PHASE Phase
* @{
*/
#define LL_SPI_PHASE_1EDGE (0x00000000UL)
#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
/**
* @}
*/
/** @defgroup SPI_LL_EC_POLARITY Polarity
* @{
*/
#define LL_SPI_POLARITY_LOW (0x00000000UL)
#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
/**
* @}
*/
/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
* @{
*/
#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
/**
* @}
*/
/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
* @{
*/
#define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS)
#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
/**
* @}
*/
/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
* @{
*/
#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
#define LL_SPI_MSB_FIRST (0x00000000UL)
/**
* @}
*/
/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
* @{
*/
#define LL_SPI_FULL_DUPLEX (0x00000000UL)
#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
/**
* @}
*/
/** @defgroup SPI_LL_EC_DATAWIDTH Data Width
* @{
*/
#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
| SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
| SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
| SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
| SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
| SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
| SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
/**
* @}
*/
/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
* @{
*/
#define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
| SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
* @{
*/
#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup SPI_LL_EC_CRC CRC
* @{
*/
#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
| SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
| SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
| SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
| SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
| SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
| SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
/**
* @}
*/
/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
* @{
*/
#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
#define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
/**
* @}
*/
/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
* @{
*/
#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
/**
* @}
*/
/** @defgroup SPI_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection
* @brief SPI Autonomous Trigger selection
* @{
*/
#define LL_SPI_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for SPI1 and SPI2 */
#define LL_SPI_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for SPI3 */
/*!< HW Trigger signal is GPDMA_CH0_TRG */
#define LL_SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x00000000U))
/*!< HW Trigger signal is GPDMA_CH1_TRG */
#define LL_SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH2_TRG */
#define LL_SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is GPDMA_CH3_TRG */
#define LL_SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI4_TRG */
#define LL_SPI_GRP1_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI9_TRG */
#define LL_SPI_GRP1_EXTI9_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM1_CH1_TRG */
#define LL_SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM2_CH1_TRG */
#define LL_SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP1_TRG */
#define LL_SPI_GRP1_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP2_TRG */
#define LL_SPI_GRP1_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_ALRA_TRG */
#define LL_SPI_GRP1_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_WUT_TRG */
#define LL_SPI_GRP1_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPDMA_CH0_TRG */
#define LL_SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x00000000U))
/*!< HW Trigger signal is LPDMA_CH1_TRG */
#define LL_SPI_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPDMA_CH2_TRG */
#define LL_SPI_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPDMA_CH3_TRG */
#define LL_SPI_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI4_TRG */
#define LL_SPI_GRP2_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is EXTI8_TRG */
#define LL_SPI_GRP2_EXTI8_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM1_CH1_TRG */
#define LL_SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is LPTIM3_CH1_TRG */
#define LL_SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP1_TRG */
#define LL_SPI_GRP2_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is COMP2_TRG */
#define LL_SPI_GRP2_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_ALRA_TRG */
#define LL_SPI_GRP2_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos))
/*!< HW Trigger signal is RTC_WUT_TRG */
#define LL_SPI_GRP2_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos))
/**
* @}
*/
/** @defgroup SPI_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
* @brief SPI Autonomous Trigger Polarity
* @{
*/
#define LL_SPI_TRIG_POLARITY_RISING 0x00000000U /*!< SPI triggered on rising edge */
#define LL_SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /*!< SPI triggered on falling edge */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
* @{
*/
/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in SPI register
* @param __INSTANCE__ SPI Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in SPI register
* @param __INSTANCE__ SPI Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
* @{
*/
/** @defgroup SPI_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable SPI peripheral
* @rmtoll CR1 SPE LL_SPI_Enable
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
* @brief Disable SPI peripheral
* @note When disabling the SPI, follow the procedure described in the Reference Manual.
* @rmtoll CR1 SPE LL_SPI_Disable
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
* @brief Check if SPI peripheral is enabled
* @rmtoll CR1 SPE LL_SPI_IsEnabled
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
}
/**
* @brief Swap the MOSI and MISO pin
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
}
/**
* @brief Restore default function for MOSI and MISO pin
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
}
/**
* @brief Check if MOSI and MISO pin are swapped
* @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
}
/**
* @brief Enable GPIO control
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
}
/**
* @brief Disable GPIO control
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
}
/**
* @brief Check if GPIO control is active
* @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
}
/**
* @brief Set SPI Mode to Master or Slave
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG2 MASTER LL_SPI_SetMode
* @param SPIx SPI Instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_SPI_MODE_MASTER
* @arg @ref LL_SPI_MODE_SLAVE
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
{
MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
}
/**
* @brief Get SPI Mode (Master or Slave)
* @rmtoll CFG2 MASTER LL_SPI_GetMode
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_MODE_MASTER
* @arg @ref LL_SPI_MODE_SLAVE
*/
__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
}
/**
* @brief Configure the Idleness applied by master between active edge of SS and first send data
* @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
* @param SPIx SPI Instance
* @param MasterSSIdleness This parameter can be one of the following values:
* @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
{
MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
}
/**
* @brief Get the configured Idleness applied by master
* @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
*/
__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
}
/**
* @brief Configure the idleness applied by master between data frame
* @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
* @param SPIx SPI Instance
* @param MasterInterDataIdleness This parameter can be one of the following values:
* @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
{
MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
}
/**
* @brief Get the configured inter data idleness
* @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
*/
__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
}
/**
* @brief Set transfer size
* @note Count is the number of frame to be transferred
* @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
* @param SPIx SPI Instance
* @param Count 0..0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
{
MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
}
/**
* @brief Get transfer size
* @note Count is the number of frame to be transferred
* @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
* @param SPIx SPI Instance
* @retval 0..0xFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
}
/**
* @brief Lock the AF configuration of associated IOs
* @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
* the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
* @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
}
/**
* @brief Check if the AF configuration is locked.
* @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
}
/**
* @brief Set Tx CRC Initialization Pattern
* @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
* @param SPIx SPI Instance
* @param TXCRCInitAll This parameter can be one of the following values:
* @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
* @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
}
/**
* @brief Get Tx CRC Initialization Pattern
* @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
* @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
*/
__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
}
/**
* @brief Set Rx CRC Initialization Pattern
* @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
* @param SPIx SPI Instance
* @param RXCRCInitAll This parameter can be one of the following values:
* @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
* @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
}
/**
* @brief Get Rx CRC Initialization Pattern
* @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
* @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
*/
__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
}
/**
* @brief Set internal SS input level ignoring what comes from PIN.
* @note This configuration has effect only with config LL_SPI_NSS_SOFT
* @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
* @param SPIx SPI Instance
* @param SSLevel This parameter can be one of the following values:
* @arg @ref LL_SPI_SS_LEVEL_HIGH
* @arg @ref LL_SPI_SS_LEVEL_LOW
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
}
/**
* @brief Get internal SS input level
* @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_SS_LEVEL_HIGH
* @arg @ref LL_SPI_SS_LEVEL_LOW
*/
__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
}
/**
* @brief Enable CRC computation on 33/17 bits
* @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
}
/**
* @brief Disable CRC computation on 33/17 bits
* @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
}
/**
* @brief Check if Enable CRC computation on 33/17 bits is enabled
* @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
}
/**
* @brief Suspend an ongoing transfer for Master configuration
* @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
}
/**
* @brief Start effective transfer on wire for Master configuration
* @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
}
/**
* @brief Check if there is an unfinished master transfer
* @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
}
/**
* @brief Enable Master Rx auto suspend in case of overrun
* @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
}
/**
* @brief Disable Master Rx auto suspend in case of overrun
* @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
}
/**
* @brief Check if Master Rx auto suspend is activated
* @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
}
/**
* @brief Set Underrun behavior
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
* @param SPIx SPI Instance
* @param UDRConfig This parameter can be one of the following values:
* @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
* @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
{
MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
}
/**
* @brief Get Underrun behavior
* @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
* @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
*/
__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
}
/**
* @brief Set Serial protocol used
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG2 SP LL_SPI_SetStandard
* @param SPIx SPI Instance
* @param Standard This parameter can be one of the following values:
* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
* @arg @ref LL_SPI_PROTOCOL_TI
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
{
MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
}
/**
* @brief Get Serial protocol used
* @rmtoll CFG2 SP LL_SPI_GetStandard
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
* @arg @ref LL_SPI_PROTOCOL_TI
*/
__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
}
/**
* @brief Set Clock phase
* @note This configuration can not be changed when SPI is enabled.
* This bit is not used in SPI TI mode.
* @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
* @param SPIx SPI Instance
* @param ClockPhase This parameter can be one of the following values:
* @arg @ref LL_SPI_PHASE_1EDGE
* @arg @ref LL_SPI_PHASE_2EDGE
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
{
MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
}
/**
* @brief Get Clock phase
* @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_PHASE_1EDGE
* @arg @ref LL_SPI_PHASE_2EDGE
*/
__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
}
/**
* @brief Set Clock polarity
* @note This configuration can not be changed when SPI is enabled.
* This bit is not used in SPI TI mode.
* @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
* @param SPIx SPI Instance
* @param ClockPolarity This parameter can be one of the following values:
* @arg @ref LL_SPI_POLARITY_LOW
* @arg @ref LL_SPI_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
{
MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
}
/**
* @brief Get Clock polarity
* @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_POLARITY_LOW
* @arg @ref LL_SPI_POLARITY_HIGH
*/
__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
}
/**
* @brief Set NSS polarity
* @note This configuration can not be changed when SPI is enabled.
* This bit is not used in SPI TI mode.
* @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
* @param SPIx SPI Instance
* @param NSSPolarity This parameter can be one of the following values:
* @arg @ref LL_SPI_NSS_POLARITY_LOW
* @arg @ref LL_SPI_NSS_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
{
MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
}
/**
* @brief Get NSS polarity
* @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_NSS_POLARITY_LOW
* @arg @ref LL_SPI_NSS_POLARITY_HIGH
*/
__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
}
/**
* @brief Set Baudrate Prescaler
* @note This configuration can not be changed when SPI is enabled.
* SPI BaudRate = fPCLK/Pescaler.
* @rmtoll CFG1 MBR BPASS LL_SPI_SetBaudRatePrescaler
* @param SPIx SPI Instance
* @param Baudrate This parameter can be one of the following values:
* @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
{
MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate);
}
/**
* @brief Get Baudrate Prescaler
* @rmtoll CFG1 MBR BPASS LL_SPI_GetBaudRatePrescaler
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
*/
__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS)));
}
/**
* @brief Set Transfer Bit Order
* @note This configuration can not be changed when SPI is enabled.
* This bit is not used in SPI TI mode.
* @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
* @param SPIx SPI Instance
* @param BitOrder This parameter can be one of the following values:
* @arg @ref LL_SPI_LSB_FIRST
* @arg @ref LL_SPI_MSB_FIRST
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
{
MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
}
/**
* @brief Get Transfer Bit Order
* @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_LSB_FIRST
* @arg @ref LL_SPI_MSB_FIRST
*/
__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
}
/**
* @brief Set Transfer Mode
* @note This configuration can not be changed when SPI is enabled except for half duplex direction
* using LL_SPI_SetHalfDuplexDirection.
* @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
* CFG2 COMM LL_SPI_SetTransferDirection
* @param SPIx SPI Instance
* @param TransferDirection This parameter can be one of the following values:
* @arg @ref LL_SPI_FULL_DUPLEX
* @arg @ref LL_SPI_SIMPLEX_TX
* @arg @ref LL_SPI_SIMPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
}
/**
* @brief Get Transfer Mode
* @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
* CFG2 COMM LL_SPI_GetTransferDirection
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_FULL_DUPLEX
* @arg @ref LL_SPI_SIMPLEX_TX
* @arg @ref LL_SPI_SIMPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
*/
__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
{
uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
return (Hddir | Comm);
}
/**
* @brief Set direction for Half-Duplex Mode
* @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
* @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
* @param SPIx SPI Instance
* @param HalfDuplexDirection This parameter can be one of the following values:
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
}
/**
* @brief Get direction for Half-Duplex Mode
* @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
* @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
*/
__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
}
/**
* @brief Set Frame Data Size
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
* @param SPIx SPI Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_SPI_DATAWIDTH_4BIT
* @arg @ref LL_SPI_DATAWIDTH_5BIT
* @arg @ref LL_SPI_DATAWIDTH_6BIT
* @arg @ref LL_SPI_DATAWIDTH_7BIT
* @arg @ref LL_SPI_DATAWIDTH_8BIT
* @arg @ref LL_SPI_DATAWIDTH_9BIT
* @arg @ref LL_SPI_DATAWIDTH_10BIT
* @arg @ref LL_SPI_DATAWIDTH_11BIT
* @arg @ref LL_SPI_DATAWIDTH_12BIT
* @arg @ref LL_SPI_DATAWIDTH_13BIT
* @arg @ref LL_SPI_DATAWIDTH_14BIT
* @arg @ref LL_SPI_DATAWIDTH_15BIT
* @arg @ref LL_SPI_DATAWIDTH_16BIT
* @arg @ref LL_SPI_DATAWIDTH_17BIT
* @arg @ref LL_SPI_DATAWIDTH_18BIT
* @arg @ref LL_SPI_DATAWIDTH_19BIT
* @arg @ref LL_SPI_DATAWIDTH_20BIT
* @arg @ref LL_SPI_DATAWIDTH_21BIT
* @arg @ref LL_SPI_DATAWIDTH_22BIT
* @arg @ref LL_SPI_DATAWIDTH_23BIT
* @arg @ref LL_SPI_DATAWIDTH_24BIT
* @arg @ref LL_SPI_DATAWIDTH_25BIT
* @arg @ref LL_SPI_DATAWIDTH_26BIT
* @arg @ref LL_SPI_DATAWIDTH_27BIT
* @arg @ref LL_SPI_DATAWIDTH_28BIT
* @arg @ref LL_SPI_DATAWIDTH_29BIT
* @arg @ref LL_SPI_DATAWIDTH_30BIT
* @arg @ref LL_SPI_DATAWIDTH_31BIT
* @arg @ref LL_SPI_DATAWIDTH_32BIT
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
{
MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
}
/**
* @brief Get Frame Data Size
* @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_DATAWIDTH_4BIT
* @arg @ref LL_SPI_DATAWIDTH_5BIT
* @arg @ref LL_SPI_DATAWIDTH_6BIT
* @arg @ref LL_SPI_DATAWIDTH_7BIT
* @arg @ref LL_SPI_DATAWIDTH_8BIT
* @arg @ref LL_SPI_DATAWIDTH_9BIT
* @arg @ref LL_SPI_DATAWIDTH_10BIT
* @arg @ref LL_SPI_DATAWIDTH_11BIT
* @arg @ref LL_SPI_DATAWIDTH_12BIT
* @arg @ref LL_SPI_DATAWIDTH_13BIT
* @arg @ref LL_SPI_DATAWIDTH_14BIT
* @arg @ref LL_SPI_DATAWIDTH_15BIT
* @arg @ref LL_SPI_DATAWIDTH_16BIT
* @arg @ref LL_SPI_DATAWIDTH_17BIT
* @arg @ref LL_SPI_DATAWIDTH_18BIT
* @arg @ref LL_SPI_DATAWIDTH_19BIT
* @arg @ref LL_SPI_DATAWIDTH_20BIT
* @arg @ref LL_SPI_DATAWIDTH_21BIT
* @arg @ref LL_SPI_DATAWIDTH_22BIT
* @arg @ref LL_SPI_DATAWIDTH_23BIT
* @arg @ref LL_SPI_DATAWIDTH_24BIT
* @arg @ref LL_SPI_DATAWIDTH_25BIT
* @arg @ref LL_SPI_DATAWIDTH_26BIT
* @arg @ref LL_SPI_DATAWIDTH_27BIT
* @arg @ref LL_SPI_DATAWIDTH_28BIT
* @arg @ref LL_SPI_DATAWIDTH_29BIT
* @arg @ref LL_SPI_DATAWIDTH_30BIT
* @arg @ref LL_SPI_DATAWIDTH_31BIT
* @arg @ref LL_SPI_DATAWIDTH_32BIT
*/
__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
}
/**
* @brief Set threshold of FIFO that triggers a transfer event
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
* @param SPIx SPI Instance
* @param Threshold This parameter can be one of the following values:
* @arg @ref LL_SPI_FIFO_TH_01DATA
* @arg @ref LL_SPI_FIFO_TH_02DATA
* @arg @ref LL_SPI_FIFO_TH_03DATA
* @arg @ref LL_SPI_FIFO_TH_04DATA
* @arg @ref LL_SPI_FIFO_TH_05DATA
* @arg @ref LL_SPI_FIFO_TH_06DATA
* @arg @ref LL_SPI_FIFO_TH_07DATA
* @arg @ref LL_SPI_FIFO_TH_08DATA
* @arg @ref LL_SPI_FIFO_TH_09DATA
* @arg @ref LL_SPI_FIFO_TH_10DATA
* @arg @ref LL_SPI_FIFO_TH_11DATA
* @arg @ref LL_SPI_FIFO_TH_12DATA
* @arg @ref LL_SPI_FIFO_TH_13DATA
* @arg @ref LL_SPI_FIFO_TH_14DATA
* @arg @ref LL_SPI_FIFO_TH_15DATA
* @arg @ref LL_SPI_FIFO_TH_16DATA
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
{
MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
}
/**
* @brief Get threshold of FIFO that triggers a transfer event
* @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_FIFO_TH_01DATA
* @arg @ref LL_SPI_FIFO_TH_02DATA
* @arg @ref LL_SPI_FIFO_TH_03DATA
* @arg @ref LL_SPI_FIFO_TH_04DATA
* @arg @ref LL_SPI_FIFO_TH_05DATA
* @arg @ref LL_SPI_FIFO_TH_06DATA
* @arg @ref LL_SPI_FIFO_TH_07DATA
* @arg @ref LL_SPI_FIFO_TH_08DATA
* @arg @ref LL_SPI_FIFO_TH_09DATA
* @arg @ref LL_SPI_FIFO_TH_10DATA
* @arg @ref LL_SPI_FIFO_TH_11DATA
* @arg @ref LL_SPI_FIFO_TH_12DATA
* @arg @ref LL_SPI_FIFO_TH_13DATA
* @arg @ref LL_SPI_FIFO_TH_14DATA
* @arg @ref LL_SPI_FIFO_TH_15DATA
* @arg @ref LL_SPI_FIFO_TH_16DATA
*/
__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
}
/**
* @brief Enable CRC
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
}
/**
* @brief Disable CRC
* @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
}
/**
* @brief Check if CRC is enabled
* @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
}
/**
* @brief Set CRC Length
* @note This configuration can not be changed when SPI is enabled.
* @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
* @param SPIx SPI Instance
* @param CRCLength This parameter can be one of the following values:
* @arg @ref LL_SPI_CRC_4BIT
* @arg @ref LL_SPI_CRC_5BIT
* @arg @ref LL_SPI_CRC_6BIT
* @arg @ref LL_SPI_CRC_7BIT
* @arg @ref LL_SPI_CRC_8BIT
* @arg @ref LL_SPI_CRC_9BIT
* @arg @ref LL_SPI_CRC_10BIT
* @arg @ref LL_SPI_CRC_11BIT
* @arg @ref LL_SPI_CRC_12BIT
* @arg @ref LL_SPI_CRC_13BIT
* @arg @ref LL_SPI_CRC_14BIT
* @arg @ref LL_SPI_CRC_15BIT
* @arg @ref LL_SPI_CRC_16BIT
* @arg @ref LL_SPI_CRC_17BIT
* @arg @ref LL_SPI_CRC_18BIT
* @arg @ref LL_SPI_CRC_19BIT
* @arg @ref LL_SPI_CRC_20BIT
* @arg @ref LL_SPI_CRC_21BIT
* @arg @ref LL_SPI_CRC_22BIT
* @arg @ref LL_SPI_CRC_23BIT
* @arg @ref LL_SPI_CRC_24BIT
* @arg @ref LL_SPI_CRC_25BIT
* @arg @ref LL_SPI_CRC_26BIT
* @arg @ref LL_SPI_CRC_27BIT
* @arg @ref LL_SPI_CRC_28BIT
* @arg @ref LL_SPI_CRC_29BIT
* @arg @ref LL_SPI_CRC_30BIT
* @arg @ref LL_SPI_CRC_31BIT
* @arg @ref LL_SPI_CRC_32BIT
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
{
MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
}
/**
* @brief Get CRC Length
* @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_CRC_4BIT
* @arg @ref LL_SPI_CRC_5BIT
* @arg @ref LL_SPI_CRC_6BIT
* @arg @ref LL_SPI_CRC_7BIT
* @arg @ref LL_SPI_CRC_8BIT
* @arg @ref LL_SPI_CRC_9BIT
* @arg @ref LL_SPI_CRC_10BIT
* @arg @ref LL_SPI_CRC_11BIT
* @arg @ref LL_SPI_CRC_12BIT
* @arg @ref LL_SPI_CRC_13BIT
* @arg @ref LL_SPI_CRC_14BIT
* @arg @ref LL_SPI_CRC_15BIT
* @arg @ref LL_SPI_CRC_16BIT
* @arg @ref LL_SPI_CRC_17BIT
* @arg @ref LL_SPI_CRC_18BIT
* @arg @ref LL_SPI_CRC_19BIT
* @arg @ref LL_SPI_CRC_20BIT
* @arg @ref LL_SPI_CRC_21BIT
* @arg @ref LL_SPI_CRC_22BIT
* @arg @ref LL_SPI_CRC_23BIT
* @arg @ref LL_SPI_CRC_24BIT
* @arg @ref LL_SPI_CRC_25BIT
* @arg @ref LL_SPI_CRC_26BIT
* @arg @ref LL_SPI_CRC_27BIT
* @arg @ref LL_SPI_CRC_28BIT
* @arg @ref LL_SPI_CRC_29BIT
* @arg @ref LL_SPI_CRC_30BIT
* @arg @ref LL_SPI_CRC_31BIT
* @arg @ref LL_SPI_CRC_32BIT
*/
__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
}
/**
* @brief Set NSS Mode
* @note This configuration can not be changed when SPI is enabled.
* This bit is not used in SPI TI mode.
* @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
* CFG2 SSOE LL_SPI_SetNSSMode
* @param SPIx SPI Instance
* @param NSS This parameter can be one of the following values:
* @arg @ref LL_SPI_NSS_SOFT
* @arg @ref LL_SPI_NSS_HARD_INPUT
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
{
MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
}
/**
* @brief Set NSS Mode
* @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
* CFG2 SSOE LL_SPI_GetNSSMode
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_NSS_SOFT
* @arg @ref LL_SPI_NSS_HARD_INPUT
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
*/
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
}
/**
* @brief Enable NSS pulse mgt
* @note This configuration can not be changed when SPI is enabled.
* This bit is not used in SPI TI mode.
* @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
}
/**
* @brief Disable NSS pulse mgt
* @note This configuration can not be changed when SPI is enabled.
* This bit is not used in SPI TI mode.
* @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
}
/**
* @brief Check if NSS pulse is enabled
* @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if there is enough data in FIFO to read a full packet
* @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
}
/**
* @brief Check if there is enough space in FIFO to hold a full packet
* @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
}
/**
* @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
* @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
}
/**
* @brief Check that end of transfer event occurred
* @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
}
/**
* @brief Check that all required data has been filled in the fifo according to transfer size
* @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
}
/**
* @brief Get Underrun error flag
* @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
}
/**
* @brief Get CRC error flag
* @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
}
/**
* @brief Get Mode fault error flag
* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
}
/**
* @brief Get Overrun error flag
* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
}
/**
* @brief Get TI Frame format error flag
* @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
}
/**
* @brief Check if a suspend operation is done
* @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
}
/**
* @brief Check if last TxFIFO or CRC frame transmission is completed
* @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
}
/**
* @brief Check if at least one 32-bit data is available in RxFIFO
* @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
}
/**
* @brief Get number of data framed remaining in current TSIZE
* @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
* @param SPIx SPI Instance
* @retval 0..0xFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
}
/**
* @brief Get RxFIFO packing Level
* @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_RX_FIFO_0PACKET
* @arg @ref LL_SPI_RX_FIFO_1PACKET
* @arg @ref LL_SPI_RX_FIFO_2PACKET
* @arg @ref LL_SPI_RX_FIFO_3PACKET
*/
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
}
/**
* @brief Clear End Of Transfer flag
* @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
}
/**
* @brief Clear TXTF flag
* @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
}
/**
* @brief Clear Underrun error flag
* @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
}
/**
* @brief Clear Overrun error flag
* @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
}
/**
* @brief Clear CRC error flag
* @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
}
/**
* @brief Clear Mode fault error flag
* @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
}
/**
* @brief Clear Frame format error flag
* @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
}
/**
* @brief Clear SUSP flag
* @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable Rx Packet available IT
* @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IER, SPI_IER_RXPIE);
}
/**
* @brief Enable Tx Packet space available IT
* @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IER, SPI_IER_TXPIE);
}
/**
* @brief Enable Duplex Packet available IT
* @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IER, SPI_IER_DXPIE);
}
/**
* @brief Enable End Of Transfer IT
* @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IER, SPI_IER_EOTIE);
}
/**
* @brief Enable TXTF IT
* @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
}
/**
* @brief Enable Underrun IT
* @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IER, SPI_IER_UDRIE);
}
/**
* @brief Enable Overrun IT
* @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IER, SPI_IER_OVRIE);
}
/**
* @brief Enable CRC Error IT
* @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
}
/**
* @brief Enable TI Frame Format Error IT
* @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
}
/**
* @brief Enable MODF IT
* @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->IER, SPI_IER_MODFIE);
}
/**
* @brief Disable Rx Packet available IT
* @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
}
/**
* @brief Disable Tx Packet space available IT
* @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
}
/**
* @brief Disable Duplex Packet available IT
* @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
}
/**
* @brief Disable End Of Transfer IT
* @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
}
/**
* @brief Disable TXTF IT
* @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
}
/**
* @brief Disable Underrun IT
* @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
}
/**
* @brief Disable Overrun IT
* @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
}
/**
* @brief Disable CRC Error IT
* @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
}
/**
* @brief Disable TI Frame Format Error IT
* @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
}
/**
* @brief Disable MODF IT
* @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
}
/**
* @brief Check if Rx Packet available IT is enabled
* @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
}
/**
* @brief Check if Tx Packet space available IT is enabled
* @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
}
/**
* @brief Check if Duplex Packet available IT is enabled
* @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
}
/**
* @brief Check if End Of Transfer IT is enabled
* @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
}
/**
* @brief Check if TXTF IT is enabled
* @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if Underrun IT is enabled
* @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
}
/**
* @brief Check if Overrun IT is enabled
* @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
}
/**
* @brief Check if CRC Error IT is enabled
* @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if TI Frame Format Error IT is enabled
* @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
}
/**
* @brief Check if MODF IT is enabled
* @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Enable DMA Rx
* @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
}
/**
* @brief Disable DMA Rx
* @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
}
/**
* @brief Check if DMA Rx is enabled
* @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Tx
* @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
}
/**
* @brief Disable DMA Tx
* @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
}
/**
* @brief Check if DMA Tx is enabled
* @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_DATA_Management DATA_Management
* @{
*/
/**
* @brief Read Data Register
* @rmtoll RXDR . LL_SPI_ReceiveData8
* @param SPIx SPI Instance
* @retval 0..0xFF
*/
__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
{
return (*((__IO uint8_t *)&SPIx->RXDR));
}
/**
* @brief Read Data Register
* @rmtoll RXDR . LL_SPI_ReceiveData16
* @param SPIx SPI Instance
* @retval 0..0xFFFF
*/
__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
{
#if defined (__GNUC__)
__IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
return (*spirxdr);
#else
return (*((__IO uint16_t *)&SPIx->RXDR));
#endif /* __GNUC__ */
}
/**
* @brief Read Data Register
* @rmtoll RXDR . LL_SPI_ReceiveData32
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
{
return (*((__IO uint32_t *)&SPIx->RXDR));
}
/**
* @brief Write Data Register
* @rmtoll TXDR . LL_SPI_TransmitData8
* @param SPIx SPI Instance
* @param TxData 0..0xFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
{
*((__IO uint8_t *)&SPIx->TXDR) = TxData;
}
/**
* @brief Write Data Register
* @rmtoll TXDR . LL_SPI_TransmitData16
* @param SPIx SPI Instance
* @param TxData 0..0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
#if defined (__GNUC__)
__IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
*spitxdr = TxData;
#else
*((__IO uint16_t *)&SPIx->TXDR) = TxData;
#endif /* __GNUC__ */
}
/**
* @brief Write Data Register
* @rmtoll TXDR . LL_SPI_TransmitData32
* @param SPIx SPI Instance
* @param TxData 0..0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
{
*((__IO uint32_t *)&SPIx->TXDR) = TxData;
}
/**
* @brief Set polynomial for CRC calcul
* @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
* @param SPIx SPI Instance
* @param CRCPoly 0..0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
{
WRITE_REG(SPIx->CRCPOLY, CRCPoly);
}
/**
* @brief Get polynomial for CRC calcul
* @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->CRCPOLY));
}
/**
* @brief Set the underrun pattern
* @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
* @param SPIx SPI Instance
* @param Pattern 0..0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
{
WRITE_REG(SPIx->UDRDR, Pattern);
}
/**
* @brief Get the underrun pattern
* @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->UDRDR));
}
/**
* @brief Get Rx CRC
* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->RXCRC));
}
/**
* @brief Get Tx CRC
* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->TXCRC));
}
/**
* @}
*/
/** @defgroup SPI_LL_AutonomousMode Configuration functions related to Autonomous mode feature
* @{
*/
/**
* @brief Enable Selected Trigger
* @rmtoll AUTOCR TRIGEN LL_SPI_Enable_SelectedTrigger
* @param SPIx SPI Instance.
* @retval None
*/
__STATIC_INLINE void LL_SPI_Enable_SelectedTrigger(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN);
}
/**
* @brief Disable Selected Trigger
* @rmtoll AUTOCR TRIGEN LL_SPI_Disable_SelectedTrigger
* @param SPIx SPI Instance.
* @retval None
*/
__STATIC_INLINE void LL_SPI_Disable_SelectedTrigger(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN);
}
/**
* @brief Indicate if selected Trigger is disabled or enabled
* @rmtoll AUTOCR TRIGEN LL_SPI_IsEnabled_SelectedTrigger
* @param SPIx SPI Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabled_SelectedTrigger(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN) == (SPI_AUTOCR_TRIGEN)) ? 1UL : 0UL);
}
/**
* @brief Set the trigger polarity
* @rmtoll AUTOCR TRIGPOL LL_SPI_SetTriggerPolarity
* @param SPIx SPI Instance.
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_SPI_TRIG_POLARITY_RISING
* @arg @ref LL_SPI_TRIG_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetTriggerPolarity(SPI_TypeDef *SPIx, uint32_t Polarity)
{
MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL, Polarity);
}
/**
* @brief Get the trigger polarity
* @rmtoll AUTOCR TRIGPOL LL_SPI_GetTriggerPolarity
* @param SPIx SPI Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_TRIG_POLARITY_RISING
* @arg @ref LL_SPI_TRIG_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_SPI_GetTriggerPolarity(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL));
}
/**
* @brief Set the selected trigger
* @rmtoll AUTOCR TRIGSEL LL_SPI_SetSelectedTrigger
* @param SPIx SPI Instance.
* @param Trigger This parameter can be one of the following values:
* @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG
* @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG
* @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG
* @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG
* @arg @ref LL_SPI_GRP1_EXTI4_TRG
* @arg @ref LL_SPI_GRP1_EXTI9_TRG
* @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG
* @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG
* @arg @ref LL_SPI_GRP1_COMP1_TRG
* @arg @ref LL_SPI_GRP1_COMP2_TRG
* @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG
* @arg @ref LL_SPI_GRP1_RTC_WUT_TRG
* @arg @ref LL_SPI_GRP2_LPDMA_CH0_TCF_TRG
* @arg @ref LL_SPI_GRP2_LPDMA_CH1_TCF_TRG
* @arg @ref LL_SPI_GRP2_LPDMA_CH2_TCF_TRG
* @arg @ref LL_SPI_GRP2_LPDMA_CH3_TCF_TRG
* @arg @ref LL_SPI_GRP2_EXTI4_TRG
* @arg @ref LL_SPI_GRP2_EXTI8_TRG
* @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG
* @arg @ref LL_SPI_GRP2_LPTIM3_CH1_TRG
* @arg @ref LL_SPI_GRP2_COMP1_TRG
* @arg @ref LL_SPI_GRP2_COMP2_TRG
* @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG
* @arg @ref LL_SPI_GRP2_RTC_WUT_TRG
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetSelectedTrigger(SPI_TypeDef *SPIx, uint32_t Trigger)
{
MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL, (Trigger & SPI_AUTOCR_TRIGSEL_Msk));
}
/**
* @brief Get the selected trigger
* @rmtoll AUTOCR TRIGSEL LL_SPI_GetSelectedTrigger
* @param SPIx SPI Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG
* @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG
* @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG
* @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG
* @arg @ref LL_SPI_GRP1_EXTI4_TRG
* @arg @ref LL_SPI_GRP1_EXTI9_TRG
* @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG
* @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG
* @arg @ref LL_SPI_GRP1_COMP1_TRG
* @arg @ref LL_SPI_GRP1_COMP2_TRG
* @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG
* @arg @ref LL_SPI_GRP1_RTC_WUT_TRG
* @arg @ref LL_SPI_GRP2_LPDMA_CH0_TCF_TRG
* @arg @ref LL_SPI_GRP2_LPDMA_CH1_TCF_TRG
* @arg @ref LL_SPI_GRP2_LPDMA_CH2_TCF_TRG
* @arg @ref LL_SPI_GRP2_LPDMA_CH3_TCF_TRG
* @arg @ref LL_SPI_GRP2_EXTI4_TRG
* @arg @ref LL_SPI_GRP2_EXTI8_TRG
* @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG
* @arg @ref LL_SPI_GRP2_LPTIM3_CH1_TRG
* @arg @ref LL_SPI_GRP2_COMP1_TRG
* @arg @ref LL_SPI_GRP2_COMP2_TRG
* @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG
* @arg @ref LL_SPI_GRP2_RTC_WUT_TRG
*/
__STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(SPI_TypeDef *SPIx)
{
if (IS_LL_SPI_GRP2_INSTANCE(SPIx))
{
return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2));
}
else
{
return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1));
}
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_SPI_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h
|
C
|
apache-2.0
| 95,282
|
/**
******************************************************************************
* @file stm32u5xx_ll_system.h
* @author MCD Application Team
* @brief Header file of SYSTEM LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL SYSTEM driver contains a set of generic APIs that can be
used by user:
(+) Some of the FLASH features need to be handled in the SYSTEM file.
(+) Access to DBGCMU registers
(+) Access to SYSCFG registers
(+) Access to VREFBUF registers
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_SYSTEM_H
#define STM32U5xx_LL_SYSTEM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
/** @defgroup SYSTEM_LL SYSTEM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
* @{
*/
/**
* @brief Power-down in Run mode Flash key
*/
#define LL_FLASH_PDKEY1_1 0x04152637U /*!< Flash Bank1 power down key1 */
#define LL_FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash Bank1 power down key2: used with FLASH_PDKEY1
to unlock the RUN_PD bit in FLASH_ACR */
#define LL_FLASH_PDKEY2_1 0x40516273U /*!< Flash Bank2 power down key1 */
#define LL_FLASH_PDKEY2_2 0xAFBFCFDFU /*!< Flash Bank2 power down key2: used with FLASH_PDKEY2_1
to unlock the RUN_PD bit in FLASH_ACR */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection
* @{
*/
#define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell
(available in the SYSCFG_CCVR)*/
#define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation
cell code register (SYSCFG_CCCR)*/
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_CS2 SYSCFG VddIO2 compensation cell Code selection
* @{
*/
#define LL_SYSCFG_VDDIO2_CELL_CODE 0U /*VDDIO2 I/Os code from the cell
(available in the SYSCFG_CCVR)*/
#define LL_SYSCFG_VDDIO2_REGISTER_CODE SYSCFG_CCCSR_CS2 /*VDDIO2 I/Os code from the SYSCFG compensation
cell code register (SYSCFG_CCCR)*/
/**
* @}
*/
#if defined(SYSCFG_CCCSR_CS3)
/** @defgroup SYSTEM_LL_EC_CS3 SYSCFG VddHSPI compensation cell Code selection
* @{
*/
#define LL_SYSCFG_VDDHSPI_CELL_CODE 0U /*VDD HSPI I/Os code from the cell
(available in the SYSCFG_CCVR)*/
#define LL_SYSCFG_VDDHSPI_REGISTER_CODE SYSCFG_CCCSR_CS3 /*VDD HSPI I/Os code from the SYSCFG compensation
cell code register (SYSCFG_CCCR)*/
/**
* @}
*/
#endif /* SYSCFG_CCCSR_CS3 */
/** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE STATUS
* @{
*/
#define LL_SYSCFG_MEMORIES_ERASE_ON_GOING 0U /*Memory erase on going*/
#define LL_SYSCFG_MEMORIES_ERASE_ENDED SYSCFG_MESR_MCLR /*Memory erase done */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
* @{
*/
/** @defgroup SYSTEM_LL_EC_FASTMODEPLUS SYSCFG FASTMODEPLUS
* @{
*/
#define LL_SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define LL_SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define LL_SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define LL_SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
* @{
*/
#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
with Break Input of TIM1/8/15/16/17 */
#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
with TIM1/8/15/16/17 Break Input and also the PVDE
and PLS bits of the Power Control Interface */
#define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal
with Break Input of TIM1/8/15/16/17 */
#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33
with Break Input of TIM1/15/16/17 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
* @note Only available when system implements security (TZEN=1)
* @{
*/
#define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */
#define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */
#define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */
#define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */
#define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */
#define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
* @{
*/
#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
* @{
*/
#define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1FZR2_DBG_FDCAN_STOP /*!< The counter clock of FDCAN is stopped when the core is halted*/
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB3_GRP1_I2C3_STOP DBGMCU_APB3FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/
#define LL_DBGMCU_APB3_GRP1_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
#define LL_DBGMCU_APB3_GRP1_LPTIM3_STOP DBGMCU_APB3FZR_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted*/
#define LL_DBGMCU_APB3_GRP1_LPTIM4_STOP DBGMCU_APB3FZR_DBG_LPTIM4_STOP /*!< The counter clock of LPTIM4 is stopped when the core is halted*/
#define LL_DBGMCU_APB3_GRP1_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP DBGMCU_AHB1FZR_DBG_GPDMA0_STOP /*!< The counter clock of GPDMA0 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_STOP /*!< The counter clock of GPDMA1 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP DBGMCU_AHB1FZR_DBG_GPDMA2_STOP /*!< The counter clock of GPDMA2 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP DBGMCU_AHB1FZR_DBG_GPDMA3_STOP /*!< The counter clock of GPDMA3 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP DBGMCU_AHB1FZR_DBG_GPDMA4_STOP /*!< The counter clock of GPDMA4 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP DBGMCU_AHB1FZR_DBG_GPDMA5_STOP /*!< The counter clock of GPDMA5 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP DBGMCU_AHB1FZR_DBG_GPDMA6_STOP /*!< The counter clock of GPDMA6 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP DBGMCU_AHB1FZR_DBG_GPDMA7_STOP /*!< The counter clock of GPDMA7 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP DBGMCU_AHB1FZR_DBG_GPDMA8_STOP /*!< The counter clock of GPDMA8 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP DBGMCU_AHB1FZR_DBG_GPDMA9_STOP /*!< The counter clock of GPDMA9 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP DBGMCU_AHB1FZR_DBG_GPDMA10_STOP /*!< The counter clock of GPDMA10 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP DBGMCU_AHB1FZR_DBG_GPDMA11_STOP /*!< The counter clock of GPDMA11 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP DBGMCU_AHB1FZR_DBG_GPDMA12_STOP /*!< The counter clock of GPDMA12 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP DBGMCU_AHB1FZR_DBG_GPDMA13_STOP /*!< The counter clock of GPDMA13 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP DBGMCU_AHB1FZR_DBG_GPDMA14_STOP /*!< The counter clock of GPDMA14 is stopped when the core is halted*/
#define LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP DBGMCU_AHB1FZR_DBG_GPDMA15_STOP /*!< The counter clock of GPDMA15 is stopped when the core is halted*/
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_AHB3_GRP1_STOP_IP DBGMCU AHB3 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP DBGMCU_AHB3FZR_DBG_LPDMA0_STOP /*!< The counter clock of LPDMA0 is stopped when the core is halted*/
#define LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP DBGMCU_AHB3FZR_DBG_LPDMA1_STOP /*!< The counter clock of LPDMA1 is stopped when the core is halted*/
#define LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP DBGMCU_AHB3FZR_DBG_LPDMA2_STOP /*!< The counter clock of LPDMA2 is stopped when the core is halted*/
#define LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP DBGMCU_AHB3FZR_DBG_LPDMA3_STOP /*!< The counter clock of LPDMA3 is stopped when the core is halted*/
/**
* @}
*/
#if defined(VREFBUF)
/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
* @{
*/
#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */
#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 0 (VREF_OUT3) */
#define LL_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_2 /*!< Voltage reference scale 1 (VREF_OUT4) */
/**
* @}
*/
#endif /* VREFBUF */
/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
* @{
*/
#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH zero wait state */
#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH one wait state */
#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH two wait states */
#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH three wait states */
#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH four wait states */
#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait states */
#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
* @{
*/
/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
* @{
*/
/**
* @brief Enable I/O analog switches supplied by VDD.
* @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_EnableAnalogSwitchVdd
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableAnalogSwitchVdd(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
}
/**
* @brief Disable I/O analog switches supplied by VDD.
* @note I/O analog switches are supplied by VDDA or booster
* when booster in on.
* Dedicated voltage booster (supplied by VDD) is the recommended
* configuration with low VDDA voltage operation.
* @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_DisableAnalogSwitchVdd
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableAnalogSwitchVdd(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
}
/**
* @brief Enable I/O analog switch voltage booster.
* @note When voltage booster is enabled, I/O analog switches are supplied
* by a dedicated voltage booster, from VDD power domain. This is
* the recommended configuration with low VDDA voltage operation.
* @note The I/O analog switch voltage booster is relevant for peripherals
* using I/O in analog input: ADC, COMP, OPAMP.
* However, COMP and OPAMP inputs have a high impedance and
* voltage booster do not impact performance significantly.
* Therefore, the voltage booster is mainly intended for
* usage with ADC.
* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Disable I/O analog switch voltage booster.
* @note When voltage booster is enabled, I/O analog switches are supplied
* by a dedicated voltage booster, from VDD power domain. This is
* the recommended configuration with low VDDA voltage operation.
* @note The I/O analog switch voltage booster is relevant for peripherals
* using I/O in analog input: ADC, COMP, OPAMP.
* However, COMP and OPAMP inputs have a high impedance and
* voltage booster do not impact performance significantly.
* Therefore, the voltage booster is mainly intended for
* usage with ADC.
* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Enable the fast mode plus driving capability.
* @rmtoll SYSCFG_CFGR1 PBx_FMP LL_SYSCFG_EnableFastModePlus
* @param ConfigFastModePlus This parameter can be a combination of the following values:
* @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6
* @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7
* @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8
* @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
}
/**
* @brief Disable the fast mode plus driving capability.
* @rmtoll SYSCFG_CFGR1 PBx_FMP LL_SYSCFG_DisableFastModePlus
* @param ConfigFastModePlus This parameter can be a combination of the following values:
* @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6
* @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7
* @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8
* @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
}
/**
* @brief Enable Floating Point Unit Invalid operation Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
{
SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
}
/**
* @brief Enable Floating Point Unit Divide-by-zero Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
{
SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
}
/**
* @brief Enable Floating Point Unit Underflow Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
{
SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
}
/**
* @brief Enable Floating Point Unit Overflow Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
{
SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
}
/**
* @brief Enable Floating Point Unit Input denormal Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
{
SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
}
/**
* @brief Enable Floating Point Unit Inexact Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
{
SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
}
/**
* @brief Disable Floating Point Unit Invalid operation Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
{
CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
}
/**
* @brief Disable Floating Point Unit Divide-by-zero Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
{
CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
}
/**
* @brief Disable Floating Point Unit Underflow Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
{
CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
}
/**
* @brief Disable Floating Point Unit Overflow Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
{
CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
}
/**
* @brief Disable Floating Point Unit Input denormal Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
{
CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
}
/**
* @brief Disable Floating Point Unit Inexact Interrupt
* @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
{
CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
}
/**
* @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
{
return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0) == SYSCFG_FPUIMR_FPU_IE_0) ? 1UL : 0UL);
}
/**
* @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
{
return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1) == SYSCFG_FPUIMR_FPU_IE_1) ? 1UL : 0UL);
}
/**
* @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
{
return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2) == SYSCFG_FPUIMR_FPU_IE_2) ? 1UL : 0UL);
}
/**
* @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
{
return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3) == SYSCFG_FPUIMR_FPU_IE_3) ? 1UL : 0UL);
}
/**
* @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
{
return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4) == SYSCFG_FPUIMR_FPU_IE_4) ? 1UL : 0UL);
}
/**
* @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
{
return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5) == SYSCFG_FPUIMR_FPU_IE_5) ? 1UL : 0UL);
}
/**
* @brief Set connections to TIM1/8/15/16/17 Break inputs
* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
* SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
* SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
* SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
* @param Break This parameter can be a combination of the following values:
* @arg @ref LL_SYSCFG_TIMBREAK_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_PVD
* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
{
MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
}
/**
* @brief Get connections to TIM1/8/15/16/17 Break inputs
* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
* SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
* SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
* SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
* @retval Returned value can be can be a combination of the following values:
* @arg @ref LL_SYSCFG_TIMBREAK_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_PVD
* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | \
SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
}
/** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management
* @{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Configure Secure mode
* @note Only available from secure state when system implements security (TZEN=1)
* @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
* SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
* SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
* @param Configuration This parameter shall be the full combination
* of the following values:
* @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
* @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
* @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration)
{
WRITE_REG(SYSCFG->SECCFGR, Configuration);
}
#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief Get Secure mode configuration
* @note Only available when system implements security (TZEN=1)
* @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n
* SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n
* SECCFGR FPUSEC LL_SYSCFG_ConfigSecure
* @retval Returned value is the combination of the following values:
* @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
* @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
* @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void)
{
return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU));
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup SYSTEM_LL_EF_COMPENSATION SYSCFG COMPENSATION
* @{
*/
/**
* @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD
* @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue
* @retval Returned value is the PMOS compensation cell
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV1));
}
/**
* @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD
* @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue
* @retval Returned value is the NMOS compensation cell
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV1));
}
/**
* @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2
* @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue
* @retval Returned value is the PMOS compensation cell
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV2));
}
/**
* @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2
* @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue
* @retval Returned value is the NMOS compensation cell
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV2));
}
#if defined(SYSCFG_CCVR_PCV3)
/**
* @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD
* @rmtoll CCVR PCV3 LL_SYSCFG_GetPMOSVddHSPICompensationValue
* @retval Returned value is the PMOS compensation cell
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationValue(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV3));
}
/**
* @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD
* @rmtoll CCVR NCV3 LL_SYSCFG_GetNMOSVddHSPICompensationValue
* @retval Returned value is the NMOS compensation cell
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationValue(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV3));
}
#endif /* SYSCFG_CCVR_PCV3 */
/**
* @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD
* @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode
* @param PMOSCode PMOS compensation code
* This code is applied to the PMOS compensation cell when the CS1 bit of the
* SYSCFG_CCCSR is set
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode)
{
MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC1, PMOSCode << SYSCFG_CCCR_PCC1_Pos);
}
/**
* @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD
* @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode
* @retval Returned value is the PMOS compensation cell
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC1));
}
/**
* @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2
* @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode
* @param PMOSCode PMOS compensation code
* This code is applied to the PMOS compensation cell when the CS2 bit of the
* SYSCFG_CCCSR is set
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode)
{
MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos);
}
/**
* @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2
* @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode
* @retval Returned value is the PMOS compensation
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC2));
}
#if defined(SYSCFG_CCCR_PCC3)
/**
* @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD
* @rmtoll CCCR PCC3 LL_SYSCFG_SetPMOSVddHSPICompensationCode
* @param PMOSCode PMOS compensation code
* This code is applied to the PMOS compensation cell when the CS3 bit of the
* SYSCFG_CCCSR is set
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode)
{
MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC3, PMOSCode << SYSCFG_CCCR_PCC3_Pos);
}
/**
* @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD
* @rmtoll CCCR PCC3 LL_SYSCFG_GetPMOSVddHSPICompensationCode
* @retval Returned value is the PMOS compensation
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationCode(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC3));
}
#endif /* SYSCFG_CCCR_PCC3 */
/**
* @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD
* @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode
* @param NMOSCode NMOS compensation code
* This code is applied to the NMOS compensation cell when the CS2 bit of the
* SYSCFG_CMPCR is set
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode)
{
MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC1, NMOSCode << SYSCFG_CCCR_NCC1_Pos);
}
/**
* @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD
* @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode
* @retval Returned value is the Vdd compensation cell code for NMOS transistors
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC1));
}
/**
* @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2
* @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode
* @param NMOSCode NMOS compensation code
* This code is applied to the NMOS compensation cell when the CS2 bit of the
* SYSCFG_CMPCR is set
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode)
{
MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos);
}
/**
* @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2
* @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode
* @retval Returned value is the NMOS compensation cell code
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC2));
}
#if defined(SYSCFG_CCCR_NCC3)
/**
* @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD
* @rmtoll CCCR NCC3 LL_SYSCFG_SetNMOSVddHSPICompensationCode
* @param NMOSCode NMOS compensation code
* This code is applied to the NMOS compensation cell when the CS3 bit of the
* SYSCFG_CCCSR is set
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode)
{
MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC3, NMOSCode << SYSCFG_CCCR_NCC3_Pos);
}
/**
* @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD
* @rmtoll CCCR NCC3 LL_SYSCFG_GetNMOSVddHSPICompensationCode
* @retval Returned value is the NMOS compensation cell code
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationCode(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC3));
}
#endif /* SYSCFG_CCCR_NCC3 */
/**
* @brief Enable the Compensation Cell of GPIO supplied by VDD
* @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell
* @note The vdd compensation cell can be used only when the device supply
* voltage ranges from 1.71 to 3.6 V
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void)
{
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
}
/**
* @brief Enable the Compensation Cell of GPIO supplied by VDDIO2
* @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell
* @note The Vdd I/O compensation cell can be used only when the device supply
* voltage ranges from 1.08 to 3.6 V
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void)
{
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
}
#if defined(SYSCFG_CCCSR_EN3)
/**
* @brief Enable the Compensation Cell of HSPI IO supplied by VDD
* @rmtoll CCCSR EN3 LL_SYSCFG_EnableVddHSPICompensationCell
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableVddHSPICompensationCell(void)
{
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
}
#endif /* SYSCFG_CCCSR_EN3 */
/**
* @brief Disable the Compensation Cell of GPIO supplied by VDD
* @rmtoll CCCSR EN1 LL_SYSCFG_DisableVddCompensationCell
* @note The Vdd compensation cell can be used only when the device supply
* voltage ranges from 1.71 to 3.6 V
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void)
{
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
}
/**
* @brief Disable the Compensation Cell of GPIO supplied by VDDIO2
* @rmtoll CCCSR EN2 LL_SYSCFG_DisableVddIO2CompensationCell
* @note The Vdd I/O compensation cell can be used only when the device supply
* voltage ranges from 1.08 to 3.6 V
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void)
{
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
}
#if defined(SYSCFG_CCCSR_EN3)
/**
* @brief Disable the Compensation Cell of HSPI IO supplied by VDD
* @rmtoll CCCSR EN3 LL_SYSCFG_DisableVddHSPICompensationCell
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableVddHSPICompensationCell(void)
{
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
}
#endif /* SYSCFG_CCCSR_EN3 */
/**
* @brief Check if the Compensation Cell of GPIO supplied by VDD is enable
* @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void)
{
return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1) == SYSCFG_CCCSR_EN1) ? 1UL : 0UL);
}
/**
* @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enable
* @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void)
{
return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2) == SYSCFG_CCCSR_EN2) ? 1UL : 0UL);
}
#if defined(SYSCFG_CCCSR_EN3)
/**
* @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enable
* @rmtoll CCCSR EN3 LL_SYSCFG_IsEnabled_VddHSPICompensationCell
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void)
{
return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3) == SYSCFG_CCCSR_EN3) ? 1UL : 0UL);
}
#endif /* SYSCFG_CCCSR_EN3 */
/**
* @brief Get Compensation Cell ready Flag of GPIO supplied by VDD
* @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void)
{
return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY1) == (SYSCFG_CCCSR_RDY1)) ? 1UL : 0UL);
}
/**
* @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2
* @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void)
{
return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY2) == (SYSCFG_CCCSR_RDY2)) ? 1UL : 0UL);
}
#if defined(SYSCFG_CCCSR_RDY3)
/**
* @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD
* @rmtoll CCCSR RDY3 LL_SYSCFG_IsActiveFlag_VddHSPICMPCR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void)
{
return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY3) == (SYSCFG_CCCSR_RDY3)) ? 1UL : 0UL);
}
#endif /* SYSCFG_CCCSR_RDY3 */
/**
* @brief Set the compensation cell code selection of GPIO supplied by VDD
* @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode
* @param CompCode: Selects the code to be applied for the Vdd compensation cell
* This parameter can be one of the following values:
* @arg LL_SYSCFG_VDD_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
* @arg LL_SYSCFG_VDD_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode)
{
SET_BIT(SYSCFG->CCCSR, CompCode);
}
/**
* @brief Set the compensation cell code selection of GPIO supplied by VDDIO2
* @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode
* @param CompCode: Selects the code to be applied for the VddIO compensation cell
* This parameter can be one of the following values:
* @arg LL_SYSCFG_VDDIO2_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
* @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode)
{
SET_BIT(SYSCFG->CCCSR, CompCode);
}
#if defined(SYSCFG_CCCSR_CS3)
/**
* @brief Set the compensation cell code selection of HSPI IO supplied by VDD
* @rmtoll CCCSR CS3 LL_SYSCFG_SetVddHSPICellCompensationCode
* @param CompCode: Selects the code to be applied for the VddIO compensation cell
* This parameter can be one of the following values:
* @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
* @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode)
{
SET_BIT(SYSCFG->CCCSR, CompCode);
}
#endif /* SYSCFG_CCCSR_CS3 */
/**
* @brief Get the compensation cell code selection of GPIO supplied by VDD
* @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode
* @retval Returned value can be one of the following values:
* @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
* @arg LL_SYSCFG_VDD_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1));
}
/**
* @brief Get the compensation cell code selection of GPIO supplied by VDDIO2
* @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode
* @retval Returned value can be one of the following values:
* @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
* @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Selected Code is from the SYSCFG compensation
cell code register (SYSCFG_CCCR)
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2));
}
#if defined(SYSCFG_CCCSR_CS3)
/**
* @brief Get the compensation cell code selection of HSPI IO supplied by VDD
* @rmtoll CCCSR CS3 LL_SYSCFG_GetVddHSPICellCompensationCode
* @retval Returned value can be one of the following values:
* @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
* @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Selected Code is from the SYSCFG compensation
cell code register (SYSCFG_CCCR)
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetVddHSPICellCompensationCode(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS3));
}
#endif /* SYSCFG_CCCSR_CS3 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
* @{
*/
/**
* @brief Return the device identifier
* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
}
/**
* @brief Return the device revision identifier
* @note This field indicates the revision of the device.
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
}
/**
* @brief Enable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Enable the Debug Clock Trace
* @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
}
/**
* @brief Disable the Debug Clock Trace
* @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
}
/**
* @brief Check if clock trace is enabled or disabled.
* @rmtoll DBGMCU_CR_TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
{
return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN) == DBGMCU_CR_TRACE_CLKEN) ? 1UL : 0UL);
}
/**
* @brief Set Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
* @param PinAssignment This parameter can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
{
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
}
/**
* @brief Get Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
* @retval Returned value can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
{
return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
}
/**
* @brief Freeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->APB1FZR1, Periphs);
}
/**
* @brief Freeze APB1 peripherals (group2 peripherals)
* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->APB1FZR2, Periphs);
}
/**
* @brief Unfreeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
}
/**
* @brief Unfreeze APB1 peripherals (group2 peripherals)
* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
}
/**
* @brief Freeze APB2 peripherals
* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->APB2FZR, Periphs);
}
/**
* @brief Unfreeze APB2 peripherals
* @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
}
/**
* @brief Freeze APB3 peripherals
* @rmtoll DBGMCU_APB3FZ DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
* @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
* @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP
* @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP
* @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->APB3FZR, Periphs);
}
/**
* @brief Unfreeze APB3 peripherals
* @rmtoll DBGMCU_APB3FZR DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
* @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
* @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP
* @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP
* @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->APB3FZR, Periphs);
}
/**
* @brief Freeze AHB1 peripherals
* @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->AHB1FZR, Periphs);
}
/**
* @brief Unfreeze AHB1 peripherals
* @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->AHB1FZR, Periphs);
}
/**
* @brief Freeze AHB3 peripherals
* @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP LL_DBGMCU_AHB3_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP
* @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP
* @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP
* @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->AHB3FZR, Periphs);
}
/**
* @brief Unfreeze AHB3 peripherals
* @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP LL_DBGMCU_AHB3_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP
* @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP
* @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP
* @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->AHB3FZR, Periphs);
}
/**
* @}
*/
#if defined(VREFBUF)
/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
* @{
*/
/**
* @brief Enable Internal voltage reference
* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_Enable(void)
{
SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
/**
* @brief Disable Internal voltage reference
* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_Disable(void)
{
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
/**
* @brief Enable high impedance (VREF+pin is high impedance)
* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
{
SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
}
/**
* @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
{
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
}
/**
* @brief Set the Voltage reference scale
* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
* @param Scale This parameter can be one of the following values:
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
{
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
}
/**
* @brief Get the Voltage reference scale
* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
* @retval Returned value can be one of the following values:
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
*/
__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
{
return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
}
/**
* @brief Check if Voltage reference buffer is ready
* @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
{
return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL);
}
/**
* @brief Get the trimming code for VREFBUF calibration
* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
* @retval Between 0 and 0x3F
*/
__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
{
return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
}
/**
* @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
* @param Value Between 0 and 0x3F
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
{
WRITE_REG(VREFBUF->CCR, Value);
}
/**
* @}
*/
#endif /* VREFBUF */
/** @defgroup SYSTEM_LL_EF_FLASH FLASH
* @{
*/
/**
* @brief Set FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
* @param Latency This parameter can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
* @arg @ref LL_FLASH_LATENCY_3
* @arg @ref LL_FLASH_LATENCY_4
* @arg @ref LL_FLASH_LATENCY_5
* @arg @ref LL_FLASH_LATENCY_6
* @arg @ref LL_FLASH_LATENCY_7
* @arg @ref LL_FLASH_LATENCY_8
* @arg @ref LL_FLASH_LATENCY_9
* @arg @ref LL_FLASH_LATENCY_10
* @arg @ref LL_FLASH_LATENCY_11
* @arg @ref LL_FLASH_LATENCY_12
* @arg @ref LL_FLASH_LATENCY_13
* @arg @ref LL_FLASH_LATENCY_14
* @arg @ref LL_FLASH_LATENCY_15
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
}
/**
* @brief Get FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
* @retval Returned value can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
* @arg @ref LL_FLASH_LATENCY_3
* @arg @ref LL_FLASH_LATENCY_4
* @arg @ref LL_FLASH_LATENCY_5
* @arg @ref LL_FLASH_LATENCY_6
* @arg @ref LL_FLASH_LATENCY_7
* @arg @ref LL_FLASH_LATENCY_8
* @arg @ref LL_FLASH_LATENCY_9
* @arg @ref LL_FLASH_LATENCY_10
* @arg @ref LL_FLASH_LATENCY_11
* @arg @ref LL_FLASH_LATENCY_12
* @arg @ref LL_FLASH_LATENCY_13
* @arg @ref LL_FLASH_LATENCY_14
* @arg @ref LL_FLASH_LATENCY_15
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
}
/**
* @brief Enable Flash Power-down mode during run mode or Low-power run mode
* @note Flash memory can be put in power-down mode only when the code is executed
* from RAM
* @note Flash must not be accessed when power down is enabled
* @note Flash must not be put in power-down while a program or an erase operation
* is on-going
* @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
* FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n
* FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown\n
* FLASH_PDKEYR PDKEY2_1 LL_FLASH_EnableRunPowerDown\n
* FLASH_PDKEYR PDKEY2_2 LL_FLASH_EnableRunPowerDown
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
{
/* Following values must be written consecutively to unlock the RUN_PD bit in
FLASH_ACR */
WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1);
WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2);
WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1);
WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2);
/*Request to enter flash in power mode */
SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1 | FLASH_ACR_PDREQ2);
}
/**
* @brief Enable flash Power-down mode during run mode or Low-power run mode of bank1
* @note Bank 1 of flash memory can be put in power-down mode only when the code is executed
* from RAM
* @note Bank1 of flash must not be accessed when power down is enabled
* @note Bank1 of flash must not be put in power-down while a program or an erase operation
* is on-going
* @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
* FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n
* FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown\n
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank1(void)
{
/* Following values must be written consecutively to unlock the RUN_PD bit in
FLASH_ACR */
WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1);
WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2);
/*Request to enter flash in power mode */
SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1);
}
/**
* @brief Enable flash Power-down mode during run mode or Low-power run mode of Bank2
* @note Bank 2 of flash memory can be put in power-down mode only when the code is executed
* from RAM
* @note Bank2 of flash must not be accessed when power down is enabled
* @note Bank2 of flash must not be put in power-down while a program or an erase operation
* is on-going
* @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
* FLASH_PDKEYR PDKEY2_1 LL_FLASH_EnableRunPowerDown\n
* FLASH_PDKEYR PDKEY2_2 LL_FLASH_EnableRunPowerDown\n
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank2(void)
{
/* Following values must be written consecutively to unlock the RUN_PD bit in
FLASH_ACR */
WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1);
WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2);
/*Request to enter flash in power mode */
SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2);
}
/**
* @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
* @note Flash must not be put in power-down while a program or an erase operation
* is on-going
* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
}
/**
* @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
}
/**
* @}
*/
/** @defgroup SYSTEM_LL_EF_ERASE_MEMORIE_STATUS ERASE MEMORIE STATUS
* @{
*/
/**
* @brief Clear Status of End of Erase for ICACHE and PKA RAMs
* @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void)
{
SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE);
}
/**
* @brief Get Status of End of Erase for ICACHE and PKA RAMs
* @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus
* @retval Returned value can be one of the following values:
* @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
* @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void)
{
return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE));
}
/**
* @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
* @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void)
{
SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR);
}
/**
* @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
* @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus
* @retval Returned value can be one of the following values:
* @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
* @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void)
{
return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR));
}
/**
* @}
*/
#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32u5xx_LL_SYSTEM_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h
|
C
|
apache-2.0
| 69,210
|
/**
******************************************************************************
* @file stm32u5xx_ll_tim.h
* @author MCD Application Team
* @brief Header file of TIM LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32U5xx_LL_TIM_H
#define __STM32U5xx_LL_TIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (TIM1) \
|| defined (TIM2) \
|| defined (TIM3) \
|| defined (TIM4) \
|| defined (TIM5) \
|| defined (TIM6) \
|| defined (TIM7) \
|| defined (TIM8) \
|| defined (TIM15) \
|| defined (TIM16) \
|| defined (TIM17) \
|| defined (TIM20)
/** @defgroup TIM_LL TIM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup TIM_LL_Private_Variables TIM Private Variables
* @{
*/
static const uint8_t OFFSET_TAB_CCMRx[] =
{
0x00U, /* 0: TIMx_CH1 */
0x00U, /* 1: TIMx_CH1N */
0x00U, /* 2: TIMx_CH2 */
0x00U, /* 3: TIMx_CH2N */
0x04U, /* 4: TIMx_CH3 */
0x04U, /* 5: TIMx_CH3N */
0x04U, /* 6: TIMx_CH4 */
0x04U, /* 7: TIMx_CH4N */
0x38U, /* 8: TIMx_CH5 */
0x38U /* 9: TIMx_CH6 */
};
static const uint8_t SHIFT_TAB_OCxx[] =
{
0U, /* 0: OC1M, OC1FE, OC1PE */
0U, /* 1: - NA */
8U, /* 2: OC2M, OC2FE, OC2PE */
0U, /* 3: - NA */
0U, /* 4: OC3M, OC3FE, OC3PE */
0U, /* 5: - NA */
8U, /* 6: OC4M, OC4FE, OC4PE */
0U, /* 7: - NA */
0U, /* 8: OC5M, OC5FE, OC5PE */
8U /* 9: OC6M, OC6FE, OC6PE */
};
static const uint8_t SHIFT_TAB_ICxx[] =
{
0U, /* 0: CC1S, IC1PSC, IC1F */
0U, /* 1: - NA */
8U, /* 2: CC2S, IC2PSC, IC2F */
0U, /* 3: - NA */
0U, /* 4: CC3S, IC3PSC, IC3F */
0U, /* 5: - NA */
8U, /* 6: CC4S, IC4PSC, IC4F */
0U, /* 7: - NA */
0U, /* 8: - NA */
0U /* 9: - NA */
};
static const uint8_t SHIFT_TAB_CCxP[] =
{
0U, /* 0: CC1P */
2U, /* 1: CC1NP */
4U, /* 2: CC2P */
6U, /* 3: CC2NP */
8U, /* 4: CC3P */
10U, /* 5: CC3NP */
12U, /* 6: CC4P */
14U, /* 7: CC4NP */
16U, /* 8: CC5P */
20U /* 9: CC6P */
};
static const uint8_t SHIFT_TAB_OISx[] =
{
0U, /* 0: OIS1 */
1U, /* 1: OIS1N */
2U, /* 2: OIS2 */
3U, /* 3: OIS2N */
4U, /* 4: OIS3 */
5U, /* 5: OIS3N */
6U, /* 6: OIS4 */
7U, /* 7: OIS4N */
8U, /* 8: OIS5 */
10U /* 9: OIS6 */
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup TIM_LL_Private_Constants TIM Private Constants
* @{
*/
/* Defines used for the bit position in the register and perform offsets */
#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
/* Generic bit definitions for TIMx_AF1 register */
#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
#define DT_DELAY_1 ((uint8_t)0x7F)
#define DT_DELAY_2 ((uint8_t)0x3F)
#define DT_DELAY_3 ((uint8_t)0x1F)
#define DT_DELAY_4 ((uint8_t)0x1F)
/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
#define DT_RANGE_1 ((uint8_t)0x00)
#define DT_RANGE_2 ((uint8_t)0x80)
#define DT_RANGE_3 ((uint8_t)0xC0)
#define DT_RANGE_4 ((uint8_t)0xE0)
/** Legacy definitions for compatibility purpose
@cond 0
*/
/**
@endcond
*/
#define OCREF_CLEAR_SELECT_POS (28U)
#define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup TIM_LL_Private_Macros TIM Private Macros
* @{
*/
/** @brief Convert channel id into channel index.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval none
*/
#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
/** @brief Calculate the deadtime sampling period(in ps).
* @param __TIMCLK__ timer input clock frequency (in Hz).
* @param __CKD__ This parameter can be one of the following values:
* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
* @retval none
*/
#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
* @{
*/
/**
* @brief TIM Time Base configuration structure definition.
*/
typedef struct
{
uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetPrescaler().*/
uint32_t CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetCounterMode().*/
uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
Some timer instances may support 32 bits counters. In that case this parameter must
be a number between 0x0000 and 0xFFFFFFFF.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetAutoReload().*/
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetClockDivision().*/
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
GP timers: this parameter must be a number between Min_Data = 0x00 and
Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
/**
* @brief TIM Output Compare configuration structure definition.
*/
typedef struct
{
uint32_t OCMode; /*!< Specifies the output mode.
This parameter can be a value of @ref TIM_LL_EC_OCMODE.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetMode().*/
uint32_t OCState; /*!< Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
This feature can be modified afterwards using unitary functions
@ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
This feature can be modified afterwards using unitary functions
@ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
This feature can be modified afterwards using unitary function
LL_TIM_OC_SetCompareCHx (x=1..6).*/
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetPolarity().*/
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetPolarity().*/
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetIdleState().*/
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetIdleState().*/
} LL_TIM_OC_InitTypeDef;
/**
* @brief TIM Input Capture configuration structure definition.
*/
typedef struct
{
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPolarity().*/
uint32_t ICActiveInput; /*!< Specifies the input.
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetActiveInput().*/
uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPrescaler().*/
uint32_t ICFilter; /*!< Specifies the input capture filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetFilter().*/
} LL_TIM_IC_InitTypeDef;
/**
* @brief TIM Encoder interface configuration structure definition.
*/
typedef struct
{
uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetEncoderMode().*/
uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPolarity().*/
uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetActiveInput().*/
uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetFilter().*/
uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPolarity().*/
uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetActiveInput().*/
uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetFilter().*/
} LL_TIM_ENCODER_InitTypeDef;
/**
* @brief TIM Hall sensor interface configuration structure definition.
*/
typedef struct
{
uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPolarity().*/
uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
Prescaler must be set to get a maximum counter period longer than the
time interval between 2 consecutive changes on the Hall inputs.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
This parameter can be a value of
@ref TIM_LL_EC_IC_FILTER.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetFilter().*/
uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
A positive pulse (TRGO event) is generated with a programmable delay every time
a change occurs on the Hall inputs.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetCompareCH2().*/
} LL_TIM_HALLSENSOR_InitTypeDef;
/**
* @brief BDTR (Break and Dead Time) structure definition
*/
typedef struct
{
uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
This parameter can be a value of @ref TIM_LL_EC_OSSR
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetOffStates()
@note This bit-field cannot be modified as long as LOCK level 2 has been
programmed. */
uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
This parameter can be a value of @ref TIM_LL_EC_OSSI
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetOffStates()
@note This bit-field cannot be modified as long as LOCK level 2 has been
programmed. */
uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
register has been written, their content is frozen until the next reset.*/
uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
switching-on of the outputs.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetDeadTime()
@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
programmed. */
uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
This feature can be modified afterwards using unitary functions
@ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
This feature can be modified afterwards using unitary function
@ref LL_TIM_ConfigBRK()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
This feature can be modified afterwards using unitary function
@ref LL_TIM_ConfigBRK()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
This feature can be modified afterwards using unitary functions
@ref LL_TIM_ConfigBRK()
@note Bidirectional break input is only supported by advanced timers instances.
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
This feature can be modified afterwards using unitary functions
@ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
This feature can be modified afterwards using unitary function
@ref LL_TIM_ConfigBRK2()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
This feature can be modified afterwards using unitary function
@ref LL_TIM_ConfigBRK2()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
This feature can be modified afterwards using unitary functions
@ref LL_TIM_ConfigBRK2()
@note Bidirectional break input is only supported by advanced timers instances.
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
This feature can be modified afterwards using unitary functions
@ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
} LL_TIM_BDTR_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
* @{
*/
/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_TIM_ReadReg function.
* @{
*/
#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
#define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
#define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
#define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
#define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
* @{
*/
#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
* @{
*/
#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
/**
* @}
*/
/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
* @{
*/
#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup TIM_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
* @{
*/
#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
#define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
#define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
#define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
/**
* @}
*/
/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
* @{
*/
#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
* @{
*/
#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
* @{
*/
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
/**
* @}
*/
/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
* @{
*/
#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
/**
* @}
*/
/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
* @{
*/
#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
/**
* @}
*/
/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
* @{
*/
#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
/**
* @}
*/
/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
* @{
*/
#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
/**
* @}
*/
/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
* @{
*/
#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_CHANNEL Channel
* @{
*/
#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
#define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
* @{
*/
#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
* @{
*/
#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
#define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
#define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
/**
* @}
*/
/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
* @{
*/
#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
/**
* @}
*/
/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
* @{
*/
#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
/**
* @}
*/
/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
* @{
*/
#define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
* @{
*/
#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
* @{
*/
#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
/**
* @}
*/
/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
* @{
*/
#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
* @{
*/
#define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
/**
* @}
*/
/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
* @{
*/
#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
* @{
*/
#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
#define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
#define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TRGO Trigger Output
* @{
*/
#define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
#define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
* @{
*/
#define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
* @{
*/
#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
#define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
the counter are controlled. */
/**
* @}
*/
/** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
* @{
*/
#define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
#define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TS Trigger Selection
* @{
*/
#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
#define LL_TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
#define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
#define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
#define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
#define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
#define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
* @{
*/
#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
* @{
*/
#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
* @{
*/
#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
* @{
*/
#define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM1_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
#define LL_TIM_TIM1_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
#define LL_TIM_TIM1_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
#if defined(ADC2)
#define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 2 */
#define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
#endif /* ADC2*/
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
#if defined(ADC2)
#define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 1 */
#endif /* ADC2*/
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
* @{
*/
#define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM2_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
#define LL_TIM_TIM2_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
#define LL_TIM_TIM2_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
#if defined(DCMI) && defined(LTDC)
#define LL_TIM_TIM2_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */
#define LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */
#endif /* DCMI && LTDC */
#define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
#define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
#define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */
#define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
#if defined(DSI)
#define LL_TIM_TIM2_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to DSI_TE */
#endif /* DSI */
#if defined(DCMI) && defined(LTDC)
#define LL_TIM_TIM2_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */
#define LL_TIM_TIM2_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */
#endif /* DCMI && LTDC */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
* @{
*/
#define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM3_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
#define LL_TIM_TIM3_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
#define LL_TIM_TIM3_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
#if defined(DCMI) && defined(LTDC)
#define LL_TIM_TIM3_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */
#define LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */
#endif /* DCMI && LTDC */
#define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
#define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
#if defined(DSI)
#define LL_TIM_TIM3_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DSI_TE */
#endif /* DSI */
#define LL_TIM_TIM3_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 1 */
#define LL_TIM_TIM3_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC1 analog watchdog 2 */
#define LL_TIM_TIM3_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 3 */
#if defined(DCMI) && defined(LTDC)
#define LL_TIM_TIM3_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */
#define LL_TIM_TIM3_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */
#endif /* DCMI && LTDC */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
* @{
*/
#define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM4_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
#define LL_TIM_TIM4_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
#define LL_TIM_TIM4_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
#if defined(DCMI) && defined(LTDC)
#define LL_TIM_TIM4_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */
#define LL_TIM_TIM4_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */
#endif /* DCMI && LTDC */
#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
#define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
#if defined(DSI)
#define LL_TIM_TIM4_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DSI_TE */
#endif /* DSI */
#if defined(ADC2)
#define LL_TIM_TIM4_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 AWD1 */
#define LL_TIM_TIM4_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ETR input is connected to ADC2 AWD2 */
#define LL_TIM_TIM4_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 AWD3 */
#endif /* ADC2 */
#if defined(DCMI) && defined(LTDC)
#define LL_TIM_TIM4_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */
#define LL_TIM_TIM4_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */
#endif /* DCMI && LTDC */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
* @{
*/
#define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM5_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM5_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM5_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
#define LL_TIM_TIM5_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
#define LL_TIM_TIM5_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
#if defined(DCMI) && defined(LTDC)
#define LL_TIM_TIM5_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */
#define LL_TIM_TIM5_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */
#endif /* DCMI && LTDC */
#define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
#define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
#if defined(DSI)
#define LL_TIM_TIM5_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DSI_TE */
#endif /* DSI */
#if defined(DCMI) && defined(LTDC)
#define LL_TIM_TIM5_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */
#define LL_TIM_TIM5_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */
#endif /* DCMI && LTDC */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
* @{
*/
#define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM8_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
#define LL_TIM_TIM8_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
#define LL_TIM_TIM8_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
#if defined (ADC2)
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ADC2 AWD2 */
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 AWD3 */
#endif /* ADC2 */
#define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */
#define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
#define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
#define LL_TIM_TIM8_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
#define LL_TIM_TIM8_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
#define LL_TIM_TIM8_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
#if defined (ADC2)
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ADC2 AWD1 */
#endif /* ADC2 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
* @{
*/
#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
* @{
*/
#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
* @{
*/
#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
* @{
*/
#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_OSSI OSSI
* @{
*/
#define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
/**
* @}
*/
/** @defgroup TIM_LL_EC_OSSR OSSR
* @{
*/
#define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
* @{
*/
#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
* @{
*/
#define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
#define LL_TIM_BKIN_SOURCE_MDF1 TIM1_AF1_BKDF1BK0E /*!< internal signal: Digital filter break output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
* @{
*/
#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
* @{
*/
#define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
* @{
*/
#define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
/**
* @}
*/
/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
* @{
*/
#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
/**
* @}
*/
/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
* @{
*/
#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
/**
* @}
*/
/** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
* @{
*/
#define LL_TIM_DMA_UPDATE TIM_DCR_DBSS_0 /*!< Transfer source is update event */
#define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 /*!< Transfer source is CC1 event */
#define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC2 event */
#define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 /*!< Transfer source is CC3 event */
#define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is CC4 event */
#define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is COM event */
#define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is trigger event */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000UL /*!< TIM1 TI1 is connected to GPIO */
#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 TI1 is connected to COMP1 output */
#define LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 TI1 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2 TI1 is connected to GPIO */
#define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 TI1 is connected to COMP1 output */
#define LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 TI1 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM16 External Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000UL /*!< TIM2 TI2 is connected to GPIO */
#define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 TI2 is connected to COMP1 output */
#define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 TI2 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
* @{
*/
#define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000UL /*!< TIM2 TI4 is connected to COMP1 output */
#define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 TI4 is connected to COMP1 output */
#define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 TI4 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3 TI1 is connected to GPIO */
#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 TI1 is connected to COMP1 output */
#define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 TI1 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 External Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000UL /*!< TIM3 TI2 is connected to GPIO */
#define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 TI2 is connected to COMP1 output */
#define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 TI2 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 External Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000UL /*!< TIM4 TI1 is connected to GPIO */
#define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 TI1 is connected to COMP1 output */
#define LL_TIM_TIM4_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4 TI1 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 External Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000UL /*!< TIM4 TI2 is connected to GPIO */
#define LL_TIM_TIM4_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4 TI2 is connected to COMP1 output */
#define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4 TI2 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 External Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000UL /*!< TIM5 TI1 is connected to GPIO */
#define LL_TIM_TIM5_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5 TI1 is connected to LSI */
#define LL_TIM_TIM5_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5 TI1 is connected to LSE */
#define LL_TIM_TIM5_TI1_RMP_RTC (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 TI1 is connected to RTC Wakeup */
#define LL_TIM_TIM5_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5 TI1 is connected to COMP1 output */
#define LL_TIM_TIM5_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5 TI1 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM5_TI2_RMP TIM5 External Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM5_TI2_RMP_GPIO 0x00000000UL /*!< TIM5 TI2 is connected to GPIO */
#define LL_TIM_TIM5_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5 TI2 is connected to COMP1 output */
#define LL_TIM_TIM5_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5 TI2 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000UL /*!< TIM8 TI1 is connected to GPIO */
#define LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8 TI1 is connected to COMP1 output */
#define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8 TI1 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000UL /*!< TIM15 TI1 is connected to GPIO */
#define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15 TI1 is connected to LSE */
#define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15 TI1 is connected to COMP1 output */
#define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15 TI1 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 External Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000UL /*!< TIM15 TI2 is connected to GPIO */
#define LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM15 TI2 is connected to COMP2 output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000UL /*!< TIM16 TI1 is connected to GPIO */
#define LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 TI1 is connected to MCO */
#define LL_TIM_TIM16_TI1_RMP_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to HSE DIV32 */
#define LL_TIM_TIM16_TI1_RMP_RTC TIM_TISEL_TI1SEL_2 /*!< TIM16 TI1 is connected to RTC */
#define LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to LSE */
#define LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 TI1 is connected to LSI */
#define LL_TIM_TIM16_TI1_RMP_MSIS_1024 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to MSIS/1024 */
#define LL_TIM_TIM16_TI1_RMP_MSIS_4 TIM_TISEL_TI1SEL_3 /*!< TIM16 TI1 is connected to MSIS/4 */
#define LL_TIM_TIM16_TI1_RMP_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to HSI/256 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17 TI1 is connected to GPIO */
#define LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 TI1 is connected to MCO */
#define LL_TIM_TIM17_TI1_RMP_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to HSE DIV32 */
#define LL_TIM_TIM17_TI1_RMP_RTC TIM_TISEL_TI1SEL_2 /*!< TIM17 TI1 is connected to RTC */
#define LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to LSE */
#define LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 TI1 is connected to LSI */
#define LL_TIM_TIM17_TI1_RMP_MSIS_1024 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to MSIS/1024 */
#define LL_TIM_TIM17_TI1_RMP_MSIS_4 TIM_TISEL_TI1SEL_3 /*!< TIM17 TI1 is connected to MSIS/4 */
#define LL_TIM_TIM17_TI1_RMP_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to HSI/256 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
* @{
*/
#define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_MSK /*!< OCREF_CLR_INT is connected to ETRF */
#define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
#define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
/**
* @}
*/
/** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
* @{
*/
#define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
#define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
#define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
/**
* @}
*/
/** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
* @{
*/
#define LL_TIM_INDEX_BLANK_ALWAYS 0x00000000U /*!< Index always active */
#define LL_TIM_INDEX_BLANK_TI3 TIM_ECR_IBLK_0 /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
#define LL_TIM_INDEX_BLANK_TI4 TIM_ECR_IBLK_1 /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
/**
* @}
*/
/** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
* @{
*/
#define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
#define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
#define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
#define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
#define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
#define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
* @{
*/
#define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
#define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
/**
* @}
*/
/** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
* @{
*/
#define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
#define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
#define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
#define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
#define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
#define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
#define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
#define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
/**
* @}
*/
/** Legacy definitions for compatibility purpose
@cond 0
*/
#define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
/**
@endcond
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
* @{
*/
/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in TIM register.
* @param __INSTANCE__ TIM Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in TIM register.
* @param __INSTANCE__ TIM Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
* @{
*/
/**
* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
* to TIMx_CNT register bit 31)
* @param __CNT__ Counter value
* @retval UIF status bit
*/
#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
/**
* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __CKD__ This parameter can be one of the following values:
* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
* @param __DT__ deadtime duration (in ns)
* @retval DTG[0:7]
*/
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
(uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
(((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
(uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
(__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
(((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
(uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
(__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
(((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
(uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
(__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
0U)
/**
* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __CNTCLK__ counter clock frequency (in Hz)
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __FREQ__ output signal frequency (in Hz)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
* output signal frequency.
* @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __FREQ__ output signal frequency (in Hz)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
(uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
/**
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare
* active/inactive delay.
* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @retval Compare value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
* output compare active/inactive delay.
* @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @retval Compare value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
* (when the timer operates in one pulse mode).
* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @param __PULSE__ pulse duration (in us)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
* pulse duration (when the timer operates in one pulse mode).
* @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @param __PULSE__ pulse duration (in us)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @brief HELPER macro retrieving the ratio of the input capture prescaler
* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
* @param __ICPSC__ This parameter can be one of the following values:
* @arg @ref LL_TIM_ICPSC_DIV1
* @arg @ref LL_TIM_ICPSC_DIV2
* @arg @ref LL_TIM_ICPSC_DIV4
* @arg @ref LL_TIM_ICPSC_DIV8
* @retval Input capture prescaler ratio (1, 2, 4 or 8)
*/
#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
* @{
*/
/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
* @{
*/
/**
* @brief Enable timer counter.
* @rmtoll CR1 CEN LL_TIM_EnableCounter
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR1, TIM_CR1_CEN);
}
/**
* @brief Disable timer counter.
* @rmtoll CR1 CEN LL_TIM_DisableCounter
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
}
/**
* @brief Indicates whether the timer counter is enabled.
* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
}
/**
* @brief Enable update event generation.
* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
* @brief Disable update event generation.
* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
* @brief Indicates whether update event generation is enabled.
* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
* @param TIMx Timer instance
* @retval Inverted state of bit (0 or 1).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
}
/**
* @brief Set update event source
* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
* generate an update interrupt or DMA request if enabled:
* - Counter overflow/underflow
* - Setting the UG bit
* - Update generation through the slave mode controller
* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
* overflow/underflow generates an update interrupt or DMA request if enabled.
* @rmtoll CR1 URS LL_TIM_SetUpdateSource
* @param TIMx Timer instance
* @param UpdateSource This parameter can be one of the following values:
* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
{
MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
}
/**
* @brief Get actual event update source
* @rmtoll CR1 URS LL_TIM_GetUpdateSource
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
*/
__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
}
/**
* @brief Set one pulse mode (one shot v.s. repetitive).
* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
* @param TIMx Timer instance
* @param OnePulseMode This parameter can be one of the following values:
* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
{
MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
}
/**
* @brief Get actual one pulse mode.
* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
*/
__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
}
/**
* @brief Set the timer counter counting mode.
* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
* requires a timer reset to avoid unexpected direction
* due to DIR bit readonly in center aligned mode.
* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
* CR1 CMS LL_TIM_SetCounterMode
* @param TIMx Timer instance
* @param CounterMode This parameter can be one of the following values:
* @arg @ref LL_TIM_COUNTERMODE_UP
* @arg @ref LL_TIM_COUNTERMODE_DOWN
* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
{
MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
}
/**
* @brief Get actual counter mode.
* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
* CR1 CMS LL_TIM_GetCounterMode
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_COUNTERMODE_UP
* @arg @ref LL_TIM_COUNTERMODE_DOWN
* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
{
uint32_t counter_mode;
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
if (counter_mode == 0U)
{
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
}
return counter_mode;
}
/**
* @brief Enable auto-reload (ARR) preload.
* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
}
/**
* @brief Disable auto-reload (ARR) preload.
* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
}
/**
* @brief Indicates whether auto-reload (ARR) preload is enabled.
* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
}
/**
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
* (when supported) and the digital filters.
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_SetClockDivision
* @param TIMx Timer instance
* @param ClockDivision This parameter can be one of the following values:
* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
{
MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
}
/**
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
* generators (when supported) and the digital filters.
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_GetClockDivision
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
*/
__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
}
/**
* @brief Set the counter value.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note If dithering is activated, pay attention to the Counter value interpretation
* @rmtoll CNT CNT LL_TIM_SetCounter
* @param TIMx Timer instance
* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
{
WRITE_REG(TIMx->CNT, Counter);
}
/**
* @brief Get the counter value.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note If dithering is activated, pay attention to the Counter value interpretation
* @rmtoll CNT CNT LL_TIM_GetCounter
* @param TIMx Timer instance
* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CNT));
}
/**
* @brief Get the current direction of the counter
* @rmtoll CR1 DIR LL_TIM_GetDirection
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_COUNTERDIRECTION_UP
* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
*/
__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
}
/**
* @brief Set the prescaler value.
* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
* @note The prescaler can be changed on the fly as this control register is buffered. The new
* prescaler ratio is taken into account at the next update event.
* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
* @rmtoll PSC PSC LL_TIM_SetPrescaler
* @param TIMx Timer instance
* @param Prescaler between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
{
WRITE_REG(TIMx->PSC, Prescaler);
}
/**
* @brief Get the prescaler value.
* @rmtoll PSC PSC LL_TIM_GetPrescaler
* @param TIMx Timer instance
* @retval Prescaler value between Min_Data=0 and Max_Data=65535
*/
__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->PSC));
}
/**
* @brief Set the auto-reload value.
* @note The counter is blocked while the auto-reload value is null.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
* In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
* parameter.
* @rmtoll ARR ARR LL_TIM_SetAutoReload
* @param TIMx Timer instance
* @param AutoReload between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
{
WRITE_REG(TIMx->ARR, AutoReload);
}
/**
* @brief Get the auto-reload value.
* @rmtoll ARR ARR LL_TIM_GetAutoReload
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note If dithering is activated, pay attention to the returned value interpretation
* @param TIMx Timer instance
* @retval Auto-reload value
*/
__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->ARR));
}
/**
* @brief Set the repetition counter value.
* @note For advanced timer instances RepetitionCounter can be up to 65535.
* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
{
WRITE_REG(TIMx->RCR, RepetitionCounter);
}
/**
* @brief Get the repetition counter value.
* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
* @param TIMx Timer instance
* @retval Repetition counter value
*/
__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->RCR));
}
/**
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
* in an atomic way.
* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
}
/**
* @brief Disable update interrupt flag (UIF) remapping.
* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
}
/**
* @brief Indicate whether update interrupt flag (UIF) copy is set.
* @param Counter Counter value
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
{
return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
}
/**
* @brief Enable dithering.
* @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides dithering.
* @rmtoll CR1 DITHEN LL_TIM_EnableDithering
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
}
/**
* @brief Disable dithering.
* @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides dithering.
* @rmtoll CR1 DITHEN LL_TIM_DisableDithering
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
}
/**
* @brief Indicates whether dithering is activated.
* @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides dithering.
* @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
* @{
*/
/**
* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
* they are updated only when a commutation event (COM) occurs.
* @note Only on channels that have a complementary output.
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
}
/**
* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
}
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
* @param TIMx Timer instance
* @param CCUpdateSource This parameter can be one of the following values:
* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
{
MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
}
/**
* @brief Set the trigger of the capture/compare DMA request.
* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
* @param TIMx Timer instance
* @param DMAReqTrigger This parameter can be one of the following values:
* @arg @ref LL_TIM_CCDMAREQUEST_CC
* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
{
MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
}
/**
* @brief Get actual trigger of the capture/compare DMA request.
* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_CCDMAREQUEST_CC
* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
*/
__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
}
/**
* @brief Set the lock level to freeze the
* configuration of several capture/compare parameters.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* the lock mechanism is supported by a timer instance.
* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
* @param TIMx Timer instance
* @param LockLevel This parameter can be one of the following values:
* @arg @ref LL_TIM_LOCKLEVEL_OFF
* @arg @ref LL_TIM_LOCKLEVEL_1
* @arg @ref LL_TIM_LOCKLEVEL_2
* @arg @ref LL_TIM_LOCKLEVEL_3
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
}
/**
* @brief Enable capture/compare channels.
* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
* CCER CC1NE LL_TIM_CC_EnableChannel\n
* CCER CC2E LL_TIM_CC_EnableChannel\n
* CCER CC2NE LL_TIM_CC_EnableChannel\n
* CCER CC3E LL_TIM_CC_EnableChannel\n
* CCER CC3NE LL_TIM_CC_EnableChannel\n
* CCER CC4E LL_TIM_CC_EnableChannel\n
* CCER CC4NE LL_TIM_CC_EnableChannel\n
* CCER CC5E LL_TIM_CC_EnableChannel\n
* CCER CC6E LL_TIM_CC_EnableChannel
* @param TIMx Timer instance
* @param Channels This parameter can be a combination of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
SET_BIT(TIMx->CCER, Channels);
}
/**
* @brief Disable capture/compare channels.
* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
* CCER CC1NE LL_TIM_CC_DisableChannel\n
* CCER CC2E LL_TIM_CC_DisableChannel\n
* CCER CC2NE LL_TIM_CC_DisableChannel\n
* CCER CC3E LL_TIM_CC_DisableChannel\n
* CCER CC3NE LL_TIM_CC_DisableChannel\n
* CCER CC4E LL_TIM_CC_DisableChannel\n
* CCER CC4NE LL_TIM_CC_DisableChannel\n
* CCER CC5E LL_TIM_CC_DisableChannel\n
* CCER CC6E LL_TIM_CC_DisableChannel
* @param TIMx Timer instance
* @param Channels This parameter can be a combination of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
CLEAR_BIT(TIMx->CCER, Channels);
}
/**
* @brief Indicate whether channel(s) is(are) enabled.
* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
* CCER CC4E LL_TIM_CC_IsEnabledChannel\n
* CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
* CCER CC5E LL_TIM_CC_IsEnabledChannel\n
* CCER CC6E LL_TIM_CC_IsEnabledChannel
* @param TIMx Timer instance
* @param Channels This parameter can be a combination of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
* @{
*/
/**
* @brief Configure an output channel.
* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
* CCER CC1P LL_TIM_OC_ConfigOutput\n
* CCER CC2P LL_TIM_OC_ConfigOutput\n
* CCER CC3P LL_TIM_OC_ConfigOutput\n
* CCER CC4P LL_TIM_OC_ConfigOutput\n
* CCER CC5P LL_TIM_OC_ConfigOutput\n
* CCER CC6P LL_TIM_OC_ConfigOutput\n
* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
* CR2 OIS6 LL_TIM_OC_ConfigOutput
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
}
/**
* @brief Define the behavior of the output reference signal OCxREF from which
* OCx and OCxN (when relevant) are derived.
* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
* CCMR1 OC2M LL_TIM_OC_SetMode\n
* CCMR2 OC3M LL_TIM_OC_SetMode\n
* CCMR2 OC4M LL_TIM_OC_SetMode\n
* CCMR3 OC5M LL_TIM_OC_SetMode\n
* CCMR3 OC6M LL_TIM_OC_SetMode
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_TIM_OCMODE_FROZEN
* @arg @ref LL_TIM_OCMODE_ACTIVE
* @arg @ref LL_TIM_OCMODE_INACTIVE
* @arg @ref LL_TIM_OCMODE_TOGGLE
* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
* @arg @ref LL_TIM_OCMODE_PWM1
* @arg @ref LL_TIM_OCMODE_PWM2
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
* @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
* @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
/**
* @brief Get the output compare mode of an output channel.
* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
* CCMR1 OC2M LL_TIM_OC_GetMode\n
* CCMR2 OC3M LL_TIM_OC_GetMode\n
* CCMR2 OC4M LL_TIM_OC_GetMode\n
* CCMR3 OC5M LL_TIM_OC_GetMode\n
* CCMR3 OC6M LL_TIM_OC_GetMode
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_OCMODE_FROZEN
* @arg @ref LL_TIM_OCMODE_ACTIVE
* @arg @ref LL_TIM_OCMODE_INACTIVE
* @arg @ref LL_TIM_OCMODE_TOGGLE
* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
* @arg @ref LL_TIM_OCMODE_PWM1
* @arg @ref LL_TIM_OCMODE_PWM2
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
* @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
* @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
/**
* @brief Set the polarity of an output channel.
* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
* CCER CC1NP LL_TIM_OC_SetPolarity\n
* CCER CC2P LL_TIM_OC_SetPolarity\n
* CCER CC2NP LL_TIM_OC_SetPolarity\n
* CCER CC3P LL_TIM_OC_SetPolarity\n
* CCER CC3NP LL_TIM_OC_SetPolarity\n
* CCER CC4P LL_TIM_OC_SetPolarity\n
* CCER CC4NP LL_TIM_OC_SetPolarity\n
* CCER CC5P LL_TIM_OC_SetPolarity\n
* CCER CC6P LL_TIM_OC_SetPolarity
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_TIM_OCPOLARITY_HIGH
* @arg @ref LL_TIM_OCPOLARITY_LOW
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Get the polarity of an output channel.
* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
* CCER CC1NP LL_TIM_OC_GetPolarity\n
* CCER CC2P LL_TIM_OC_GetPolarity\n
* CCER CC2NP LL_TIM_OC_GetPolarity\n
* CCER CC3P LL_TIM_OC_GetPolarity\n
* CCER CC3NP LL_TIM_OC_GetPolarity\n
* CCER CC4P LL_TIM_OC_GetPolarity\n
* CCER CC4NP LL_TIM_OC_GetPolarity\n
* CCER CC5P LL_TIM_OC_GetPolarity\n
* CCER CC6P LL_TIM_OC_GetPolarity
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_OCPOLARITY_HIGH
* @arg @ref LL_TIM_OCPOLARITY_LOW
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Set the IDLE state of an output channel
* @note This function is significant only for the timer instances
* supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
* can be used to check whether or not a timer instance provides
* a break input.
* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
* CR2 OIS2N LL_TIM_OC_SetIdleState\n
* CR2 OIS2 LL_TIM_OC_SetIdleState\n
* CR2 OIS2N LL_TIM_OC_SetIdleState\n
* CR2 OIS3 LL_TIM_OC_SetIdleState\n
* CR2 OIS3N LL_TIM_OC_SetIdleState\n
* CR2 OIS4 LL_TIM_OC_SetIdleState\n
* CR2 OIS4N LL_TIM_OC_SetIdleState\n
* CR2 OIS5 LL_TIM_OC_SetIdleState\n
* CR2 OIS6 LL_TIM_OC_SetIdleState
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @param IdleState This parameter can be one of the following values:
* @arg @ref LL_TIM_OCIDLESTATE_LOW
* @arg @ref LL_TIM_OCIDLESTATE_HIGH
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
/**
* @brief Get the IDLE state of an output channel
* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
* CR2 OIS2N LL_TIM_OC_GetIdleState\n
* CR2 OIS2 LL_TIM_OC_GetIdleState\n
* CR2 OIS2N LL_TIM_OC_GetIdleState\n
* CR2 OIS3 LL_TIM_OC_GetIdleState\n
* CR2 OIS3N LL_TIM_OC_GetIdleState\n
* CR2 OIS4 LL_TIM_OC_GetIdleState\n
* CR2 OIS4N LL_TIM_OC_GetIdleState\n
* CR2 OIS5 LL_TIM_OC_GetIdleState\n
* CR2 OIS6 LL_TIM_OC_GetIdleState
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_OCIDLESTATE_LOW
* @arg @ref LL_TIM_OCIDLESTATE_HIGH
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
/**
* @brief Enable fast mode for the output channel.
* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
* CCMR2 OC4FE LL_TIM_OC_EnableFast\n
* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
* CCMR3 OC6FE LL_TIM_OC_EnableFast
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Disable fast mode for the output channel.
* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
* CCMR2 OC4FE LL_TIM_OC_DisableFast\n
* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
* CCMR3 OC6FE LL_TIM_OC_DisableFast
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Indicates whether fast mode is enabled for the output channel.
* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
* CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
* CCMR3 OC6PE LL_TIM_OC_EnablePreload
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
* CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
* CCMR3 OC6PE LL_TIM_OC_DisablePreload
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
* @brief Enable clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
* CCMR2 OC4CE LL_TIM_OC_EnableClear\n
* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
* CCMR3 OC6CE LL_TIM_OC_EnableClear
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Disable clearing the output channel on an external event.
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
* CCMR2 OC4CE LL_TIM_OC_DisableClear\n
* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
* CCMR3 OC6CE LL_TIM_OC_DisableClear
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
* @note This function enables clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
* the Ocx and OCxN signals).
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
* @param TIMx Timer instance
* @param DeadTime between Min_Data=0 and Max_Data=255
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
}
/**
* @brief Set compare value for output channel 1 (TIMx_CCR1).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
WRITE_REG(TIMx->CCR1, CompareValue);
}
/**
* @brief Set compare value for output channel 2 (TIMx_CCR2).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
WRITE_REG(TIMx->CCR2, CompareValue);
}
/**
* @brief Set compare value for output channel 3 (TIMx_CCR3).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
WRITE_REG(TIMx->CCR3, CompareValue);
}
/**
* @brief Set compare value for output channel 4 (TIMx_CCR4).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
WRITE_REG(TIMx->CCR4, CompareValue);
}
/**
* @brief Set compare value for output channel 5 (TIMx_CCR5).
* @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
}
/**
* @brief Set compare value for output channel 6 (TIMx_CCR6).
* @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
WRITE_REG(TIMx->CCR6, CompareValue);
}
/**
* @brief Get compare value (TIMx_CCR1) set for output channel 1.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR1));
}
/**
* @brief Get compare value (TIMx_CCR2) set for output channel 2.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR2));
}
/**
* @brief Get compare value (TIMx_CCR3) set for output channel 3.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel 3 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR3));
}
/**
* @brief Get compare value (TIMx_CCR4) set for output channel 4.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR4));
}
/**
* @brief Get compare value (TIMx_CCR5) set for output channel 5.
* @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
}
/**
* @brief Get compare value (TIMx_CCR6) set for output channel 6.
* @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR6));
}
/**
* @brief Select on which reference signal the OC5REF is combined to.
* @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the combined 3-phase PWM mode.
* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
* @param TIMx Timer instance
* @param GroupCH5 This parameter can be a combination of the following values:
* @arg @ref LL_TIM_GROUPCH5_NONE
* @arg @ref LL_TIM_GROUPCH5_OC1REFC
* @arg @ref LL_TIM_GROUPCH5_OC2REFC
* @arg @ref LL_TIM_GROUPCH5_OC3REFC
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
{
MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
}
/**
* @brief Set the pulse on compare pulse width prescaler.
* @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
* @param TIMx Timer instance
* @param PulseWidthPrescaler This parameter can be one of the following values:
* @arg @ref LL_TIM_PWPRSC_X1
* @arg @ref LL_TIM_PWPRSC_X2
* @arg @ref LL_TIM_PWPRSC_X4
* @arg @ref LL_TIM_PWPRSC_X8
* @arg @ref LL_TIM_PWPRSC_X16
* @arg @ref LL_TIM_PWPRSC_X32
* @arg @ref LL_TIM_PWPRSC_X64
* @arg @ref LL_TIM_PWPRSC_X128
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
}
/**
* @brief Get the pulse on compare pulse width prescaler.
* @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_PWPRSC_X1
* @arg @ref LL_TIM_PWPRSC_X2
* @arg @ref LL_TIM_PWPRSC_X4
* @arg @ref LL_TIM_PWPRSC_X8
* @arg @ref LL_TIM_PWPRSC_X16
* @arg @ref LL_TIM_PWPRSC_X32
* @arg @ref LL_TIM_PWPRSC_X64
* @arg @ref LL_TIM_PWPRSC_X128
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
}
/**
* @brief Set the pulse on compare pulse width duration.
* @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
* @param TIMx Timer instance
* @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
}
/**
* @brief Get the pulse on compare pulse width duration.
* @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
* @param TIMx Timer instance
* @retval Returned value can be between Min_Data=0 and Max_Data=255:
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
* @{
*/
/**
* @brief Configure input channel.
* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
* CCMR1 IC1PSC LL_TIM_IC_Config\n
* CCMR1 IC1F LL_TIM_IC_Config\n
* CCMR1 CC2S LL_TIM_IC_Config\n
* CCMR1 IC2PSC LL_TIM_IC_Config\n
* CCMR1 IC2F LL_TIM_IC_Config\n
* CCMR2 CC3S LL_TIM_IC_Config\n
* CCMR2 IC3PSC LL_TIM_IC_Config\n
* CCMR2 IC3F LL_TIM_IC_Config\n
* CCMR2 CC4S LL_TIM_IC_Config\n
* CCMR2 IC4PSC LL_TIM_IC_Config\n
* CCMR2 IC4F LL_TIM_IC_Config\n
* CCER CC1P LL_TIM_IC_Config\n
* CCER CC1NP LL_TIM_IC_Config\n
* CCER CC2P LL_TIM_IC_Config\n
* CCER CC2NP LL_TIM_IC_Config\n
* CCER CC3P LL_TIM_IC_Config\n
* CCER CC3NP LL_TIM_IC_Config\n
* CCER CC4P LL_TIM_IC_Config\n
* CCER CC4NP LL_TIM_IC_Config
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
<< SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
(Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Set the active input.
* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
* CCMR2 CC4S LL_TIM_IC_SetActiveInput
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @param ICActiveInput This parameter can be one of the following values:
* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
* @arg @ref LL_TIM_ACTIVEINPUT_TRC
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
/**
* @brief Get the current active input.
* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
* CCMR2 CC4S LL_TIM_IC_GetActiveInput
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
* @arg @ref LL_TIM_ACTIVEINPUT_TRC
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
/**
* @brief Set the prescaler of input channel.
* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @param ICPrescaler This parameter can be one of the following values:
* @arg @ref LL_TIM_ICPSC_DIV1
* @arg @ref LL_TIM_ICPSC_DIV2
* @arg @ref LL_TIM_ICPSC_DIV4
* @arg @ref LL_TIM_ICPSC_DIV8
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
/**
* @brief Get the current prescaler value acting on an input channel.
* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_ICPSC_DIV1
* @arg @ref LL_TIM_ICPSC_DIV2
* @arg @ref LL_TIM_ICPSC_DIV4
* @arg @ref LL_TIM_ICPSC_DIV8
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
/**
* @brief Set the input filter duration.
* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
* CCMR1 IC2F LL_TIM_IC_SetFilter\n
* CCMR2 IC3F LL_TIM_IC_SetFilter\n
* CCMR2 IC4F LL_TIM_IC_SetFilter
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @param ICFilter This parameter can be one of the following values:
* @arg @ref LL_TIM_IC_FILTER_FDIV1
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
/**
* @brief Get the input filter duration.
* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
* CCMR1 IC2F LL_TIM_IC_GetFilter\n
* CCMR2 IC3F LL_TIM_IC_GetFilter\n
* CCMR2 IC4F LL_TIM_IC_GetFilter
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_IC_FILTER_FDIV1
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
/**
* @brief Set the input channel polarity.
* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
* CCER CC1NP LL_TIM_IC_SetPolarity\n
* CCER CC2P LL_TIM_IC_SetPolarity\n
* CCER CC2NP LL_TIM_IC_SetPolarity\n
* CCER CC3P LL_TIM_IC_SetPolarity\n
* CCER CC3NP LL_TIM_IC_SetPolarity\n
* CCER CC4P LL_TIM_IC_SetPolarity\n
* CCER CC4NP LL_TIM_IC_SetPolarity
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @param ICPolarity This parameter can be one of the following values:
* @arg @ref LL_TIM_IC_POLARITY_RISING
* @arg @ref LL_TIM_IC_POLARITY_FALLING
* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Get the current input channel polarity.
* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
* CCER CC1NP LL_TIM_IC_GetPolarity\n
* CCER CC2P LL_TIM_IC_GetPolarity\n
* CCER CC2NP LL_TIM_IC_GetPolarity\n
* CCER CC3P LL_TIM_IC_GetPolarity\n
* CCER CC3NP LL_TIM_IC_GetPolarity\n
* CCER CC4P LL_TIM_IC_GetPolarity\n
* CCER CC4NP LL_TIM_IC_GetPolarity
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_IC_POLARITY_RISING
* @arg @ref LL_TIM_IC_POLARITY_FALLING
* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
}
/**
* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
}
/**
* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
}
/**
* @brief Get captured value for input channel 1.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* input channel 1 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR1));
}
/**
* @brief Get captured value for input channel 2.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* input channel 2 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR2));
}
/**
* @brief Get captured value for input channel 3.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* input channel 3 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR3));
}
/**
* @brief Get captured value for input channel 4.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* input channel 4 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR4));
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
* @{
*/
/**
* @brief Enable external clock mode 2.
* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
}
/**
* @brief Disable external clock mode 2.
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
}
/**
* @brief Indicate whether external clock mode 2 is enabled.
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
}
/**
* @brief Set the clock source of the counter clock.
* @note when selected clock source is external clock mode 1, the timer input
* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
* function. This timer input must be configured by calling
* the @ref LL_TIM_IC_Config() function.
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode1.
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
* SMCR ECE LL_TIM_SetClockSource
* @param TIMx Timer instance
* @param ClockSource This parameter can be one of the following values:
* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
}
/**
* @brief Set the encoder interface mode.
* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the encoder mode.
* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
* @param TIMx Timer instance
* @param EncoderMode This parameter can be one of the following values:
* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
* @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
* @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
* @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
* @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
* @arg @ref LL_TIM_ENCODERMODE_X1_TI1
* @arg @ref LL_TIM_ENCODERMODE_X1_TI2
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
* @{
*/
/**
* @brief Set the trigger output (TRGO) used for timer synchronization .
* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can operate as a master timer.
* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
* @param TIMx Timer instance
* @param TimerSynchronization This parameter can be one of the following values:
* @arg @ref LL_TIM_TRGO_RESET
* @arg @ref LL_TIM_TRGO_ENABLE
* @arg @ref LL_TIM_TRGO_UPDATE
* @arg @ref LL_TIM_TRGO_CC1IF
* @arg @ref LL_TIM_TRGO_OC1REF
* @arg @ref LL_TIM_TRGO_OC2REF
* @arg @ref LL_TIM_TRGO_OC3REF
* @arg @ref LL_TIM_TRGO_OC4REF
* @arg @ref LL_TIM_TRGO_ENCODERCLK
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
{
MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
}
/**
* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
* @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can be used for ADC synchronization.
* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
* @param TIMx Timer Instance
* @param ADCSynchronization This parameter can be one of the following values:
* @arg @ref LL_TIM_TRGO2_RESET
* @arg @ref LL_TIM_TRGO2_ENABLE
* @arg @ref LL_TIM_TRGO2_UPDATE
* @arg @ref LL_TIM_TRGO2_CC1F
* @arg @ref LL_TIM_TRGO2_OC1
* @arg @ref LL_TIM_TRGO2_OC2
* @arg @ref LL_TIM_TRGO2_OC3
* @arg @ref LL_TIM_TRGO2_OC4
* @arg @ref LL_TIM_TRGO2_OC5
* @arg @ref LL_TIM_TRGO2_OC6
* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
{
MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
}
/**
* @brief Set the synchronization mode of a slave timer.
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
* @param TIMx Timer instance
* @param SlaveMode This parameter can be one of the following values:
* @arg @ref LL_TIM_SLAVEMODE_DISABLED
* @arg @ref LL_TIM_SLAVEMODE_RESET
* @arg @ref LL_TIM_SLAVEMODE_GATED
* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
* @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
}
/**
* @brief Set the selects the trigger input to be used to synchronize the counter.
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR TS LL_TIM_SetTriggerInput
* @param TIMx Timer instance
* @param TriggerInput This parameter can be one of the following values:
* @arg @ref LL_TIM_TS_ITR0
* @arg @ref LL_TIM_TS_ITR1
* @arg @ref LL_TIM_TS_ITR2
* @arg @ref LL_TIM_TS_ITR3
* @arg @ref LL_TIM_TS_TI1F_ED
* @arg @ref LL_TIM_TS_TI1FP1
* @arg @ref LL_TIM_TS_TI2FP2
* @arg @ref LL_TIM_TS_ETRF
* @arg @ref LL_TIM_TS_ITR4
* @arg @ref LL_TIM_TS_ITR5
* @arg @ref LL_TIM_TS_ITR6
* @arg @ref LL_TIM_TS_ITR7
* @arg @ref LL_TIM_TS_ITR8
* @arg @ref LL_TIM_TS_ITR11
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
}
/**
* @brief Enable the Master/Slave mode.
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
}
/**
* @brief Disable the Master/Slave mode.
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
}
/**
* @brief Indicates whether the Master/Slave mode is enabled.
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
}
/**
* @brief Configure the external trigger (ETR) input.
* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an external trigger input.
* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
* SMCR ETPS LL_TIM_ConfigETR\n
* SMCR ETF LL_TIM_ConfigETR
* @param TIMx Timer instance
* @param ETRPolarity This parameter can be one of the following values:
* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
* @param ETRPrescaler This parameter can be one of the following values:
* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
* @param ETRFilter This parameter can be one of the following values:
* @arg @ref LL_TIM_ETR_FILTER_FDIV1
* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
uint32_t ETRFilter)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
}
/**
* @brief Select the external trigger (ETR) input source.
* @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports ETR source selection.
* @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
* @param TIMx Timer instance
* @param ETRSource This parameter can be one of the following values:
*
* TIM1: any combination of ETR_RMP where
*
* @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM1_ETRSOURCE_MSIK
* @arg @ref LL_TIM_TIM1_ETRSOURCE_HSI
* @arg @ref LL_TIM_TIM1_ETRSOURCE_MSIS
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (*)
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 (*)
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (*)
*
* TIM2: any combination of ETR_RMP where
*
* @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM2_ETRSOURCE_MSIK
* @arg @ref LL_TIM_TIM2_ETRSOURCE_HSI
* @arg @ref LL_TIM_TIM2_ETRSOURCE_MSIS
* @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMI_VSYNC (*)
* @arg @ref LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC (*)
* @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
* @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
* @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR
* @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
* @arg @ref LL_TIM_TIM2_ETRSOURCE_DSI_TE (*)
* @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMI_HSYNC (*)
* @arg @ref LL_TIM_TIM2_ETRSOURCE_LTDC_HSYNC (*)
*
* TIM3: any combination of ETR_RMP where
*
* @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM3_ETRSOURCE_MSIK
* @arg @ref LL_TIM_TIM3_ETRSOURCE_HSI
* @arg @ref LL_TIM_TIM3_ETRSOURCE_MSIS
* @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMI_VSYNC (*)
* @arg @ref LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC (*)
* @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
* @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
* @arg @ref LL_TIM_TIM3_ETRSOURCE_DSI_TE (*)
* @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD1
* @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD2
* @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD3
* @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMI_HSYNC (*)
* @arg @ref LL_TIM_TIM3_ETRSOURCE_LTDC_HSYNC (*)
*
* TIM4: any combination of ETR_RMP where
*
* @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM4_ETRSOURCE_MSIK
* @arg @ref LL_TIM_TIM4_ETRSOURCE_HSI
* @arg @ref LL_TIM_TIM4_ETRSOURCE_MSIS
* @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMI_VSYNC (*)
* @arg @ref LL_TIM_TIM4_ETRSOURCE_LTDC_VSYNC (*)
* @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
* @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
* @arg @ref LL_TIM_TIM4_ETRSOURCE_DSI_TE (*)
* @arg @ref LL_TIM_TIM4_ETRSOURCE_ADC2_AWD1 (*)
* @arg @ref LL_TIM_TIM4_ETRSOURCE_ADC2_AWD2 (*)
* @arg @ref LL_TIM_TIM4_ETRSOURCE_ADC2_AWD3 (*)
* @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMI_HSYNC (*)
* @arg @ref LL_TIM_TIM4_ETRSOURCE_LTDC_HSYNC (*)
*
* TIM5: any combination of ETR_RMP where
*
* @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM5_ETRSOURCE_MSIK
* @arg @ref LL_TIM_TIM5_ETRSOURCE_HSI
* @arg @ref LL_TIM_TIM5_ETRSOURCE_MSIS
* @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMI_VSYNC (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_LTDC_VSYNC (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
* @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
* @arg @ref LL_TIM_TIM5_ETRSOURCE_DSI_TE (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMI_HSYNC (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_LTDC_HSYNC (*)
*
* TIM8: any combination of ETR_RMP where
*
* . . ETR_RMP can be one of the following values
* @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM8_ETRSOURCE_MSIK
* @arg @ref LL_TIM_TIM8_ETRSOURCE_HSI
* @arg @ref LL_TIM_TIM8_ETRSOURCE_MSIS
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (*)
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (*)
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD1
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD2
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD3
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD1
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD2
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD3
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (*)
*
* (*) Value not defined in all devices. \n
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
{
MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
}
/**
* @brief Enable SMS preload.
* @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
}
/**
* @brief Disable SMS preload.
* @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
}
/**
* @brief Indicate whether SMS preload is enabled.
* @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
}
/**
* @brief Set the preload source of SMS.
* @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
* @param TIMx Timer instance
* @param PreloadSource This parameter can be one of the following values:
* @arg @ref LL_TIM_SMSPS_TIMUPDATE
* @arg @ref LL_TIM_SMSPS_INDEX
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
}
/**
* @brief Get the preload source of SMS.
* @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_SMSPS_TIMUPDATE
* @arg @ref LL_TIM_SMSPS_INDEX
*/
__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Break_Function Break function configuration
* @{
*/
/**
* @brief Enable the break function.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKE LL_TIM_EnableBRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
}
/**
* @brief Disable the break function.
* @rmtoll BDTR BKE LL_TIM_DisableBRK
* @param TIMx Timer instance
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
}
/**
* @brief Configure the break input.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @note Bidirectional mode is only supported by advanced timer instances.
* Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
* a timer instance is an advanced-control timer.
* @note In bidirectional mode (BKBID bit set), the Break input is configured both
* in input mode and in open drain output mode. Any active Break event will
* assert a low logic level on the Break input to indicate an internal break
* event to external devices.
* @note When bidirectional mode isn't supported, BreakAFMode must be set to
* LL_TIM_BREAK_AFMODE_INPUT.
* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
* BDTR BKF LL_TIM_ConfigBRK\n
* BDTR BKBID LL_TIM_ConfigBRK
* @param TIMx Timer instance
* @param BreakPolarity This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_POLARITY_LOW
* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
* @param BreakFilter This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
* @param BreakAFMode This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_AFMODE_INPUT
* @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
uint32_t BreakAFMode)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
}
/**
* @brief Disarm the break input (when it operates in bidirectional mode).
* @note The break input can be disarmed only when it is configured in
* bidirectional mode and when when MOE is reset.
* @note Purpose is to be able to have the input voltage back to high-state,
* whatever the time constant on the output .
* @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
}
/**
* @brief Re-arm the break input (when it operates in bidirectional mode).
* @note The Break input is automatically armed as soon as MOE bit is set.
* @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
}
/**
* @brief Enable the break 2 function.
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
}
/**
* @brief Disable the break 2 function.
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
}
/**
* @brief Configure the break 2 input.
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @note Bidirectional mode is only supported by advanced timer instances.
* Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
* a timer instance is an advanced-control timer.
* @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
* in input mode and in open drain output mode. Any active Break event will
* assert a low logic level on the Break 2 input to indicate an internal break
* event to external devices.
* @note When bidirectional mode isn't supported, Break2AFMode must be set to
* LL_TIM_BREAK2_AFMODE_INPUT.
* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
* BDTR BK2F LL_TIM_ConfigBRK2\n
* BDTR BK2BID LL_TIM_ConfigBRK2
* @param TIMx Timer instance
* @param Break2Polarity This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
* @param Break2Filter This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
* @param Break2AFMode This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
* @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
uint32_t Break2AFMode)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
}
/**
* @brief Disarm the break 2 input (when it operates in bidirectional mode).
* @note The break 2 input can be disarmed only when it is configured in
* bidirectional mode and when when MOE is reset.
* @note Purpose is to be able to have the input voltage back to high-state,
* whatever the time constant on the output.
* @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
}
/**
* @brief Re-arm the break 2 input (when it operates in bidirectional mode).
* @note The Break 2 input is automatically armed as soon as MOE bit is set.
* @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
}
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
* BDTR OSSR LL_TIM_SetOffStates
* @param TIMx Timer instance
* @param OffStateIdle This parameter can be one of the following values:
* @arg @ref LL_TIM_OSSI_DISABLE
* @arg @ref LL_TIM_OSSI_ENABLE
* @param OffStateRun This parameter can be one of the following values:
* @arg @ref LL_TIM_OSSR_DISABLE
* @arg @ref LL_TIM_OSSR_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
}
/**
* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
}
/**
* @brief Disable automatic output (MOE can be set only by software).
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
}
/**
* @brief Indicate whether automatic output is enabled.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
}
/**
* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
}
/**
* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
}
/**
* @brief Indicates whether outputs are enabled.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
}
/**
* @brief Enable the signals connected to the designated timer break input.
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
* AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
* AF2 BK2INE LL_TIM_EnableBreakInputSource\n
* AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
* AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
* AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
* @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN
* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
* @param Source This parameter can be one of the following values:
* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
* @arg @ref LL_TIM_BKIN_SOURCE_MDF1
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
SET_BIT(*pReg, Source);
}
/**
* @brief Disable the signals connected to the designated timer break input.
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
* AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
* AF2 BK2INE LL_TIM_DisableBreakInputSource\n
* AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
* AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
* AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
* @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN
* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
* @param Source This parameter can be one of the following values:
* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
* @arg @ref LL_TIM_BKIN_SOURCE_MDF1
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
CLEAR_BIT(*pReg, Source);
}
/**
* @brief Set the polarity of the break signal for the timer break input.
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
* AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
* AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
* AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
* AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
* AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
* @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN
* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
* @param Source This parameter can be one of the following values:
* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_TIM_BKIN_POLARITY_LOW
* @arg @ref LL_TIM_BKIN_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
uint32_t Polarity)
{
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
}
/**
* @brief Enable asymmetrical deadtime.
* @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides asymmetrical deadtime.
* @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
}
/**
* @brief Disable asymmetrical dead-time.
* @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides asymmetrical deadtime.
* @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
}
/**
* @brief Indicates whether asymmetrical deadtime is activated.
* @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides asymmetrical deadtime.
* @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
}
/**
* @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
* rising edge of OCxN signals).
* @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* asymmetrical dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
* (LOCK bits in TIMx_BDTR register).
* @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
* @param TIMx Timer instance
* @param DeadTime between Min_Data=0 and Max_Data=255
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
{
MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
}
/**
* @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
* the rising edge of OCxN signals).
* @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* asymmetrical dead-time insertion feature is supported by a timer instance.
* @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
* (LOCK bits in TIMx_BDTR register).
* @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
* @param TIMx Timer instance
* @retval Returned value can be between Min_Data=0 and Max_Data=255:
*/
__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
}
/**
* @brief Enable deadtime preload.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides deadtime preload.
* @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
}
/**
* @brief Disable dead-time preload.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides deadtime preload.
* @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
}
/**
* @brief Indicates whether deadtime preload is activated.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides deadtime preload.
* @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
* @{
*/
/**
* @brief Configures the timer DMA burst feature.
* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports the DMA burst mode.
* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
* DCR DBA LL_TIM_ConfigDMABurst
* @param TIMx Timer instance
* @param DMABurstBaseAddress This parameter can be one of the following values:
* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
* @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
* @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
* @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
* @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
* @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
* @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
* @param DMABurstLength This parameter can be one of the following values:
* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
* @param DMABurstSource This parameter can be one of the following values:
* @arg @ref LL_TIM_DMA_UPDATE
* @arg @ref LL_TIM_DMA_CC1
* @arg @ref LL_TIM_DMA_CC2
* @arg @ref LL_TIM_DMA_CC3
* @arg @ref LL_TIM_DMA_CC4
* @arg @ref LL_TIM_DMA_COM
* @arg @ref LL_TIM_DMA_TRIGGER
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
uint32_t DMABurstSource)
{
MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
(DMABurstBaseAddress | DMABurstLength | DMABurstSource));
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Encoder Encoder configuration
* @{
*/
/**
* @brief Enable encoder index.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IE LL_TIM_EnableEncoderIndex
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->ECR, TIM_ECR_IE);
}
/**
* @brief Disable encoder index.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IE LL_TIM_DisableEncoderIndex
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
}
/**
* @brief Indicate whether encoder index is enabled.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
}
/**
* @brief Set index direction
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IDIR LL_TIM_SetIndexDirection
* @param TIMx Timer instance
* @param IndexDirection This parameter can be one of the following values:
* @arg @ref LL_TIM_INDEX_UP_DOWN
* @arg @ref LL_TIM_INDEX_UP
* @arg @ref LL_TIM_INDEX_DOWN
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
}
/**
* @brief Get actual index direction
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IDIR LL_TIM_GetIndexDirection
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_INDEX_UP_DOWN
* @arg @ref LL_TIM_INDEX_UP
* @arg @ref LL_TIM_INDEX_DOWN
*/
__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
}
/**
* @brief Set index blanking
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IBLK LL_TIM_SetIndexblanking
* @param TIMx Timer instance
* @param Indexblanking This parameter can be one of the following values:
* @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
* @arg @ref LL_TIM_INDEX_BLANK_TI3
* @arg @ref LL_TIM_INDEX_BLANK_TI4
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
}
/**
* @brief Get actual index blanking
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IBLK LL_TIM_GetIndexblanking
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
* @arg @ref LL_TIM_INDEX_BLANK_TI3
* @arg @ref LL_TIM_INDEX_BLANK_TI4
*/
__STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
}
/**
* @brief Enable first index.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
}
/**
* @brief Disable first index.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
}
/**
* @brief Indicates whether first index is enabled.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
}
/**
* @brief Set index positioning
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
* @param TIMx Timer instance
* @param IndexPositionning This parameter can be one of the following values:
* @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
* @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_UP_UP
* @arg @ref LL_TIM_INDEX_POSITION_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_UP
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
}
/**
* @brief Get actual index positioning
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
* @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_UP_UP
* @arg @ref LL_TIM_INDEX_POSITION_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_UP
*/
__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
}
/**
* @brief Configure encoder index.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
* ECR IBLK LL_TIM_ConfigIDX\n
* ECR FIDX LL_TIM_ConfigIDX\n
* ECR IPOS LL_TIM_ConfigIDX
* @param TIMx Timer instance
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
* @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
* @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
* @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
* @{
*/
/**
* @brief Remap TIM inputs (input channel, internal/external triggers).
* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* a some timer inputs can be remapped.
* @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
* TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
* TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
* TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
* TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
* TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
* TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
*
* @param TIMx Timer instance
* @param Remap Remap param depends on the TIMx. Description available only
* in CHM version of the User Manual (not in .pdf).
* Otherwise see Reference Manual description of TISEL registers.
*
* Below description summarizes "Timer Instance" and "Remap" param combinations:
*
* TIM1: one of the following values:
* @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
* @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output
* @arg LL_TIM_TIM1_TI1_RMP_COMP2: TIM1 TI1 is connected to COMP2 output
*
* TIM2: one of the following values:
* @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO
* @arg LL_TIM_TIM2_TI1_RMP_COMP1: TIM2 TI1 is connected to COMP1 output
* @arg LL_TIM_TIM2_TI1_RMP_COMP2: TIM2 TI1 is connected to COMP2 output
* @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO
* @arg LL_TIM_TIM2_TI2_RMP_COMP1: TIM2 TI2 is connected to COMP1 output
* @arg LL_TIM_TIM2_TI2_RMP_COMP2: TIM2 TI2 is connected to COMP2 output
* @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
* @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output
* @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output
*
* TIM3: one of the following values:
* @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
* @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output
* @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output
* @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO
* @arg LL_TIM_TIM3_TI2_RMP_COMP1: TIM3 TI2 is connected to COMP1 output
* @arg LL_TIM_TIM3_TI2_RMP_COMP2: TIM3 TI2 is connected to COMP2 output
*
* TIM4: one of the following values:
* @arg LL_TIM_TIM4_TI1_RMP_GPIO: TIM4 TI1 is connected to GPIO
* @arg LL_TIM_TIM4_TI1_RMP_COMP1: TIM4 TI1 is connected to COMP1 output
* @arg LL_TIM_TIM4_TI1_RMP_COMP2: TIM4 TI1 is connected to COMP2 output
* @arg LL_TIM_TIM4_TI2_RMP_GPIO: TIM4 TI2 is connected to GPIO
* @arg LL_TIM_TIM4_TI2_RMP_COMP1: TIM4 TI2 is connected to COMP1 output
* @arg LL_TIM_TIM4_TI2_RMP_COMP2: TIM4 TI2 is connected to COMP2 output
*
* TIM5: one of the following values:
* @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
* @arg LL_TIM_TIM5_TI1_RMP_LSI: TIM5 TI1 is connected to LSI
* @arg LL_TIM_TIM5_TI1_RMP_LSE: TIM5 TI1 is connected to LSE
* @arg LL_TIM_TIM5_TI1_RMP_RTC: TIM5 TI1 is connected to RTC Wakeup
* @arg LL_TIM_TIM5_TI1_RMP_COMP1: TIM5 TI1 is connected to COMP1 output
* @arg LL_TIM_TIM5_TI1_RMP_COMP2: TIM5 TI1 is connected to COMP2 output
* @arg LL_TIM_TIM5_TI2_RMP_GPIO: TIM5 TI2 is connected to GPIO
* @arg LL_TIM_TIM5_TI2_RMP_COMP1: TIM5 TI2 is connected to COMP1 output
* @arg LL_TIM_TIM5_TI2_RMP_COMP2: TIM5 TI2 is connected to COMP2 output
*
* TIM8: one of the following values:
* @arg TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
* @arg TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output
*
* TIM15: one of the following values:
* @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
* @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
* @arg LL_TIM_TIM15_TI1_RMP_COMP1: TIM15 TI1 is connected to COMP1 output
* @arg LL_TIM_TIM15_TI1_RMP_COMP2: TIM15 TI1 is connected to COMP2 output
* @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO
* @arg LL_TIM_TIM15_TI2_RMP_COMP2: TIM15 TI2 is connected to COMP2 output
*
* TIM16: one of the following values:
* @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
* @arg LL_TIM_TIM16_TI1_RMP_MCO: TIM16 TI1 is connected to MCO
* @arg LL_TIM_TIM16_TI1_RMP_HSE_DIV32: TIM16 TI1 is connected to HSE DIV32
* @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC
* @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
* @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
* @arg LL_TIM_TIM16_TI1_RMP_MSIS_1024: TIM16 TI1 is connected to MSIS/1024
* @arg LL_TIM_TIM16_TI1_RMP_MSIS_4: TIM16 TI1 is connected to MSIS/4
* @arg LL_TIM_TIM16_TI1_RMP_HSI_256: TIM16 TI1 is connected to HSI/256
*
* TIM17: one of the following values:
* @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
* @arg LL_TIM_TIM17_TI1_RMP_MCO: TIM17 TI1 is connected to MCO
* @arg LL_TIM_TIM17_TI1_RMP_HSE_DIV32: TIM17 TI1 is connected to HSE DIV32
* @arg LL_TIM_TIM17_TI1_RMP_RTC: TIM17 TI1 is connected to RTC
* @arg LL_TIM_TIM17_TI1_RMP_LSE: TIM17 TI1 is connected to LSE
* @arg LL_TIM_TIM17_TI1_RMP_LSI: TIM17 TI1 is connected to LSI
* @arg LL_TIM_TIM17_TI1_RMP_MSIS_1024: TIM17 TI1 is connected to MSIS/1024
* @arg LL_TIM_TIM17_TI1_RMP_MSIS_4: TIM17 TI1 is connected to MSIS/4
* @arg LL_TIM_TIM17_TI1_RMP_HSI_256: TIM17 TI1 is connected to HSI/256
*
*
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
{
MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
}
/**
* @brief Enable request for HSE/32 clock used for TISEL remap.
* @note Only TIM16 and TIM17 support HSE/32 remap
* @note The Cut1.x contains a limitation when using HSE/32 as input capture for TIM16
* @note Bug ID 56: On TIM16, the HSE/32 input capture requires the set of HSE32EN bit of TIM17 Option Register
* @rmtoll OR HSE32EN LL_TIM_EnableHSE32
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->OR1, TIM_OR1_HSE32EN);
}
/**
* @brief Disable request for HSE/32 clock used for TISEL remap.
* @note Only TIM16 and TIM17 support HSE/32 remap
* @rmtoll OR HSE32EN LL_TIM_DisableHSE32
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->OR1, TIM_OR1_HSE32EN);
}
/**
* @brief Indicate whether request for HSE/32 clock is enabled.
* @note Only TIM16 and TIM17 support HSE/32 remap
* @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->OR1, TIM_OR1_HSE32EN) == (TIM_OR1_HSE32EN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
* @{
*/
/**
* @brief Set the OCREF clear input source
* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
* @note This function can only be used in Output compare and PWM modes.
* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
* @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
* @param TIMx Timer instance
* @param OCRefClearInputSource This parameter can be one of the following values:
* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
* @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
* @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos);
MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
* @{
*/
/**
* @brief Clear the update interrupt flag (UIF).
* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
}
/**
* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
}
/**
* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
}
/**
* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
}
/**
* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
}
/**
* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
}
/**
* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
}
/**
* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the commutation interrupt flag (COMIF).
* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
}
/**
* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the trigger interrupt flag (TIF).
* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
}
/**
* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the break interrupt flag (BIF).
* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
}
/**
* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the break 2 interrupt flag (B2IF).
* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
}
/**
* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
}
/**
* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
* (Capture/Compare 1 interrupt is pending).
* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
}
/**
* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
* (Capture/Compare 2 over-capture interrupt is pending).
* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
}
/**
* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
* (Capture/Compare 3 over-capture interrupt is pending).
* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
}
/**
* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
* (Capture/Compare 4 over-capture interrupt is pending).
* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
}
/**
* @brief Clear the system break interrupt flag (SBIF).
* @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
}
/**
* @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
* @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the transition error interrupt flag (TERRF).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
}
/**
* @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
}
/**
* @brief Clear the index error interrupt flag (IERRF).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
}
/**
* @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
}
/**
* @brief Clear the direction change interrupt flag (DIRF).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
}
/**
* @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
}
/**
* @brief Clear the index interrupt flag (IDXF).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
}
/**
* @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_IT_Management IT-Management
* @{
*/
/**
* @brief Enable update interrupt (UIE).
* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_UIE);
}
/**
* @brief Disable update interrupt (UIE).
* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
}
/**
* @brief Indicates whether the update interrupt (UIE) is enabled.
* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 1 interrupt (CC1IE).
* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
}
/**
* @brief Disable capture/compare 1 interrupt (CC1IE).
* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
}
/**
* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 2 interrupt (CC2IE).
* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
}
/**
* @brief Disable capture/compare 2 interrupt (CC2IE).
* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
}
/**
* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 3 interrupt (CC3IE).
* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
}
/**
* @brief Disable capture/compare 3 interrupt (CC3IE).
* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
}
/**
* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 4 interrupt (CC4IE).
* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
}
/**
* @brief Disable capture/compare 4 interrupt (CC4IE).
* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
}
/**
* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
}
/**
* @brief Enable commutation interrupt (COMIE).
* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
}
/**
* @brief Disable commutation interrupt (COMIE).
* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
}
/**
* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
}
/**
* @brief Enable trigger interrupt (TIE).
* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_TIE);
}
/**
* @brief Disable trigger interrupt (TIE).
* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
}
/**
* @brief Indicates whether the trigger interrupt (TIE) is enabled.
* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
}
/**
* @brief Enable break interrupt (BIE).
* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_BIE);
}
/**
* @brief Disable break interrupt (BIE).
* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
}
/**
* @brief Indicates whether the break interrupt (BIE) is enabled.
* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
}
/**
* @brief Enable transition error interrupt (TERRIE).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
}
/**
* @brief Disable transition error interrupt (TERRIE).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
}
/**
* @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable index error interrupt (IERRIE).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
}
/**
* @brief Disable index error interrupt (IERRIE).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
}
/**
* @brief Indicates whether the index error interrupt (IERRIE) is enabled.
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable direction change interrupt (DIRIE).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
}
/**
* @brief Disable direction change interrupt (DIRIE).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
}
/**
* @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable index interrupt (IDXIE).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
}
/**
* @brief Disable index interrupt (IDXIE).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
}
/**
* @brief Indicates whether the index interrupt (IDXIE) is enabled.
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Enable update DMA request (UDE).
* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_UDE);
}
/**
* @brief Disable update DMA request (UDE).
* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
}
/**
* @brief Indicates whether the update DMA request (UDE) is enabled.
* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 1 DMA request (CC1DE).
* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
}
/**
* @brief Disable capture/compare 1 DMA request (CC1DE).
* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
}
/**
* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 2 DMA request (CC2DE).
* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
}
/**
* @brief Disable capture/compare 2 DMA request (CC2DE).
* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
}
/**
* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 3 DMA request (CC3DE).
* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
}
/**
* @brief Disable capture/compare 3 DMA request (CC3DE).
* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
}
/**
* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 4 DMA request (CC4DE).
* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
}
/**
* @brief Disable capture/compare 4 DMA request (CC4DE).
* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
}
/**
* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
}
/**
* @brief Enable commutation DMA request (COMDE).
* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
}
/**
* @brief Disable commutation DMA request (COMDE).
* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
}
/**
* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
}
/**
* @brief Enable trigger interrupt (TDE).
* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_TDE);
}
/**
* @brief Disable trigger interrupt (TDE).
* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
}
/**
* @brief Indicates whether the trigger interrupt (TDE) is enabled.
* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
* @{
*/
/**
* @brief Generate an update event.
* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_UG);
}
/**
* @brief Generate Capture/Compare 1 event.
* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
}
/**
* @brief Generate Capture/Compare 2 event.
* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
}
/**
* @brief Generate Capture/Compare 3 event.
* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
}
/**
* @brief Generate Capture/Compare 4 event.
* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
}
/**
* @brief Generate commutation event.
* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_COMG);
}
/**
* @brief Generate trigger event.
* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_TG);
}
/**
* @brief Generate break event.
* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_BG);
}
/**
* @brief Generate break 2 event.
* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_B2G);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
* @{
*/
ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32U5xx_LL_TIM_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h
|
C
|
apache-2.0
| 297,108
|
/**
******************************************************************************
* @file stm32u5xx_ll_ucpd.h
* @author MCD Application Team
* @brief Header file of UCPD LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_UCPD_H
#define STM32U5xx_LL_UCPD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (UCPD1)
/** @defgroup UCPD_LL UCPD
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure
* @{
*/
/**
* @brief UCPD Init structures definition
*/
typedef struct
{
uint32_t psc_ucpdclk; /*!< Specify the prescaler for the UCPD clock.
This parameter can be a value of @ref UCPD_LL_EC_PSC.
This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk().
*/
uint32_t transwin; /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV)
to achieve a legal tTransitionWindow (set according to peripheral clock to define
an interval of between 12 and 20 us).
This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
This value can be modified afterwards using function @ref LL_UCPD_SetTransWin().
*/
uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order to generate
tInterframeGap from the peripheral clock.
This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap().
*/
uint32_t HbitClockDiv; /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock
e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock :
"UCPD1_CLK".
This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv().
*/
} LL_UCPD_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants
* @{
*/
/** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_ucpd_ReadReg function
* @{
*/
#define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */
#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */
#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */
#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */
#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */
#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */
#define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */
#define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */
#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */
#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */
#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */
#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */
#define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */
#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */
#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */
#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!<Status of DC level on CC1 pin */
#define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2 /*!<Status of DC level on CC2 pin */
#define LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT /*!<Fast Role Swap detection event */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions
* @{
*/
#define LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE /*!< Enable transmit interrupt status */
#define LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE /*!< Enable transmit message discarded interrupt */
#define LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE /*!< Enable transmit message sent interrupt */
#define LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE /*!< Enable transmit message abort interrupt */
#define LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE /*!< Enable HRST discarded interrupt */
#define LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE /*!< Enable HRST sent interrupt */
#define LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE /*!< Enable tx data underrun condition interrupt */
#define LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE /*!< Enable Receive data register not empty interrupt */
#define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
#define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE /*!< Enable Rx Hard Reset detect interrupt */
#define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE /*!< Enable Rx data overflow interrupt */
#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE /*!< Enable Rx message received */
#define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE /*!< Enable Type C voltage level event on CC1 */
#define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE /*!< Enable Type C voltage level event on CC2 */
#define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE /*!< Enable fast Role Swap detection event */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_ORDERSET Ordered sets value
* @brief definition of the usual Ordered sets
* @{
*/
#define LL_UCPD_SYNC1 0x18u /*!< K-code for Startsynch #1 */
#define LL_UCPD_SYNC2 0x11u /*!< K-code for Startsynch #2 */
#define LL_UCPD_SYNC3 0x06u /*!< K-code for Startsynch #3 */
#define LL_UCPD_RST1 0x07u /*!< K-code for Hard Reset #1 */
#define LL_UCPD_RST2 0x19u /*!< K-code for Hard Reset #2 */
#define LL_UCPD_EOP 0x0Du /*!< K-code for EOP End of Packet */
#define LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP Ordered set coding */
#define LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Ordered set coding */
#define LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP'' Ordered set coding */
#define LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u )) /*!< Hard Reset Ordered set coding */
#define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< Cable Reset Ordered set coding */
#define LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Debug Ordered set coding */
#define LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP'' Debug Ordered set coding */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_MODE Role Mode
* @{
*/
#define LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE /*!< Mode SNK Rd */
#define LL_UCPD_ROLE_SRC 0x0U /*!< Mode SRC Rp */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_RESISTOR Resistor value
* @{
*/
#define LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0 /*!< Rp default */
#define LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1 /*!< Rp 1.5 A */
#define LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE /*!< Rp 3.0 A */
#define LL_UCPD_RESISTOR_NONE 0x0U /*!< No resistor */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_CFG1_ORDERSET ordered set configuration
* @{
*/
#define LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0 /*!< SOP Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1 /*!< SOP' Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2 /*!< SOP'' Ordered set detection enabled */
#define LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3 /*!< Hard Reset Ordered set detection enabled */
#define LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4 /*!< Cable Reset Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5 /*!< SOP' Debug Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6 /*!< SOP'' Debug Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7 /*!< SOP extension#1 Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8 /*!< SOP extension#2 Ordered set detection enabled */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_CCxEVT CCx event
* @{
*/
#define LL_UCPD_SNK_CC1_VOPEN 0x00u /*!< CC1 Sink Open state */
#define LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0 /*!< CC1 Sink vRP default state */
#define LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1 /*!< CC1 Sink vRP 1.5A state */
#define LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1) /*!< CC1 Sink vRP 3.0A state */
#define LL_UCPD_SNK_CC2_VOPEN 0x00u /*!< CC2 Sink Open state */
#define LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0 /*!< CC2 Sink vRP default state */
#define LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1 /*!< CC2 Sink vRP 1.5A state */
#define LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1) /*!< CC2 Sink vRP 3.0A state */
#define LL_UCPD_SRC_CC1_VRA 0x0U /*!< CC1 Source vRA state */
#define LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0 /*!< CC1 Source vRD state */
#define LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1 /*!< CC1 Source Open state */
#define LL_UCPD_SRC_CC2_VRA 0x0U /*!< CC2 Source vRA state */
#define LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0 /*!< CC2 Source vRD state */
#define LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1 /*!< CC2 Source Open state */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_PSC prescaler for UCPDCLK
* @{
*/
#define LL_UCPD_PSC_DIV1 0x0u /*!< Bypass pre-scaling / divide by 1 */
#define LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0 /*!< Pre-scale clock by dividing by 2 */
#define LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1 /*!< Pre-scale clock by dividing by 4 */
#define LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0) /*!< Pre-scale clock by dividing by 8 */
#define LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2 /*!< Pre-scale clock by dividing by 16 */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_CCENABLE CC pin enable
* @{
*/
#define LL_UCPD_CCENABLE_NONE 0x0U /*!< Neither PHY is activated (e.g. disabled state of source) */
#define LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0 /*!< Controls apply to only CC1 */
#define LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1 /*!< Controls apply to only CC1 */
#define LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1) /*!< Controls apply to both CC1 and CC2 (normal usage for sink/source) */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_CCPIN CC pin selection
* @{
*/
#define LL_UCPD_CCPIN_CC1 0x0U /*!< Use CC1 IO for power delivery communication */
#define LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL /*!< Use CC2 IO for power delivery communication */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_RXMODE Receiver mode
* @{
*/
#define LL_UCPD_RXMODE_NORMAL 0x0U /*!< Normal receive mode */
#define LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE /*!< BIST receive mode (BIST Test Data Mode) */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_TXMODE Type of Tx packet
* @{
*/
#define LL_UCPD_TXMODE_NORMAL 0x0U /*!< Initiate the transfer of a Tx message */
#define LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0 /*!< Trigger a the transfer of a Cable Reset sequence */
#define LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1 /*!< Trigger a BIST test sequence send (BIST Carrier Mode 2) */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_RXORDSET Rx ordered set code detected
* @{
*/
#define LL_UCPD_RXORDSET_SOP 0x0U /*!< SOP code detected in receiver */
#define LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0 /*!< SOP' code detected in receiver */
#define LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1 /*!< SOP'' code detected in receiver */
#define LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1) /*!< SOP' Debug code detected in receiver */
#define LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2 /*!< SOP'' Debug code detected in receiver */
#define LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0) /*!< Cable Reset code detected in receiver */
#define LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1) /*!< SOP extension#1 code detected in receiver */
#define LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0) /*!< SOP extension#2 code detected in receiver */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup UCPD_LL_Exported_Macros UCPD Exported Macros
* @{
*/
/** @defgroup UCPD_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in UCPD register
* @param __INSTANCE__ UCPD Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in UCPD register
* @param __INSTANCE__ UCPD Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions
* @{
*/
/** @defgroup UCPD_LL_EF_Configuration Configuration
* @{
*/
/** @defgroup UCPD_LL_EF_CFG1 CFG1 register
* @{
*/
/**
* @brief Enable UCPD peripheral
* @rmtoll CFG1 UCPDEN LL_UCPD_Enable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
}
/**
* @brief Disable UCPD peripheral
* @note When disabling the UCPD, follow the procedure described in the Reference Manual.
* @rmtoll CFG1 UCPDEN LL_UCPD_Disable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
}
/**
* @brief Check if UCPD peripheral is enabled
* @rmtoll CFG1 UCPDEN LL_UCPD_IsEnabled
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL);
}
/**
* @brief Set the receiver ordered set detection enable
* @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet
* @param UCPDx UCPD Instance
* @param OrderSet This parameter can be combination of the following values:
* @arg @ref LL_UCPD_ORDERSET_SOP
* @arg @ref LL_UCPD_ORDERSET_SOP1
* @arg @ref LL_UCPD_ORDERSET_SOP2
* @arg @ref LL_UCPD_ORDERSET_HARDRST
* @arg @ref LL_UCPD_ORDERSET_CABLERST
* @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG
* @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG
* @arg @ref LL_UCPD_ORDERSET_SOP_EXT1
* @arg @ref LL_UCPD_ORDERSET_SOP_EXT2
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet)
{
MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet);
}
/**
* @brief Set the prescaler for ucpd clock
* @rmtoll CFG1 UCPDCLK LL_UCPD_SetPSCClk
* @param UCPDx UCPD Instance
* @param Psc This parameter can be one of the following values:
* @arg @ref LL_UCPD_PSC_DIV1
* @arg @ref LL_UCPD_PSC_DIV2
* @arg @ref LL_UCPD_PSC_DIV4
* @arg @ref LL_UCPD_PSC_DIV8
* @arg @ref LL_UCPD_PSC_DIV16
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc)
{
MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc);
}
/**
* @brief Set the number of cycles (minus 1) of the half bit clock
* @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin
* @param UCPDx UCPD Instance
* @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
{
MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos);
}
/**
* @brief Set the clock divider value to generate an interframe gap
* @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap
* @param UCPDx UCPD Instance
* @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
{
MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos);
}
/**
* @brief Set the clock divider value to generate an interframe gap
* @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv
* @param UCPDx UCPD Instance
* @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock)
{
MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos);
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_CFG2 CFG2 register
* @{
*/
/**
* @brief Enable Rx Analog Filter
* @rmtoll CFG2 RXAFILTEN LL_UCPD_RxAnalogFilterEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxAnalogFilterEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN);
}
/**
* @brief Disable Rx Analog Filter
* @rmtoll CFG2 RXAFILTEN LL_UCPD_RxAnalogFilterDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxAnalogFilterDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN);
}
/**
* @brief Enable the wakeup mode
* @rmtoll CFG2 WUPEN LL_UCPD_WakeUpEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
}
/**
* @brief Disable the wakeup mode
* @rmtoll CFG2 WUPEN LL_UCPD_WakeUpDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
}
/**
* @brief Force clock enable
* @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
}
/**
* @brief Force clock disable
* @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
}
/**
* @brief RxFilter enable
* @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
}
/**
* @brief RxFilter disable
* @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup UCPD_LL_EF_CR CR register
* @{
*/
/**
* @brief Type C detector for CC2 enable
* @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
}
/**
* @brief Type C detector for CC2 disable
* @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
}
/**
* @brief Type C detector for CC1 enable
* @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
}
/**
* @brief Type C detector for CC1 disable
* @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
}
/**
* @brief Source Vconn discharge enable
* @rmtoll CR RDCH LL_UCPD_VconnDischargeEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_RDCH);
}
/**
* @brief Source Vconn discharge disable
* @rmtoll CR RDCH LL_UCPD_VconnDischargeDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH);
}
/**
* @brief Signal Fast Role Swap request
* @rmtoll CR FRSTX LL_UCPD_VconnDischargeDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_FRSTX);
}
/**
* @brief Fast Role swap RX detection enable
* @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_FRSDetectionEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
}
/**
* @brief Fast Role swap RX detection disable
* @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_FRSDetectionDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
}
/**
* @brief Set cc enable
* @rmtoll CR CC1VCONNEN LL_UCPD_SetccEnable
* @param UCPDx UCPD Instance
* @param CCEnable This parameter can be one of the following values:
* @arg @ref LL_UCPD_CCENABLE_NONE
* @arg @ref LL_UCPD_CCENABLE_CC1
* @arg @ref LL_UCPD_CCENABLE_CC2
* @arg @ref LL_UCPD_CCENABLE_CC1CC2
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable)
{
MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable);
}
/**
* @brief Set UCPD SNK role
* @rmtoll CR ANAMODE LL_UCPD_SetSNKRole
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
}
/**
* @brief Set UCPD SRC role
* @rmtoll CR ANAMODE LL_UCPD_SetSRCRole
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
}
/**
* @brief Get UCPD Role
* @rmtoll CR ANAMODE LL_UCPD_GetRole
* @param UCPDx UCPD Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_UCPD_ROLE_SNK
* @arg @ref LL_UCPD_ROLE_SRC
*/
__STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx)
{
return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE));
}
/**
* @brief Set Rp resistor
* @rmtoll CR ANASUBMODE LL_UCPD_SetRpResistor
* @param UCPDx UCPD Instance
* @param Resistor This parameter can be one of the following values:
* @arg @ref LL_UCPD_RESISTOR_DEFAULT
* @arg @ref LL_UCPD_RESISTOR_1_5A
* @arg @ref LL_UCPD_RESISTOR_3_0A
* @arg @ref LL_UCPD_RESISTOR_NONE
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor)
{
MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE, Resistor);
}
/**
* @brief Set CC pin
* @rmtoll CR PHYCCSEL LL_UCPD_SetCCPin
* @param UCPDx UCPD Instance
* @param CCPin This parameter can be one of the following values:
* @arg @ref LL_UCPD_CCPIN_CC1
* @arg @ref LL_UCPD_CCPIN_CC2
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin)
{
MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL, CCPin);
}
/**
* @brief Rx enable
* @rmtoll CR PHYRXEN LL_UCPD_RxEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
}
/**
* @brief Rx disable
* @rmtoll CR PHYRXEN LL_UCPD_RxDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
}
/**
* @brief Set Rx mode
* @rmtoll CR RXMODE LL_UCPD_SetRxMode
* @param UCPDx UCPD Instance
* @param RxMode This parameter can be one of the following values:
* @arg @ref LL_UCPD_RXMODE_NORMAL
* @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode)
{
MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode);
}
/**
* @brief Send Hard Reset
* @rmtoll CR TXHRST LL_UCPD_SendHardReset
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_TXHRST);
}
/**
* @brief Send message
* @rmtoll CR TXSEND LL_UCPD_SendMessage
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_TXSEND);
}
/**
* @brief Set Tx mode
* @rmtoll CR TXMODE LL_UCPD_SetTxMode
* @param UCPDx UCPD Instance
* @param TxMode This parameter can be one of the following values:
* @arg @ref LL_UCPD_TXMODE_NORMAL
* @arg @ref LL_UCPD_TXMODE_CABLE_RESET
* @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode)
{
MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode);
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_IT_Management Interrupt Management
* @{
*/
/**
* @brief Enable FRS interrupt
* @rmtoll IMR FRSEVTIE LL_UCPD_EnableIT_FRS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_FRS(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
}
/**
* @brief Enable type c event on CC2
* @rmtoll IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
}
/**
* @brief Enable type c event on CC1
* @rmtoll IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
}
/**
* @brief Enable Rx message end interrupt
* @rmtoll IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
}
/**
* @brief Enable Rx overrun interrupt
* @rmtoll IMR RXOVRIE LL_UCPD_EnableIT_RxOvr
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
}
/**
* @brief Enable Rx hard resrt interrupt
* @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
}
/**
* @brief Enable Rx orderset interrupt
* @rmtoll IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
}
/**
* @brief Enable Rx non empty interrupt
* @rmtoll IMR RXNEIE LL_UCPD_EnableIT_RxNE
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
}
/**
* @brief Enable TX underrun interrupt
* @rmtoll IMR TXUNDIE LL_UCPD_EnableIT_TxUND
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
}
/**
* @brief Enable hard reset sent interrupt
* @rmtoll IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
}
/**
* @brief Enable hard reset discard interrupt
* @rmtoll IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
}
/**
* @brief Enable Tx message abort interrupt
* @rmtoll IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
}
/**
* @brief Enable Tx message sent interrupt
* @rmtoll IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
}
/**
* @brief Enable Tx message discarded interrupt
* @rmtoll IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
}
/**
* @brief Enable Tx data receive interrupt
* @rmtoll IMR TXISIE LL_UCPD_EnableIT_TxIS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
}
/**
* @brief Disable FRS interrupt
* @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_FRS(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
}
/**
* @brief Disable type c event on CC2
* @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
}
/**
* @brief Disable type c event on CC1
* @rmtoll IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
}
/**
* @brief Disable Rx message end interrupt
* @rmtoll IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
}
/**
* @brief Disable Rx overrun interrupt
* @rmtoll IMR RXOVRIE LL_UCPD_DisableIT_RxOvr
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
}
/**
* @brief Disable Rx hard resrt interrupt
* @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
}
/**
* @brief Disable Rx orderset interrupt
* @rmtoll IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
}
/**
* @brief Disable Rx non empty interrupt
* @rmtoll IMR RXNEIE LL_UCPD_DisableIT_RxNE
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
}
/**
* @brief Disable TX underrun interrupt
* @rmtoll IMR TXUNDIE LL_UCPD_DisableIT_TxUND
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
}
/**
* @brief Disable hard reset sent interrupt
* @rmtoll IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
}
/**
* @brief Disable hard reset discard interrupt
* @rmtoll IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
}
/**
* @brief Disable Tx message abort interrupt
* @rmtoll IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
}
/**
* @brief Disable Tx message sent interrupt
* @rmtoll IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
}
/**
* @brief Disable Tx message discarded interrupt
* @rmtoll IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
}
/**
* @brief Disable Tx data receive interrupt
* @rmtoll IMR TXISIE LL_UCPD_DisableIT_TxIS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
}
/**
* @brief Check if FRS interrupt enabled
* @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL);
}
/**
* @brief Check if type c event on CC2 enabled
* @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL);
}
/**
* @brief Check if type c event on CC1 enabled
* @rmtoll IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL);
}
/**
* @brief Check if Rx message end interrupt enabled
* @rmtoll IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL);
}
/**
* @brief Check if Rx overrun interrupt enabled
* @rmtoll IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL);
}
/**
* @brief Check if Rx hard resrt interrupt enabled
* @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL);
}
/**
* @brief Check if Rx orderset interrupt enabled
* @rmtoll IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL);
}
/**
* @brief Check if Rx non empty interrupt enabled
* @rmtoll IMR RXNEIE LL_UCPD_IsEnableIT_RxNE
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL);
}
/**
* @brief Check if TX underrun interrupt enabled
* @rmtoll IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL);
}
/**
* @brief Check if hard reset sent interrupt enabled
* @rmtoll IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL);
}
/**
* @brief Check if hard reset discard interrupt enabled
* @rmtoll IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message abort interrupt enabled
* @rmtoll IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message sent interrupt enabled
* @rmtoll IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message discarded interrupt enabled
* @rmtoll IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL);
}
/**
* @brief Check if Tx data receive interrupt enabled
* @rmtoll IMR TXISIE LL_UCPD_IsEnableIT_TxIS
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear
* @{
*/
/**
* @brief Clear FRS interrupt
* @rmtoll ICR FRSEVTIE LL_UCPD_ClearFlag_FRS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_FRS(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_FRSEVTCF);
}
/**
* @brief Clear type c event on CC2
* @rmtoll IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF);
}
/**
* @brief Clear type c event on CC1
* @rmtoll IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF);
}
/**
* @brief Clear Rx message end interrupt
* @rmtoll ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF);
}
/**
* @brief Clear Rx overrun interrupt
* @rmtoll ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF);
}
/**
* @brief Clear Rx hard resrt interrupt
* @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF);
}
/**
* @brief Clear Rx orderset interrupt
* @rmtoll ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF);
}
/**
* @brief Clear TX underrun interrupt
* @rmtoll ICR TXUNDIE LL_UCPD_ClearFlag_TxUND
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF);
}
/**
* @brief Clear hard reset sent interrupt
* @rmtoll ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF);
}
/**
* @brief Clear hard reset discard interrupt
* @rmtoll ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF);
}
/**
* @brief Clear Tx message abort interrupt
* @rmtoll ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF);
}
/**
* @brief Clear Tx message sent interrupt
* @rmtoll ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF);
}
/**
* @brief Clear Tx message discarded interrupt
* @rmtoll ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF);
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Check if FRS interrupt
* @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL);
}
/**
* @brief Check if type c event on CC2
* @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL);
}
/**
* @brief Check if type c event on CC1
* @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL);
}
/**
* @brief Check if Rx message end interrupt
* @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL);
}
/**
* @brief Check if Rx overrun interrupt
* @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL);
}
/**
* @brief Check if Rx hard resrt interrupt
* @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL);
}
/**
* @brief Check if Rx orderset interrupt
* @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL);
}
/**
* @brief Check if Rx non empty interrupt
* @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL);
}
/**
* @brief Check if TX underrun interrupt
* @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL);
}
/**
* @brief Check if hard reset sent interrupt
* @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL);
}
/**
* @brief Check if hard reset discard interrupt
* @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message abort interrupt
* @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message sent interrupt
* @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message discarded interrupt
* @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL);
}
/**
* @brief Check if Tx data receive interrupt
* @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL);
}
/**
* @brief return the vstate value for CC2
* @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC2
* @param UCPDx UCPD Instance
* @retval val
*/
__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx)
{
return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2;
}
/**
* @brief return the vstate value for CC1
* @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC1
* @param UCPDx UCPD Instance
* @retval val
*/
__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx)
{
return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1;
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Rx DMA Enable
* @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMAEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
}
/**
* @brief Rx DMA Disable
* @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMADisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
}
/**
* @brief Tx DMA Enable
* @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMAEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
}
/**
* @brief Tx DMA Disable
* @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMADisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
}
/**
* @brief Check if DMA Tx is enabled
* @rmtoll CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Check if DMA Rx is enabled
* @rmtoll CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_DATA_Management DATA Management
* @{
*/
/**
* @brief write the orderset for Tx message
* @rmtoll TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet
* @param UCPDx UCPD Instance
* @param TxOrderSet one of the following value
* @arg @ref LL_UCPD_ORDERED_SET_SOP
* @arg @ref LL_UCPD_ORDERED_SET_SOP1
* @arg @ref LL_UCPD_ORDERED_SET_SOP2
* @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET
* @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET
* @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG
* @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG
* @retval None
*/
__STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
{
WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet);
}
/**
* @brief write the Tx paysize
* @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize
* @param UCPDx UCPD Instance
* @param TxPaySize
* @retval None.
*/
__STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
{
WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize);
}
/**
* @brief Write data
* @rmtoll TXDR DR LL_UCPD_WriteData
* @param UCPDx UCPD Instance
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None.
*/
__STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data)
{
WRITE_REG(UCPDx->TXDR, Data);
}
/**
* @brief read RX the orderset
* @rmtoll RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet
* @param UCPDx UCPD Instance
* @retval RxOrderSet one of the following value
* @arg @ref LL_UCPD_RXORDSET_SOP
* @arg @ref LL_UCPD_RXORDSET_SOP1
* @arg @ref LL_UCPD_RXORDSET_SOP2
* @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG
* @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG
* @arg @ref LL_UCPD_RXORDSET_CABLE_RESET
* @arg @ref LL_UCPD_RXORDSET_SOPEXT1
* @arg @ref LL_UCPD_RXORDSET_SOPEXT2
*/
__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx)
{
return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET);
}
/**
* @brief Read the Rx paysize
* @rmtoll RX_PAYSZ RXPAYSZ LL_UCPD_ReadRxPaySize
* @param UCPDx UCPD Instance
* @retval RXPaysize.
*/
__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx)
{
return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ);
}
/**
* @brief Read data
* @rmtoll TXDR RXDATA LL_UCPD_ReadData
* @param UCPDx UCPD Instance
* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx)
{
return READ_REG(UCPDx->RXDR);
}
/**
* @brief Set Rx OrderSet Ext1
* @rmtoll RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1
* @param UCPDx UCPD Instance
* @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
{
WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt);
}
/**
* @brief Set Rx OrderSet Ext2
* @rmtoll RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2
* @param UCPDx UCPD Instance
* @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
{
WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct);
void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
#endif /* defined (UCPD1) */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_UCPD_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h
|
C
|
apache-2.0
| 62,487
|
/**
******************************************************************************
* @file stm32u5xx_ll_usart.h
* @author MCD Application Team
* @brief Header file of USART LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_USART_H
#define STM32U5xx_LL_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
/** @defgroup USART_LL USART
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup USART_LL_Private_Variables USART Private Variables
* @{
*/
/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
static const uint32_t USART_PRESCALER_TAB[] =
{
1UL,
2UL,
4UL,
6UL,
8UL,
10UL,
12UL,
16UL,
32UL,
64UL,
128UL,
256UL
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_ES_INIT USART Exported Init structures
* @{
*/
/**
* @brief LL USART Init Structure definition
*/
typedef struct
{
uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
This parameter can be a value of @ref USART_LL_EC_PRESCALER.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetPrescaler().*/
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_LL_EC_STOPBITS.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_LL_EC_PARITY.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_DIRECTION.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetHWFlowCtrl().*/
uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetOverSampling().*/
} LL_USART_InitTypeDef;
/**
* @brief LL USART Clock Init Structure definition
*/
typedef struct
{
uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_CLOCK.
USART HW configuration can be modified afterwards using unitary functions
@ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
For more details, refer to description of this function. */
uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_LL_EC_POLARITY.
USART HW configuration can be modified afterwards using unitary
functions @ref LL_USART_SetClockPolarity().
For more details, refer to description of this function. */
uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_LL_EC_PHASE.
USART HW configuration can be modified afterwards using unitary
functions @ref LL_USART_SetClockPhase().
For more details, refer to description of this function. */
uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
USART HW configuration can be modified afterwards using unitary
functions @ref LL_USART_SetLastClkPulseOutput().
For more details, refer to description of this function. */
} LL_USART_ClockInitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_LL_Exported_Constants USART Exported Constants
* @{
*/
/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_USART_WriteReg function
* @{
*/
#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */
#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */
#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */
#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */
#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */
#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */
#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
/**
* @}
*/
/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_USART_ReadReg function
* @{
*/
#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */
#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */
#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */
#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */
#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */
#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */
#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */
#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */
#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */
#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
/**
* @}
*/
/** @defgroup USART_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
* @{
*/
#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */
#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */
#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */
#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */
#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */
#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
/**
* @}
*/
/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
* @{
*/
#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
/**
* @}
*/
/** @defgroup USART_LL_EC_DIRECTION Communication Direction
* @{
*/
#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
/**
* @}
*/
/** @defgroup USART_LL_EC_PARITY Parity Control
* @{
*/
#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
/**
* @}
*/
/** @defgroup USART_LL_EC_WAKEUP Wakeup
* @{
*/
#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
/**
* @}
*/
/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
* @{
*/
#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
/**
* @}
*/
/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
* @{
*/
#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_EC_CLOCK Clock Signal
* @{
*/
#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
* @{
*/
#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
/**
* @}
*/
/** @defgroup USART_LL_EC_PHASE Clock Phase
* @{
*/
#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */
#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
/**
* @}
*/
/** @defgroup USART_LL_EC_POLARITY Clock Polarity
* @{
*/
#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
/**
* @}
*/
/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
/** @defgroup USART_LL_EC_STOPBITS Stop Bits
* @{
*/
#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
/**
* @}
*/
/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
* @{
*/
#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
/**
* @}
*/
/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
* @{
*/
#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
/**
* @}
*/
/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
* @{
*/
#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
/**
* @}
*/
/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
* @{
*/
#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
/**
* @}
*/
/** @defgroup USART_LL_EC_BITORDER Bit Order
* @{
*/
#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
/**
* @}
*/
/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
* @{
*/
#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */
#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */
#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
/**
* @}
*/
/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
* @{
*/
#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
/**
* @}
*/
/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
* @{
*/
#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
/**
* @}
*/
/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
* @{
*/
#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
/**
* @}
*/
/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
* @{
*/
#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */
#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
/**
* @}
*/
/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
* @{
*/
#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
/**
* @}
*/
/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
/**
* @}
*/
/** @defgroup USART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger Selection
* @brief USART Autonomous Trigger selection
* @{
*/
#define LL_USART_GPDMA1_CH0_TCF_TRG 0U /*!< USART GPDMA1 channel0 Internal Trigger */
#define LL_USART_GPDMA1_CH1_TCF_TRG 1U /*!< USART GPDMA1 channel1 Internal Trigger */
#define LL_USART_GPDMA1_CH2_TCF_TRG 2U /*!< USART GPDMA1 channel2 Internal Trigger */
#define LL_USART_GPDMA1_CH3_TCF_TRG 3U /*!< USART GPDMA1 channel3 Internal Trigger */
#define LL_USART_EXTI_LINE6_TRG 4U /*!< USART EXTI line 6 Internal Trigger */
#define LL_USART_EXTI_LINE9_TRG 5U /*!< USART EXTI line 9 Internal Trigger */
#define LL_USART_LPTIM1_OUT_TRG 6U /*!< USART LPTIM1 out Internal Trigger */
#define LL_USART_LPTIM2_OUT_TRG 7U /*!< USART LPTIM2 out Internal Trigger */
#define LL_USART_COMP1_OUT_TRG 8U /*!< USART COMP1 out Internal Trigger */
#define LL_USART_COMP2_OUT_TRG 9U /*!< USART COMP2 out Internal Trigger */
#define LL_USART_RTC_ALRA_TRG 10U /*!< USART RTC alarm Internal Trigger */
#define LL_USART_RTC_WUT_TRG 11U /*!< USART RTC wakeup Internal Trigger */
/**
* @}
*/
/** @defgroup USART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity
* @brief USART Autonomous Trigger Polarity
* @{
*/
#define LL_USART_TRIG_POLARITY_RISING 0x00000000U /*!< USART triggered on rising edge */
#define LL_USART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< USART triggered on falling edge */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup USART_LL_Exported_Macros USART Exported Macros
* @{
*/
/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in USART register
* @param __INSTANCE__ USART Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in USART register
* @param __INSTANCE__ USART Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
* @{
*/
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
* expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
* @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
* @param __PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
(((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
* expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
* @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
* @param __PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup USART_LL_Exported_Functions USART Exported Functions
* @{
*/
/** @defgroup USART_LL_EF_Configuration Configuration functions
* @{
*/
/**
* @brief USART Enable
* @rmtoll CR1 UE LL_USART_Enable
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR1, USART_CR1_UE);
}
/**
* @brief USART Disable (all USART prescalers and outputs are disabled)
* @note When USART is disabled, USART prescalers and outputs are stopped immediately,
* and current operations are discarded. The configuration of the USART is kept, but all the status
* flags, in the USARTx_ISR are set to their default values.
* @rmtoll CR1 UE LL_USART_Disable
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
}
/**
* @brief Indicate if USART is enabled
* @rmtoll CR1 UE LL_USART_IsEnabled
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
/**
* @brief FIFO Mode Enable
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_EnableFIFO
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
}
/**
* @brief FIFO Mode Disable
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_DisableFIFO
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
}
/**
* @brief Indicate if FIFO Mode is enabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
}
/**
* @brief Configure TX FIFO Threshold
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
* @param USARTx USART Instance
* @param Threshold This parameter can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
{
ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
}
/**
* @brief Return TX FIFO Threshold Configuration
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
*/
__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
}
/**
* @brief Configure RX FIFO Threshold
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
* @param USARTx USART Instance
* @param Threshold This parameter can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
{
ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
}
/**
* @brief Return RX FIFO Threshold Configuration
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
*/
__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
}
/**
* @brief Configure TX and RX FIFOs Threshold
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n
* CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
* @param USARTx USART Instance
* @param TXThreshold This parameter can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
* @param RXThreshold This parameter can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
(RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
* @brief USART enabled in STOP Mode.
* @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
* USART clock selection is HSI or LSE in RCC.
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_EnableInStopMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
}
/**
* @brief USART disabled in STOP Mode.
* @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_DisableInStopMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
}
/**
* @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
}
/**
* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
* @rmtoll CR1 RE LL_USART_EnableDirectionRx
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
}
/**
* @brief Receiver Disable
* @rmtoll CR1 RE LL_USART_DisableDirectionRx
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
}
/**
* @brief Transmitter Enable
* @rmtoll CR1 TE LL_USART_EnableDirectionTx
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
}
/**
* @brief Transmitter Disable
* @rmtoll CR1 TE LL_USART_DisableDirectionTx
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
}
/**
* @brief Configure simultaneously enabled/disabled states
* of Transmitter and Receiver
* @rmtoll CR1 RE LL_USART_SetTransferDirection\n
* CR1 TE LL_USART_SetTransferDirection
* @param USARTx USART Instance
* @param TransferDirection This parameter can be one of the following values:
* @arg @ref LL_USART_DIRECTION_NONE
* @arg @ref LL_USART_DIRECTION_RX
* @arg @ref LL_USART_DIRECTION_TX
* @arg @ref LL_USART_DIRECTION_TX_RX
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
{
ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
}
/**
* @brief Return enabled/disabled states of Transmitter and Receiver
* @rmtoll CR1 RE LL_USART_GetTransferDirection\n
* CR1 TE LL_USART_GetTransferDirection
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_DIRECTION_NONE
* @arg @ref LL_USART_DIRECTION_RX
* @arg @ref LL_USART_DIRECTION_TX
* @arg @ref LL_USART_DIRECTION_TX_RX
*/
__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
}
/**
* @brief Configure Parity (enabled/disabled and parity mode if enabled).
* @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
* When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
* (9th or 8th bit depending on data width) and parity is checked on the received data.
* @rmtoll CR1 PS LL_USART_SetParity\n
* CR1 PCE LL_USART_SetParity
* @param USARTx USART Instance
* @param Parity This parameter can be one of the following values:
* @arg @ref LL_USART_PARITY_NONE
* @arg @ref LL_USART_PARITY_EVEN
* @arg @ref LL_USART_PARITY_ODD
* @retval None
*/
__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
{
MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
}
/**
* @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
* @rmtoll CR1 PS LL_USART_GetParity\n
* CR1 PCE LL_USART_GetParity
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_PARITY_NONE
* @arg @ref LL_USART_PARITY_EVEN
* @arg @ref LL_USART_PARITY_ODD
*/
__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
}
/**
* @brief Set Receiver Wake Up method from Mute mode.
* @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
* @param USARTx USART Instance
* @param Method This parameter can be one of the following values:
* @arg @ref LL_USART_WAKEUP_IDLELINE
* @arg @ref LL_USART_WAKEUP_ADDRESSMARK
* @retval None
*/
__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
{
MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
}
/**
* @brief Return Receiver Wake Up method from Mute mode
* @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_WAKEUP_IDLELINE
* @arg @ref LL_USART_WAKEUP_ADDRESSMARK
*/
__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
}
/**
* @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
* @rmtoll CR1 M0 LL_USART_SetDataWidth\n
* CR1 M1 LL_USART_SetDataWidth
* @param USARTx USART Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_USART_DATAWIDTH_7B
* @arg @ref LL_USART_DATAWIDTH_8B
* @arg @ref LL_USART_DATAWIDTH_9B
* @retval None
*/
__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
{
MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
}
/**
* @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
* @rmtoll CR1 M0 LL_USART_GetDataWidth\n
* CR1 M1 LL_USART_GetDataWidth
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_DATAWIDTH_7B
* @arg @ref LL_USART_DATAWIDTH_8B
* @arg @ref LL_USART_DATAWIDTH_9B
*/
__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
}
/**
* @brief Allow switch between Mute Mode and Active mode
* @rmtoll CR1 MME LL_USART_EnableMuteMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
}
/**
* @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
* @rmtoll CR1 MME LL_USART_DisableMuteMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
}
/**
* @brief Indicate if switch between Mute Mode and Active mode is allowed
* @rmtoll CR1 MME LL_USART_IsEnabledMuteMode
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
}
/**
* @brief Set Oversampling to 8-bit or 16-bit mode
* @rmtoll CR1 OVER8 LL_USART_SetOverSampling
* @param USARTx USART Instance
* @param OverSampling This parameter can be one of the following values:
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
* @retval None
*/
__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
{
MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
}
/**
* @brief Return Oversampling mode
* @rmtoll CR1 OVER8 LL_USART_GetOverSampling
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
*/
__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
}
/**
* @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
* @param USARTx USART Instance
* @param LastBitClockPulse This parameter can be one of the following values:
* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
* @retval None
*/
__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
{
MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
}
/**
* @brief Retrieve Clock pulse of the last data bit output configuration
* (Last bit Clock pulse output to the SCLK pin or not)
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
*/
__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
}
/**
* @brief Select the phase of the clock output on the SCLK pin in synchronous mode
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_SetClockPhase
* @param USARTx USART Instance
* @param ClockPhase This parameter can be one of the following values:
* @arg @ref LL_USART_PHASE_1EDGE
* @arg @ref LL_USART_PHASE_2EDGE
* @retval None
*/
__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
{
MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
}
/**
* @brief Return phase of the clock output on the SCLK pin in synchronous mode
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_GetClockPhase
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_PHASE_1EDGE
* @arg @ref LL_USART_PHASE_2EDGE
*/
__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
}
/**
* @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_SetClockPolarity
* @param USARTx USART Instance
* @param ClockPolarity This parameter can be one of the following values:
* @arg @ref LL_USART_POLARITY_LOW
* @arg @ref LL_USART_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
{
MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
}
/**
* @brief Return polarity of the clock output on the SCLK pin in synchronous mode
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_GetClockPolarity
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_POLARITY_LOW
* @arg @ref LL_USART_POLARITY_HIGH
*/
__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
}
/**
* @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
* - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
* - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
* @rmtoll CR2 CPHA LL_USART_ConfigClock\n
* CR2 CPOL LL_USART_ConfigClock\n
* CR2 LBCL LL_USART_ConfigClock
* @param USARTx USART Instance
* @param Phase This parameter can be one of the following values:
* @arg @ref LL_USART_PHASE_1EDGE
* @arg @ref LL_USART_PHASE_2EDGE
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_USART_POLARITY_LOW
* @arg @ref LL_USART_POLARITY_HIGH
* @param LBCPOutput This parameter can be one of the following values:
* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
{
MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
}
/**
* @brief Configure Clock source prescaler for baudrate generator and oversampling
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll PRESC PRESCALER LL_USART_SetPrescaler
* @param USARTx USART Instance
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
* @retval None
*/
__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
}
/**
* @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll PRESC PRESCALER LL_USART_GetPrescaler
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
*/
__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
}
/**
* @brief Enable Clock output on SCLK pin
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
}
/**
* @brief Disable Clock output on SCLK pin
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
}
/**
* @brief Indicate if Clock output on SCLK pin is enabled
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
}
/**
* @brief Set the length of the stop bits
* @rmtoll CR2 STOP LL_USART_SetStopBitsLength
* @param USARTx USART Instance
* @param StopBits This parameter can be one of the following values:
* @arg @ref LL_USART_STOPBITS_0_5
* @arg @ref LL_USART_STOPBITS_1
* @arg @ref LL_USART_STOPBITS_1_5
* @arg @ref LL_USART_STOPBITS_2
* @retval None
*/
__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
{
MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
}
/**
* @brief Retrieve the length of the stop bits
* @rmtoll CR2 STOP LL_USART_GetStopBitsLength
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_STOPBITS_0_5
* @arg @ref LL_USART_STOPBITS_1
* @arg @ref LL_USART_STOPBITS_1_5
* @arg @ref LL_USART_STOPBITS_2
*/
__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
}
/**
* @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
* @note Call of this function is equivalent to following function call sequence :
* - Data Width configuration using @ref LL_USART_SetDataWidth() function
* - Parity Control and mode configuration using @ref LL_USART_SetParity() function
* - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
* @rmtoll CR1 PS LL_USART_ConfigCharacter\n
* CR1 PCE LL_USART_ConfigCharacter\n
* CR1 M0 LL_USART_ConfigCharacter\n
* CR1 M1 LL_USART_ConfigCharacter\n
* CR2 STOP LL_USART_ConfigCharacter
* @param USARTx USART Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_USART_DATAWIDTH_7B
* @arg @ref LL_USART_DATAWIDTH_8B
* @arg @ref LL_USART_DATAWIDTH_9B
* @param Parity This parameter can be one of the following values:
* @arg @ref LL_USART_PARITY_NONE
* @arg @ref LL_USART_PARITY_EVEN
* @arg @ref LL_USART_PARITY_ODD
* @param StopBits This parameter can be one of the following values:
* @arg @ref LL_USART_STOPBITS_0_5
* @arg @ref LL_USART_STOPBITS_1
* @arg @ref LL_USART_STOPBITS_1_5
* @arg @ref LL_USART_STOPBITS_2
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
uint32_t StopBits)
{
MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
}
/**
* @brief Configure TX/RX pins swapping setting.
* @rmtoll CR2 SWAP LL_USART_SetTXRXSwap
* @param USARTx USART Instance
* @param SwapConfig This parameter can be one of the following values:
* @arg @ref LL_USART_TXRX_STANDARD
* @arg @ref LL_USART_TXRX_SWAPPED
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
{
MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
}
/**
* @brief Retrieve TX/RX pins swapping configuration.
* @rmtoll CR2 SWAP LL_USART_GetTXRXSwap
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_TXRX_STANDARD
* @arg @ref LL_USART_TXRX_SWAPPED
*/
__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
}
/**
* @brief Configure RX pin active level logic
* @rmtoll CR2 RXINV LL_USART_SetRXPinLevel
* @param USARTx USART Instance
* @param PinInvMethod This parameter can be one of the following values:
* @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
{
MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
}
/**
* @brief Retrieve RX pin active level logic configuration
* @rmtoll CR2 RXINV LL_USART_GetRXPinLevel
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
*/
__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
}
/**
* @brief Configure TX pin active level logic
* @rmtoll CR2 TXINV LL_USART_SetTXPinLevel
* @param USARTx USART Instance
* @param PinInvMethod This parameter can be one of the following values:
* @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
{
MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
}
/**
* @brief Retrieve TX pin active level logic configuration
* @rmtoll CR2 TXINV LL_USART_GetTXPinLevel
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
*/
__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
}
/**
* @brief Configure Binary data logic.
* @note Allow to define how Logical data from the data register are send/received :
* either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
* @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic
* @param USARTx USART Instance
* @param DataLogic This parameter can be one of the following values:
* @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
* @retval None
*/
__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
{
MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
}
/**
* @brief Retrieve Binary data configuration
* @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
*/
__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
}
/**
* @brief Configure transfer bit order (either Less or Most Significant Bit First)
* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
* @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder
* @param USARTx USART Instance
* @param BitOrder This parameter can be one of the following values:
* @arg @ref LL_USART_BITORDER_LSBFIRST
* @arg @ref LL_USART_BITORDER_MSBFIRST
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
{
MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
}
/**
* @brief Return transfer bit order (either Less or Most Significant Bit First)
* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
* @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_BITORDER_LSBFIRST
* @arg @ref LL_USART_BITORDER_MSBFIRST
*/
__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
}
/**
* @brief Enable Auto Baud-Rate Detection
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_ABREN);
}
/**
* @brief Disable Auto Baud-Rate Detection
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
}
/**
* @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
}
/**
* @brief Set Auto Baud-Rate mode bits
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
* @param USARTx USART Instance
* @param AutoBaudRateMode This parameter can be one of the following values:
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
* @retval None
*/
__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
{
MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
}
/**
* @brief Return Auto Baud-Rate mode
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
*/
__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
}
/**
* @brief Enable Receiver Timeout
* @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
}
/**
* @brief Disable Receiver Timeout
* @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
}
/**
* @brief Indicate if Receiver Timeout feature is enabled
* @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
}
/**
* @brief Set Address of the USART node.
* @note This is used in multiprocessor communication during Mute mode or Stop mode,
* for wake up with address mark detection.
* @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
* (b7-b4 should be set to 0)
* 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
* (This is used in multiprocessor communication during Mute mode or Stop mode,
* for wake up with 7-bit address mark detection.
* The MSB of the character sent by the transmitter should be equal to 1.
* It may also be used for character detection during normal reception,
* Mute mode inactive (for example, end of block detection in ModBus protocol).
* In this case, the whole received character (8-bit) is compared to the ADD[7:0]
* value and CMF flag is set on match)
* @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n
* CR2 ADDM7 LL_USART_ConfigNodeAddress
* @param USARTx USART Instance
* @param AddressLen This parameter can be one of the following values:
* @arg @ref LL_USART_ADDRESS_DETECT_4B
* @arg @ref LL_USART_ADDRESS_DETECT_7B
* @param NodeAddress 4 or 7 bit Address of the USART node.
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
{
MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
(uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
}
/**
* @brief Return 8 bit Address of the USART node as set in ADD field of CR2.
* @note If 4-bit Address Detection is selected in ADDM7,
* only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
* If 7-bit Address Detection is selected in ADDM7,
* only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
* @rmtoll CR2 ADD LL_USART_GetNodeAddress
* @param USARTx USART Instance
* @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
*/
__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
}
/**
* @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
* @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_ADDRESS_DETECT_4B
* @arg @ref LL_USART_ADDRESS_DETECT_7B
*/
__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
}
/**
* @brief Enable RTS HW Flow Control
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_RTSE);
}
/**
* @brief Disable RTS HW Flow Control
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
}
/**
* @brief Enable CTS HW Flow Control
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_CTSE);
}
/**
* @brief Disable CTS HW Flow Control
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
}
/**
* @brief Configure HW Flow Control mode (both CTS and RTS)
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
* CR3 CTSE LL_USART_SetHWFlowCtrl
* @param USARTx USART Instance
* @param HardwareFlowControl This parameter can be one of the following values:
* @arg @ref LL_USART_HWCONTROL_NONE
* @arg @ref LL_USART_HWCONTROL_RTS
* @arg @ref LL_USART_HWCONTROL_CTS
* @arg @ref LL_USART_HWCONTROL_RTS_CTS
* @retval None
*/
__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
{
MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
}
/**
* @brief Return HW Flow Control configuration (both CTS and RTS)
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
* CR3 CTSE LL_USART_GetHWFlowCtrl
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_HWCONTROL_NONE
* @arg @ref LL_USART_HWCONTROL_RTS
* @arg @ref LL_USART_HWCONTROL_CTS
* @arg @ref LL_USART_HWCONTROL_RTS_CTS
*/
__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
}
/**
* @brief Enable One bit sampling method
* @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
}
/**
* @brief Disable One bit sampling method
* @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
}
/**
* @brief Indicate if One bit sampling method is enabled
* @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
}
/**
* @brief Enable Overrun detection
* @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
}
/**
* @brief Disable Overrun detection
* @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
}
/**
* @brief Indicate if Overrun detection is enabled
* @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
/**
* @brief Configure USART BRR register for achieving expected Baud Rate value.
* @note Compute and set USARTDIV value in BRR Register (full BRR content)
* according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
* @note Peripheral clock and Baud rate values provided as function parameters should be valid
* (Baud rate value != 0)
* @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
* @rmtoll BRR BRR LL_USART_SetBaudRate
* @param USARTx USART Instance
* @param PeriphClk Peripheral Clock
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
* @param OverSampling This parameter can be one of the following values:
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
* @param BaudRate Baud Rate
* @retval None
*/
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling,
uint32_t BaudRate)
{
uint32_t usartdiv;
uint32_t brrtemp;
if (PrescalerValue > LL_USART_PRESCALER_DIV256)
{
/* Do not overstep the size of USART_PRESCALER_TAB */
}
else if (BaudRate == 0U)
{
/* Can Not divide per 0 */
}
else if (OverSampling == LL_USART_OVERSAMPLING_8)
{
usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
brrtemp = usartdiv & 0xFFF0U;
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
USARTx->BRR = brrtemp;
}
else
{
USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
}
}
/**
* @brief Return current Baud Rate value, according to USARTDIV present in BRR register
* (full BRR content), and to used Peripheral Clock and Oversampling mode values
* @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
* @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
* @rmtoll BRR BRR LL_USART_GetBaudRate
* @param USARTx USART Instance
* @param PeriphClk Peripheral Clock
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
* @param OverSampling This parameter can be one of the following values:
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
* @retval Baud Rate
*/
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling)
{
uint32_t usartdiv;
uint32_t brrresult = 0x0U;
uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
usartdiv = USARTx->BRR;
if (usartdiv == 0U)
{
/* Do not perform a division by 0 */
}
else if (OverSampling == LL_USART_OVERSAMPLING_8)
{
usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
if (usartdiv != 0U)
{
brrresult = (periphclkpresc * 2U) / usartdiv;
}
}
else
{
if ((usartdiv & 0xFFFFU) != 0U)
{
brrresult = periphclkpresc / usartdiv;
}
}
return (brrresult);
}
/**
* @brief Set Receiver Time Out Value (expressed in nb of bits duration)
* @rmtoll RTOR RTO LL_USART_SetRxTimeout
* @param USARTx USART Instance
* @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
* @retval None
*/
__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
{
MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
}
/**
* @brief Get Receiver Time Out Value (expressed in nb of bits duration)
* @rmtoll RTOR RTO LL_USART_GetRxTimeout
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
*/
__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
}
/**
* @brief Set Block Length value in reception
* @rmtoll RTOR BLEN LL_USART_SetBlockLength
* @param USARTx USART Instance
* @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
{
MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
}
/**
* @brief Get Block Length value in reception
* @rmtoll RTOR BLEN LL_USART_GetBlockLength
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
* @{
*/
/**
* @brief Enable IrDA mode
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_EnableIrda
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_IREN);
}
/**
* @brief Disable IrDA mode
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_DisableIrda
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
}
/**
* @brief Indicate if IrDA mode is enabled
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_IsEnabledIrda
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
}
/**
* @brief Configure IrDA Power Mode (Normal or Low Power)
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
* @param USARTx USART Instance
* @param PowerMode This parameter can be one of the following values:
* @arg @ref LL_USART_IRDA_POWER_NORMAL
* @arg @ref LL_USART_IRDA_POWER_LOW
* @retval None
*/
__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
{
MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
}
/**
* @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_IRDA_POWER_NORMAL
* @arg @ref LL_USART_PHASE_2EDGE
*/
__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
}
/**
* @brief Set Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
* @param USARTx USART Instance
* @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
* @brief Return Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
* @param USARTx USART Instance
* @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
*/
__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
* @{
*/
/**
* @brief Enable Smartcard NACK transmission
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_NACK);
}
/**
* @brief Disable Smartcard NACK transmission
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
}
/**
* @brief Indicate if Smartcard NACK transmission is enabled
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
}
/**
* @brief Enable Smartcard mode
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_EnableSmartcard
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_SCEN);
}
/**
* @brief Disable Smartcard mode
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_DisableSmartcard
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
}
/**
* @brief Indicate if Smartcard mode is enabled
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
}
/**
* @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
* In transmission mode, it specifies the number of automatic retransmission retries, before
* generating a transmission error (FE bit set).
* In reception mode, it specifies the number or erroneous reception trials, before generating a
* reception error (RXNE and PE bits set)
* @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
* @param USARTx USART Instance
* @param AutoRetryCount Value between Min_Data=0 and Max_Data=7
* @retval None
*/
__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
{
MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
}
/**
* @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
* @param USARTx USART Instance
* @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
*/
__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
}
/**
* @brief Set Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
* @param USARTx USART Instance
* @param PrescalerValue Value between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
* @brief Return Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
* @param USARTx USART Instance
* @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
*/
__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
}
/**
* @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
* @param USARTx USART Instance
* @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
{
MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
}
/**
* @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
* @param USARTx USART Instance
* @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
*/
__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
* @{
*/
/**
* @brief Enable Single Wire Half-Duplex mode
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
}
/**
* @brief Disable Single Wire Half-Duplex mode
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
}
/**
* @brief Indicate if Single Wire Half-Duplex mode is enabled
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
* @{
*/
/**
* @brief Enable SPI Synchronous Slave mode
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_EnableSPISlave
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
}
/**
* @brief Disable SPI Synchronous Slave mode
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_DisableSPISlave
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
}
/**
* @brief Indicate if SPI Synchronous Slave mode is enabled
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
}
/**
* @brief Enable SPI Slave Selection using NSS input pin
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @note SPI Slave Selection depends on NSS input pin
* (The slave is selected when NSS is low and deselected when NSS is high).
* @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
}
/**
* @brief Disable SPI Slave Selection using NSS input pin
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @note SPI Slave will be always selected and NSS input pin will be ignored.
* @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
}
/**
* @brief Indicate if SPI Slave Selection depends on NSS input pin
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
* @{
*/
/**
* @brief Set LIN Break Detection Length
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
* @param USARTx USART Instance
* @param LINBDLength This parameter can be one of the following values:
* @arg @ref LL_USART_LINBREAK_DETECT_10B
* @arg @ref LL_USART_LINBREAK_DETECT_11B
* @retval None
*/
__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
{
MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
}
/**
* @brief Return LIN Break Detection Length
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_LINBREAK_DETECT_10B
* @arg @ref LL_USART_LINBREAK_DETECT_11B
*/
__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
}
/**
* @brief Enable LIN mode
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_EnableLIN
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_LINEN);
}
/**
* @brief Disable LIN mode
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_DisableLIN
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
}
/**
* @brief Indicate if LIN mode is enabled
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
* @{
*/
/**
* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
* @param USARTx USART Instance
* @param Time Value between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
{
MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
}
/**
* @brief Return DEDT (Driver Enable De-Assertion Time)
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
* @param USARTx USART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
*/
__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
}
/**
* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
* @param USARTx USART Instance
* @param Time Value between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
{
MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
}
/**
* @brief Return DEAT (Driver Enable Assertion Time)
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
* @param USARTx USART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
*/
__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
}
/**
* @brief Enable Driver Enable (DE) Mode
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_EnableDEMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_DEM);
}
/**
* @brief Disable Driver Enable (DE) Mode
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_DisableDEMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
}
/**
* @brief Indicate if Driver Enable (DE) Mode is enabled
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
}
/**
* @brief Select Driver Enable Polarity
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
* @param USARTx USART Instance
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_USART_DE_POLARITY_HIGH
* @arg @ref LL_USART_DE_POLARITY_LOW
* @retval None
*/
__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
{
MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
}
/**
* @brief Return Driver Enable Polarity
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_DE_POLARITY_HIGH
* @arg @ref LL_USART_DE_POLARITY_LOW
*/
__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
}
/**
* @}
*/
/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
* @{
*/
/**
* @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
* @note In UART mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - CLKEN bit in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* @note Other remaining configurations items related to Asynchronous Mode
* (as Baud Rate, Word length, Parity, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
* CR2 CLKEN LL_USART_ConfigAsyncMode\n
* CR3 SCEN LL_USART_ConfigAsyncMode\n
* CR3 IREN LL_USART_ConfigAsyncMode\n
* CR3 HDSEL LL_USART_ConfigAsyncMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN, CLKEN bits in the USART_CR2 register,
- SCEN, IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
}
/**
* @brief Perform basic configuration of USART for enabling use in Synchronous Mode
* @note In Synchronous mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the USART in Synchronous mode.
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
* @note Other remaining configurations items related to Synchronous Mode
* (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
* CR2 CLKEN LL_USART_ConfigSyncMode\n
* CR3 SCEN LL_USART_ConfigSyncMode\n
* CR3 IREN LL_USART_ConfigSyncMode\n
* CR3 HDSEL LL_USART_ConfigSyncMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- SCEN, IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
/* set the UART/USART in Synchronous mode */
SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
}
/**
* @brief Perform basic configuration of USART for enabling use in LIN Mode
* @note In LIN mode, the following bits must be kept cleared:
* - STOP and CLKEN bits in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also set the UART/USART in LIN mode.
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
* - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
* @note Other remaining configurations items related to LIN Mode
* (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
* dedicated functions
* @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
* CR2 STOP LL_USART_ConfigLINMode\n
* CR2 LINEN LL_USART_ConfigLINMode\n
* CR3 IREN LL_USART_ConfigLINMode\n
* CR3 SCEN LL_USART_ConfigLINMode\n
* CR3 HDSEL LL_USART_ConfigLINMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- IREN, SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
/* Set the UART/USART in LIN mode */
SET_BIT(USARTx->CR2, USART_CR2_LINEN);
}
/**
* @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
* @note In Half Duplex mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - CLKEN bit in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* This function also sets the UART/USART in Half Duplex mode.
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
* @note Other remaining configurations items related to Half Duplex Mode
* (as Baud Rate, Word length, Parity, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
* CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
* CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
* CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
* CR3 IREN LL_USART_ConfigHalfDuplexMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
{
/* In Half Duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
/* set the UART/USART in Half Duplex mode */
SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
}
/**
* @brief Perform basic configuration of USART for enabling use in Smartcard Mode
* @note In Smartcard mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also configures Stop bits to 1.5 bits and
* sets the USART in Smartcard mode (SCEN bit).
* Clock Output is also enabled (CLKEN).
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
* - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
* - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
* @note Other remaining configurations items related to Smartcard Mode
* (as Baud Rate, Word length, Parity, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
* CR2 STOP LL_USART_ConfigSmartcardMode\n
* CR2 CLKEN LL_USART_ConfigSmartcardMode\n
* CR3 HDSEL LL_USART_ConfigSmartcardMode\n
* CR3 SCEN LL_USART_ConfigSmartcardMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
{
/* In Smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Configure Stop bits to 1.5 bits */
/* Synchronous mode is activated by default */
SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
/* set the UART/USART in Smartcard mode */
SET_BIT(USARTx->CR3, USART_CR3_SCEN);
}
/**
* @brief Perform basic configuration of USART for enabling use in Irda Mode
* @note In IRDA mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - STOP and CLKEN bits in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the UART/USART in IRDA mode (IREN bit).
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
* - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
* @note Other remaining configurations items related to Irda Mode
* (as Baud Rate, Word length, Power mode, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
* CR2 CLKEN LL_USART_ConfigIrdaMode\n
* CR2 STOP LL_USART_ConfigIrdaMode\n
* CR3 SCEN LL_USART_ConfigIrdaMode\n
* CR3 HDSEL LL_USART_ConfigIrdaMode\n
* CR3 IREN LL_USART_ConfigIrdaMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
{
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
SET_BIT(USARTx->CR3, USART_CR3_IREN);
}
/**
* @brief Perform basic configuration of USART for enabling use in Multi processor Mode
* (several USARTs connected in a network, one of the USARTs can be the master,
* its TX output connected to the RX inputs of the other slaves USARTs).
* @note In MultiProcessor mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - CLKEN bit in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* @note Other remaining configurations items related to Multi processor Mode
* (as Baud Rate, Wake Up Method, Node address, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
* CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
* CR3 SCEN LL_USART_ConfigMultiProcessMode\n
* CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
* CR3 IREN LL_USART_ConfigMultiProcessMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- IREN, SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
}
/**
* @}
*/
/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if the USART Parity Error Flag is set or not
* @rmtoll ISR PE LL_USART_IsActiveFlag_PE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Framing Error Flag is set or not
* @rmtoll ISR FE LL_USART_IsActiveFlag_FE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Noise error detected Flag is set or not
* @rmtoll ISR NE LL_USART_IsActiveFlag_NE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART OverRun Error Flag is set or not
* @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART IDLE line detected Flag is set or not
* @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
/**
* @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Transmission Complete Flag is set or not
* @rmtoll ISR TC LL_USART_IsActiveFlag_TC
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
/**
* @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART LIN Break Detection Flag is set or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART CTS interrupt Flag is set or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART CTS Flag is set or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Receiver Time Out Flag is set or not
* @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART End Of Block Flag is set or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
}
/**
* @brief Check if the SPI Slave Underrun error flag is set or not
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Auto-Baud Rate Error Flag is set or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Auto-Baud Rate Flag is set or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Busy Flag is set or not
* @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Character Match Flag is set or not
* @rmtoll ISR CMF LL_USART_IsActiveFlag_CM
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Send Break Flag is set or not
* @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
* @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
* @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Receive Enable Acknowledge Flag is set or not
* @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART TX FIFO Empty Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART RX FIFO Full Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
}
/**
* @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
* @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART TX FIFO Threshold Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART RX FIFO Threshold Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
}
/**
* @brief Clear Parity Error Flag
* @rmtoll ICR PECF LL_USART_ClearFlag_PE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_PECF);
}
/**
* @brief Clear Framing Error Flag
* @rmtoll ICR FECF LL_USART_ClearFlag_FE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_FECF);
}
/**
* @brief Clear Noise Error detected Flag
* @rmtoll ICR NECF LL_USART_ClearFlag_NE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_NECF);
}
/**
* @brief Clear OverRun Error Flag
* @rmtoll ICR ORECF LL_USART_ClearFlag_ORE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
}
/**
* @brief Clear IDLE line detected Flag
* @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
}
/**
* @brief Clear TX FIFO Empty Flag
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
}
/**
* @brief Clear Transmission Complete Flag
* @rmtoll ICR TCCF LL_USART_ClearFlag_TC
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
}
/**
* @brief Clear Smartcard Transmission Complete Before Guard Time Flag
* @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
}
/**
* @brief Clear LIN Break Detection Flag
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
}
/**
* @brief Clear CTS Interrupt Flag
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
}
/**
* @brief Clear Receiver Time Out Flag
* @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
}
/**
* @brief Clear End Of Block Flag
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
}
/**
* @brief Clear SPI Slave Underrun Flag
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
}
/**
* @brief Clear Character Match Flag
* @rmtoll ICR CMCF LL_USART_ClearFlag_CM
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable IDLE Interrupt
* @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
/**
* @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
* @brief Enable Transmission Complete Interrupt
* @rmtoll CR1 TCIE LL_USART_EnableIT_TC
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
/**
* @brief Enable TX Empty and TX FIFO Not Full Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
* @brief Enable Parity Error Interrupt
* @rmtoll CR1 PEIE LL_USART_EnableIT_PE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
}
/**
* @brief Enable Character Match Interrupt
* @rmtoll CR1 CMIE LL_USART_EnableIT_CM
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
}
/**
* @brief Enable Receiver Timeout Interrupt
* @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
}
/**
* @brief Enable End Of Block Interrupt
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
}
/**
* @brief Enable TX FIFO Empty Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
}
/**
* @brief Enable RX FIFO Full Interrupt
* @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
}
/**
* @brief Enable LIN Break Detection Interrupt
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
}
/**
* @brief Enable Error Interrupt
* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
* 0: Interrupt is inhibited
* 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
* @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
}
/**
* @brief Enable CTS Interrupt
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
/**
* @brief Enable TX FIFO Threshold Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
}
/**
* @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
/**
* @brief Enable RX FIFO Threshold Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
}
/**
* @brief Disable IDLE Interrupt
* @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
/**
* @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
* @brief Disable Transmission Complete Interrupt
* @rmtoll CR1 TCIE LL_USART_DisableIT_TC
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
/**
* @brief Disable TX Empty and TX FIFO Not Full Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
* @brief Disable Parity Error Interrupt
* @rmtoll CR1 PEIE LL_USART_DisableIT_PE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
}
/**
* @brief Disable Character Match Interrupt
* @rmtoll CR1 CMIE LL_USART_DisableIT_CM
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
}
/**
* @brief Disable Receiver Timeout Interrupt
* @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
}
/**
* @brief Disable End Of Block Interrupt
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
}
/**
* @brief Disable TX FIFO Empty Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
}
/**
* @brief Disable RX FIFO Full Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
}
/**
* @brief Disable LIN Break Detection Interrupt
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
}
/**
* @brief Disable Error Interrupt
* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
* 0: Interrupt is inhibited
* 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
* @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
}
/**
* @brief Disable CTS Interrupt
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
/**
* @brief Disable TX FIFO Threshold Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
}
/**
* @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
/**
* @brief Disable RX FIFO Threshold Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
}
/**
* @brief Check if the USART IDLE Interrupt source is enabled or disabled.
* @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
/**
* @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
* @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF
/**
* @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Parity Error Interrupt is enabled or disabled.
* @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Character Match Interrupt is enabled or disabled.
* @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled.
* @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART End Of Block Interrupt is enabled or disabled.
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Error Interrupt is enabled or disabled.
* @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART CTS Interrupt is enabled or disabled.
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
/**
* @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
}
/**
* @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_DMA_Management DMA_Management
* @{
*/
/**
* @brief Enable DMA Mode for reception
* @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
}
/**
* @brief Disable DMA Mode for reception
* @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
}
/**
* @brief Check if DMA Mode is enabled for reception
* @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Mode for transmission
* @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
}
/**
* @brief Disable DMA Mode for transmission
* @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
}
/**
* @brief Check if DMA Mode is enabled for transmission
* @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Disabling on Reception Error
* @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_DDRE);
}
/**
* @brief Disable DMA Disabling on Reception Error
* @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
}
/**
* @brief Indicate if DMA Disabling on Reception Error is disabled
* @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
}
/**
* @brief Get the data register address used for DMA transfer
* @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n
* @rmtoll TDR TDR LL_USART_DMA_GetRegAddr
* @param USARTx USART Instance
* @param Direction This parameter can be one of the following values:
* @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
* @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
{
uint32_t data_reg_addr;
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
/* return address of TDR register */
data_reg_addr = (uint32_t) &(USARTx->TDR);
}
else
{
/* return address of RDR register */
data_reg_addr = (uint32_t) &(USARTx->RDR);
}
return data_reg_addr;
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Read Receiver Data register (Receive Data value, 8 bits)
* @rmtoll RDR RDR LL_USART_ReceiveData8
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
{
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**
* @brief Read Receiver Data register (Receive Data value, 9 bits)
* @rmtoll RDR RDR LL_USART_ReceiveData9
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x1FF
*/
__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
{
return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
}
/**
* @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
* @rmtoll TDR TDR LL_USART_TransmitData8
* @param USARTx USART Instance
* @param Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
{
USARTx->TDR = Value;
}
/**
* @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
* @rmtoll TDR TDR LL_USART_TransmitData9
* @param USARTx USART Instance
* @param Value between Min_Data=0x00 and Max_Data=0x1FF
* @retval None
*/
__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
{
USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Execution Execution
* @{
*/
/**
* @brief Request an Automatic Baud Rate measurement on next received data frame
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
}
/**
* @brief Request Break sending
* @rmtoll RQR SBKRQ LL_USART_RequestBreakSending
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
}
/**
* @brief Put USART in mute mode and set the RWU flag
* @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
}
/**
* @brief Request a Receive Data and FIFO flush
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @note Allows to discard the received data without reading them, and avoid an overrun
* condition.
* @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
}
/**
* @brief Request a Transmit data and FIFO flush
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
}
/**
* @}
*/
/** @defgroup USART_LL_Autonomous_Mode Configuration functions related to Autonomous mode feature
* @{
*/
/**
* @brief Enable Selected Trigger
* @rmtoll AUTOCR TRIGEN LL_USART_Enable_SelectedTrigger
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_Enable_SelectedTrigger(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN);
}
/**
* @brief Disable Selected Trigger
* @rmtoll AUTOCR TRIGEN LL_USART_Disable_SelectedTrigger
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_Disable_SelectedTrigger(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN);
}
/**
* @brief Indicate if Selected Trigger is disabled or enabled
* @rmtoll AUTOCR TRIGEN LL_USART_IsEnabled_SelectedTrigger
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabled_SelectedTrigger(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Autonomous Send Idle Frame feature
* @rmtoll AUTOCR IDLEDIS LL_USART_Enable_AutonomousSendIdleFrame
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_Enable_AutonomousSendIdleFrame(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
}
/**
* @brief Disable Autonomous Send Idle Frame feature
* @rmtoll AUTOCR IDLEDIS LL_USART_Disable_AutonomousSendIdleFrame
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_Disable_AutonomousSendIdleFrame(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS);
}
/**
* @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled
* @rmtoll AUTOCR IDLEDIS LL_USART_IsEnabled_AutonomousSendIdleFrame
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabled_AutonomousSendIdleFrame(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL);
}
/**
* @brief Configure the Number of transferred data in bytes
* @rmtoll AUTOCR TDN LL_USART_SetNbTxData
* @param USARTx USART Instance
* @param Nbdata This parameter can be a value between 0 and 0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_USART_SetNbTxData(USART_TypeDef *USARTx, uint32_t Nbdata)
{
MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata);
}
/**
* @brief Retrieve the Number of transferred data in bytes
* @rmtoll AUTOCR TDN LL_USART_GetNbTxData
* @param USARTx USART Instance
* @retval Returned value can be a value between 0 and 0xFFFF
*/
__STATIC_INLINE uint32_t LL_USART_GetNbTxData(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TDN));
}
/**
* @brief Set the trigger polarity
* @rmtoll AUTOCR TRIGPOL LL_USART_SetTriggerPolarity
* @param USARTx USART Instance
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_USART_TRIG_POLARITY_RISING
* @arg @ref LL_USART_TRIG_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTriggerPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
{
MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity);
}
/**
* @brief Get the trigger polarity
* @rmtoll AUTOCR TRIGPOL LL_USART_GetTriggerPolarity
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_TRIG_POLARITY_RISING
* @arg @ref LL_USART_TRIG_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_USART_GetTriggerPolarity(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL));
}
/**
* @brief Set the selected trigger
* @rmtoll AUTOCR TRIGSEL LL_USART_SetSelectedTrigger
* @param USARTx USART Instance
* @param Trigger This parameter can be one of the following values:
* @arg @ref LL_USART_GPDMA1_CH0_TCF_TRG
* @arg @ref LL_USART_GPDMA1_CH1_TCF_TRG
* @arg @ref LL_USART_GPDMA1_CH2_TCF_TRG
* @arg @ref LL_USART_GPDMA1_CH3_TCF_TRG
* @arg @ref LL_USART_EXTI_LINE6_TRG
* @arg @ref LL_USART_EXTI_LINE9_TRG
* @arg @ref LL_USART_LPTIM1_OUT_TRG
* @arg @ref LL_USART_LPTIM2_OUT_TRG
* @arg @ref LL_USART_COMP1_OUT_TRG
* @arg @ref LL_USART_COMP2_OUT_TRG
* @arg @ref LL_USART_RTC_ALRA_TRG
* @arg @ref LL_USART_RTC_WUT_TRG
* @retval None
*/
__STATIC_INLINE void LL_USART_SetSelectedTrigger(USART_TypeDef *USARTx, uint32_t Trigger)
{
MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos));
}
/**
* @brief Get the selected trigger
* @rmtoll AUTOCR TRIGSEL LL_USART_GetSelectedTrigger
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_GPDMA1_CH0_TCF_TRG
* @arg @ref LL_USART_GPDMA1_CH1_TCF_TRG
* @arg @ref LL_USART_GPDMA1_CH2_TCF_TRG
* @arg @ref LL_USART_GPDMA1_CH3_TCF_TRG
* @arg @ref LL_USART_EXTI_LINE6_TRG
* @arg @ref LL_USART_EXTI_LINE9_TRG
* @arg @ref LL_USART_LPTIM1_OUT_TRG
* @arg @ref LL_USART_LPTIM2_OUT_TRG
* @arg @ref LL_USART_COMP1_OUT_TRG
* @arg @ref LL_USART_COMP2_OUT_TRG
* @arg @ref LL_USART_RTC_ALRA_TRG
* @arg @ref LL_USART_RTC_WUT_TRG
*/
__STATIC_INLINE uint32_t LL_USART_GetSelectedTrigger(USART_TypeDef *USARTx)
{
return (uint32_t)((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_USART_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h
|
C
|
apache-2.0
| 176,989
|
/**
******************************************************************************
* @file stm32u5xx_ll_usb.h
* @author MCD Application Team
* @brief Header file of USB Low Layer HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_USB_H
#define STM32U5xx_LL_USB_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal_def.h"
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup USB_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief USB Mode definition
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
typedef enum
{
USB_DEVICE_MODE = 0,
USB_HOST_MODE = 1,
USB_DRD_MODE = 2
} USB_OTG_ModeTypeDef;
/**
* @brief URB States definition
*/
typedef enum
{
URB_IDLE = 0,
URB_DONE,
URB_NOTREADY,
URB_NYET,
URB_ERROR,
URB_STALL
} USB_OTG_URBStateTypeDef;
/**
* @brief Host channel States definition
*/
typedef enum
{
HC_IDLE = 0,
HC_XFRC,
HC_HALTED,
HC_NAK,
HC_NYET,
HC_STALL,
HC_XACTERR,
HC_BBLERR,
HC_DATATGLERR
} USB_OTG_HCStateTypeDef;
/**
* @brief USB Instance Initialization Structure definition
*/
typedef struct
{
uint32_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t Host_channels; /*!< Host Channels number.
This parameter Depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref PCD_Speed/HCD_Speed
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
} USB_OTG_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_iso_incomplete; /*!< Endpoint isoc condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_LL_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t even_odd_frame; /*!< IFrame parity
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t tx_fifo_num; /*!< Transmission FIFO number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_size; /*!< requested transfer size */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
} USB_OTG_EPTypeDef;
typedef struct
{
uint8_t dev_addr; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t ep_num; /*!< Endpoint number.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t ep_is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t speed; /*!< USB Host Channel speed.
This parameter can be any value of @ref HCD_Device_Speed:
(HCD_DEVICE_SPEED_xxx) */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
uint8_t ep_type; /*!< Endpoint Type.
This parameter can be any value of @ref USB_LL_EP_Type */
uint16_t max_packet; /*!< Endpoint Max packet size.
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t data_pid; /*!< Initial data PID.
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
uint32_t XferSize; /*!< OTG Channel transfer size. */
uint32_t xfer_len; /*!< Current transfer length. */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
uint8_t toggle_in; /*!< IN transfer current toggle flag.
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t toggle_out; /*!< OUT transfer current toggle flag
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
uint32_t ErrCnt; /*!< Host channel error count. */
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @defgroup USB_OTG_CORE VERSION ID
* @{
*/
#define USB_OTG_CORE_ID_300A 0x4F54300AU
#define USB_OTG_CORE_ID_310A 0x4F54310AU
/**
* @}
*/
/** @defgroup USB_Core_Mode_ USB Core Mode
* @{
*/
#define USB_OTG_MODE_DEVICE 0U
#define USB_OTG_MODE_HOST 1U
#define USB_OTG_MODE_DRD 2U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_HS_SPEED 0U
#define USBD_HSINFS_SPEED 1U
#define USBH_HS_SPEED 0U
#define USBD_FS_SPEED 2U
#define USBH_FSLS_SPEED 1U
/**
* @}
*/
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
* @{
*/
#define USB_OTG_SPEED_HIGH 0U
#define USB_OTG_SPEED_HIGH_IN_FULL 1U
#define USB_OTG_SPEED_FULL 3U
/**
* @}
*/
/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
* @{
*/
#define USB_OTG_EMBEDDED_PHY 2U
#define USB_OTG_HS_EMBEDDED_PHY 3U
/**
* @}
*/
/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
* @{
*/
#ifndef USBD_HS_TRDT_VALUE
#define USBD_HS_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
#ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5U
#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
*/
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
* @{
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/**
* @}
*/
/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
* @{
*/
#define DCFG_FRAME_INTERVAL_80 0U
#define DCFG_FRAME_INTERVAL_85 1U
#define DCFG_FRAME_INTERVAL_90 2U
#define DCFG_FRAME_INTERVAL_95 3U
/**
* @}
*/
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define EP_MPS_64 0U
#define EP_MPS_32 1U
#define EP_MPS_16 2U
#define EP_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
* @{
*/
#define EP_SPEED_LOW 0U
#define EP_SPEED_FULL 1U
#define EP_SPEED_HIGH 2U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
* @{
*/
#define STS_GOUT_NAK 1U
#define STS_DATA_UPDT 2U
#define STS_XFER_COMP 3U
#define STS_SETUP_COMP 4U
#define STS_SETUP_UPDT 6U
/**
* @}
*/
/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
* @{
*/
#define HCFG_30_60_MHZ 0U
#define HCFG_48_MHZ 1U
#define HCFG_6_MHZ 2U
/**
* @}
*/
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0U
#define HPRT0_PRTSPD_FULL_SPEED 1U
#define HPRT0_PRTSPD_LOW_SPEED 2U
/**
* @}
*/
#define HCCHAR_CTRL 0U
#define HCCHAR_ISOC 1U
#define HCCHAR_BULK 2U
#define HCCHAR_INTR 3U
#define HC_PID_DATA0 0U
#define HC_PID_DATA2 1U
#define HC_PID_DATA1 2U
#define HC_PID_SETUP 3U
#define GRXSTS_PKTSTS_IN 2U
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
#define TEST_J 1U
#define TEST_K 2U
#define TEST_SE0_NAK 3U
#define TEST_PACKET 4U
#define TEST_FORCE_EN 5U
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+ USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+ USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+ USB_OTG_HOST_CHANNEL_BASE\
+ ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#define EP_ADDR_MSK 0xFU
#ifndef USE_USB_DOUBLE_BUFFER
#define USE_USB_DOUBLE_BUFFER 1U
#endif /* USE_USB_DOUBLE_BUFFER */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len, uint8_t dma);
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address, uint8_t speed,
uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
USB_OTG_HCTypeDef *hc, uint8_t dma);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32U5xx_LL_USB_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h
|
C
|
apache-2.0
| 20,975
|
/**
******************************************************************************
* @file stm32u5xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32U5xx_LL_UTILS_H
#define __STM32U5xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @brief Package data register base address
*/
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
This parameter can be a value of @ref RCC_LL_EC_PLL1MBOOST_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_ConfigDomain_SYS(). */
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 8 and Max_Data = 86
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_ConfigDomain_SYS(). */
uint32_t PLLR; /*!< Division for the main system clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 128
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_ConfigDomain_SYS(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB3Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
* @{
*/
#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA132 0x00000003U /*!< UFBGA132 package type */
#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */
#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007U /*!< UFBGA169 package type */
#define LL_UTILS_PACKAGETYPE_LQFP64_SMPS 0x00000008U /*!< LQFP64 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_WLSCP90_SMPS 0x00000009U /*!< WLSCP90 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_UFBGA132_SMPS 0x0000000BU /*!< UFBGA132 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_LQFP48_SMPS 0x0000000DU /*!< LQFP48 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000FU /*!< UFBGA169 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_WLCSP144 0x00000010U /*!< WLCSP144 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000011U /*!< UFBGA144 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP144_SMPS 0x00000018U /*!< WLCSP144 with internal SMPS package t */
#define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS 0x00000019U /*!< UFBGA144 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_WLCSP208_SMPS 0x0000001BU /*!< WLCSP208 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_TFBGA216_SMPS 0x0000001CU /*!< TFBGA216 with internal SMPS package type */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
}
/**
* @brief Get Package type
* @retval Returned value can be one of the following values:
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA132
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP64_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_WLSCP90_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA132_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP208_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216_SMPS
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup LL_UTILS_Aliased_Functions LL UTILS Aliased Functions maintained for legacy purpose
* @{
*/
#define LL_PLL1_ConfigSystemClock_MSI LL_PLL_ConfigSystemClock_MSI
#define LL_PLL1_ConfigSystemClock_HSI LL_PLL_ConfigSystemClock_HSI
#define LL_PLL1_ConfigSystemClock_HSE LL_PLL_ConfigSystemClock_HSE
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32U5xx_LL_UTILS_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h
|
C
|
apache-2.0
| 13,244
|
/**
******************************************************************************
* @file stm32u5xx_ll_wwdg.h
* @author MCD Application Team
* @brief Header file of WWDG LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32U5xx_LL_WWDG_H
#define STM32U5xx_LL_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx.h"
/** @addtogroup STM32U5xx_LL_Driver
* @{
*/
#if defined (WWDG)
/** @defgroup WWDG_LL WWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
* @{
*/
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
/**
* @}
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
* @{
*/
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
#define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */
#define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */
#define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */
#define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/128 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
* @{
*/
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
* @{
*/
/**
* @brief Write a value in WWDG register
* @param __INSTANCE__ WWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in WWDG register
* @param __INSTANCE__ WWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
* @{
*/
/** @defgroup WWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
* then it cannot be disabled again except by a reset.
* This bit is set by software and only cleared by hardware after a reset.
* When WDGA = 1, the watchdog can generate a reset.
* @rmtoll CR WDGA LL_WWDG_Enable
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
{
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
}
/**
* @brief Checks if Window Watchdog is enabled
* @rmtoll CR WDGA LL_WWDG_IsEnabled
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
/**
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
* @rmtoll CR T LL_WWDG_SetCounter
* @param WWDGx WWDG Instance
* @param Counter 0..0x7F (7 bit counter value)
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
{
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
}
/**
* @brief Return current Watchdog Counter Value (7 bits counter value)
* @rmtoll CR T LL_WWDG_GetCounter
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Counter value
*/
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
/**
* @brief Set the time base of the prescaler (WDGTB).
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
* is decremented every (4096 x 2expWDGTB) PCLK cycles
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
* @param WWDGx WWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_WWDG_PRESCALER_1
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
* @arg @ref LL_WWDG_PRESCALER_16
* @arg @ref LL_WWDG_PRESCALER_32
* @arg @ref LL_WWDG_PRESCALER_64
* @arg @ref LL_WWDG_PRESCALER_128
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
}
/**
* @brief Return current Watchdog Prescaler Value
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
* @param WWDGx WWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_WWDG_PRESCALER_1
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
* @arg @ref LL_WWDG_PRESCALER_16
* @arg @ref LL_WWDG_PRESCALER_32
* @arg @ref LL_WWDG_PRESCALER_64
* @arg @ref LL_WWDG_PRESCALER_128
*/
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
/**
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
* @note This window value defines when write in the WWDG_CR register
* to program Watchdog counter is allowed.
* Watchdog counter value update must occur only when the counter value
* is lower than the Watchdog window register value.
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
* (in the control register) is refreshed before the downcounter has reached
* the watchdog window register value.
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
* @rmtoll CFR W LL_WWDG_SetWindow
* @param WWDGx WWDG Instance
* @param Window 0x00..0x7F (7 bit Window value)
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
{
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
}
/**
* @brief Return current Watchdog Window Value (7 bits value)
* @rmtoll CFR W LL_WWDG_GetWindow
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Window value
*/
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
/**
* @}
*/
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
* @note This bit is set by hardware when the counter has reached the value 0x40.
* It must be cleared by software by writing 0.
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
/**
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
}
/**
* @}
*/
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable the Early Wakeup Interrupt.
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
* This interrupt is only cleared by hardware after a reset
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
{
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
}
/**
* @brief Check if Early Wakeup Interrupt is enabled
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* WWDG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32U5xx_LL_WWDG_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_wwdg.h
|
C
|
apache-2.0
| 11,071
|
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<h1 id="release-notes-for-stm32cubeu5-hal-and-ll-drivers">Release Notes for <mark>STM32CubeU5 HAL and LL drivers</mark></h1>
<p>Copyright © 2021 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
<h1 id="purpose">Purpose</h1>
<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
<p>The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.</p>
<p>The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one-shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:</p>
<ul>
<li>New set of inline functions for direct and atomic register access</li>
<li>One-shot operations that can be used by the HAL drivers or from application level</li>
<li>Full independence from HAL and standalone usage (without HAL drivers)</li>
<li>Full features coverage of all the supported peripherals</li>
</ul>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" checked aria-hidden="true"><strong>V1.1.0 / 16-February-2022</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li><strong>HAL and LL drivers</strong> Maintenance Release for STM32U575xx / STM32U585xx devices and new support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices (Please Refer to the <a href="Drivers/STM32U5xx_HAL_Driver/Release_Notes.html">release notes</a> for details)</li>
<li>Add <strong>New LTDC, GFXMMU, DSI, GPU2D HAL drivers</strong> highlighting the graphics aspect of STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices</li>
<li>Add <strong>New HAL XSPI driver</strong> which supports OCTOSPI and Hexa-Deca SPI interface for both STM32U575/STM32U585 and STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices</li>
<li><strong>All the HAL/LL drivers</strong> are updated to support both STM32U575/STM32U585 and STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices</li>
<li>General updates to fix known defects and implementation enhancements</li>
<li>The HAL and LL drivers provided within this package are <strong>MISRA-C, MCU ASTYLE and CodeSonar compliant</strong>, and have been reviewed with a static analysis tool to eliminate possible run-time errors</li>
</ul>
<h3 id="hal-drivers-updates">- <strong>HAL Drivers</strong> updates</h3>
<ul>
<li>All the <strong>HAL</strong> drivers are updated to support both STM32U575/STM32U585 and STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices</li>
<li><strong>HAL ADC</strong> driver
<ul>
<li>Add the following functions:
<ul>
<li>HAL_ADCEx_MultiModeStart_DMA_Data32()</li>
<li>HAL_ADCEx_MultiModeGetValue_Data32()</li>
</ul></li>
<li>Update the DMA data length management implementation according to source/destination width</li>
<li>Enhance HAL_ADCEx_Calibration_GetValue() function implementation for proper ADC4 instance support<br />
</li>
<li>Enhance HAL_ADC_DeInit() and HAL_ADC_ConfigChannel() function implementation</li>
</ul></li>
<li><strong>HAL DCACHE</strong> driver
<ul>
<li>Add HAL_DCACHE_IsEnabled API to check whether the DCACHE is enabled or not</li>
<li>Enhance HAL_DCACHE_UnRegisterCallback() API</li>
<li>Enhance the timeout management</li>
<li>Enhance error code management by :
<ul>
<li>Resetting DCACHE handle error code any time a new operation is launched</li>
<li>Adding HAL_DCACHE_ERROR_INVALID_OPERATION error code: used in HAL_DCACHE_SetReadBurstType() API when DCACHE is enabled</li>
<li>Adding HAL_DCACHE_ERROR_EVICTION_CLEAN error code: used in HAL_DCACHE_IRQHandler() API when DCACHE error interrupt flag is set</li>
</ul></li>
<li>Change the returned HAL status when there is an ongoing operation from HAL_ERROR to HAL_BUSY</li>
<li>Change DCACHE handle state to HAL_DCACHE_STATE_READY any time a new operation is launched</li>
</ul></li>
<li><strong>HAL DMA</strong> driver
<ul>
<li>Enhance LinkAllocatedPort implementation</li>
</ul></li>
<li><strong>HAL GPIO</strong> driver
<ul>
<li>Reorder EXTI configuration in HAL_GPIO_Init() API</li>
</ul></li>
<li><strong>HAL GTZC</strong> driver
<ul>
<li>Rename GTZC_PERIPH_DCMI define to GTZC_PERIPH_DCMI_PSSI</li>
</ul></li>
<li><strong>HAL</strong> driver
<ul>
<li>Add the following functions:
<ul>
<li>HAL_SYSCFG_SetOTGPHYReferenceClockSelection()
<ul>
<li>HAL_SYSCFG_SetOTGPHYPowerDownConfig()</li>
<li>HAL_SYSCFG_EnableOTGPHY()</li>
</ul></li>
<li>HAL_SYSCFG_EnableVddCompensationCell()
<ul>
<li>HAL_SYSCFG_EnableVddIO2CompensationCell()</li>
<li>HAL_SYSCFG_EnableVddHSPICompensationCell()</li>
<li>HAL_SYSCFG_DisableVddCompensationCell()</li>
<li>HAL_SYSCFG_DisableVddIO2CompensationCell()</li>
<li>HAL_SYSCFG_DisableVddHSPICompensationCell()</li>
</ul></li>
</ul></li>
</ul></li>
<li><strong>HAL HCD</strong> driver
<ul>
<li>Fix handling of ODDFRM bit in OTG_HCCHARx for Isochronous IN transactions</li>
</ul></li>
<li><strong>HAL ICACHE</strong> driver
<ul>
<li>Add HAL_ICACHE_IsEnabled() API to check whether the ICACHE is enabled or not<br />
</li>
</ul></li>
<li><strong>HAL LPTIM</strong> driver
<ul>
<li>Add HAL_LPTIM_IC_GetOffset() function</li>
<li>Rename HAL_LPTIM_ReadCompare to HAL_LPTIM_ReadCapturedValue</li>
<li>Add parameters checks in HAL_LPTIM_xxx_Start_DMA functions</li>
</ul></li>
<li><strong>HAL MMC</strong> driver
<ul>
<li>Add the following functions:
<ul>
<li>HAL_MMC_SleepDevice()</li>
<li>HAL_MMC_AwakeDevice()</li>
</ul></li>
</ul></li>
<li><strong>HAL PCD</strong> driver
<ul>
<li>Add the following functions:
<ul>
<li>HAL_PCD_EP_Abort()</li>
<li>HAL_PCD_SetTestMode()</li>
</ul></li>
<li>Correct received transfer length with USB DMA activated</li>
<li>Add handling of USB OUT Endpoint disable interrupt</li>
<li>Fix device IN endpoint isoc incomplete transfer interrupt handling</li>
<li>Fix USB device Isoc OUT Endpoint incomplete transfer interrupt handling</li>
<li>Set DCD timeout to minimum value of 300ms before starting BCD primary detection process</li>
</ul></li>
<li><strong>HAL PWR</strong> driver
<ul>
<li>Add the following functions:
<ul>
<li>HAL_PWREx_EnableUSBHSTranceiverSupply()</li>
<li>HAL_PWREx_DisableUSBHSTranceiverSupply()</li>
<li>Rename PWR_SRAMx_PAGEx_MODE_RETENTION to PWR_SRAMx_PAGEx_MODE</li>
</ul></li>
</ul></li>
<li><strong>HAL RCC</strong> driver
<ul>
<li>Enhance HAL_RCC_ClockConfig() function implementation</li>
<li>Update HAL_RCC_OscConfig() function implementation on PWR clocking control</li>
<li>Update HAL_RCC_OscConfig() function implementation to be tolerant to an identical PLL1 parameters re-configuration</li>
<li>Enhance of PLL1 outputs clearing time in HAL_RCC_OscConfig()</li>
<li>Remove RCC_PLL_SOURCE_NONE from correct parameters list on PLL1 configuration</li>
<li>Rename RCC_PERIPHCLK_CLK48 to RCC_PERIPHCLK_ICLK defines</li>
<li>Rename RCC_CLK48CLKSOURCE_XXX to RCC_ICLK_CLKSOURCE_XXX defines</li>
<li>Rename __HAL_RCC_ADC1_XXX_YYY to __HAL_RCC_ADC12_XXX_YYY macros</li>
<li>Rename __HAL_RCC_USB_OTG_FS_CLK_XXX to __HAL_RCC_USB_CLK_XXX macros</li>
<li>Rename Clk48ClockSelection to IclkClockSelection in RCC_PeriphCLKInitTypeDef</li>
</ul></li>
<li><strong>HAL SPI</strong> driver
<ul>
<li>Fix compilation warning with GNU compiler</li>
</ul></li>
<li><strong>HAL TIM</strong> driver
<ul>
<li>Add IS_TIM_PERIOD macro in HAL_TIM_xxx_Init functions<br />
</li>
</ul></li>
<li><strong>HAL UART</strong> driver
<ul>
<li>Rework HAL_UART_DMAPause() function in order to use DMA instead of UART to pause data transfer</li>
<li>Rework HAL_UART_DMAResume() function in order to use DMA instead of UART to resume data transfer</li>
</ul></li>
<li><strong>HAL USART</strong> driver
<ul>
<li>Rework HAL_USART_DMAPause() function in order to use DMA instead of USART to pause data transfer</li>
<li>Rework HAL_USART_DMAResume() function in order to use DMA instead of USART to resume data transfer</li>
</ul></li>
</ul>
<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
<ul>
<li>All the <strong>LL</strong> drivers are updated to support both STM32U575/STM32U585 and STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices</li>
<li><strong>LL ADC</strong> driver
<ul>
<li>Add the following functions:
<ul>
<li>LL_ADC_SetVrefProtection()</li>
<li>LL_ADC_GetVrefProtection()</li>
</ul></li>
</ul></li>
<li><strong>LL I2C</strong> driver
<ul>
<li>Add I2C instances 5 and 6 configuration within LL driver</li>
</ul></li>
<li><strong>LL LPTIM</strong> driver
<ul>
<li>Add LL_LPTIM_IC_GET_OFFSET macro</li>
<li>Rename the following static inline functions:
<ul>
<li>LL_LPTIM_SetCompareCH1 to LL_LPTIM_OC_SetCompareCH1</li>
<li>LL_LPTIM_SetCompareCH2 to LL_LPTIM_OC_SetCompareCH2</li>
<li>LL_LPTIM_GetCompareCH1 to LL_LPTIM_OC_GetCompareCH1</li>
<li>LL_LPTIM_GetCompareCH2 to LL_LPTIM_OC_GetCompareCH2</li>
</ul></li>
</ul></li>
<li><strong>LL OPAMP</strong> driver
<ul>
<li>Add __LL_OPAMP_COMMON_INSTANCE macro</li>
</ul></li>
<li><strong>LL RCC</strong> driver
<ul>
<li>Add the following functions:
<ul>
<li>LL_RCC_SetUSBPHYClockSource()</li>
<li>LL_RCC_PLL3_EnableDomain_HSPI_LTDC()</li>
<li>LL_RCC_PLL3_DisableDomain_HSPI_LTDC()</li>
<li>LL_RCC_PLL3_ConfigDomain_HSPI_LTDC()</li>
<li>LL_RCC_PLL1_IsEnabledDomain_SAI()</li>
<li>LL_RCC_PLL1_IsEnabledDomain_48M()</li>
<li>LL_RCC_PLL1_IsEnabledDomain_SYS()</li>
<li>LL_RCC_PLL2_IsEnabledDomain_SAI()</li>
<li>LL_RCC_PLL2_IsEnabledDomain_48M()</li>
<li>LL_RCC_PLL2_IsEnabledDomain_ADC()</li>
<li>LL_RCC_PLL3_IsEnabledDomain_SAI()</li>
<li>LL_RCC_PLL3_IsEnabledDomain_48M()</li>
<li>LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC()</li>
</ul></li>
<li>Enhance the following functions implementation:
<ul>
<li>LL_RCC_GetUSARTClockFreq(): Fix LPUART1 returned frequency when PCLK3 is set as clock source</li>
<li>LL_RCC_GetPPPClockFreq: Add check of PLL output enable bit status</li>
</ul></li>
<li>Rename the macro __LL_RCC_CALC_PLL3CLK_HSPI_FREQ to __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ</li>
<li>Rename the static API RCC_PLL3_GetFreqDomain_HSPI to RCC_PLL3_GetFreqDomain_HSPI_LTDC</li>
<li>Rename LL_RCC_USART6_CLKSOURCE_PCLK2 to LL_RCC_USART6_CLKSOURCE_PCLK1</li>
</ul></li>
<li><strong>LL RTC</strong> driver
<ul>
<li>Add LL_RTC_IsActiveFlag_ITAMP7() function</li>
</ul></li>
<li><strong>LL USART</strong> driver
<ul>
<li>Add USART instance 6 configuration within LL driver</li>
</ul></li>
<li><strong>LL USB</strong> driver
<ul>
<li>Add USB_EPStopXfer() function</li>
</ul></li>
</ul>
<p>Backward compatibility ensured by legacy defines</p>
<h2 id="known-limitations">Known Limitations</h2>
<ul>
<li>N/A</li>
</ul>
<h2 id="backward-compatibility">Backward compatibility</h2>
<ul>
<li>N/A</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" checked aria-hidden="true"><strong>V1.0.2 / 14-October-2021</strong></label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>Patch release V1.0.2 of <strong>HAL and LL drivers</strong> for <strong>STM32U575xx / STM32U585xx</strong> devices</li>
</ul>
<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL DAC</strong> driver
<ul>
<li>Rename of the LPTIM1/3 trigger of the LL DAC to be in line with Reference Manual:
<ul>
<li>Rename LL_DAC_TRIG_EXT_LPTIM1_OUT to LL_DAC_TRIG_EXT_LPTIM1_CH1</li>
<li>Rename LL_DAC_TRIG_EXT_LPTIM3_OUT to LL_DAC_TRIG_EXT_LPTIM3_CH1</li>
</ul></li>
</ul></li>
<li>Backward compatibility ensured by legacy defines</li>
</ul>
<h2 id="known-limitations-1">Known Limitations</h2>
<ul>
<li>N/A</li>
</ul>
<h2 id="backward-compatibility-1">Backward compatibility</h2>
<ul>
<li>N/A</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.0.1 / 01-October-2021</strong></label>
<div>
<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Patch release V1.0.1 of <strong>HAL and LL drivers</strong> for <strong>STM32U575xx / STM32U585xx</strong> devices</li>
</ul>
<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL ADC</strong> driver
<ul>
<li>Update the DMA data length management implementation according source/destination width</li>
<li>Finetune HAL_ADCEx_Calibration_GetValue API to return correct calibration value for ADC4</li>
</ul></li>
<li><strong>HAL DAC</strong> driver
<ul>
<li>Rename of the LPTIM1/3 trigger of the DAC to be in line with Reference Manual:
<ul>
<li>Rename DAC_TRIGGER_STOP_LPTIM1_OUT to DAC_TRIGGER_STOP_LPTIM1_CH1</li>
<li>Rename DAC_TRIGGER_STOP_LPTIM3_OUT to DAC_TRIGGER_STOP_LPTIM3_CH1</li>
<li>Rename DAC_TRIGGER_LPTIM1_OUT to DAC_TRIGGER_LPTIM1_CH1</li>
<li>Rename DAC_TRIGGER_LPTIM3_OUT to DAC_TRIGGER_LPTIM3_CH1</li>
</ul></li>
</ul></li>
<li><strong>HAL DMA</strong> driver
<ul>
<li>Fix DMA register callback error returning in case of invalid callback.</li>
<li>Enhance HAL_DMA_GetLockChannelAttributes API implementation to detect wrong parameters values</li>
<li>Enhance IS_DMA_ATTRIBUTES macro implementation to detect uncovered cases.</li>
<li>Optimize DMA_List_CheckNodesBaseAddresses API implementation by reducing parameters number</li>
<li>Optimize DMA_List_CheckNodesTypes API implementation by reducing parameters number</li>
</ul></li>
<li><strong>HAL GTZC</strong> driver
<ul>
<li>Fix issue with the APIs HAL_GTZC_MPCBB_ConfigMem : The CFGLOCK register should be updated after the update of SECCFGR and PRIVCFGR</li>
</ul></li>
<li><strong>HAL I2C </strong> driver
<ul>
<li>Add handle errors support in polling mode</li>
</ul></li>
<li><strong>HAL RCC </strong> driver
<ul>
<li>Fix setting Flash latency from MSIRange in Oscillator Configuration</li>
</ul></li>
</ul>
<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL I2C</strong> driver
<ul>
<li>Add LL_I2C_EnableFastModePlus, LL_I2C_DisableFastModePlus and LL_I2C_IsEnabledFastModePlus APIs</li>
</ul></li>
</ul>
<h2 id="known-limitations-2">Known Limitations</h2>
<ul>
<li>N/A</li>
</ul>
<h2 id="backward-compatibility-2">Backward compatibility</h2>
<ul>
<li>N/A</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 28-June-2021</strong></label>
<div>
<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>First official release of <strong>HAL and LL drivers</strong> for <strong>STM32U575xx / STM32U585xx</strong> devices</li>
</ul>
<h2 id="known-limitations-3">Known Limitations</h2>
<ul>
<li>N/A</li>
</ul>
</div>
</div>
</div>
</div>
<footer class="sticky">
<p>For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span></p>
This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.
</footer>
</body>
</html>
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Release_Notes.html
|
HTML
|
apache-2.0
| 16,736
|
/**
******************************************************************************
* @file stm32u5xx_hal.c
* @author MCD Application Team
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
The HAL contains two APIs' categories:
(+) Common HAL APIs
(+) Services HAL APIs
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup HAL HAL
* @brief HAL module driver
* @{
*/
#ifdef HAL_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup HAL_Private_Defines HAL Private Defines
* @{
*/
/**
* @brief STM32U5xx HAL Driver version number 1.1.0
*/
#define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32U5xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\
|(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\
|(__STM32U5xx_HAL_VERSION_SUB2 << 8U )\
|(__STM32U5xx_HAL_VERSION_RC))
#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Exported variables --------------------------------------------------------*/
/** @defgroup HAL_Exported_Variables HAL Exported Variables
* @{
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initializes the Flash interface the NVIC allocation and initial clock
configuration. It initializes the systick also when timeout is needed
and the backup domain when enabled.
(+) De-Initializes common part of the HAL.
(+) Configure The time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
(++) Time base configuration function (HAL_InitTick ()) is called automatically
at the beginning of the program after reset by HAL_Init() or at any time
when clock is configured, by HAL_RCC_ClockConfig().
(++) Source of time base is configured to generate interrupts at regular
time intervals. Care must be taken if HAL_Delay() is called from a
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
(++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
/**
* @brief Configure the Flash prefetch, the time base source, NVIC and any required global low
* level hardware by calling the HAL_MspInit() callback function to be optionally defined
* in user file stm32u5xx_hal_msp.c.
*
* @note HAL_Init() function is called at the beginning of program after reset and before
* the clock configuration.
*
* @note In the default implementation the System Timer (Systick) is used as source of time base.
* The Systick configuration is based on MSI clock, as MSI is the clock
* used after a system Reset and the NVIC configuration is set to Priority group 4.
* Once done, time base tick starts incrementing: the tick variable counter is incremented
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos];
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
return HAL_ERROR;
}
/* Init the low level hardware */
HAL_MspInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief This function de-Initializes common part of the HAL and stops the systick.
* This function is optional.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
__HAL_RCC_APB1_FORCE_RESET();
__HAL_RCC_APB1_RELEASE_RESET();
__HAL_RCC_APB2_FORCE_RESET();
__HAL_RCC_APB2_RELEASE_RESET();
__HAL_RCC_AHB1_FORCE_RESET();
__HAL_RCC_AHB1_RELEASE_RESET();
__HAL_RCC_AHB2_FORCE_RESET();
__HAL_RCC_AHB2_RELEASE_RESET();
__HAL_RCC_AHB3_FORCE_RESET();
__HAL_RCC_AHB3_RELEASE_RESET();
/* De-Init the low level hardware */
HAL_MspDeInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the MSP.
* @retval None
*/
__weak void HAL_MspDeInit(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function configures the source of the time base.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
if ((uint32_t)uwTickFreq == 0UL)
{
return HAL_ERROR;
}
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup HAL_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Provide a tick value in millisecond
(+) Provide a blocking delay in millisecond
(+) Suspend the time base source interrupt
(+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
(+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP mode
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in Systick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += (uint32_t)uwTickFreq;
}
/**
* @brief Provides a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
}
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
return uwTickPrio;
}
/**
* @brief Set new tick Freq.
* @retval Status
*/
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status == HAL_OK)
{
uwTickFreq = Freq;
}
}
return status;
}
/**
* @brief Return tick frequency.
* @retval tick period in Hz
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
return uwTickFreq;
}
/**
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait += (uint32_t)(uwTickFreq);
}
while ((HAL_GetTick() - tickstart) < wait)
{
}
}
/**
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Returns the HAL revision
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
return __STM32U5xx_HAL_VERSION;
}
/**
* @brief Returns the device revision identifier.
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
{
return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);
}
/**
* @brief Returns the device identifier.
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
{
return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
* @brief HAL Debug functions
*
@verbatim
===============================================================================
##### HAL Debug functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes.
* @retval None
*/
void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes.
* @retval None
*/
void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode.
* @retval None
*/
void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode.
* @retval None
*/
void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
* @brief HAL SYSCFG configuration functions
*
@verbatim
===============================================================================
##### HAL SYSCFG configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the Voltage reference buffer
(+) Enable/Disable the Voltage reference buffer
(+) Enable/Disable the I/O analog switch voltage booster
@endverbatim
* @{
*/
/**
* @brief Configure the internal voltage reference buffer voltage scale.
* @param VoltageScaling: specifies the output voltage to achieve
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 1.5 V.
* This requires VDDA equal to or higher than 1.8 V.
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 1.8 V.
* This requires VDDA equal to or higher than 2.1 V.
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT1 around 2.048 V.
* This requires VDDA equal to or higher than 2.4 V.
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT1 around 2.5 V.
* This requires VDDA equal to or higher than 2.8 V.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
}
/**
* @brief Configure the internal voltage reference buffer high impedance mode.
* @param Mode: specifies the high impedance mode
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
}
/**
* @brief Tune the Internal Voltage Reference buffer (VREFBUF).
* @retval None
*/
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
}
/**
* @brief Enable the Internal Voltage Reference buffer (VREFBUF).
* @retval HAL_OK/HAL_TIMEOUT
*/
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
{
uint32_t tickstart;
SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait for VRR bit */
while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
{
if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Disable the Internal Voltage Reference buffer (VREFBUF).
*
* @retval None
*/
void HAL_SYSCFG_DisableVREFBUF(void)
{
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
/**
* @brief Enable the I/O analog switch voltage booster
*
* @retval None
*/
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Disable the I/O analog switch voltage booster
*
* @retval None
*/
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Enable the Compensation Cell of GPIO supplied by VDD
* @rmtoll CCCSR EN1 HAL_SYSCFG_EnableVddCompensationCell
* @note The vdd compensation cell can be used only when the device supply
* voltage ranges from 1.71 to 3.6 V
* @retval None
*/
void HAL_SYSCFG_EnableVddCompensationCell(void)
{
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
}
/**
* @brief Enable the Compensation Cell of GPIO supplied by VDDIO2
* @rmtoll CCCSR EN2 HAL_SYSCFG_EnableVddIO2CompensationCell
* @note The Vdd I/O compensation cell can be used only when the device supply
* voltage ranges from 1.08 to 3.6 V
* @retval None
*/
void HAL_SYSCFG_EnableVddIO2CompensationCell(void)
{
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
}
#if defined(SYSCFG_CCCSR_EN3)
/**
* @brief Enable the Compensation Cell of HSPI IO supplied by VDD
* @rmtoll CCCSR EN3 HAL_SYSCFG_EnableVddHSPICompensationCell
* @retval None
*/
void HAL_SYSCFG_EnableVddHSPICompensationCell(void)
{
SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
}
#endif /* SYSCFG_CCCSR_EN3 */
/**
* @brief Disable the Compensation Cell of GPIO supplied by VDD
* @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell
* @note The Vdd compensation cell can be used only when the device supply
* voltage ranges from 1.71 to 3.6 V
* @retval None
*/
void HAL_SYSCFG_DisableVddCompensationCell(void)
{
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
}
/**
* @brief Disable the Compensation Cell of GPIO supplied by VDDIO2
* @rmtoll CCCSR EN2 HAL_SYSCFG_DisableVddIO2CompensationCell
* @note The Vdd I/O compensation cell can be used only when the device supply
* voltage ranges from 1.08 to 3.6 V
* @retval None
*/
void HAL_SYSCFG_DisableVddIO2CompensationCell(void)
{
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
}
#if defined(SYSCFG_CCCSR_EN3)
/**
* @brief Disable the Compensation Cell of HSPI IO supplied by VDD
* @rmtoll CCCSR EN3 HAL_SYSCFG_DisableVddHSPICompensationCell
* @retval None
*/
void HAL_SYSCFG_DisableVddHSPICompensationCell(void)
{
CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
}
#endif /* SYSCFG_CCCSR_EN3 */
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions
* @brief SYSCFG lock management functions.
*
@verbatim
===============================================================================
##### SYSCFG lock functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Lock the SYSCFG item(s).
* @note Setting lock(s) depends on privilege mode in secure/non-secure code
* Lock(s) cleared only at system reset
* @param Item Item(s) to set lock on.
* This parameter can be a combination of @ref SYSCFG_Lock_items
* @retval None
*/
void HAL_SYSCFG_Lock(uint32_t Item)
{
/* Check the parameters */
assert_param(IS_SYSCFG_LOCK_ITEMS(Item));
/* Privilege secure/non-secure locks */
SYSCFG->CNSLCKR = (0xFFFFU & Item); /* non-secure lock item in 16 lowest bits */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Privilege secure only locks */
SYSCFG->CSLCKR = ((0xFFFF0000U & Item) >> 16U); /* Secure-only lock item in 16 highest bits */
#endif /* __ARM_FEATURE_CMSE */
}
/**
* @brief Get the lock state of SYSCFG item.
* @note Getting lock(s) depends on privilege mode in secure/non-secure code
* @param pItem pointer to return locked items
* the return value can be a combination of @ref SYSCFG_Lock_items
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem)
{
uint32_t tmp_lock;
/* Check null pointer */
if (pItem == NULL)
{
return HAL_ERROR;
}
/* Get the non-secure lock state */
tmp_lock = SYSCFG->CNSLCKR;
/* Get the secure lock state in secure code */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
tmp_lock |= (SYSCFG->CSLCKR << 16U);
#endif /* __ARM_FEATURE_CMSE */
/* Return overall lock status */
*pItem = tmp_lock;
return HAL_OK;
}
/**
* @}
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions
* @brief SYSCFG attributes management functions.
*
@verbatim
===============================================================================
##### SYSCFG attributes functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Configure the SYSCFG item attribute(s).
* @note Available attributes are to secure SYSCFG items, so this function is
* only available in secure
* @param Item Item(s) to set attributes on.
* This parameter can be a one or a combination of @ref SYSCFG_Attributes_items
* @param Attributes specifies the secure/non-secure attributes.
* @retval None
*/
void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes)
{
uint32_t tmp;
/* Check the parameters */
assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item));
assert_param(IS_SYSCFG_ATTRIBUTES(Attributes));
tmp = SYSCFG_S->SECCFGR;
/* Set or reset Item */
if ((Attributes & SYSCFG_SEC) != 0x00U)
{
tmp |= Item;
}
else
{
tmp &= ~Item;
}
/* Set secure attributes */
SYSCFG_S->SECCFGR = tmp;
}
/**
* @brief Get the attribute of a SYSCFG item.
* @note Available attributes are to secure SYSCFG items, so this function is
* only available in secure
* @param Item Single item to get secure/non-secure attribute from.
* @param pAttributes pointer to return the attribute.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
{
/* Check null pointer */
if (pAttributes == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item));
/* Get the secure attribute state */
if ((SYSCFG_S->SECCFGR & Item) != 0U)
{
*pAttributes = SYSCFG_SEC;
}
else
{
*pAttributes = SYSCFG_NSEC;
}
return HAL_OK;
}
/**
* @}
*/
#endif /* __ARM_FEATURE_CMSE */
#ifdef SYSCFG_OTGHSPHYCR_EN
/**
* @brief Enable the OTG PHY .
* @param OTGPHYConfig: Defines the OTG PHY configuration. This parameter can be
SYSCFG_OTG_HS_PHY_ENABLE, SYSCFG_OTG_HS_PHY_UNDERRESET
* @retval None
*/
void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig)
{
/* Check the parameter */
assert_param(IS_SYSCFG_OTGPHY_CONFIG(OTGPHYConfig));
MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN, (uint32_t)(OTGPHYConfig) << SYSCFG_OTGHSPHYCR_EN_Pos);
}
/**
* @brief Set the OTG PHY Power Down config.
* @param PowerDownConfig: Defines the OTG PHY Power down configuration. This parameter can be
SYSCFG_OTG_HS_PHY_POWER_ON, SYSCFG_OTG_HS_PHY_POWER_DOWN
* @retval None
*/
void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig)
{
/* Check the parameter */
assert_param(IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(PowerDownConfig));
MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL, (uint32_t)(PowerDownConfig) << SYSCFG_OTGHSPHYCR_PDCTRL_Pos);
}
/**
* @brief Set the OTG PHY reference clock selection.
* @param RefClockSelection: Defines the OTG PHY reference clock selection. This parameter can be
* SYSCFG_OTG_HS_PHY_CLK_SELECT_1, SYSCFG_OTG_HS_PHY_CLK_SELECT_2, SYSCFG_OTG_HS_PHY_CLK_SELECT_3
* SYSCFG_OTG_HS_PHY_CLK_SELECT_4, SYSCFG_OTG_HS_PHY_CLK_SELECT_5, SYSCFG_OTG_HS_PHY_CLK_SELECT_6
* @retval None
*/
void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClockSelection)
{
/* Check the parameter */
assert_param(IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(RefClockSelection));
MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, \
(uint32_t)(RefClockSelection) << SYSCFG_OTGHSPHYCR_CLKSEL_Pos);
}
#endif /* SYSCFG_OTGHSPHYCR_EN */
/**
* @}
*/
#endif /* HAL_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c
|
C
|
apache-2.0
| 27,676
|
/**
******************************************************************************
* @file stm32u5xx_hal_adc.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Initialization and de-initialization functions
* ++ Initialization and Configuration of ADC
* + Operation functions
* ++ Start, stop, get result of conversions of regular
* group, using 3 possible modes: polling, interruption or DMA.
* + Control functions
* ++ Channels configuration on regular group
* ++ Analog Watchdog configuration
* + State functions
* ++ ADC state machine management
* ++ Interrupts and flags management
* Other functions (extended functions) are available in file
* "stm32u5xx_hal_adc_ex.c".
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### ADC peripheral features #####
==============================================================================
[..]
(+) 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
(+) Interrupt generation at the end of regular conversion and in case of
analog watchdog or overrun events.
(+) Single and continuous conversion modes.
(+) Scan mode for conversion of several channels sequentially.
(+) Data alignment with in-built data coherency.
(+) Programmable sampling time (channel wise)
(+) External trigger (timer or EXTI) with configurable polarity
(+) DMA request generation for transfer of conversions data of regular group.
(+) Configurable delay between conversions in Dual interleaved mode.
(+) ADC channels selectable single/differential input.
(+) ADC offset shared on 4 offset instances.
(+) ADC calibration
(+) ADC conversion of regular group.
(+) ADC supply requirements: 1.62 V to 3.6 V.
(+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
Vdda or to an external voltage reference).
##### How to use this driver #####
==============================================================================
[..]
*** Configuration of top level parameters related to ADC ***
============================================================
[..]
(#) Enable the ADC interface
(++) As prerequisite, ADC clock must be configured at RCC top level.
(++) Two clock settings are mandatory:
(+++) ADC clock (core clock, also possibly conversion clock).
(+++) ADC clock (conversions clock).
Six possible clock sources: synchronous clock derived from AHB clock
or asynchronous clock derived from system clock, the PLL2, the HSE, the HSI or the MSIK.
(+++) Example:
Into HAL_ADC_MspInit() (recommended code location) or with
other device clock parameters configuration:
(+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
RCC_ADCCLKSOURCE_PLL2 enable: (optional: if asynchronous clock selected)
(+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
(+++) PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2;
(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
(++) ADC clock source and clock prescaler are configured at ADC level with
parameter "ClockPrescaler" using function HAL_ADC_Init().
(#) ADC pins configuration
(++) Enable the clock for the ADC GPIOs
using macro __HAL_RCC_GPIOx_CLK_ENABLE()
(++) Configure these ADC pins in analog mode
using function HAL_GPIO_Init()
(#) Optionally, in case of usage of ADC with interruptions:
(++) Configure the NVIC for ADC
using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
into the function of corresponding ADC interruption vector
ADCx_IRQHandler().
(#) Optionally, in case of usage of DMA:
(++) Configure the DMA (DMA channel, mode normal or circular, ...)
using function HAL_DMA_Init().
(++) Configure the NVIC for DMA
using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
(++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
into the function of corresponding DMA interruption vector
DMAx_Channelx_IRQHandler().
*** Configuration of ADC, group regular, channels parameters ***
================================================================
[..]
(#) Configure the ADC parameters (resolution, data alignment, ...)
and regular group parameters (conversion trigger, sequencer, ...)
using function HAL_ADC_Init().
(#) Configure the channels for regular group parameters (channel number,
channel rank into sequencer, ..., into regular group)
using function HAL_ADC_ConfigChannel().
(#) Optionally, configure the analog watchdog parameters (channels
monitored, thresholds, ...)
using function HAL_ADC_AnalogWDGConfig().
*** Execution of ADC conversions ***
====================================
[..]
(#) Optionally, perform an automatic ADC calibration to improve the
conversion accuracy
using function HAL_ADCEx_Calibration_Start().
(#) ADC driver can be used among three modes: polling, interruption,
transfer by DMA.
(++) ADC conversion by polling:
(+++) Activate the ADC peripheral and start conversions
using function HAL_ADC_Start()
(+++) Wait for ADC conversion completion
using function HAL_ADC_PollForConversion()
(+++) Retrieve conversion results
using function HAL_ADC_GetValue()
(+++) Stop conversion and disable the ADC peripheral
using function HAL_ADC_Stop()
(++) ADC conversion by interruption:
(+++) Activate the ADC peripheral and start conversions
using function HAL_ADC_Start_IT()
(+++) Wait for ADC conversion completion by call of function
HAL_ADC_ConvCpltCallback()
(this function must be implemented in user program)
(+++) Retrieve conversion results
using function HAL_ADC_GetValue()
(+++) Stop conversion and disable the ADC peripheral
using function HAL_ADC_Stop_IT()
(++) ADC conversion with transfer by DMA:
(+++) Activate the ADC peripheral and start conversions
using function HAL_ADC_Start_DMA()
(+++) Wait for ADC conversion completion by call of function
HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
(these functions must be implemented in user program)
(+++) Conversion results are automatically transferred by DMA into
destination variable address.
(+++) Stop conversion and disable the ADC peripheral
using function HAL_ADC_Stop_DMA()
[..]
(@) Callback functions must be implemented in user program:
(+@) HAL_ADC_ErrorCallback()
(+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
(+@) HAL_ADC_ConvCpltCallback()
(+@) HAL_ADC_ConvHalfCpltCallback
*** Deinitialization of ADC ***
============================================================
[..]
(#) Disable the ADC interface
(++) ADC clock can be hard reset and disabled at RCC top level.
(++) Hard reset of ADC peripherals
using macro __HAL_RCC_ADCx_FORCE_RESET(), __HAL_RCC_ADCx_RELEASE_RESET().
(++) ADC clock disable
using the equivalent macro/functions as configuration step.
(+++) Example:
Into HAL_ADC_MspDeInit() (recommended code location) or with
other device clock parameters configuration:
(+++) __HAL_RCC_ADC_CLK_DISABLE(); (if not used anymore)
RCC_ADCDACCLKSOURCE_HSI restore: (optional)
(+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
(+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
(+++) PeriphClkInit.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HSI;
(+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
(#) ADC pins configuration
(++) Disable the clock for the ADC GPIOs
using macro __HAL_RCC_GPIOx_CLK_DISABLE()
(#) Optionally, in case of usage of ADC with interruptions:
(++) Disable the NVIC for ADC
using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
(#) Optionally, in case of usage of DMA:
(++) Deinitialize the DMA
using function HAL_DMA_Init().
(++) Disable the NVIC for DMA
using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
[..]
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_ADC_RegisterCallback()
to register an interrupt callback.
[..]
Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
(+) ErrorCallback : ADC error callback
(+) InjectedConvCpltCallback : ADC group injected conversion complete callback
(+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
(+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
(+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
(+) EndOfSamplingCallback : ADC end of sampling callback
(+) MspInitCallback : ADC Msp Init callback
(+) MspDeInitCallback : ADC Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
weak function.
[..]
@ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
(+) ErrorCallback : ADC error callback
(+) InjectedConvCpltCallback : ADC group injected conversion complete callback
(+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
(+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
(+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
(+) EndOfSamplingCallback : ADC end of sampling callback
(+) MspInitCallback : ADC Msp Init callback
(+) MspDeInitCallback : ADC Msp DeInit callback
[..]
By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
or @ref HAL_ADC_Init() function.
[..]
When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup ADC ADC
* @brief ADC HAL module driver
* @{
*/
#ifdef HAL_ADC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup ADC_Private_Constants ADC Private Constants
* @{
*/
#define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR1_RES |\
ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |\
ADC_CFGR1_DISCEN | ADC_CFGR1_DISCNUM |\
ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
when no regular conversion is on-going */
#define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\
ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
(neither regular nor injected) is on-going */
/* Timeout values for ADC operations (enable settling time, */
/* disable settling time, ...). */
/* Values defined to be higher than worst cases: low clock frequency, */
/* maximum prescalers. */
#define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
#define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
/* Timeout to wait for current conversion on going to be completed. */
/* Timeout fixed to worst case, for 1 channel. */
/* - maximum sampling time (830.5 adc_clk) */
/* - ADC resolution (Tsar 14 bits= 14.5 adc_clk) */
/* - ADC clock with prescaler 256 */
/* 823 * 256 = 210688 clock cycles max */
/* Unit: cycles of CPU clock. */
#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688) /*!< ADC conversion completion time-out value */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ADC_Exported_Functions ADC Exported Functions
* @{
*/
/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief ADC Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the ADC.
(+) De-initialize the ADC.
@endverbatim
* @{
*/
/**
* @brief Initialize the ADC peripheral and regular group according to
* parameters specified in structure "ADC_InitTypeDef".
* @note As prerequisite, ADC clock must be configured at RCC top level
* (refer to description of RCC configuration for ADC
* in header of this file).
* @note Possibility to update parameters on the fly:
* This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
* coming from ADC state reset. Following calls to this function can
* be used to reconfigure some parameters of ADC_InitTypeDef
* structure on the fly, without modifying MSP configuration. If ADC
* MSP has to be modified again, HAL_ADC_DeInit() must be called
* before HAL_ADC_Init().
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_InitTypeDef".
* @note This function configures the ADC within 2 scopes: scope of entire
* ADC and scope of regular group. For parameters details, see comments
* of structure "ADC_InitTypeDef".
* @note Parameters related to common ADC registers (ADC clock mode) are set
* only if all ADCs are disabled.
* If this is not the case, these common parameters setting are
* bypassed without error reporting: it can be the intended behaviour in
* case of update of a parameter of ADC_InitTypeDef on the fly,
* without disabling the other ADCs.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpCFGR1 = 0UL;
uint32_t tmpCFGR2 = 0UL;
uint32_t tmp_adc_reg_is_conversion_on_going;
__IO uint32_t wait_loop_index;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
/* Check ADC handle */
if (hadc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
}
else
{
assert_param(IS_ADC4_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
assert_param(IS_ADC4_LOW_POWER(hadc->Init.LowPowerAutoPowerOff));
assert_param(IS_ADC4_VREF_PROT(hadc->Init.VrefProtection));
assert_param(IS_ADC4_EXTTRIG(hadc->Init.ExternalTrigConv));
assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode));
assert_param(IS_ADC4_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1));
assert_param(IS_ADC4_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2));
}
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
{
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
if (hadc->Init.DiscontinuousConvMode == ENABLE)
{
assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
}
}
else
{
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
{
assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
}
}
}
/* DISCEN and CONT bits cannot be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
{
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/* Init the ADC Callback settings */
hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
}
hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
if (hadc->MspInitCallback == NULL)
{
hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
/* Initialize Lock */
hadc->Lock = HAL_UNLOCKED;
}
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
{
/* Disable ADC deep power down mode */
LL_ADC_DisableDeepPowerDown(hadc->Instance);
/* System was in deep power down mode, calibration must
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
{
/* Enable ADC internal voltage regulator */
LL_ADC_EnableInternalRegulator(hadc->Instance);
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
tmp_hal_status = HAL_ERROR;
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Configuration of common ADC parameters */
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - clock configuration */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
{
/* Reset configuration of ADC common register CCR: */
/* */
/* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
/* according to adc->Init.ClockPrescaler. It selects the clock */
/* source and sets the clock division factor. */
/* */
/* Some parameters of this register are not reset, since they are set */
/* by other functions and must be kept in case of usage of this */
/* function on the fly (update of a parameter of ADC_InitTypeDef */
/* without needing to reconfigure all other ADC groups/channels */
/* parameters): */
/* - when multimode feature is available, multimode-related */
/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
/* HAL_ADCEx_MultiModeConfigChannel() ) */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() or */
/* HAL_ADCEx_InjectedConfigChannel() ) */
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
}
}
else
{
/* Some parameters of this register are not reset, since they are set */
/* by other functions and must be kept in case of usage of this */
/* function on the fly (update of a parameter of ADC_InitTypeDef */
/* without needing to reconfigure all other ADC groups/channels */
/* parameters): */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() ) */
/* Configuration of ADC resolution */
MODIFY_REG(hadc->Instance->CFGR1,
ADC_CFGR1_RES,
__LL_ADC_RESOLUTION_ADC1_TO_ADC4(hadc->Init.Resolution)); /* Convert resolution for the ADC4 */
/* Configuration of ADC clock mode: clock source AHB or HSI with */
/* selectable prescaler. */
MODIFY_REG(ADC4_COMMON->CCR,
ADC_CCR_PRESC,
hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
}
}
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
/* Configuration of ADC: */
/* - resolution Init.Resolution */
/* - external trigger to start conversion Init.ExternalTrigConv */
/* - external trigger polarity Init.ExternalTrigConvEdge */
/* - continuous conversion mode Init.ContinuousConvMode */
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
tmpCFGR1 = (/*ADC_CFGR_AUTODELAY((uint32_t)hadc->Init.LowPowerAutoWait) |*/
ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
hadc->Init.Overrun |
hadc->Init.Resolution |
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
}
else
{
/* Configuration of ADC: */
/* - discontinuous mode */
/* - LowPowerAutoWait mode */
/* - LowPowerAutoPowerOff mode */
/* - continuous conversion mode */
/* - overrun */
/* - external trigger to start conversion */
/* - external trigger polarity */
/* - data alignment */
/* - resolution */
/* - scan direction */
/* - DMA continuous request */
tmpCFGR1 |= (ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
hadc->Init.DataAlign |
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
ADC_CFGR_DMACONTREQ(hadc, (uint32_t)hadc->Init.DMAContinuousRequests));
}
if (hadc->Init.DiscontinuousConvMode == ENABLE)
{
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
tmpCFGR1 |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
}
else
{
if (hadc->Init.ContinuousConvMode == DISABLE)
{
/* Enable the selected ADC group regular discontinuous mode */
tmpCFGR1 |= ADC_CFGR1_DISCEN;
}
else
{
/* ADC regular group discontinuous was intended to be enabled, */
/* but ADC regular group modes continuous and sequencer discontinuous */
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
}
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | hadc->Init.ExternalTrigConvEdge);
}
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR_FIELDS_1, tmpCFGR1);
}
else
{
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC4_CFGR1_EXTSEL) | hadc->Init.ExternalTrigConvEdge);
}
/* Update ADC configuration register with previous settings */
MODIFY_REG(hadc->Instance->CFGR1,
ADC_CFGR1_DISCEN |
ADC4_CFGR1_WAIT |
ADC_CFGR1_CONT |
ADC_CFGR1_OVRMOD |
ADC_CFGR1_EXTSEL |
ADC_CFGR1_EXTEN |
ADC4_CFGR1_ALIGN |
ADC4_CFGR1_SCANDIR |
ADC4_CFGR1_DMACFG,
tmpCFGR1);
if (hadc->Init.LowPowerAutoPowerOff != ADC_LOW_POWER_NONE)
{
SET_BIT(hadc->Instance->PW, hadc->Init.LowPowerAutoPowerOff);
}
if (hadc->Init.VrefProtection != ADC_VREF_PPROT_NONE)
{
SET_BIT(hadc->Instance->PW, hadc->Init.VrefProtection);
}
}
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular and injected groups: */
/* - Conversion data management Init.ConversionDataManagement */
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
/* - Oversampling parameters Init.Oversampling */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
{
tmpCFGR1 = (ADC_CFGR_AUTODELAY((uint32_t)hadc->Init.LowPowerAutoWait) |
ADC_CFGR_DMACONTREQ(hadc, (uint32_t)hadc->Init.ConversionDataManagement));
MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_AUTDLY | ADC_CFGR1_DMNGT, tmpCFGR1);
if (hadc->Init.GainCompensation != 0UL)
{
LL_ADC_SetGainCompensation(hadc->Instance, hadc->Init.GainCompensation);
}
if (hadc->Init.OversamplingMode == ENABLE)
{
assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
|| (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
{
/* Multi trigger is not applicable to software-triggered conversions */
assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
}
/* Configuration of Oversampler: */
/* - Oversampling Ratio */
/* - Right bit shift */
/* - Left bit shift */
/* - Triggered mode */
/* - Oversampling mode (continued/resumed) */
/* - trigger frequency mode */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
ADC_CFGR2_ROVSE |
(hadc->Init.Oversampling.Ratio << ADC_CFGR2_OVSR_Pos) |
hadc->Init.Oversampling.RightBitShift |
hadc->Init.Oversampling.TriggeredMode |
hadc->Init.Oversampling.OversamplingStopReset |
(hadc->Init.TriggerFrequencyMode >> 2UL));
}
else
{
/* Disable ADC oversampling scope on ADC group regular */
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
}
/* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
}
/* Configuration of regular group sequencer: */
/* - if scan mode is disabled, regular channels sequence length is set to */
/* 0x00: 1 channel converted (channel on regular rank 1) */
/* Parameter "NbrOfConversion" is discarded. */
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
{
/* Set number of ranks in regular group sequencer */
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
}
else
{
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
}
/* Initialize the ADC state */
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
}
else
{
/* Configuration of ADC: */
/* - oversampling enable */
/* - oversampling ratio */
/* - oversampling shift */
/* - oversampling discontinuous mode (triggered mode) */
/* - trigger frequency mode */
tmpCFGR2 |= (hadc->Init.Oversampling.Ratio |
hadc->Init.Oversampling.RightBitShift |
hadc->Init.Oversampling.TriggeredMode |
hadc->Init.TriggerFrequencyMode
);
if (hadc->Init.OversamplingMode == ENABLE)
{
SET_BIT(tmpCFGR2, ADC_CFGR2_ROVSE);
}
MODIFY_REG(hadc->Instance->CFGR2,
ADC_CFGR2_LFTRIG | ADC_CFGR2_ROVSE | ADC4_CFGR2_OVSR | ADC_CFGR2_OVSS | ADC_CFGR2_TROVS,
tmpCFGR2);
/* Channel sampling time configuration */
LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, \
hadc->Init.SamplingTimeCommon1);
LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, \
hadc->Init.SamplingTimeCommon2);
/* Configuration of regular group sequencer: */
/* - if scan mode is disabled, regular channels sequence length is set to */
/* 0x00: 1 channel converted (channel on regular rank 1) */
/* Parameter "NbrOfConversion" is discarded. */
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
/* Channels must be configured into each rank using function */
/* "HAL_ADC_ConfigChannel()". */
if (hadc->Init.ScanConvMode == ADC4_SCAN_DISABLE)
{
/* Set sequencer scan length by clearing ranks above rank 1 */
/* and do not modify rank 1 value. */
SET_BIT(hadc->Instance->CHSELR, ADC_CHSELR_SQ2_TO_SQ8);
}
else if (hadc->Init.ScanConvMode == ADC4_SCAN_ENABLE)
{
/* Count number of ranks available in HAL ADC handle variable */
uint32_t ADCGroupRegularSequencerRanksCount;
/* Parse all ranks from 1 to 8 */
for (ADCGroupRegularSequencerRanksCount = 0UL; ADCGroupRegularSequencerRanksCount < (8UL); \
ADCGroupRegularSequencerRanksCount++)
{
/* Check each sequencer rank until value of end of sequence */
if (((hadc->ADCGroupRegularSequencerRanks >> (ADCGroupRegularSequencerRanksCount * 4UL)) & ADC_CHSELR_SQ1) ==
ADC_CHSELR_SQ1)
{
break;
}
}
if (ADCGroupRegularSequencerRanksCount == 1UL)
{
/* Set ADC group regular sequencer: */
/* Set sequencer scan length by clearing ranks above rank 1 */
/* and do not modify rank 1 value. */
SET_BIT(hadc->Instance->CHSELR, ADC_CHSELR_SQ2_TO_SQ8);
}
else
{
/* Set ADC group regular sequencer: */
/* - Set ADC group regular sequencer to value memorized */
/* in HAL ADC handle */
/* Note: This value maybe be initialized at a unknown value, */
/* therefore after the first call of "HAL_ADC_Init()", */
/* each rank corresponding to parameter "NbrOfConversion" */
/* must be set using "HAL_ADC_ConfigChannel()". */
/* - Set sequencer scan length by clearing ranks above maximum rank */
/* and do not modify other ranks value. */
MODIFY_REG(hadc->Instance->CHSELR,
ADC_CHSELR_SQ_ALL,
(ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC4_REGULAR_RANK_2) & 0x1FUL)) \
| (hadc->ADCGroupRegularSequencerRanks)
);
}
}
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core IP clocking. */
/* Check through register CFGR1 (excluding analog watchdog configuration: */
/* set into separate dedicated function, and bits of ADC resolution set */
/* out of temporary variable 'tmpCFGR1'). */
if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_RES))
== tmpCFGR1)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
tmp_hal_status = HAL_ERROR;
}
}
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
tmp_hal_status = HAL_ERROR;
}
return tmp_hal_status;
}
/**
* @brief Deinitialize the ADC peripheral registers to their default reset
* values, with deinitialization of the ADC MSP.
* @note For devices with several ADCs: reset of ADC common registers is done
* only if all ADCs sharing the same common group are disabled.
* (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
* all ADC instances use the same core clock at RCC level, disabling
* the core clock reset all ADC instances).
* If this is not the case, reset of these common parameters reset is
* bypassed without error reporting: it can be the intended behavior in
* case of reset of a single ADC while the other ADCs sharing the same
* common group is still running.
* @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
* this saves more power by reducing leakage currents
* and is particularly interesting before entering MCU low-power modes.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check ADC handle */
if (hadc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
/* Stop potential conversion on going */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
/* Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_READY;
}
}
/* Note: HAL ADC deInit is done independently of ADC conversion stop */
/* and disable return status. In case of status fail, attempt to */
/* perform deinitialization anyway and it is up user code in */
/* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
/* system RCC hard reset. */
/* ========== Reset ADC registers ========== */
/* Reset register IER */
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 |
ADC_IT_AWD1 | ADC_IT_OVR |
ADC_IT_JEOS | ADC_IT_JEOC |
ADC_IT_EOS | ADC_IT_EOC |
ADC_IT_EOSMP | ADC_IT_RDY));
/* Reset register ISR */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 |
ADC_FLAG_AWD1 | ADC_FLAG_OVR |
ADC_FLAG_JEOS | ADC_FLAG_JEOC |
ADC_FLAG_EOS | ADC_FLAG_EOC |
ADC_FLAG_EOSMP | ADC_FLAG_RDY));
/* Reset register CR */
/* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
no direct reset applicable.
Update CR register to reset value where doable by software */
CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
/* Reset register CFGR */
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_AWD1CH | ADC_CFGR1_JAUTO | ADC_CFGR1_JAWD1EN |
ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_JDISCEN |
ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN | ADC_CFGR1_AUTDLY |
ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL |
ADC_CFGR1_RES | ADC_CFGR1_DMNGT);
/* Reset register CFGR2 */
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
/* Reset register SMPR1 */
CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
/* Reset register SMPR2 */
CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
/* Reset register LTR1 and HTR1 */
CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR_LT);
CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR_HT);
/* Reset register LTR2 and HTR2*/
CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR_LT);
CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR_HT);
/* Reset register LTR3 and HTR3 */
CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR_LT);
CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR_HT);
/* Reset register SQR1 */
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
ADC_SQR1_SQ1 | ADC_SQR1_L);
/* Reset register SQR2 */
CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
/* Reset register SQR3 */
CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
/* Reset register SQR4 */
CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
/* Register JSQR was reset when the ADC was disabled */
/* Reset register DR */
/* bits in access mode read only, no direct reset applicable*/
/* Reset register OFR1 */
CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSETPOS | ADC_OFR1_USAT | ADC_OFR1_SSAT | ADC_OFR1_OFFSET1_CH |
ADC_OFR1_OFFSET1);
/* Reset register OFR2 */
CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSETPOS | ADC_OFR2_USAT | ADC_OFR2_SSAT | ADC_OFR2_OFFSET2_CH |
ADC_OFR2_OFFSET2);
/* Reset register OFR3 */
CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSETPOS | ADC_OFR3_USAT | ADC_OFR3_SSAT | ADC_OFR3_OFFSET3_CH |
ADC_OFR3_OFFSET3);
/* Reset register OFR4 */
CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSETPOS | ADC_OFR4_USAT | ADC_OFR4_SSAT | ADC_OFR4_OFFSET4_CH |
ADC_OFR4_OFFSET4);
/* Reset register GCOMP */
CLEAR_BIT(hadc->Instance->GCOMP, ADC_GCOMP_GCOMP | ADC_GCOMP_GCOMPCOEFF);
/* Reset registers JDR1, JDR2, JDR3, JDR4 */
/* bits in access mode read only, no direct reset applicable*/
/* Reset register AWD2CR */
CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
/* Reset register AWD3CR */
CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
/* Reset register DIFSEL */
CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
/* Reset register PCSEL */
CLEAR_BIT(hadc->Instance->PCSEL, ADC_PCSEL_PCSEL);
/* Reset register CALFACT */
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF | ADC_CALFACT_LATCH_COEF);
}
else
{
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 |
ADC_IT_AWD1 | ADC_IT_OVR |
ADC_IT_EOS | ADC_IT_EOC |
ADC_IT_EOSMP | ADC_IT_RDY));
/* Reset register ISR */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 |
ADC_FLAG_AWD1 | ADC_FLAG_OVR |
ADC_FLAG_EOS | ADC_FLAG_EOC |
ADC_FLAG_EOSMP | ADC_FLAG_RDY));
/* Reset register CR */
/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
/* "read-set": no direct reset applicable. */
/* Reset register CFGR1 */
hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
ADC4_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC4_CFGR1_ALIGN | ADC_CFGR1_RES |
ADC4_CFGR1_SCANDIR | ADC4_CFGR1_DMACFG | ADC4_CFGR1_DMAEN);
/* Reset register CFGR2 */
/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
/* already done above. */
hadc->Instance->CFGR2 &= ~(ADC_CFGR2_ROVSE | ADC4_CFGR2_OVSR |
ADC_CFGR2_TROVS | ADC4_CFGR2_LFTRIG);
/* Reset register SMPR */
hadc->Instance->SMPR1 &= ~ADC_SMPR1_SMP1;
/* Reset register TR1 */
hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1);
/* Reset register CHSELR */
hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
/* Reset register DR */
/* bits in access mode read only, no direct reset applicable */
/* Reset register CCR */
ADC12_COMMON->CCR &= ~(ADC_CCR_VBATEN | ADC_CCR_VSENSEEN | ADC_CCR_VREFEN | ADC_CCR_PRESC);
}
/* ========== Reset common ADC registers ========== */
/* Software is allowed to change common parameters only when all the other
ADCs are disabled. */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
{
/* Reset configuration of ADC common register CCR:
- clock mode: CKMODE, PRESCEN
- multimode related parameters (when this feature is available): MDMA,
DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
- internal measurement paths: Vbat, temperature sensor, Vref (set into
HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
*/
ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
}
/* DeInit the low level hardware.
For example:
__HAL_RCC_ADC_FORCE_RESET();
__HAL_RCC_ADC_RELEASE_RESET();
__HAL_RCC_ADC_CLK_DISABLE();
Keep in mind that all ADCs use the same clock: disabling
the clock will reset all ADCs.
*/
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
if (hadc->MspDeInitCallback == NULL)
{
hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: RCC clock, NVIC */
hadc->MspDeInitCallback(hadc);
#else
/* DeInit the low level hardware: RCC clock, NVIC */
HAL_ADC_MspDeInit(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
if (hadc->Instance == ADC4)
{
/* Reset HAL ADC handle variable */
hadc->ADCGroupRegularSequencerRanks = 0x00000000UL;
}
else
{
/* Reset injected channel configuration parameters */
hadc->InjectionConfig.ContextQueue = 0;
hadc->InjectionConfig.ChannelCount = 0;
}
/* Set ADC state */
hadc->State = HAL_ADC_STATE_RESET;
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Initialize the ADC MSP.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_MspInit must be implemented in the user file.
*/
}
/**
* @brief DeInitialize the ADC MSP.
* @param hadc ADC handle
* @note All ADC instances use the same core clock at RCC level, disabling
* the core clock reset all ADC instances).
* @retval None
*/
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_MspDeInit must be implemented in the user file.
*/
}
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User ADC Callback
* To be used instead of the weak predefined callback
* @param hadc Pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
* @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
* @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
* @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
* @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
* @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
* @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
* @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
* @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
pADC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
{
switch (CallbackID)
{
case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
hadc->ConvCpltCallback = pCallback;
break;
case HAL_ADC_CONVERSION_HALF_CB_ID :
hadc->ConvHalfCpltCallback = pCallback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
hadc->LevelOutOfWindowCallback = pCallback;
break;
case HAL_ADC_ERROR_CB_ID :
hadc->ErrorCallback = pCallback;
break;
case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
hadc->InjectedConvCpltCallback = pCallback;
break;
case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
hadc->InjectedQueueOverflowCallback = pCallback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
hadc->LevelOutOfWindow2Callback = pCallback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
hadc->LevelOutOfWindow3Callback = pCallback;
break;
case HAL_ADC_END_OF_SAMPLING_CB_ID :
hadc->EndOfSamplingCallback = pCallback;
break;
case HAL_ADC_MSPINIT_CB_ID :
hadc->MspInitCallback = pCallback;
break;
case HAL_ADC_MSPDEINIT_CB_ID :
hadc->MspDeInitCallback = pCallback;
break;
default :
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else if (HAL_ADC_STATE_RESET == hadc->State)
{
switch (CallbackID)
{
case HAL_ADC_MSPINIT_CB_ID :
hadc->MspInitCallback = pCallback;
break;
case HAL_ADC_MSPDEINIT_CB_ID :
hadc->MspDeInitCallback = pCallback;
break;
default :
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a ADC Callback
* ADC callback is redirected to the weak predefined callback
* @param hadc Pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
* @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
* @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
* @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
* @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
* @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
* @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
* @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
* @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
* @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
{
switch (CallbackID)
{
case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
break;
case HAL_ADC_CONVERSION_HALF_CB_ID :
hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
break;
case HAL_ADC_ERROR_CB_ID :
hadc->ErrorCallback = HAL_ADC_ErrorCallback;
break;
case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
break;
case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
break;
case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
break;
case HAL_ADC_END_OF_SAMPLING_CB_ID :
hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
break;
case HAL_ADC_MSPINIT_CB_ID :
hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
break;
case HAL_ADC_MSPDEINIT_CB_ID :
hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else if (HAL_ADC_STATE_RESET == hadc->State)
{
switch (CallbackID)
{
case HAL_ADC_MSPINIT_CB_ID :
hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
break;
case HAL_ADC_MSPDEINIT_CB_ID :
hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
* @brief ADC IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start conversion of regular group.
(+) Stop conversion of regular group.
(+) Poll for conversion complete on regular group.
(+) Poll for conversion event.
(+) Get result of regular channel conversion.
(+) Start conversion of regular group and enable interruptions.
(+) Stop conversion of regular group and disable interruptions.
(+) Handle ADC interrupt request
(+) Start conversion of regular group and enable DMA transfer.
(+) Stop conversion of regular group and disable ADC DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Enable ADC, start conversion of regular group.
* @note Interruptions enabled in this function: None.
* @note Case of multimode enabled (when multimode feature is available):
* if ADC is Slave, ADC is enabled but conversion is not started,
* if ADC is master, ADC is enabled and multimode conversion is started.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmp_adc_master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
__HAL_LOCK(hadc);
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
HAL_ADC_STATE_REG_BUSY);
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
#if defined(ADC_MULTIMODE_SUPPORT)
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- by default if ADC is Master or Independent or if multimode feature is not available
- if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif /* ADC_MULTIMODE_SUPPORT */
/* Set ADC error code */
/* Check if a conversion is on going on ADC group injected */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
/* Reset ADC error code fields related to regular conversions only */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
}
else
{
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
}
else
{
/* Set ADC error code */
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Case of multimode enabled (when multimode feature is available): */
/* - if ADC is slave and dual regular conversions are enabled, ADC is */
/* enabled only (conversion is not started), */
/* - if ADC is master, ADC is enabled and conversion is started. */
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
)
{
/* Multimode feature is not available or ADC Instance is Independent or Master,
or is not Slave ADC with dual regular conversions enabled.
Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */
if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
/* if Master ADC JAUTO bit is set, update Slave State in setting
HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
tmp_adc_master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
if (READ_BIT(tmp_adc_master->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
}
#else
if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
#endif /* ADC_MULTIMODE_SUPPORT */
}
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
__HAL_UNLOCK(hadc);
}
}
else
{
tmp_hal_status = HAL_BUSY;
}
return tmp_hal_status;
}
/**
* @brief Stop ADC conversion of regular group (and injected channels in
* case of auto_injection mode), disable ADC peripheral.
* @note: ADC peripheral disable is forcing stop of potential
* conversion on injected group. If injected group is under use, it
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
/* 2. Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
}
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Wait for regular group conversion to be completed.
* @note ADC conversion flags EOS (end of sequence) and EOC (end of
* conversion) are cleared by this function, with an exception:
* if low power feature "LowPowerAutoWait" is enabled, flags are
* not cleared to not interfere with this feature until data register
* is read using function HAL_ADC_GetValue().
* @note This function cannot be used in a particular setup: ADC configured
* in DMA mode and polling for end of each conversion (ADC init
* parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
* In this case, DMA resets the flag EOC and polling cannot be
* performed on each conversion. Nevertheless, polling can still
* be performed on the complete sequence (ADC init
* parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
* @param hadc ADC handle
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t tmp_flag_end;
uint32_t tmp_cfgr;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmp_adc_master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* If end of conversion selected to end of sequence conversions */
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
{
tmp_flag_end = ADC_FLAG_EOS;
}
/* If end of conversion selected to end of unitary conversion */
else /* ADC_EOC_SINGLE_CONV */
{
/* Verification that ADC configuration is compliant with polling for */
/* each conversion: */
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and and polling for end of each conversion. */
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
#if defined(ADC_MULTIMODE_SUPPORT)
if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
)
{
/* Check ADC DMA mode */
if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0) != 0UL)
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
return HAL_ERROR;
}
else
{
tmp_flag_end = (ADC_FLAG_EOC);
}
}
else
{
/* Check ADC DMA mode in multimode */
if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
return HAL_ERROR;
}
else
{
tmp_flag_end = (ADC_FLAG_EOC);
}
}
#else
/* Check ADC DMA mode */
if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0) != 0UL)
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
return HAL_ERROR;
}
else
{
tmp_flag_end = (ADC_FLAG_EOC);
}
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
if ((hadc->Instance->CFGR1 & ADC4_CFGR1_DMAEN) != 0UL)
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
return HAL_ERROR;
}
else
{
tmp_flag_end = (ADC_FLAG_EOC);
}
}
}
/* Get tick count */
tickstart = HAL_GetTick();
/* Wait until End of unitary conversion or sequence conversions flag is raised */
while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
{
/* Check if timeout is disabled (set to infinite wait) */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_TIMEOUT;
}
}
}
}
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
&& (hadc->Init.ContinuousConvMode == DISABLE)
)
{
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
/* Check whether end of sequence is reached */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
#if defined(ADC_MULTIMODE_SUPPORT)
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
)
{
/* Retrieve handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
}
else
{
/* Retrieve Master ADC CFGR register */
tmp_adc_master = ADC_MASTER_REGISTER(hadc);
tmp_cfgr = READ_REG(tmp_adc_master->CFGR1);
}
#else
/* Retrieve handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear polled flag */
if (tmp_flag_end == ADC_FLAG_EOS)
{
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
}
else
{
/* Clear end of conversion EOC flag of regular group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
/* until data register is read using function HAL_ADC_GetValue(). */
if (READ_BIT(tmp_cfgr, ADC_CFGR1_AUTDLY) == 0UL)
{
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
}
}
else
{
/* Check whether end of sequence is reached */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
{
/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
/* ADSTART==0 (no conversion on going) */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_READY);
}
else
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
/* Clear end of conversion flag of regular group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
/* until data register is read using function HAL_ADC_GetValue(). */
if (hadc->Init.LowPowerAutoWait == DISABLE)
{
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
}
}
return HAL_OK;
}
/**
* @brief Poll for ADC event.
* @param hadc ADC handle
* @param EventType the ADC event type.
* This parameter can be one of the following values:
* @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
* @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog,
* present on all STM32 devices)
* @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog,
* not present on all STM32 families)
* @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog,
* not present on all STM32 families)
* @arg @ref ADC_OVR_EVENT ADC Overrun event
* @param Timeout Timeout value in millisecond.
* @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
* Indeed, the latter is reset only if hadc->Init.Overrun field is set
* to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
* by a new converted data as soon as OVR is cleared.
* To reset OVR flag once the preserved data is retrieved, the user can resort
* to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
{
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EVENT_TYPE(EventType));
/* Get tick count */
tickstart = HAL_GetTick();
/* Check selected event flag */
while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
{
/* Check if timeout is disabled (set to infinite wait) */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
/* New check to avoid false timeout detection in case of preemption */
if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_TIMEOUT;
}
}
}
}
switch (EventType)
{
/* End Of Sampling event */
case ADC_EOSMP_EVENT:
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
/* Clear the End Of Sampling flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
break;
/* Analog watchdog (level out of window) event */
/* Note: In case of several analog watchdog enabled, if needed to know */
/* which one triggered and on which ADCx, test ADC state of analog watchdog */
/* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
/* For example: */
/* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
/* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
/* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
/* Check analog watchdog 1 flag */
case ADC_AWD_EVENT:
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
break;
/* Check analog watchdog 2 flag */
case ADC_AWD2_EVENT:
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
break;
/* Check analog watchdog 3 flag */
case ADC_AWD3_EVENT:
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
break;
/* Overrun event */
default: /* Case ADC_OVR_EVENT */
/* If overrun is set to overwrite previous data, overrun event is not */
/* considered as an error. */
/* (cf ref manual "Managing conversions without using the DMA and without */
/* overrun ") */
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
/* Set ADC error code to overrun */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
}
else
{
/* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
otherwise, data register is potentially overwritten by new converted data as soon
as OVR is cleared. */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
break;
}
return HAL_OK;
}
/**
* @brief Enable ADC, start conversion of regular group with interruption.
* @note Interruptions enabled in this function according to initialization
* setting : EOC (end of conversion), EOS (end of sequence),
* OVR overrun.
* Each of these interruptions has its dedicated callback function.
* @note Case of multimode enabled (when multimode feature is available):
* HAL_ADC_Start_IT() must be called for ADC Slave first, then for
* ADC Master.
* For ADC Slave, ADC is enabled only (conversion is not started).
* For ADC Master, ADC is enabled and multimode conversion is started.
* @note To guarantee a proper reset of all interruptions once all the needed
* conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
* a correct stop of the IT-based conversions.
* @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
* interruption. If required (e.g. in case of oversampling with trigger
* mode), the user must:
* 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
* 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
* before calling HAL_ADC_Start_IT().
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmp_adc_master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
__HAL_LOCK(hadc);
tmp_hal_status = ADC_Enable(hadc);
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
HAL_ADC_STATE_REG_BUSY);
#if defined(ADC_MULTIMODE_SUPPORT)
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- by default if ADC is Master or Independent or if multimode feature is not available
- if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif /* ADC_MULTIMODE_SUPPORT */
/* Set ADC error code */
/* Check if a conversion is on going on ADC group injected */
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
{
/* Reset ADC error code fields related to regular conversions only */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
}
else
{
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Disable all interruptions before enabling the desired ones */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
/* Enable ADC end of conversion interrupt */
switch (hadc->Init.EOCSelection)
{
case ADC_EOC_SEQ_CONV:
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
break;
/* case ADC_EOC_SINGLE_CONV */
default:
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
break;
}
/* Enable ADC overrun interrupt */
/* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
behavior and no CPU time is lost for a non-processed interruption */
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
{
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
}
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Case of multimode enabled (when multimode feature is available): */
/* - if ADC is slave and dual regular conversions are enabled, ADC is */
/* enabled only (conversion is not started), */
/* - if ADC is master, ADC is enabled and conversion is started. */
/* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
)
{
/* Multimode feature is not available or ADC Instance is Independent or Master,
or is not Slave ADC with dual regular conversions enabled.
Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */
if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
/* Enable as well injected interruptions in case
HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
allows to start regular and injected conversions when JAUTO is
set with a single call to HAL_ADC_Start_IT() */
switch (hadc->Init.EOCSelection)
{
case ADC_EOC_SEQ_CONV:
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
break;
/* case ADC_EOC_SINGLE_CONV */
default:
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
break;
}
}
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
/* hadc is the handle of a Slave ADC with dual regular conversions
enabled. Therefore, ADC_CR_ADSTART is NOT set */
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
/* if Master ADC JAUTO bit is set, Slave injected interruptions
are enabled nevertheless (for same reason as above) */
tmp_adc_master = ADC_MASTER_REGISTER(hadc);
if (READ_BIT(tmp_adc_master->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
{
/* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
and in resetting HAL_ADC_STATE_INJ_EOC bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
/* Next, set Slave injected interruptions */
switch (hadc->Init.EOCSelection)
{
case ADC_EOC_SEQ_CONV:
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
break;
/* case ADC_EOC_SINGLE_CONV */
default:
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
break;
}
}
}
#else
if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO) != 0UL)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
/* Enable as well injected interruptions in case
HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
allows to start regular and injected conversions when JAUTO is
set with a single call to HAL_ADC_Start_IT() */
switch (hadc->Init.EOCSelection)
{
case ADC_EOC_SEQ_CONV:
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
break;
/* case ADC_EOC_SINGLE_CONV */
default:
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
break;
}
}
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
__HAL_UNLOCK(hadc);
}
}
else
{
tmp_hal_status = HAL_BUSY;
}
return tmp_hal_status;
}
/**
* @brief Stop ADC conversion of regular group (and injected group in
* case of auto_injection mode), disable interrution of
* end-of-conversion, disable ADC peripheral.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
/* Disable ADC end of conversion interrupt for regular group */
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
/* 2. Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_READY);
}
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Enable ADC, start conversion of regular group and transfer result through DMA.
* @note Interruptions enabled in this function:
* overrun (if applicable), DMA half transfer, DMA transfer complete.
* Each of these interruptions has its dedicated callback function.
* @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
* is designed for single-ADC mode only. For multimode, the dedicated
* HAL_ADCEx_MultiModeStart_DMA() function must be used.
* @param hadc ADC handle
* @param pData Destination Buffer address.
* @param Length Number of data to be transferred from ADC peripheral to memory
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
{
HAL_StatusTypeDef tmp_hal_status;
uint32_t LengthInBytes;
DMA_NodeConfTypeDef node_conf;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
__HAL_LOCK(hadc);
#if defined(ADC_MULTIMODE_SUPPORT)
/* Ensure that multimode regular conversions are not enabled. */
/* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
)
#endif /* ADC_MULTIMODE_SUPPORT */
{
tmp_hal_status = ADC_Enable(hadc);
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
HAL_ADC_STATE_REG_BUSY);
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
#if defined(ADC_MULTIMODE_SUPPORT)
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- if ADC instance is master or if multimode feature is not available
- if multimode setting is disabled (ADC instance slave in independent mode) */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check if a conversion is on going on ADC group injected */
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
{
/* Reset ADC error code fields related to regular conversions only */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
}
else
{
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
}
else
{
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
/* ADC start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC */
/* operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* With DMA, overrun event is always considered as an error even if
hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
ADC_IT_OVR is enabled. */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
if (hadc->Instance == ADC4)
{
/* Enable ADC DMA mode */
hadc->Instance->CFGR1 |= ADC4_CFGR1_DMAEN;
}
/* Start the DMA channel */
/* Check linkedlist mode */
if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
{
/* Length should be converted to number of bytes */
if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
{
return HAL_ERROR;
}
/* Length should be converted to number of bytes */
if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
{
/* Word -> Bytes */
LengthInBytes = Length * 4U;
}
else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
{
/* Halfword -> Bytes */
LengthInBytes = Length * 2U;
}
else /* Bytes */
{
/* Same size already expressed in Bytes */
LengthInBytes = Length;
}
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes;
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
(uint32_t)&hadc->Instance->DR;
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
}
else
{
tmp_hal_status = HAL_ERROR;
}
}
else
{
/* Length should be converted to number of bytes */
if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
{
/* Word -> Bytes */
LengthInBytes = Length * 4U;
}
else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
{
/* Halfword -> Bytes */
LengthInBytes = Length * 2U;
}
else /* Bytes */
{
/* Same size already expressed in Bytes */
LengthInBytes = Length;
}
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, \
LengthInBytes);
}
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
__HAL_UNLOCK(hadc);
}
}
#if defined(ADC_MULTIMODE_SUPPORT)
else
{
tmp_hal_status = HAL_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hadc);
}
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
tmp_hal_status = HAL_BUSY;
}
return tmp_hal_status;
}
/**
* @brief Stop ADC conversion of regular group (and injected group in
* case of auto_injection mode), disable ADC DMA transfer, disable
* ADC peripheral.
* @note: ADC peripheral disable is forcing stop of potential
* conversion on ADC group injected. If ADC group injected is under use, it
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
* @note Case of multimode enabled (when multimode feature is available):
* HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
* For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
/* 1. Stop potential ADC group regular conversion on going */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
/* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1, 0UL);
}
else
{
/* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
CLEAR_BIT(hadc->Instance->CFGR1, ADC4_CFGR1_DMAEN);
}
/* Disable the DMA channel (in case of DMA in circular mode or stop */
/* while DMA transfer is on going) */
if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
{
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Check if DMA channel effectively disabled */
if (tmp_hal_status != HAL_OK)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
}
}
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
/* 2. Disable the ADC peripheral */
/* Update "tmp_hal_status" only if DMA channel disabling passed, */
/* to keep in memory a potential failing status. */
if (tmp_hal_status == HAL_OK)
{
tmp_hal_status = ADC_Disable(hadc);
}
else
{
(void)ADC_Disable(hadc);
}
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
{
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
}
else
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_READY);
}
}
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Get ADC regular group conversion result.
* @note Reading register DR automatically clears ADC flag EOC
* (ADC group regular end of unitary conversion).
* @note This function does not clear ADC flag EOS
* (ADC group regular end of sequence conversion).
* Occurrence of flag EOS rising:
* - If sequencer is composed of 1 rank, flag EOS is equivalent
* to flag EOC.
* - If sequencer is composed of several ranks, during the scan
* sequence flag EOC only is raised, at the end of the scan sequence
* both flags EOC and EOS are raised.
* To clear this flag, either use function:
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
* model polling: @ref HAL_ADC_PollForConversion()
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Note: EOC flag is not cleared here by software because automatically */
/* cleared by hardware when reading register DR. */
/* Return ADC converted value */
return hadc->Instance->DR;
}
/**
* @brief Handle ADC interrupt request.
* @param hadc ADC handle
* @retval None
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
{
uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
uint32_t tmp_isr = hadc->Instance->ISR;
uint32_t tmp_ier = hadc->Instance->IER;
uint32_t tmp_adc_inj_is_trigger_source_sw_start;
uint32_t tmp_adc_reg_is_trigger_source_sw_start;
uint32_t tmp_cfgr;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmp_adc_master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
/* ========== Check End of Sampling flag for ADC group regular ========== */
if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
{
/* Update state machine on end of sampling status if not in error state */
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
}
/* End Of Sampling callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->EndOfSamplingCallback(hadc);
#else
HAL_ADCEx_EndOfSamplingCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
}
/* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
{
/* Update state machine on conversion status if not in error state */
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
}
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
{
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
)
{
/* check CONT bit directly in handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
}
else
{
/* else need to check Master ADC CONT bit */
tmp_adc_master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
tmp_cfgr = READ_REG(tmp_adc_master->CFGR1);
}
#else
tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
#endif /* ADC_MULTIMODE_SUPPORT */
/* Carry on if continuous mode is disabled */
if (READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) != ADC_CFGR1_CONT)
{
/* If End of Sequence is reached, disable interrupts */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
{
/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
/* ADSTART==0 (no conversion on going) */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* Disable ADC end of sequence conversion interrupt */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
else
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
}
}
}
else
{
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
&& (hadc->Init.ContinuousConvMode == DISABLE)
)
{
/* If End of Sequence is reached, disable interrupts */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
{
/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
/* ADSTART==0 (no conversion on going) */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_READY);
}
else
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
}
}
}
/* Conversion complete callback */
/* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
/* to determine if conversion has been triggered from EOC or EOS, */
/* possibility to use: */
/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */
/* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
/* conversion flags clear induces the release of the preserved data.*/
/* Therefore, if the preserved data value is needed, it must be */
/* read preliminarily into HAL_ADC_ConvCpltCallback(). */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
/* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
(((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
{
/* Update state machine on conversion status if not in error state */
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
}
/* Retrieve ADC configuration */
tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
)
{
tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
}
else
{
tmp_adc_master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
tmp_cfgr = READ_REG(tmp_adc_master->CFGR1);
}
#else
tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
#endif /* ADC_MULTIMODE_SUPPORT */
/* Disable interruption if no further conversion upcoming by injected */
/* external trigger or by automatic injected conversion with regular */
/* group having no further conversion upcoming (same conditions as */
/* regular group interruption disabling above), */
/* and if injected scan sequence is completed. */
if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
{
if ((READ_BIT(tmp_cfgr, ADC_CFGR1_JAUTO) == 0UL) ||
((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
(READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) == 0UL)))
{
/* If End of Sequence is reached, disable interrupts */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
{
/* Particular case if injected contexts queue is enabled: */
/* when the last context has been fully processed, JSQR is reset */
/* by the hardware. Even if no injected conversion is planned to come */
/* (queue empty, triggers are ignored), it can start again */
/* immediately after setting a new context (JADSTART is still set). */
/* Therefore, state of HAL ADC injected group is kept to busy. */
/* No ADC_CFGR1_JQM for STM32U5 */
/* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
/* JADSTART==0 (no conversion on going) */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* Disable ADC end of sequence conversion interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
}
}
}
/* Injected Conversion complete callback */
/* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
interruption has been triggered by end of conversion or end of
sequence. */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->InjectedConvCpltCallback(hadc);
#else
HAL_ADCEx_InjectedConvCpltCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
}
} /* Specific ADC1 or ADC2 only */
/* ========== Check Analog watchdog 1 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Level out of window 1 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindowCallback(hadc);
#else
HAL_ADC_LevelOutOfWindowCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
}
/* ========== Check analog watchdog 2 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
/* Level out of window 2 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindow2Callback(hadc);
#else
HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
}
/* ========== Check analog watchdog 3 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
/* Level out of window 3 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindow3Callback(hadc);
#else
HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
}
/* ========== Check Overrun flag ========== */
if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
{
/* If overrun is set to overwrite previous data (default setting), */
/* overrun event is not considered as an error. */
/* (cf ref manual "Managing conversions without using the DMA and without */
/* overrun ") */
/* Exception for usage with DMA overrun event always considered as an */
/* error. */
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
{
overrun_error = 1UL;
}
else
{
/* Check DMA configuration */
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
#if defined(ADC_MULTIMODE_SUPPORT)
/* Check DMA configuration */
if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
{
/* Multimode (when feature is available) is enabled,
Common Control Register MDMA bits must be checked. */
if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
{
overrun_error = 1UL;
}
}
else
{
/* Multimode not set or feature not available or ADC independent */
if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMNGT) != 0UL)
{
overrun_error = 1UL;
}
}
#else
/* Multimode not set or feature not available or ADC independent */
if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMNGT) != 0UL)
{
overrun_error = 1UL;
}
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
/* Check DMA configuration */
if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE_ADC4)
{
overrun_error = 1UL;
}
}
}
if (overrun_error == 1UL)
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
/* Set ADC error code to overrun */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
/* Error callback */
/* Note: In case of overrun, ADC conversion data is preserved until */
/* flag OVR is reset. */
/* Therefore, old ADC conversion data can be retrieved in */
/* function "HAL_ADC_ErrorCallback()". */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/* Clear ADC overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
}
/**
* @brief Conversion complete callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvCpltCallback must be implemented in the user file.
*/
}
/**
* @brief Conversion DMA half-transfer callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
*/
}
/**
* @brief Analog watchdog 1 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
*/
}
/**
* @brief ADC error callback in non-blocking mode
* (ADC conversion with interruption or transfer by DMA).
* @note In case of error due to overrun when using ADC with DMA transfer
* (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
* - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
* - If needed, restart a new ADC conversion using function
* "HAL_ADC_Start_DMA()"
* (this function is also clearing overrun flag)
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ErrorCallback must be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure channels on regular group
(+) Configure the analog watchdog
@endverbatim
* @{
*/
/**
* @brief Configure a channel to be assigned to ADC group regular.
* @note In case of usage of internal measurement channels:
* Vbat/VrefInt/TempSensor.
* These internal paths can be disabled using function
* HAL_ADC_DeInit().
* @note Possibility to update parameters on the fly:
* This function initializes channel into ADC group regular,
* following calls to this function can be used to reconfigure
* some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
* without resetting the ADC.
* The setting of these parameters is conditioned to ADC state:
* Refer to comments of structure "ADC_ChannelConfTypeDef".
* @param hadc ADC handle
* @param pConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_offset_shifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
uint32_t tmp_channel;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff));
assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pConfig->Offset));
/* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
ignored (considered as reset) */
assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
/* Verification of channel number */
if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
{
assert_param(IS_ADC_CHANNEL(pConfig->Channel));
}
else
{
#if defined(ADC2)
assert_param(IS_ADC12_DIFF_CHANNEL(pConfig->Channel));
#else
assert_param(IS_ADC1_DIFF_CHANNEL(pConfig->Channel));
#endif /* ADC2 */
}
}
else
{
assert_param(IS_ADC4_SAMPLE_TIME_COMMON(pConfig->SamplingTime));
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
(hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
{
assert_param(IS_ADC4_REGULAR_RANK_SEQ_FIXED(pConfig->Rank));
}
else
{
assert_param(IS_ADC4_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
assert_param(IS_ADC4_REGULAR_RANK(pConfig->Rank));
}
}
__HAL_LOCK(hadc);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel rank */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
/* ADC channels preselection */
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) & 0x1FUL));
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmp_offset_shifted);
assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSignedSaturation));
/* Set ADC selected offset sign */
LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
/* Set ADC selected offset signed saturation */
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfig->OffsetNumber, \
(pConfig->OffsetSignedSaturation == ENABLE) \
? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \
: LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
else
{
/* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
If this is the case, offset OFRx is disabled since
pConfig->OffsetNumber = ADC_OFFSET_NONE. */
if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
{
CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSAT);
}
if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
{
CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSAT);
}
if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
{
CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSAT);
}
if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
{
CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSAT);
}
}
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */
/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
/* Configuration of differential mode */
if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Set sampling time of the selected ADC channel */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
tmp_channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel) \
+ 1UL) & 0x1FUL);
LL_ADC_SetChannelSamplingTime(hadc->Instance, tmp_channel, pConfig->SamplingTime);
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
{
/* Configuration of common ADC parameters */
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
/* Software is allowed to change common parameters only when all ADCs */
/* of the common group are disabled. */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
{
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) \
* ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel \
& LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
if (ADC_VREFINT_INSTANCE(hadc))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
}
}
else
{
/* nothing to do */
}
}
/* If the requested internal measurement path has already been */
/* enabled and other ADC of the common group are enabled, internal */
/* measurement paths cannot be enabled. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
}
}
}
else
{
/* Remap Internal Channels for Cut1 vs Cut2 (or 4M) */
tmp_channel = pConfig->Channel;
#if !defined (ADC2)
if (HAL_GetREVID() == REV_ID_A) /* STM32U5 silicon Rev.A */
{
if (pConfig->Channel == ADC4_CHANNEL_TEMPSENSOR)
{
tmp_channel = (LL_ADC_CHANNEL_22 | ADC_CHANNEL_ID_INTERNAL_CH);
}
else if (pConfig->Channel == ADC4_CHANNEL_VBAT)
{
tmp_channel = (LL_ADC_CHANNEL_23 | ADC_CHANNEL_ID_INTERNAL_CH);
}
else if (pConfig->Channel == ADC_CHANNEL_VCORE)
{
tmp_channel = (LL_ADC_CHANNEL_VREFINT | LL_ADC_CHANNEL_DIFFERENCIATION_VREFINT_VCORE);
}
else if (pConfig->Channel == ADC_CHANNEL_DAC1CH1_ADC4)
{
tmp_channel = (LL_ADC_CHANNEL_20 | ADC_CHANNEL_ID_INTERNAL_CH);
}
else if (pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4)
{
tmp_channel = (LL_ADC_CHANNEL_21 | ADC_CHANNEL_ID_INTERNAL_CH);
}
else
{
tmp_channel = pConfig->Channel;
}
}
#endif /* ADC2 */
/* Configure channel: depending on rank setting, add it or remove it from */
/* ADC sequencer. */
/* If sequencer set to not fully configurable with channel rank set to */
/* none, remove the channel from the sequencer. */
/* Otherwise (sequencer set to fully configurable or to to not fully */
/* configurable with channel rank to be set), configure the selected */
/* channel. */
if (pConfig->Rank != ADC4_RANK_NONE)
{
/* Regular sequence configuration */
/* Note: ADC channel configuration requires few ADC clock cycles */
/* to be ready. Processing of ADC settings in this function */
/* induce that a specific wait time is not necessary. */
/* For more details on ADC channel configuration ready, */
/* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
(hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
{
/* Sequencer set to not fully configurable: */
/* Set the channel by enabling the corresponding bitfield. */
LL_ADC_REG_SetSequencerChAdd(hadc->Instance, tmp_channel);
}
else
{
/* Sequencer set to fully configurable: */
/* Set the channel by entering it into the selected rank. */
/* Memorize the channel set into variable in HAL ADC handle */
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
ADC_CHSELR_SQ1 << (pConfig->Rank & 0x1FUL),
__LL_ADC_CHANNEL_TO_DECIMAL_NB(tmp_channel) << (pConfig->Rank & 0x1FUL));
/* If the selected rank is below ADC group regular sequencer length, */
/* apply the configuration in ADC register. */
/* Note: Otherwise, configuration is not applied. */
/* To apply it, parameter'NbrOfConversion' must be increased. */
if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
{
#if !defined (ADC2)
if (HAL_GetREVID() <= REV_ID_A) /* STM32U5 silicon Rev.A */
{
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(tmp_channel) >= 20UL)
{
tmp_channel = (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(tmp_channel) - 9UL));
}
}
#endif /* ADC2 */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, tmp_channel);
}
}
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, tmp_channel, pConfig->SamplingTime);
/* Management of internal measurement channels: VrefInt/TempSensor/Vbat */
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
/* channel configuration parameter "Rank". */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((pConfig->Channel == ADC4_CHANNEL_TEMPSENSOR) \
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
else if ((pConfig->Channel == ADC4_CHANNEL_VBAT) && ((tmp_config_internal_channel \
& LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) \
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
}
else if ((pConfig->Channel == ADC_CHANNEL_VCORE) \
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
#if !defined (ADC2)
if (ADC_VCORE_INSTANCE(hadc))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
if (HAL_GetREVID() <= REV_ID_A) /* STM32U5 silicon Rev.A */
{
SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL);
}
}
#endif /* ADC2 */
}
else
{
/* nothing to do */
}
/* If STM32U5 silicon Rev.B (or 4M), ADC_CHANNEL_DAC1CH1 and ADC_CHANNEL_DAC1CH2 are both on Channel 21
and selection is done via ADC_OR[0] register */
#if !defined (ADC2)
if (HAL_GetREVID() == REV_ID_B) /* STM32U5 silicon Rev.B */
{
if ((pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4) \
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL);
}
}
#else
if ((pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4) \
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL);
}
#endif /* ADC2 */
}
}
else
{
/* Regular sequencer configuration */
/* Note: Case of sequencer set to fully configurable: */
/* Sequencer rank cannot be disabled, only affected to */
/* another channel. */
/* To remove a rank, use parameter 'NbrOfConversion". */
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
(hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
{
/* Sequencer set to not fully configurable: */
/* Reset the channel by disabling the corresponding bitfield. */
LL_ADC_REG_SetSequencerChRem(hadc->Instance, tmp_channel);
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
}
else if (pConfig->Channel == ADC_CHANNEL_VBAT)
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel);
}
else if (pConfig->Channel == ADC_CHANNEL_VREFINT)
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
}
else if (pConfig->Channel == ADC_CHANNEL_VCORE)
{
#if !defined (ADC2)
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
if (HAL_GetREVID() <= REV_ID_A) /* STM32U5 silicon Rev.A */
{
SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL);
}
#endif /* ADC2 */
}
else
{
/* nothing to do */
}
/* If STM32U5 2M silicon Rev.B (or 4M), ADC_CHANNEL_DAC1CH1 and ADC_CHANNEL_DAC1CH2 are both on Channel 21
and selection is done via ADC_OR[0] register */
#if !defined (ADC2)
if (HAL_GetREVID() == REV_ID_B) /* STM32U5 silicon Rev.B */
{
if ((pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4) \
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL);
}
}
#else
if ((pConfig->Channel == ADC_CHANNEL_DAC1CH2_ADC4) \
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
SET_BIT((hadc->Instance->OR), ADC_OR_CHN0SEL);
}
#endif /* ADC2 */
}
}
}
}
/* If a conversion is on going on regular group, no update on regular */
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Configure the analog watchdog.
* @note Possibility to update parameters on the fly:
* This function initializes the selected analog watchdog, successive
* calls to this function can be used to reconfigure some parameters
* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
* the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_AnalogWDGConfTypeDef".
* @param hadc ADC handle
* @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_awd_high_threshold_shifted;
uint32_t tmp_awd_low_threshold_shifted;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
(pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
(pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
{
assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel));
}
/* Verify thresholds range */
if (hadc->Init.OversamplingMode == ENABLE)
{
/* Case of oversampling enabled: thresholds are compared to oversampling
intermediate computation (after ratio, before shift application) */
assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc),
pAnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc),
pAnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
}
else
{
/* Verify if thresholds are within the selected ADC resolution */
assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
}
__HAL_LOCK(hadc);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on ADC groups regular and injected: */
/* - Analog watchdog channels */
/* - Analog watchdog thresholds */
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
}
else
{
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = 0UL; /* No injected channels for ADC4 so force \
tmp_adc_is_conversion_on_going_injected to 0 */
}
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
{
/* Analog watchdog configuration */
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
{
/* Configuration of analog watchdog: */
/* - Set the analog watchdog enable mode: one or overall group of */
/* channels, on groups regular and-or injected. */
switch (pAnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR));
break;
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
LL_ADC_GROUP_INJECTED));
break;
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
__LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
LL_ADC_GROUP_REGULAR_INJECTED));
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
break;
case ADC_ANALOGWATCHDOG_ALL_INJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
break;
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
break;
}
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
/* Set the filtering configuration */
assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(pAnalogWDGConfig->FilteringConfig));
LL_ADC_SetAWDFilteringConfiguration(hadc->Instance, hadc->Instance->HTR1, pAnalogWDGConfig->FilteringConfig);
}
/* Shift the offset in function of the selected ADC resolution: */
/* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
/* are set to 0 */
tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
tmp_awd_low_threshold_shifted);
/* Update state, clear previous result related to AWD1 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Clear flag ADC analog watchdog */
/* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
/* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
/* (in case left enabled by previous ADC operations). */
LL_ADC_ClearFlag_AWD1(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if (pAnalogWDGConfig->ITMode == ENABLE)
{
LL_ADC_EnableIT_AWD1(hadc->Instance);
}
else
{
LL_ADC_DisableIT_AWD1(hadc->Instance);
}
}
/* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
else
{
switch (pAnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
/* Update AWD by bitfield to keep the possibility to monitor */
/* several channels by successive calls of this function. */
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
SET_BIT(hadc->Instance->AWD2CR, (1UL \
<< (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
}
else
{
SET_BIT(hadc->Instance->AWD3CR, (1UL \
<< (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
}
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
case ADC_ANALOGWATCHDOG_ALL_INJEC:
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, \
LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
break;
}
/* Shift the thresholds in function of the selected ADC resolution */
/* have to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
if (hadc->Instance == ADC4)
{
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber,
tmp_awd_high_threshold_shifted,
tmp_awd_low_threshold_shifted);
}
else /* ADC1 or ADC2 */
{
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
MODIFY_REG(hadc->Instance->LTR2, ADC_LTR_LT, tmp_awd_low_threshold_shifted);
MODIFY_REG(hadc->Instance->HTR2, ADC_HTR_HT, tmp_awd_high_threshold_shifted);
}
else
{
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
MODIFY_REG(hadc->Instance->LTR3, ADC_LTR_LT, tmp_awd_low_threshold_shifted);
MODIFY_REG(hadc->Instance->HTR3, ADC_HTR_HT, tmp_awd_high_threshold_shifted);
}
}
if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
/* Update state, clear previous result related to AWD2 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
/* Clear flag ADC analog watchdog */
/* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
/* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
/* (in case left enabled by previous ADC operations). */
LL_ADC_ClearFlag_AWD2(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if (pAnalogWDGConfig->ITMode == ENABLE)
{
LL_ADC_EnableIT_AWD2(hadc->Instance);
}
else
{
LL_ADC_DisableIT_AWD2(hadc->Instance);
}
}
/* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
else
{
/* Update state, clear previous result related to AWD3 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
/* Clear flag ADC analog watchdog */
/* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
/* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
/* (in case left enabled by previous ADC operations). */
LL_ADC_ClearFlag_AWD3(hadc->Instance);
/* Configure ADC analog watchdog interrupt */
if (pAnalogWDGConfig->ITMode == ENABLE)
{
LL_ADC_EnableIT_AWD3(hadc->Instance);
}
else
{
LL_ADC_DisableIT_AWD3(hadc->Instance);
}
}
}
}
/* If a conversion is on going on ADC group regular or injected, no update */
/* could be done on neither of the AWD configuration structure parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @}
*/
/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
* @brief ADC Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral state and errors functions #####
===============================================================================
[..]
This subsection provides functions to get in run-time the status of the
peripheral.
(+) Check the ADC state
(+) Check the ADC error code
@endverbatim
* @{
*/
/**
* @brief Return the ADC handle state.
* @note ADC state machine is managed by bitfields, ADC status must be
* compared with states bits.
* For example:
* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
* @param hadc ADC handle
* @retval ADC handle state (bitfield on 32 bits)
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Return ADC handle state */
return hadc->State;
}
/**
* @brief Return the ADC error code.
* @param hadc ADC handle
* @retval ADC error code (bitfield on 32 bits)
*/
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
return hadc->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup ADC_Private_Functions ADC Private Functions
* @{
*/
/**
* @brief Stop ADC conversion.
* @param hadc ADC handle
* @param ConversionGroup ADC group regular and/or injected.
* This parameter can be one of the following values:
* @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
* @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
* @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
{
uint32_t tickstart;
uint32_t conversion_timeout_cpu_cycles = 0UL;
uint32_t conversion_group_reassigned = ConversionGroup;
uint32_t tmp_adc_cr_adstart_jadstart;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
/* Verification if ADC is not already stopped (on regular and injected */
/* groups) to bypass this function if not needed. */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((tmp_adc_is_conversion_on_going_regular != 0UL) || (tmp_adc_is_conversion_on_going_injected != 0UL))
{
/* Particular case of continuous auto-injection mode combined with */
/* auto-delay mode. */
/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
/* injected group stop ADC_CR_JADSTP). */
/* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
/* (see reference manual). */
if (((hadc->Instance->CFGR1 & ADC_CFGR1_JAUTO) != 0UL)
&& (hadc->Init.ContinuousConvMode == ENABLE)
&& (hadc->Init.LowPowerAutoWait == ENABLE)
)
{
/* Use stop of regular group */
conversion_group_reassigned = ADC_REGULAR_GROUP;
/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
{
if (conversion_timeout_cpu_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
conversion_timeout_cpu_cycles++;
}
/* Clear JEOS */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
}
/* Stop potential conversion on going on ADC group regular */
if (conversion_group_reassigned != ADC_INJECTED_GROUP)
{
/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
{
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
{
/* Stop ADC group regular conversion */
LL_ADC_REG_StopConversion(hadc->Instance);
}
}
}
/* Stop potential conversion on going on ADC group injected */
if (conversion_group_reassigned != ADC_REGULAR_GROUP)
{
/* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
{
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
{
/* Stop ADC group injected conversion */
LL_ADC_INJ_StopConversion(hadc->Instance);
}
}
}
/* Selection of start and stop bits with respect to the regular or injected group */
switch (conversion_group_reassigned)
{
case ADC_REGULAR_INJECTED_GROUP:
tmp_adc_cr_adstart_jadstart = (ADC_CR_ADSTART | ADC_CR_JADSTART);
break;
case ADC_INJECTED_GROUP:
tmp_adc_cr_adstart_jadstart = ADC_CR_JADSTART;
break;
/* Case ADC_REGULAR_GROUP only*/
default:
tmp_adc_cr_adstart_jadstart = ADC_CR_ADSTART;
break;
}
/* Wait for conversion effectively stopped */
tickstart = HAL_GetTick();
while ((hadc->Instance->CR & tmp_adc_cr_adstart_jadstart) != 0UL)
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & tmp_adc_cr_adstart_jadstart) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
}
}
}
return HAL_OK;
}
/**
* @brief Enable the selected ADC.
* @note Prerequisite condition to use this function: ADC must be disabled
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
uint32_t tickstart;
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Check if conditions to enable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
| ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
LL_ADC_Enable(hadc->Instance);
/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
/* performed automatically by hardware and flag ADC ready is not set. */
if ((hadc->Init.LowPowerAutoPowerOff == ADC_LOW_POWER_NONE) || (hadc->Instance != ADC4))
{
/* Wait for ADC effectively enabled */
tickstart = HAL_GetTick();
/* Poll for ADC ready flag raised except case of multimode enabled
and ADC slave selected. */
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
)
#endif /* ADC_MULTIMODE_SUPPORT */
{
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
{
/* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
has been cleared (after a calibration), ADEN bit is reset by the
calibration logic.
The workaround is to continue setting ADEN until ADRDY is becomes 1.
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
4 ADC clock cycle duration */
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
LL_ADC_Enable(hadc->Instance);
}
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
{
/* New check to avoid false timeout detection in case of preemption */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
}
}
}
}
}
return HAL_OK;
}
/**
* @brief Disable the selected ADC.
* @note Prerequisite condition to use this function: ADC conversions must be
* stopped.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
{
uint32_t tickstart;
const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
&& (tmp_adc_is_disable_on_going == 0UL)
)
{
/* Check if conditions to disable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
{
/* Disable the ADC peripheral */
LL_ADC_Disable(hadc->Instance);
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
/* Get tick count */
tickstart = HAL_GetTick();
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
}
}
}
return HAL_OK;
}
/**
* @brief DMA transfer complete callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Update state machine on conversion status if not in error state */
if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
/* Is it the end of the regular sequence ? */
if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
{
/* Are conversions software-triggered ? */
if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
{
/* Is CONT bit set ? */
if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_CONT) == 0UL)
{
/* CONT bit is not set, no more conversions expected */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
}
}
else
{
/* DMA End of Transfer interrupt was triggered but conversions sequence
is not over. If DMACFG is set to 0, conversions are stopped. */
if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT) == 0UL)
{
/* DMACFG bit is not set, conversions are stopped. */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
}
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
else /* DMA and-or internal error occurred */
{
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
{
/* Call HAL ADC Error Callback function */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
else
{
/* Call ADC DMA error callback */
hadc->DMA_Handle->XferErrorCallback(hdma);
}
}
}
/**
* @brief DMA half transfer complete callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvHalfCpltCallback(hadc);
#else
HAL_ADC_ConvHalfCpltCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/**
* @brief DMA error callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
/* Set ADC error code to DMA error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
/* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/**
* @}
*/
#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c
|
C
|
apache-2.0
| 182,193
|
/**
******************************************************************************
* @file stm32u5xx_hal_adc_ex.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Operation functions
* ++ Start, stop, get result of conversions of ADC group injected,
* using 2 possible modes: polling, interruption.
* ++ Calibration
* +++ ADC automatic self-calibration
* +++ Calibration factors get or set
* ++ Multimode feature when available
* + Control functions
* ++ Channels configuration on ADC group injected
* + State functions
* ++ ADC group injected contexts queue management
* Other functions (generic functions) are available in file
* "stm32u5xx_hal_adc.c".
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
[..]
(@) Sections "ADC peripheral features" and "How to use this driver" are
available in file of generic functions "stm32u5xx_hal_adc.c".
[..]
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup ADCEx ADCEx
* @brief ADC Extended HAL module driver
* @{
*/
#ifdef HAL_ADC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
* @{
*/
#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
once the ADC is enabled */
/* Fixed timeout value for ADC calibration. */
/* Values defined to be higher than worst cases: low clock frequency, */
/* maximum prescalers. */
/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */
/* according to Data sheet), calibration_time MAX = 16384 / f_ADC */
/* 16384 / 4577.63671875 = 3.58s */
/* At maximum CPU speed (400 MHz), this means */
/* 3.58 * 400 MHz = 1432000000 CPU cycles */
#define ADC_CALIBRATION_TIMEOUT (1432000000U) /*!< ADC calibration time-out value */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
* @{
*/
/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
* @brief Extended IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Perform the ADC self-calibration for single or differential ending.
(+) Get calibration factors for single or differential ending.
(+) Set calibration factors for single or differential ending.
(+) Start conversion of ADC group injected.
(+) Stop conversion of ADC group injected.
(+) Poll for conversion complete on ADC group injected.
(+) Get result of ADC group injected channel conversion.
(+) Start conversion of ADC group injected and enable interruptions.
(+) Stop conversion of ADC group injected and disable interruptions.
(+) When multimode feature is available, start multimode and enable DMA transfer.
(+) Stop multimode and disable ADC DMA transfer.
(+) Get result of multimode conversion.
@endverbatim
* @{
*/
/**
* @brief Perform an ADC automatic self-calibration
* Calibration prerequisite: ADC must be disabled (execute this
* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
* @param hadc ADC handle
* @param CalibrationMode Selection of calibration offset or
* linear calibration offset.
* @arg ADC_CALIB_OFFSET Channel in mode calibration offset
* @arg ADC_CALIB_OFFSET_LINEARITY Channel in mode linear calibration offset
* @param SingleDiff Selection of single-ended or differential input
* This parameter can be one of the following values:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
{
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
UNUSED(SingleDiff); /* STM32U5 calibration is not making difference between Single and Diff ended */
/* We keep this to be inligne with old products API and for any further use */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
__HAL_LOCK(hadc);
/* Calibration prerequisite: ADC must be disabled. */
/* Disable the ADC (if not already disabled) */
tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL);
/* Start ADC calibration in mode single-ended or differential */
LL_ADC_StartCalibration(hadc->Instance, CalibrationMode);
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
{
wait_loop_index++;
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
}
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
}
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Note: No need to update variable "tmp_hal_status" here: already set */
/* to state "HAL_ERROR" by function disabling the ADC. */
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Get the calibration factor.
* @param hadc ADC handle.
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @retval Calibration value.
*/
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
uint32_t Calib_Val = 0UL;
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
if (hadc->Instance != ADC4)
{
tmp_hal_status = ADC_Enable(hadc); /* ADC need to be enabled to perform calibration for ADC1/2 and not for ADC4 */
}
if (tmp_hal_status == HAL_OK)
{
/* Return the selected ADC calibration value */
Calib_Val = LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff);
}
if (hadc->Instance != ADC4)
{
tmp_hal_status = ADC_Disable(hadc);
UNUSED(tmp_hal_status);
}
return Calib_Val;
}
/**
* @brief Get the calibration factor from automatic conversion result
* @param hadc ADC handle
* @param pLinearCalib_Buffer: Linear calibration factor
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer)
{
uint32_t cnt;
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
{
SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF);
for (cnt = 0UL; cnt <= 8UL; cnt++)
{
MODIFY_REG(hadc->Instance->CR,
(ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0),
(cnt << ADC_CR_CALINDEX0_Pos)); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/
pLinearCalib_Buffer[cnt] = (uint32_t)(READ_BIT(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT_Msk));
}
}
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
tmp_hal_status = ADC_Disable(hadc);
return tmp_hal_status;
}
/**
* @brief Set the calibration factor to overwrite automatic conversion result.
* ADC must be enabled and no conversion is ongoing.
* @param hadc ADC handle
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
uint32_t CalibrationFactor)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
assert_param(IS_ADC_CALFACT(CalibrationFactor));
__HAL_LOCK(hadc);
/* Verification of hardware constraints before modifying the calibration */
/* factors register: ADC must be enabled, no conversion on going. */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
{
/* Set the selected ADC calibration value */
LL_ADC_SetCalibrationOffsetFactor(hadc->Instance, SingleDiff, CalibrationFactor);
}
else
{
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Update ADC error code */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
/* Update ADC state machine to error */
tmp_hal_status = HAL_ERROR;
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Set the linear calibration factor
* @param hadc ADC handle
* @param pLinearCalib_Buffer: Linear calibration factor
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *pLinearCalib_Buffer)
{
uint32_t cnt;
__IO uint32_t wait_loop_index;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
/* Exit deep power down mode if still in that state */
if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
{
/* Exit deep power down mode */
CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
/* System was in deep power down mode, calibration must
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
{
/* Enable ADC internal voltage regulator */
SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
/* Delay for ADC stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL)));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
}
if (ADC_Enable(hadc) == HAL_OK)
{
/* We need to wait till ADC_ISR_ADRDY flag go up to set calibration values. */
/* However this is already done by ADC_Enable(). */
/* Therefore a simple check of the flag could help to ensure ADC is ready. */
if ((hadc->Instance->ISR & ADC_ISR_ADRDY) == 0UL)
{
return HAL_ERROR;
}
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF | ADC_CALFACT_CAPTURE_COEF);
for (cnt = 0UL; cnt <= 8UL; cnt++)
{
MODIFY_REG(hadc->Instance->CR,
(ADC_CR_CALINDEX3 | ADC_CR_CALINDEX2 | ADC_CR_CALINDEX1 | ADC_CR_CALINDEX0),
(cnt << ADC_CR_CALINDEX0_Pos)); /* LinearityWord == CalibIndex (1 to 8 for linearity reading)*/
MODIFY_REG(hadc->Instance->CALFACT2, ADC_CALFACT2_CALFACT, pLinearCalib_Buffer[cnt]);
}
}
SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF);
CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CAPTURE_COEF);
return HAL_OK;
}
/**
* @brief Enable ADC, start conversion of injected group.
* @note Interruptions enabled in this function: None.
* @note Case of multimode enabled when multimode feature is available:
* HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
* then for ADC master.
* For ADC slave, ADC is enabled only (conversion is not started).
* For ADC master, ADC is enabled and multimode conversion is started.
* @param hadc ADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
{
tmp_hal_status = HAL_BUSY;
}
else
{
/* In case of software trigger detection enabled, JQDIS must be set
(which can be done only if ADSTART and JADSTART are both cleared).
If JQDIS is not set at that point, returns an error
- since software trigger detection is disabled. User needs to
resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
- or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
the queue is empty */
__HAL_LOCK(hadc);
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
{
/* Clear ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
/* Set ADC state */
/* - Clear state bitfield related to injected group conversion results */
/* - Set state bitfield related to injected operation */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
#if defined(ADC_MULTIMODE_SUPPORT)
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- if ADC instance is master or if multimode feature is not available
- if multimode setting is disabled (ADC instance slave in independent mode) */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear ADC group injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Enable conversion of injected group, if automatic injected conversion */
/* is disabled. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Case of multimode enabled (when multimode feature is available): */
/* if ADC is slave, */
/* - ADC is enabled only (conversion is not started), */
/* - if multimode only concerns regular conversion, ADC is enabled */
/* and conversion is started. */
/* If ADC is master or independent, */
/* - ADC is enabled and conversion is started. */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
)
{
/* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
{
LL_ADC_INJ_StartConversion(hadc->Instance);
}
}
else
{
/* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#else
if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
{
LL_ADC_INJ_StartConversion(hadc->Instance);
}
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
__HAL_UNLOCK(hadc);
}
}
return tmp_hal_status;
}
/**
* @brief Stop conversion of injected channels. Disable ADC peripheral if
* no regular conversion is on going.
* @note If ADC must be disabled and if conversion is on going on
* regular group, function HAL_ADC_Stop must be used to stop both
* injected and regular groups, and disable the ADC.
* @note If injected group mode auto-injection is enabled,
* function HAL_ADC_Stop must be used.
* @note In case of multimode enabled (when multimode feature is available),
* HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
* For ADC master, conversion is stopped and ADC is disabled.
* For ADC slave, ADC is disabled only (conversion stop of ADC master
* has already stopped conversion of ADC slave).
* @param hadc ADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
/* 1. Stop potential conversion on going on injected group only. */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
/* Disable ADC peripheral if injected conversions are effectively stopped */
/* and if no conversion on regular group is on-going */
if (tmp_hal_status == HAL_OK)
{
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* 2. Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
}
}
/* Conversion on injected group is stopped, but ADC not disabled since */
/* conversion on regular group is still running. */
else
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
}
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Wait for injected group conversion to be completed.
* @param hadc ADC handle
* @param Timeout Timeout value in millisecond.
* @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is
* checked and cleared depending on AUTDLY bit status.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t tmp_flag_end;
uint32_t tmp_adc_inj_is_trigger_source_sw_start;
uint32_t tmp_adc_reg_is_trigger_source_sw_start;
uint32_t tmp_cfgr;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmp_adc_master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* If end of sequence selected */
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
{
tmp_flag_end = ADC_FLAG_JEOS;
}
else /* end of conversion selected */
{
tmp_flag_end = ADC_FLAG_JEOC;
}
tickstart = HAL_GetTick();
/* Wait until End of Conversion or Sequence flag is raised */
while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
{
/* Check if timeout is disabled (set to infinite wait) */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_TIMEOUT;
}
}
}
}
/* Retrieve ADC configuration */
tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
)
{
tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
}
else
{
tmp_adc_master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
tmp_cfgr = READ_REG(tmp_adc_master->CFGR1);
}
#else
tmp_cfgr = READ_REG(hadc->Instance->CFGR1);
#endif /* ADC_MULTIMODE_SUPPORT */
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
/* Determine whether any further conversion upcoming on group injected */
/* by external trigger or by automatic injected conversion */
/* from group regular. */
if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) ||
((READ_BIT(tmp_cfgr, ADC_CFGR1_JAUTO) == 0UL) &&
((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
(READ_BIT(tmp_cfgr, ADC_CFGR1_CONT) == 0UL))))
{
/* Check whether end of sequence is reached */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
{
/* Particular case if injected contexts queue is enabled: */
/* when the last context has been fully processed, JSQR is reset */
/* by the hardware. Even if no injected conversion is planned to come */
/* (queue empty, triggers are ignored), it can start again */
/* immediately after setting a new context (JADSTART is still set). */
/* Therefore, state of HAL ADC injected group is kept to busy. */
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
}
}
}
/* Clear polled flag */
if (tmp_flag_end == ADC_FLAG_JEOS)
{
/* Clear end of sequence JEOS flag of injected group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature. */
/* For injected groups, no new conversion will start before JEOS is */
/* cleared. */
if (READ_BIT(tmp_cfgr, ADC_CFGR1_AUTDLY) == 0UL)
{
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
}
}
else
{
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
}
return HAL_OK;
}
/**
* @brief Enable ADC, start conversion of injected group with interruption.
* @note Interruptions enabled in this function according to initialization
* setting : JEOC (end of conversion) or JEOS (end of sequence)
* @note Case of multimode enabled (when multimode feature is enabled):
* HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
* then for ADC master.
* For ADC slave, ADC is enabled only (conversion is not started).
* For ADC master, ADC is enabled and multimode conversion is started.
* @param hadc ADC handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
{
tmp_hal_status = HAL_BUSY;
}
else
{
/* In case of software trigger detection enabled, JQDIS must be set
(which can be done only if ADSTART and JADSTART are both cleared).
If JQDIS is not set at that point, returns an error
- since software trigger detection is disabled. User needs to
resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
- or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
the queue is empty */
__HAL_LOCK(hadc);
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
{
/* Clear ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
/* Set ADC state */
/* - Clear state bitfield related to injected group conversion results */
/* - Set state bitfield related to injected operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
HAL_ADC_STATE_INJ_BUSY);
#if defined(ADC_MULTIMODE_SUPPORT)
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- if ADC instance is master or if multimode feature is not available
- if multimode setting is disabled (ADC instance slave in independent mode) */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear ADC group injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Enable ADC end of conversion interrupt */
switch (hadc->Init.EOCSelection)
{
case ADC_EOC_SEQ_CONV:
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
break;
/* case ADC_EOC_SINGLE_CONV */
default:
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
break;
}
/* Enable conversion of injected group, if automatic injected conversion */
/* is disabled. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Case of multimode enabled (when multimode feature is available): */
/* if ADC is slave, */
/* - ADC is enabled only (conversion is not started), */
/* - if multimode only concerns regular conversion, ADC is enabled */
/* and conversion is started. */
/* If ADC is master or independent, */
/* - ADC is enabled and conversion is started. */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
)
{
/* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
{
LL_ADC_INJ_StartConversion(hadc->Instance);
}
}
else
{
/* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
}
#else
if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
{
LL_ADC_INJ_StartConversion(hadc->Instance);
}
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
__HAL_UNLOCK(hadc);
}
}
return tmp_hal_status;
}
/**
* @brief Stop conversion of injected channels, disable interruption of
* end-of-conversion. Disable ADC peripheral if no regular conversion
* is on going.
* @note If ADC must be disabled and if conversion is on going on
* regular group, function HAL_ADC_Stop must be used to stop both
* injected and regular groups, and disable the ADC.
* @note If injected group mode auto-injection is enabled,
* function HAL_ADC_Stop must be used.
* @note Case of multimode enabled (when multimode feature is available):
* HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
* then for ADC slave.
* For ADC master, conversion is stopped and ADC is disabled.
* For ADC slave, ADC is disabled only (conversion stop of ADC master
* has already stopped conversion of ADC slave).
* @note In case of auto-injection mode, HAL_ADC_Stop() must be used.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
/* 1. Stop potential conversion on going on injected group only. */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
/* Disable ADC peripheral if injected conversions are effectively stopped */
/* and if no conversion on the other group (regular group) is intended to */
/* continue. */
if (tmp_hal_status == HAL_OK)
{
/* Disable ADC end of conversion interrupt for injected channels */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS));
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* 2. Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
}
}
/* Conversion on injected group is stopped, but ADC not disabled since */
/* conversion on regular group is still running. */
else
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
}
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
* @note Multimode must have been previously configured using
* HAL_ADCEx_MultiModeConfigChannel() function.
* Interruptions enabled in this function:
* overrun, DMA half transfer, DMA transfer complete.
* Each of these interruptions has its dedicated callback function.
* @note State field of Slave ADC handle is not updated in this configuration:
* user should not rely on it for information related to Slave regular
* conversions.
* @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
* @param pData Destination Buffer address.
* @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
{
HAL_StatusTypeDef tmp_hal_status;
ADC_HandleTypeDef tmp_hadc_slave;
ADC_Common_TypeDef *tmp_adc_common;
uint32_t LengthInBytes;
DMA_NodeConfTypeDef node_conf;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
{
tmp_hal_status = HAL_BUSY;
}
else
{
__HAL_LOCK(hadc);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmp_hadc_slave.Instance == NULL)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
/* Enable the ADC peripherals: master and slave (in case if not already */
/* enabled previously) */
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
{
/* Reinitialize the LowPowerAutoPowerOff parameter from master to slave */
tmp_hadc_slave.Init.LowPowerAutoPowerOff = hadc->Init.LowPowerAutoPowerOff;
tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
}
/* Start multimode conversion of ADCs pair */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
(HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR \
| HAL_ADC_STATE_REG_EOSMP),
HAL_ADC_STATE_REG_BUSY);
ADC_CLEAR_ERRORCODE(hadc);
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
/* Pointer to the common control register */
tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Start the DMA channel */
/* Check linkedlist mode */
if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
{
/* Length should be converted to number of bytes */
if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hadc->DMA_Handle->LinkedListQueue->Head) != HAL_OK)
{
return HAL_ERROR;
}
/* Length should be converted to number of bytes */
if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
{
/* Word -> Bytes */
LengthInBytes = Length * 4U;
}
else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
{
/* Halfword -> Bytes */
LengthInBytes = Length * 2U;
}
else /* Bytes */
{
/* Same size already expressed in Bytes */
LengthInBytes = Length;
}
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes;
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
(uint32_t)&tmp_adc_common->CDR;
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
}
else
{
tmp_hal_status = HAL_ERROR;
}
}
else
{
/* Length should be converted to number of bytes */
if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
{
/* Word -> Bytes */
LengthInBytes = Length * 4U;
}
else if (hadc->DMA_Handle->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
{
/* Halfword -> Bytes */
LengthInBytes = Length * 2U;
}
else /* Bytes */
{
/* Same size already expressed in Bytes */
LengthInBytes = Length;
}
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR, (uint32_t)pData, \
LengthInBytes);
}
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
__HAL_UNLOCK(hadc);
}
}
return tmp_hal_status;
}
/**
* @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
* @note Multimode is kept enabled after this function. MultiMode DMA bits
* (MDMA and DMACFG bits of common CCR register) are maintained. To disable
* Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
* reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
* resort to HAL_ADCEx_DisableMultiMode() API.
* @note In case of DMA configured in circular mode, function
* HAL_ADC_Stop_DMA() must be called after this function with handle of
* ADC slave, to properly disable the DMA channel.
* @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
uint32_t tickstart;
ADC_HandleTypeDef tmp_hadc_slave;
uint32_t tmp_hadc_slave_conversion_on_going;
HAL_StatusTypeDef tmp_hadc_slave_disable_status;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
/* 1. Stop potential multimode conversion on going, on regular and injected groups */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmp_hadc_slave.Instance == NULL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
/* Procedure to disable the ADC peripheral: wait for conversions */
/* effectively stopped (ADC master and ADC slave), then disable ADC */
/* 1. Wait for ADC conversion completion for ADC master and ADC slave */
tickstart = HAL_GetTick();
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
/* New check to avoid false timeout detection in case of preemption */
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
}
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
}
/* Disable the DMA channel (in case of DMA in circular mode or stop */
/* while DMA transfer is on going) */
/* Note: DMA channel of ADC slave should be stopped after this function */
/* with HAL_ADC_Stop_DMA() API. */
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Check if DMA channel effectively disabled */
if (tmp_hal_status == HAL_ERROR)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
}
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
/* 2. Disable the ADC peripherals: master and slave */
/* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
/* memory a potential failing status. */
if (tmp_hal_status == HAL_OK)
{
tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
if ((ADC_Disable(hadc) == HAL_OK) &&
(tmp_hadc_slave_disable_status == HAL_OK))
{
tmp_hal_status = HAL_OK;
}
}
else
{
/* In case of error, attempt to disable ADC master and slave without status assert */
(void) ADC_Disable(hadc);
(void) ADC_Disable(&tmp_hadc_slave);
}
/* Set ADC state (ADC master) */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
* @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
* @retval The converted data values.
*/
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc)
{
const ADC_Common_TypeDef *tmp_adc_common;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
/* Prevent unused argument(s) compilation warning if no assert_param check */
/* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
UNUSED(hadc);
/* Pointer to the common control register */
tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* Return the multi mode conversion value */
return tmp_adc_common->CDR;
}
/**
* @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA.
* @note Multimode must have been previously configured using
* HAL_ADCEx_MultiModeConfigChannel() function.
* Interruptions enabled in this function:
* overrun, DMA half transfer, DMA transfer complete.
* Each of these interruptions has its dedicated callback function.
* @note State field of Slave ADC handle is not updated in this configuration:
* user should not rely on it for information related to Slave regular
* conversions.
* @param hadc ADC handle of ADC
* @note - Only ADC master could start the conversion.
* - Two ADC conversions (Master & Slave) per external trig and so two DMA requests.
* @param pData Destination Buffer address.
* @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA_Data32(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length)
{
HAL_StatusTypeDef tmp_hal_status;
ADC_HandleTypeDef tmp_hadc_slave;
ADC_Common_TypeDef *tmp_adc_common;
uint32_t LengthInBytes;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
{
return HAL_BUSY;
}
else
{
__HAL_LOCK(hadc);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmp_hadc_slave.Instance == NULL)
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
/* Enable the ADC peripherals: master and slave (in case if not already */
/* enabled previously) */
tmp_hal_status = ADC_Enable(hadc);
if (tmp_hal_status == HAL_OK)
{
/* Reinitialize the LowPowerAutoPowerOff parameter from master to slave */
tmp_hadc_slave.Init.LowPowerAutoPowerOff = hadc->Init.LowPowerAutoPowerOff;
tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
}
/* Start multimode conversion of ADCs pair */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
(HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR \
| HAL_ADC_STATE_REG_EOSMP),
HAL_ADC_STATE_REG_BUSY);
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
/* Pointer to the common control register */
tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Length should be converted to number of bytes */
LengthInBytes = (uint32_t)(Length * 4U);
/* Start the DMA channel */
if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL))
{
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (LengthInBytes * 2U);
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
(uint32_t)&tmp_adc_common->CDR2;
hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle);
}
else
{
tmp_hal_status = HAL_ERROR;
};
}
else
{
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmp_adc_common->CDR2, (uint32_t)pData, \
(LengthInBytes * 2U));
}
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hadc);
}
/* Return function status */
return tmp_hal_status;
}
}
/**
* @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration.
* @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
* @retval The converted data values.
*/
uint32_t HAL_ADCEx_MultiModeGetValue_Data32(ADC_HandleTypeDef *hadc)
{
const ADC_Common_TypeDef *tmpADC_Common;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
/* Prevent unused argument(s) compilation warning if no assert_param check */
/* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */
UNUSED(hadc);
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* Return the multi mode conversion value */
return tmpADC_Common->CDR2;
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Get ADC injected group conversion result.
* @note Reading register JDRx automatically clears ADC flag JEOC
* (ADC group injected end of unitary conversion).
* @note This function does not clear ADC flag JEOS
* (ADC group injected end of sequence conversion)
* Occurrence of flag JEOS rising:
* - If sequencer is composed of 1 rank, flag JEOS is equivalent
* to flag JEOC.
* - If sequencer is composed of several ranks, during the scan
* sequence flag JEOC only is raised, at the end of the scan sequence
* both flags JEOC and EOS are raised.
* Flag JEOS must not be cleared by this function because
* it would not be compliant with low power features
* (feature low power auto-wait, not available on all STM32 families).
* To clear this flag, either use function:
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
* model polling: @ref HAL_ADCEx_InjectedPollForConversion()
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
* @param hadc ADC handle
* @param InjectedRank the converted ADC injected rank.
* This parameter can be one of the following values:
* @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
* @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
* @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
* @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
* @retval ADC group injected conversion data
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
{
uint32_t tmp_jdr;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
/* Get ADC converted value */
switch (InjectedRank)
{
case ADC_INJECTED_RANK_4:
tmp_jdr = hadc->Instance->JDR4;
break;
case ADC_INJECTED_RANK_3:
tmp_jdr = hadc->Instance->JDR3;
break;
case ADC_INJECTED_RANK_2:
tmp_jdr = hadc->Instance->JDR2;
break;
case ADC_INJECTED_RANK_1:
default:
tmp_jdr = hadc->Instance->JDR1;
break;
}
return tmp_jdr;
}
/**
* @brief Injected conversion complete callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
*/
}
/**
* @brief Injected context queue overflow callback.
* @note This callback is called if injected context queue is enabled
(parameter "QueueInjectedContext" in injected channel configuration)
and if a new injected context is set when queue is full (maximum 2
contexts).
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
*/
}
/**
* @brief Analog watchdog 2 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
*/
}
/**
* @brief Analog watchdog 3 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
*/
}
/**
* @brief End Of Sampling callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
*/
}
/**
* @brief Stop ADC conversion of regular group (and injected channels in
* case of auto_injection mode), disable ADC peripheral if no
* conversion is on going on injected group.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
/* 1. Stop potential regular conversion on going */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
/* Disable ADC peripheral if regular conversions are effectively stopped
and if no injected conversions are on-going */
if (tmp_hal_status == HAL_OK)
{
/* Clear HAL_ADC_STATE_REG_BUSY bit */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* 2. Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
}
}
/* Conversion on injected group is stopped, but ADC not disabled since */
/* conversion on regular group is still running. */
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
}
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Stop ADC conversion of ADC groups regular and injected,
* disable interrution of end-of-conversion,
* disable ADC peripheral if no conversion is on going
* on injected group.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
/* 1. Stop potential regular conversion on going */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
/* Disable ADC peripheral if conversions are effectively stopped
and if no injected conversion is on-going */
if (tmp_hal_status == HAL_OK)
{
/* Clear HAL_ADC_STATE_REG_BUSY bit */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
/* Disable all regular-related interrupts */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
/* 2. Disable ADC peripheral if no injected conversions are on-going */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
tmp_hal_status = ADC_Disable(hadc);
/* if no issue reported */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
}
}
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
}
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
/**
* @brief Stop ADC conversion of regular group (and injected group in
* case of auto_injection mode), disable ADC DMA transfer, disable
* ADC peripheral if no conversion is on going
* on injected group.
* @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
* For multimode (when multimode feature is available),
* HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
/* 1. Stop potential regular conversion on going */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
/* Disable ADC peripheral if conversions are effectively stopped
and if no injected conversion is on-going */
if (tmp_hal_status == HAL_OK)
{
/* Clear HAL_ADC_STATE_REG_BUSY bit */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
MODIFY_REG(hadc->Instance->CFGR1, ADC_CFGR1_DMNGT_0 | ADC_CFGR1_DMNGT_1, 0UL);
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* while DMA transfer is on going) */
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Check if DMA channel effectively disabled */
if (tmp_hal_status != HAL_OK)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
}
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
/* 2. Disable the ADC peripheral */
/* Update "tmp_hal_status" only if DMA channel disabling passed, */
/* to keep in memory a potential failing status. */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
if (tmp_hal_status == HAL_OK)
{
tmp_hal_status = ADC_Disable(hadc);
}
else
{
(void)ADC_Disable(hadc);
}
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
}
}
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
}
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
* conversion is on-going.
* @note Multimode is kept enabled after this function. Multimode DMA bits
* (MDMA and DMACFG bits of common CCR register) are maintained. To disable
* multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
* reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
* resort to HAL_ADCEx_DisableMultiMode() API.
* @note In case of DMA configured in circular mode, function
* HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
* ADC slave, to properly disable the DMA channel.
* @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
ADC_HandleTypeDef tmp_hadc_slave;
uint32_t tmp_hadc_slave_conversion_on_going;
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
/* 1. Stop potential multimode conversion on going, on regular groups */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
/* Clear HAL_ADC_STATE_REG_BUSY bit */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmp_hadc_slave.Instance == NULL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
/* Procedure to disable the ADC peripheral: wait for conversions */
/* effectively stopped (ADC master and ADC slave), then disable ADC */
/* 1. Wait for ADC conversion completion for ADC master and ADC slave */
tickstart = HAL_GetTick();
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
|| (tmp_hadc_slave_conversion_on_going == 1UL)
)
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
}
/* Disable the DMA channel (in case of DMA in circular mode or stop */
/* while DMA transfer is on going) */
/* Note: DMA channel of ADC slave should be stopped after this function */
/* with HAL_ADCEx_RegularStop_DMA() API. */
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Check if DMA channel effectively disabled */
if (tmp_hal_status != HAL_OK)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
}
/* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
/* 2. Disable the ADC peripherals: master and slave if no injected */
/* conversion is on-going. */
/* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
/* memory a potential failing status. */
if (tmp_hal_status == HAL_OK)
{
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
tmp_hal_status = ADC_Disable(hadc);
if (tmp_hal_status == HAL_OK)
{
if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
{
tmp_hal_status = ADC_Disable(&tmp_hadc_slave);
}
}
}
if (tmp_hal_status == HAL_OK)
{
/* Both Master and Slave ADC's could be disabled. Update Master State */
/* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
}
else
{
/* injected (Master or Slave) conversions are still on-going,
no Master State change */
}
}
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
* @brief ADC Extended Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure channels on injected group
(+) Configure multimode when multimode feature is available
(+) Enable or Disable Injected Queue
(+) Disable ADC voltage regulator
(+) Enter ADC deep-power-down mode
@endverbatim
* @{
*/
/**
* @brief Configure a channel to be assigned to ADC group injected.
* @note Possibility to update parameters on the fly:
* This function initializes injected group, following calls to this
* function can be used to reconfigure some parameters of structure
* "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
* The setting of these parameters is conditioned to ADC state:
* Refer to comments of structure "ADC_InjectionConfTypeDef".
* @note In case of usage of internal measurement channels:
* Vbat/VrefInt/TempSensor.
* These internal paths can be disabled using function
* HAL_ADC_DeInit().
* @note Caution: For Injected Context Queue use, a context must be fully
* defined before start of injected conversion. All channels are configured
* consecutively for the same ADC instance. Therefore, the number of calls to
* HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
* InjectedNbrOfConversion for each context.
* - Example 1: If 1 context is intended to be used (or if there is no use of the
* Injected Queue Context feature) and if the context contains 3 injected ranks
* (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
* called once for each channel (i.e. 3 times) before starting a conversion.
* This function must not be called to configure a 4th injected channel:
* it would start a new context into context queue.
* - Example 2: If 2 contexts are intended to be used and each of them contains
* 3 injected ranks (InjectedNbrOfConversion = 3),
* HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
* for each context (3 channels x 2 contexts = 6 calls). Conversion can
* start once the 1st context is set, that is after the first three
* HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
* @param hadc ADC handle
* @param pConfigInjected Structure of ADC injected group and ADC channel for
* injected group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *pConfigInjected)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_offset_shifted;
uint32_t tmp_config_internal_channel;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
__IO uint32_t wait_loop_index;
uint32_t tmp_jsqr_context_queue_being_built = 0U;
uint32_t tmp_channel;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
assert_param(IS_ADC_EXTTRIGINJEC(pConfigInjected->ExternalTrigInjecConv));
assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
{
assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
}
/* Check offset range according to oversampling setting */
if (hadc->Init.OversamplingMode == ENABLE)
{
assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc),
pConfigInjected->InjectedOffset / (hadc->Init.Oversampling.Ratio + 1U)));
}
else
{
assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
}
/* JDISCEN and JAUTO bits can't be set at the same time */
assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE) \
&& (pConfigInjected->AutoInjectedConv == ENABLE)));
/* DISCEN and JAUTO bits can't be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
/* Verification of channel number */
if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
{
assert_param(IS_ADC_CHANNEL(pConfigInjected->InjectedChannel));
}
else
{
if (hadc->Instance != ADC4) /* ADC1 or ADC2 */
{
#if defined (ADC2)
assert_param(IS_ADC12_DIFF_CHANNEL(pConfigInjected->InjectedChannel));
#else
assert_param(IS_ADC1_DIFF_CHANNEL(pConfigInjected->InjectedChannel));
#endif /* ADC2 */
}
}
__HAL_LOCK(hadc);
/* Configuration of injected group sequencer: */
/* Hardware constraint: Must fully define injected context register JSQR */
/* before make it entering into injected sequencer queue. */
/* */
/* - if scan mode is disabled: */
/* * Injected channels sequence length is set to 0x00: 1 channel */
/* converted (channel on injected rank 1) */
/* Parameter "InjectedNbrOfConversion" is discarded. */
/* * Injected context register JSQR setting is simple: register is fully */
/* defined on one call of this function (for injected rank 1) and can */
/* be entered into queue directly. */
/* - if scan mode is enabled: */
/* * Injected channels sequence length is set to parameter */
/* "InjectedNbrOfConversion". */
/* * Injected context register JSQR setting more complex: register is */
/* fully defined over successive calls of this function, for each */
/* injected channel rank. It is entered into queue only when all */
/* injected ranks have been set. */
/* Note: Scan mode is not present by hardware on this device, but used */
/* by software for alignment over all STM32 devices. */
if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
(pConfigInjected->InjectedNbrOfConversion == 1U))
{
/* Configuration of context register JSQR: */
/* - number of ranks in injected group sequencer: fixed to 1st rank */
/* (scan mode disabled, only rank 1 used) */
/* - external trigger to start conversion */
/* - external trigger polarity */
/* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
{
/* Enable external trigger if trigger selection is different of */
/* software start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
/* software start. */
if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
| (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| pConfigInjected->ExternalTrigInjecConvEdge
);
}
else
{
tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
}
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
/* For debug and informative reasons, hadc handle saves JSQR setting */
hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
}
}
else
{
/* Case of scan mode enabled, several channels to set into injected group */
/* sequencer. */
/* */
/* Procedure to define injected context register JSQR over successive */
/* calls of this function, for each injected channel rank: */
/* 1. Start new context and set parameters related to all injected */
/* channels: injected sequence length and trigger. */
/* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
/* call of the context under setting */
if (hadc->InjectionConfig.ChannelCount == 0U)
{
/* Initialize number of channels that will be configured on the context */
/* being built */
hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
/* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
call, this context will be written in JSQR register at the last call.
At this point, the context is merely reset */
hadc->InjectionConfig.ContextQueue = 0x00000000U;
/* Configuration of context register JSQR: */
/* - number of ranks in injected group sequencer */
/* - external trigger to start conversion */
/* - external trigger polarity */
/* Enable external trigger if trigger selection is different of */
/* software start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
/* software start. */
if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
| (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
| pConfigInjected->ExternalTrigInjecConvEdge
);
}
else
{
tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
}
}
/* 2. Continue setting of context under definition with parameter */
/* related to each channel: channel rank sequence */
/* Clear the old JSQx bits for the selected rank */
tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
/* Set the JSQx bits for the selected rank */
tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
/* Decrease channel count */
hadc->InjectionConfig.ChannelCount--;
/* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
call, aggregate the setting to those already built during the previous
HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */
hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
/* 4. End of context setting: if this is the last channel set, then write context
into register JSQR and make it enter into queue */
if (hadc->InjectionConfig.ChannelCount == 0U)
{
MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
}
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on injected group: */
/* - Injected context queue: Queue disable (active context is kept) or */
/* enable (context decremented, up to 2 contexts queued) */
/* - Injected discontinuous mode: can be enabled only if auto-injected */
/* mode is disabled. */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* ADC channels preselection */
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel) & 0x1FUL));
/* If auto-injected mode is disabled: no constraint */
if (pConfigInjected->AutoInjectedConv == DISABLE)
{
MODIFY_REG(hadc->Instance->CFGR1,
ADC_CFGR1_JDISCEN,
ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
}
/* If auto-injected mode is enabled: Injected discontinuous setting is */
/* discarded. */
else
{
MODIFY_REG(hadc->Instance->CFGR1,
ADC_CFGR1_JDISCEN,
ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
}
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular and injected groups: */
/* - Automatic injected conversion: can be enabled if injected group */
/* external triggers are disabled. */
/* - Channel sampling time */
/* - Channel offset */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
)
{
/* If injected group external triggers are disabled (set to injected */
/* software start): no constraint */
if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
|| (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
{
if (pConfigInjected->AutoInjectedConv == ENABLE)
{
SET_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
}
else
{
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
}
}
/* If Automatic injected conversion was intended to be set and could not */
/* due to injected group external triggers enabled, error is reported. */
else
{
if (pConfigInjected->AutoInjectedConv == ENABLE)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
else
{
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_JAUTO);
}
}
if (pConfigInjected->InjecOversamplingMode == ENABLE)
{
assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
/* JOVSE must be reset in case of triggered regular mode */
assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) ==
(ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
/* Configuration of Injected Oversampler: */
/* - Oversampling Ratio */
/* - Right bit shift */
/* Enable OverSampling mode */
MODIFY_REG(hadc->Instance->CFGR2,
ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS,
ADC_CFGR2_JOVSE | pConfigInjected->InjecOversampling.Ratio |
pConfigInjected->InjecOversampling.RightBitShift
);
}
else
{
/* Disable Regular OverSampling */
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
}
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
pConfigInjected->InjectedSamplingTime);
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
tmp_offset_shifted);
/* Set ADC selected offset sign */
LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign);
/* Set ADC selected offset signed saturation */
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
(pConfigInjected->InjectedOffsetSignedSaturation == ENABLE)
? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE \
: LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
else
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) ==
__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, pConfigInjected->InjectedChannel,
LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) ==
__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, pConfigInjected->InjectedChannel,
LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) ==
__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel,
LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) ==
__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, pConfigInjected->InjectedChannel,
LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
}
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */
/* - Internal measurement channels: Vbat/VrefInt/TempSensor */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
/* Configuration of differential mode */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Set sampling time of the selected ADC channel */
tmp_channel = __LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel) \
+ 1UL) & 0x1FUL);
LL_ADC_SetChannelSamplingTime(hadc->Instance, tmp_channel, pConfigInjected->InjectedSamplingTime);
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
{
/* Configuration of common ADC parameters (continuation) */
/* Software is allowed to change common parameters only when all ADCs */
/* of the common group are disabled. */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
}
else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
{
if (ADC_VREFINT_INSTANCE(hadc))
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
}
}
else
{
/* nothing to do */
}
}
/* If the requested internal measurement path has already been enabled */
/* and other ADC of the common group are enabled, internal */
/* measurement paths cannot be enabled. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
}
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Enable ADC multimode and configure multimode parameters
* @note Possibility to update parameters on the fly:
* This function initializes multimode parameters, following
* calls to this function can be used to reconfigure some parameters
* of structure "ADC_MultiModeTypeDef" on the fly, without resetting
* the ADCs.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_MultiModeTypeDef".
* @note To move back configuration from multimode to single mode, ADC must
* be reset (using function HAL_ADC_Init() ).
* @param hadc Master ADC handle
* @param pMultimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pMultimode)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
ADC_Common_TypeDef *tmp_adc_common;
ADC_HandleTypeDef tmp_hadc_slave;
uint32_t tmp_hadc_slave_conversion_on_going;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
{
assert_param(IS_ADC_DUAL_DATA_MODE(pMultimode->DualModeData));
assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
}
__HAL_LOCK(hadc);
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
if (tmp_hadc_slave.Instance == NULL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
__HAL_UNLOCK(hadc);
return HAL_ERROR;
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
&& (tmp_hadc_slave_conversion_on_going == 0UL))
{
/* Pointer to the common control register */
tmp_adc_common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* If multimode is selected, configure all pMultimode parameters. */
/* Otherwise, reset pMultimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
{
MODIFY_REG(tmp_adc_common->CCR, ADC_CCR_DAMDF, pMultimode->DualModeData);
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
/* Note: Delay range depends on selected resolution: */
/* from 1 to 12 clock cycles for 12 bits */
/* from 1 to 10 clock cycles for 10 bits, */
/* from 1 to 8 clock cycles for 8 bits */
/* from 1 to 6 clock cycles for 6 bits */
/* If a higher delay is selected, it will be clipped to maximum delay */
/* range */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
{
MODIFY_REG(tmp_adc_common->CCR, (ADC_CCR_DUAL | ADC_CCR_DELAY), \
(pMultimode->Mode | pMultimode->TwoSamplingDelay));
}
}
else /* ADC_MODE_INDEPENDENT */
{
CLEAR_BIT(tmp_adc_common->CCR, ADC_CCR_DAMDF);
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
{
CLEAR_BIT(tmp_adc_common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
}
}
}
/* If one of the ADC sharing the same common group is enabled, no update */
/* could be done on neither of the multimode structure parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
tmp_hal_status = HAL_ERROR;
}
__HAL_UNLOCK(hadc);
return tmp_hal_status;
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Disable ADC voltage regulator.
* @note Disabling voltage regulator allows to save power. This operation can
* be carried out only when ADC is disabled.
* @note To enable again the voltage regulator, the user is expected to
* resort to HAL_ADC_Init() API.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
LL_ADC_DisableInternalRegulator(hadc->Instance);
tmp_hal_status = HAL_OK;
}
else
{
tmp_hal_status = HAL_ERROR;
}
return tmp_hal_status;
}
/**
* @brief Enter ADC deep-power-down mode
* @note This mode is achieved in setting DEEPPWD bit and allows to save power
* in reducing leakage currents. It is particularly interesting before
* entering stop modes.
* @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the
* ADC voltage regulator. This means that this API encompasses
* HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
* calibration is lost.
* @note To exit the ADC deep-power-down mode, the user is expected to
* resort to HAL_ADC_Init() API as well as to relaunch a calibration
* with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
* saved calibration factor.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
{
HAL_StatusTypeDef tmp_hal_status;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
LL_ADC_EnableDeepPowerDown(hadc->Instance);
tmp_hal_status = HAL_OK;
}
else
{
tmp_hal_status = HAL_ERROR;
}
return tmp_hal_status;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c
|
C
|
apache-2.0
| 102,160
|
/**
******************************************************************************
* @file stm32u5xx_hal_comp.c
* @author MCD Application Team
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
* + Initialization and de-initialization functions
* + Start/Stop operation functions in polling mode
* + Start/Stop operation functions in interrupt mode (through EXTI interrupt)
* + Peripheral control functions
* + Peripheral state functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### COMP Peripheral features #####
==============================================================================
[..]
The STM32U5xx device family integrates two analog comparators instances:
COMP1, COMP2.
(#) Comparators input minus (inverting input) and input plus (non inverting input)
can be set to internal references or to GPIO pins
(refer to GPIO list in reference manual).
(#) Comparators output level is available using HAL_COMP_GetOutputLevel()
and can be redirected to other peripherals: GPIO pins (in mode
alternate functions for comparator), timers.
(refer to GPIO list in reference manual).
(#) The comparators have interrupt capability through the EXTI controller
with wake-up from sleep and stop modes:
(++) COMP1 is internally connected to EXTI Line 20
(++) COMP2 is internally connected to EXTI Line 21
(#) Pairs of comparators instances can be combined in window mode
(2 consecutive instances odd and even COMP<x> and COMP<x+1>).
From the corresponding IRQ handler, the right interrupt source can be retrieved
using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions to configure and program the comparator instances
of STM32U5xx devices.
To use the comparator, perform the following steps:
(#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
(++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
using HAL_GPIO_Init().
(++) If needed, configure the GPIO connected to comparator output in alternate function mode
using HAL_GPIO_Init().
(++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
interrupt vector using HAL_NVIC_EnableIRQ() function.
(#) Configure the comparator using HAL_COMP_Init() function:
(++) Select the input minus (inverting input)
(++) Select the input plus (non-inverting input)
(++) Select the hysteresis
(++) Select the blanking source
(++) Select the output polarity
(++) Select the power mode
(++) Select the window mode
-@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
to enable internal control clock of the comparators.
However, this is a legacy strategy. In future STM32 families,
COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
Therefore, for compatibility anticipation, it is recommended to
implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
(#) Reconfiguration on-the-fly of comparator can be done by calling again
function HAL_COMP_Init() with new input structure parameters values.
(#) Enable the comparator using HAL_COMP_Start() function.
(#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
to manage comparator outputs (events and output level).
(#) Disable the comparator using HAL_COMP_Stop() function.
(#) De-initialize the comparator using HAL_COMP_DeInit() function.
(#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
The only way to unlock the comparator is a device hardware reset.
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_COMP_RegisterCallback()
to register an interrupt callback.
[..]
Function HAL_COMP_RegisterCallback() allows to register following callbacks:
(+) TriggerCallback : callback for COMP trigger.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
weak function.
[..]
HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TriggerCallback : callback for COMP trigger.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
all callbacks are set to the corresponding weak functions:
example HAL_COMP_TriggerCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
or HAL_COMP_Init() function.
[..]
When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_COMP_MODULE_ENABLED
#if defined (COMP1) || defined (COMP2)
/** @defgroup COMP COMP
* @brief COMP HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup COMP_Private_Constants
* @{
*/
/* Delay for COMP startup time. */
/* Note: Delay required to reach propagation delay specification. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */
/* Delay for COMP voltage scaler stabilization time. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART_SCALER"). */
/* Unit: us */
#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL) /*!< Delay for COMP voltage scaler stabilization time */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup COMP_Exported_Functions COMP Exported Functions
* @{
*/
/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and de-initialization functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions to initialize and de-initialize comparators
@endverbatim
* @{
*/
/**
* @brief Initialize the COMP according to the specified
* parameters in the COMP_InitTypeDef and initialize the associated handle.
* @note If the selected comparator is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
uint32_t tmp_csr;
uint32_t exti_line;
uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */
__IO uint32_t wait_loop_index = 0UL;
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if (hcomp == NULL)
{
status = HAL_ERROR;
}
else if (__HAL_COMP_IS_LOCKED(hcomp))
{
status = HAL_ERROR;
}
else
{
/* Check the parameters */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.InputPlus));
assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InputMinus));
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
assert_param(IS_COMP_WINDOWMODE(hcomp->Instance, hcomp->Init.WindowMode));
if (hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE)
{
assert_param(IS_COMP_WINDOWOUTPUT(hcomp->Init.WindowOutput));
}
if (hcomp->State == HAL_COMP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcomp->Lock = HAL_UNLOCKED;
/* Set COMP error code to none */
COMP_CLEAR_ERRORCODE(hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Init the COMP Callback settings */
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
if (hcomp->MspInitCallback == NULL)
{
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
/* Note: Internal control clock of the comparators must */
/* be enabled in "HAL_COMP_MspInit()" */
/* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */
hcomp->MspInitCallback(hcomp);
#else
/* Init the low level hardware */
/* Note: Internal control clock of the comparators must */
/* be enabled in "HAL_COMP_MspInit()" */
/* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */
HAL_COMP_MspInit(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
/* Memorize voltage scaler state before initialization */
comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0));
/* Set COMP parameters */
tmp_csr = (hcomp->Init.InputMinus
| hcomp->Init.InputPlus
| hcomp->Init.BlankingSrce
| hcomp->Init.Hysteresis
| hcomp->Init.OutputPol
| hcomp->Init.Mode
);
/* Set parameters in COMP register */
/* Note: Update all bits except read-only, lock and enable bits */
MODIFY_REG(hcomp->Instance->CSR,
COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL |
COMP_CSR_WINMODE | COMP_CSR_POLARITY | COMP_CSR_HYST |
COMP_CSR_BLANKSEL,
tmp_csr
);
/* Set window mode */
/* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */
/* instances. Therefore, this function can update another COMP */
/* instance that the one currently selected. */
if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
{
CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
}
else if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON)
{
SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
}
else
{
CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE);
CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE);
}
/* Set window mode output */
/* Note: Window mode mode output can also be used when window mode */
/* is disabled, to use comparators in independent mode with their */
/* output connected through exclusive-or circuitry. */
switch (hcomp->Init.WindowOutput)
{
case COMP_WINDOWOUTPUT_COMP1:
SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
break;
case COMP_WINDOWOUTPUT_COMP2:
CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
break;
case COMP_WINDOWOUTPUT_BOTH:
SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
break;
default: /* COMP_WINDOWOUTPUT_EACH_COMP */
CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT);
CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT);
break;
}
/* Delay for COMP scaler bridge voltage stabilization */
/* Apply the delay if voltage scaler bridge is required and not already enabled */
if ((READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)) != 0UL) &&
(comp_voltage_scaler_initialized == 0UL))
{
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
/* Get the EXTI line corresponding to the selected COMP instance */
exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
/* Manage EXTI settings */
if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
{
/* Configure EXTI rising edge */
if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
{
SET_BIT(EXTI->RTSR1, exti_line);
}
else
{
CLEAR_BIT(EXTI->RTSR1, exti_line);
}
/* Configure EXTI falling edge */
if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
{
SET_BIT(EXTI->FTSR1, exti_line);
}
else
{
CLEAR_BIT(EXTI->FTSR1, exti_line);
}
/* Clear COMP EXTI pending bit (if any) */
WRITE_REG(EXTI->RPR1, exti_line);
WRITE_REG(EXTI->FPR1, exti_line);
/* Configure EXTI event mode */
if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
{
SET_BIT(EXTI->EMR1, exti_line);
}
else
{
CLEAR_BIT(EXTI->EMR1, exti_line);
}
/* Configure EXTI interrupt mode */
if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
{
SET_BIT(EXTI->IMR1, exti_line);
}
else
{
CLEAR_BIT(EXTI->IMR1, exti_line);
}
}
else
{
/* Disable EXTI event mode */
CLEAR_BIT(EXTI->EMR1, exti_line);
/* Disable EXTI interrupt mode */
CLEAR_BIT(EXTI->IMR1, exti_line);
}
/* Set HAL COMP handle state */
/* Note: Transition from state reset to state ready, */
/* otherwise (coming from state ready or busy) no state update. */
if (hcomp->State == HAL_COMP_STATE_RESET)
{
hcomp->State = HAL_COMP_STATE_READY;
}
}
return status;
}
/**
* @brief DeInitialize the COMP peripheral.
* @note Deinitialization cannot be performed if the COMP configuration is locked.
* To unlock the configuration, perform a system reset.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if (hcomp == NULL)
{
status = HAL_ERROR;
}
else if (__HAL_COMP_IS_LOCKED(hcomp))
{
status = HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
/* Set COMP_CSR register to reset value */
WRITE_REG(hcomp->Instance->CSR, 0x00000000UL);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
if (hcomp->MspDeInitCallback == NULL)
{
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: GPIO, RCC clock, NVIC */
hcomp->MspDeInitCallback(hcomp);
#else
/* DeInit the low level hardware: GPIO, RCC clock, NVIC */
HAL_COMP_MspDeInit(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/* Set HAL COMP handle state */
hcomp->State = HAL_COMP_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hcomp);
}
return status;
}
/**
* @brief Initialize the COMP MSP.
* @param hcomp COMP handle
* @retval None
*/
__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcomp);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_COMP_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the COMP MSP.
* @param hcomp COMP handle
* @retval None
*/
__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcomp);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_COMP_MspDeInit could be implemented in the user file
*/
}
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User COMP Callback
* To be used instead of the weak predefined callback
* @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
* the configuration information for the specified COMP.
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
* @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
pCOMP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (HAL_COMP_STATE_READY == hcomp->State)
{
switch (CallbackID)
{
case HAL_COMP_TRIGGER_CB_ID :
hcomp->TriggerCallback = pCallback;
break;
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = pCallback;
break;
case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_COMP_STATE_RESET == hcomp->State)
{
switch (CallbackID)
{
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = pCallback;
break;
case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a COMP Callback
* COMP callback is redirected to the weak predefined callback
* @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
* the configuration information for the specified COMP.
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
* @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (HAL_COMP_STATE_READY == hcomp->State)
{
switch (CallbackID)
{
case HAL_COMP_TRIGGER_CB_ID :
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
break;
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
break;
case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_COMP_STATE_RESET == hcomp->State)
{
switch (CallbackID)
{
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
break;
case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
* @brief Start-Stop operation functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start a comparator instance.
(+) Stop a comparator instance.
@endverbatim
* @{
*/
/**
* @brief Start the comparator.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{
__IO uint32_t wait_loop_index = 0UL;
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if (hcomp == NULL)
{
status = HAL_ERROR;
}
else if (__HAL_COMP_IS_LOCKED(hcomp))
{
status = HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
if (hcomp->State == HAL_COMP_STATE_READY)
{
/* Enable the selected comparator */
SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
/* Set HAL COMP handle state */
hcomp->State = HAL_COMP_STATE_BUSY;
/* Delay for COMP startup time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while (wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
else
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Stop the comparator.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if (hcomp == NULL)
{
status = HAL_ERROR;
}
else if (__HAL_COMP_IS_LOCKED(hcomp))
{
status = HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
/* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */
/* (all states except HAL_COMP_STATE_RESET and except locked status. */
if (hcomp->State != HAL_COMP_STATE_RESET)
{
/* Disable the selected comparator */
CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
/* Set HAL COMP handle state */
hcomp->State = HAL_COMP_STATE_READY;
}
else
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Comparator IRQ handler.
* @param hcomp COMP handle
* @retval None
*/
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
{
/* Get the EXTI line corresponding to the selected COMP instance */
uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
/* Check COMP EXTI flag */
if (READ_BIT(EXTI->RPR1, exti_line) != 0UL)
{
/* Check whether comparator is in independent or window mode */
if (READ_BIT(hcomp->Instance->CSR, COMP_CSR_WINMODE) != 0UL)
{
/* Clear COMP EXTI line pending bit of the pair of comparators */
/* in window mode. */
/* Note: Pair of comparators in window mode can both trig IRQ when */
/* input voltage is changing from "out of window" area */
/* (low or high ) to the other "out of window" area (high or low).*/
/* Both flags must be cleared to call comparator trigger */
/* callback is called once. */
WRITE_REG(EXTI->RPR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI->RPR1, exti_line);
}
/* COMP trigger user callback */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
hcomp->TriggerCallback(hcomp);
#else
HAL_COMP_TriggerCallback(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
else if (READ_BIT(EXTI->FPR1, exti_line) != 0UL)
{
/* Check whether comparator is in independent or window mode */
if (READ_BIT(hcomp->Instance->CSR, COMP_CSR_WINMODE) != 0UL)
{
/* Clear COMP EXTI line pending bit of the pair of comparators */
/* in window mode. */
/* Note: Pair of comparators in window mode can both trig IRQ when */
/* input voltage is changing from "out of window" area */
/* (low or high ) to the other "out of window" area (high or low).*/
/* Both flags must be cleared to call comparator trigger */
/* callback is called once. */
WRITE_REG(EXTI->FPR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI->FPR1, exti_line);
}
/* COMP trigger user callback */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
hcomp->TriggerCallback(hcomp);
#else
HAL_COMP_TriggerCallback(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
else
{
/* nothing to do */
}
}
/**
* @}
*/
/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
* @brief Management functions.
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the comparators.
@endverbatim
* @{
*/
/**
* @brief Lock the selected comparator configuration.
* @note A system reset is required to unlock the comparator configuration.
* @note Locking the comparator from reset state is possible
* if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if (hcomp == NULL)
{
status = HAL_ERROR;
}
else if (__HAL_COMP_IS_LOCKED(hcomp))
{
status = HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
/* Set HAL COMP handle state */
switch (hcomp->State)
{
case HAL_COMP_STATE_RESET:
hcomp->State = HAL_COMP_STATE_RESET_LOCKED;
break;
case HAL_COMP_STATE_READY:
hcomp->State = HAL_COMP_STATE_READY_LOCKED;
break;
default: /* HAL_COMP_STATE_BUSY */
hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
break;
}
/* Set the lock bit corresponding to selected comparator */
__HAL_COMP_LOCK(hcomp);
}
return status;
}
/**
* @brief Return the output level (high or low) of the selected comparator.
* The output level depends on the selected polarity.
* If the polarity is not inverted:
* - Comparator output is low when the input plus is at a lower
* voltage than the input minus
* - Comparator output is high when the input plus is at a higher
* voltage than the input minus
* If the polarity is inverted:
* - Comparator output is high when the input plus is at a lower
* voltage than the input minus
* - Comparator output is low when the input plus is at a higher
* voltage than the input minus
* @param hcomp COMP handle
* @retval Returns the selected comparator output level:
* @arg COMP_OUTPUT_LEVEL_LOW
* @arg COMP_OUTPUT_LEVEL_HIGH
*
*/
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
return (uint32_t)((READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE)) >> COMP_CSR_VALUE_Pos);
}
/**
* @brief Comparator trigger callback.
* @param hcomp COMP handle
* @retval None
*/
__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcomp);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_COMP_TriggerCallback should be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the COMP handle state.
* @param hcomp COMP handle
* @retval HAL state
*/
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
{
/* Check the COMP handle allocation */
if (hcomp == NULL)
{
return HAL_COMP_STATE_RESET;
}
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
/* Return HAL COMP handle state */
return hcomp->State;
}
/**
* @brief Return the COMP error code.
* @param hcomp COMP handle
* @retval COMP error code
*/
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
return hcomp->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* COMP1 || COMP2 */
#endif /* HAL_COMP_MODULE_ENABLED */
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_comp.c
|
C
|
apache-2.0
| 34,664
|
/**
******************************************************************************
* @file stm32u5xx_hal_cordic.c
* @author MCD Application Team
* @brief CORDIC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORDIC peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
* + Callback functions
* + IRQ handler management
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
================================================================================
##### How to use this driver #####
================================================================================
[..]
The CORDIC HAL driver can be used as follows:
(#) Initialize the CORDIC low level resources by implementing the HAL_CORDIC_MspInit():
(++) Enable the CORDIC interface clock using __HAL_RCC_CORDIC_CLK_ENABLE()
(++) In case of using interrupts (e.g. HAL_CORDIC_Calculate_IT())
(+++) Configure the CORDIC interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CORDIC IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In CORDIC IRQ handler, call HAL_CORDIC_IRQHandler()
(++) In case of using DMA to control data transfer (e.g. HAL_CORDIC_Calculate_DMA())
(+++) Enable the DMA2 interface clock using
__HAL_RCC_DMA2_CLK_ENABLE()
(+++) Configure and enable two DMA channels one for managing data transfer from
memory to peripheral (input channel) and another channel for managing data
transfer from peripheral to memory (output channel)
(+++) Associate the initialized DMA handle to the CORDIC DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA channels.
Resort to HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
(#) Initialize the CORDIC HAL using HAL_CORDIC_Init(). This function
(++) resorts to HAL_CORDIC_MspInit() for low-level initialization,
(#) Configure CORDIC processing (calculation) using HAL_CORDIC_Configure().
This function configures:
(++) Processing functions: Cosine, Sine, Phase, Modulus, Arctangent,
Hyperbolic cosine, Hyperbolic sine, Hyperbolic arctangent,
Natural log, Square root
(++) Scaling factor: 1 to 2exp(-7)
(++) Width of input data: 32 bits input data size (Q1.31 format) or 16 bits
input data size (Q1.15 format)
(++) Width of output data: 32 bits output data size (Q1.31 format) or 16 bits
output data size (Q1.15 format)
(++) Number of 32-bit write expected for one calculation: One 32-bits write
or Two 32-bit write
(++) Number of 32-bit read expected after one calculation: One 32-bits read
or Two 32-bit read
(++) Precision: 1 to 15 cycles for calculation (the more cycles, the better precision)
(#) Four processing (calculation) functions are available:
(++) Polling mode: processing API is blocking function
i.e. it processes the data and wait till the processing is finished
API is HAL_CORDIC_Calculate
(++) Polling Zero-overhead mode: processing API is blocking function
i.e. it processes the data and wait till the processing is finished
A bit faster than standard polling mode, but blocking also AHB bus
API is HAL_CORDIC_CalculateZO
(++) Interrupt mode: processing API is not blocking functions
i.e. it processes the data under interrupt
API is HAL_CORDIC_Calculate_IT
(++) DMA mode: processing API is not blocking functions and the CPU is
not used for data transfer,
i.e. the data transfer is ensured by DMA
API is HAL_CORDIC_Calculate_DMA
(#) Call HAL_CORDIC_DeInit() to de-initialize the CORDIC peripheral. This function
(++) resorts to HAL_CORDIC_MspDeInit() for low-level de-initialization,
*** Callback registration ***
=============================================
The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function HAL_CORDIC_RegisterCallback() to register an interrupt callback.
Function HAL_CORDIC_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : Error Callback.
(+) CalculateCpltCallback : Calculate complete Callback.
(+) MspInitCallback : CORDIC MspInit.
(+) MspDeInitCallback : CORDIC MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
weak function.
HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : Error Callback.
(+) CalculateCpltCallback : Calculate complete Callback.
(+) MspInitCallback : CORDIC MspInit.
(+) MspDeInitCallback : CORDIC MspDeInit.
By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET,
all callbacks are set to the corresponding weak functions:
examples HAL_CORDIC_ErrorCallback(), HAL_CORDIC_CalculateCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak function in the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() only when
these callbacks are null (not registered beforehand).
if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_CORDIC_RegisterCallback() before calling HAL_CORDIC_DeInit()
or HAL_CORDIC_Init() function.
When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
#if defined(CORDIC)
#ifdef HAL_CORDIC_MODULE_ENABLED
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup CORDIC CORDIC
* @brief CORDIC HAL driver modules.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CORDIC_Private_Functions CORDIC Private Functions
* @{
*/
static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff);
static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff);
static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma);
static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma);
static void CORDIC_DMAError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions
* @{
*/
/** @defgroup CORDIC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize the CORDIC peripheral and the associated handle
(+) DeInitialize the CORDIC peripheral
(+) Initialize the CORDIC MSP (MCU Specific Package)
(+) De-Initialize the CORDIC MSP
[..]
@endverbatim
* @{
*/
/**
* @brief Initialize the CORDIC peripheral and the associated handle.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic)
{
/* Check the CORDIC handle allocation */
if (hcordic == NULL)
{
/* Return error status */
return HAL_ERROR;
}
/* Check the instance */
assert_param(IS_CORDIC_ALL_INSTANCE(hcordic->Instance));
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
if (hcordic->State == HAL_CORDIC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcordic->Lock = HAL_UNLOCKED;
/* Reset callbacks to legacy functions */
hcordic->ErrorCallback = HAL_CORDIC_ErrorCallback; /* Legacy weak ErrorCallback */
hcordic->CalculateCpltCallback = HAL_CORDIC_CalculateCpltCallback; /* Legacy weak CalculateCpltCallback */
if (hcordic->MspInitCallback == NULL)
{
hcordic->MspInitCallback = HAL_CORDIC_MspInit; /* Legacy weak MspInit */
}
/* Initialize the low level hardware */
hcordic->MspInitCallback(hcordic);
}
#else
if (hcordic->State == HAL_CORDIC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcordic->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware */
HAL_CORDIC_MspInit(hcordic);
}
#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
/* Set CORDIC error code to none */
hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
/* Reset pInBuff and pOutBuff */
hcordic->pInBuff = NULL;
hcordic->pOutBuff = NULL;
/* Reset NbCalcToOrder and NbCalcToGet */
hcordic->NbCalcToOrder = 0U;
hcordic->NbCalcToGet = 0U;
/* Reset DMADirection */
hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
/* Change CORDIC peripheral state */
hcordic->State = HAL_CORDIC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the CORDIC peripheral.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic)
{
/* Check the CORDIC handle allocation */
if (hcordic == NULL)
{
/* Return error status */
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CORDIC_ALL_INSTANCE(hcordic->Instance));
/* Change CORDIC peripheral state */
hcordic->State = HAL_CORDIC_STATE_BUSY;
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
if (hcordic->MspDeInitCallback == NULL)
{
hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
}
/* De-Initialize the low level hardware */
hcordic->MspDeInitCallback(hcordic);
#else
/* De-Initialize the low level hardware: CLOCK, NVIC, DMA */
HAL_CORDIC_MspDeInit(hcordic);
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
/* Set CORDIC error code to none */
hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
/* Reset pInBuff and pOutBuff */
hcordic->pInBuff = NULL;
hcordic->pOutBuff = NULL;
/* Reset NbCalcToOrder and NbCalcToGet */
hcordic->NbCalcToOrder = 0U;
hcordic->NbCalcToGet = 0U;
/* Reset DMADirection */
hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
/* Change CORDIC peripheral state */
hcordic->State = HAL_CORDIC_STATE_RESET;
/* Reset Lock */
hcordic->Lock = HAL_UNLOCKED;
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the CORDIC MSP.
* @param hcordic CORDIC handle
* @retval None
*/
__weak void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcordic);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CORDIC_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the CORDIC MSP.
* @param hcordic CORDIC handle
* @retval None
*/
__weak void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcordic);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CORDIC_MspDeInit can be implemented in the user file
*/
}
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
/**
* @brief Register a CORDIC CallBack.
* To be used instead of the weak predefined callback.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_CORDIC_ERROR_CB_ID error Callback ID
* @arg @ref HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID
* @arg @ref HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
void (* pCallback)(CORDIC_HandleTypeDef *_hcordic))
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
/* Return error status */
return HAL_ERROR;
}
if (hcordic->State == HAL_CORDIC_STATE_READY)
{
switch (CallbackID)
{
case HAL_CORDIC_ERROR_CB_ID :
hcordic->ErrorCallback = pCallback;
break;
case HAL_CORDIC_CALCULATE_CPLT_CB_ID :
hcordic->CalculateCpltCallback = pCallback;
break;
case HAL_CORDIC_MSPINIT_CB_ID :
hcordic->MspInitCallback = pCallback;
break;
case HAL_CORDIC_MSPDEINIT_CB_ID :
hcordic->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hcordic->State == HAL_CORDIC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_CORDIC_MSPINIT_CB_ID :
hcordic->MspInitCallback = pCallback;
break;
case HAL_CORDIC_MSPDEINIT_CB_ID :
hcordic->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
/**
* @brief Unregister a CORDIC CallBack.
* CORDIC callback is redirected to the weak predefined callback.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_CORDIC_ERROR_CB_ID error Callback ID
* @arg @ref HAL_CORDIC_CALCULATE_CPLT_CB_ID calculate complete Callback ID
* @arg @ref HAL_CORDIC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CORDIC_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (hcordic->State == HAL_CORDIC_STATE_READY)
{
switch (CallbackID)
{
case HAL_CORDIC_ERROR_CB_ID :
hcordic->ErrorCallback = HAL_CORDIC_ErrorCallback;
break;
case HAL_CORDIC_CALCULATE_CPLT_CB_ID :
hcordic->CalculateCpltCallback = HAL_CORDIC_CalculateCpltCallback;
break;
case HAL_CORDIC_MSPINIT_CB_ID :
hcordic->MspInitCallback = HAL_CORDIC_MspInit;
break;
case HAL_CORDIC_MSPDEINIT_CB_ID :
hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
break;
default :
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hcordic->State == HAL_CORDIC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_CORDIC_MSPINIT_CB_ID :
hcordic->MspInitCallback = HAL_CORDIC_MspInit;
break;
case HAL_CORDIC_MSPDEINIT_CB_ID :
hcordic->MspDeInitCallback = HAL_CORDIC_MspDeInit;
break;
default :
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup CORDIC_Exported_Functions_Group2 Peripheral Control functions
* @brief Control functions.
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Configure the CORDIC peripheral: function, precision, scaling factor,
number of input data and output data, size of input data and output data.
(+) Calculate output data of CORDIC processing on input date, using the
existing CORDIC configuration
[..] Four processing functions are available for calculation:
(+) Polling mode
(+) Polling mode, with Zero-Overhead register access
(+) Interrupt mode
(+) DMA mode
@endverbatim
* @{
*/
/**
* @brief Configure the CORDIC processing according to the specified
parameters in the CORDIC_ConfigTypeDef structure.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module
* @param sConfig pointer to a CORDIC_ConfigTypeDef structure that
* contains the CORDIC configuration information.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_CORDIC_FUNCTION(sConfig->Function));
assert_param(IS_CORDIC_PRECISION(sConfig->Precision));
assert_param(IS_CORDIC_SCALE(sConfig->Scale));
assert_param(IS_CORDIC_NBWRITE(sConfig->NbWrite));
assert_param(IS_CORDIC_NBREAD(sConfig->NbRead));
assert_param(IS_CORDIC_INSIZE(sConfig->InSize));
assert_param(IS_CORDIC_OUTSIZE(sConfig->OutSize));
/* Check handle state is ready */
if (hcordic->State == HAL_CORDIC_STATE_READY)
{
/* Apply all configuration parameters in CORDIC control register */
MODIFY_REG(hcordic->Instance->CSR, \
(CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE | \
CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE), \
(sConfig->Function | sConfig->Precision | sConfig->Scale | \
sConfig->NbWrite | sConfig->NbRead | sConfig->InSize | sConfig->OutSize));
}
else
{
/* Set CORDIC error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
/* Return error status */
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @brief Carry out data of CORDIC processing in polling mode,
* according to the existing CORDIC configuration.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module.
* @param pInBuff Pointer to buffer containing input data for CORDIC processing.
* @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
* @param NbCalc Number of CORDIC calculation to process.
* @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t index;
int32_t *p_tmp_in_buff = pInBuff;
int32_t *p_tmp_out_buff = pOutBuff;
/* Check parameters setting */
if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
/* Return error status */
return HAL_ERROR;
}
/* Check handle state is ready */
if (hcordic->State == HAL_CORDIC_STATE_READY)
{
/* Reset CORDIC error code */
hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
/* Change the CORDIC state */
hcordic->State = HAL_CORDIC_STATE_BUSY;
/* Get tick */
tickstart = HAL_GetTick();
/* Write of input data in Write Data register, and increment input buffer pointer */
CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
/* Calculation is started.
Provide next set of input data, until number of calculation is achieved */
for (index = (NbCalc - 1U); index > 0U; index--)
{
/* Write of input data in Write Data register, and increment input buffer pointer */
CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
/* Wait for RRDY flag to be raised */
do
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if ((HAL_GetTick() - tickstart) > Timeout)
{
/* Set CORDIC error code */
hcordic->ErrorCode = HAL_CORDIC_ERROR_TIMEOUT;
/* Change the CORDIC state */
hcordic->State = HAL_CORDIC_STATE_READY;
/* Return function status */
return HAL_ERROR;
}
}
} while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY));
/* Read output data from Read Data register, and increment output buffer pointer */
CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
}
/* Read output data from Read Data register, and increment output buffer pointer */
CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
/* Change the CORDIC state */
hcordic->State = HAL_CORDIC_STATE_READY;
/* Return function status */
return HAL_OK;
}
else
{
/* Set CORDIC error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
/* Return function status */
return HAL_ERROR;
}
}
/**
* @brief Carry out data of CORDIC processing in Zero-Overhead mode (output data being read
* soon as input data are written), according to the existing CORDIC configuration.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module.
* @param pInBuff Pointer to buffer containing input data for CORDIC processing.
* @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
* @param NbCalc Number of CORDIC calculation to process.
* @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t index;
int32_t *p_tmp_in_buff = pInBuff;
int32_t *p_tmp_out_buff = pOutBuff;
/* Check parameters setting */
if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
/* Return error status */
return HAL_ERROR;
}
/* Check handle state is ready */
if (hcordic->State == HAL_CORDIC_STATE_READY)
{
/* Reset CORDIC error code */
hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
/* Change the CORDIC state */
hcordic->State = HAL_CORDIC_STATE_BUSY;
/* Get tick */
tickstart = HAL_GetTick();
/* Write of input data in Write Data register, and increment input buffer pointer */
CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
/* Calculation is started.
Provide next set of input data, until number of calculation is achieved */
for (index = (NbCalc - 1U); index > 0U; index--)
{
/* Write of input data in Write Data register, and increment input buffer pointer */
CORDIC_WriteInDataIncrementPtr(hcordic, &p_tmp_in_buff);
/* Read output data from Read Data register, and increment output buffer pointer
The reading is performed in Zero-Overhead mode:
reading is ordered immediately without waiting result ready flag */
CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if ((HAL_GetTick() - tickstart) > Timeout)
{
/* Set CORDIC error code */
hcordic->ErrorCode = HAL_CORDIC_ERROR_TIMEOUT;
/* Change the CORDIC state */
hcordic->State = HAL_CORDIC_STATE_READY;
/* Return function status */
return HAL_ERROR;
}
}
}
/* Read output data from Read Data register, and increment output buffer pointer
The reading is performed in Zero-Overhead mode:
reading is ordered immediately without waiting result ready flag */
CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff);
/* Change the CORDIC state */
hcordic->State = HAL_CORDIC_STATE_READY;
/* Return function status */
return HAL_OK;
}
else
{
/* Set CORDIC error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
/* Return function status */
return HAL_ERROR;
}
}
/**
* @brief Carry out data of CORDIC processing in interrupt mode,
* according to the existing CORDIC configuration.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module.
* @param pInBuff Pointer to buffer containing input data for CORDIC processing.
* @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
* @param NbCalc Number of CORDIC calculation to process.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc)
{
int32_t *tmp_pInBuff = pInBuff;
/* Check parameters setting */
if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
/* Return error status */
return HAL_ERROR;
}
/* Check handle state is ready */
if (hcordic->State == HAL_CORDIC_STATE_READY)
{
/* Reset CORDIC error code */
hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
/* Change the CORDIC state */
hcordic->State = HAL_CORDIC_STATE_BUSY;
/* Store the buffers addresses and number of calculations in handle,
provisioning initial write of input data that will be done */
if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
{
/* Two writes of input data are expected */
tmp_pInBuff++;
tmp_pInBuff++;
}
else
{
/* One write of input data is expected */
tmp_pInBuff++;
}
hcordic->pInBuff = tmp_pInBuff;
hcordic->pOutBuff = pOutBuff;
hcordic->NbCalcToOrder = NbCalc - 1U;
hcordic->NbCalcToGet = NbCalc;
/* Enable Result Ready Interrupt */
__HAL_CORDIC_ENABLE_IT(hcordic, CORDIC_IT_IEN);
/* Set back pointer to start of input data buffer */
tmp_pInBuff = pInBuff;
/* Initiate the processing by providing input data
in the Write Data register */
WRITE_REG(hcordic->Instance->WDATA, (uint32_t)*tmp_pInBuff);
/* Check if second write of input data is expected */
if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
{
/* Increment pointer to input data */
tmp_pInBuff++;
/* Perform second write of input data */
WRITE_REG(hcordic->Instance->WDATA, (uint32_t)*tmp_pInBuff);
}
/* Return function status */
return HAL_OK;
}
else
{
/* Set CORDIC error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
/* Return function status */
return HAL_ERROR;
}
}
/**
* @brief Carry out input and/or output data of CORDIC processing in DMA mode,
* according to the existing CORDIC configuration.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module.
* @param pInBuff Pointer to buffer containing input data for CORDIC processing.
* @param pOutBuff Pointer to buffer where output data of CORDIC processing will be stored.
* @param NbCalc Number of CORDIC calculation to process.
* @param DMADirection Direction of DMA transfers.
* This parameter can be one of the following values:
* @arg @ref CORDIC_DMA_Direction CORDIC DMA direction
* @note pInBuff or pOutBuff is unused in case of unique DMADirection transfer, and can
* be set to NULL value in this case.
* @note pInBuff and pOutBuff buffers must be 32-bit aligned to ensure a correct
* DMA transfer to and from the Peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t DMADirection)
{
HAL_StatusTypeDef status;
uint32_t sizeinbuff;
uint32_t sizeoutbuff;
uint32_t inputaddr;
uint32_t outputaddr;
/* Check the parameters */
assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection));
/* Check parameters setting */
if (NbCalc == 0U)
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
/* Return error status */
return HAL_ERROR;
}
/* Check if CORDIC DMA direction "Out" is requested */
if ((DMADirection == CORDIC_DMA_DIR_OUT) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
{
/* Check parameters setting */
if (pOutBuff == NULL)
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
/* Return error status */
return HAL_ERROR;
}
}
/* Check if CORDIC DMA direction "In" is requested */
if ((DMADirection == CORDIC_DMA_DIR_IN) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
{
/* Check parameters setting */
if (pInBuff == NULL)
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_PARAM;
/* Return error status */
return HAL_ERROR;
}
}
if (hcordic->State == HAL_CORDIC_STATE_READY)
{
/* Reset CORDIC error code */
hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
/* Change the CORDIC state */
hcordic->State = HAL_CORDIC_STATE_BUSY;
/* Get DMA direction */
hcordic->DMADirection = DMADirection;
/* Check if CORDIC DMA direction "Out" is requested */
if ((DMADirection == CORDIC_DMA_DIR_OUT) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
{
/* Set the CORDIC DMA transfer complete callback */
hcordic->hdmaOut->XferCpltCallback = CORDIC_DMAOutCplt;
/* Set the DMA error callback */
hcordic->hdmaOut->XferErrorCallback = CORDIC_DMAError;
/* Check number of output data at each calculation,
to retrieve the size of output data buffer */
if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NRES))
{
sizeoutbuff = 2U * NbCalc;
}
else
{
sizeoutbuff = NbCalc;
}
/* Convert the output buffer size into corresponding number of bytes.
This is necessary as the DMA handles the data at byte-level. */
sizeoutbuff = 4U * sizeoutbuff;
outputaddr = (uint32_t)pOutBuff;
/* Enable the DMA stream managing CORDIC output data read */
if ((hcordic->hdmaOut->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hcordic->hdmaOut->LinkedListQueue != NULL) && (hcordic->hdmaOut->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
sizeoutbuff; /* Set DMA data size */
hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)&hcordic->Instance->RDATA; /* Set DMA source address */
hcordic->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
outputaddr; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hcordic->hdmaOut);
}
else
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
/* Return error status */
return HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, outputaddr, sizeoutbuff);
}
if (status != HAL_OK)
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
/* Return error status */
return HAL_ERROR;
}
/* Enable output data Read DMA requests */
SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_REN);
}
/* Check if CORDIC DMA direction "In" is requested */
if ((DMADirection == CORDIC_DMA_DIR_IN) || (DMADirection == CORDIC_DMA_DIR_IN_OUT))
{
/* Set the CORDIC DMA transfer complete callback */
hcordic->hdmaIn->XferCpltCallback = CORDIC_DMAInCplt;
/* Set the DMA error callback */
hcordic->hdmaIn->XferErrorCallback = CORDIC_DMAError;
/* Check number of input data expected for each calculation,
to retrieve the size of input data buffer */
if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
{
sizeinbuff = 2U * NbCalc;
}
else
{
sizeinbuff = NbCalc;
}
/* Convert the input buffer size into corresponding number of bytes.
This is necessary as the DMA handles the data at byte-level. */
sizeinbuff = 4U * sizeinbuff;
inputaddr = (uint32_t)pInBuff;
/* Enable the DMA stream managing CORDIC input data write */
if ((hcordic->hdmaIn->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hcordic->hdmaIn->LinkedListQueue != NULL) && (hcordic->hdmaIn->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
sizeinbuff; /* Set DMA data size */
hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
inputaddr; /* Set DMA source address */
hcordic->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hcordic->Instance->WDATA; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hcordic->hdmaIn);
}
else
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
/* Return error status */
return HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hcordic->hdmaIn, inputaddr, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff);
}
if (status != HAL_OK)
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
/* Return error status */
return HAL_ERROR;
}
/* Enable input data Write DMA request */
SET_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN);
}
/* Return function status */
return HAL_OK;
}
else
{
/* Set CORDIC error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_NOT_READY;
/* Return function status */
return HAL_ERROR;
}
}
/**
* @}
*/
/** @defgroup CORDIC_Exported_Functions_Group3 Callback functions
* @brief Callback functions.
*
@verbatim
==============================================================================
##### Callback functions #####
==============================================================================
[..] This section provides Interruption and DMA callback functions:
(+) DMA or Interrupt calculate complete
(+) DMA or Interrupt error
@endverbatim
* @{
*/
/**
* @brief CORDIC error callback.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module
* @retval None
*/
__weak void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcordic);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_CORDIC_ErrorCallback can be implemented in the user file
*/
}
/**
* @brief CORDIC calculate complete callback.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module
* @retval None
*/
__weak void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcordic);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_CORDIC_CalculateCpltCallback can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CORDIC_Exported_Functions_Group4 IRQ handler management
* @brief IRQ handler.
*
@verbatim
==============================================================================
##### IRQ handler management #####
==============================================================================
[..] This section provides IRQ handler function.
@endverbatim
* @{
*/
/**
* @brief Handle CORDIC interrupt request.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module
* @retval None
*/
void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic)
{
/* Check if calculation complete interrupt is enabled and if result ready
flag is raised */
if (__HAL_CORDIC_GET_IT_SOURCE(hcordic, CORDIC_IT_IEN) != 0U)
{
if (__HAL_CORDIC_GET_FLAG(hcordic, CORDIC_FLAG_RRDY) != 0U)
{
/* Decrement number of calculations to get */
hcordic->NbCalcToGet--;
/* Read output data from Read Data register, and increment output buffer pointer */
CORDIC_ReadOutDataIncrementPtr(hcordic, &(hcordic->pOutBuff));
/* Check if calculations are still to be ordered */
if (hcordic->NbCalcToOrder > 0U)
{
/* Decrement number of calculations to order */
hcordic->NbCalcToOrder--;
/* Continue the processing by providing another write of input data
in the Write Data register, and increment input buffer pointer */
CORDIC_WriteInDataIncrementPtr(hcordic, &(hcordic->pInBuff));
}
/* Check if all calculations results are got */
if (hcordic->NbCalcToGet == 0U)
{
/* Disable Result Ready Interrupt */
__HAL_CORDIC_DISABLE_IT(hcordic, CORDIC_IT_IEN);
/* Change the CORDIC state */
hcordic->State = HAL_CORDIC_STATE_READY;
/* Call calculation complete callback */
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
/*Call registered callback*/
hcordic->CalculateCpltCallback(hcordic);
#else
/*Call legacy weak (surcharged) callback*/
HAL_CORDIC_CalculateCpltCallback(hcordic);
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
}
}
}
}
/**
* @}
*/
/** @defgroup CORDIC_Exported_Functions_Group5 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
==============================================================================
##### Peripheral State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the CORDIC handle state.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module
* @retval HAL state
*/
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic)
{
/* Return CORDIC handle state */
return hcordic->State;
}
/**
* @brief Return the CORDIC peripheral error.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module
* @note The returned error is a bit-map combination of possible errors
* @retval Error bit-map
*/
uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic)
{
/* Return CORDIC error code */
return hcordic->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup CORDIC_Private_Functions
* @{
*/
/**
* @brief Write input data for CORDIC processing, and increment input buffer pointer.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module.
* @param ppInBuff Pointer to pointer to input buffer.
* @retval none
*/
static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff)
{
/* First write of input data in the Write Data register */
WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
/* Increment input data pointer */
(*ppInBuff)++;
/* Check if second write of input data is expected */
if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NARGS))
{
/* Second write of input data in the Write Data register */
WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
/* Increment input data pointer */
(*ppInBuff)++;
}
}
/**
* @brief Read output data of CORDIC processing, and increment output buffer pointer.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure that contains
* the configuration information for CORDIC module.
* @param ppOutBuff Pointer to pointer to output buffer.
* @retval none
*/
static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
{
/* First read of output data from the Read Data register */
**ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);
/* Increment output data pointer */
(*ppOutBuff)++;
/* Check if second read of output data is expected */
if (HAL_IS_BIT_SET(hcordic->Instance->CSR, CORDIC_CSR_NRES))
{
/* Second read of output data from the Read Data register */
**ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);
/* Increment output data pointer */
(*ppOutBuff)++;
}
}
/**
* @brief DMA CORDIC Input Data process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma)
{
CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable the DMA transfer for input request */
CLEAR_BIT(hcordic->Instance->CSR, CORDIC_DMA_WEN);
/* Check if DMA direction is CORDIC Input only (no DMA for CORDIC Output) */
if (hcordic->DMADirection == CORDIC_DMA_DIR_IN)
{
/* Change the CORDIC DMA direction to none */
hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
/* Change the CORDIC state to ready */
hcordic->State = HAL_CORDIC_STATE_READY;
/* Call calculation complete callback */
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
/*Call registered callback*/
hcordic->CalculateCpltCallback(hcordic);
#else
/*Call legacy weak (surcharged) callback*/
HAL_CORDIC_CalculateCpltCallback(hcordic);
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
}
}
/**
* @brief DMA CORDIC Output Data process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma)
{
CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable the DMA transfer for output request */
CLEAR_BIT(hcordic->Instance->CSR, CORDIC_DMA_REN);
/* Change the CORDIC DMA direction to none */
hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
/* Change the CORDIC state to ready */
hcordic->State = HAL_CORDIC_STATE_READY;
/* Call calculation complete callback */
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
/*Call registered callback*/
hcordic->CalculateCpltCallback(hcordic);
#else
/*Call legacy weak (surcharged) callback*/
HAL_CORDIC_CalculateCpltCallback(hcordic);
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
}
/**
* @brief DMA CORDIC communication error callback.
* @param hdma DMA handle.
* @retval None
*/
static void CORDIC_DMAError(DMA_HandleTypeDef *hdma)
{
CORDIC_HandleTypeDef *hcordic = (CORDIC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Set CORDIC handle state to error */
hcordic->State = HAL_CORDIC_STATE_READY;
/* Set CORDIC handle error code to DMA error */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
/* Call user callback */
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
/*Call registered callback*/
hcordic->ErrorCallback(hcordic);
#else
/*Call legacy weak (surcharged) callback*/
HAL_CORDIC_ErrorCallback(hcordic);
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CORDIC_MODULE_ENABLED */
#endif /* CORDIC */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c
|
C
|
apache-2.0
| 47,678
|
/**
******************************************************************************
* @file stm32u5xx_hal_cortex.c
* @author MCD Application Team
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and Configuration functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M33 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest pre-emption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure SysTick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
inside the stm32u5xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
[..]
*** How to configure MPU (secure and non secure) using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to Enable and configure the MPU secure and non-secure.
(#) Enable the MPU using HAL_MPU_Enable() function.
(#) Disable the MPU using HAL_MPU_Disable() function.
(#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU.
(#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU.
(#) Configure the MPU region using HAL_MPU_ConfigRegion()
and HAL_MPU_ConfigRegion_NS() to address the non secure MPU.
(#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes()
and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU.
@endverbatim
******************************************************************************
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
========================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
========================================================================================================================
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
| | | 4 bits for subpriority
------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
| | | 3 bits for subpriority
------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bit for subpriority
------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bit for subpriority
========================================================================================================================
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup CORTEX
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
* @{
*/
static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit);
static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
SysTick functionalities
@endverbatim
* @{
*/
/**
* @brief Set the priority grouping field (pre-emption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
* 0 bit for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Set the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
* CMSIS device file (stm32u5xxxx.h))
* @param PreemptPriority: The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enable a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
* CMSIS device file (stm32u5xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disable a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
* CMSIS device file (stm32u5xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiate a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @}
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
/**
* @brief Get the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Get the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
* CMSIS device file (stm32u5xxxx.h))
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
* 1 bit for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
* 0 bit for subpriority
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority,
uint32_t *const pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Set Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
* CMSIS device file (stm32u5xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Get Pending Interrupt (read the pending register in the NVIC
* and return the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
* CMSIS device file (stm32u5xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clear the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
* CMSIS device file (stm32u5xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Get active interrupt (read the active register in NVIC and return the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
* CMSIS device file (stm32u5xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configure the SysTick clock source.
* @param CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
switch (CLKSource)
{
/* Select HCLK as Systick clock source */
case SYSTICK_CLKSOURCE_HCLK:
SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
break;
/* Select HCLK_DIV8 as Systick clock source */
case SYSTICK_CLKSOURCE_HCLK_DIV8:
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U));
break;
/* Select LSI as Systick clock source */
case SYSTICK_CLKSOURCE_LSI:
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0);
break;
/* Select LSE as Systick clock source */
case SYSTICK_CLKSOURCE_LSE:
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk);
MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1);
break;
default:
/* Nothing to do */
break;
}
}
/**
* @brief Handle SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
/**
* @brief Enable the MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Follow ARM recommendation with */
/* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
__DMB(); /* Force memory writes before continuing */
__ISB(); /* Flush and refill pipeline with updated permissions */
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Enable the non-secure MPU.
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable_NS(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Follow ARM recommendation with */
/* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */
__DMB(); /* Force memory writes before continuing */
__ISB(); /* Flush and refill pipeline with updated permissions */
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Disable the MPU.
* @retval None
*/
void HAL_MPU_Disable(void)
{
__DMB(); /* Force any outstanding transfers to complete before disabling MPU */
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Disable the non-secure MPU.
* @retval None
*/
void HAL_MPU_Disable_NS(void)
{
__DMB(); /* Force any outstanding transfers to complete before disabling MPU */
/* Disable the MPU */
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Initialize and configure the Region and the memory to be protected.
* @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
{
MPU_ConfigRegion(MPU, pMPU_RegionInit);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Initialize and configure the Region and the memory to be protected for non-secure MPU.
* @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit)
{
MPU_ConfigRegion(MPU_NS, pMPU_RegionInit);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Initialize and configure the memory attributes.
* @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
{
MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Initialize and configure the memory attributes for non-secure MPU.
* @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
{
MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup CORTEX_Private_Functions
* @{
*/
static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit)
{
/* Check the parameters */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
assert_param(IS_MPU_INSTANCE(MPUx));
#endif /* __ARM_FEATURE_CMSE */
assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number));
assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable));
/* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */
__DMB();
/* Set the Region number */
MPUx->RNR = pMPU_RegionInit->Number;
if (pMPU_RegionInit->Enable != MPU_REGION_DISABLE)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission));
assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable));
MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) |
((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) |
((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) |
((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos));
MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) |
((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) |
((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos));
}
else
{
MPUx->RBAR = 0U;
MPUx->RLAR = 0U;
}
}
static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit)
{
__IO uint32_t *p_mair;
uint32_t attr_values;
uint32_t attr_number;
/* Check the parameters */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
assert_param(IS_MPU_INSTANCE(MPUx));
#endif /* __ARM_FEATURE_CMSE */
assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number));
/* No need to check Attributes value as all 0x0..0xFF possible */
/* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */
__DMB();
if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4)
{
/* Program MPU_MAIR0 */
p_mair = &(MPUx->MAIR0);
attr_number = pMPU_AttributesInit->Number;
}
else
{
/* Program MPU_MAIR1 */
p_mair = &(MPUx->MAIR1);
attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U;
}
attr_values = *(p_mair);
attr_values &= ~(0xFFUL << (attr_number * 8U));
*(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U));
}
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c
|
C
|
apache-2.0
| 26,596
|
/**
******************************************************************************
* @file stm32u5xx_hal_crc.c
* @author MCD Application Team
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(+) Initialize CRC calculator
(++) specify generating polynomial (peripheral default or non-default one)
(++) specify initialization value (peripheral default or non-default one)
(++) specify input data format
(++) specify input or output data inversion mode if any
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
input data buffer starting with the previously computed CRC as
initialization value
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
input data buffer starting with the defined initialization value
(default or non-default) to initiate CRC calculation
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup CRC CRC
* @brief CRC HAL module driver.
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CRC_Private_Functions CRC Private Functions
* @{
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral
(+) Initialize the CRC MSP (MCU Specific Package)
(+) DeInitialize the CRC MSP
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
hcrc->State = HAL_CRC_STATE_BUSY;
/* check whether or not non-default generating polynomial has been
* picked up by user */
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
{
/* initialize peripheral with default generating polynomial */
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
}
else
{
/* initialize CRC peripheral with generating polynomial defined by user */
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
{
return HAL_ERROR;
}
}
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
}
else
{
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
}
/* set input data inversion mode */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
/* set output data inversion mode */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
/* makes sure the input data format (bytes, halfwords or words stream)
* is properly specified by user */
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the CRC peripheral.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if (hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
/* Check the CRC peripheral state */
if (hcrc->State == HAL_CRC_STATE_BUSY)
{
return HAL_BUSY;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hcrc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the CRC MSP.
* @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions.
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
using combination of the previous CRC value and the new one.
[..] or
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
independently of the previous CRC value.
@endverbatim
* @{
*/
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with the previously computed CRC as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
switch (hcrc->InputDataFormat)
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter Data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
case CRC_INPUTDATA_FORMAT_BYTES:
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
default:
break;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
* written in hcrc->Instance->DR) */
__HAL_CRC_DR_RESET(hcrc);
switch (hcrc->InputDataFormat)
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter 32-bit input data to the CRC calculator */
for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
case CRC_INPUTDATA_FORMAT_BYTES:
/* Specific 8-bit input data handling */
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
/* Specific 16-bit input data handling */
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
default:
break;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return the CRC computed value */
return temp;
}
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the CRC handle state.
* @param hcrc CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup CRC_Private_Functions
* @{
*/
/**
* @brief Enter 8-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer
* @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
uint32_t i; /* input data buffer index */
uint16_t data;
__IO uint16_t *pReg;
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
* handling by the peripheral */
for (i = 0U; i < (BufferLength / 4U); i++)
{
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
(uint32_t)pBuffer[(4U * i) + 3U];
}
/* last bytes specific handling */
if ((BufferLength % 4U) != 0U)
{
if ((BufferLength % 4U) == 1U)
{
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
}
if ((BufferLength % 4U) == 2U)
{
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = data;
}
if ((BufferLength % 4U) == 3U)
{
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = data;
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
}
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @brief Enter 16-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer
* @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
uint32_t i; /* input data buffer index */
__IO uint16_t *pReg;
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
* a correct type handling by the peripheral */
for (i = 0U; i < (BufferLength / 2U); i++)
{
hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
}
if ((BufferLength % 2U) != 0U)
{
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = pBuffer[2U * i];
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c
|
C
|
apache-2.0
| 17,026
|
/**
******************************************************************************
* @file stm32u5xx_hal_crc_ex.c
* @author MCD Application Team
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
================================================================================
##### How to use this driver #####
================================================================================
[..]
(+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
(+) Configure Input or Output data inversion
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup CRCEx CRCEx
* @brief CRC Extended HAL module driver
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
* @{
*/
/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
* @brief Extended Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Extended configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the generating polynomial
(+) Configure the input data inversion
(+) Configure the output data inversion
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC polynomial if different from default one.
* @param hcrc CRC handle
* @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
* This parameter is written in normal representation, e.g.
* @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
* @param PolyLength CRC polynomial length.
* This parameter can be one of the following values:
* @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
* @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
/* check polynomial definition vs polynomial size:
* polynomial length must be aligned with polynomial
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
{
}
switch (PolyLength)
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
break;
}
if (status == HAL_OK)
{
/* set generating polynomial */
WRITE_REG(hcrc->Instance->POL, Pol);
/* set generating polynomial size */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
}
/* Return function status */
return status;
}
/**
* @brief Set the Reverse Input data mode.
* @param hcrc CRC handle
* @param InputReverseMode Input Data inversion mode.
* This parameter can be one of the following values:
* @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
* @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
* @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
* @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set input data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the Reverse Output data mode.
* @param hcrc CRC handle
* @param OutputReverseMode Output Data inversion mode.
* This parameter can be one of the following values:
* @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
* @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set output data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c
|
C
|
apache-2.0
| 7,388
|
/**
******************************************************************************
* @file stm32u5xx_hal_cryp.c
* @author MCD Application Team
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
* + Initialization, de-initialization, set config and get config functions
* + DMA callback functions
* + CRYP IRQ handler management
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The CRYP HAL driver can be used as follows:
(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
(##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE
(##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
(##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
(+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
(+++) Configure and enable two DMA channels one for managing data transfer from
memory to peripheral (input channel) and another stream for managing data
transfer from peripheral to memory (output channel)
(+++) Associate the initialized DMA handle to the CRYP DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the two DMA channels. The output channel should have higher
priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
(#)Initialize the CRYP according to the specified parameters :
(##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
(##) The key size: 128, 192 or 256.
(##) The AES Algorithm ECB/CBC/CTR/GCM or CCM.
(##) The initialization vector (counter). It is not used in ECB mode.
(##) The key buffer used for encryption/decryption.
(+++) In some specific configurations, the key is written by the application
code out of the HAL scope. In that case, user can still resort to the
HAL APIs as usual but must make sure that pKey pointer is set to NULL.
(##) The DataWidthUnit field. It specifies whether the data length (or the payload
length for authentication algorithms) is in words or bytes.
(##) The Header used only in AES GCM and CCM Algorithm for authentication.
(##) The HeaderSize used to give size of header buffer in word or bytes, depending upon HeaderWidthUnit field.
(##) The HeaderWidthUnit field. It specifies whether the header length
(for authentication algorithms) is in words or bytes.
(##) The B0 block is the first authentication block used only in AES CCM mode.
(##) The KeyIVConfigSkip used to process several messages in a row.
(##) The KeyMode used to special key operation modes (for SAES : wrapped key, shared key with AES peripheral).
(##) The KeySelect, Only for SAES, used to select key from different key source.
(##) The KeyProtection, Only for SAES, used for security context enforcement.
(#)Three processing (encryption/decryption) functions are available:
(##) Polling mode: encryption and decryption APIs are blocking functions
i.e. they process the data and wait till the processing is finished,
e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
(##) Interrupt mode: encryption and decryption APIs are not blocking functions
i.e. they process the data under interrupt,
e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
(##) DMA mode: encryption and decryption APIs are not blocking functions
i.e. the data transfer is ensured by DMA,
e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
(#)When the processing function is called at first time after HAL_CRYP_Init()
the CRYP peripheral is configured and processes the buffer in input.
At second call, no need to Initialize the CRYP, user have to get current configuration via
HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
new parametres, finally user can start encryption/decryption.
(#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
(#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
without having to configure again the Key or the Initialization Vector between each API call,
the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
or HAL_CRYP_Decrypt_DMA().
[..]
The cryptographic processor supports following standards:
(#) The advanced encryption standard (AES) supported:
(##)128-bit data block processing
(##) chaining modes supported :
(+++) Electronic Code Book(ECB)
(+++) Cipher Block Chaining (CBC)
(+++) Counter mode (CTR)
(+++) Galois/counter mode (GCM/GMAC)
(+++) Counter with Cipher Block Chaining-Message(CCM)
(##) keys length Supported : 128-bit and 256-bit
[..]
(@) Specific care must be taken to format the key and the Initialization Vector IV!
[..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where
b127 is the MSB and b0 the LSB, the key must be stored in MCU memory
(+) as a sequence of words where the MSB word comes first (occupies the
lowest memory address)
(++) address n+0 : 0b b127 .. b120 b119 .. b112 b111 .. b104 b103 .. b96
(++) address n+4 : 0b b95 .. b88 b87 .. b80 b79 .. b72 b71 .. b64
(++) address n+8 : 0b b63 .. b56 b55 .. b48 b47 .. b40 b39 .. b32
(++) address n+C : 0b b31 .. b24 b23 .. b16 b15 .. b8 b7 .. b0
[..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}.
The 4 32-bit words that make the key must be stored as follows in MCU memory:
(+) address n+0 : 0x B15 B14 B13 B12
(+) address n+4 : 0x B11 B10 B9 B8
(+) address n+8 : 0x B7 B6 B5 B4
(+) address n+C : 0x B3 B2 B1 B0
[..] which leads to the expected setting
(+) AES_KEYR3 = 0x B15 B14 B13 B12
(+) AES_KEYR2 = 0x B11 B10 B9 B8
(+) AES_KEYR1 = 0x B7 B6 B5 B4
(+) AES_KEYR0 = 0x B3 B2 B1 B0
[..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}.
The 8 32-bit words that make the key must be stored as follows in MCU memory:
(+) address n+00 : 0x B31 B30 B29 B28
(+) address n+04 : 0x B27 B26 B25 B24
(+) address n+08 : 0x B23 B22 B21 B20
(+) address n+0C : 0x B19 B18 B17 B16
(+) address n+10 : 0x B15 B14 B13 B12
(+) address n+14 : 0x B11 B10 B9 B8
(+) address n+18 : 0x B7 B6 B5 B4
(+) address n+1C : 0x B3 B2 B1 B0
[..] which leads to the expected setting
(+) AES_KEYR7 = 0x B31 B30 B29 B28
(+) AES_KEYR6 = 0x B27 B26 B25 B24
(+) AES_KEYR5 = 0x B23 B22 B21 B20
(+) AES_KEYR4 = 0x B19 B18 B17 B16
(+) AES_KEYR3 = 0x B15 B14 B13 B12
(+) AES_KEYR2 = 0x B11 B10 B9 B8
(+) AES_KEYR1 = 0x B7 B6 B5 B4
(+) AES_KEYR0 = 0x B3 B2 B1 B0
[..] Initialization Vector IV (4 32-bit words) format must follow the same as
that of a 128-bit long key.
[..] Note that key and IV registers are not sensitive to swap mode selection.
[..] This section describes the AES Galois/counter mode (GCM) supported by the peripherals:
(#) Algorithm supported :
(##) Galois/counter mode (GCM)
(##) Galois message authentication code (GMAC) :is exactly the same as
GCM algorithm composed only by an header.
(#) Four phases are performed in GCM :
(##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
(##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash
computation only.
(##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream
encryption + data XORing. It works in a similar way for ciphertext (C).
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
HAL_CRYPEx_AESGCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond
to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits.
(#) structure of message construction in GCM is defined as below :
(##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
(##) The authenticated header A (also knows as Additional Authentication Data AAD)
this part of the message is only authenticated, not encrypted.
(##) The plaintext message P is both authenticated and encrypted as ciphertext.
GCM standard specifies that ciphertext has same bit length as the plaintext.
(##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
(on 64 bits)
[..] A more detailed description of the GCM message structure is available below.
[..] This section describe The AES Counter with Cipher Block Chaining-Message
Authentication Code (CCM) supported by the peripheral:
(#) Specific parameters for CCM :
(##) B0 block : follows NIST Special Publication 800-38C,
(##) B1 block (header)
(##) CTRx block : control blocks
[..] A detailed description of the CCM message structure is available below.
(#) CCM in peripheral:
(##) To perform message payload encryption or decryption AES is configured in CTR mode.
(##) For authentication two phases are performed :
- Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message
only cleartext payload (not the ciphertext payload) is used and no outpout.
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag.
user should consider only part of this 4 words, if Tag length is less than 128 bits
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
to register an interrupt callback.
[..]
Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback.
(+) OutCpltCallback : Output FIFO transfer completed callback.
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : CRYP MspInit.
(+) MspDeInitCallback : CRYP MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback.
(+) OutCpltCallback : Output FIFO transfer completed callback.
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : CRYP MspInit.
(+) MspDeInitCallback : CRYP MspDeInit.
[..]
By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
all callbacks are set to the corresponding weak functions :
examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
these callbacks are null (not registered beforehand).
if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
keep and use the user MspInit/MspDeInit functions (registered beforehand)
[..]
Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
or @ref HAL_CRYP_Init() function.
[..]
When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
*** Suspend/Resume feature ***
==============================
[..]
The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
allows the user to resort to the suspend/resume feature.
A low priority block processing can be suspended to process a high priority block
instead. When the high priority block processing is over, the low priority block
processing can be resumed, restarting from the point where it was suspended. This
feature is applicable only in non-blocking interrupt mode.
[..] User must resort to HAL_CRYP_Suspend() to suspend the low priority block
processing. This API manages the hardware block processing suspension and saves all the
internal data that will be needed to restart later on. Upon HAL_CRYP_Suspend() completion,
the user can launch the processing of any other block (high priority block processing).
[..] When the high priority block processing is over, user must invoke HAL_CRYP_Resume()
to resume the low priority block processing. Ciphering (or deciphering) restarts from
the suspension point and ends as usual.
[..] HAL_CRYP_Suspend() reports an error when the suspension request is sent too late
(i.e when the low priority block processing is about to end). There is no use to
suspend the tag generation processing for authentication algorithms.
[..]
(@) If the key is written out of HAL scope (case pKey pointer set to NULL by the user),
the block processing suspension/resumption mechanism is NOT applicable.
[..]
(@) If the Key and Initialization Vector are configured only once and configuration is
skipped for consecutive processings (case KeyIVConfigSkip set to CRYP_KEYIVCONFIG_ONCE),
the block processing suspension/resumption mechanism is NOT applicable.
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup CRYP
* @{
*/
#if defined(AES)
#ifdef HAL_CRYP_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup CRYP_Private_Defines
* @{
*/
#define CRYP_GENERAL_TIMEOUT 82U
#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey
is 299 clock cycles.*/
#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
#define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */
#define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */
#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
/* CTR1 information to use in CCM algorithm */
#define CRYP_CCM_CTR1_0 0x07FFFFFFU
#define CRYP_CCM_CTR1_1 0xFFFFFF00U
#define CRYP_CCM_CTR1_2 0x00000001U
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @addtogroup CRYP_Private_Macros
* @{
*/
#define CRYP_SET_PHASE(__HANDLE__, __PHASE__)\
MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))
/**
* @}
*/
/* Private struct -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup CRYP_Private_Functions
* @{
*/
static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size);
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp);
static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output);
static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input);
static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output);
static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input);
static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output, uint32_t KeySize);
static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input, uint32_t KeySize);
static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp);
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @addtogroup CRYP_Exported_Functions
* @{
*/
/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
========================================================================================
##### Initialization, de-initialization and Set and Get configuration functions #####
========================================================================================
[..] This section provides functions allowing to:
(+) Initialize the CRYP
(+) DeInitialize the CRYP
(+) Initialize the CRYP MSP
(+) DeInitialize the CRYP MSP
(+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
Parameters which are configured in This section are :
(+) Key size
(+) Data Type : 32,16, 8 or 1bit
(+) AlgoMode : ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
(+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
@endverbatim
* @{
*/
/**
* @brief Initializes the CRYP according to the specified
* parameters in the CRYP_ConfigTypeDef and creates the associated handle.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
{
uint32_t cr_value;
uint32_t Timeout = CRYP_GENERAL_TIMEOUT;
uint32_t tickstart;
/* Check the CRYP handle allocation */
if (hcryp == NULL)
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
if (hcryp->State == HAL_CRYP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcryp->Lock = HAL_UNLOCKED;
hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
if (hcryp->MspInitCallback == NULL)
{
hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
hcryp->MspInitCallback(hcryp);
}
#else
if (hcryp->State == HAL_CRYP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcryp->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRYP_MspInit(hcryp);
}
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
if (hcryp->Instance == AES)
{
/* Set the key size, data type and Algorithm */
cr_value = (uint32_t)(hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode);
/* Set the key size, data type, algorithm and mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, cr_value);
}
else
{
/* SAES is initializing, fetching random number from the RNG */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
__HAL_CRYP_DISABLE(hcryp);
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
cr_value = (uint32_t)(hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | \
hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection);
/* Set the key size, data type, algorithm, Key selection and key protection */
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KEYSEL |
AES_CR_KEYPROT, cr_value);
}
/* Reset Error Code field */
hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
/* Reset peripheral Key and IV configuration flag */
hcryp->KeyIVConfig = 0U;
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Set the default CRYP phase */
hcryp->Phase = CRYP_PHASE_READY;
return HAL_OK;
}
/**
* @brief De-Initializes the CRYP peripheral.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
{
/* Check the CRYP handle allocation */
if (hcryp == NULL)
{
return HAL_ERROR;
}
/* Set the default CRYP phase */
hcryp->Phase = CRYP_PHASE_READY;
/* Reset CrypInCount and CrypOutCount */
hcryp->CrypInCount = 0;
hcryp->CrypOutCount = 0;
hcryp->CrypHeaderCount = 0;
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Set IPRST for software reset */
SET_BIT(hcryp->Instance->CR, AES_CR_IPRST);
/* Clear IPRST to allow writing registers */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_IPRST);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
if (hcryp->MspDeInitCallback == NULL)
{
hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware */
hcryp->MspDeInitCallback(hcryp);
#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_CRYP_MspDeInit(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_RESET;
__HAL_UNLOCK(hcryp);
return HAL_OK;
}
/**
* @brief Configure the CRYP according to the specified
* parameters in the CRYP_ConfigTypeDef
* @param hcryp pointer to a CRYP_HandleTypeDef structure
* @param pConf pointer to a CRYP_ConfigTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
{
/* Check the CRYP handle allocation */
if ((hcryp == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
assert_param(IS_CRYP_DATATYPE(pConf->DataType));
assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Set CRYP parameters */
hcryp->Init.DataType = pConf->DataType;
hcryp->Init.pKey = pConf->pKey;
hcryp->Init.Algorithm = pConf->Algorithm;
hcryp->Init.KeySize = pConf->KeySize;
hcryp->Init.pInitVect = pConf->pInitVect;
hcryp->Init.Header = pConf->Header;
hcryp->Init.HeaderSize = pConf->HeaderSize;
hcryp->Init.B0 = pConf->B0;
hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
hcryp->Init.KeyMode = pConf->KeyMode;
hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
if (hcryp->Instance == AES)
{
/* Set the key size(This bit field is do not care in the DES or TDES modes)
data type, AlgoMode and operating mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD,
hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode);
}
else
{
hcryp->Init.KeySelect = pConf->KeySelect;
hcryp->Init.KeyProtection = pConf->KeyProtection;
/* In case of HSW, HW or SW key selection, we should specify Key mode selection (SAES_CR_KMOD) */
if ((hcryp->Init.KeySelect != CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_WRAPPED))
{
/* Set key mode selection (Normal, Wrapped or Shared key )*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
}
/* Set the key size data type, AlgoMode and operating mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \
AES_CR_KEYSEL | AES_CR_KEYPROT, hcryp->Init.DataType | hcryp->Init.KeySize | \
hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection);
}
/* Clear error flags */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
__HAL_UNLOCK(hcryp);
/* Reset Error Code field */
hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Set the default CRYP phase */
hcryp->Phase = CRYP_PHASE_READY;
return HAL_OK;
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
}
/**
* @brief Get CRYP Configuration parameters in associated handle.
* @param pConf pointer to a CRYP_ConfigTypeDef structure
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
{
/* Check the CRYP handle allocation */
if ((hcryp == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Get CRYP parameters */
pConf->DataType = hcryp->Init.DataType;
pConf->pKey = hcryp->Init.pKey;
pConf->Algorithm = hcryp->Init.Algorithm;
pConf->KeySize = hcryp->Init.KeySize;
pConf->pInitVect = hcryp->Init.pInitVect;
pConf->Header = hcryp->Init.Header;
pConf->HeaderSize = hcryp->Init.HeaderSize;
pConf->B0 = hcryp->Init.B0;
pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
pConf->KeyMode = hcryp->Init.KeyMode;
pConf->KeySelect = hcryp->Init.KeySelect;
pConf->KeyProtection = hcryp->Init.KeyProtection;
pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
return HAL_OK;
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
}
/**
* @brief Initializes the CRYP MSP.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes CRYP MSP.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_MspDeInit could be implemented in the user file
*/
}
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User CRYP Callback
* To be used instead of the weak predefined callback
* @param hcryp cryp handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
* @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
* @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
pCRYP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
__HAL_LOCK(hcryp);
if (hcryp->State == HAL_CRYP_STATE_READY)
{
switch (CallbackID)
{
case HAL_CRYP_INPUT_COMPLETE_CB_ID :
hcryp->InCpltCallback = pCallback;
break;
case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
hcryp->OutCpltCallback = pCallback;
break;
case HAL_CRYP_ERROR_CB_ID :
hcryp->ErrorCallback = pCallback;
break;
case HAL_CRYP_MSPINIT_CB_ID :
hcryp->MspInitCallback = pCallback;
break;
case HAL_CRYP_MSPDEINIT_CB_ID :
hcryp->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hcryp->State == HAL_CRYP_STATE_RESET)
{
switch (CallbackID)
{
case HAL_CRYP_MSPINIT_CB_ID :
hcryp->MspInitCallback = pCallback;
break;
case HAL_CRYP_MSPDEINIT_CB_ID :
hcryp->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
__HAL_UNLOCK(hcryp);
return status;
}
/**
* @brief Unregister an CRYP Callback
* CRYP callback is redirected to the weak predefined callback
* @param hcryp cryp handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
* @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
* @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
* @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
__HAL_LOCK(hcryp);
if (hcryp->State == HAL_CRYP_STATE_READY)
{
switch (CallbackID)
{
case HAL_CRYP_INPUT_COMPLETE_CB_ID :
hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
break;
case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
break;
case HAL_CRYP_ERROR_CB_ID :
hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_CRYP_MSPINIT_CB_ID :
hcryp->MspInitCallback = HAL_CRYP_MspInit;
break;
case HAL_CRYP_MSPDEINIT_CB_ID :
hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
break;
default :
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hcryp->State == HAL_CRYP_STATE_RESET)
{
switch (CallbackID)
{
case HAL_CRYP_MSPINIT_CB_ID :
hcryp->MspInitCallback = HAL_CRYP_MspInit;
break;
case HAL_CRYP_MSPDEINIT_CB_ID :
hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
break;
default :
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
/* Return error status */
status = HAL_ERROR;
}
__HAL_UNLOCK(hcryp);
return status;
}
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/**
* @brief Request CRYP processing suspension when in interruption mode.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @note Set the handle field SuspendRequest to the appropriate value so that
* the on-going CRYP processing is suspended as soon as the required
* conditions are met.
* @note HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done
* in non-blocking interrupt mode.
* @note It is advised not to suspend the CRYP processing when the DMA controller
* is managing the data transfer.
* @retval None
*/
void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
{
/* Set Handle SuspendRequest field */
hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
}
/**
* @brief CRYP processing suspension and peripheral internal parameters storage.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @note peripheral internal parameters are stored to be readily available when
* suspended processing is resumed later on.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
{
HAL_CRYP_STATETypeDef state;
/* Request suspension */
HAL_CRYP_ProcessSuspend(hcryp);
do
{
state = HAL_CRYP_GetState(hcryp);
} while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
{
/* Processing was already over or was about to end. No suspension done */
return HAL_ERROR;
}
else
{
/* Suspend Processing */
/* If authentication algorithms on-going, carry out first saving steps
before disable the peripheral */
if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \
(hcryp->Init.Algorithm == CRYP_AES_CCM))
{
/* Save Suspension registers */
CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
/* Save Key */
CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
/* Save IV */
CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
}
/* Disable AES */
__HAL_CRYP_DISABLE(hcryp);
/* Save low-priority block CRYP handle parameters */
hcryp->Init_saved = hcryp->Init;
hcryp->pCrypInBuffPtr_saved = hcryp->pCrypInBuffPtr;
hcryp->pCrypOutBuffPtr_saved = hcryp->pCrypOutBuffPtr;
hcryp->CrypInCount_saved = hcryp->CrypInCount;
hcryp->CrypOutCount_saved = hcryp->CrypOutCount;
hcryp->Phase_saved = hcryp->Phase;
hcryp->State_saved = hcryp->State;
hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)\
? (hcryp->Size / 4U) : hcryp->Size);
hcryp->SizesSum_saved = hcryp->SizesSum;
hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount;
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
(hcryp->Init.Algorithm == CRYP_AES_CTR))
{
/* Save Initialisation Vector registers */
CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved);
}
/* Save Control register */
hcryp->CR_saved = hcryp->Instance->CR;
}
return HAL_OK;
}
/**
* @brief CRYP processing resumption.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @note Processing restarts at the exact point where it was suspended, based
* on the parameters saved at suspension time.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
{
/* Check the CRYP handle allocation */
if (hcryp == NULL)
{
return HAL_ERROR;
}
if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
{
/* CRYP was not suspended */
return HAL_ERROR;
}
else
{
/* Restore low-priority block CRYP handle parameters */
hcryp->Init = hcryp->Init_saved;
hcryp->State = hcryp->State_saved;
/* Chaining algorithms case */
if ((hcryp->Init_saved.Algorithm == CRYP_AES_ECB) || \
(hcryp->Init_saved.Algorithm == CRYP_AES_CBC) || \
(hcryp->Init_saved.Algorithm == CRYP_AES_CTR))
{
/* Restore low-priority block CRYP handle parameters */
if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \
(hcryp->Init.Algorithm == CRYP_AES_CTR))
{
hcryp->Init.pInitVect = hcryp->IV_saved;
}
__HAL_CRYP_DISABLE(hcryp);
(void) HAL_CRYP_Init(hcryp);
}
else /* Authentication algorithms case */
{
/* Restore low-priority block CRYP handle parameters */
hcryp->Phase = hcryp->Phase_saved;
hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved;
hcryp->SizesSum = hcryp->SizesSum_saved;
/* Disable AES and write-back SUSPxR registers */;
__HAL_CRYP_DISABLE(hcryp);
/* Restore AES Suspend Registers */
CRYP_Write_SuspendRegisters(hcryp, hcryp->SUSPxR_saved);
/* Restore Control, Key and IV Registers, then enable AES */
hcryp->Instance->CR = hcryp->CR_saved;
CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved);
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
__HAL_CRYP_ENABLE(hcryp);
/* At the same time, set handle state back to READY to be able to resume the AES calculations
without the processing APIs returning HAL_BUSY when called. */
hcryp->State = HAL_CRYP_STATE_READY;
}
/* Resume low-priority block processing under IT */
hcryp->ResumingFlag = 1U;
if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved,
hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
{
return HAL_ERROR;
}
}
else
{
if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved,
hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
{
return HAL_ERROR;
}
}
}
return HAL_OK;
}
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
/**
* @}
*/
/** @defgroup CRYP_Exported_Functions_Group2 Encryption Decryption functions
* @brief Encryption Decryption functions.
*
@verbatim
==============================================================================
##### Encrypt Decrypt functions #####
==============================================================================
[..] This section provides API allowing to Encrypt/Decrypt Data following
(+) Standard AES algorithms supported by the peripheral:
- Electronic Code Book(ECB)
- Cipher Block Chaining (CBC)
- Counter mode (CTR)
- Cipher Block Chaining (CBC)
- Counter mode (CTR)
- Galois/counter mode (GCM)
- Counter with Cipher Block Chaining-Message(CCM)
[..] Three processing functions are available:
(+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
(+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
(+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
@endverbatim
* @{
*/
/* GCM message structure additional details
ICB
+-------------------------------------------------------+
| Initialization vector (IV) | Counter |
|----------------|----------------|-----------|---------|
127 95 63 31 0
Bit Number Register Contents
---------- --------------- -----------
127 ...96 CRYP_IV1R[31:0] ICB[127:96]
95 ...64 CRYP_IV1L[31:0] B0[95:64]
63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
GCM last block definition
+-------------------------------------------------------------------+
| Bit[0] | Bit[32] | Bit[64] | Bit[96] |
|-----------|--------------------|-----------|----------------------|
| 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
|-----------|--------------------|-----------|----------------------|
*/
/* CCM message blocks description
(##) B0 block : According to NIST Special Publication 800-38C,
The first block B0 is formatted as follows, where l(m) is encoded in
most-significant-byte first order:
Octet Number Contents
------------ ---------
0 Flags
1 ... 15-q Nonce N
16-q ... 15 Q
the Flags field is formatted as follows:
Bit Number Contents
---------- ----------------------
7 Reserved (always zero)
6 Adata
5 ... 3 (t-2)/2
2 ... 0 [q-1]3
- Q: a bit string representation of the octet length of P (plaintext)
- q The octet length of the binary representation of the octet length of the payload
- A nonce (N), n The octet length of the where n+q=15.
- Flags: most significant octet containing four flags for control information,
- t The octet length of the MAC.
(##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
the associated data length expressed in bytes (a) defined as below:
- If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
- If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
- If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
(##) CTRx block : control blocks
- Generation of CTR1 from first block B0 information :
equal to B0 with first 5 bits zeroed and most significant bits storing octet
length of P also zeroed, then incremented by one
Bit Number Register Contents
---------- --------------- -----------
127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
bit 0 that is set to 1
95 ...64 CRYP_IV1L[31:0] B0[95:64]
63 ... 32 CRYP_IV0R[31:0] B0[63:32]
31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
- Generation of CTR0: same as CTR1 with bit[0] set to zero.
*/
/**
* @brief Encryption mode.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pInput Pointer to the input buffer (plaintext)
* @param Size Length of the plaintext buffer either in word or in byte, according to DataWidthUnit
* @param pOutput Pointer to the output buffer(ciphertext)
* @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput,
uint32_t Timeout)
{
uint32_t algo;
HAL_StatusTypeDef status;
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif /* USE_FULL_ASSERT */
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = pInput;
hcryp->pCrypOutBuffPtr = pOutput;
/* Calculate Size parameter in Byte */
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
hcryp->Size = Size * 4U;
}
else
{
hcryp->Size = Size;
}
if (hcryp->Instance == AES)
{
/* Set the operating mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
}
else
{
/* Set the operating mode and normal key selection */
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL);
}
/* Algo get algorithm selected */
algo = hcryp->Instance->CR & AES_CR_CHMOD;
switch (algo)
{
case CRYP_AES_ECB:
case CRYP_AES_CBC:
case CRYP_AES_CTR:
/* AES encryption */
status = CRYP_AES_Encrypt(hcryp, Timeout);
break;
case CRYP_AES_GCM_GMAC:
/* AES GCM encryption */
status = CRYP_AESGCM_Process(hcryp, Timeout);
break;
case CRYP_AES_CCM:
/* AES CCM encryption */
status = CRYP_AESCCM_Process(hcryp, Timeout);
break;
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
break;
}
if (status == HAL_OK)
{
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
}
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Decryption mode.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pInput Pointer to the input buffer (ciphertext )
* @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit
* @param pOutput Pointer to the output buffer(plaintext)
* @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput,
uint32_t Timeout)
{
HAL_StatusTypeDef status;
uint32_t algo;
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif /* USE_FULL_ASSERT */
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = pInput;
hcryp->pCrypOutBuffPtr = pOutput;
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
hcryp->Size = Size * 4U;
}
else
{
hcryp->Size = Size;
}
/* Set Decryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
/* algo get algorithm selected */
algo = hcryp->Instance->CR & AES_CR_CHMOD;
switch (algo)
{
case CRYP_AES_ECB:
case CRYP_AES_CBC:
case CRYP_AES_CTR:
/* AES decryption */
status = CRYP_AES_Decrypt(hcryp, Timeout);
break;
case CRYP_AES_GCM_GMAC:
/* AES GCM decryption */
status = CRYP_AESGCM_Process(hcryp, Timeout);
break;
case CRYP_AES_CCM:
/* AES CCM decryption */
status = CRYP_AESCCM_Process(hcryp, Timeout);
break;
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
break;
}
if (status == HAL_OK)
{
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
}
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Encryption in interrupt mode.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pInput Pointer to the input buffer (plaintext)
* @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit
* @param pOutput Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput)
{
HAL_StatusTypeDef status;
uint32_t algo;
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif /* USE_FULL_ASSERT */
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if (hcryp->ResumingFlag == 1U)
{
hcryp->ResumingFlag = 0U;
if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
{
hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
}
else
{
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
}
}
else
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
{
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
}
hcryp->pCrypInBuffPtr = pInput;
hcryp->pCrypOutBuffPtr = pOutput;
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
hcryp->Size = Size * 4U;
}
else
{
hcryp->Size = Size;
}
/* Set encryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
/* algo get algorithm selected */
algo = hcryp->Instance->CR & AES_CR_CHMOD;
switch (algo)
{
case CRYP_AES_ECB:
case CRYP_AES_CBC:
case CRYP_AES_CTR:
/* AES encryption */
status = CRYP_AES_Encrypt_IT(hcryp);
break;
case CRYP_AES_GCM_GMAC:
/* AES GCM encryption */
status = CRYP_AESGCM_Process_IT(hcryp);
break;
case CRYP_AES_CCM:
/* AES CCM encryption */
status = CRYP_AESCCM_Process_IT(hcryp);
break;
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
break;
}
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Decryption in interrupt mode.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pInput Pointer to the input buffer (ciphertext )
* @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit
* @param pOutput Pointer to the output buffer(plaintext)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput)
{
HAL_StatusTypeDef status;
uint32_t algo;
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif /* USE_FULL_ASSERT */
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if (hcryp->ResumingFlag == 1U)
{
hcryp->ResumingFlag = 0U;
if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
{
hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
}
else
{
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
}
}
else
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
{
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
}
hcryp->pCrypInBuffPtr = pInput;
hcryp->pCrypOutBuffPtr = pOutput;
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
hcryp->Size = Size * 4U;
}
else
{
hcryp->Size = Size;
}
/* Set decryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
/* algo get algorithm selected */
algo = hcryp->Instance->CR & AES_CR_CHMOD;
switch (algo)
{
case CRYP_AES_ECB:
case CRYP_AES_CBC:
case CRYP_AES_CTR:
/* AES decryption */
status = CRYP_AES_Decrypt_IT(hcryp);
break;
case CRYP_AES_GCM_GMAC:
/* AES GCM decryption */
status = CRYP_AESGCM_Process_IT(hcryp);
break;
case CRYP_AES_CCM:
/* AES CCM decryption */
status = CRYP_AESCCM_Process_IT(hcryp);
break;
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
break;
}
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Encryption in DMA mode.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pInput Pointer to the input buffer (plaintext)
* @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit
* @param pOutput Pointer to the output buffer(ciphertext)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput)
{
HAL_StatusTypeDef status;
uint32_t count;
uint32_t algo;
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif /* USE_FULL_ASSERT */
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = pInput;
hcryp->pCrypOutBuffPtr = pOutput;
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
hcryp->Size = Size * 4U;
}
else
{
hcryp->Size = Size;
}
/* Set encryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
/* algo get algorithm selected */
algo = hcryp->Instance->CR & AES_CR_CHMOD;
switch (algo)
{
case CRYP_AES_ECB:
case CRYP_AES_CBC:
case CRYP_AES_CTR:
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG))
{
if (hcryp->Instance == AES)
{
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /* After sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
}
else
{
/* We should re-write Key, in the case where we change key after first operation */
if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
{
/* Set the Key */
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
/* Wait for KEYVALID flag to be set */
count = CRYP_TIMEOUT_KEYPREPARATION;
do
{
count--;
if (count == 0U)
{
/* Disable the SAES peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID));
}
/* Set the Initialization Vector */
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
CRYP_SetIV(hcryp);
}
} /* If (dokeyivconfig == 1U) */
/* Peripheral Key configuration to not do, IV to configure for CBC */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG)
{
if (hcryp->Init.Algorithm == CRYP_AES_CBC)
{
/* Set the Initialization Vector */
CRYP_SetIV(hcryp);
}
}
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Start DMA process transfer for AES */
CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size), (uint32_t)(hcryp->pCrypOutBuffPtr));
status = HAL_OK;
break;
case CRYP_AES_GCM_GMAC:
/* AES GCM encryption */
status = CRYP_AESGCM_Process_DMA(hcryp);
break;
case CRYP_AES_CCM:
/* AES CCM encryption */
status = CRYP_AESCCM_Process_DMA(hcryp);
break;
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
break;
}
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Decryption in DMA mode.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pInput Pointer to the input buffer (ciphertext )
* @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit
* @param pOutput Pointer to the output buffer(plaintext)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput)
{
HAL_StatusTypeDef status;
uint32_t algo;
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif /* USE_FULL_ASSERT */
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = pInput;
hcryp->pCrypOutBuffPtr = pOutput;
/* Calculate Size parameter in Byte*/
if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
{
hcryp->Size = Size * 4U;
}
else
{
hcryp->Size = Size;
}
/* Set decryption operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
/* algo get algorithm selected */
algo = hcryp->Instance->CR & AES_CR_CHMOD;
switch (algo)
{
case CRYP_AES_ECB:
case CRYP_AES_CBC:
case CRYP_AES_CTR:
/* AES decryption */
status = CRYP_AES_Decrypt_DMA(hcryp);
break;
case CRYP_AES_GCM_GMAC:
/* AES GCM decryption */
status = CRYP_AESGCM_Process_DMA(hcryp);
break;
case CRYP_AES_CCM:
/* AES CCM decryption */
status = CRYP_AESCCM_Process_DMA(hcryp);
break;
default:
hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
break;
}
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @}
*/
/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
* @brief CRYP IRQ handler.
*
@verbatim
==============================================================================
##### CRYP IRQ handler management #####
==============================================================================
[..] This section provides CRYP IRQ handler and callback functions.
(+) HAL_CRYP_IRQHandler CRYP interrupt request
(+) HAL_CRYP_InCpltCallback input data transfer complete callback
(+) HAL_CRYP_OutCpltCallback output data transfer complete callback
(+) HAL_CRYP_ErrorCallback CRYP error callback
(+) HAL_CRYP_GetState return the CRYP state
(+) HAL_CRYP_GetError return the CRYP error code
@endverbatim
* @{
*/
/**
* @brief This function handles cryptographic interrupt request.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval None
*/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
{
/* Check if Read or write error occurred */
if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET)
{
/* If write Error occurred */
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
}
/* If read Error occurred */
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF);
}
}
/* Check if Key error occurred */
if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET)
{
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY;
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF);
/*Call weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
}
}
if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET)
{
if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
{
/* Clear computation complete flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM))
{
/* if header phase */
if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
{
CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
}
else /* if payload phase */
{
CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
}
}
else /* AES Algorithm ECB,CBC or CTR*/
{
CRYP_AES_IT(hcryp);
}
}
}
}
/**
* @brief Return the CRYP error code.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for the CRYP peripheral
* @retval CRYP error code
*/
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
{
return hcryp->ErrorCode;
}
/**
* @brief Returns the CRYP state.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @retval HAL state
*/
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
{
return hcryp->State;
}
/**
* @brief Input FIFO transfer completed callback.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @retval None
*/
__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_InCpltCallback could be implemented in the user file
*/
}
/**
* @brief Output FIFO transfer completed callback.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @retval None
*/
__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_OutCpltCallback could be implemented in the user file
*/
}
/**
* @brief CRYP error callback.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @retval None
*/
__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcryp);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CRYP_ErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup CRYP_Private_Functions
* @{
*/
/**
* @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
* @param hcryp pointer to a CRYP_HandleTypeDef structure
* @param Timeout specify Timeout value
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
uint32_t tickstart;
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG))
{
if (hcryp->Instance == AES)
{
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /* After sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
}
else
{
/* We should re-write Key, in the case where we change key after first operation */
if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
{
/* Set the Key */
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
/* Get tick */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
}
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector */
CRYP_SetIV(hcryp);
}
} /* If (dokeyivconfig == 1U) */
/* Peripheral Key configuration to not do, IV to configure for CBC */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG)
{
if (hcryp->Init.Algorithm == CRYP_AES_CBC)
{
/* Set the Initialization Vector*/
CRYP_SetIV(hcryp);
}
}
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
{
/* Write plain data and get cipher data */
CRYP_AES_ProcessData(hcryp, Timeout);
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
}
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
return HAL_OK;
}
/**
* @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t count;
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG))
{
if (hcryp->Instance == AES)
{
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
}
else
{
/* we should re-write Key, in the case where we change key after first operation*/
if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
{
/* Set the Key */
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
/* Wait for KEYVALID flag to be set */
count = CRYP_TIMEOUT_KEYPREPARATION;
do
{
count--;
if (count == 0U)
{
/* Disable the SAES peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID));
}
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector*/
CRYP_SetIV(hcryp);
}
} /* if (dokeyivconfig == 1U) */
/* Peripheral Key configuration to not do, IV to configure for CBC */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG)
{
if (hcryp->Init.Algorithm == CRYP_AES_CBC)
{
/* Set the Initialization Vector*/
CRYP_SetIV(hcryp);
}
}
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
if (hcryp->Size != 0U)
{
/* Enable computation complete flag and Key, Read and Write error interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
else
{
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
}
return HAL_OK;
}
/**
* @brief Decryption in ECB/CBC & CTR mode with AES Standard
* @param hcryp pointer to a CRYP_HandleTypeDef structure
* @param Timeout Specify Timeout value
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if (dokeyivconfig == 1U)
{
if (hcryp->Instance == AES)
{
/* Key preparation for ECB/CBC */
if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
{
/* key preparation for decryption, operating mode 2*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL);
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
/* Set the Key */
if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
{
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
}
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Wait for CCF flag to be raised */
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* Return to decryption operating mode(Mode 3)*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
else /*Algorithm CTR */
{
/* Set the Key */
if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
{
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
}
}
}
else /*SAES*/
{
/* key preparation for decryption, operating mode 2*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
/* we should re-write Key, in the case where we change key after first operation*/
if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
{
if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
}
/* Enable SAES */
__HAL_CRYP_ENABLE(hcryp);
/* Wait for CCF flag to be raised */
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* End of Key preparation for ECB/CBC */
/* Return to decryption operating mode(Mode 3)*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
/* Set IV */
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector*/
CRYP_SetIV(hcryp);
}
} /* if (dokeyivconfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
{
/* Write plain data and get cipher data */
CRYP_AES_ProcessData(hcryp, Timeout);
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
}
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
return HAL_OK;
}
/**
* @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t count;
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if (dokeyivconfig == 1U)
{
if (hcryp->Instance == AES)
{
/* Key preparation for ECB/CBC */
if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
/* key preparation for decryption, operating mode 2*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL);
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
/* Set the Key */
if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
{
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
}
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Wait for CCF flag to be raised */
count = CRYP_TIMEOUT_KEYPREPARATION;
do
{
count--;
if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* Return to decryption operating mode(Mode 3)*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
else /*Algorithm CTR */
{
if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
{
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
}
}
}
else /*SAES*/
{
/* key preparation for decryption, operating mode 2*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
/* we should re-write Key, in the case where we change key after first operation*/
if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
{
if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
}
/* Enable SAES */
__HAL_CRYP_ENABLE(hcryp);
/* Wait for CCF flag to be raised */
count = CRYP_TIMEOUT_KEYPREPARATION;
do
{
count--;
if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* End of Key preparation for ECB/CBC */
/* Return to decryption operating mode(Mode 3)*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
/* Set IV */
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector*/
CRYP_SetIV(hcryp);
}
} /* if (dokeyivconfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
if (hcryp->Size != 0U)
{
/* Enable computation complete flag and error interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
else
{
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
}
return HAL_OK;
}
/**
* @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
{
uint32_t count;
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
}
}
if (dokeyivconfig == 1U)
{
if (hcryp->Instance == AES)
{
/* Key preparation for ECB/CBC */
if (hcryp->Init.Algorithm != CRYP_AES_CTR)
{
/* key preparation for decryption, operating mode 2*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL);
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
/* Set the Key */
if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
{
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
}
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Wait for CCF flag to be raised */
count = CRYP_TIMEOUT_KEYPREPARATION;
do
{
count--;
if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* Return to decryption operating mode(Mode 3)*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
else /*Algorithm CTR */
{
/* Set the Key */
if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
{
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
}
}
}
else /*SAES*/
{
/* key preparation for decryption, operating mode 2*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
/* we should re-write Key, in the case where we change key after first operation*/
if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL))
{
if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
}
/* Enable SAES */
__HAL_CRYP_ENABLE(hcryp);
/* Wait for CCF flag to be raised */
count = CRYP_TIMEOUT_KEYPREPARATION;
do
{
count--;
if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* End of Key preparation for ECB/CBC */
/* Return to decryption operating mode(Mode 3)*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
}
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector*/
CRYP_SetIV(hcryp);
}
} /* if (dokeyivconfig == 1U) */
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
if (hcryp->Size != 0U)
{
/* Set the input and output addresses and start DMA transfer */
CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size), (uint32_t)(hcryp->pCrypOutBuffPtr));
}
else
{
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
}
return HAL_OK;
}
/**
* @brief DMA CRYP input data process complete callback.
* @param hdma DMA handle
* @retval None
*/
static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
{
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
uint32_t loopcounter;
uint32_t headersize_in_bytes;
uint32_t tmp;
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
}; /* 8-bit data type */
/* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
in the DMACR register */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED)
{
/* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */
CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
}
else
{
headersize_in_bytes = hcryp->Init.HeaderSize;
}
if ((headersize_in_bytes % 16U) != 0U)
{
/* Write last words that couldn't be fed by DMA */
hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U);
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
/* If the header size is a multiple of words */
if ((headersize_in_bytes % 4U) == 0U)
{
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
else
{
/* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
loopcounter++;
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
/* Wait for computation completion before moving forward */
CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
} /* if ((headersize_in_bytes % 16U) != 0U) */
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Initiate payload DMA IN and processed data DMA OUT transfers */
(void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp);
}
/* Call input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
* @brief DMA CRYP output data process complete callback.
* @param hdma DMA handle
* @retval None
*/
static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
{
uint32_t count;
uint32_t npblb;
uint32_t lastwordsize;
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t mode;
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable the DMA transfer for output FIFO request by resetting
the DMAOUTEN bit in the CR register */
CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* Last block transfer in case of GCM or CCM with Size not %16*/
if (((hcryp->Size) % 16U) != 0U)
{
/* set CrypInCount and CrypOutCount to exact number of word already computed via DMA */
hcryp->CrypInCount = (hcryp->Size / 16U) * 4U;
hcryp->CrypOutCount = hcryp->CrypInCount;
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
mode = hcryp->Instance->CR & AES_CR_MODE;
if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* Last block optionally pad the data with zeros*/
for (count = 0U; count < lastwordsize; count++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
while (count < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
count++;
}
CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE);
/*Read the output block from the output FIFO */
for (count = 0U; count < 4U; count++)
{
/* Read the output block from the output FIFO and put them in temporary buffer
then get CrypOutBuff from temporary buffer */
temp[count] = hcryp->Instance->DOUTR;
}
count = 0U;
while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count];
hcryp->CrypOutCount++;
count++;
}
}
if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
&& ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
{
/* Disable CRYP (not allowed in GCM)*/
__HAL_CRYP_DISABLE(hcryp);
}
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
/* Call output data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
* @brief DMA CRYP communication error callback.
* @param hdma DMA handle
* @retval None
*/
static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
{
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
/* DMA error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* Call error callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/**
* @brief Set the DMA configuration and start the DMA transfer
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param inputaddr address of the input buffer
* @param Size size of the input and output buffers in words, must be a multiple of 4.
* @param outputaddr address of the output buffer
* @retval None
*/
static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
{
HAL_StatusTypeDef status;
/* Set the CRYP DMA transfer complete callback */
hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
/* Set the DMA input error callback */
hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
/* Set the CRYP DMA transfer complete callback */
hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
/* Set the DMA output error callback */
hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
{
/* Enable CRYP (not allowed in GCM & CCM)*/
__HAL_CRYP_ENABLE(hcryp);
}
/* Enable the DMA input channel */
if ((hcryp->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hcryp->hdmain->LinkedListQueue != NULL) && (hcryp->hdmain->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hcryp->hdmain->LinkedListQueue->Head->\
LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; /* Set DMA data size */
hcryp->hdmain->LinkedListQueue->Head->\
LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr; /* Set DMA source address */
hcryp->hdmain->LinkedListQueue->Head->\
LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hcryp->Instance->DINR; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hcryp->hdmain);
}
else
{
/* Return error status */
status = HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size);
}
if (status != HAL_OK)
{
/* DMA error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
/*Call registered error callback*/
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/* Enable the DMA output channel */
if ((hcryp->hdmaout->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hcryp->hdmaout->LinkedListQueue != NULL) && (hcryp->hdmaout->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = \
Size; /* Set DMA data size */
hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
(uint32_t)&hcryp->Instance->DOUTR; /* Set DMA source address */
hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = \
outputaddr; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hcryp->hdmaout);
}
else
{
/* Return error status */
status = HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size);
}
if (status != HAL_OK)
{
/* DMA error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
/* Call error callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/* Enable In and Out DMA requests */
SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
}
/**
* @brief Set the DMA configuration and start the header DMA transfer
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param inputaddr address of the input buffer
* @param Size size of the input buffer in words, must be a multiple of 4
* @retval None
*/
static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size)
{
HAL_StatusTypeDef status;
/* Set the CRYP DMA transfer complete callback */
hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
/* Set the DMA input error callback */
hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
/* Mark that header is fed to the peripheral in DMA mode */
hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED;
/* Enable the DMA input channel */
if ((hcryp->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hcryp->hdmain->LinkedListQueue != NULL) && (hcryp->hdmain->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hcryp->hdmain->LinkedListQueue->Head->\
LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; /* Set DMA data size */
hcryp->hdmain->LinkedListQueue->Head->\
LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr; /* Set DMA source address */
hcryp->hdmain->LinkedListQueue->Head->\
LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hcryp->Instance->DINR; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hcryp->hdmain);
}
else
{
/* Return error status */
status = HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size);
}
if (status != HAL_OK)
{
/* DMA error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
/* Call error callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/* Enable IN DMA requests */
SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
return status;
}
/**
* @brief Process Data: Write Input data in polling mode and used in AES functions.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Timeout Specify Timeout value
* @retval None
*/
static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t i;
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
/* Wait for CCF flag to be raised */
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
/*Call registered error callback*/
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* Read the output block from the output FIFO and put them in temporary buffer then
get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
}
i = 0U;
while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
i++;
}
}
/**
* @brief Handle CRYP block input/output data handling under interruption.
* @note The function is called under interruption only, once
* interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @retval HAL status
*/
static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t i;
if (hcryp->State == HAL_CRYP_STATE_BUSY)
{
/* Read the output block from the output FIFO and put them in temporary buffer then
get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
}
i = 0U;
while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
i++;
}
if (hcryp->CrypOutCount == (hcryp->Size / 4U))
{
/* Disable Computation Complete flag and errors interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
__HAL_UNLOCK(hcryp);
/* Call Output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
else
{
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/* If suspension flag has been raised, suspend processing
only if not already at the end of the payload */
if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
{
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* reset SuspendRequest */
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
/* Disable Computation Complete Flag and Errors Interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_SUSPENDED;
/* Mark that the payload phase is suspended */
hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
__HAL_UNLOCK(hcryp);
}
else
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
{
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
if (hcryp->CrypInCount == (hcryp->Size / 4U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
}
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
/**
* @brief Writes Key in Key registers.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param KeySize Size of Key
* @note If pKey is NULL, the Key registers are not written.
* @retval None
*/
static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
{
if (hcryp->Init.pKey != NULL)
{
switch (KeySize)
{
case CRYP_KEYSIZE_256B:
hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
break;
case CRYP_KEYSIZE_128B:
hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
break;
default:
break;
}
}
}
/**
* @brief Writes initialization vector in IV registers.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @note If IV is NULL, the IV registers are not written.
* @retval None
*/
static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp)
{
if (hcryp->Init.pInitVect != NULL)
{
/* Set the Initialization Vector*/
hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
}
}
/**
* @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t wordsize = ((uint32_t)hcryp->Size / 4U);
uint32_t npblb;
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t index;
uint32_t lastwordsize;
uint32_t incount; /* Temporary CrypInCount Value */
uint32_t outcount; /* Temporary CrypOutCount Value */
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
if (dokeyivconfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
/****************************** Init phase **********************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
CRYP_SetIV(hcryp);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* just wait for hash computation */
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/************************ Header phase *************************************/
if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
/*************************Payload phase ************************************/
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
} /* if (dokeyivconfig == 1U) */
if ((hcryp->Size % 16U) != 0U)
{
/* recalculate wordsize */
wordsize = ((wordsize / 4U) * 4U);
}
/* Get tick */
tickstart = HAL_GetTick();
/* Write input data and get output Data */
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
while ((incount < wordsize) && (outcount < wordsize))
{
/* Write plain data and get cipher data */
CRYP_AES_ProcessData(hcryp, Timeout);
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state & error code */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
}
if ((hcryp->Size % 16U) != 0U)
{
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
/* Set Npblb in case of AES GCM payload encryption to get right tag*/
if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* last block optionally pad the data with zeros*/
for (index = 0U; index < lastwordsize; index ++)
{
/* Write the last Input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
while (index < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0U;
index++;
}
/* Wait for CCF flag to be raised */
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/*Read the output block from the output FIFO */
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then
get CrypOutBuff from temporary buffer */
temp[index] = hcryp->Instance->DOUTR;
}
for (index = 0U; index < lastwordsize; index++)
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
hcryp->CrypOutCount++;
}
}
return HAL_OK;
}
/**
* @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t count;
uint32_t loopcounter;
uint32_t lastwordsize;
uint32_t npblb;
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
uint32_t headersize_in_bytes;
uint32_t tmp;
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
}; /* 8-bit data type */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
{
CRYP_PhaseProcessingResume(hcryp);
return HAL_OK;
}
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
/* Manage header size given in bytes to handle cases where
header size is not a multiple of 4 bytes */
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
}
else
{
headersize_in_bytes = hcryp->Init.HeaderSize;
}
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
/* Configure Key, IV and process message (header and payload) */
if (dokeyivconfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
/******************************* Init phase *********************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
CRYP_SetIV(hcryp);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* just wait for hash computation */
count = CRYP_TIMEOUT_GCMCCMINITPHASE;
do
{
count--;
if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/***************************** Header phase *********************************/
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable computation complete flag and error interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Select payload phase once the header phase is performed */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
/* Write the payload Input block in the IN FIFO */
if (hcryp->Size == 0U)
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
}
else if (hcryp->Size >= 16U)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
if (hcryp->CrypInCount == (hcryp->Size / 4U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else /* Size < 16Bytes : first block is the last block*/
{
/* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
Workaround is implemented in polling mode, so if last block of
payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
/* Compute the number of padding bytes in last block of payload */
npblb = 16U - ((uint32_t)hcryp->Size);
if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* last block optionally pad the data with zeros*/
for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
while (loopcounter < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
}
/* Enter header data */
/* Cher first whether header length is small enough to enter the full header in one shot */
else if (headersize_in_bytes <= 16U)
{
/* Write header data, padded with zeros if need be */
for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
/* If the header size is a multiple of words */
if ((headersize_in_bytes % 4U) == 0U)
{
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
hcryp->CrypHeaderCount++;
}
}
else
{
/* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
loopcounter++;
hcryp->CrypHeaderCount++ ;
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
hcryp->CrypHeaderCount++;
}
}
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
else
{
/* Write the first input header block in the Input FIFO,
the following header data will be fed after interrupt occurrence */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}
} /* end of if (dokeyivconfig == 1U) */
else /* Key and IV have already been configured,
header has already been processed;
only process here message payload */
{
/* Enable computation complete flag and error interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
/* Write the payload Input block in the IN FIFO */
if (hcryp->Size == 0U)
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
}
else if (hcryp->Size >= 16U)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
if (hcryp->CrypInCount == (hcryp->Size / 4U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else /* Size < 16Bytes : first block is the last block*/
{
/* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
Workaround is implemented in polling mode, so if last block of
payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
/* Compute the number of padding bytes in last block of payload */
npblb = 16U - ((uint32_t)hcryp->Size);
if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* last block optionally pad the data with zeros*/
for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
while (loopcounter < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
}
return HAL_OK;
}
/**
* @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
uint32_t count;
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
if (dokeyivconfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
/*************************** Init phase ************************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
/* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
CRYP_SetIV(hcryp);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* just wait for hash computation */
count = CRYP_TIMEOUT_GCMCCMINITPHASE;
do
{
count--;
if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/************************ Header phase *************************************/
if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
{
return HAL_ERROR;
}
}
else
{
/* Initialization and header phases already done, only do payload phase */
if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
{
return HAL_ERROR;
}
} /* if (DoKeyIVConfig == 1U) */
return HAL_OK;
}
/**
* @brief AES CCM encryption/decryption processing in polling mode
* encrypt/decrypt are performed with authentication preparation.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t wordsize = ((uint32_t)hcryp->Size / 4U);
uint32_t loopcounter;
uint32_t npblb;
uint32_t lastwordsize;
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t incount; /* Temporary CrypInCount Value */
uint32_t outcount; /* Temporary CrypOutCount Value */
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
if (dokeyivconfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
/********************** Init phase ******************************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
/* Set the initialization vector (IV) with B0 */
hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* just wait for hash computation */
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/************************ Header phase *************************************/
/* Header block(B1) : associated data length expressed in bytes concatenated
with Associated Data (A)*/
if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
/*************************Payload phase ************************************/
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Select payload phase once the header phase is performed */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
} /* if (dokeyivconfig == 1U) */
if ((hcryp->Size % 16U) != 0U)
{
/* recalculate wordsize */
wordsize = ((wordsize / 4U) * 4U);
}
/* Get tick */
tickstart = HAL_GetTick();
/* Write input data and get output data */
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
while ((incount < wordsize) && (outcount < wordsize))
{
/* Write plain data and get cipher data */
CRYP_AES_ProcessData(hcryp, Timeout);
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
}
if ((hcryp->Size % 16U) != 0U)
{
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT)
{
/* Set Npblb in case of AES CCM payload decryption to get right tag */
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* Write the last input block in the IN FIFO */
for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0U;
loopcounter++;
}
/* just wait for hash computation */
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then
get CrypOutBuff from temporary buffer */
temp[loopcounter] = hcryp->Instance->DOUTR;
}
for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter];
hcryp->CrypOutCount++;
}
}
return HAL_OK;
}
/**
* @brief AES CCM encryption/decryption process in interrupt mode
* encrypt/decrypt are performed with authentication preparation.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t count;
uint32_t loopcounter;
uint32_t lastwordsize;
uint32_t npblb;
uint32_t mode;
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
uint32_t headersize_in_bytes;
uint32_t tmp;
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
}; /* 8-bit data type */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED))
{
CRYP_PhaseProcessingResume(hcryp);
return HAL_OK;
}
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
/* Configure Key, IV and process message (header and payload) */
if (dokeyivconfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
/********************** Init phase ******************************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
/* Set the initialization vector (IV) with B0 */
hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* just wait for hash computation */
count = CRYP_TIMEOUT_GCMCCMINITPHASE;
do
{
count--;
if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/***************************** Header phase *********************************/
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable computation complete flag and error interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
}
else
{
headersize_in_bytes = hcryp->Init.HeaderSize;
}
if (headersize_in_bytes == 0U) /* Header phase is skipped */
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
if (hcryp->Init.Algorithm == CRYP_AES_CCM)
{
/* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
hcryp->CrypHeaderCount++;
}
/* Write the payload Input block in the IN FIFO */
if (hcryp->Size == 0U)
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
}
else if (hcryp->Size >= 16U)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else /* Size < 4 words : first block is the last block*/
{
/* Compute the number of padding bytes in last block of payload */
npblb = 16U - (uint32_t)hcryp->Size;
mode = hcryp->Instance->CR & AES_CR_MODE;
if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* Last block optionally pad the data with zeros*/
for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
while (loopcounter < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
/* Enter header data */
/* Check first whether header length is small enough to enter the full header in one shot */
else if (headersize_in_bytes <= 16U)
{
/* Last block optionally pad the data with zeros*/
for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}
/* If the header size is a multiple of words */
if ((headersize_in_bytes % 4U) == 0U)
{
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
else
{
/* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
hcryp->CrypHeaderCount++;
loopcounter++;
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
else
{
/* Write the first input header block in the Input FIFO,
the following header data will be fed after interrupt occurrence */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/
} /* end of if (dokeyivconfig == 1U) */
else /* Key and IV have already been configured,
header has already been processed;
only process here message payload */
{
/* Write the payload Input block in the IN FIFO */
if (hcryp->Size == 0U)
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
}
else if (hcryp->Size >= 16U)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else /* Size < 4 words : first block is the last block*/
{
/* Compute the number of padding bytes in last block of payload */
npblb = 16U - (uint32_t)hcryp->Size;
mode = hcryp->Instance->CR & AES_CR_MODE;
if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* Last block optionally pad the data with zeros*/
for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
while (loopcounter < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
/* Call Input transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
return HAL_OK;
}
/**
* @brief AES CCM encryption/decryption process in DMA mode
* encrypt/decrypt are performed with authentication preparation.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
{
uint32_t count;
uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
{
if (hcryp->KeyIVConfig == 1U)
{
/* If the Key and IV configuration has to be done only once
and if it has already been done, skip it */
dokeyivconfig = 0U;
hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
}
else
{
/* If the Key and IV configuration has to be done only once
and if it has not been done already, do it and set KeyIVConfig
to keep track it won't have to be done again next time */
hcryp->KeyIVConfig = 1U;
hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
}
}
else
{
hcryp->SizesSum = hcryp->Size;
}
if (dokeyivconfig == 1U)
{
/* Reset CrypHeaderCount */
hcryp->CrypHeaderCount = 0U;
/********************** Init phase ******************************************/
CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
/* Set the Key */
if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED)
{
CRYP_SetKey(hcryp, hcryp->Init.KeySize);
}
else /*after sharing the key, AES should set KMOD[1:0] to 00.*/
{
hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED;
}
/* Set the initialization vector (IV) with B0 */
hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0);
hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U);
hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U);
hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* just wait for hash computation */
count = CRYP_TIMEOUT_GCMCCMINITPHASE;
do
{
count--;
if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/********************* Header phase *****************************************/
if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
{
return HAL_ERROR;
}
}
else
{
/* Initialization and header phases already done, only do payload phase */
if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
{
return HAL_ERROR;
}
} /* if (DoKeyIVConfig == 1U) */
return HAL_OK;
}
/**
* @brief Sets the payload phase in interrupt mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval state
*/
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t lastwordsize;
uint32_t npblb;
uint32_t mode;
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
uint32_t i;
/***************************** Payload phase *******************************/
/* Read the output block from the output FIFO and put them in temporary buffer then
get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
}
i = 0U;
while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
hcryp->CrypOutCount++;
i++;
}
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size))
{
/* When in CCM with Key and IV configuration skipped, don't disable interruptions */
if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U)))
{
/* Disable computation complete flag and errors interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
}
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
/* Call output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Output complete callback*/
hcryp->OutCpltCallback(hcryp);
#else
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
{
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/* If suspension flag has been raised, suspend processing
only if not already at the end of the payload */
if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
{
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* reset SuspendRequest */
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
/* Disable Computation Complete Flag and Errors Interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_SUSPENDED;
/* Mark that the payload phase is suspended */
hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED;
__HAL_UNLOCK(hcryp);
}
else
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
{
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
}
else /* Last block of payload < 128bit*/
{
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size);
mode = hcryp->Instance->CR & AES_CR_MODE;
if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* Last block optionally pad the data with zeros*/
for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
while (loopcounter < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
}
/**
* @brief Sets the payload phase in DMA mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @retval state
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
uint32_t index;
uint32_t npblb;
uint32_t lastwordsize;
uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t count;
uint32_t reg;
/************************ Payload phase ************************************/
if (hcryp->Size == 0U)
{
/* Process unLocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state and phase */
hcryp->State = HAL_CRYP_STATE_READY;
}
else if (hcryp->Size >= 16U)
{
/*DMA transfer must not include the last block in case of Size is not %16 */
CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)((hcryp->Size / 16U) * 16U),
(uint32_t)(hcryp->pCrypOutBuffPtr));
}
else /* length of input data is < 16 */
{
/* Compute the number of padding bytes in last block of payload */
npblb = 16U - (uint32_t)hcryp->Size;
/* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/
reg = hcryp->Instance->CR & (AES_CR_CHMOD | AES_CR_MODE);
if ((reg == (CRYP_AES_GCM_GMAC | CRYP_OPERATINGMODE_ENCRYPT)) || \
(reg == (CRYP_AES_CCM | CRYP_OPERATINGMODE_DECRYPT)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* last block optionally pad the data with zeros*/
for (index = 0U; index < lastwordsize; index ++)
{
/* Write the last Input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
while (index < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0U;
index++;
}
/* Wait for CCF flag to be raised */
count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
do
{
count-- ;
if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/*Read the output block from the output FIFO */
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary
buffer then get CrypOutBuff from temporary buffer */
temp[index] = hcryp->Instance->DOUTR;
}
for (index = 0U; index < lastwordsize; index++)
{
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
/* Change the CRYP state to ready */
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
}
return HAL_OK;
}
/**
* @brief Sets the header phase in polling mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module(Header & HeaderSize)
* @param Timeout Timeout value
* @retval state
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t loopcounter;
uint32_t size_in_bytes;
uint32_t tmp;
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
size_in_bytes = hcryp->Init.HeaderSize * 4U;
}
else
{
size_in_bytes = hcryp->Init.HeaderSize;
}
if ((size_in_bytes != 0U))
{
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
if ((size_in_bytes % 16U) == 0U)
{
/* No padding */
for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
{
/* Write the input block in the data input register */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
}
}
else
{
/* Write header block in the IN FIFO without last block */
for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
{
/* Write the input block in the data input register */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
}
/* Write last complete words */
for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}
/* If the header size is a multiple of words */
if ((size_in_bytes % 4U) == 0U)
{
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
else
{
/* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
loopcounter++;
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
}
}
else
{
/*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
}
return HAL_OK;
}
/**
* @brief Sets the header phase when using DMA in process
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module(Header & HeaderSize)
* @retval None
*/
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
uint32_t headersize_in_bytes;
uint32_t tmp;
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
}; /* 8-bit data type */
/***************************** Header phase for GCM/GMAC or CCM *********************************/
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
}
else
{
headersize_in_bytes = hcryp->Init.HeaderSize;
}
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* If header size is at least equal to 16 bytes, feed the header through DMA.
If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ),
last bytes feeding and padding will be done in CRYP_DMAInCplt() */
if (headersize_in_bytes >= 16U)
{
/* Initiate header DMA transfer */
if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header),
(uint16_t)((headersize_in_bytes / 16U) * 16U)) != HAL_OK)
{
return HAL_ERROR;
}
}
else
{
if (headersize_in_bytes != 0U)
{
/* Header length is larger than 0 and strictly less than 16 bytes */
/* Write last complete words */
for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
/* If the header size is a multiple of words */
if ((headersize_in_bytes % 4U) == 0U)
{
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
else
{
/* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
loopcounter++;
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
} /* if (headersize_in_bytes != 0U) */
/* Move to payload phase if header length is null or
if the header length was less than 16 and header written by software instead of DMA */
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
/* Initiate payload DMA IN and processed data DMA OUT transfers */
if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK)
{
return HAL_ERROR;
}
} /* if (headersize_in_bytes >= 16U) */
return HAL_OK;
}
/**
* @brief Sets the header phase in interrupt mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module(Header & HeaderSize)
* @retval None
*/
static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
uint32_t lastwordsize;
uint32_t npblb;
uint32_t mode;
uint32_t headersize_in_bytes;
uint32_t tmp;
uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
}; /* 8-bit data type */
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
{
headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
}
else
{
headersize_in_bytes = hcryp->Init.HeaderSize;
}
/***************************** Header phase *********************************/
/* Test whether or not the header phase is over.
If the test below is true, move to payload phase */
if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Select payload phase */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
if (hcryp->Init.Algorithm == CRYP_AES_CCM)
{
/* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
hcryp->CrypHeaderCount++;
}
/* Write the payload Input block in the IN FIFO */
if (hcryp->Size == 0U)
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
}
else if (hcryp->Size >= 16U)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call the input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else /* Size < 4 words : first block is the last block*/
{
/* Compute the number of padding bytes in last block of payload */
npblb = 16U - ((uint32_t)hcryp->Size);
mode = hcryp->Instance->CR & AES_CR_MODE;
if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* Last block optionally pad the data with zeros*/
for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
while (loopcounter < 4U)
{
/* Pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
}
else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U))
{
/* Can enter full 4 header words */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/* If suspension flag has been raised, suspend processing
only if not already at the end of the header */
if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND)
{
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* reset SuspendRequest */
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
/* Disable Computation Complete Flag and Errors Interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_SUSPENDED;
/* Mark that the payload phase is suspended */
hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED;
__HAL_UNLOCK(hcryp);
}
else
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
{
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}
}
else /* Write last header block (4 words), padded with zeros if needed */
{
for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
/* If the header size is a multiple of words */
if ((headersize_in_bytes % 4U) == 0U)
{
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
hcryp->CrypHeaderCount++;
}
}
else
{
/* Enter last bytes, padded with zeros */
tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
hcryp->Instance->DINR = tmp;
loopcounter++;
hcryp->CrypHeaderCount++;
/* Pad the data with zeros to have a complete block */
while (loopcounter < 4U)
{
hcryp->Instance->DINR = 0x0U;
loopcounter++;
hcryp->CrypHeaderCount++;
}
}
}
}
/**
* @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Timeout Timeout duration.
* @note This function can only be used in thread mode.
* @retval HAL status
*/
static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t tickstart;
/* Get timeout */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
__HAL_CRYP_DISABLE(hcryp);
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
return HAL_OK;
}
/**
* @brief Wait for Computation Complete Flag (CCF) to raise then clear it.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Timeout Timeout duration.
* @note This function can be used in thread or handler mode.
* @retval HAL status
*/
static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t count = Timeout;
do
{
count-- ;
if (count == 0U)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
hcryp->State = HAL_CRYP_STATE_READY;
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
} while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
}
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/**
* @brief In case of message processing suspension, read the Initialization Vector.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Output Pointer to the buffer containing the saved Initialization Vector.
* @note This value has to be stored for reuse by writing the AES_IVRx registers
* as soon as the suspended processing has to be resumed.
* @retval None
*/
static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output)
{
uint32_t outputaddr = (uint32_t)Output;
*(uint32_t *)(outputaddr) = hcryp->Instance->IVR3;
outputaddr += 4U;
*(uint32_t *)(outputaddr) = hcryp->Instance->IVR2;
outputaddr += 4U;
*(uint32_t *)(outputaddr) = hcryp->Instance->IVR1;
outputaddr += 4U;
*(uint32_t *)(outputaddr) = hcryp->Instance->IVR0;
}
/**
* @brief In case of message processing resumption, rewrite the Initialization
* Vector in the AES_IVRx registers.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Input Pointer to the buffer containing the saved Initialization Vector to
* write back in the CRYP hardware block.
* @note AES must be disabled when reconfiguring the IV values.
* @retval None
*/
static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input)
{
uint32_t ivaddr = (uint32_t)Input;
hcryp->Instance->IVR3 = *(uint32_t *)(ivaddr);
ivaddr += 4U;
hcryp->Instance->IVR2 = *(uint32_t *)(ivaddr);
ivaddr += 4U;
hcryp->Instance->IVR1 = *(uint32_t *)(ivaddr);
ivaddr += 4U;
hcryp->Instance->IVR0 = *(uint32_t *)(ivaddr);
}
/**
* @brief In case of message GCM/GMAC/CCM processing suspension,
* read the Suspend Registers.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Output Pointer to the buffer containing the saved Suspend Registers.
* @note These values have to be stored for reuse by writing back the AES_SUSPxR registers
* as soon as the suspended processing has to be resumed.
* @retval None
*/
static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output)
{
uint32_t outputaddr = (uint32_t)Output;
uint32_t count = 0U;
/* In case of GCM payload phase encryption, check that suspension can be carried out */
if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC |
AES_CR_GCMPH_1 | 0x0))
{
/* Wait for BUSY flag to be cleared */
count = 0xFFF;
do
{
count--;
if (count == 0U)
{
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
HAL_CRYP_ErrorCallback(hcryp);
return;
}
} while (HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY));
}
*(uint32_t *)(outputaddr) = hcryp->Instance->SUSP7R;
outputaddr += 4U;
*(uint32_t *)(outputaddr) = hcryp->Instance->SUSP6R;
outputaddr += 4U;
*(uint32_t *)(outputaddr) = hcryp->Instance->SUSP5R;
outputaddr += 4U;
*(uint32_t *)(outputaddr) = hcryp->Instance->SUSP4R;
outputaddr += 4U;
*(uint32_t *)(outputaddr) = hcryp->Instance->SUSP3R;
outputaddr += 4U;
*(uint32_t *)(outputaddr) = hcryp->Instance->SUSP2R;
outputaddr += 4U;
*(uint32_t *)(outputaddr) = hcryp->Instance->SUSP1R;
outputaddr += 4U;
*(uint32_t *)(outputaddr) = hcryp->Instance->SUSP0R;
}
/**
* @brief In case of message GCM/GMAC/CCM processing resumption, rewrite the Suspend
* Registers in the AES_SUSPxR registers.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Input Pointer to the buffer containing the saved suspend registers to
* write back in the CRYP hardware block.
* @note AES must be disabled when reconfiguring the suspend registers.
* @retval None
*/
static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input)
{
uint32_t ivaddr = (uint32_t)Input;
hcryp->Instance->SUSP7R = *(uint32_t *)(ivaddr);
ivaddr += 4U;
hcryp->Instance->SUSP6R = *(uint32_t *)(ivaddr);
ivaddr += 4U;
hcryp->Instance->SUSP5R = *(uint32_t *)(ivaddr);
ivaddr += 4U;
hcryp->Instance->SUSP4R = *(uint32_t *)(ivaddr);
ivaddr += 4U;
hcryp->Instance->SUSP3R = *(uint32_t *)(ivaddr);
ivaddr += 4U;
hcryp->Instance->SUSP2R = *(uint32_t *)(ivaddr);
ivaddr += 4U;
hcryp->Instance->SUSP1R = *(uint32_t *)(ivaddr);
ivaddr += 4U;
hcryp->Instance->SUSP0R = *(uint32_t *)(ivaddr);
}
/**
* @brief In case of message GCM/GMAC/CCM processing suspension, read the Key Registers.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Output Pointer to the buffer containing the saved Key Registers.
* @param KeySize Indicates the key size (128 or 256 bits).
* @note These values have to be stored for reuse by writing back the AES_KEYRx registers
* as soon as the suspended processing has to be resumed.
* @retval None
*/
static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output, uint32_t KeySize)
{
uint32_t keyaddr = (uint32_t)Output;
switch (KeySize)
{
case CRYP_KEYSIZE_256B:
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
keyaddr += 4U;
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
keyaddr += 4U;
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
keyaddr += 4U;
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
keyaddr += 4U;
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U);
keyaddr += 4U;
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U);
keyaddr += 4U;
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U);
keyaddr += 4U;
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U);
break;
case CRYP_KEYSIZE_128B:
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey);
keyaddr += 4U;
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U);
keyaddr += 4U;
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U);
keyaddr += 4U;
*(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U);
break;
default:
break;
}
}
/**
* @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key
* Registers in the AES_KEYRx registers.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module.
* @param Input Pointer to the buffer containing the saved key registers to
* write back in the CRYP hardware block.
* @param KeySize Indicates the key size (128 or 256 bits)
* @note AES must be disabled when reconfiguring the Key registers.
* @retval None
*/
static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input, uint32_t KeySize)
{
uint32_t keyaddr = (uint32_t)Input;
if (KeySize == CRYP_KEYSIZE_256B)
{
hcryp->Instance->KEYR7 = *(uint32_t *)(keyaddr);
keyaddr += 4U;
hcryp->Instance->KEYR6 = *(uint32_t *)(keyaddr);
keyaddr += 4U;
hcryp->Instance->KEYR5 = *(uint32_t *)(keyaddr);
keyaddr += 4U;
hcryp->Instance->KEYR4 = *(uint32_t *)(keyaddr);
keyaddr += 4U;
}
hcryp->Instance->KEYR3 = *(uint32_t *)(keyaddr);
keyaddr += 4U;
hcryp->Instance->KEYR2 = *(uint32_t *)(keyaddr);
keyaddr += 4U;
hcryp->Instance->KEYR1 = *(uint32_t *)(keyaddr);
keyaddr += 4U;
hcryp->Instance->KEYR0 = *(uint32_t *)(keyaddr);
}
/**
* @brief Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module(Header & HeaderSize)
* @retval None
*/
static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
uint16_t lastwordsize;
uint16_t npblb;
uint32_t cr_temp;
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF | CRYP_CLEAR_CCF);
/* Enable computation complete flag and error interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* Case of header phase resumption =================================================*/
if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U))
{
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}
else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
{
/* Last block optionally pad the data with zeros*/
for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++;
}
while (loopcounter < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
}
/* Case of payload phase resumption =================================================*/
else
{
if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)
{
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Select payload phase once the header phase is performed */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
{
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
{
/* Call output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else /* Last block of payload < 128bit*/
{
/* Compute the number of padding bytes in last block of payload */
npblb = (((hcryp->Size / 16U) + 1U) * 16U) - (hcryp->Size);
cr_temp = hcryp->Instance->CR;
if ((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
(((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb) << 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* Last block optionally pad the data with zeros*/
for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
while (loopcounter < 4U)
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
}
}
}
}
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
/**
* @}
*/
#endif /* HAL_CRYP_MODULE_ENABLED */
#endif /* AES */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c
|
C
|
apache-2.0
| 199,150
|
/**
******************************************************************************
* @file stm32u5xx_hal_cryp_ex.c
* @author MCD Application Team
* @brief CRYPEx HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the Cryptography (CRYP) peripheral.
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup CRYPEx
* @{
*/
#if defined(AES)
#ifdef HAL_CRYP_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup CRYPEx_Private_Defines
* @{
*/
#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions */
#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions */
#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
/* CTR0 information to use in CCM algorithm */
#define CRYP_CCM_CTR0_0 0x07FFFFFFU
#define CRYP_CCM_CTR0_3 0xFFFFFF00U
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
static void CRYPEx_SetKey(const CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
/* Exported functions---------------------------------------------------------*/
/** @addtogroup CRYPEx_Exported_Functions
* @{
*/
/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
* @brief Extended processing functions.
*
@verbatim
==============================================================================
##### Extended AES processing functions #####
==============================================================================
[..] This section provides functions allowing to generate the authentication
TAG in Polling mode
(#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
(#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
they should be used after Encrypt/Decrypt operation.
@endverbatim
* @{
*/
/**
* @brief generate the GCM authentication TAG.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pAuthTag Pointer to the authentication buffer
* the pAuthTag generated here is 128bits length, if the TAG length is
* less than 128bits, user should consider only the valid part of pAuthTag
* buffer which correspond exactly to TAG length.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout)
{
/* Assume first Init.HeaderSize is in words */
uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
uint32_t tagaddr = (uint32_t)pAuthTag;
uint32_t i;
uint32_t tickstart;
/* Correct headerlength if Init.HeaderSize is actually in bytes */
if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
{
headerlength /= 4U;
}
if (hcryp->State == HAL_CRYP_STATE_READY)
{
__HAL_LOCK(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Check if initialization phase has already been performed */
if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
/* Select final phase */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
/* Set the encrypt operating mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
/* Write into the AES_DINR register the number of bits in header (64 bits)
followed by the number of bits in the payload */
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = (uint32_t)(headerlength);
hcryp->Instance->DINR = 0U;
hcryp->Instance->DINR = (uint32_t)(inputlength);
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
/* Read the authentication TAG in the output FIFO */
for (i = 0U; i < 4U; i++)
{
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr += 4U;
}
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* Disable the peripheral */
__HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
}
else /* Initialization phase has not been performed */
{
/* Disable the Peripheral */
__HAL_CRYP_DISABLE(hcryp);
/* Sequence error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
/**
* @brief AES CCM Authentication TAG generation.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pAuthTag Pointer to the authentication buffer
* the pAuthTag generated here is 128bits length, if the TAG length is
* less than 128bits, user should consider only the valid part of pAuthTag
* buffer which correspond exactly to TAG length.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *pAuthTag, uint32_t Timeout)
{
uint32_t tagaddr = (uint32_t)pAuthTag;
uint32_t i;
uint32_t tickstart;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
__HAL_LOCK(hcryp);
/* Disable interrupts in case they were kept enabled to proceed
a single message in several iterations */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Check if initialization phase has already been performed */
if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
/* Select final phase */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
/* Set encrypt operating mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
/* Read the authentication TAG in the output FIFO */
for (i = 0U; i < 4U; i++)
{
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
tagaddr += 4U;
}
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
}
else /* Initialization phase has not been performed */
{
/* Disable the peripheral */
__HAL_CRYP_DISABLE(hcryp);
/* Sequence error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
else
{
/* Busy error code field */
hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup CRYPEx_Exported_Functions_Group2 Wrap and Unwrap key functions
* @brief Wrap and Unwrap key functions.
*
@verbatim
==============================================================================
##### Wrap and Unwrap key #####
==============================================================================
[..] This section provides API allowing to wrap (encrypt) and unwrap (decrypt)
key using one of the following keys, and AES Algorithm.
Key selection :
- Derived hardware unique key (DHUK)
- XOR of DHUK and BHK
- Boot hardware key (BHK)
- Key registers AES_KEYx
@endverbatim
* @{
*/
/**
* @brief Wrap (encrypt) application keys.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pInput Pointer to the Key buffer to encrypt
* @param pOutput Pointer to the Key buffer encrypted
* @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t *pOutput, uint32_t Timeout)
{
HAL_StatusTypeDef status;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = pInput;
hcryp->pCrypOutBuffPtr = pOutput;
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Set the operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
status = CRYPEx_KeyEncrypt(hcryp, Timeout);
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @brief Unwrap (Decrypt) application keys.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pInput Pointer to the Key buffer to decrypt
* @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t Timeout)
{
HAL_StatusTypeDef status;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = pInput;
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Set the operating mode*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED);
status = CRYPEx_KeyDecrypt(hcryp, Timeout);
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @}
*/
/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions
* @brief Encrypt and Decrypt Shared key functions.
*
@verbatim
==============================================================================
##### Encrypt and Decrypt Shared key functions #####
==============================================================================
[..] This section provides API allowing to Encrypt and Decrypt Shared key
@endverbatim
* @{
*/
/**
* @brief Encrypt Shared key.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pKey Pointer to the Key buffer to share
* @param pOutput Pointer to the Key buffer encrypted
* @param ID Key share identification
* @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t *pOutput, uint32_t ID,
uint32_t Timeout)
{
HAL_StatusTypeDef status;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = pKey;
hcryp->pCrypOutBuffPtr = pOutput;
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Set the operating mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID);
status = CRYPEx_KeyEncrypt(hcryp, Timeout);
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @brief Decrypt Shared key.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param pKey Pointer to the Key buffer to share
* @param ID Key share identification
* @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t ID, uint32_t Timeout)
{
HAL_StatusTypeDef status;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Change state Busy */
hcryp->State = HAL_CRYP_STATE_BUSY;
__HAL_LOCK(hcryp);
/* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */
hcryp->CrypInCount = 0U;
hcryp->CrypOutCount = 0U;
hcryp->pCrypInBuffPtr = pKey;
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Set the operating mode */
MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID);
status = CRYPEx_KeyDecrypt(hcryp, Timeout);
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup CRYP_Private_Functions
* @{
*/
/**
* @brief Key Decryption
* @param hcryp pointer to a CRYP_HandleTypeDef structure
* @param Timeout specify Timeout value
* @note It is strongly recommended to select hardware secret keys
* @retval HAL status
*/
static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t incount; /* Temporary CrypInCount Value */
uint32_t i;
uint32_t tickstart;
/* key preparation for decryption, operating mode 2*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
/* It is strongly recommended to select hardware secret keys */
if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL)
{
/* Set the Key */
CRYPEx_SetKey(hcryp, hcryp->Init.KeySize);
}
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* End of Key preparation for ECB/CBC */
/* Return to decryption operating mode(Mode 3)*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector */
hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
}
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = CRYPEx_PHASE_PROCESS;
if (hcryp->Init.KeySize == CRYP_KEYSIZE_128B)
{
incount = 4U;
}
else
{
incount = 8U;
}
while (hcryp->CrypInCount < incount)
{
/* Write four times to input the key to encrypt */
for (i = 0U; i < 4U; i++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
}
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_OK;
}
/**
* @brief Key Encryption
* @param hcryp pointer to a CRYP_HandleTypeDef structure
* @param Timeout specify Timeout value
* @retval HAL status
*/
static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t incount; /* Temporary CrypInCount Value */
uint32_t i;
uint32_t tickstart;
uint32_t temp; /* Temporary CrypOutBuff */
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
if (hcryp->Init.Algorithm != CRYP_AES_ECB)
{
/* Set the Initialization Vector */
hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
}
/* It is strongly recommended to select hardware secret keys */
if (hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL)
{
/* Set the Key */
CRYPEx_SetKey(hcryp, hcryp->Init.KeySize);
}
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for Valid KEY flag to set */
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_KEYVALID))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
/* Enable CRYP */
__HAL_CRYP_ENABLE(hcryp);
/* Set the phase */
hcryp->Phase = CRYPEx_PHASE_PROCESS;
if (hcryp->Init.KeySize == CRYP_KEYSIZE_128B)
{
incount = 4U;
}
else
{
incount = 8U;
}
while (hcryp->CrypInCount < incount)
{
for (i = 0U; i < 4U; i++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
/* Wait for CCF flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF);
/* Read the output block from the output FIFO and put them in temporary buffer then
get CrypOutBuff from temporary buffer */
for (i = 0U; i < 4U; i++)
{
temp = hcryp->Instance->DOUTR;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
hcryp->CrypOutCount++;
}
}
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
__HAL_UNLOCK(hcryp);
return HAL_OK;
}
/**
* @brief Write Key in Key registers.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param KeySize Size of Key
* @note If pKey is NULL, the Key registers are not written.
* @retval None
*/
static void CRYPEx_SetKey(const CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
{
if (hcryp->Init.pKey != NULL)
{
switch (KeySize)
{
case CRYP_KEYSIZE_256B:
hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U);
hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U);
hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U);
hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U);
hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U);
hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U);
hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U);
break;
case CRYP_KEYSIZE_128B:
hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U);
hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U);
hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U);
break;
default:
break;
}
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CRYP_MODULE_ENABLED */
#endif /* AES */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c
|
C
|
apache-2.0
| 25,256
|
/**
******************************************************************************
* @file stm32u5xx_hal_dac.c
* @author MCD Application Team
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### DAC Peripheral features #####
==============================================================================
[..]
*** DAC Channels ***
====================
[..]
STM32U5 devices integrate two 12-bit Digital Analog Converters
The 2 converters (i.e. channel1 & channel2)
can be used independently or simultaneously (dual mode):
(#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
peripherals (ex. ADC).
(#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
peripherals (ex. ADC).
*** DAC Triggers ***
====================
[..]
Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
[..]
Digital to Analog conversion can be triggered by:
(#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
The used pin (GPIOx_PIN_9) must be configured in input mode.
(#) Timers TRGO: TIM1, TIM2, TIM4, TIM5, TIM6, TIM7, TIM8 and TIM15
(DAC_TRIGGER_T1_TRGO, DAC_TRIGGER_T2_TRGO...)
(#) Low Power Timers TRGO: LPTIM1 and LPTIM3
(DAC_TRIGGER_LPTIM1_OUT, DAC_TRIGGER_LPTIM3_OUT)
(#) Software using DAC_TRIGGER_SOFTWARE
[..]
The trigger selection depends on the PWR mode:
in stop0, stop1 and stop2 we should select DAC_TRIGGER_EXT_IT9,
DAC_TRIGGER_LPTIM1_OUT or DAC_TRIGGER_LPTIM3_OUT.The other triggers
are not functional.
*** DAC Buffer mode feature ***
===============================
[..]
Each DAC channel integrates an output buffer that can be used to
reduce the output impedance, and to drive external loads directly
without having to add an external operational amplifier.
To enable, the output buffer use
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
[..]
(@) Refer to the device datasheet for more details about output
impedance value with and without output buffer.
*** GPIO configurations guidelines ***
=====================
[..]
When a DAC channel is used (ex channel1 on PA4) and the other is not
(ex channel2 on PA5 is configured in Analog and disabled).
Channel1 may disturb channel2 as coupling effect.
Note that there is no coupling on channel2 as soon as channel2 is turned on.
Coupling on adjacent channel could be avoided as follows:
when unused PA5 is configured as INPUT PULL-UP or DOWN.
PA5 is configured in ANALOG just before it is turned on.
*** DAC Sample and Hold feature ***
========================
[..]
For each converter, 2 modes are supported: normal mode and
"sample and hold" mode (i.e. low power mode).
In the sample and hold mode, the DAC core converts data, then holds the
converted voltage on a capacitor. When not converting, the DAC cores and
buffer are completely turned off between samples and the DAC output is
tri-stated, therefore reducing the overall power consumption. A new
stabilization period is needed before each new conversion.
The sample and hold allow setting internal or external voltage @
low power consumption cost (output value can be at any given rate either
by CPU or DMA).
The Sample and hold block and registers uses either LSI & run in
several power modes: run mode, sleep mode, low power run, low power sleep
mode & stop1 mode.
Low power stop1 mode allows only static conversion.
To enable Sample and Hold mode
Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
RCC_LSI_ON parameters.
Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
& DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
DAC_HoldTime & DAC_RefreshTime;
*** DAC calibration feature ***
===================================
[..]
(#) The 2 converters (channel1 & channel2) provide calibration capabilities.
(++) Calibration aims at correcting some offset of output buffer.
(++) The DAC uses either factory calibration settings OR user defined
calibration (trimming) settings (i.e. trimming mode).
(++) The user defined settings can be figured out using self calibration
handled by HAL_DACEx_SelfCalibrate.
(++) HAL_DACEx_SelfCalibrate:
(+++) Runs automatically the calibration.
(+++) Enables the user trimming mode
(+++) Updates a structure with trimming values with fresh calibration
results.
The user may store the calibration results for larger
(ex monitoring the trimming as a function of temperature
for instance)
*** DAC wave generation feature ***
===================================
[..]
Both DAC channels can be used to generate
(#) Noise wave
(#) Triangle wave
*** DAC data format ***
=======================
[..]
The DAC data format can be:
(#) 8-bit right alignment using DAC_ALIGN_8B_R
(#) 12-bit left alignment using DAC_ALIGN_12B_L
(#) 12-bit right alignment using DAC_ALIGN_12B_R
*** DAC data value to voltage correspondence ***
================================================
[..]
The analog output voltage on each DAC channel pin is determined
by the following equation:
[..]
DAC_OUTx = VREF+ * DOR / 4095
(+) with DOR is the Data Output Register
[..]
VREF+ is the input voltage reference (refer to the device datasheet)
[..]
e.g. To set DAC_OUT1 to 0.7V, use
(+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
*** DMA requests ***
=====================
[..]
A DMA request can be generated when an external trigger (but not a software trigger)
occurs if DMA requests are enabled using HAL_DAC_Start_DMA().
DMA requests are mapped as following:
GPDMA requests are mapped as following:
(+) DAC channel1 mapped on GPDMA request 2 (can be any GPDMA channel)
(+) DAC channel2 mapped on GPDMA request 3 (can be any GPDMA channel)
LPDMA requests are mapped as following:
(+) DAC channel1 mapped on LPDMA request 8 (can be any LPDMA channel)
(+) DAC channel2 mapped on LPDMA request 9 (can be any LPDMA channel)
*** High frequency interface mode ***
=====================================
[..]
The high frequency interface informs DAC instance about the bus frequency in use.
It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent)
provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function.
Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended
function figured out the correct setting.
The high frequency mode is same for all converters of a same DAC instance. Either same
parameter DAC_HighFrequency is used for all DAC converters or again self
DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter.
[..]
(@) For Dual mode and specific signal (Triangle and noise) generation please
refer to Extended Features Driver description
##### How to use this driver #####
==============================================================================
[..]
(+) DAC APB clock must be enabled to get write access to DAC
registers using HAL_DAC_Init()
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
(+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
(+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
*** Calibration mode IO operation ***
======================================
[..]
(+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
(+) Run the calibration using HAL_DACEx_SelfCalibrate()
(+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
*** Polling mode IO operation ***
=================================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start()
(+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
(+) Stop the DAC peripheral using HAL_DAC_Stop()
*** DMA mode IO operation ***
==============================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
of data to be transferred at each end of conversion
First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
(+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
function is executed and user can add his own code by customization of function pointer
HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
function is executed and user can add his own code by customization of function pointer
HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
(+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
(+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
function is executed and user can add his own code by customization of function pointer
HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
(+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
(+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
(+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
(+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
(+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
(+) MspInitCallback : DAC MspInit.
(+) MspDeInitCallback : DAC MspdeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
(+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
(+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
(+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
(+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
(+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
(+) MspInitCallback : DAC MspInit.
(+) MspDeInitCallback : DAC MspdeInit.
(+) All Callbacks
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
or @ref HAL_DAC_Init function.
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DAC HAL driver.
(+) __HAL_DAC_ENABLE : Enable the DAC peripheral
(+) __HAL_DAC_DISABLE : Disable the DAC peripheral
(+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
(+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
[..]
(@) You can refer to the DAC HAL driver header file for more useful macros
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_DAC_MODULE_ENABLED
#if defined(DAC1)
/** @defgroup DAC DAC
* @brief DAC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DAC_Private_Constants DAC Private Constants
* @{
*/
#define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */
#define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */
#define HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /* 160 MHz */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions -------------------------------------------------------*/
/** @defgroup DAC_Exported_Functions DAC Exported Functions
* @{
*/
/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DAC.
(+) De-initialize the DAC.
@endverbatim
* @{
*/
/**
* @brief Initialize the DAC peripheral according to the specified parameters
* in the DAC_InitStruct and initialize the associated handle.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
{
/* Check DAC handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
if (hdac->State == HAL_DAC_STATE_RESET)
{
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the DAC Callback settings */
hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
if (hdac->MspInitCallback == NULL)
{
hdac->MspInitCallback = HAL_DAC_MspInit;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the low level hardware */
hdac->MspInitCallback(hdac);
#else
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_BUSY;
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Deinitialize the DAC peripheral registers to their default reset values.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
{
/* Check DAC handle */
if (hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
if (hdac->MspDeInitCallback == NULL)
{
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
}
/* DeInit the low level hardware */
hdac->MspDeInitCallback(hdac);
#else
/* DeInit the low level hardware */
HAL_DAC_MspDeInit(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
/* Change DAC state */
hdac->State = HAL_DAC_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the DAC MSP.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the DAC MSP.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Start conversion.
(+) Stop conversion.
(+) Start conversion and enable DMA transfer.
(+) Stop conversion and disable DMA transfer.
(+) Get result of conversion.
@endverbatim
* @{
*/
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
/* Ensure minimum wait before using peripheral after enabling it */
HAL_Delay(1);
if (Channel == DAC_CHANNEL_1)
{
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
{
/* Enable the selected DAC software conversion */
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
}
}
else
{
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
{
/* Enable the selected DAC software conversion*/
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
}
}
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables DAC and stop conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
/* Ensure minimum wait before enabling peripheral after disabling it */
HAL_Delay(1);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
HAL_StatusTypeDef status;
uint32_t tmpreg;
uint32_t LengthInBytes;
DMA_NodeConfTypeDef node_conf;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
if (Channel == DAC_CHANNEL_1)
{
/* Set the DMA transfer complete callback for channel1 */
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
/* Set the DMA half transfer complete callback for channel1 */
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
/* Set the DMA error callback for channel1 */
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
/* Case of use of channel 1 */
switch (Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
break;
default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
break;
}
}
else
{
/* Set the DMA transfer complete callback for channel2 */
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
/* Set the DMA half transfer complete callback for channel2 */
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
/* Set the DMA error callback for channel2 */
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
/* Enable the selected DAC channel2 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
/* Case of use of channel 2 */
switch (Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
break;
default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
break;
}
}
/* Enable the DMA channel */
if (Channel == DAC_CHANNEL_1)
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
/* Enable the DMA channel */
/* Check linkedlist mode */
if ((hdac->DMA_Handle1->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hdac->DMA_Handle1->LinkedListQueue != NULL) && (hdac->DMA_Handle1->LinkedListQueue->Head != NULL))
{
/* Length should be converted to number of bytes */
if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hdac->DMA_Handle1->LinkedListQueue->Head) != HAL_OK)
{
return HAL_ERROR;
}
/* Length should be converted to number of bytes */
if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
{
/* Word -> Bytes */
LengthInBytes = Length * 4U;
}
else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
{
/* Halfword -> Bytes */
LengthInBytes = Length * 2U;
}
else /* Bytes */
{
/* Same size already expressed in Bytes */
LengthInBytes = Length;
}
/* Set DMA data size */
hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
/* Set DMA source address */
hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
/* Enable the DMA channel */
status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle1);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
/* Length should be converted to number of bytes */
if (hdac->DMA_Handle1->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
{
/* Word -> Bytes */
LengthInBytes = Length * 4U;
}
else if (hdac->DMA_Handle1->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
{
/* Halfword -> Bytes */
LengthInBytes = Length * 2U;
}
else /* Bytes */
{
/* Same size already expressed in Bytes */
LengthInBytes = Length;
}
/* Enable the DMA channel */
status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, LengthInBytes);
}
}
else
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
/* Enable the DMA channel */
/* Check linkedlist mode */
if ((hdac->DMA_Handle2->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hdac->DMA_Handle2->LinkedListQueue != NULL) && (hdac->DMA_Handle2->LinkedListQueue->Head != NULL))
{
/* Length should be converted to number of bytes */
if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hdac->DMA_Handle2->LinkedListQueue->Head) != HAL_OK)
{
return HAL_ERROR;
}
/* Length should be converted to number of bytes */
if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
{
/* Word -> Bytes */
LengthInBytes = Length * 4U;
}
else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
{
/* Halfword -> Bytes */
LengthInBytes = Length * 2U;
}
else /* Bytes */
{
/* Same size already expressed in Bytes */
LengthInBytes = Length;
}
/* Set DMA data size */
hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
/* Set DMA source address */
hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
/* Enable the DMA channel */
status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle2);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
/* Length should be converted to number of bytes */
if (hdac->DMA_Handle2->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
{
/* Word -> Bytes */
LengthInBytes = Length * 4U;
}
else if (hdac->DMA_Handle2->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
{
/* Halfword -> Bytes */
LengthInBytes = Length * 2U;
}
else /* Bytes */
{
/* Same size already expressed in Bytes */
LengthInBytes = Length;
}
/* Enable the DMA channel */
status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, LengthInBytes);
}
}
/* Process Unlocked */
__HAL_UNLOCK(hdac);
if (status == HAL_OK)
{
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
/* Ensure minimum wait before using peripheral after enabling it */
HAL_Delay(1);
}
else
{
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
}
/* Return function status */
return status;
}
/**
* @brief Disables DAC and stop conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Disable the selected DAC channel DMA request */
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
/* Ensure minimum wait before enabling peripheral after disabling it */
HAL_Delay(1);
/* Disable the DMA channel */
/* Channel1 is used */
if (Channel == DAC_CHANNEL_1)
{
/* Disable the DMA channel */
(void)HAL_DMA_Abort(hdac->DMA_Handle1);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
}
else /* Channel2 is used for */
{
/* Disable the DMA channel */
(void)HAL_DMA_Abort(hdac->DMA_Handle2);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Handles DAC interrupt request
* This function uses the interruption of DMA
* underrun.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
{
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
{
/* Check underrun flag of DAC channel 1 */
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
/* Set DAC error code to channel1 DMA underrun error */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
/* Disable the selected DAC channel1 DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh1(hdac);
#else
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
{
/* Check underrun flag of DAC channel 2 */
if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
/* Set DAC error code to channel2 DMA underrun error */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
/* Disable the selected DAC channel2 DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh2(hdac);
#else
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
}
/**
* @brief Set the specified data holding register value for DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Alignment Specifies the data alignment.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data Data to be loaded in the selected data holding register.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
__IO uint32_t tmp = 0UL;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
/* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */
if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL)
{
assert_param(IS_DAC_DATA(Data));
}
tmp = (uint32_t)hdac->Instance;
if (Channel == DAC_CHANNEL_1)
{
tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
}
else
{
tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
}
/* Set the DAC channel selected data holding register */
*(__IO uint32_t *) tmp = Data;
/* Return function status */
return HAL_OK;
}
/**
* @brief Conversion complete callback in non-blocking mode for Channel1
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
*/
}
/**
* @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
*/
}
/**
* @brief Error DAC callback for Channel1.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
*/
}
/**
* @brief DMA underrun DAC callback for channel1.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Configure channels.
(+) Set the specified data holding register value for DAC channel.
@endverbatim
* @{
*/
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Returns the DAC channel data output register value */
if (Channel == DAC_CHANNEL_1)
{
return hdac->Instance->DOR1;
}
else
{
return hdac->Instance->DOR2;
}
}
/**
* @brief Configures the selected DAC channel.
* @note By calling this function, if the application will be run in stop
* mode, the DAC_Trigger field of the structure sConfig
* should be one of the following values:
* - DAC_TRIGGER_STOP_LPTIM1_OUT
* - DAC_TRIGGER_STOP_LPTIM3_OUT
* - DAC_TRIGGER_STOP_EXT_IT9
* For application where DAC is not run in stop mode, the DAC trigger
* should be a value of @ref DAC_trigger_selection
* @note By calling this function, the high frequency interface mode (HFSEL bits)
* will be set. This parameter scope is the DAC instance. As the function
* is called for each channel, the @ref DAC_HighFrequency of @arg sConfig
* must be the same at each call.
* (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect).
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig DAC configuration structure.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
uint32_t tmpreg1;
uint32_t tmpreg2;
uint32_t tickstart;
uint32_t hclkfreq;
uint32_t connectOnChip;
/* Check the DAC parameters */
assert_param(IS_DAC_AUTONOMOUS(sConfig->DAC_AutonomousMode));
assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency));
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
{
assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
}
assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
{
assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
}
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode));
assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Sample and hold configuration */
if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
{
/* Get timeout */
tickstart = HAL_GetTick();
if (Channel == DAC_CHANNEL_1)
{
/* SHSR1 can be written when BWST1 is cleared */
while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* New check to avoid false timeout detection in case of preemption */
if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
HAL_Delay(1);
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
else /* Channel 2 */
{
/* SHSR2 can be written when BWST2 is cleared */
while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* New check to avoid false timeout detection in case of preemption */
if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
HAL_Delay(1U);
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
/* HoldTime */
MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
/* RefreshTime */
MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
}
/* Autonomous mode configuration */
MODIFY_REG(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE, sConfig->DAC_AutonomousMode);
if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
/* USER TRIMMING */
{
/* Get the DAC CCR value */
tmpreg1 = hdac->Instance->CCR;
/* Clear trimming value */
tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
/* Configure for the selected trimming offset */
tmpreg2 = sConfig->DAC_TrimmingValue;
/* Calculate CCR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
/* Write to DAC CCR */
hdac->Instance->CCR = tmpreg1;
}
/* else factory trimming is used (factory setting are available at reset)*/
/* SW Nothing has nothing to do */
/* Get the DAC MCR value */
tmpreg1 = hdac->Instance->MCR;
/* Clear DAC_MCR_MODEx bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
{
connectOnChip = 0x00000000UL;
}
else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
{
connectOnChip = DAC_MCR_MODE1_0;
}
else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
{
if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
{
connectOnChip = DAC_MCR_MODE1_0;
}
else
{
connectOnChip = 0x00000000UL;
}
}
tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
/* Clear DAC_MCR_DMADOUBLEx */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: DMA double data mode */
tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL;
/* Clear DAC_MCR_SINFORMATx */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: Signed format */
tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL;
/* Clear DAC_MCR_HFSEL bits */
tmpreg1 &= ~(DAC_MCR_HFSEL);
/* Configure for both DAC channels: high frequency mode */
if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency)
{
hclkfreq = HAL_RCC_GetHCLKFreq();
if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ)
{
tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ;
}
else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ)
{
tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ;
}
else
{
tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE;
}
}
else
{
tmpreg1 |= sConfig->DAC_HighFrequency;
}
/* Calculate MCR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
/* Write to DAC MCR */
hdac->Instance->MCR = tmpreg1;
/* DAC in normal operating mode hence clear DAC_CR_CENx bit */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
/* Clear TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
tmpreg2 = sConfig->DAC_Trigger;
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
==============================================================================
##### Peripheral State and Errors functions #####
==============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DAC state.
(+) Check the DAC Errors.
@endverbatim
* @{
*/
/**
* @brief return the DAC handle state
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL state
*/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
{
/* Return DAC handle state */
return hdac->State;
}
/**
* @brief Return the DAC error code
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval DAC Error Code
*/
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
{
return hdac->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions
* @{
*/
/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
* @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
* @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
* @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
* @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
* @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
* @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
* @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
*
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
pDAC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdac);
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
{
case HAL_DAC_CH1_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh1 = pCallback;
break;
case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh1 = pCallback;
break;
case HAL_DAC_CH1_ERROR_ID :
hdac->ErrorCallbackCh1 = pCallback;
break;
case HAL_DAC_CH1_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh1 = pCallback;
break;
case HAL_DAC_CH2_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh2 = pCallback;
break;
case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh2 = pCallback;
break;
case HAL_DAC_CH2_ERROR_ID :
hdac->ErrorCallbackCh2 = pCallback;
break;
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = pCallback;
break;
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = pCallback;
break;
case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hdac->State == HAL_DAC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = pCallback;
break;
case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdac);
return status;
}
/**
* @brief Unregister a User DAC Callback
* DAC Callback is redirected to the weak (surcharged) predefined callback
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
* @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
* @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
* @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
* @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
* @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
* @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
* @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
* @retval status
*/
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdac);
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
{
case HAL_DAC_CH1_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
break;
case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
break;
case HAL_DAC_CH1_ERROR_ID :
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
break;
case HAL_DAC_CH1_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
break;
case HAL_DAC_CH2_COMPLETE_CB_ID :
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
break;
case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
break;
case HAL_DAC_CH2_ERROR_ID :
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
break;
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
break;
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = HAL_DAC_MspInit;
break;
case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
case HAL_DAC_ALL_CB_ID :
hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
hdac->MspInitCallback = HAL_DAC_MspInit;
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hdac->State == HAL_DAC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = HAL_DAC_MspInit;
break;
case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
default :
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdac);
return status;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DAC_Private_Functions
* @{
*/
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvCpltCallbackCh1(hdac);
#else
HAL_DAC_ConvCpltCallbackCh1(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @brief DMA half transfer complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Conversion complete callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvHalfCpltCallbackCh1(hdac);
#else
HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ErrorCallbackCh1(hdac);
#else
HAL_DAC_ErrorCallbackCh1(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 */
#endif /* HAL_DAC_MODULE_ENABLED */
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c
|
C
|
apache-2.0
| 61,741
|
/**
******************************************************************************
* @file stm32u5xx_hal_dac_ex.c
* @author MCD Application Team
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** Dual mode IO operation ***
==============================
[..]
(+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
for dual mode operation.
If software trigger is selected, using HAL_DACEx_DualStart() will start
the conversion of the value previously set by HAL_DACEx_DualSetValue().
(+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
for dual mode operation.
(+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
for dual mode operation using DMA to feed DAC converters.
First issued trigger will start the conversion of the value previously
set by HAL_DACEx_DualSetValue().
The same callbacks that are used in single mode are called in dual mode to notify
transfer completion (half complete or complete), errors or underrun.
(+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
for dual mode operation using DMA to feed DAC converters.
(+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
Channel 1 and Channel 2.
*** Signal generation operation ***
===================================
[..]
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
(+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
(+) HAL_DACEx_SetUserTrimming to set user trimming value.
(+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
after reset, user setting if HAL_DACEx_SetUserTrimming have been used
at least one time after reset).
*** Autonomous Mode operation ***
===================================
[..]
(+) Use HAL_DACx_SetConfigAutonomousMode() to configure the autonomous mode
(+) Use HAL_DACx_GetConfigAutonomousMode() to get the current configuration of the autonomous mode
(+) Use HAL_DACx_ClearConfigAutonomousMode() to clear the configuration of the autonomous mode
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_DAC_MODULE_ENABLED
#if defined(DAC1)
/** @defgroup DACEx DACEx
* @brief DAC Extended HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
* @{
*/
/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
* @brief Extended IO operation functions
*
@verbatim
==============================================================================
##### Extended features functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Start conversion.
(+) Stop conversion.
(+) Start conversion and enable DMA transfer.
(+) Stop conversion and disable DMA transfer.
(+) Get result of conversion.
(+) Get result of dual mode conversion.
@endverbatim
* @{
*/
/**
* @brief Enables DAC and starts conversion of both channels.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
{
uint32_t tmp_swtrig = 0UL;
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
/* Ensure minimum wait before using peripheral after enabling it */
HAL_Delay(1);
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
}
if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
{
tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
}
/* Enable the selected DAC software conversion*/
SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables DAC and stop conversion of both channels.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
{
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
/* Ensure minimum wait before enabling peripheral after disabling it */
HAL_Delay(1);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The DAC channel that will request data from DMA.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param pData The destination peripheral Buffer address.
* @param Length The length of data to be transferred from memory to DAC peripheral
* @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
HAL_StatusTypeDef status;
uint32_t tmpreg;
uint32_t LengthInBytes;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
if (Channel == DAC_CHANNEL_1)
{
/* Set the DMA transfer complete callback for channel1 */
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
/* Set the DMA half transfer complete callback for channel1 */
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
/* Set the DMA error callback for channel1 */
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
}
else
{
/* Set the DMA transfer complete callback for channel2 */
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
/* Set the DMA half transfer complete callback for channel2 */
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
/* Set the DMA error callback for channel2 */
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
/* Enable the selected DAC channel2 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
}
switch (Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12RD;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
break;
default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
break;
}
/* Enable the DMA channel */
if (Channel == DAC_CHANNEL_1)
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
/* Length should be converted to number of bytes */
LengthInBytes = Length * 4U;
/* Check linkedlist mode */
if ((hdac->DMA_Handle1->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hdac->DMA_Handle1->LinkedListQueue != NULL) && (hdac->DMA_Handle1->LinkedListQueue->Head != NULL))
{
/* Set DMA data size */
hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
/* Set DMA source address */
hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
/* Enable the DMA channel */
status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle1);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
/* Enable the DMA channel */
status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, LengthInBytes);
}
}
else
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
/* Length should be converted to number of bytes */
LengthInBytes = Length * 4U;
/* Check linkedlist mode */
if ((hdac->DMA_Handle2->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hdac->DMA_Handle2->LinkedListQueue != NULL) && (hdac->DMA_Handle2->LinkedListQueue->Head != NULL))
{
/* Set DMA data size */
hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
/* Set DMA source address */
hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
/* Enable the DMA channel */
status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle2);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
/* Enable the DMA channel */
status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, LengthInBytes);
}
}
/* Process Unlocked */
__HAL_UNLOCK(hdac);
if (status == HAL_OK)
{
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
/* Ensure minimum wait before using peripheral after enabling it */
HAL_Delay(1);
}
else
{
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
}
/* Return function status */
return status;
}
/**
* @brief Disables DAC and stop conversion both channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The DAC channel that requests data from DMA.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
HAL_StatusTypeDef status;
/* Disable the selected DAC channel DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
/* Ensure minimum wait before enabling peripheral after disabling it */
HAL_Delay(1);
/* Disable the DMA channel */
/* Channel1 is used */
if (Channel == DAC_CHANNEL_1)
{
/* Disable the DMA channel */
status = HAL_DMA_Abort(hdac->DMA_Handle1);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
}
else
{
/* Disable the DMA channel */
status = HAL_DMA_Abort(hdac->DMA_Handle2);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
/* Check if DMA Channel effectively disabled */
if (status != HAL_OK)
{
/* Update DAC state machine to error */
hdac->State = HAL_DAC_STATE_ERROR;
}
else
{
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Amplitude Select max triangle amplitude.
* This parameter can be one of the following values:
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
* @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
* @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
* @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
* @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
* @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
* @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the triangle wave generation for the selected DAC channel */
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
(DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Enable or disable the selected DAC channel wave generation.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Amplitude Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values:
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the noise wave generation for the selected DAC channel */
MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
(DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the specified data holding register value for dual DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Alignment Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* DAC_ALIGN_8B_R: 8bit right data alignment selected
* DAC_ALIGN_12B_L: 12bit left data alignment selected
* DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
* @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
* @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
{
uint32_t data;
uint32_t tmp;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (Alignment == DAC_ALIGN_8B_R)
{
data = ((uint32_t)Data2 << 8U) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16U) | Data1;
}
tmp = (uint32_t)hdac->Instance;
tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
/* Return function status */
return HAL_OK;
}
/**
* @brief Conversion complete callback in non-blocking mode for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief Error DAC callback for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief DMA underrun DAC callback for Channel2.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief Run the self calibration of one DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig DAC channel configuration structure.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
* @retval HAL status
* @note Calibration runs about 7 ms.
*/
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t tmp;
uint32_t trimmingvalue;
uint32_t delta;
/* store/restore channel configuration structure purpose */
uint32_t oldmodeconfiguration;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Check the DAC handle allocation */
/* Check if DAC running */
if (hdac == NULL)
{
status = HAL_ERROR;
}
else if (hdac->State == HAL_DAC_STATE_BUSY)
{
status = HAL_ERROR;
}
else
{
/* Process locked */
__HAL_LOCK(hdac);
/* Store configuration */
oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
/* Disable the selected DAC channel */
CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
/* Wait for ready bit to be de-asserted */
HAL_Delay(1);
/* Set mode in MCR for calibration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
/* Set DAC Channel1 DHR register to the middle value */
tmp = (uint32_t)hdac->Instance;
if (Channel == DAC_CHANNEL_1)
{
tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
}
else
{
tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
}
*(__IO uint32_t *) tmp = 0x0800UL;
/* Enable the selected DAC channel calibration */
/* i.e. set DAC_CR_CENx bit */
SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
/* Init trimming counter */
/* Medium value */
trimmingvalue = 16UL;
delta = 8UL;
while (delta != 0UL)
{
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1);
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
{
/* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
trimmingvalue -= delta;
}
else
{
/* DAC_SR_CAL_FLAGx is LOW try lower trimming */
trimmingvalue += delta;
}
delta >>= 1UL;
}
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
/* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
/* i.e. minimum time needed between two calibration steps */
HAL_Delay(1U);
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
/* Trimming is actually one value more */
trimmingvalue++;
/* Set right trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
}
/* Disable the selected DAC channel calibration */
/* i.e. clear DAC_CR_CENx bit */
CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
sConfig->DAC_TrimmingValue = trimmingvalue;
sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
/* Restore configuration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
/* Process unlocked */
__HAL_UNLOCK(hdac);
}
return status;
}
/**
* @brief Set the trimming mode and trimming value (user trimming mode applied).
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig DAC configuration structure updated with new DAC trimming value.
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param NewTrimmingValue DAC new trimming value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
/* Check the DAC handle allocation */
if (hdac == NULL)
{
status = HAL_ERROR;
}
else
{
/* Process locked */
__HAL_LOCK(hdac);
/* Set new trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
/* Update trimming mode */
sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
sConfig->DAC_TrimmingValue = NewTrimmingValue;
/* Process unlocked */
__HAL_UNLOCK(hdac);
}
return status;
}
/**
* @brief Return the DAC trimming value.
* @param hdac DAC handle
* @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval Trimming value : range: 0->31
*
*/
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameter */
assert_param(IS_DAC_CHANNEL(Channel));
/* Retrieve trimming */
return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
}
/**
* @}
*/
/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Set the specified data holding register value for DAC channel.
@endverbatim
* @{
*/
/**
* @brief Return the last data output value of the selected DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
{
uint32_t tmp = 0UL;
tmp |= hdac->Instance->DOR1;
tmp |= hdac->Instance->DOR2 << 16UL;
/* Returns the DAC channel data output register value */
return tmp;
}
/**
* @}
*/
/**
* @brief Set autonomous mode Configuration.
* @note The autonomous mode applies to the 2 channels of a DAC block (same for both channels)
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig pointer to Autonomous mode structure parameters.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_SetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig)
{
assert_param(IS_DAC_AUTONOMOUS(sConfig->AutonomousModeState));
if (hdac->State == HAL_DAC_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hdac);
hdac->State = HAL_DAC_STATE_BUSY;
/* NOTE: The set/reset of the bit automode in the AUTOCR
register is for both dac_channel1 and dac_channel2 */
/* Update the AUTOCR register */
MODIFY_REG(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE, sConfig->AutonomousModeState);
/* Update the DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdac);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Get autonomous mode Configuration.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig pointer to Autonomous mode structure parameters.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_GetConfigAutonomousMode(DAC_HandleTypeDef *hdac, DAC_AutonomousModeConfTypeDef *sConfig)
{
/* Fill Autonomous structure parameter */
sConfig->AutonomousModeState = READ_BIT(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE);
return HAL_OK;
}
/**
* @brief Clear autonomous mode Configuration.
* @note The autonomous mode applies to the 2 channels of a DAC block (same for both channels)
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_ClearConfigAutonomousMode(DAC_HandleTypeDef *hdac)
{
if (hdac->State == HAL_DAC_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hdac);
hdac->State = HAL_DAC_STATE_BUSY;
/* NOTE: The set/reset of the bit automode in the AUTOCR
register is for both dac_channel1 and dac_channel2 */
/* Clear AUTOCR register */
CLEAR_BIT(hdac->Instance->AUTOCR, DAC_AUTOCR_AUTOMODE);
hdac->State = HAL_DAC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdac);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DACEx_Private_Functions DACEx private functions
* @brief Extended private functions
* @{
*/
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvCpltCallbackCh2(hdac);
#else
HAL_DACEx_ConvCpltCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @brief DMA half transfer complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Conversion complete callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ConvHalfCpltCallbackCh2(hdac);
#else
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA error callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->ErrorCallbackCh2(hdac);
#else
HAL_DACEx_ErrorCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
hdac->State = HAL_DAC_STATE_READY;
}
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 */
#endif /* HAL_DAC_MODULE_ENABLED */
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac_ex.c
|
C
|
apache-2.0
| 35,096
|
/**
******************************************************************************
* @file stm32u5xx_hal_dcache.c
* @author MCD Application Team
* @brief DCACHE HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DCACHE.
* + Initialization and Configuration
* + Cache coherency command
* + Monitoring management
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(#) Configure and enable the MPU to override default config if needed, please refers
to ARM manual for default memory attribute. Then enable DCache.
[..]
(+) Use HAL_DCACHE_Invalidate() to invalidate the full cache content:
(++) Cache content is lost, and reloaded when needed.
(++) Used for complete invalidate of the dcache in case.
(++) Blocking call until operation is done.
(+) Use HAL_DCACHE_InvalidateByAddr() to invalidate cache content for specific range:
(++) Cache content for specific range is lost, and reloaded when needed.
(++) Used when excepting a buffer to be updated by a peripheral (typically DMA transfer)
(++) Blocking call until operation is done.
(+) Use HAL_DCACHE_CleanByAddr() to clean cache content for a specific range:
(++) Cache content for specific range is written back to memory.
(++) Used when buffer is updated by CPU before usage by a peripheral (typically DMA transfer)
(++) Blocking call until operation is done.
(+) Use HAL_DCACHE_CleanInvalidateByAddr() to clean and invalidate cache content for a specific range:
(++) Cache content for specific range is written back to memory, and reloaded when needed.
(++) Used when sharing buffer between CPU and other peripheral.
(++) Recommended to use for MPU reprogramming.
(++) Blocking call until operation is done.
*** Interrupt mode IO operation ***
===================================
[..]
(+) Configure the DCACHE interrupt priority using HAL_NVIC_SetPriority()
(+) Enable the DCACHE IRQ handler using HAL_NVIC_EnableIRQ()
(+) Override weak definition for following callback (if needed):
(++)HAL_DCACHE_CleanAndInvalidateByAddrCallback()
(++)HAL_DCACHE_InvalidateCompleteCallback()
(++)HAL_DCACHE_InvalidateByAddrCallback()
(++)HAL_DCACHE_CleanByAddrCallback()
(++)HAL_DCACHE_ErrorCallback()
(+) Use HAL_DCACHE_<COMMAND>_IT() to start a DCache operation with IT enabled.
(+) Use HAL_DCACHE_IRQHandler() called under DCACHE_IRQHandler() Interrupt subroutine
[..] Use HAL_DCACHE_GetState() function to return the DCACHE state and HAL_DCACHE_GetError()
in case of error detection.
*** DCACHE HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DCACHE HAL driver.
(+) __HAL_DCACHE_ENABLE_IT : Enable DCACHE interrupts.
(+) __HAL_DCACHE_DISABLE_IT : Disable DCACHE interrupts.
(+) __HAL_DCACHE_GET_IT_SOURCE: Check whether the specified DCACHE interrupt source is enabled or not.
(+) __HAL_DCACHE_GET_FLAG : Check whether the selected DCACHE flag is set or not.
(+) __HAL_DCACHE_CLEAR_FLAG : Clear the selected DCACHE flags.
[..]
(@) You can refer to the header file of the DCACHE HAL driver for more useful macros.
[..]
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup DCACHE DCACHE
* @brief HAL DCACHE module driver
* @{
*/
#ifdef HAL_DCACHE_MODULE_ENABLED
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DCACHE_Private_Macros DCACHE Private Macros
* @{
*/
#define IS_DCACHE_REGION_SIZE(__SIZE__) ((__SIZE__) > 0U)
#define IS_DCACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) & ~DCACHE_MONITOR_ALL) == 0U)
#define IS_DCACHE_SINGLE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == DCACHE_MONITOR_READ_HIT) || \
((__TYPE__) == DCACHE_MONITOR_READ_MISS) || \
((__TYPE__) == DCACHE_MONITOR_WRITE_HIT) || \
((__TYPE__) == DCACHE_MONITOR_WRITE_MISS))
#define IS_DCACHE_READ_BURST_TYPE(__OUTPUTBURSTTYPE__) (((__OUTPUTBURSTTYPE__) == DCACHE_READ_BURST_WRAP) || \
((__OUTPUTBURSTTYPE__) == DCACHE_READ_BURST_INCR))
/**
* @}
*/
/* Private typedef -----------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DCACHE_Private_Constants DCACHE Private Constants
* @{
*/
#define DCACHE_COMMAND_TIMEOUT_VALUE 200U /* 200ms*/
#define DCACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
#define DCACHE_COMMAND_INVALIDATE DCACHE_CR_CACHECMD_1
#define DCACHE_COMMAND_CLEAN DCACHE_CR_CACHECMD_0
#define DCACHE_COMMAND_CLEAN_INVALIDATE (DCACHE_CR_CACHECMD_0|DCACHE_CR_CACHECMD_1)
#define DCACHE_POLLING_MODE 0U
#define DCACHE_IT_MODE 1U
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef DCACHE_CommandByAddr(DCACHE_HandleTypeDef *hdcache, uint32_t Command,
const uint32_t *const pAddr, uint32_t dSize, uint32_t mode);
/* Exported functions --------------------------------------------------------*/
/** @defgroup DCACHE_Exported_Functions DCACHE Exported Functions
* @{
*/
/** @defgroup DCACHE_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
deinitialize the DCACHEx peripheral:
(+) User must implement HAL_DCACHE_MspInit() function in which he configures
all related peripherals resources (CLOCK, MPU, IT and NVIC ).
(+) Call the function HAL_DCACHE_Init() to configure the selected device with
the selected configuration:
(++) ReadBurstType
(+) Call the function HAL_DCACHE_DeInit() to restore the reset configuration
of the selected DCACHEx peripheral.
@endverbatim
* @{
*/
/**
* @brief Initializes the DCACHE according to the specified parameters
* in the DCACHE_InitTypeDef and initialize the associated handle.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHE.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_Init(DCACHE_HandleTypeDef *hdcache)
{
HAL_StatusTypeDef status;
/* Check the DCACHE handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_READ_BURST_TYPE(hdcache->Init.ReadBurstType));
if (hdcache->State == HAL_DCACHE_STATE_RESET)
{
/* Init the DCACHE Callback settings with legacy weak */
hdcache->ErrorCallback = HAL_DCACHE_ErrorCallback;
hdcache->CleanByAddrCallback = HAL_DCACHE_CleanByAddrCallback;
hdcache->InvalidateByAddrCallback = HAL_DCACHE_InvalidateByAddrCallback;
hdcache->InvalidateCompleteCallback = HAL_DCACHE_InvalidateCompleteCallback;
hdcache->CleanAndInvalidateByAddrCallback = HAL_DCACHE_CleanAndInvalidateByAddrCallback;
if (hdcache->MspInitCallback == NULL)
{
hdcache->MspInitCallback = HAL_DCACHE_MspInit;
}
/* Init the low level hardware */
hdcache->MspInitCallback(hdcache);
}
/* Init the error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE;
/* Init the DCACHE handle state */
hdcache->State = HAL_DCACHE_STATE_READY;
/* Set requested read burst type */
MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_HBURST, hdcache->Init.ReadBurstType);
/* Enable the selected DCACHE peripheral */
status = HAL_DCACHE_Enable(hdcache);
return status;
}
/**
* @brief DeInitialize the Data cache.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_DeInit(DCACHE_HandleTypeDef *hdcache)
{
HAL_StatusTypeDef status;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
/* Update the error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE;
/* Return to the reset state */
hdcache->State = HAL_DCACHE_STATE_RESET;
/* Disable cache */
status = HAL_DCACHE_Disable(hdcache);
/* reset monitor values */
(void)HAL_DCACHE_Monitor_Reset(hdcache, DCACHE_MONITOR_ALL);
/* Reset all remaining bit */
WRITE_REG(hdcache->Instance->CR, 0U);
WRITE_REG(hdcache->Instance->CMDRSADDRR, 0U);
WRITE_REG(hdcache->Instance->CMDREADDRR, 0U);
WRITE_REG(hdcache->Instance->FCR, DCACHE_FCR_CCMDENDF | DCACHE_FCR_CERRF | DCACHE_FCR_CBSYENDF);
if (hdcache->MspDeInitCallback == NULL)
{
hdcache->MspDeInitCallback = HAL_DCACHE_MspDeInit;
}
/* DeInit the low level hardware */
hdcache->MspDeInitCallback(hdcache);
return status;
}
/**
* @brief Initialize the DCACHE MSP.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval None
*/
__weak void HAL_DCACHE_MspInit(DCACHE_HandleTypeDef *hdcache)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcache);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DCACHE_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the DCACHE MSP.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval None
*/
__weak void HAL_DCACHE_MspDeInit(DCACHE_HandleTypeDef *hdcache)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcache);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DCACHE_MspDeInit can be implemented in the user file
*/
}
/** @defgroup DCACHE_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Enable the Data cache.
(+) Disable the Data cache.
(+) Set Read Burst Type.
(+) Invalidate the Data cache.
(+) Invalidate the Data cache with interrupt.
(+) Clean the Data cache by Addr.
(+) Invalidate the Data cache by Addr.
(+) Clean and Invalidate the Data cache by Addr.
(+) Clean the Data cache by Addr with interrupt.
(+) Invalidate the Data cache by Addr with interrupt.
(+) Clean and Invalidate the Data cache by Addr with interrupt.
@endverbatim
* @{
*/
/**
* @brief Enable the Data cache.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_Enable(DCACHE_HandleTypeDef *hdcache)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
/* Check no ongoing operation */
if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
{
/* Return busy status */
status = HAL_BUSY;
}
else
{
/* Update the error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE;
/* Enable the selected DCACHE peripheral */
SET_BIT(hdcache->Instance->CR, DCACHE_CR_EN);
}
return status;
}
/**
* @brief Disable the Data cache.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_Disable(DCACHE_HandleTypeDef *hdcache)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
/* Check DCACHE handle status */
if (HAL_DCACHE_IsEnabled(hdcache) != 0U)
{
/* Update the error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE;
/* Change DCACHE handle state */
hdcache->State = HAL_DCACHE_STATE_READY;
/* Disable the selected DCACHE peripheral */
CLEAR_BIT(hdcache->Instance->CR, DCACHE_CR_EN);
/* Get timeout */
tickstart = HAL_GetTick();
/* Wait for end of data cache disabling */
while (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
{
if ((HAL_GetTick() - tickstart) > DCACHE_DISABLE_TIMEOUT_VALUE)
{
if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
{
/* Update error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT;
/* Change the DCACHE handle state */
hdcache->State = HAL_DCACHE_STATE_ERROR;
/* Return error status */
status = HAL_ERROR;
break;
}
}
}
}
return status;
}
/**
* @brief Check whether the Data Cache is enabled or not.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval Status (0: disabled, 1: enabled)
*/
uint32_t HAL_DCACHE_IsEnabled(DCACHE_HandleTypeDef *hdcache)
{
return ((READ_BIT(hdcache->Instance->CR, DCACHE_CR_EN) != 0U) ? 1UL : 0UL);
}
/**
* @brief Set Read Burst Type.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param ReadBurstType Burst type to be applied for Data Cache
* DCACHE_READ_BURST_WRAP, DCACHE_READ_BURST_INC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_SetReadBurstType(DCACHE_HandleTypeDef *hdcache, uint32_t ReadBurstType)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_READ_BURST_TYPE(ReadBurstType));
/* check DCACHE status */
if (HAL_DCACHE_IsEnabled(hdcache) == 0U)
{
/* Set requested read burst type */
MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_HBURST, ReadBurstType);
}
else
{
/* Update the error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_INVALID_OPERATION;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Invalidate the Data cache.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @note This function waits for end of full cache invalidation
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_Invalidate(DCACHE_HandleTypeDef *hdcache)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
/* Check no ongoing operation */
if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
{
/* Return busy status */
status = HAL_BUSY;
}
else
{
/* Update the error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE;
/* Change DCACHE Handle state */
hdcache->State = HAL_DCACHE_STATE_READY;
/* Make sure flags are reset */
WRITE_REG(hdcache->Instance->FCR, (DCACHE_FCR_CBSYENDF | DCACHE_FCR_CCMDENDF));
/* Set no operation on address range */
MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_CACHECMD, 0U);
/* Launch cache invalidation */
SET_BIT(hdcache->Instance->CR, DCACHE_CR_CACHEINV);
/* Get timeout */
tickstart = HAL_GetTick();
/* Wait for end of cache invalidation */
while (READ_BIT(hdcache->Instance->SR, DCACHE_SR_BUSYF) != 0U)
{
if ((HAL_GetTick() - tickstart) > DCACHE_COMMAND_TIMEOUT_VALUE)
{
if (READ_BIT(hdcache->Instance->SR, DCACHE_SR_BUSYF) != 0U)
{
/* Update error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT;
/* Change the DCACHE state */
hdcache->State = HAL_DCACHE_STATE_ERROR;
/* Return error status */
status = HAL_ERROR;
break;
}
}
}
}
return status;
}
/**
* @brief Invalidate the Data cache for a specific region.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param pAddr Start address of the region to be Invalidated
* @param dSize Size of the region to be Invalidated(in bytes)
* @note This function waits for end of cache Invalidation
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_InvalidateByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
uint32_t dSize)
{
HAL_StatusTypeDef status;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_REGION_SIZE(dSize));
status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_INVALIDATE, pAddr, dSize, DCACHE_POLLING_MODE);
return status;
}
/**
* @brief Clean the Data cache by Addr.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param pAddr Start address of the region to be Cleaned
* @param dSize Size of the region to be Cleaned (in bytes)
* @note This function waits for end of cache Clean
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_CleanByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr, uint32_t dSize)
{
HAL_StatusTypeDef status;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_REGION_SIZE(dSize));
status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_CLEAN, pAddr, dSize, DCACHE_POLLING_MODE);
return status;
}
/**
* @brief Clean and Invalidate the Data cache by Addr.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param pAddr Start address of the region to be Cleaned and Invalidated
* @param dSize Size of the region to be Cleaned and Invalidated (in bytes)
* @note This function waits for end of cache Clean and Invalidation
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
uint32_t dSize)
{
HAL_StatusTypeDef status;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_REGION_SIZE(dSize));
status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_CLEAN_INVALIDATE, pAddr, dSize, DCACHE_POLLING_MODE);
return status;
}
/**
* @brief Invalidate the Data cache with interrupt.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @note This function launches maintenance operation and returns immediately.
* User application shall resort to interrupt generation to check
* the end of operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_Invalidate_IT(DCACHE_HandleTypeDef *hdcache)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
/* Check no ongoing operation */
if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
{
/* Return busy status */
status = HAL_BUSY;
}
else
{
/* Update the error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE;
/* Change DCACHE Handle state */
hdcache->State = HAL_DCACHE_STATE_READY;
/* Make sure BSYENDF is reset */
WRITE_REG(hdcache->Instance->FCR, (DCACHE_FCR_CBSYENDF | DCACHE_FCR_CCMDENDF));
/* Set no operation on address range for callback under interrupt */
MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_CACHECMD, 0U);
/* Enable end of cache invalidation interrupt */
SET_BIT(hdcache->Instance->IER, DCACHE_IER_BSYENDIE);
/* Launch cache invalidation */
SET_BIT(hdcache->Instance->CR, DCACHE_CR_CACHEINV);
}
return status;
}
/**
* @brief Invalidate the Data cache by Addr with interrupt.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param pAddr Start address of the region to be Invalidated
* @param dSize Size of the region to be Invalidated
* @note This function launches maintenance operation and returns immediately.
* User application shall resort to interrupt generation to check
* the end of operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_InvalidateByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
uint32_t dSize)
{
HAL_StatusTypeDef status;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_REGION_SIZE(dSize));
status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_INVALIDATE, pAddr, dSize, DCACHE_IT_MODE);
return status;
}
/**
* @brief Clean the Data cache by Addr with interrupt.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param pAddr Start address of the region to be Cleaned
* @param dSize Size of the region to be Cleaned
* @note This function launches maintenance operation and returns immediately.
* User application shall resort to interrupt generation to check
* the end of operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_CleanByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
uint32_t dSize)
{
HAL_StatusTypeDef status;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_REGION_SIZE(dSize));
status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_CLEAN, pAddr, dSize, DCACHE_IT_MODE);
return status;
}
/**
* @brief Clean and Invalidate the Data cache by Addr with interrupt.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param pAddr Start address of the region to be Cleaned and Invalidated
* @param dSize Size of the region to be Cleaned and Invalidated
* @note This function launches maintenance operation and returns immediately.
* User application shall resort to interrupt generation to check
* the end of operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_CleanInvalidByAddr_IT(DCACHE_HandleTypeDef *hdcache, const uint32_t *const pAddr,
uint32_t dSize)
{
HAL_StatusTypeDef status;
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_REGION_SIZE(dSize));
status = DCACHE_CommandByAddr(hdcache, DCACHE_COMMAND_CLEAN_INVALIDATE, pAddr, dSize, DCACHE_IT_MODE);
return status;
}
/**
* @brief Handle the Data Cache interrupt request.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @note This API should be called under the DCACHE_IRQHandler().
* @retval None
*/
void HAL_DCACHE_IRQHandler(DCACHE_HandleTypeDef *hdcache)
{
/* Get current interrupt flags and interrupt sources value */
uint32_t itflags = READ_REG(hdcache->Instance->SR);
uint32_t itsources = READ_REG(hdcache->Instance->IER);
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
/* Check Data cache Error interrupt flag */
if (((itflags & itsources) & DCACHE_FLAG_ERROR) != 0U)
{
/* Clear DCACHE error pending flag */
__HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_ERROR);
/* Update data cache error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_EVICTION_CLEAN;
/* Data cache error interrupt user callback */
hdcache->ErrorCallback(hdcache);
}
if (READ_BIT(hdcache->Instance->CR, DCACHE_CR_CACHECMD) == 0U) /* no operation by range */
{
/* Clear DCACHE busyend pending flag */
__HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_BUSYEND);
/* Data cache invalidate complete interrupt user callback */
hdcache->InvalidateCompleteCallback(hdcache);
}
else if (READ_BIT(hdcache->Instance->CR, DCACHE_CR_CACHECMD_1 | DCACHE_CR_CACHECMD_0) == \
(DCACHE_CR_CACHECMD_1 | DCACHE_CR_CACHECMD_0))
{
/* Clear DCACHE cmdend pending flag */
__HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND);
/* Data cache clean and invalidate range cmdend interrupt user callback */
hdcache->CleanAndInvalidateByAddrCallback(hdcache);
}
else if (READ_BIT(hdcache->Instance->CR, DCACHE_CR_CACHECMD_0) == DCACHE_CR_CACHECMD_0)
{
/* Clear DCACHE cmdend pending flag */
__HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND);
/* Data cache clean range cmdend interrupt user callback */
hdcache->CleanByAddrCallback(hdcache);
}
else
{
/* Clear DCACHE cmdend pending flag */
__HAL_DCACHE_CLEAR_FLAG(hdcache, DCACHE_FLAG_CMDEND);
/* Data cache Invalidate range cmdend interrupt user callback */
hdcache->InvalidateByAddrCallback(hdcache);
}
}
/**
* @brief Cache clean command by address callback.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval None
*/
__weak void HAL_DCACHE_CleanByAddrCallback(DCACHE_HandleTypeDef *hdcache)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcache);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DCACHE_CleanByAddrCallback() should be implemented in the user file
*/
}
/**
* @brief Cache Invalidate command by address callback.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval None
*/
__weak void HAL_DCACHE_InvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcache);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DCACHE_InvalidateByAddrCallback() should be implemented in the user file
*/
}
/**
* @brief Cache clean and Invalidate command by address callback.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval None
*/
__weak void HAL_DCACHE_CleanAndInvalidateByAddrCallback(DCACHE_HandleTypeDef *hdcache)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcache);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DCACHE_CleanAndInvalidateByAddrCallback() should be implemented in the user file
*/
}
/**
* @brief Cache full invalidation complete callback.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval None
*/
__weak void HAL_DCACHE_InvalidateCompleteCallback(DCACHE_HandleTypeDef *hdcache)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcache);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DCACHE_InvalidateCompleteCallback() should be implemented in the user file
*/
}
/**
* @brief Error callback.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval None
*/
__weak void HAL_DCACHE_ErrorCallback(DCACHE_HandleTypeDef *hdcache)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcache);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DCACHE_ErrorCallback() should be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DCACHE_Exported_Functions_Group3 Peripheral State,
* @brief Peripheral State,
*
@verbatim
===============================================================================
##### Peripheral State #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the DCACHE handle state.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @retval HAL state
*/
HAL_DCACHE_StateTypeDef HAL_DCACHE_GetState(DCACHE_HandleTypeDef *hdcache)
{
/* Return DCACHE handle state */
return hdcache->State;
}
/**
* @}
*/
/**
* @brief Return the DCACHE error code
* @param hdcache pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHE.
* @retval DCACHE Error Code
*/
uint32_t HAL_DCACHE_GetError(DCACHE_HandleTypeDef *hdcache)
{
/* Return DCACHE handle error code */
return hdcache->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DCACHE_Exported_Functions
* @{
*/
/** @addtogroup DCACHE_Exported_Functions_Group1
* @{
*/
/**
* @brief Register a User DCACHE Callback
* To be used instead of the weak predefined callback
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID Clean By Addr callback ID
* @arg @ref HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID Invalidate By Addr callback ID
* @arg @ref HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID Clean and Invalidate By Addr callback ID
* @arg @ref HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID Invalidate Complete ID
* @arg @ref HAL_DCACHE_ERROR_CB_ID Error callback ID
* @arg @ref HAL_DCACHE_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_DCACHE_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_RegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID,
pDCACHE_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
/* Return error status */
return HAL_ERROR;
}
if (hdcache->State == HAL_DCACHE_STATE_READY)
{
switch (CallbackID)
{
case HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID :
hdcache->CleanByAddrCallback = pCallback;
break;
case HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID :
hdcache->InvalidateByAddrCallback = pCallback;
break;
case HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID :
hdcache->CleanAndInvalidateByAddrCallback = pCallback;
break;
case HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID :
hdcache->InvalidateCompleteCallback = pCallback;
break;
case HAL_DCACHE_ERROR_CB_ID :
hdcache->ErrorCallback = pCallback;
break;
case HAL_DCACHE_MSPINIT_CB_ID :
hdcache->MspInitCallback = pCallback;
break;
case HAL_DCACHE_MSPDEINIT_CB_ID :
hdcache->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hdcache->State == HAL_DCACHE_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DCACHE_MSPINIT_CB_ID :
hdcache->MspInitCallback = pCallback;
break;
case HAL_DCACHE_MSPDEINIT_CB_ID :
hdcache->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister an DCACHE Callback
* DCACHE callback is redirected to the weak predefined callback
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID Clean By Addr callback ID
* @arg @ref HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID Invalidate By Addr callback ID
* @arg @ref HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID Clean and Invalidate By Addr callback ID
* @arg @ref HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID Invalidate Complete callback ID
* @arg @ref HAL_DCACHE_ERROR_CB_ID Error callback ID
* @arg @ref HAL_DCACHE_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_DCACHE_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_UnRegisterCallback(DCACHE_HandleTypeDef *hdcache, HAL_DCACHE_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (hdcache->State == HAL_DCACHE_STATE_READY)
{
switch (CallbackID)
{
case HAL_DCACHE_CLEAN_BY_ADDRESS_CB_ID :
/* Legacy weak Clean By Addr Callback */
hdcache->CleanByAddrCallback = HAL_DCACHE_CleanByAddrCallback;
break;
case HAL_DCACHE_INVALIDATE_BY_ADDRESS_CB_ID :
/* Legacy weak Invalidate By Addr Callback */
hdcache->InvalidateByAddrCallback = HAL_DCACHE_InvalidateByAddrCallback;
break;
case HAL_DCACHE_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID :
/* Legacy weak Clean and Invalidate By Addr Callback */
hdcache->CleanAndInvalidateByAddrCallback = HAL_DCACHE_CleanAndInvalidateByAddrCallback;
break;
case HAL_DCACHE_INVALIDATE_COMPLETE_CB_ID :
/* Legacy weak Invalidate Complete Callback */
hdcache->InvalidateCompleteCallback = HAL_DCACHE_InvalidateCompleteCallback;
break;
case HAL_DCACHE_ERROR_CB_ID :
/* Legacy weak ErrorCallback */
hdcache->ErrorCallback = HAL_DCACHE_ErrorCallback;
break;
case HAL_DCACHE_MSPINIT_CB_ID :
/* Legacy weak MspInit */
hdcache->MspInitCallback = HAL_DCACHE_MspInit;
break;
case HAL_DCACHE_MSPDEINIT_CB_ID :
/* Legacy weak MspDeInit */
hdcache->MspDeInitCallback = HAL_DCACHE_MspDeInit;
break;
default :
/* Update the error code */
hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_DCACHE_STATE_RESET == hdcache->State)
{
switch (CallbackID)
{
case HAL_DCACHE_MSPINIT_CB_ID :
/* Legacy weak MspInit */
hdcache->MspInitCallback = HAL_DCACHE_MspInit;
break;
case HAL_DCACHE_MSPDEINIT_CB_ID :
/* Legacy weak MspDeInit */
hdcache->MspDeInitCallback = HAL_DCACHE_MspDeInit;
break;
default :
/* Update the error code */
hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdcache->ErrorCode |= HAL_DCACHE_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Start the Data Cache performance monitoring.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param MonitorType Monitoring type
* This parameter can be a combination of the following values:
* @arg DCACHE_MONITOR_READ_HIT
* @arg DCACHE_MONITOR_READ_MISS
* @arg DCACHE_MONITOR_WRITE_HIT
* @arg DCACHE_MONITOR_WRITE_MISS
* @arg DCACHE_MONITOR_ALL
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_Monitor_Start(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType)
{
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType));
SET_BIT(hdcache->Instance->CR, MonitorType);
return HAL_OK;
}
/**
* @brief Stop the Data Cache performance monitoring.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @note Stopping the monitoring does not reset the values.
* @param MonitorType Monitoring type
* This parameter can be a combination of the following values:
* @arg DCACHE_MONITOR_READ_HIT
* @arg DCACHE_MONITOR_READ_MISS
* @arg DCACHE_MONITOR_WRITE_HIT
* @arg DCACHE_MONITOR_WRITE_MISS
* @arg DCACHE_MONITOR_ALL
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_Monitor_Stop(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType)
{
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType));
CLEAR_BIT(hdcache->Instance->CR, MonitorType);
return HAL_OK;
}
/**
* @brief Reset the Data Cache performance monitoring values.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param MonitorType Monitoring type
* This parameter can be a combination of the following values:
* @arg DCACHE_MONITOR_READ_HIT
* @arg DCACHE_MONITOR_READ_MISS
* @arg DCACHE_MONITOR_WRITE_HIT
* @arg DCACHE_MONITOR_WRITE_MISS
* @arg DCACHE_MONITOR_ALL
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCACHE_Monitor_Reset(DCACHE_HandleTypeDef *hdcache, uint32_t MonitorType)
{
/* Check the dcache handle allocation */
if (hdcache == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
assert_param(IS_DCACHE_MONITOR_TYPE(MonitorType));
/* Force/Release reset */
SET_BIT(hdcache->Instance->CR, (MonitorType << 2U));
CLEAR_BIT(hdcache->Instance->CR, (MonitorType << 2U));
return HAL_OK;
}
/**
* @brief Get the Data Cache performance Read Hit monitoring value.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @note Upon reaching the maximum value, monitor does not wrap.
* @retval Read Hit monitoring value
*/
uint32_t HAL_DCACHE_Monitor_GetReadHitValue(DCACHE_HandleTypeDef *hdcache)
{
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
/*return the Read Hit monitor value*/
return hdcache->Instance->RHMONR;
}
/**
* @brief Get the Data Cache performance Read Miss monitoring value.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @note Upon reaching the maximum value, monitor does not wrap.
* @retval Read Miss monitoring value
*/
uint32_t HAL_DCACHE_Monitor_GetReadMissValue(DCACHE_HandleTypeDef *hdcache)
{
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
/*return the Read Miss monitor value*/
return hdcache->Instance->RMMONR;
}
/**
* @brief Get the Data Cache performance Write Hit monitoring value.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @note Upon reaching the maximum value, monitor does not wrap.
* @retval Write Hit monitoring value
*/
uint32_t HAL_DCACHE_Monitor_GetWriteHitValue(DCACHE_HandleTypeDef *hdcache)
{
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
/*return the Write Hit monitor value*/
return hdcache->Instance->WHMONR;
}
/**
* @brief Get the Data Cache performance Write Miss monitoring value.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @note Upon reaching the maximum value, monitor does not wrap.
* @retval Write Miss monitoring value
*/
uint32_t HAL_DCACHE_Monitor_GetWriteMissValue(DCACHE_HandleTypeDef *hdcache)
{
/* Check the parameters */
assert_param(IS_DCACHE_ALL_INSTANCE(hdcache->Instance));
/*return the Write Miss monitor value*/
return hdcache->Instance->WMMONR;
}
/**
* @}
*/
/**
* @brief launch dcache command Clean, Invalidate or clean and invalidate by Addr.
* @param hdcache Pointer to a DCACHE_HandleTypeDef structure that contains
* the configuration information for the specified DCACHEx peripheral.
* @param Command command to be applied for the dcache
* DCACHE_COMMAND_INVALIDATE, DCACHE_COMMAND_CLEAN, DCACHE_COMMAND_CLEAN_INVALIDATE
* @param pAddr Start address of region to be Cleaned, Invalidated or Cleaned and Invalidated.
* @param dSize Size of the region to be Cleaned, Invalidated or Cleaned and Invalidated (in bytes).
* @param mode mode to be applied for the dcache
* DCACHE_IT_MODE, DCACHE_POLLING_MODE.
* @retval HAL status
*/
static HAL_StatusTypeDef DCACHE_CommandByAddr(DCACHE_HandleTypeDef *hdcache, uint32_t Command,
const uint32_t *const pAddr, uint32_t dSize, uint32_t mode)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t op_addr = (uint32_t)pAddr;
uint32_t tickstart;
/* Check no ongoing operation */
if (READ_BIT(hdcache->Instance->SR, (DCACHE_SR_BUSYF | DCACHE_SR_BUSYCMDF)) != 0U)
{
/* Return busy status */
status = HAL_BUSY;
}
else
{
/* Update the error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_NONE;
/* Update the DCACHE handle State */
hdcache->State = HAL_DCACHE_STATE_READY;
/* Make sure flags are reset */
WRITE_REG(hdcache->Instance->FCR, (DCACHE_FCR_CBSYENDF | DCACHE_FCR_CCMDENDF));
/* Fill area start address */
WRITE_REG(hdcache->Instance->CMDRSADDRR, op_addr);
/* Fill area end address */
WRITE_REG(hdcache->Instance->CMDREADDRR, (op_addr + dSize - 1U));
/* Set command */
MODIFY_REG(hdcache->Instance->CR, DCACHE_CR_CACHECMD, Command);
/* Enable IT if required */
if (mode == DCACHE_IT_MODE)
{
/* Enable end of cache command interrupt */
SET_BIT(hdcache->Instance->IER, DCACHE_IER_CMDENDIE);
/* Launch cache command */
SET_BIT(hdcache->Instance->CR, DCACHE_CR_STARTCMD);
}
else
{
/* Make sure that end of cache command interrupt is disabled */
CLEAR_BIT(hdcache->Instance->IER, DCACHE_IER_CMDENDIE);
/* Launch cache command */
SET_BIT(hdcache->Instance->CR, DCACHE_CR_STARTCMD);
/* Get timeout */
tickstart = HAL_GetTick();
/* Wait for end of cache command */
while (READ_BIT(hdcache->Instance->SR, DCACHE_SR_CMDENDF) == 0U)
{
if ((HAL_GetTick() - tickstart) > DCACHE_COMMAND_TIMEOUT_VALUE)
{
if (READ_BIT(hdcache->Instance->SR, DCACHE_SR_CMDENDF) == 0U)
{
/* Update error code */
hdcache->ErrorCode = HAL_DCACHE_ERROR_TIMEOUT;
/* Change the DCACHE state */
hdcache->State = HAL_DCACHE_STATE_ERROR;
/* Return error status */
status = HAL_ERROR;
break;
}
}
}
}
}
return status;
}
#endif /* HAL_DCACHE_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcache.c
|
C
|
apache-2.0
| 48,998
|
/**
******************************************************************************
* @file stm32u5xx_hal_dcmi.c
* @author MCD Application Team
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Error functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The sequence below describes how to use this driver to capture image
from a camera module connected to the DCMI Interface.
This sequence does not take into account the configuration of the
camera module, which should be made before to configure and enable
the DCMI to capture images.
(#) Program the required configuration through following parameters:
horizontal and vertical polarity, pixel clock polarity, Capture Rate,
Synchronization Mode, code of the frame delimiter and data width
using HAL_DCMI_Init() function.
(#) Configure the selected DMA stream to transfer Data from DCMI DR
register to the destination memory buffer.
(#) Program the required configuration through following parameters:
DCMI mode, destination memory Buffer address and the data length
and enable capture using HAL_DCMI_Start_DMA() function.
(#) Optionally, configure and Enable the CROP feature to select a rectangular
window from the received image using HAL_DCMI_ConfigCrop()
and HAL_DCMI_EnableCrop() functions
(#) The capture can be stopped using HAL_DCMI_Stop() function.
(#) To control DCMI state you can use the function HAL_DCMI_GetState().
*** DCMI HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DCMI HAL driver.
(+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
(+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
(+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
(+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
(+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
(+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
(+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
[..]
(@) You can refer to the DCMI HAL driver header file for more useful macros
*** Callback registration ***
=============================
The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions HAL_DCMI_RegisterCallback() to register a user callback.
Function HAL_DCMI_RegisterCallback() allows to register following callbacks:
(+) FrameEventCallback : callback for DCMI Frame Event.
(+) VsyncEventCallback : callback for DCMI Vsync Event.
(+) LineEventCallback : callback for DCMI Line Event.
(+) ErrorCallback : callback for DCMI error detection.
(+) MspInitCallback : callback for DCMI MspInit.
(+) MspDeInitCallback : callback for DCMI MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
This function allows to reset following callbacks:
(+) FrameEventCallback : callback for DCMI Frame Event.
(+) VsyncEventCallback : callback for DCMI Vsync Event.
(+) LineEventCallback : callback for DCMI Line Event.
(+) ErrorCallback : callback for DCMI error.
(+) MspInitCallback : callback for DCMI MspInit.
(+) MspDeInitCallback : callback for DCMI MspDeInit.
By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples FrameEventCallback(), HAL_DCMI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init
and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_DCMI_RegisterCallback before calling HAL_DCMI_DeInit
or HAL_DCMI_Init function.
When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
#ifdef HAL_DCMI_MODULE_ENABLED
#if defined (DCMI)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup DCMI DCMI
* @brief DCMI HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup DCMI_Private_Constants DCMI Private Constants
* @{
*/
/** @defgroup DCMI_Stop_TimeOut DCMI Stop Time Out
* @{
*/
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup DCMI_Private_Functions DCMI Private Functions
* @{
*/
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
* @{
*/
/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DCMI
(+) De-initialize the DCMI
@endverbatim
* @{
*/
/**
* @brief Initializes the DCMI according to the specified
* parameters in the DCMI_InitTypeDef and create the associated handle.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
{
/* Check the DCMI peripheral state */
if (hdcmi == NULL)
{
return HAL_ERROR;
}
/* Check function parameters */
assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
/* Init the DCMI Callback settings */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
if (hdcmi->MspInitCallback == NULL)
{
/* Legacy weak MspInit Callback */
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
}
/* Initialize the low level hardware (MSP) */
hdcmi->MspInitCallback(hdcmi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_DCMI_MspInit(hdcmi);
#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
}
/* Change the DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B)
{
/* Byte select mode must be programmed to the reset value if the extended mode
is not set to 8-bit data capture on every pixel clock */
hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL;
}
/* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG | \
DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS | \
DCMI_CR_LSM | DCMI_CR_OELS);
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode | \
hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode | \
hdcmi->Init.LineSelectStart);
if (hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
{
hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) | \
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos) | \
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) | \
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos));
}
/* Enable the Line, Vsync, Error and Overrun interrupts */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
/* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
return HAL_OK;
}
/**
* @brief Deinitializes the DCMI peripheral registers to their default reset
* values.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
{
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
if (hdcmi->MspDeInitCallback == NULL)
{
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
}
/* De-Initialize the low level hardware (MSP) */
hdcmi->MspDeInitCallback(hdcmi);
#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_DCMI_MspDeInit(hdcmi);
#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */
/* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @brief Initializes the DCMI MSP.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the DCMI MSP.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure destination address and data length and
Enables DCMI DMA request and enables DCMI capture
(+) Stop the DCMI capture.
(+) Handles DCMI interrupt request.
@endverbatim
* @{
*/
/**
* @brief Enables DCMI DMA request and enables DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @param DCMI_Mode DCMI capture mode snapshot or continuous grab.
* @param pData The destination memory Buffer address (LCD Frame buffer).
* @param Length The length of capture to be transferred.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
uint32_t tmp_length = Length;
HAL_StatusTypeDef status = HAL_OK;
uint32_t cllr_offset;
uint32_t tmp1;
uint32_t tmp2;
/* Check function parameters */
assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Enable DCMI by setting DCMIEN bit */
__HAL_DCMI_ENABLE(hdcmi);
/* Configure the DCMI Mode */
hdcmi->Instance->CR &= ~(DCMI_CR_CM);
hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
/* Set the DMA memory0 conversion complete callback */
hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
/* Set the DMA error callback */
hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
/* Set the dma abort callback */
hdcmi->DMA_Handle->XferAbortCallback = NULL;
/* Reset transfer counters value */
hdcmi->XferCount = 0;
hdcmi->XferTransferNumber = 0;
hdcmi->XferSize = 0;
hdcmi->pBuffPtr = 0;
/* Length should be converted to number of bytes */
tmp_length = tmp_length * 4U;
if (tmp_length <= 0xFFFFU)
{
/* Continuoues Mode */
/* Enable the DMA Stream */
if ((hdcmi->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hdcmi->DMA_Handle->LinkedListQueue != 0U) && (hdcmi->DMA_Handle->LinkedListQueue->Head != 0U))
{
/* Set Source , Destination , Length for DMA Xfer */
/* Set DMA data size */
hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = tmp_length;
/* Set DMA source address */
hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
(uint32_t)&hdcmi->Instance->DR;
/* Set DMA destination address */
hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
status = HAL_DMAEx_List_Start_IT(hdcmi->DMA_Handle);
}
else
{
/* Set Error Code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
/* Return function status */
status = HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, tmp_length);
}
}
else /* DCMI_DOUBLE_BUFFER Mode */
{
/* Double buffering is used through 2 Nodes
Calculate the elementary size to be transferred by each node */
/* Initialize transfer parameters */
hdcmi->XferCount = 1;
hdcmi->XferSize = tmp_length;
hdcmi->pBuffPtr = pData;
/* Get the number of buffer */
while (hdcmi->XferSize > 0xFFFFU)
{
hdcmi->XferSize = (hdcmi->XferSize / 2U);
hdcmi->XferCount = hdcmi->XferCount * 2U;
}
/* Update DCMI counter and transfer number*/
hdcmi->XferCount = (hdcmi->XferCount - 1U);
hdcmi->XferTransferNumber = hdcmi->XferCount;
if ((hdcmi->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hdcmi->DMA_Handle->LinkedListQueue != 0U) && (hdcmi->DMA_Handle->LinkedListQueue->Head != 0U))
{
/* Update first node */
/* Set DMA Data size */
hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hdcmi->XferSize ;
/* Set DMA Source address */
hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
(uint32_t)&hdcmi->Instance->DR;
/* Set DMA Destination address */
hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Get CLLR offset */
cllr_offset = (hdcmi->DMA_Handle->LinkedListQueue->Head->NodeInfo & NODE_CLLR_IDX) >> 8U;
/* Update second node */
if (hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[cllr_offset] != 0U)
{
tmp1 = (uint32_t)hdcmi->DMA_Handle->LinkedListQueue->Head ;
tmp2 = hdcmi->DMA_Handle->LinkedListQueue->Head->LinkRegisters[cllr_offset];
/* Update second node */
/* Set DMA Data size */
((DMA_NodeTypeDef *)((tmp1 & DMA_CLBAR_LBA) + \
(tmp2 & DMA_CLLR_LA)))->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hdcmi->XferSize;
/* Set DMA Source address */
((DMA_NodeTypeDef *)((tmp1 & DMA_CLBAR_LBA) + \
(tmp2 & DMA_CLLR_LA)))->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \
(uint32_t)&hdcmi->Instance->DR;
/* Set DMA Destination address */
((DMA_NodeTypeDef *)((tmp1 & DMA_CLBAR_LBA) + \
(tmp2 & DMA_CLLR_LA)))->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = \
(uint32_t)pData + hdcmi->XferSize;
if (HAL_DMAEx_List_Start_IT(hdcmi->DMA_Handle) != HAL_OK)
{
/* Set Error Code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
/* Return function status */
status = HAL_ERROR;
}
}
else
{
/* Set Error Code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
/* Return function status */
status = HAL_ERROR;
}
}
else
{
/* Set Error Code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
/* Return function status */
status = HAL_ERROR;
}
}
else
{
/* Set Error Code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
/* Return function status */
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Enable Capture */
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
}
else
{
/* Set Error Code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
/* Return function status */
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @brief Disable DCMI DMA request and Disable DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi)
{
uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Disable Capture */
hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
/* Check if the DCMI capture effectively disabled */
do
{
count-- ;
if (count == 0U)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
status = HAL_TIMEOUT;
break;
}
} while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
/* Disable the DCMI */
__HAL_DCMI_DISABLE(hdcmi);
/* Disable the DMA */
(void)HAL_DMA_Abort(hdcmi->DMA_Handle);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return status;
}
/**
* @brief Suspend DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi)
{
uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
if (hdcmi->State == HAL_DCMI_STATE_BUSY)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
/* Disable Capture */
hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
/* Check if the DCMI capture effectively disabled */
do
{
count-- ;
if (count == 0U)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
status = HAL_TIMEOUT;
break;
}
} while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U);
}
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return status;
}
/**
* @brief Resume DCMI capture
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi)
{
/* Process locked */
__HAL_LOCK(hdcmi);
if (hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Enable Capture */
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
}
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return HAL_OK;
}
/**
* @brief Handles DCMI interrupt request.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for the DCMI.
* @retval None
*/
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
{
uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
/* Synchronization error interrupt management *******************************/
if ((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
{
/* Clear the Synchronization error flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_ERROR;
/* Set the synchronization error callback */
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
{
DCMI_DMAError(hdcmi->DMA_Handle);
}
}
/* Overflow interrupt management ********************************************/
if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
{
/* Clear the Overflow flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_ERROR;
/* Set the overflow callback */
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK)
{
DCMI_DMAError(hdcmi->DMA_Handle);
}
}
/* Line Interrupt management ************************************************/
if ((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
{
/* Clear the Line interrupt flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
/* Line interrupt Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI line event callback*/
hdcmi->LineEventCallback(hdcmi);
#else
HAL_DCMI_LineEventCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* VSYNC interrupt management ***********************************************/
if ((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
{
/* Clear the VSYNC flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
/* VSYNC Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI vsync event callback*/
hdcmi->VsyncEventCallback(hdcmi);
#else
HAL_DCMI_VsyncEventCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/* FRAME interrupt management ***********************************************/
if ((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
{
/* When snapshot mode, disable Vsync, Error and Overrun interrupts */
if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
{
/* Disable the Line, Vsync, Error and Overrun interrupts */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
}
/* Disable the Frame interrupt */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
/* Clear the End of Frame flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
/* Frame Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI frame event callback*/
hdcmi->FrameEventCallback(hdcmi);
#else
HAL_DCMI_FrameEventCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
}
/**
* @brief Error DCMI callback.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief Line Event callback.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_LineEventCallback could be implemented in the user file
*/
}
/**
* @brief VSYNC Event callback.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_VsyncEventCallback could be implemented in the user file
*/
}
/**
* @brief Frame Event callback.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_FrameEventCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the CROP feature.
(+) Enable/Disable the CROP feature.
(+) Set embedded synchronization delimiters unmasks.
@endverbatim
* @{
*/
/**
* @brief Configure the DCMI CROP coordinate.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @param YSize DCMI Line number
* @param XSize DCMI Pixel per line
* @param X0 DCMI window X offset
* @param Y0 DCMI window Y offset
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize,
uint32_t YSize)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Check the parameters */
assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
/* Configure CROP */
hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos));
hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_CWSTRT_VST_Pos));
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @brief Disable the Crop feature.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Disable DCMI Crop feature */
hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
/* Change the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @brief Enable the Crop feature.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Enable DCMI Crop feature */
hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
/* Change the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @brief Set embedded synchronization delimiters unmasks.
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains
* the embedded synchronization delimiters unmasks.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Write DCMI embedded synchronization unmask register */
hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) | \
((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos) | \
((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos) | \
((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos));
/* Change the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DCMI state.
(+) Get the specific DCMI error flag.
@endverbatim
* @{
*/
/**
* @brief Return the DCMI state
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL state
*/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
{
return hdcmi->State;
}
/**
* @brief Return the DCMI error code
* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval DCMI Error Code
*/
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
{
return hdcmi->ErrorCode;
}
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DCMI Callback
* To be used instead of the weak predefined callback
* @param hdcmi DCMI handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
* @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
* @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
* @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
* @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID,
pDCMI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
else
{
if (hdcmi->State == HAL_DCMI_STATE_READY)
{
switch (CallbackID)
{
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = pCallback;
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = pCallback;
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = pCallback;
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = pCallback;
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = pCallback;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Unregister a DCMI Callback
* DCMI callback is redirected to the weak predefined callback
* @param hdcmi DCMI handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID
* @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID
* @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID
* @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID
* @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (hdcmi->State == HAL_DCMI_STATE_READY)
{
switch (CallbackID)
{
case HAL_DCMI_FRAME_EVENT_CB_ID :
hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */
break;
case HAL_DCMI_VSYNC_EVENT_CB_ID :
hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */
break;
case HAL_DCMI_LINE_EVENT_CB_ID :
hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */
break;
case HAL_DCMI_ERROR_CB_ID :
hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hdcmi->State == HAL_DCMI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DCMI_MSPINIT_CB_ID :
hdcmi->MspInitCallback = HAL_DCMI_MspInit;
break;
case HAL_DCMI_MSPDEINIT_CB_ID :
hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit;
break;
default :
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DCMI_Private_Functions DCMI Private Functions
* @{
*/
/**
* @brief DMA conversion complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
uint32_t tmp1;
uint32_t tmp2;
DMA_NodeTypeDef *pnode;
uint32_t pbuff;
uint32_t transfernumber;
uint32_t transfercount;
uint32_t transfersize ;
/* Update Nodes destinations */
if (hdcmi->XferSize != 0U)
{
pbuff = hdcmi->pBuffPtr;
transfernumber = hdcmi->XferTransferNumber;
transfercount = hdcmi->XferCount;
transfersize = hdcmi->XferSize;
tmp1 = hdcmi->DMA_Handle->Instance->CLLR & DMA_CLLR_LA;
tmp2 = hdcmi->DMA_Handle->Instance->CLBAR & DMA_CLBAR_LBA;
pnode = (DMA_NodeTypeDef *)(uint32_t)(tmp1 | tmp2);
if (hdcmi->XferCount > 1U)
{
pnode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pbuff + ((transfernumber - transfercount + 2U) * transfersize);
hdcmi->XferCount--;
}
else if (hdcmi->XferCount == 1U)
{
pnode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = hdcmi->pBuffPtr;
hdcmi->XferCount--;
}
else
{
pnode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = hdcmi->pBuffPtr + hdcmi->XferSize;
/* When Continuous mode, re-set dcmi XferCount */
if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_CONTINUOUS)
{
hdcmi->XferCount = hdcmi->XferTransferNumber ;
}
/* When snapshot mode, set dcmi state to ready */
else
{
hdcmi->State = HAL_DCMI_STATE_READY;
}
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
}
}
else /* Snapshot Mode */
{
/* Enable the Frame interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
/* When snapshot mode, set dcmi state to ready */
if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
{
hdcmi->State = HAL_DCMI_STATE_READY;
}
}
}
/**
* @brief DMA error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
{
DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_ULE)
{
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Set DCMI Error Code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
}
/* DCMI error Callback */
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
/*Call registered DCMI error callback*/
hdcmi->ErrorCallback(hdcmi);
#else
HAL_DCMI_ErrorCallback(hdcmi);
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
}
/**
* @}
*/
/**
* @}
*/
#endif /* DCMI */
#endif /* HAL_DCMI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c
|
C
|
apache-2.0
| 44,291
|
/**
**********************************************************************************************************************
* @file stm32u5xx_hal_dma.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following functionalities of the Direct Memory Access
* (DMA) peripheral:
* + Initialization/De-Initialization Functions
* + I/O Operation Functions
* + State and Errors Functions
* + DMA Attributes Functions
*
**********************************************************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
**********************************************************************************************************************
@verbatim
======================================================================================================================
############### How to use this driver ###############
======================================================================================================================
[..]
DMA transfer modes are divided to 2 major categories :
(+) Normal transfers (legacy)
(+) Linked-list transfers
[..]
Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended
module.
[..]
Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended
module as extensions to normal mode.
Advanced features are :
(+) Repeated block feature.
(+) Trigger feature.
(+) Data handling feature.
[..]
DMA Legacy circular transfer, is replaced by circular linked-list configuration.
*** Initialization and De-Initialization ***
============================================
[..]
For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal
SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between
peripherals and DMA requests.
[..]
For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through
the following parameters:
(+) Request : Specifies the DMA channel request
Request parameters :
(++) can be a value of @ref DMA_Request_Selection
(+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel
(++) can be a value of @ref DMA_Block_Request
(+) Direction : Specifies the transfer direction for DMA channel
(++) can be a value of @ref DMA_Transfer_Direction
(+) SrcInc : Specifies the source increment mode for the DMA channel
(++) can be a value of @ref DMA_Source_Increment_Mode
(+) DestInc : Specifies the destination increment mode for the DMA channel
(++) can be a value of @ref DMA_Destination_Increment_Mode
(+) SrcDataWidth : Specifies the source data width for the DMA channel
(++) can be a value of @ref DMA_Source_Data_Width
(+) DestDataWidth : Specifies the destination data width for the DMA channel
(++) can be a value of @ref DMA_Destination_Data_Width
(+) Priority : Specifies the priority for the DMA channel
(++) can be a value of @ref DMA_Priority_Level
(+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel
(++) can be a value of between 1 and 64
(+) DestBurstLength : Specifies the destination burst length (number of beats) for the DMA channel
(++) can be a value of between 1 and 64
(+) TransferAllocatedPort : Specifies the source and destination allocated ports
(++) can be a value of @ref DMA_Transfer_Allocated_Port
(+) TransferEventMode : Specifies the transfer event mode for the DMA channel
(++) can be a value of @ref DMA_Transfer_Event_Mode
(+) Mode : Specifies the transfer mode for the DMA channel
(++) can be a value of @ref DMA_Transfer_Mode
*** Polling mode IO operation ***
=================================
[..]
(+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination
address and the size of data to be transferred.
(+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be
configured by User depending on his application.
Transfer level can be :
(++) HAL_DMA_HALF_TRANSFER
(++) HAL_DMA_FULL_TRANSFER
For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code.
(+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode.
This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA
channel. (This API should not be called from an interrupt service routine)
*** Interrupt mode IO operation ***
===================================
[..]
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
(+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list :
(++) XferCpltCallback : transfer complete callback.
(++) XferHalfCpltCallback : half transfer complete callback.
(++) XferErrorCallback : transfer error callback.
(++) XferAbortCallback : transfer abort complete callback.
(++) XferSuspendCallback : transfer suspend complete callback.
(+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration
of source address,destination address and the size of data to be transferred.
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt.
(+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode.
This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended,
an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback
XferAbortCallback. (This API could be called from an interrupt service routine)
*** State and errors ***
========================
[..]
(+) Use HAL_DMA_GetState() function to get the DMA state.
(+) Use HAL_DMA_GetError() function to get the DMA error code.
*** Security and privilege attributes ***
=========================================
[..]
(+) Use HAL_DMA_ConfigChannelAttributes() function to configure DMA channel security and privilege attributes.
(++) Security : at channel level, at source level and at destination level.
(++) Privilege : at channel level.
(+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes.
(+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes
configuration. This API is called once after each system boot.
When this API is called, HAL_DMA_ConfigChannelAttributes() API cannot be used anymore.
(+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status.
*** DMA HAL driver macros list ***
==================================
[..]
Below the list of most used macros in DMA HAL driver.
(+) __HAL_DMA_ENABLE : Enable the specified DMA Channel.
(+) __HAL_DMA_DISABLE : Disable the specified DMA Channel.
(+) __HAL_DMA_GET_FLAG : Get the DMA Channel pending flags.
(+) __HAL_DMA_CLEAR_FLAG : Clear the DMA Channel pending flags.
(+) __HAL_DMA_ENABLE_IT : Enable the specified DMA Channel interrupts.
(+) __HAL_DMA_DISABLE_IT : Disable the specified DMA Channel interrupts.
(+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not.
[..]
(@) You can refer to the header file of the DMA HAL driver for more useful macros.
@endverbatim
**********************************************************************************************************************
*/
/* Includes ----------------------------------------------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup DMA DMA
* @brief DMA HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private typedef ---------------------------------------------------------------------------------------------------*/
/* Private constants -------------------------------------------------------------------------------------------------*/
/* Private macro -----------------------------------------------------------------------------------------------------*/
/* Private variables -------------------------------------------------------------------------------------------------*/
/* Private function prototypes ---------------------------------------------------------------------------------------*/
static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma,
uint32_t SrcAddress,
uint32_t DstAddress,
uint32_t SrcDataSize);
static void DMA_Init(DMA_HandleTypeDef const *const hdma);
/* Exported functions ------------------------------------------------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions DMA Exported Functions
* @{
*/
/** @addtogroup DMA_Exported_Functions_Group1
*
@verbatim
======================================================================================================================
############### Initialization and de-initialization functions ###############
======================================================================================================================
[..]
This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode.
[..]
(+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual.
(+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel.
@endverbatim
* @{
*/
/**
* @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and
* create the associated handle.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma)
{
/* Get tick number */
uint32_t tickstart = HAL_GetTick();
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
if ((hdma->Init.Direction == DMA_MEMORY_TO_PERIPH) || (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY))
{
assert_param(IS_DMA_REQUEST(hdma->Init.Request));
}
assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest));
assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc));
assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc));
assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth));
assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode));
assert_param(IS_DMA_MODE(hdma->Init.Mode));
/* Check DMA channel instance */
if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
{
assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength));
assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength));
assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort));
}
/* Allocate lock resource */
__HAL_UNLOCK(hdma);
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
/* Check if the DMA channel is effectively disabled */
while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_ERROR;
return HAL_ERROR;
}
}
/* Initialize the DMA channel registers */
DMA_Init(hdma);
/* Update DMA channel operation mode */
hdma->Mode = hdma->Init.Mode;
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitialize the DMA channel when it is configured in normal mode.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma)
{
DMA_TypeDef *p_dma_instance;
uint32_t tickstart = HAL_GetTick();
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Get DMA instance */
p_dma_instance = GET_DMA_INSTANCE(hdma);
/* Disable the selected DMA Channel */
__HAL_DMA_DISABLE(hdma);
/* Check if the DMA channel is effectively disabled */
while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_ERROR;
return HAL_ERROR;
}
}
/* Reset DMA Channel registers */
hdma->Instance->CLBAR = 0U;
hdma->Instance->CCR = 0U;
hdma->Instance->CTR1 = 0U;
hdma->Instance->CTR2 = 0U;
hdma->Instance->CBR1 = 0U;
hdma->Instance->CSAR = 0U;
hdma->Instance->CDAR = 0U;
hdma->Instance->CLLR = 0U;
/* Reset 2D Addressing registers */
if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
{
hdma->Instance->CTR3 = 0U;
hdma->Instance->CBR2 = 0U;
}
/* Clear privilege attribute */
CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Clear secure attribute */
CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
DMA_FLAG_TO));
/* Clean all callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
hdma->XferSuspendCallback = NULL;
/* Clean DMA queue */
hdma->LinkedListQueue = NULL;
/* Clean DMA parent */
if (hdma->Parent != NULL)
{
hdma->Parent = NULL;
}
/* Update DMA channel operation mode */
hdma->Mode = DMA_NORMAL;
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group2
*
@verbatim
======================================================================================================================
############### IO operation functions ###############
======================================================================================================================
[..]
This section provides functions allowing to :
(+) Configure the source, destination address and data size and Start DMA transfer in normal mode
(+) Abort DMA transfer
(+) Poll for transfer complete
(+) Handle DMA interrupt request
(+) Register and Unregister DMA callbacks
[..]
(+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode).
(+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode).
(+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode).
(+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode).
(+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode).
This API cannot be used for circular transfers.
(+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode).
(+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and
unregister user customized callbacks.
User callbacks are called under HAL_DMA_IRQHandler().
@endverbatim
* @{
*/
/**
* @brief Start the DMA channel transfer in normal mode (Blocking mode).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
* the specified DMA Channel.
* @param SrcAddress : The source data address.
* @param DstAddress : The destination data address.
* @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma,
uint32_t SrcAddress,
uint32_t DstAddress,
uint32_t SrcDataSize)
{
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize));
/* Process locked */
__HAL_LOCK(hdma);
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Configure the source address, destination address, the data size and clear flags */
DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize);
/* Enable DMA channel */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param SrcAddress : The source data address.
* @param DstAddress : The destination data address.
* @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma,
uint32_t SrcAddress,
uint32_t DstAddress,
uint32_t SrcDataSize)
{
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize));
/* Process locked */
__HAL_LOCK(hdma);
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Configure the source address, destination address, the data size and clear flags */
DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize);
/* Enable common interrupts: Transfer Complete and Transfer Errors ITs */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO));
/* Check half transfer complete callback */
if (hdma->XferHalfCpltCallback != NULL)
{
/* If Half Transfer complete callback is set, enable the corresponding IT */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
}
/* Check Half suspend callback */
if (hdma->XferSuspendCallback != NULL)
{
/* If Transfer suspend callback is set, enable the corresponding IT */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP);
}
/* Enable DMA channel */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Abort any on-going DMA channel transfer (Blocking mode).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @note After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel
* is suspended while a data transfer is on-going, the current data will be transferred and the channel will be
* effectively suspended only after the transfer of any on-going data is finished.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma)
{
/* Get tick number */
uint32_t tickstart = HAL_GetTick();
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check DMA channel state */
if (hdma->State != HAL_DMA_STATE_BUSY)
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
else
{
/* Suspend the channel */
hdma->Instance->CCR |= DMA_CCR_SUSP;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_SUSPEND;
/* Check if the DMA Channel is suspended */
while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
{
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_ERROR;
/* Check DMA channel transfer mode */
if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
/* Update the linked-list queue state */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
}
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
}
/* Reset the channel */
hdma->Instance->CCR |= DMA_CCR_RESET;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_ABORT;
/* Clear all status flags */
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
DMA_FLAG_TO));
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_READY;
/* Check DMA channel transfer mode */
if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
/* Update the linked-list queue state */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
/* Clear remaining data size to ensure loading linked-list from memory next start */
hdma->Instance->CBR1 = 0U;
}
/* Process Unlocked */
__HAL_UNLOCK(hdma);
}
return HAL_OK;
}
/**
* @brief Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma)
{
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check DMA channel state */
if (hdma->State != HAL_DMA_STATE_BUSY)
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
return HAL_ERROR;
}
else
{
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_ABORT;
/* Suspend the channel and activate suspend interrupt */
hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE);
}
return HAL_OK;
}
/**
* @brief Polling for transfer status (Blocking mode).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param CompleteLevel : Specifies the DMA level complete.
* @param Timeout : Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma,
HAL_DMA_LevelCompleteTypeDef CompleteLevel,
uint32_t Timeout)
{
/* Get tick number */
uint32_t tickstart = HAL_GetTick();
uint32_t level_flag;
uint32_t tmp_csr;
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel));
/* Check DMA channel state */
if (hdma->State != HAL_DMA_STATE_BUSY)
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
/* Polling mode is not supported in circular mode */
if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR)
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Get the level transfer complete flag */
level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT);
/* Get DMA channel status */
tmp_csr = hdma->Instance->CSR;
while ((tmp_csr & level_flag) == 0U)
{
/* Check for the timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
/*
If timeout, abort the current transfer.
Note that the Abort function will
- Clear all transfer flags.
- Unlock.
- Set the State.
*/
(void)HAL_DMA_Abort(hdma);
return HAL_ERROR;
}
}
/* Get a newer CSR register value */
tmp_csr = hdma->Instance->CSR;
}
/* Check trigger overrun flag */
if ((tmp_csr & DMA_FLAG_TO) != 0U)
{
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TO;
/* Clear the error flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO);
}
/* Check error flags */
if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U)
{
/* Check the data transfer error flag */
if ((tmp_csr & DMA_FLAG_DTE) != 0U)
{
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_DTE;
/* Clear the error flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE);
}
/* Check the update link error flag */
if ((tmp_csr & DMA_FLAG_ULE) != 0U)
{
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_ULE;
/* Clear the error flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE);
}
/* Check the user setting error flag */
if ((tmp_csr & DMA_FLAG_USE) != 0U)
{
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_USE;
/* Clear the error flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE);
}
/* Reset the channel */
hdma->Instance->CCR |= DMA_CCR_RESET;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_READY;
/* Check DMA channel transfer mode */
if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
/* Update the linked-list queue state */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
}
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
/* Clear the transfer level flag */
if (CompleteLevel == HAL_DMA_HALF_TRANSFER)
{
/* Clear the Half Transfer flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT);
}
else if (CompleteLevel == HAL_DMA_FULL_TRANSFER)
{
/* Clear the transfer flags */
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT));
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_READY;
/* Check DMA channel transfer mode */
if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
/* Update the linked-list queue state */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
}
/* Process unlocked */
__HAL_UNLOCK(hdma);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Handle DMA interrupt request (Non-blocking mode).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval None.
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
{
DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma);
uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
/* Global Interrupt Flag management *********************************************************************************/
if (IS_DMA_GLOBAL_ACTIVE_FLAG(p_dma_instance, global_it_flag) == 0U)
{
return; /* the global interrupt flag for the current channel is down , nothing to do */
}
/* Data Transfer Error Interrupt management *************************************************************************/
if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U))
{
/* Check if interrupt source is enabled */
if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U)
{
/* Clear the transfer error flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE);
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_DTE;
}
}
/* Update Linked-list Error Interrupt management ********************************************************************/
if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U))
{
/* Check if interrupt source is enabled */
if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U)
{
/* Clear the update linked-list error flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE);
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_ULE;
}
}
/* User Setting Error Interrupt management **************************************************************************/
if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U))
{
/* Check if interrupt source is enabled */
if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U)
{
/* Clear the user setting error flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE);
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_USE;
}
}
/* Trigger Overrun Interrupt management *****************************************************************************/
if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U))
{
/* Check if interrupt source is enabled */
if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U)
{
/* Clear the trigger overrun flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO);
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TO;
}
}
/* Half Transfer Complete Interrupt management **********************************************************************/
if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U))
{
/* Check if interrupt source is enabled */
if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
{
/* Clear the half transfer flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT);
/* Check half transfer complete callback */
if (hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
}
}
}
/* Suspend Transfer Interrupt management ****************************************************************************/
if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U))
{
/* Check if interrupt source is enabled */
if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U)
{
/* Clear the block transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP);
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_ABORT)
{
/* Disable the suspend transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP);
/* Reset the channel internal state and reset the FIFO */
hdma->Instance->CCR |= DMA_CCR_RESET;
if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
{
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_ERROR;
}
else
{
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_READY;
}
/* Check DMA channel transfer mode */
if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
/* Update the linked-list queue state */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
}
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Check transfer abort callback */
if (hdma->XferAbortCallback != NULL)
{
/* Transfer abort callback */
hdma->XferAbortCallback(hdma);
}
return;
}
else
{
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_SUSPEND;
/* Check transfer suspend callback */
if (hdma->XferSuspendCallback != NULL)
{
/* Transfer suspend callback */
hdma->XferSuspendCallback(hdma);
}
}
}
}
/* Transfer Complete Interrupt management ***************************************************************************/
if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U))
{
/* Check if interrupt source is enabled */
if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
{
/* Check DMA channel transfer mode */
if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
/* If linked-list transfer */
if (hdma->Instance->CLLR == 0U)
{
if (hdma->Instance->CBR1 == 0U)
{
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_READY;
/* Update the linked-list queue state */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
}
}
}
else
{
/* If normal transfer */
if (hdma->Instance->CBR1 == 0U)
{
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_READY;
}
}
/* Clear TC and HT transfer flags */
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT));
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Check transfer complete callback */
if (hdma->XferCpltCallback != NULL)
{
/* Channel Transfer Complete callback */
hdma->XferCpltCallback(hdma);
}
}
}
/* Manage error case ************************************************************************************************/
if (hdma->ErrorCode != HAL_DMA_ERROR_NONE)
{
/* Reset the channel internal state and reset the FIFO */
hdma->Instance->CCR |= DMA_CCR_RESET;
if ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
{
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_ERROR;
}
else
{
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_READY;
}
/* Check DMA channel transfer mode */
if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
/* Update the linked-list queue state */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
}
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Check transfer error callback */
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
}
/**
* @brief Register callback according to specified ID.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration.
* @param pCallback : Pointer to private callback function.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
HAL_DMA_CallbackIDTypeDef CallbackID,
void (*const pCallback)(DMA_HandleTypeDef *const _hdma))
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma);
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Check callback ID */
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
{
/* Register transfer complete callback */
hdma->XferCpltCallback = pCallback;
break;
}
case HAL_DMA_XFER_HALFCPLT_CB_ID:
{
/* Register half transfer callback */
hdma->XferHalfCpltCallback = pCallback;
break;
}
case HAL_DMA_XFER_ERROR_CB_ID:
{
/* Register transfer error callback */
hdma->XferErrorCallback = pCallback;
break;
}
case HAL_DMA_XFER_ABORT_CB_ID:
{
/* Register abort callback */
hdma->XferAbortCallback = pCallback;
break;
}
case HAL_DMA_XFER_SUSPEND_CB_ID:
{
/* Register suspend callback */
hdma->XferSuspendCallback = pCallback;
break;
}
default:
{
/* Update error status */
status = HAL_ERROR;
break;
}
}
}
else
{
/* Update error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
/**
* @brief Unregister callback according to specified ID.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
HAL_DMA_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma);
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Check callback ID */
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
{
/* UnRegister transfer complete callback */
hdma->XferCpltCallback = NULL;
break;
}
case HAL_DMA_XFER_HALFCPLT_CB_ID:
{
/* UnRegister half transfer callback */
hdma->XferHalfCpltCallback = NULL;
break;
}
case HAL_DMA_XFER_ERROR_CB_ID:
{
/* UnRegister transfer error callback */
hdma->XferErrorCallback = NULL;
break;
}
case HAL_DMA_XFER_ABORT_CB_ID:
{
/* UnRegister abort callback */
hdma->XferAbortCallback = NULL;
break;
}
case HAL_DMA_XFER_SUSPEND_CB_ID:
{
/* UnRegister suspend callback */
hdma->XferSuspendCallback = NULL;
break;
}
case HAL_DMA_XFER_ALL_CB_ID:
{
/* UnRegister all available callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
hdma->XferSuspendCallback = NULL;
break;
}
default:
{
/* Update error status */
status = HAL_ERROR;
break;
}
}
}
else
{
/* Update error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group3
*
@verbatim
======================================================================================================================
############### State and Errors functions ###############
======================================================================================================================
[..]
This section provides functions allowing to :
(+) Check the DMA state
(+) Get error code
[..]
(+) The HAL_DMA_GetState() function allows to get the DMA channel state.
(+) The HAL_DMA_DeInit() function allows to get the DMA channel error code.
@endverbatim
* @{
*/
/**
* @brief Returns the DMA channel state.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval DMA state.
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma)
{
/* Return the DMA channel state */
return hdma->State;
}
/**
* @brief Return the DMA channel error code.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval DMA Error Code.
*/
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma)
{
/* Return the DMA channel error code */
return hdma->ErrorCode;
}
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group4
*
@verbatim
======================================================================================================================
############### DMA Attributes functions ###############
======================================================================================================================
[..]
This section provides functions allowing to :
(+) Configure DMA channel secure and privilege attributes.
(+) Get DMA channel secure and privilege attributes.
(+) Lock DMA channel secure and privilege attributes configuration.
(+) Check whether DMA channel secure and privilege attributes configuration is locked or not.
[..]
(+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel security and privilege
attributes.
(+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel security and privilege attributes
configuration.
(+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel security and privilege attributes.
(+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel security and privilege
attributes lock status.
@endverbatim
* @{
*/
/**
* @brief Configure the DMA channel security and privilege attribute(s).
* @note These attributes cannot be modified when the corresponding lock state is enabled.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
* the specified DMA Channel.
* @param ChannelAttributes : Specifies the DMA channel secure/privilege attributes.
* This parameter can be a one or a combination of @ref DMA_Channel_Attributes.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes)
{
DMA_TypeDef *p_dma_instance;
uint32_t channel_idx;
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes));
/* Get DMA instance */
p_dma_instance = GET_DMA_INSTANCE(hdma);
/* Get channel index */
channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
/* Check DMA channel privilege attribute management */
if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK)
{
/* Configure DMA channel privilege attribute */
if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV)
{
p_dma_instance->PRIVCFGR |= channel_idx;
}
else
{
p_dma_instance->PRIVCFGR &= (~channel_idx);
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Check DMA channel security attribute management */
if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) == DMA_CHANNEL_ATTR_SEC_MASK)
{
/* Configure DMA channel security attribute */
if ((ChannelAttributes & DMA_CHANNEL_SEC) == DMA_CHANNEL_SEC)
{
p_dma_instance->SECCFGR |= channel_idx;
}
else
{
p_dma_instance->SECCFGR &= (~channel_idx);
}
}
/* Channel source security attribute management */
if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) == DMA_CHANNEL_ATTR_SEC_SRC_MASK)
{
/* Configure DMA channel source security attribute */
if ((ChannelAttributes & DMA_CHANNEL_SRC_SEC) == DMA_CHANNEL_SRC_SEC)
{
hdma->Instance->CTR1 |= DMA_CTR1_SSEC;
}
else
{
hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC);
}
}
/* Channel destination security attribute management */
if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) == DMA_CHANNEL_ATTR_SEC_DEST_MASK)
{
/* Configure DMA channel destination security attribute */
if ((ChannelAttributes & DMA_CHANNEL_DEST_SEC) == DMA_CHANNEL_DEST_SEC)
{
hdma->Instance->CTR1 |= DMA_CTR1_DSEC;
}
else
{
hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC);
}
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
return HAL_OK;
}
/**
* @brief Get the DMA channel security and privilege attributes.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
* for the specified DMA Channel.
* @param pChannelAttributes : Pointer to the returned attributes.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
uint32_t *const pChannelAttributes)
{
DMA_TypeDef *p_dma_instance;
uint32_t attributes;
uint32_t channel_idx;
/* Check the DMA peripheral handle and channel attributes parameters */
if ((hdma == NULL) || (pChannelAttributes == NULL))
{
return HAL_ERROR;
}
/* Get DMA instance */
p_dma_instance = GET_DMA_INSTANCE(hdma);
/* Get channel index */
channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
/* Get DMA channel privilege attribute */
attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Get DMA channel security attribute */
attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC;
/* Get DMA channel source security attribute */
attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC;
/* Get DMA channel destination security attribute */
attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC;
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* return value */
*pChannelAttributes = attributes;
return HAL_OK;
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Lock the DMA channel security and privilege attribute(s).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma)
{
DMA_TypeDef *p_dma_instance;
uint32_t channel_idx;
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Get DMA instance */
p_dma_instance = GET_DMA_INSTANCE(hdma);
/* Get channel index */
channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
/* Lock the DMA channel privilege and security attributes */
p_dma_instance->RCFGLOCKR |= channel_idx;
return HAL_OK;
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @brief Get the security and privilege attribute lock state of a DMA channel.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or
* DMA_CHANNEL_ATTRIBUTE_LOCKED).
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState)
{
DMA_TypeDef *p_dma_instance;
uint32_t channel_idx;
/* Check the DMA peripheral handle and lock state parameters */
if ((hdma == NULL) || (pLockState == NULL))
{
return HAL_ERROR;
}
/* Get DMA instance */
p_dma_instance = GET_DMA_INSTANCE(hdma);
/* Get channel index */
channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
/* Get channel lock attribute state */
*pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \
DMA_CHANNEL_ATTRIBUTE_LOCKED;
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions -------------------------------------------------------------------------------------------------*/
/** @defgroup DMA_Private_Functions DMA Private Functions
* @brief DMA Private Functions
* @{
*/
/**
* @brief Set the DMA channel normal transfer parameters.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param SrcAddress : The source data address.
* @param DstAddress : The destination data address.
* @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
* @retval None.
*/
static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma,
uint32_t SrcAddress,
uint32_t DstAddress,
uint32_t SrcDataSize)
{
/* Configure the DMA channel data size */
MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT));
/* Clear all interrupt flags */
__HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
DMA_FLAG_TO);
/* Configure DMA channel source address */
hdma->Instance->CSAR = SrcAddress;
/* Configure DMA channel destination address */
hdma->Instance->CDAR = DstAddress;
}
/**
* @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval None.
*/
static void DMA_Init(DMA_HandleTypeDef const *const hdma)
{
uint32_t tmpreg;
/* Prepare DMA Channel Control Register (CCR) value *****************************************************************/
tmpreg = hdma->Init.Priority;
/* Write DMA Channel Control Register (CCR) */
MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
/* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/
tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth;
/* Add parameters specific to GPDMA */
if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
{
tmpreg |= (hdma->Init.TransferAllocatedPort |
(((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) |
(((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1));
}
/* Write DMA Channel Transfer Register 1 (CTR1) */
MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg);
/* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/
tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode;
/* Memory to Peripheral Transfer */
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
{
tmpreg |= DMA_CTR2_DREQ;
}
}
/* Memory to Memory Transfer */
else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY)
{
tmpreg |= DMA_CTR2_SWREQ;
}
else
{
/* Nothing to do */
}
/* Write DMA Channel Transfer Register 2 (CTR2) */
MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM |
DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_REQSEL), tmpreg);
/* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/
WRITE_REG(hdma->Instance->CBR1, 0U);
/* If 2D Addressing is supported by current channel */
if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
{
/* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/
WRITE_REG(hdma->Instance->CTR3, 0U);
/* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/
WRITE_REG(hdma->Instance->CBR2, 0U);
}
/* Write DMA Channel linked-list address register (CLLR) ************************************************************/
WRITE_REG(hdma->Instance->CLLR, 0U);
}
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c
|
C
|
apache-2.0
| 56,304
|
/**
******************************************************************************
* @file stm32u5xx_hal_dma2d.c
* @author MCD Application Team
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Program the required configuration through the following parameters:
the transfer mode, the output color mode and the output offset using
HAL_DMA2D_Init() function.
(#) Program the required configuration through the following parameters:
the input color mode, the input color, the input alpha value, the alpha mode,
the red/blue swap mode, the inverted alpha mode and the input offset using
HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
*** Polling mode IO operation ***
=================================
[..]
(#) Configure pdata parameter (explained hereafter), destination and data length
and enable the transfer using HAL_DMA2D_Start().
(#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
user can specify the value of timeout according to his end application.
*** Interrupt mode IO operation ***
===================================
[..]
(#) Configure pdata parameter, destination and data length and enable
the transfer using HAL_DMA2D_Start_IT().
(#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
(#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback (member
of DMA2D handle structure).
(#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
XferErrorCallback.
-@- In Register-to-Memory transfer mode, pdata parameter is the register
color, in Memory-to-memory or Memory-to-Memory with pixel format
conversion pdata is the source address.
-@- Configure the foreground source address, the background source address,
the destination and data length then Enable the transfer using
HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
in interrupt mode.
-@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
are used if the memory to memory with blending transfer mode is selected.
(#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
(#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
(#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
HAL_DMA2D_DisableDeadTime().
(#) The transfer can be suspended, resumed and aborted using the following
functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
(#) The CLUT loading can be suspended, resumed and aborted using the following
functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
HAL_DMA2D_CLUTLoading_Abort().
(#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
(#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
*** DMA2D HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DMA2D HAL driver :
(+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
(+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
(+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
(+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
(+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
(+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
*** Callback registration ***
===================================
[..]
(#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
(#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
(+) XferCpltCallback : callback for transfer complete.
(+) XferErrorCallback : callback for transfer error.
(+) LineEventCallback : callback for line event.
(+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
(+) MspInitCallback : DMA2D MspInit.
(+) MspDeInitCallback : DMA2D MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) XferCpltCallback : callback for transfer complete.
(+) XferErrorCallback : callback for transfer error.
(+) LineEventCallback : callback for line event.
(+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
(+) MspInitCallback : DMA2D MspInit.
(+) MspDeInitCallback : DMA2D MspDeInit.
(#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
as weak (surcharged) functions. They must be defined by the user to be resorted to.
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
or @ref HAL_DMA2D_Init function.
When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
[..]
(@) You can refer to the DMA2D HAL driver header file for more useful macros
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
#ifdef HAL_DMA2D_MODULE_ENABLED
#if defined (DMA2D)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup DMA2D DMA2D
* @brief DMA2D HAL module driver
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
* @{
*/
/** @defgroup DMA2D_TimeOut DMA2D Time Out
* @{
*/
#define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */
#define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */
/**
* @}
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
* @{
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
uint32_t Height);
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
* @{
*/
/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DMA2D
(+) De-initialize the DMA2D
@endverbatim
* @{
*/
/**
* @brief Initialize the DMA2D according to the specified
* parameters in the DMA2D_InitTypeDef and create the associated handle.
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
{
/* Check the DMA2D peripheral state */
if (hdma2d == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
if (hdma2d->State == HAL_DMA2D_STATE_RESET)
{
/* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
if (hdma2d->MspInitCallback == NULL)
{
hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
}
/* Init the low level hardware */
hdma2d->MspInitCallback(hdma2d);
}
#else
if (hdma2d->State == HAL_DMA2D_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hdma2d->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
}
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* DMA2D CR register configuration -------------------------------------------*/
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
/* DMA2D OPFCCR register configuration ---------------------------------------*/
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB,
hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
/* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS),
((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \
(hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
return HAL_OK;
}
/**
* @brief Deinitializes the DMA2D peripheral registers to their default reset
* values.
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
{
/* Check the DMA2D peripheral state */
if (hdma2d == NULL)
{
return HAL_ERROR;
}
/* Before aborting any DMA2D transfer or CLUT loading, check
first whether or not DMA2D clock is enabled */
if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
{
/* Abort DMA2D transfer if any */
if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
{
if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
{
/* Issue when aborting DMA2D transfer */
return HAL_ERROR;
}
}
else
{
/* Abort background CLUT loading if any */
if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
{
if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
{
/* Issue when aborting background CLUT loading */
return HAL_ERROR;
}
}
else
{
/* Abort foreground CLUT loading if any */
if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
{
if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
{
/* Issue when aborting foreground CLUT loading */
return HAL_ERROR;
}
}
}
}
}
/* Reset DMA2D control registers*/
hdma2d->Instance->CR = 0U;
hdma2d->Instance->IFCR = 0x3FU;
hdma2d->Instance->FGOR = 0U;
hdma2d->Instance->BGOR = 0U;
hdma2d->Instance->FGPFCCR = 0U;
hdma2d->Instance->BGPFCCR = 0U;
hdma2d->Instance->OPFCCR = 0U;
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
if (hdma2d->MspDeInitCallback == NULL)
{
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
}
/* DeInit the low level hardware */
hdma2d->MspDeInitCallback(hdma2d);
#else
/* Carry on with de-initialization of low level hardware */
HAL_DMA2D_MspDeInit(hdma2d);
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdma2d);
return HAL_OK;
}
/**
* @brief Initializes the DMA2D MSP.
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_DMA2D_MspInit can be implemented in the user file.
*/
}
/**
* @brief DeInitializes the DMA2D MSP.
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_DMA2D_MspDeInit can be implemented in the user file.
*/
}
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DMA2D Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hdma2d DMA2D handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
* @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
* @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
* @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
* @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
* @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
* @retval status
*/
HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
pDMA2D_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma2d);
if (HAL_DMA2D_STATE_READY == hdma2d->State)
{
switch (CallbackID)
{
case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
hdma2d->XferCpltCallback = pCallback;
break;
case HAL_DMA2D_TRANSFERERROR_CB_ID :
hdma2d->XferErrorCallback = pCallback;
break;
case HAL_DMA2D_LINEEVENT_CB_ID :
hdma2d->LineEventCallback = pCallback;
break;
case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
hdma2d->CLUTLoadingCpltCallback = pCallback;
break;
case HAL_DMA2D_MSPINIT_CB_ID :
hdma2d->MspInitCallback = pCallback;
break;
case HAL_DMA2D_MSPDEINIT_CB_ID :
hdma2d->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
{
switch (CallbackID)
{
case HAL_DMA2D_MSPINIT_CB_ID :
hdma2d->MspInitCallback = pCallback;
break;
case HAL_DMA2D_MSPDEINIT_CB_ID :
hdma2d->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma2d);
return status;
}
/**
* @brief Unregister a DMA2D Callback
* DMA2D Callback is redirected to the weak (surcharged) predefined callback
* @param hdma2d DMA2D handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
* @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
* @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
* @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
* @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
* @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
* @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
* @retval status
*/
HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma2d);
if (HAL_DMA2D_STATE_READY == hdma2d->State)
{
switch (CallbackID)
{
case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
hdma2d->XferCpltCallback = NULL;
break;
case HAL_DMA2D_TRANSFERERROR_CB_ID :
hdma2d->XferErrorCallback = NULL;
break;
case HAL_DMA2D_LINEEVENT_CB_ID :
hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
break;
case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
break;
case HAL_DMA2D_MSPINIT_CB_ID :
hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
break;
case HAL_DMA2D_MSPDEINIT_CB_ID :
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
break;
default :
/* Update the error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
{
switch (CallbackID)
{
case HAL_DMA2D_MSPINIT_CB_ID :
hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
break;
case HAL_DMA2D_MSPDEINIT_CB_ID :
hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
break;
default :
/* Update the error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma2d);
return status;
}
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the pdata, destination address and data size then
start the DMA2D transfer.
(+) Configure the source for foreground and background, destination address
and data size then start a MultiBuffer DMA2D transfer.
(+) Configure the pdata, destination address and data size then
start the DMA2D transfer with interrupt.
(+) Configure the source for foreground and background, destination address
and data size then start a MultiBuffer DMA2D transfer with interrupt.
(+) Abort DMA2D transfer.
(+) Suspend DMA2D transfer.
(+) Resume DMA2D transfer.
(+) Enable CLUT transfer.
(+) Configure CLUT loading then start transfer in polling mode.
(+) Configure CLUT loading then start transfer in interrupt mode.
(+) Abort DMA2D CLUT loading.
(+) Suspend DMA2D CLUT loading.
(+) Resume DMA2D CLUT loading.
(+) Poll for transfer complete.
(+) handle DMA2D interrupt request.
(+) Transfer watermark callback.
(+) CLUT Transfer Complete callback.
@endverbatim
* @{
*/
/**
* @brief Start the DMA2D Transfer.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param pdata Configure the source memory Buffer address if
* Memory-to-Memory or Memory-to-Memory with pixel format
* conversion mode is selected, or configure
* the color value if Register-to-Memory mode is selected.
* @param DstAddress The destination memory Buffer address.
* @param Width The width of data to be transferred from source
* to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
return HAL_OK;
}
/**
* @brief Start the DMA2D Transfer with interrupt enabled.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param pdata Configure the source memory Buffer address if
* the Memory-to-Memory or Memory-to-Memory with pixel format
* conversion mode is selected, or configure
* the color value if Register-to-Memory mode is selected.
* @param DstAddress The destination memory Buffer address.
* @param Width The width of data to be transferred from source
* to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
/* Enable the transfer complete, transfer error and configuration error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
return HAL_OK;
}
/**
* @brief Start the multi-source DMA2D Transfer.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param SrcAddress1 The source memory Buffer address for the foreground layer.
* @param SrcAddress2 The source memory Buffer address for the background layer.
* @param DstAddress The destination memory Buffer address.
* @param Width The width of data to be transferred from source
* to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
{
/*blending & fixed FG*/
WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
}
else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
{
/*blending & fixed BG*/
WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
}
else
{
/* Configure DMA2D Stream source2 address */
WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
}
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
return HAL_OK;
}
/**
* @brief Start the multi-source DMA2D Transfer with interrupt enabled.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param SrcAddress1 The source memory Buffer address for the foreground layer.
* @param SrcAddress2 The source memory Buffer address for the background layer.
* @param DstAddress The destination memory Buffer address.
* @param Width The width of data to be transferred from source
* to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG)
{
/*blending & fixed FG*/
WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress2, DstAddress, Width, Height);
}
else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_BG)
{
/*blending & fixed BG*/
WRITE_REG(hdma2d->Instance->BGCOLR, SrcAddress2);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
}
else
{
WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
}
/* Enable the transfer complete, transfer error and configuration error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
return HAL_OK;
}
/**
* @brief Abort the DMA2D Transfer.
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
{
uint32_t tickstart;
/* Abort the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue) */
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
/* Get tick */
tickstart = HAL_GetTick();
/* Check if the DMA2D is effectively disabled */
while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_TIMEOUT;
}
}
/* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
/* Change the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_OK;
}
/**
* @brief Suspend the DMA2D Transfer.
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
{
uint32_t tickstart;
/* Suspend the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
/* Get tick */
tickstart = HAL_GetTick();
/* Check if the DMA2D is effectively suspended */
while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
{
if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
}
else
{
/* Make sure SUSP bit is cleared since it is meaningless
when no transfer is on-going */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
}
return HAL_OK;
}
/**
* @brief Resume the DMA2D Transfer.
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
{
/* Check the SUSP and START bits */
if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
{
/* Ongoing transfer is suspended: change the DMA2D state before resuming */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
}
/* Resume the DMA2D transfer */
/* START bit is reset to make sure not to set it again, in the event the HW clears it
between the register read and the register write by the CPU (writing 0 has no
effect on START bitvalue). */
CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START));
return HAL_OK;
}
/**
* @brief Enable the DMA2D CLUT Transfer.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Enable the background CLUT loading */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
}
else
{
/* Enable the foreground CLUT loading */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
return HAL_OK;
}
/**
* @brief Start DMA2D CLUT Loading.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
}
/* Configure the CLUT of the foreground DMA2D layer */
else
{
/* Write foreground CLUT memory address */
WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
return HAL_OK;
}
/**
* @brief Start DMA2D CLUT Loading with interrupt enabled.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
}
/* Configure the CLUT of the foreground DMA2D layer */
else
{
/* Write foreground CLUT memory address */
WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
return HAL_OK;
}
/**
* @brief Start DMA2D CLUT Loading.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @note API obsolete and maintained for compatibility with legacy. User is
* invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from
* code compactness, code size and improved heap usage.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
}
/* Configure the CLUT of the foreground DMA2D layer */
else
{
/* Write foreground CLUT memory address */
WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
return HAL_OK;
}
/**
* @brief Start DMA2D CLUT Loading with interrupt enabled.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @note API obsolete and maintained for compatibility with legacy. User is
* invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit
* from code compactness, code size and improved heap usage.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
}
/* Configure the CLUT of the foreground DMA2D layer */
else
{
/* Write foreground CLUT memory address */
WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
}
return HAL_OK;
}
/**
* @brief Abort the DMA2D CLUT loading.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
uint32_t tickstart;
const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
/* Abort the CLUT loading */
SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
/* If foreground CLUT loading is considered, update local variables */
if (LayerIdx == DMA2D_FOREGROUND_LAYER)
{
reg = &(hdma2d->Instance->FGPFCCR);
}
/* Get tick */
tickstart = HAL_GetTick();
/* Check if the CLUT loading is aborted */
while ((*reg & DMA2D_BGPFCCR_START) != 0U)
{
if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_TIMEOUT;
}
}
/* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
/* Change the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_OK;
}
/**
* @brief Suspend the DMA2D CLUT loading.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
uint32_t tickstart;
uint32_t loadsuspended;
const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
/* Suspend the CLUT loading */
SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
/* If foreground CLUT loading is considered, update local variables */
if (LayerIdx == DMA2D_FOREGROUND_LAYER)
{
reg = &(hdma2d->Instance->FGPFCCR);
}
/* Get tick */
tickstart = HAL_GetTick();
/* Check if the CLUT loading is suspended */
/* 1st condition: Suspend Check */
loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
/* 2nd condition: Not Start Check */
loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
while (loadsuspended == 0UL)
{
if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
/* 1st condition: Suspend Check */
loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
/* 2nd condition: Not Start Check */
loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
}
/* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
if ((*reg & DMA2D_BGPFCCR_START) != 0U)
{
hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
}
else
{
/* Make sure SUSP bit is cleared since it is meaningless
when no transfer is on-going */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
}
return HAL_OK;
}
/**
* @brief Resume the DMA2D CLUT loading.
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
/* Check the SUSP and START bits for background or foreground CLUT loading */
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Background CLUT loading suspension check */
if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
{
if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
{
/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
}
}
}
else
{
/* Foreground CLUT loading suspension check */
if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
{
if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
{
/* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
}
}
}
/* Resume the CLUT loading */
CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
return HAL_OK;
}
/**
* @brief Polling for transfer complete or CLUT loading.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t layer_start;
__IO uint32_t isrflags = 0x0U;
/* Polling for DMA2D transfer */
if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
{
isrflags = READ_REG(hdma2d->Instance->ISR);
if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
{
if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
}
if ((isrflags & DMA2D_FLAG_TE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
}
/* Clear the transfer and configuration error flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_ERROR;
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_TIMEOUT;
}
}
}
}
/* Polling for CLUT loading (foreground or background) */
layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
if (layer_start != 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
{
isrflags = READ_REG(hdma2d->Instance->ISR);
if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
{
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
}
if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
}
if ((isrflags & DMA2D_FLAG_TE) != 0U)
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
}
/* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_ERROR;
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_TIMEOUT;
}
}
}
}
/* Clear the transfer complete and CLUT loading flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_OK;
}
/**
* @brief Handle DMA2D interrupt request.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
{
uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
uint32_t crflags = READ_REG(hdma2d->Instance->CR);
/* Transfer Error Interrupt management ***************************************/
if ((isrflags & DMA2D_FLAG_TE) != 0U)
{
if ((crflags & DMA2D_IT_TE) != 0U)
{
/* Disable the transfer Error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
/* Clear the transfer error flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
if (hdma2d->XferErrorCallback != NULL)
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
}
}
}
/* Configuration Error Interrupt management **********************************/
if ((isrflags & DMA2D_FLAG_CE) != 0U)
{
if ((crflags & DMA2D_IT_CE) != 0U)
{
/* Disable the Configuration Error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
/* Clear the Configuration error flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
if (hdma2d->XferErrorCallback != NULL)
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
}
}
}
/* CLUT access Error Interrupt management ***********************************/
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
{
if ((crflags & DMA2D_IT_CAE) != 0U)
{
/* Disable the CLUT access error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
/* Clear the CLUT access error flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
if (hdma2d->XferErrorCallback != NULL)
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
}
}
}
/* Transfer watermark Interrupt management **********************************/
if ((isrflags & DMA2D_FLAG_TW) != 0U)
{
if ((crflags & DMA2D_IT_TW) != 0U)
{
/* Disable the transfer watermark interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
/* Clear the transfer watermark flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
/* Transfer watermark Callback */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
hdma2d->LineEventCallback(hdma2d);
#else
HAL_DMA2D_LineEventCallback(hdma2d);
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
}
}
/* Transfer Complete Interrupt management ************************************/
if ((isrflags & DMA2D_FLAG_TC) != 0U)
{
if ((crflags & DMA2D_IT_TC) != 0U)
{
/* Disable the transfer complete interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
/* Clear the transfer complete flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
if (hdma2d->XferCpltCallback != NULL)
{
/* Transfer complete Callback */
hdma2d->XferCpltCallback(hdma2d);
}
}
}
/* CLUT Transfer Complete Interrupt management ******************************/
if ((isrflags & DMA2D_FLAG_CTC) != 0U)
{
if ((crflags & DMA2D_IT_CTC) != 0U)
{
/* Disable the CLUT transfer complete interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
/* Clear the CLUT transfer complete flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
/* CLUT Transfer complete Callback */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
hdma2d->CLUTLoadingCpltCallback(hdma2d);
#else
HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
}
}
}
/**
* @brief Transfer watermark callback.
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_DMA2D_LineEventCallback can be implemented in the user file.
*/
}
/**
* @brief CLUT Transfer Complete callback.
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the DMA2D foreground or background layer parameters.
(+) Configure the DMA2D CLUT transfer.
(+) Configure the line watermark
(+) Configure the dead time value.
(+) Enable or disable the dead time value functionality.
@endverbatim
* @{
*/
/**
* @brief Configure the DMA2D Layer according to the specified
* parameters in the DMA2D_HandleTypeDef.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
DMA2D_LayerCfgTypeDef *pLayerCfg;
uint32_t regMask;
uint32_t regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
if (hdma2d->Init.Mode != DMA2D_R2M)
{
assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
if (hdma2d->Init.Mode != DMA2D_M2M)
{
assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
}
}
assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
/* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \
(pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
{
regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
}
else
{
regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
}
/* Configure the background DMA2D layer */
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write DMA2D BGPFCCR register */
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
/* DMA2D BGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
/* DMA2D BGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
{
WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
DMA2D_BGCOLR_RED));
}
}
/* Configure the foreground DMA2D layer */
else
{
/* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
/* DMA2D FGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
/* DMA2D FGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
{
WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
DMA2D_FGCOLR_RED));
}
}
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_OK;
}
/**
* @brief Configure the DMA2D CLUT Transfer.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
* @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @note API obsolete and maintained for compatibility with legacy. User is invited
* to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness,
* code size and improved heap usage.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Configure the CLUT of the background DMA2D layer */
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
{
/* Write background CLUT memory address */
WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
}
/* Configure the CLUT of the foreground DMA2D layer */
else
{
/* Write foreground CLUT memory address */
WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
}
/* Set the DMA2D state to Ready*/
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_OK;
}
/**
* @brief Configure the line watermark.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @param Line Line Watermark configuration (maximum 16-bit long value expected).
* @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
* @note The transfer watermark interrupt is disabled once it has occurred.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
{
/* Check the parameters */
if (Line > DMA2D_LWR_LW)
{
return HAL_ERROR;
}
else
{
/* Process locked */
__HAL_LOCK(hdma2d);
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Sets the Line watermark configuration */
WRITE_REG(hdma2d->Instance->LWR, Line);
/* Enable the Line interrupt */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_OK;
}
}
/**
* @brief Enable DMA2D dead time feature.
* @param hdma2d DMA2D handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
{
/* Process Locked */
__HAL_LOCK(hdma2d);
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Set DMA2D_AMTCR EN bit */
SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_OK;
}
/**
* @brief Disable DMA2D dead time feature.
* @param hdma2d DMA2D handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
{
/* Process Locked */
__HAL_LOCK(hdma2d);
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Clear DMA2D_AMTCR EN bit */
CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_OK;
}
/**
* @brief Configure dead time.
* @note The dead time value represents the guaranteed minimum number of cycles between
* two consecutive transactions on the AHB bus.
* @param hdma2d DMA2D handle.
* @param DeadTime dead time value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
{
/* Process Locked */
__HAL_LOCK(hdma2d);
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Set DMA2D_AMTCR DT field */
MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
hdma2d->State = HAL_DMA2D_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to:
(+) Get the DMA2D state
(+) Get the DMA2D error code
@endverbatim
* @{
*/
/**
* @brief Return the DMA2D state
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL state
*/
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
{
return hdma2d->State;
}
/**
* @brief Return the DMA2D error code
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for DMA2D.
* @retval DMA2D Error Code
*/
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
{
return hdma2d->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
* @{
*/
/**
* @brief Set the DMA2D transfer parameters.
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the specified DMA2D.
* @param pdata The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param Width The width of data to be transferred from source to destination.
* @param Height The height of data to be transferred from source to destination.
* @retval HAL status
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
uint32_t Height)
{
uint32_t tmp;
uint32_t tmp1;
uint32_t tmp2;
uint32_t tmp3;
uint32_t tmp4;
/* Configure DMA2D data size */
MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
/* Register to memory DMA2D mode selected */
if (hdma2d->Init.Mode == DMA2D_R2M)
{
tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
tmp2 = pdata & DMA2D_OCOLR_RED_1;
tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
/* Prepare the value to be written to the OCOLR register according to the color mode */
if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
{
tmp = (tmp3 | tmp2 | tmp1 | tmp4);
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
{
tmp = (tmp3 | tmp2 | tmp4);
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
{
tmp2 = (tmp2 >> 19U);
tmp3 = (tmp3 >> 10U);
tmp4 = (tmp4 >> 3U);
tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
{
tmp1 = (tmp1 >> 31U);
tmp2 = (tmp2 >> 19U);
tmp3 = (tmp3 >> 11U);
tmp4 = (tmp4 >> 3U);
tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
}
else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
{
tmp1 = (tmp1 >> 28U);
tmp2 = (tmp2 >> 20U);
tmp3 = (tmp3 >> 12U);
tmp4 = (tmp4 >> 4U);
tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
}
/* Write to DMA2D OCOLR register */
WRITE_REG(hdma2d->Instance->OCOLR, tmp);
}
else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/
{
WRITE_REG(hdma2d->Instance->BGMAR, pdata);
}
else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */
{
/* Configure DMA2D source address */
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DMA2D */
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c
|
C
|
apache-2.0
| 75,283
|
/**
**********************************************************************************************************************
* @file stm32u5xx_hal_dma_ex.c
* @author MCD Application Team
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following functionalities of the DMA extension
* peripheral:
* + Linked-List Initialization and De-Initialization Functions
* + Linked-List I/O Operation Functions
* + Linked-List Management Functions
* + Data Handling, Repeated Block and Trigger Configuration Functions
* + Suspend and Resume Operation Functions
* + FIFO Status Function
*
**********************************************************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
**********************************************************************************************************************
@verbatim
======================================================================================================================
############### How to use this driver ###############
======================================================================================================================
[..]
Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as
linked-list (list of Node items). Each node is defined by its data structure.
Each node specifies a standalone DMA channel.
When enabled, the DMA channel fetch the first linked-list node from SRAM (known as head node). When executed, the
next linked list node will be fetched and executed. This operation is repeated until the end of the whole
linked-list queue. Optionally, the linked-list can be linear where the last linked-list queue node is not linked
to another queue node or circular where the last linked-list node is linked to any linked-list queue node.
(+) Linear linked-list:
The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node
(tail node) ones. When the last node is completed, the DMA channel remains in idle state and another
transfer can be lunched.
(+) Circular linked-list:
The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node (tail
node). When last node is executed, the DMA channel fetches the first circular node another time and repeat
the same sequence in an infinite loop (Circular transfer). To stop the DMA channel, an abort operation is
required. This linked-list mode replaces the legacy circular transfers.
[..]
In order to reduce linked-list queue executing time and power consumption, the DMA channel supports executing the
dynamic linked-list format. In fact, the DMA supports the execution of 2 types of linked-list formats : static and
dynamic.
(+) Static linked-list:
The static linked-list format refers to the full linked-list node where all DMA channel parameters are
fetched and executed independently of the redundancy of information.
(+) Dynamic linked-list:
The dynamic linked-list format refer to the customized linked-list node where only DMA channel necessary
parameters are fetched and executed (Example: data size = 20 on previous node, and data size = 20 on the
current node => No need to update it).
For linked-list transfers, the DMA channel can execute the linked-list queue node by node. This feature is named
link step mode. When activated, enabling the DMA channel first time allows to fetch the head node from memory
then it stops. Then, another DMA channel enable is needed to execute the node. After that, keeping enabling the
DMA channel is needed to execute each node until the end of linked-list queue. When the linked-list queue is
circular, enabling the DMA channel in an infinite loop is required to keep the DMA channel running. This feature
is useful for debug purpose or asynchronously executing queue nodes.
[..]
Each DMA channel transfer (normal or linked-list), is highly configurable according to DMA channel instance
integrated in devices. These configuration can be :
(+) Repeated block configuration :
If the feature is supported, the DMA channel can performs a repeated block transfers. Named also 2
dimension addressing transfers, this feature can transfer n iteration of programmed block transfer (Block
transfer is the legacy data size). Additional to the repeat count of a block, DMA channel addresses can
jump after at burst and block level. The jump length is a programmable parameter defined by DMA user.
(++) Jump at burst level :
The DMA channel keep an empty area, between each 2 consecutive bursts transmitted.
(++) Jump at block level :
The DMA channel keep an empty area, between each 2 consecutive blocks transmitted.
(+) Trigger :
The DMA channel transfers can be conditioned by hardware signals edges (rising or falling) named hardware
triggers. Trigger condition can be applied at :
(++) Single/Burst level :
Each single/burst data transmission is conditioned by a signal trigger hit.
(++) Block level :
Each block data transmission is conditioned by a signal trigger hit.
(++) Repeated block level :
Each repeated block data transmission is conditioned by a signal trigger hit.
(++) Node level :
Each node execution is conditioned by a signal trigger hit.
The DMA channel can report a trigger overrun when detects more than 2 trigger signal edges before
executing the current transfer.
(+) Data handling :
The data handling feature is a FIFO capability that can be :
(++) Padding pattern :
Padding selected pattern (zero padding or sign extension) when the source data width is smaller
than the destination data width at single level.
(++) Truncation :
Truncate section from the source data single when the source data width is bigger than the
destination data width.
(++) Pack/Unpack :
Pack a set of data when source data width is smaller than the destination data width.
Unpack a set of data when source data width is bigger than the destination data width.
(++) Exchange :
Exchange data at byte and half-word on the destination and at byte level on the source.
[..]
Each DMA channel transfer (normal or linked-list) when it is active, can be suspended and resumed at run time
application. When trying to suspend an ongoing transfer, the DMA channel isn't suspended instantly but complete
the current ongoing single/burst then it stops.
When the DMA channel is suspended, the current transfer can be resumed instantly.
[..]
The DMA channel that supports FIFO, can report in real time the number of beats remains on destination (Output)
FIFO level.
*** Linked-List Initialization and De-Initialization operation ***
==================================================================
[..]
Differently from normal transfers, DMA channel initialization and de-initialization need less parameters as the
remaining transfer parameters are defined by linked-list nodes.
(+) Use HAL_DMAEx_List_Init() to initialize a DMA channel in linked-list mode according to programmed fields.
When called, the DMA channel will be ready to execute linked-list queues.
(+) Use HAL_DMAEx_List_DeInit() to de-initialize a DMA channel in linked-list mode.
When called, the DMA channel will be in reset. It is mandatory to reinitialize it for next transfer.
*** Linked-List I/O Operation ***
=================================
[..]
(+) Use HAL_DMAEx_List_Start() to start a DMA transfer in linked-list mode after the configuration of
linked-list queue base address and offset in polling mode (Blocking mode).
(+) Use HAL_DMAEx_List_Start_IT() to start a DMA transfer in linked-list mode after the configuration of
linked-list queue base address and offset in interrupt mode (Non-blocking mode).
*** Linked-List Management ***
==============================
[..]
The linked-list management is a software processing independently of DMA channel hardware. It allows to reset,
build, create, insert, remove, replace, circularize, convert both nodes and queue in order to perform DMA
channel transfers in linked-list mode.
Linked-list APIs and types are adapted to reduce memory footprint.
*** Linked-list nodes building ***
[..]
At node level, the operations that can be done are building a new linked-list node or get a linked-list node
information from a built node. The linked-list nodes have two forms according to 2 dimensions addressing
capability. The linear addressing nodes contains the information of all DMA channel features except the 2
dimension addressing features and the 2 dimensions addressing nodes contain the information of all available
features.
(+) Use HAL_DMAEx_List_BuildNode() to build the DMA linked-list node according to the specified parameters.
Build operation allow to convert the specified parameter in values known by the DMA channel and place them
in memory.
Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the
link access port can access to the specified SRAM.
(+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node.
This API can be used when need to change few parameter to build new node.
*** Inserting nodes to linked-list queue ***
[..]
In order to build a sequence of DMA transaction with different configuration, we need to insert built node at
linked-list queue (node present an elementary DMA transaction) in linked-list queue on any position to have the
full flexibility of ordering nodes or extend the sequence of queue transactions.
(+) Use HAL_DMAEx_List_InsertNode() to insert new built node in any queue position of linked-list queue
according to selecting previous node. When calling this API with previous node parameter is NULL, the
inserted node will be placed at the head of the linked-list queue.
(++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned.
(++) This API must be called for static queues format.
(++) This API shall be avoided when adding new node at the head or the tail of queue (overhead of
footprint and performance : use HAL_DMAEx_List_InsertNode_Head() or HAL_DMAEx_List_InsertNode_Tail()
instead).
(+) Use HAL_DMAEx_List_InsertNode_Head() to insert new built node at the head of linked-list queue. The head
node will not be overwritten but will be the second queue node.
(++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned.
(++) This API must be called for static queues format.
(+) Use HAL_DMAEx_List_InsertNode_Tail() to insert new built node at the tail of linked-list queue. The tail
node will not be overwritten but will be the penultimate queue node.
(++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned.
(++) This API must be called for static queues format.
*** Removing nodes from linked-list queue ***
[..]
There is some cases when removing a node from linked-list queue is needed (need to remove an elementary DMA
transaction). Removing node allows to unlink a node from DMA linked-list queue (NOT DELETED), so the removed node
can be reused for another queue or to be added to the same queue without need to rebuild it in next step.
(+) Use HAL_DMAEx_List_RemoveNode() to remove any yet built and inserted node from linked-list queue according
to selected node.
(++) This API must be called for static queues format.
(++) This API shall be avoided when removing the head or the tail of linked-list queue (overhead of
footprint and performance : use HAL_DMAEx_List_RemoveNode_Head() or HAL_DMAEx_List_RemoveNode_Tail()
instead).
(+) Use HAL_DMAEx_List_RemoveNode_Head() to remove the head node from linked-list queue.
(++) This API must be called for static queues format.
(+) Use HAL_DMAEx_List_RemoveNode_Tail() to remove the tail node from linked-list queue.
(++) This API must be called for static queues format.
*** Replacing nodes on linked-list queue ***
[..]
There is some cases when replacing a node from linked-list queue is needed (need to replace an elementary DMA
transfer, by another one that have not the same configuration). Replacing node allows to unlink the node to be
replaced from DMA linked-list queue (NOT DELETED) and link instead a new node. So the replaced node can be reused
for another queue or to be added to the same queue without need to rebuild it in next step and the new node cannot
be reused except when remove it or replaced in next step.
(+) Use HAL_DMAEx_List_ReplaceNode() to replace any yet built and inserted node on linked-list queue according
to selected node.
(++) This API must be called for static queues format.
(++) This API shall be avoided when replacing the head or the tail linked-list queue (overhead of
footprint and performance : use HAL_DMAEx_List_ReplaceNode_Head() or
HAL_DMAEx_List_ReplaceNode_Tail() instead).
(+) Use HAL_DMAEx_List_ReplaceNode_Head() to replace the head node of linked-list queue.
(++) This API must be called for static queues format.
(+) Use HAL_DMAEx_List_ReplaceNode_Tail() to replace the tail node from linked-list queue.
(++) This API must be called for static queues format.
*** Reset linked-list queue ***
[..]
After finishing using a linked-list queue, it can be reset and cleared and it's content nodes will be
unlinked (NOT DELETED) and reused on another queue.
(+) Use HAL_DMAEx_List_ResetQ() to reset a linked-list queue and unlink all it's content nodes.
(++) This API must be called for ready state queues.
(++) This API must be called for static queues format.
*** Inserting linked-list queue ***
[..]
To ensure the flexibility of building linked-list queue by their targeted functionalities (Example: 3 nodes for
action 1 and 5 nodes for action 2), it is possible to build a queue for action 1 that contains action 1 nodes and
a queue for action 2 that contains action 2 nodes then concatenating the 2 queues. So, there are some cases where
the management of linked-list at queue granularity is needed.
(+) Use HAL_DMAEx_List_InsertQ() to insert source linked-list queue to a destination linked-list queue
according to selecting previous node.
(++) This API must be called for static queues format.
(++) This API shall be avoided when inserting source linked-list queue at the head or the tail of
destination queue (overhead of footprint and performance : use HAL_DMAEx_List_InsertQ_Head() or
HAL_DMAEx_List_InsertQ_Tail() instead).
(+) Use HAL_DMAEx_List_InsertQ_Head() to insert a source linked-list queue at the head of linked-list
destination queue.
(++) This API must be called for static queues format.
(+) Use HAL_DMAEx_List_InsertQ_Tail() to insert a source linked-list queue at the tail of linked-list
destination queue.
(++) This API must be called for static queues format.
*** Circularizing linked-list queue ***
[..]
In order to perform tasks in infinite loop with DMA channel, it is possible to circularize the linked-list queues.
Circularizing queue allows to link last linked-list queue node to any previous node of the same queue (This node
is named first circular queue). When the first circular node is the head node, all linked-list queue nodes will be
executed in infinite loop. When the first circular node is not the head nodes, all precedent nodes are executed
once and all remaining nodes are executed in an infinite loop.
(+) Use HAL_DMAEx_List_SetCircularModeConfig() to circularize the linked-list queue according to first
circular node selected.
(++) This API must be called for static queues format.
(++) This API shall be avoided when first circular node is the head linked-list queue node (overhead of
footprint and performance : use HAL_DMAEx_List_SetCircularMode() instead).
(+) Use HAL_DMAEx_List_SetCircularMode() to circularize the linked-list queue with linking last queue node
with first queue node.
(++) This API must be called for static queues format.
(+) Use HAL_DMAEx_List_ClearCircularMode() to clear any linked-list queue circular configuration.
(++) This API must be called for static queues format.
*** Converting linked-list queue ***
[..]
To have the best DMA channel linked-list queue execution, it is recommended to convert yet build linked-list queue
to dynamic format (Static is the default format). When linked-list queue becomes dynamic, all queue nodes are
optimized and only changed parameters will be updated between nodes. So, the DMA will fetch only changes
parameters instead of the whole node.
(+) Use HAL_DMAEx_List_ConvertQToDynamic() to convert a linked-list queue to dynamic format.
(++) This API must be called for ready state queues.
(++) This API must be called for static queues format.
(++) This API must be called as the last API before starting the DMA channel in linked-list mode.
(+) Use HAL_DMAEx_List_ConvertQToStatic() to convert a linked-list queue to static format.
(++) This API must be called for ready state queues.
(++) This API must be called for dynamic queues format.
(++) This API must be called as the first API after the full execution of linked-list queue when the
execution mode is linear (not circular) if it is dynamic and a linked-list queue management is
needed.
(++) This API must be called as the first API after the aborting the execution of the current linked-list
queue when the execution mode is linear (not circular) if it is dynamic and a linked-list queue
management is needed.
[..]
When converting a circular queue to dynamic format and when the first circular node is the last queue node, it is
recommended to duplicate the last circular node in order to ensure the full optimization when calling
HAL_DMAEx_List_ConvertQToDynamic() API. In this case, updated information are only addresses which allow to reduce
4 words of update for linear nodes per node execution and 6 words update for 2 dimensions addressing nodes per
node execution.
*** Linking linked-list queue to DMA channel ***
[..]
In order to have the possibility of the creation of an infinity queues (limited by available memory size), the
building of linked-list queue is fully independent from DMA channels. It is possible to build all needed queues if
their size is less then available memory at startup time, then linking each time when needed a linked-list queue
to an idle DMA channel.
(+) Use HAL_DMAEx_List_LinkQ() to link a ready linked-list queue to ready DMA channel.
(++) This API supports the two format of linked-list (Static and dynamic).
(++) This API must be called for ready state queues and DMA channels.
(+) Use HAL_DMAEx_List_ConvertQToStatic() to unlink a ready linked-list queue to ready DMA channel.
(++) This API supports the two format of linked-list (Static and dynamic).
(++) This API must be called for ready state queues and DMA channels.
*** User sequence ***
[..]
To use cleanly the DMA linked-list library, ensure to apply the following call sequences :
(+) Linear transfer :
Linked-list queue building
(++) HAL_DMAEx_List_BuildNode()
(++) HAL_DMAEx_List_InsertNode_Tail()
.
.
.
(++) HAL_DMAEx_List_BuildNode()
(++) HAL_DMAEx_List_InsertNode_Tail()
(++) HAL_DMAEx_List_ConvertQToDynamic()
Linked-list queue execution
(++) HAL_DMAEx_List_Init()
(++) HAL_DMAEx_List_LinkQ()
(++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT()
(++) HAL_DMAEx_List_UnLinkQ()
(++) HAL_DMAEx_List_DeInit()
(+) Circular transfer :
Linked-list queue building
(++) HAL_DMAEx_List_BuildNode()
(++) HAL_DMAEx_List_InsertNode_Tail()
.
.
.
(++) HAL_DMAEx_List_BuildNode()
(++) HAL_DMAEx_List_InsertNode_Tail()
(++) HAL_DMAEx_List_SetCircularModeConfig() / HAL_DMAEx_List_SetCircularMode()
(++) HAL_DMAEx_List_ConvertQToDynamic()
Linked-list queue execution
(++) HAL_DMAEx_List_Init()
(++) HAL_DMAEx_List_LinkQ()
(++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT()
(++) HAL_DMA_Abort() / HAL_DMA_Abort_IT()
(++) HAL_DMAEx_List_UnLinkQ()
(++) HAL_DMAEx_List_DeInit()
*** Data Handling ***
=====================
[..]
In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to
FIFO capabilities titled data handling.
(++) Padding pattern
Padding selected patter (zero padding or sign extension) when the source data width is smaller than
the destination data width at single level.
Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000)
Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA)
(Source : 0xFABA ------> Destination : 0xFFFFFABA)
(++) Truncation :
Truncate section from the source data single when the source data width is bigger than the
destination data width.
Left truncation (Source : 0xABABCDCD ------> Destination : 0xCDCD)
Right truncation (Source : 0xABABCDCD ------> Destination : 0xABAB)
(++) Pack/Unpack :
Pack a set of data when source data width is smaller than the destination data width.
Unpack a set of data when source data width is bigger than the destination data width.
Pack (Source : 0xAB, 0xCD ------> Destination : 0xABCD)
UnPack (Source : 0xABCD ------> Destination : 0xAB, 0xCD)
(++) Exchange :
Exchange data at byte and half-word on the destination and at byte level on the source.
Source byte exchange (Source : 0xAB12CD34 ------> Destination : 0xABCD1234)
Destination byte exchange (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD)
Destination half-word exchange (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12)
(+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained
can be combined according to application needs.
(++) This API is complementary of normal transfers.
(++) This API must not be called for linked-list transfers as data handling information are configured at
node level.
(++) This API must be called only for DMA channel that supports data handling feature.
*** User sequence ***
[..]
To configure cleanly the DMA channel data handling, ensure to apply the following call sequence :
(+) Linear transfer :
(++) HAL_DMA_Init()
(++) HAL_DMAEx_ConfigDataHandling()
(++) HAL_DMA_Start()
*** Repeated Block ***
======================
[..]
When available, this feature is used when the data size is higher then 65535 bytes (Maximum block size) or for
scattering / gathering data.
(++) Gather data
Source Destination
0xAA 0xAA
0xBB 0xAA
0xAA ==> 0xAA
0xCC
0xAA
(++) Scatter data
Source Destination
0xAA 0xAA
0xAA 0xBB
0xAA ==> 0xAA
0xBB
0xAA
(+) Use HAL_DMAEx_ConfigRepeatBlock() to configure data repeated block feature. Jump addresses and
incrementing or decrementing on source and destination can be combined to have the need application
behavior.
(++) This API is complementary of normal transfers.
(++) This API must not be called for linked-list transfers as repeated block information are configured at
node level.
(++) This API must be called only for DMA channel that supports repeated block feature.
*** User sequence ***
[..]
To configure cleanly the DMA channel repeated block, ensure to apply the following call sequence :
(+) Linear transfer :
(++) HAL_DMA_Init()
(++) HAL_DMAEx_ConfigRepeatBlock()
(++) HAL_DMA_Start()
*** Trigger Configuration ***
=============================
[..]
When application needs that DMA transfers are conditioned by internal or external events, the trigger feature can
do that. Trigger signals are a set of device signal that are linked to DMA trigger inputs that allows to start the
DMA transfers.
To setup a trigger transfers, three DMA channel parameters are needed:
(+) Trigger mode
This parameter specifies the trig level.
(++) Block level
(++) Repeated block level
(++) Node level
(++) Single / Burst level
(+) Trigger polarity
This parameter specifies the DMA trigger sensitivity (Rising or falling).
(+) Trigger selection
This parameter specifies the DMA trigger hardware signal.
(+) Use HAL_DMAEx_ConfigTrigger() to configure trigger feature.
(++) This API is complementary to normal transfers APIs.
(++) This API must not be called for linked-list transfers as trigger information are configured at
node level.
*** User sequence ***
[..]
To configure cleanly the DMA channel trigger, ensure to apply the following call sequence :
(+) Linear transfer :
(++) HAL_DMA_Init()
(++) HAL_DMAEx_ConfigTrigger()
(++) HAL_DMA_Start()
*** Suspend and resume operation ***
====================================
[..]
There are several cases when needs to suspend a DMA current transfer (Example: liberate bandwidth for more
priority DMA channel transfer). Suspending DMA channel (same as abort) is available in polling (blocking mode) and
interrupt (non-blocking mode) modes. When suspended, a DMA channel can be instantly resumed.
(+) Use HAL_DMAEx_Suspend() to suspend an ongoing DMA channel transfer in polling mode (Blocking mode).
(+) Use HAL_DMAEx_Suspend_IT() to suspend an ongoing DMA channel transfer in interrupt mode (Non-blocking
mode).
(+) Use HAL_DMAEx_Resume() to resume a suspended DMA channel transfer execution.
*** FIFO status ***
===================
[..]
In several cases, the information of FIFO level is useful to inform at application level how to process remaining
data. When not empty, the DMA channel FIFO cannot be flashed only by reset.
(+) Use HAL_DMAEx_GetFifoLevel() to get the DMA channel FIFO level (available beats in FIFO).
@endverbatim
**********************************************************************************************************************
*/
/* Includes ----------------------------------------------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private types -----------------------------------------------------------------------------------------------------*/
/* Private variables -------------------------------------------------------------------------------------------------*/
/* Private Constants -------------------------------------------------------------------------------------------------*/
/* Private macros ----------------------------------------------------------------------------------------------------*/
/* Private function prototypes ---------------------------------------------------------------------------------------*/
static void DMA_List_Init(DMA_HandleTypeDef const *const hdma);
static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
DMA_NodeTypeDef *const pNode);
static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
DMA_NodeTypeDef const *const pNode);
static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
DMA_NodeTypeDef const *const pNode2,
DMA_NodeTypeDef const *const pNode3);
static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
DMA_NodeTypeDef const *const pNode2,
DMA_NodeTypeDef const *const pNode3);
static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode,
uint32_t *const cllr_mask,
uint32_t *const cllr_offset);
static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList,
DMA_NodeTypeDef const *const pNode,
DMA_NodeInQInfoTypeDef *const NodeInfo);
static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList,
DMA_NodeInQInfoTypeDef const *const NodeInfo);
static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode,
DMA_NodeTypeDef *const pDestNode);
static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr,
uint32_t CurrentNodeAddr,
uint32_t RegisterNumber);
static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr,
uint32_t CurrentNodeAddr,
uint32_t RegisterNumber);
static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
uint32_t LastNode_IsCircular);
static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
uint32_t operation);
static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode,
uint32_t RegisterIdx,
uint32_t RegisterNumber,
uint32_t Format);
static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode,
uint32_t FirstUnusedField);
static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList);
/* Exported functions ------------------------------------------------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions
* @{
*/
/** @addtogroup DMAEx_Exported_Functions_Group1
*
@verbatim
======================================================================================================================
############### Linked-List Initialization and De-Initialization Functions ###############
======================================================================================================================
[..]
This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode.
[..]
(+) The HAL_DMAEx_List_Init() function follows the DMA channel linked-list mode configuration procedures as
described in reference manual.
(+) The HAL_DMAEx_List_DeInit() function allows to de-initialize the DMA channel in linked-list mode.
@endverbatim
* @{
*/
/**
* @brief Initialize the DMA channel in linked-list mode according to the specified parameters in the
* DMA_InitLinkedListTypeDef and create the associated handle.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma)
{
/* Get tick number */
uint32_t tickstart = HAL_GetTick();
/* Check the DMA channel handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMA_PRIORITY(hdma->InitLinkedList.Priority));
assert_param(IS_DMA_LINK_STEP_MODE(hdma->InitLinkedList.LinkStepMode));
assert_param(IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(hdma->InitLinkedList.TransferEventMode));
assert_param(IS_DMA_LINKEDLIST_MODE(hdma->InitLinkedList.LinkedListMode));
/* Check DMA channel instance */
if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
{
assert_param(IS_DMA_LINK_ALLOCATED_PORT(hdma->InitLinkedList.LinkAllocatedPort));
}
/* Allocate lock resource */
__HAL_UNLOCK(hdma);
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
/* Check if the DMA channel is effectively disabled */
while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_ERROR;
return HAL_ERROR;
}
}
/* Initialize the DMA channel registers */
DMA_List_Init(hdma);
/* Update DMA channel operation mode */
hdma->Mode = hdma->InitLinkedList.LinkedListMode;
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitialize the DMA channel when it is configured in linked-list mode.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma)
{
/* Get DMA instance */
DMA_TypeDef *p_dma_instance;
/* Get tick number */
uint32_t tickstart = HAL_GetTick();
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Get DMA instance */
p_dma_instance = GET_DMA_INSTANCE(hdma);
/* Disable the selected DMA Channel */
__HAL_DMA_DISABLE(hdma);
/* Check if the DMA channel is effectively disabled */
while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_ERROR;
return HAL_ERROR;
}
}
/* Reset DMA Channel registers */
hdma->Instance->CCR = 0U;
hdma->Instance->CLBAR = 0U;
hdma->Instance->CTR1 = 0U;
hdma->Instance->CTR2 = 0U;
hdma->Instance->CBR1 = 0U;
hdma->Instance->CSAR = 0U;
hdma->Instance->CDAR = 0U;
hdma->Instance->CLLR = 0U;
/* Reset 2D Addressing registers */
if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
{
hdma->Instance->CTR3 = 0U;
hdma->Instance->CBR2 = 0U;
}
/* Clear privilege attribute */
CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Clear secure attribute */
CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
DMA_FLAG_TO));
/* Clean all callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
hdma->XferSuspendCallback = NULL;
/* Check the linked-list queue */
if (hdma->LinkedListQueue != NULL)
{
/* Update the queue state and error code */
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Clean DMA queue */
hdma->LinkedListQueue = NULL;
}
/* Clean DMA parent */
if (hdma->Parent != NULL)
{
hdma->Parent = NULL;
}
/* Update DMA channel operation mode */
hdma->Mode = DMA_NORMAL;
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup DMAEx_Exported_Functions_Group2
*
@verbatim
======================================================================================================================
############### Linked-List IO Operation Functions ###############
======================================================================================================================
[..]
This section provides functions allowing to :
(+) Configure to start DMA transfer in linked-list mode.
[..]
(+) The HAL_DMAEx_List_Start() function allows to start the DMA channel transfer in linked-list mode (Blocking
mode).
(+) The HAL_DMAEx_List_Start_IT() function allows to start the DMA channel transfer in linked-list mode
(Non-blocking mode).
(++) It is mandatory to register a linked-list queue to be executed by a DMA channel before starting
transfer otherwise a HAL_ERROR will be returned.
@endverbatim
* @{
*/
/**
* @brief Start the DMA channel transfer in linked-list mode (Blocking mode).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma)
{
HAL_DMA_StateTypeDef dma_state;
uint32_t ccr_value;
uint32_t cllr_mask;
/* Check the DMA peripheral handle and the linked-list queue parameters */
if ((hdma == NULL) || (hdma->LinkedListQueue == NULL))
{
return HAL_ERROR;
}
/* Check DMA channel state */
dma_state = hdma->State;
ccr_value = hdma->Instance->CCR & DMA_CCR_LSM;
if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U)))
{
/* Check DMA channel state is ready */
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Process locked */
__HAL_LOCK(hdma);
/* Update the DMA channel and the queue states */
hdma->State = HAL_DMA_STATE_BUSY;
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the DMA channel and the queue error codes */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL);
/* Update DMA registers for linked-list transfer */
hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA);
hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask;
}
/* Enable DMA channel */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Starts the DMA channel transfer in linked-list mode with interrupts enabled (Non-blocking mode).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma)
{
HAL_DMA_StateTypeDef dma_state;
uint32_t ccr_value;
uint32_t cllr_mask;
/* Check the DMA peripheral handle and the linked-list queue parameters */
if ((hdma == NULL) || (hdma->LinkedListQueue == NULL))
{
return HAL_ERROR;
}
/* Check DMA channel state */
dma_state = hdma->State;
ccr_value = hdma->Instance->CCR & DMA_CCR_LSM;
if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U)))
{
/* Check DMA channel state is ready */
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Process locked */
__HAL_LOCK(hdma);
/* Update the DMA channel and the queue states */
hdma->State = HAL_DMA_STATE_BUSY;
hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the DMA channel and the queue error codes */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Enable common interrupts: Transfer Complete and Transfer Errors ITs */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO));
/* Check half transfer complete callback */
if (hdma->XferHalfCpltCallback != NULL)
{
/* If half transfer complete callback is set, enable the corresponding IT */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
}
/* Check suspend callback */
if (hdma->XferSuspendCallback != NULL)
{
/* If transfer suspend callback is set, enable the corresponding IT */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP);
}
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL);
/* Update DMA registers for linked-list transfer */
hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA);
hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask;
}
/* Enable DMA channel */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Change the error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup DMAEx_Exported_Functions_Group3
*
@verbatim
======================================================================================================================
############### Linked-List Management Functions ###############
======================================================================================================================
[..]
This section provides functions allowing to :
(+) Build linked-list node.
(+) Get linked-list node configuration.
(+) Insert node to linked-list queue in any queue position.
(+) Remove any node from linked-list queue.
(+) Replace any node from linked-list queue.
(+) Reset linked-list queue.
(+) Insert linked-list queue in any queue position.
(+) Set circular mode configuration to linked-list queue.
(+) Clear circular mode configuration from linked-list queue.
(+) Convert static linked-list queue to dynamic format.
(+) Convert dynamic linked-list queue to static format.
(+) Link linked-list queue to DMA channel.
(+) Unlink linked-list queue from DMA channel.
[..]
(+) The HAL_DMAEx_List_BuildNode() function allows to build linked-list node.
Node type can be :
(++) 2 dimensions addressing node.
(++) Linear addressing node.
(+) The HAL_DMAEx_List_GetNodeConfig() function allows to get the linked-list node configuration from built node.
(+) The HAL_DMAEx_List_InsertNode() function allows to insert built linked-list node to static linked-list queue
according to selected position.
(+) The HAL_DMAEx_List_InsertNode_Head() and HAL_DMAEx_List_InsertNode_Tail() functions allow to insert built
linked-list node to the head (respectively the tail) of static linked-list queue.
(+) The HAL_DMAEx_List_RemoveNode() function allows to remove selected built linked-list node from static
linked-list queue.
(+) The HAL_DMAEx_List_RemoveNode_Head() and HAL_DMAEx_List_RemoveNode_Tail() functions allow to remove the head
(respectively the tail) built linked-list node from static linked-list queue.
(+) The HAL_DMAEx_List_ReplaceNode() function allows to replace selected built linked-list node from static
linked-list queue.
(+) The HAL_DMAEx_List_ReplaceNode_Head() and HAL_DMAEx_List_ReplaceNode_Tail() functions allow to replace the
head (respectively the tail) built linked-list node of static linked-list queue.
(+) The HAL_DMAEx_List_ResetQ() function allows to reset static linked-list queue and unlink all built linked-list
nodes.
(+) The HAL_DMAEx_List_InsertQ() function allows to insert static linked-list source queue to static linked-list
destination queue according to selected position.
(+) The HAL_DMAEx_List_InsertQ_Head() and HAL_DMAEx_List_InsertQ_Tail() functions allow to insert static
linked-list source queue to the head (respectively the tail) of static linked-list destination queue.
(+) The HAL_DMAEx_List_SetCircularModeConfig() function allows to link the last static linked-list queue node to
the selected first circular node.
(+) The HAL_DMAEx_List_SetCircularMode() function allows to link the last static linked-list queue node to the
first static linked-list queue node.
(+) The HAL_DMAEx_List_ClearCircularMode() function allows to unlink the last static linked-list queue node from
any first circular node position.
(+) The HAL_DMAEx_List_ConvertQToDynamic() function allows to convert the static linked-list queue to dynamic
format. (Optimized queue execution)
(+) The HAL_DMAEx_List_ConvertQToStatic() function allows to convert the dynamic linked-list queue to static
format. (Not optimized queue execution)
(+) The HAL_DMAEx_List_LinkQ() function allows to link the (Dynamic / Static) linked-list queue to DMA channel to
be executed.
(+) The HAL_DMAEx_List_UnLinkQ() function allows to unlink the (Dynamic / Static) linked-list queue from DMA
channel when execution is completed.
@endverbatim
* @{
*/
/**
* @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef.
* @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
* specified DMA linked-list Node.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
* configurations.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
DMA_NodeTypeDef *const pNode)
{
/* Check the node configuration and physical node parameters */
if ((pNodeConfig == NULL) || (pNode == NULL))
{
return HAL_ERROR;
}
/* Check node type parameter */
assert_param(IS_DMA_NODE_TYPE(pNodeConfig->NodeType));
/* Check DMA channel basic transfer parameters */
assert_param(IS_DMA_SOURCE_INC(pNodeConfig->Init.SrcInc));
assert_param(IS_DMA_DESTINATION_INC(pNodeConfig->Init.DestInc));
assert_param(IS_DMA_SOURCE_DATA_WIDTH(pNodeConfig->Init.SrcDataWidth));
assert_param(IS_DMA_DESTINATION_DATA_WIDTH(pNodeConfig->Init.DestDataWidth));
assert_param(IS_DMA_DATA_ALIGNMENT(pNodeConfig->DataHandlingConfig.DataAlignment));
assert_param(IS_DMA_REQUEST(pNodeConfig->Init.Request));
assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction));
assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode));
assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest));
/* Check DMA channel parameters */
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA)
{
assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.SrcBurstLength));
assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.DestBurstLength));
assert_param(IS_DMA_DATA_EXCHANGE(pNodeConfig->DataHandlingConfig.DataExchange));
assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(pNodeConfig->Init.TransferAllocatedPort));
}
/* Check DMA channel trigger parameters */
assert_param(IS_DMA_TRIGGER_POLARITY(pNodeConfig->TriggerConfig.TriggerPolarity));
if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED)
{
assert_param(IS_DMA_TRIGGER_MODE(pNodeConfig->TriggerConfig.TriggerMode));
assert_param(IS_DMA_TRIGGER_SELECTION(pNodeConfig->TriggerConfig.TriggerSelection));
}
/* Check DMA channel repeated block parameters */
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
{
assert_param(IS_DMA_REPEAT_COUNT(pNodeConfig->RepeatBlockConfig.RepeatCount));
assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset));
assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset));
assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset));
assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset));
assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset));
assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset));
assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset));
assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset));
}
/* Check DMA channel security and privilege attributes parameters */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure));
assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure));
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* Build the DMA channel node */
DMA_List_BuildNode(pNodeConfig, pNode);
return HAL_OK;
}
/**
* @brief Get a DMA channel node configuration.
* @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
* specified DMA linked-list Node.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
* configurations.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
DMA_NodeTypeDef const *const pNode)
{
/* Check the node configuration and physical node parameters */
if ((pNodeConfig == NULL) || (pNode == NULL))
{
return HAL_ERROR;
}
/* Get the DMA channel node configuration */
DMA_List_GetNodeConfig(pNodeConfig, pNode);
return HAL_OK;
}
/**
* @brief Insert new node in any queue position of linked-list queue according to selecting previous node.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers
* configurations.
* @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
* configurations.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pPrevNode,
DMA_NodeTypeDef *const pNewNode)
{
uint32_t cllr_mask;
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue and the new node parameters */
if ((pQList == NULL) || (pNewNode == NULL))
{
return HAL_ERROR;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
return HAL_ERROR;
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
/* Empty queue */
if (pQList->Head == NULL)
{
/* Add only new node to queue */
if (pPrevNode == NULL)
{
pQList->Head = pNewNode;
pQList->NodeNumber = 1U;
}
/* Add previous node then new node to queue */
else
{
pQList->Head = pPrevNode;
pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
pQList->NodeNumber = 2U;
}
}
/* Not empty queue */
else
{
/* Add new node at the head of queue */
if (pPrevNode == NULL)
{
pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
pQList->Head = pNewNode;
}
/* Add new node according to selected position */
else
{
/* Find node and get its position in selected queue */
node_info.cllr_offset = cllr_offset;
if (DMA_List_FindNode(pQList, pPrevNode, &node_info) == 0U)
{
/* Selected node is the last queue node */
if (node_info.currentnode_pos == pQList->NodeNumber)
{
/* Check if queue is circular */
if (pQList->FirstCircularNode != NULL)
{
pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
}
pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
}
/* Selected node is not the last queue node */
else
{
pNewNode->LinkRegisters[cllr_offset] = pPrevNode->LinkRegisters[cllr_offset];
pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
}
}
else
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
return HAL_ERROR;
}
}
/* Increment queue node number */
pQList->NodeNumber++;
}
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
return HAL_OK;
}
/**
* @brief Insert new node at the head of linked-list queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
* configurations.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode)
{
uint32_t cllr_mask;
uint32_t cllr_offset;
/* Check the queue and the new node parameters */
if ((pQList == NULL) || (pNewNode == NULL))
{
return HAL_ERROR;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
return HAL_ERROR;
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Empty queue */
if (pQList->Head == NULL)
{
pQList->Head = pNewNode;
}
/* Not empty queue */
else
{
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
pQList->Head = pNewNode;
}
/* Increment queue node number */
pQList->NodeNumber++;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
return HAL_OK;
}
/**
* @brief Insert new node at the tail of linked-list queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
* configurations.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode)
{
uint32_t cllr_mask;
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue and the new node parameters */
if ((pQList == NULL) || (pNewNode == NULL))
{
return HAL_ERROR;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
return HAL_ERROR;
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Empty queue */
if (pQList->Head == NULL)
{
pQList->Head = pNewNode;
}
/* Not empty queue */
else
{
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
/* Find node and get its position in selected queue */
node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Check if queue is circular */
if (pQList->FirstCircularNode != NULL)
{
pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
}
((DMA_NodeTypeDef *)node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
}
/* Increment queue node number */
pQList->NodeNumber++;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(node_info);
return HAL_OK;
}
/**
* @brief Remove node from any linked-list queue position.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers
* configurations.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNode)
{
uint32_t previousnode_addr;
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue and the node parameters */
if ((pQList == NULL) || (pNode == NULL))
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pNode, NULL, &cllr_offset);
/* Find node and get its position in selected queue */
node_info.cllr_offset = cllr_offset;
if (DMA_List_FindNode(pQList, pNode, &node_info) == 0U)
{
/* Removed node is the head node */
if (node_info.currentnode_pos == 1U)
{
/* Check if first circular node queue is the first node */
if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr))
{
/* Find last queue node */
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Clear last node link */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Clear first circular node */
pQList->FirstCircularNode = NULL;
}
/* Update the queue head node */
pQList->Head = (DMA_NodeTypeDef *)(((uint32_t)pQList->Head & DMA_CLBAR_LBA) +
(pNode->LinkRegisters[cllr_offset] & DMA_CLLR_LA));
/* Unlink node to be removed */
pNode->LinkRegisters[cllr_offset] = 0U;
}
/* Removed node is the last node */
else if (node_info.currentnode_pos == pQList->NodeNumber)
{
/* Clear CLLR for previous node */
((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Clear CLLR for last node */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Clear first circular node */
pQList->FirstCircularNode = NULL;
}
/* Removed node is in the middle */
else
{
/* Store previous node address to be updated later */
previousnode_addr = node_info.previousnode_addr;
/* Check if first circular node queue is the current node */
if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr))
{
/* Find last queue node */
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Clear last node link */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Clear first circular node */
pQList->FirstCircularNode = NULL;
}
/* Link previous node */
((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[cllr_offset] = pNode->LinkRegisters[cllr_offset];
/* Unlink node to be removed */
pNode->LinkRegisters[cllr_offset] = 0U;
}
/* Decrement node number */
pQList->NodeNumber--;
}
else
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
return HAL_ERROR;
}
/* Check if queue is empty */
if (pQList->NodeNumber == 0U)
{
/* Clean empty queue parameter */
DMA_List_CleanQueue(pQList);
}
else
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
}
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(node_info);
return HAL_OK;
}
/**
* @brief Remove the head node from linked-list queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList)
{
uint32_t cllr_offset;
uint32_t current_addr;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue parameter */
if (pQList == NULL)
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
/* Queue contains only one node */
if (pQList->NodeNumber == 1U)
{
pQList->Head->LinkRegisters[cllr_offset] = 0U;
pQList->FirstCircularNode = 0U;
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
}
/* Queue contains more then one node */
else
{
/* Check if first circular node queue is the first node */
if (pQList->FirstCircularNode == pQList->Head)
{
/* Find last queue node */
node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Clear last node link */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Clear first circular node */
pQList->FirstCircularNode = NULL;
}
current_addr = pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
pQList->Head->LinkRegisters[cllr_offset] = 0U;
pQList->Head = ((DMA_NodeTypeDef *)(current_addr + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)));
}
/* Decrement node number */
pQList->NodeNumber--;
/* Check if queue is empty */
if (pQList->NodeNumber == 0U)
{
/* Clean empty queue parameter */
DMA_List_CleanQueue(pQList);
}
else
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
}
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(node_info);
return HAL_OK;
}
/**
* @brief Remove the tail node from linked-list queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList)
{
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue parameter */
if (pQList == NULL)
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
/* Queue contains only one node */
if (pQList->NodeNumber == 1U)
{
pQList->Head->LinkRegisters[cllr_offset] = 0U;
pQList->FirstCircularNode = 0U;
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
}
/* Queue contains more then one node */
else
{
/* Find node and get its position in selected queue */
node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Clear CLLR for previous node */
((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Clear CLLR for last node */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Clear first circular node */
pQList->FirstCircularNode = NULL;
}
/* Decrement node number */
pQList->NodeNumber--;
/* Check if queue is empty */
if (pQList->NodeNumber == 0U)
{
/* Clean empty queue parameter */
DMA_List_CleanQueue(pQList);
}
else
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
}
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(node_info);
return HAL_OK;
}
/**
* @brief Replace node in linked-list queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param pOldNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list old node registers
* configurations.
* @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
* configurations.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pOldNode,
DMA_NodeTypeDef *const pNewNode)
{
uint32_t cllr_mask;
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue and the nodes parameters */
if ((pQList == NULL) || (pOldNode == NULL) || (pNewNode == NULL))
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
return HAL_ERROR;
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
/* Find node and get its position in selected queue */
node_info.cllr_offset = cllr_offset;
if (DMA_List_FindNode(pQList, pOldNode, &node_info) == 0U)
{
/* Replaced node is the head node */
if (node_info.currentnode_pos == 1U)
{
pNewNode->LinkRegisters[cllr_offset] =
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset];
pQList->Head = pNewNode;
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Check if first circular node queue is the first node */
if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr))
{
/* Find last queue node */
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Clear last node link */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
/* Set new node as first circular node */
pQList->FirstCircularNode = pNewNode;
}
}
/* Replaced node is the last */
else if (node_info.currentnode_pos == pQList->NodeNumber)
{
((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Check if first circular node queue is the last node */
if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr)))
{
/* Link first circular node to new node */
pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
/* Set new node as first circular node */
pQList->FirstCircularNode = pNewNode;
}
/* Check if first circular node queue is not the last node */
else if (pQList->FirstCircularNode != NULL)
{
/* Link first circular node to new node */
pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
}
else
{
/* Prevent MISRA-C2012-Rule-15.7 */
}
}
/* Replaced node is in the middle */
else
{
((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
pNewNode->LinkRegisters[cllr_offset] =
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset];
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Check if first circular node queue is the current node */
if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr)))
{
/* Find last node and get its position in selected queue */
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Link last queue node to new node */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
/* Set new node as first circular node */
pQList->FirstCircularNode = pNewNode;
}
}
}
else
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
return HAL_ERROR;
}
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(node_info);
return HAL_OK;
}
/**
* @brief Replace the head node of linked-list queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
* configurations.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode)
{
uint32_t cllr_offset;
uint32_t cllr_mask;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue and the new node parameters */
if ((pQList == NULL) || (pNewNode == NULL))
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
return HAL_ERROR;
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
/* Check if first circular node queue is the first node */
if (pQList->FirstCircularNode == pQList->Head)
{
/* Find last queue node */
node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Clear last node link */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
/* Set new node as first circular node */
pQList->FirstCircularNode = pNewNode;
}
/* Replace head node */
pNewNode->LinkRegisters[cllr_offset] = pQList->Head->LinkRegisters[cllr_offset];
pQList->Head->LinkRegisters[cllr_offset] = 0U;
pQList->Head = pNewNode;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(node_info);
return HAL_OK;
}
/**
* @brief Replace the tail node of linked-list queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers
* configurations.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode)
{
uint32_t cllr_mask;
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue and the new node parameters */
if ((pQList == NULL) || (pNewNode == NULL))
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset);
/* Find last node and get its position in selected queue */
node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Link previous node to new node */
((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
/* Clear CLLR for current node */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Check if first circular node queue is the last node */
if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr)))
{
/* Link first circular node to new node */
pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask;
/* Set new node as first circular node */
pQList->FirstCircularNode = pNewNode;
}
/* Check if first circular node queue is not the last node */
else if (pQList->FirstCircularNode != NULL)
{
/* Link first circular node to new node */
pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask;
}
else
{
/* Prevent MISRA-C2012-Rule-15.7 */
}
/* Check if queue contains one node */
if (pQList->NodeNumber == 1U)
{
pQList->Head = pNewNode;
}
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
return HAL_OK;
}
/**
* @brief Reset the linked-list queue and unlink queue nodes.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList)
{
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue parameter */
if (pQList == NULL)
{
return HAL_ERROR;
}
/* Check queue state */
if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY;
return HAL_ERROR;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Check the queue */
if (pQList->Head != NULL)
{
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
/* Reset selected queue nodes */
node_info.cllr_offset = cllr_offset;
DMA_List_ResetQueueNodes(pQList, &node_info);
}
/* Reset head node address */
pQList->Head = NULL;
/* Reset node number */
pQList->NodeNumber = 0U;
/* Reset first circular node */
pQList->FirstCircularNode = NULL;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_RESET;
return HAL_OK;
}
/**
* @brief Insert a source linked-list queue to a destination linked-list queue according to selecting previous node.
* @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information.
* @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers
* configurations.
* @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
DMA_NodeTypeDef const *const pPrevNode,
DMA_QListTypeDef *const pDestQList)
{
uint32_t cllr_mask;
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef src_q_node_info;
DMA_NodeInQInfoTypeDef dest_q_node_info;
/* Check the source and destination queues and the previous node parameters */
if ((pSrcQList == NULL) || (pDestQList == NULL))
{
return HAL_ERROR;
}
/* Check the source queue */
if (pSrcQList->Head == NULL)
{
/* Update the queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check the source queue type */
if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check the destination queue type */
if (pDestQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check the source queue circularity */
if (pSrcQList->FirstCircularNode != NULL)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
return HAL_ERROR;
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the source queue state */
pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the destination queue state */
pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset);
/* Empty destination queue */
if (pDestQList->Head == NULL)
{
pDestQList->Head = pSrcQList->Head;
pDestQList->NodeNumber = pSrcQList->NodeNumber;
}
/* Not empty destination queue */
else
{
/* Previous node is empty */
if (pPrevNode == NULL)
{
/* Find node and get its position in selected queue */
src_q_node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
/* Check if first circular node queue is the first node */
if (pDestQList->FirstCircularNode == pDestQList->Head)
{
/* Find node and get its position in selected queue */
dest_q_node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info);
/* Link destination queue tail node to new first circular node */
((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
/* Set the head node of source queue as the first circular node */
pDestQList->FirstCircularNode = pSrcQList->Head;
}
/* Link the last node of source queue to the fist node of destination queue */
((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask;
pDestQList->Head = pSrcQList->Head;
pDestQList->NodeNumber += pSrcQList->NodeNumber;
}
/* Previous node is not empty */
else
{
/* Find node and get its position in selected queue */
dest_q_node_info.cllr_offset = cllr_offset;
if (DMA_List_FindNode(pDestQList, pPrevNode, &dest_q_node_info) == 0U)
{
/* Selected node is the last destination queue node */
if (dest_q_node_info.currentnode_pos == pDestQList->NodeNumber)
{
/* Link the first node of source queue to the last node of destination queue */
((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
pDestQList->NodeNumber += pSrcQList->NodeNumber;
/* Check if first circular node queue is not empty */
if (pDestQList->FirstCircularNode != NULL)
{
/* Find node and get its position in selected queue */
src_q_node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
/* Find first circular node */
(void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info);
/* Link last source queue node to first destination queue */
((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
(dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask;
}
}
/* Selected node is not the last destination queue node */
else
{
/* Link the first node of source queue to the previous node of destination queue */
((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
/* Find node and get its position in selected queue */
src_q_node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
/* Link the last node of source queue to the next node of destination queue */
((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
(dest_q_node_info.nextnode_addr & DMA_CLLR_LA) | cllr_mask;
/* Update queues counter */
pDestQList->NodeNumber += pSrcQList->NodeNumber;
}
}
else
{
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
return HAL_ERROR;
}
}
}
/* Clean the source queue variable as it is obsolete */
DMA_List_CleanQueue(pSrcQList);
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the destination queue state */
pDestQList->State = HAL_DMA_QUEUE_STATE_READY;
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(src_q_node_info);
UNUSED(dest_q_node_info);
return HAL_OK;
}
/**
* @brief Insert a source linked-list queue at the head of destination queue.
* @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information.
* @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
DMA_QListTypeDef *const pDestQList)
{
uint32_t cllr_mask;
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef src_q_node_info;
DMA_NodeInQInfoTypeDef dest_q_node_info;
/* Check the source and destination queues and the previous node parameters */
if ((pSrcQList == NULL) || (pDestQList == NULL))
{
return HAL_ERROR;
}
/* Check the source queue */
if (pSrcQList->Head == NULL)
{
/* Update the queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check the source queue type */
if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check the destination queue type */
if (pDestQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
return HAL_ERROR;
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the source queue state */
pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the destination queue state */
pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset);
/* Empty destination queue */
if (pDestQList->Head == NULL)
{
pDestQList->Head = pSrcQList->Head;
pDestQList->NodeNumber = pSrcQList->NodeNumber;
}
/* Not empty destination queue */
else
{
/* Find node and get its position in selected queue */
src_q_node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
/* Check if first circular node queue is the first node */
if (pDestQList->FirstCircularNode == pDestQList->Head)
{
/* Find node and get its position in selected queue */
dest_q_node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info);
/* Link destination queue tail node to new first circular node */
((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
/* Set the head node of source queue as the first circular node */
pDestQList->FirstCircularNode = pSrcQList->Head;
}
/* Link the last node of source queue to the fist node of destination queue */
((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask;
pDestQList->Head = pSrcQList->Head;
pDestQList->NodeNumber += pSrcQList->NodeNumber;
}
/* Clean the source queue variable as it is obsolete */
DMA_List_CleanQueue(pSrcQList);
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the destination queue state */
pDestQList->State = HAL_DMA_QUEUE_STATE_READY;
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(src_q_node_info);
UNUSED(dest_q_node_info);
return HAL_OK;
}
/**
* @brief Insert a source linked-list queue at the tail of destination queue.
* @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information.
* @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
DMA_QListTypeDef *const pDestQList)
{
uint32_t cllr_mask;
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef src_q_node_info;
DMA_NodeInQInfoTypeDef dest_q_node_info;
/* Check the source and destination queues and the previous node parameters */
if ((pSrcQList == NULL) || (pDestQList == NULL))
{
return HAL_ERROR;
}
/* Check the source queue */
if (pSrcQList->Head == NULL)
{
/* Update the queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check the source queue type */
if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check the destination queue type */
if (pDestQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Check nodes base addresses */
if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE;
return HAL_ERROR;
}
/* Check nodes types compatibility */
if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U)
{
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the source queue state */
pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the source queue error code */
pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the destination queue state */
pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset);
/* Empty destination queue */
if (pDestQList->Head == NULL)
{
pDestQList->Head = pSrcQList->Head;
pDestQList->NodeNumber = pSrcQList->NodeNumber;
}
/* Not empty destination queue */
else
{
/* Find node and get its position in selected queue */
dest_q_node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info);
/* Update source queue last node CLLR to link it with destination first node */
((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask;
pDestQList->NodeNumber += pSrcQList->NodeNumber;
/* Check if first circular node queue is not empty */
if (pDestQList->FirstCircularNode != NULL)
{
/* Find node and get its position in selected queue */
src_q_node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info);
/* Find first circular node */
(void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info);
/* Link last source queue node to first destination queue */
((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] =
(dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask;
}
}
/* Clean the source queue variable as it is obsolete */
DMA_List_CleanQueue(pSrcQList);
/* Update the destination queue error code */
pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the destination queue state */
pDestQList->State = HAL_DMA_QUEUE_STATE_READY;
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(src_q_node_info);
return HAL_OK;
}
/**
* @brief Set circular mode configuration for linked-list queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param pFirstCircularNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list first circular node
* registers configurations.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pFirstCircularNode)
{
uint32_t cllr_mask;
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue and the first circular node parameters */
if ((pQList == NULL) || (pFirstCircularNode == NULL))
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check queue circular mode */
if (pQList->FirstCircularNode != NULL)
{
if (pQList->FirstCircularNode == pFirstCircularNode)
{
return HAL_OK;
}
else
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pFirstCircularNode, &cllr_mask, &cllr_offset);
/* Find the first circular node and get its position in selected queue */
node_info.cllr_offset = cllr_offset;
if (DMA_List_FindNode(pQList, pFirstCircularNode, &node_info) == 0U)
{
/* Find the last queue node and get its position in selected queue */
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Set circular mode */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pFirstCircularNode & DMA_CLLR_LA) | cllr_mask;
/* Update first circular node in queue */
pQList->FirstCircularNode = pFirstCircularNode;
}
else
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND;
return HAL_ERROR;
}
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(node_info);
return HAL_OK;
}
/**
* @brief Set circular mode for linked-list queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList)
{
uint32_t cllr_mask;
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue parameter */
if (pQList == NULL)
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check queue circular mode */
if (pQList->FirstCircularNode != NULL)
{
if (pQList->FirstCircularNode == pQList->Head)
{
return HAL_OK;
}
else
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_mask, &cllr_offset);
/* Find the last queue node and get its position in selected queue */
node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Set circular mode */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] =
((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
/* Update linked-list circular state */
pQList->FirstCircularNode = pQList->Head;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(node_info);
return HAL_OK;
}
/**
* @brief Clear circular mode for linked-list queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList)
{
uint32_t cllr_offset;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue parameter */
if (pQList == NULL)
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check queue circular mode */
if (pQList->FirstCircularNode == NULL)
{
return HAL_OK;
}
/* Check queue type */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register offset */
DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
/* Find the last queue node and get its position in selected queue */
node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pQList, NULL, &node_info);
/* Clear circular mode */
((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U;
/* Update linked-list circular configuration */
pQList->FirstCircularNode = NULL;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
/* Prevent MISRA-C2012-Rule-2.2_b */
UNUSED(node_info);
return HAL_OK;
}
/**
* @brief Convert a linked-list queue to dynamic (Optimized DMA queue execution).
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList)
{
uint32_t cllr_offset;
uint32_t currentnode_addr;
DMA_NodeTypeDef context_node;
DMA_NodeInQInfoTypeDef node_info;
/* Check the queue parameter */
if (pQList == NULL)
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check if queue is dynamic */
if (pQList->Type == QUEUE_TYPE_DYNAMIC)
{
return HAL_OK;
}
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
/* Check queue circularity */
if (pQList->FirstCircularNode != 0U)
{
/* Find the last queue node and get its position in selected queue */
node_info.cllr_offset = cllr_offset;
(void)DMA_List_FindNode(pQList, NULL, &node_info);
}
/* Set current node address */
currentnode_addr = (uint32_t)pQList->Head;
/* Store register value */
DMA_List_FillNode(pQList->Head, &context_node);
/* Convert all nodes to dyncamic (Bypass head node) */
for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++)
{
/* Update node address */
MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA));
/* Bypass the first circular node when first circular node isn't the last queue node */
if (((uint32_t)pQList->FirstCircularNode != 0U) &&
((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr) &&
((uint32_t)pQList->FirstCircularNode == currentnode_addr))
{
/* Copy first circular node to context node */
DMA_List_FillNode(pQList->FirstCircularNode, &context_node);
}
else
{
/* Convert current node to dynamic */
DMA_List_ConvertNodeToDynamic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U));
}
}
/* Check if first circular node is the last node queue */
if (((uint32_t)pQList->FirstCircularNode != 0U) &&
((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr))
{
/* Update all queue nodes CLLR */
DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_ISNOT_CIRCULAR);
}
else
{
/* Update all queue nodes CLLR */
DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_IS_CIRCULAR);
}
/* Set queue type */
pQList->Type = QUEUE_TYPE_DYNAMIC;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
return HAL_OK;
}
/**
* @brief Convert a linked-list queue to static (Not optimized DMA queue execution).
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList)
{
uint32_t cllr_offset;
uint32_t currentnode_addr;
DMA_NodeTypeDef context_node;
/* Check the queue parameter */
if (pQList == NULL)
{
return HAL_ERROR;
}
/* Check the queue */
if (pQList->Head == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY;
return HAL_ERROR;
}
/* Check if queue is static */
if (pQList->Type == QUEUE_TYPE_STATIC)
{
return HAL_OK;
}
/* Set current node address */
currentnode_addr = (uint32_t)pQList->Head;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_BUSY;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Get CLLR register mask and offset */
DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset);
/* Set all CLLR queue nodes to their default positions */
DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_POSITION);
/* Convert all nodes to static (Bypass head node) */
for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++)
{
/* Update context node register values */
DMA_List_FillNode((DMA_NodeTypeDef *)currentnode_addr, &context_node);
/* Update node address */
MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA));
/* Convert current node to static */
DMA_List_ConvertNodeToStatic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U));
}
/* Set all CLLR queue nodes to their default values */
DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_VALUE);
/* Set queue type */
pQList->Type = QUEUE_TYPE_STATIC;
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Update the queue state */
pQList->State = HAL_DMA_QUEUE_STATE_READY;
return HAL_OK;
}
/**
* @brief Link linked-list queue to a DMA channel.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma,
DMA_QListTypeDef *const pQList)
{
HAL_DMA_StateTypeDef state;
/* Check the DMA channel handle and the queue parameters */
if ((hdma == NULL) || (pQList == NULL))
{
return HAL_ERROR;
}
/* Get DMA state */
state = hdma->State;
/* Check DMA channel state */
if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND))
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
/* Check queue state */
if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY;
return HAL_ERROR;
}
/* Check linearity compatibility */
if ((IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) == 0U) &&
((pQList->Head->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR))
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_UNSUPPORTED;
return HAL_ERROR;
}
/* Check circularity compatibility */
if (hdma->Mode == DMA_LINKEDLIST_CIRCULAR)
{
/* Check first circular node */
if (pQList->FirstCircularNode == NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
}
else
{
/* Check first circular node */
if (pQList->FirstCircularNode != NULL)
{
/* Update the queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE;
return HAL_ERROR;
}
}
/* Register queue to DMA handle */
hdma->LinkedListQueue = pQList;
return HAL_OK;
}
/**
* @brief Unlink linked-list queue from a DMA channel.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma)
{
HAL_DMA_StateTypeDef state;
/* Check the DMA channel parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Get DMA state */
state = hdma->State;
/* Check DMA channel state */
if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND))
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
/* Clear queue information from DMA channel handle */
hdma->LinkedListQueue = NULL;
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup DMAEx_Exported_Functions_Group4
*
@verbatim
======================================================================================================================
############### Data handling, repeated block and trigger configuration functions ###############
======================================================================================================================
[..]
This section provides functions allowing to :
(+) Configure DMA channel data handling.
(+) Configure DMA channel repeated block.
(+) Configure DMA channel trigger.
[..]
(+) The HAL_DMAEx_ConfigDataHandling() function allows to configure DMA channel data handling.
(++) GPDMA data handling : byte-based reordering, packing/unpacking, padding/truncation, sign extension
and left/right alignment.
(++) LPDMA data handling : byte-based padding/truncation, sign extension and left/right alignment.
(+) The HAL_DMAEx_ConfigTrigger() function allows to configure DMA channel HW triggers.
(+) The HAL_DMAEx_ConfigRepeatBlock() function allows to configure DMA channel repeated block.
(++) This feature is available only for channel that supports 2 dimensions addressing capability.
@endverbatim
* @{
*/
/**
* @brief Configure the DMA channel data handling according to the specified parameters in the
* DMA_DataHandlingConfTypeDef.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
* for the specified DMA Channel.
* @param pConfigDataHandling : Pointer to a DMA_DataHandlingConfTypeDef structure that contains the data handling
* configuration.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma,
DMA_DataHandlingConfTypeDef const *const pConfigDataHandling)
{
/* Check the DMA peripheral handle and data handling parameters */
if ((hdma == NULL) || (pConfigDataHandling == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_DATA_ALIGNMENT(pConfigDataHandling->DataAlignment));
assert_param(IS_DMA_DATA_EXCHANGE(pConfigDataHandling->DataExchange));
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM),
(pConfigDataHandling->DataAlignment | pConfigDataHandling->DataExchange));
}
else
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Configure the DMA channel trigger according to the specified parameters in the DMA_TriggerConfTypeDef.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
* the specified DMA Channel.
* @param pConfigTrigger : Pointer to a DMA_TriggerConfTypeDef structure that contains the trigger configuration.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma,
DMA_TriggerConfTypeDef const *const pConfigTrigger)
{
/* Check the DMA peripheral handle and trigger parameters */
if ((hdma == NULL) || (pConfigTrigger == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMA_TRIGGER_POLARITY(pConfigTrigger->TriggerPolarity));
assert_param(IS_DMA_TRIGGER_MODE(pConfigTrigger->TriggerMode));
assert_param(IS_DMA_TRIGGER_SELECTION(pConfigTrigger->TriggerSelection));
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM),
(pConfigTrigger->TriggerPolarity | pConfigTrigger->TriggerMode |
(pConfigTrigger->TriggerSelection << DMA_CTR2_TRIGSEL_Pos)));
}
else
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Configure the DMA channel repeated block according to the specified parameters in the
* DMA_RepeatBlockConfTypeDef.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
* for the specified DMA Channel.
* @param pConfigRepeatBlock : Pointer to a DMA_RepeatBlockConfTypeDef structure that contains the repeated block
* configuration.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock)
{
uint32_t tmpreg1;
uint32_t tmpreg2;
/* Check the DMA peripheral handle and repeated block parameters */
if ((hdma == NULL) || (pConfigRepeatBlock == NULL))
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance));
assert_param(IS_DMA_REPEAT_COUNT(pConfigRepeatBlock->RepeatCount));
assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->SrcAddrOffset));
assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->DestAddrOffset));
assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkSrcAddrOffset));
assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkDestAddrOffset));
/* Check DMA channel state */
if (hdma->State == HAL_DMA_STATE_READY)
{
/* Store repeat block count */
tmpreg1 = ((pConfigRepeatBlock->RepeatCount - 1U) << DMA_CBR1_BRC_Pos);
/* Check the sign of single/burst destination address offset value */
if (pConfigRepeatBlock->DestAddrOffset < 0)
{
/* Store single/burst destination address offset configuration (signed case) */
tmpreg1 |= DMA_CBR1_DDEC;
tmpreg2 = (uint32_t)(- pConfigRepeatBlock->DestAddrOffset);
tmpreg2 = tmpreg2 << DMA_CTR3_DAO_Pos;
}
else
{
/* Store single/burst destination address offset configuration (unsigned case) */
tmpreg2 = ((uint32_t)pConfigRepeatBlock->DestAddrOffset << DMA_CTR3_DAO_Pos);
}
/* Check the sign of single/burst source address offset value */
if (pConfigRepeatBlock->SrcAddrOffset < 0)
{
/* Store single/burst source address offset configuration (signed case) */
tmpreg1 |= DMA_CBR1_SDEC;
tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->SrcAddrOffset);
}
else
{
/* Store single/burst source address offset configuration (unsigned case) */
tmpreg2 |= (uint32_t)pConfigRepeatBlock->SrcAddrOffset;
}
/* Write DMA Channel Transfer Register 3 (CTR3) */
WRITE_REG(hdma->Instance->CTR3, tmpreg2);
/* Check the sign of block destination address offset value */
if (pConfigRepeatBlock->BlkDestAddrOffset < 0)
{
/* Store block destination address offset configuration (signed case) */
tmpreg1 |= DMA_CBR1_BRDDEC;
tmpreg2 = (uint32_t)(- pConfigRepeatBlock->BlkDestAddrOffset);
tmpreg2 = tmpreg2 << DMA_CBR2_BRDAO_Pos;
}
else
{
/* Store block destination address offset configuration (unsigned case) */
tmpreg2 = ((uint32_t)pConfigRepeatBlock->BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos);
}
/* Check the sign of block source address offset value */
if (pConfigRepeatBlock->BlkSrcAddrOffset < 0)
{
/* Store block source address offset configuration (signed case) */
tmpreg1 |= DMA_CBR1_BRSDEC;
tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->BlkSrcAddrOffset);
}
else
{
/* Store block source address offset configuration (unsigned case) */
tmpreg2 |= (uint32_t)pConfigRepeatBlock->BlkSrcAddrOffset;
}
/* Write DMA Channel block register 2 (CBR2) */
WRITE_REG(hdma->Instance->CBR2, tmpreg2);
/* Write DMA Channel block register 1 (CBR1) */
WRITE_REG(hdma->Instance->CBR1, tmpreg1);
}
else
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup DMAEx_Exported_Functions_Group5
*
@verbatim
======================================================================================================================
############### Suspend and resume operation functions ###############
======================================================================================================================
[..]
This section provides functions allowing to :
(+) Suspend any ongoing DMA channel transfer.
(+) Resume any suspended DMA channel transfer.
[..]
(+) The HAL_DMAEx_Suspend() function allows to suspend any ongoing DMA channel transfer in polling mode (Blocking
mode).
(+) The HAL_DMAEx_Suspend_IT() function allows to suspend any ongoing DMA channel transfer in interrupt mode
(Non-blocking mode).
(+) The HAL_DMAEx_Resume() function allows to resume any suspended DMA channel transfer.
@endverbatim
* @{
*/
/**
* @brief Suspend any ongoing DMA channel transfer in polling mode (Blocking mode).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA channel.
* @note After suspending a DMA channel, a check for wait until the DMA channel is effectively suspended is added. If
* a channel is suspended while a data transfer is ongoing, the current data will be transferred and the
* channel will be effectively suspended only after the transfer of this single/burst data is finished.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma)
{
/* Get tick number */
uint32_t tickstart = HAL_GetTick();
/* Check the DMA peripheral handle */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check DMA channel state */
if (hdma->State != HAL_DMA_STATE_BUSY)
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
else
{
/* Suspend the channel */
hdma->Instance->CCR |= DMA_CCR_SUSP;
/* Check if the DMA channel is suspended */
while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U)
{
/* Check for the timeout */
if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
{
/* Update the DMA channel error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
}
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_SUSPEND;
}
return HAL_OK;
}
/**
* @brief Suspend any ongoing DMA channel transfer in polling mode (Non-blocking mode).
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma)
{
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check DMA channel state */
if (hdma->State != HAL_DMA_STATE_BUSY)
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
else
{
/* Suspend the DMA channel and activate suspend interrupt */
hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE);
}
return HAL_OK;
}
/**
* @brief Resume any suspended DMA channel transfer.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma)
{
/* Check the DMA peripheral handle parameter */
if (hdma == NULL)
{
return HAL_ERROR;
}
/* Check DMA channel state */
if (hdma->State != HAL_DMA_STATE_SUSPEND)
{
/* Update the DMA channel error code */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
else
{
/* Resume the DMA channel */
hdma->Instance->CCR &= (~DMA_CCR_SUSP);
/* Clear the suspend flag */
hdma->Instance->CFCR |= DMA_CFCR_SUSPF;
/* Update the DMA channel state */
hdma->State = HAL_DMA_STATE_BUSY;
}
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup DMAEx_Exported_Functions_Group6
*
@verbatim
======================================================================================================================
############### Fifo status function ###############
======================================================================================================================
[..]
This section provides function allowing to get DMA channel FIFO level.
[..]
(+) The HAL_DMAEx_GetFifoLevel() function allows to return the number of available write beats in the FIFO, in
units of the programmed destination data.
(++) This API is available only for DMA channels that supports FIFO.
@endverbatim
* @{
*/
/**
* @brief Get and returns the DMA channel FIFO level.
* @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval Returns the number of available beats in FIFO.
*/
uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma)
{
return ((hdma->Instance->CSR & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos);
}
/**
* @}
*/
/**
* @}
*/
/* Private functions -------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
* @brief DMAEx Private Functions
* @{
*/
/**
* @brief Initialize the DMA handle according to the specified parameters in the DMA_InitTypeDef.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
* specified DMA Channel.
* @retval None.
*/
static void DMA_List_Init(DMA_HandleTypeDef const *const hdma)
{
uint32_t tmpreg;
/* Prepare DMA Channel Control Register (CCR) value */
tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode;
/* Check DMA channel instance */
if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
{
tmpreg |= hdma->InitLinkedList.LinkAllocatedPort;
}
/* Write DMA Channel Control Register (CCR) */
MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
/* Write DMA Channel Control Register (CTR1) */
WRITE_REG(hdma->Instance->CTR1, 0U);
/* Write DMA Channel Control Register (CTR2) */
WRITE_REG(hdma->Instance->CTR2, hdma->InitLinkedList.TransferEventMode);
/* Write DMA Channel Control Register (CBR1) */
WRITE_REG(hdma->Instance->CBR1, 0U);
/* Write DMA Channel Control Register (CSAR) */
WRITE_REG(hdma->Instance->CSAR, 0U);
/* Write DMA Channel Control Register (CDAR) */
WRITE_REG(hdma->Instance->CDAR, 0U);
/* If 2D Addressing is supported by current channel */
if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
{
/* Write DMA Channel Control Register (CTR3) */
WRITE_REG(hdma->Instance->CTR3, 0U);
/* Write DMA Channel Control Register (CBR2) */
WRITE_REG(hdma->Instance->CBR2, 0U);
}
/* Write DMA Channel linked-list address register (CLLR) */
WRITE_REG(hdma->Instance->CLLR, 0U);
}
/**
* @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef.
* @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
* specified DMA linked-list Node.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
* configurations.
* @retval None.
*/
static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
DMA_NodeTypeDef *const pNode)
{
int32_t blockoffset;
/* Update CTR1 register value ***************************************************************************************/
/* Prepare DMA channel transfer register (CTR1) value */
pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc |
pNodeConfig->Init.DestDataWidth |
pNodeConfig->DataHandlingConfig.DataAlignment |
pNodeConfig->Init.SrcInc |
pNodeConfig->Init.SrcDataWidth;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* set source channel security attribute */
if (pNodeConfig->SrcSecure == DMA_CHANNEL_SRC_SEC)
{
pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC;
}
/* set destination channel security attribute */
if (pNodeConfig->DestSecure == DMA_CHANNEL_DEST_SEC)
{
pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC;
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* Add parameters related to DMA configuration */
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA)
{
/* Prepare DMA channel transfer register (CTR1) value */
pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |=
(pNodeConfig->Init.TransferAllocatedPort | pNodeConfig->DataHandlingConfig.DataExchange |
(((pNodeConfig->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) |
(((pNodeConfig->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1));
}
/*********************************************************************************** CTR1 register value is updated */
/* Update CTR2 register value ***************************************************************************************/
/* Prepare DMA channel transfer register 2 (CTR2) value */
pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] = pNodeConfig->Init.TransferEventMode |
(pNodeConfig->Init.Request & (DMA_CTR2_REQSEL | DMA_CTR2_SWREQ));
/* Check for memory to peripheral transfer */
if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Check for GPDMA */
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA)
{
pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_DREQ;
}
}
/* Memory to memory transfer */
else if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_MEMORY)
{
pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_SWREQ;
}
else
{
/* Prevent MISRA-C2012-Rule-15.7 */
}
/* Check if trigger feature is active */
if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED)
{
/* Prepare DMA channel transfer register 2 (CTR2) value */
pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |=
pNodeConfig->TriggerConfig.TriggerMode | pNodeConfig->TriggerConfig.TriggerPolarity |
((pNodeConfig->TriggerConfig.TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL);
}
/*********************************************************************************** CTR2 register value is updated */
/* Update CBR1 register value ***************************************************************************************/
/* Prepare DMA channel block register 1 (CBR1) value */
pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (pNodeConfig->DataSize & DMA_CBR1_BNDT);
/* If 2D addressing is supported by the selected DMA channel */
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
{
/* Set the new CBR1 Register value */
pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |=
(((pNodeConfig->RepeatBlockConfig.RepeatCount - 1U) << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC);
/* If the source address offset is negative, set SDEC bit */
if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0)
{
pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_SDEC;
}
else
{
pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_SDEC);
}
/* If the destination address offset is negative, set DDEC bit */
if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0)
{
pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_DDEC;
}
else
{
pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_DDEC);
}
/* If the repeated block source address offset is negative, set BRSEC bit */
if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0)
{
pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRSDEC;
}
else
{
pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRSDEC);
}
/* if the repeated block destination address offset is negative, set BRDEC bit */
if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0)
{
pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRDDEC;
}
else
{
pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRDDEC);
}
}
/*********************************************************************************** CBR1 register value is updated */
/* Update CSAR register value ***************************************************************************************/
pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = pNodeConfig->SrcAddress;
/*********************************************************************************** CSAR register value is updated */
/* Update CDAR register value ***************************************************************************************/
pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress;
/*********************************************************************************** CDAR register value is updated */
/* Check if the selected channel is 2D addressing */
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
{
/* Update CTR3 register value *************************************************************************************/
/* Write new CTR3 Register value : source address offset */
if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0)
{
blockoffset = (- pNodeConfig->RepeatBlockConfig.SrcAddrOffset);
pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO);
}
else
{
pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] =
((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO);
}
/* Write new CTR3 Register value : destination address offset */
if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0)
{
blockoffset = (- pNodeConfig->RepeatBlockConfig.DestAddrOffset);
pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= (((uint32_t)blockoffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO);
}
else
{
pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |=
(((uint32_t)pNodeConfig->RepeatBlockConfig.DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO);
}
/********************************************************************************* CTR3 register value is updated */
/* Update CBR2 register value *************************************************************************************/
/* Write new CBR2 Register value : repeated block source address offset */
if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0)
{
blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset);
pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CBR2_BRSAO);
}
else
{
pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] =
((uint32_t)pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset & DMA_CBR2_BRSAO);
}
/* Write new CBR2 Register value : repeated block destination address offset */
if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0)
{
blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset);
pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |=
(((uint32_t)blockoffset & DMA_CBR2_BRSAO) << DMA_CBR2_BRDAO_Pos);
}
else
{
pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |=
(((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO);
}
/********************************************************************************* CBR2 register value is updated */
}
/* Update node information value ************************************************************************************/
/* Set node information */
pNode->NodeInfo = pNodeConfig->NodeType;
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
{
pNode->NodeInfo |= (NODE_CLLR_2D_DEFAULT_OFFSET << NODE_CLLR_IDX_POS);
}
else
{
pNode->NodeInfo |= (NODE_CLLR_LINEAR_DEFAULT_OFFSET << NODE_CLLR_IDX_POS);
}
/******************************************************************************** Node information value is updated */
}
/**
* @brief Get a DMA channel node configuration.
* @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the
* specified DMA linked-list Node.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
* configurations.
* @retval None.
*/
static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
DMA_NodeTypeDef const *const pNode)
{
uint16_t offset;
/* Get node information *********************************************************************************************/
pNodeConfig->NodeType = (pNode->NodeInfo & NODE_TYPE_MASK);
/*************************************************************************************** Node type value is updated */
/* Get CTR1 fields values *******************************************************************************************/
pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SINC;
pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DINC;
pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2;
pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &
DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U;
pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &
DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U;
pNodeConfig->Init.TransferAllocatedPort = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &
(DMA_CTR1_SAP | DMA_CTR1_DAP);
pNodeConfig->DataHandlingConfig.DataExchange = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &
(DMA_CTR1_SBX | DMA_CTR1_DBX | DMA_CTR1_DHX);
pNodeConfig->DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U)
{
pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_SEC;
}
else
{
pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_NSEC;
}
if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DSEC) != 0U)
{
pNodeConfig->DestSecure = DMA_CHANNEL_DEST_SEC;
}
else
{
pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC;
}
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/*********************************************************************************** CTR1 fields values are updated */
/* Get CTR2 fields values *******************************************************************************************/
if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_SWREQ) != 0U)
{
pNodeConfig->Init.Request = DMA_REQUEST_SW;
pNodeConfig->Init.Direction = DMA_MEMORY_TO_MEMORY;
}
else
{
pNodeConfig->Init.Request = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_REQSEL;
if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_DREQ) != 0U)
{
pNodeConfig->Init.Direction = DMA_MEMORY_TO_PERIPH;
}
else
{
pNodeConfig->Init.Direction = DMA_PERIPH_TO_MEMORY;
}
}
pNodeConfig->Init.BlkHWRequest = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_BREQ);
pNodeConfig->TriggerConfig.TriggerMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGM;
pNodeConfig->TriggerConfig.TriggerPolarity = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGPOL;
pNodeConfig->TriggerConfig.TriggerSelection = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] &
DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos;
pNodeConfig->Init.TransferEventMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TCEM;
/*********************************************************************************** CTR2 fields values are updated */
/* Get CBR1 fields **************************************************************************************************/
pNodeConfig->DataSize = pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BNDT;
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
{
pNodeConfig->RepeatBlockConfig.RepeatCount =
((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos) + 1U;
}
else
{
pNodeConfig->RepeatBlockConfig.RepeatCount = 1U;
}
/*********************************************************************************** CBR1 fields values are updated */
/* Get CSAR field ***************************************************************************************************/
pNodeConfig->SrcAddress = pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET];
/************************************************************************************** CSAR field value is updated */
/* Get CDAR field ***************************************************************************************************/
pNodeConfig->DstAddress = pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET];
/************************************************************************************** CDAR field value is updated */
/* Check if the selected channel is 2D addressing */
if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
{
/* Get CTR3 field *************************************************************************************************/
offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO);
pNodeConfig->RepeatBlockConfig.SrcAddrOffset = (int32_t)offset;
offset = (uint16_t)((pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos);
pNodeConfig->RepeatBlockConfig.DestAddrOffset = (int32_t)offset;
if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_SDEC) != 0U)
{
pNodeConfig->RepeatBlockConfig.SrcAddrOffset *= (-1);
}
if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_DDEC) != 0U)
{
pNodeConfig->RepeatBlockConfig.DestAddrOffset *= (-1);
}
/************************************************************************************ CTR3 field value is updated */
/* Get CBR2 fields ************************************************************************************************/
offset = (uint16_t)(pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRSAO);
pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = (int32_t)offset;
offset = (uint16_t)((pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos);
pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = (int32_t)offset;
if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRSDEC) != 0U)
{
pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset *= (-1);
}
if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRDDEC) != 0U)
{
pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset *= (-1);
}
/************************************************************************************ CBR2 field value is updated */
}
else
{
/* Get CTR3 field *************************************************************************************************/
pNodeConfig->RepeatBlockConfig.SrcAddrOffset = 0;
pNodeConfig->RepeatBlockConfig.DestAddrOffset = 0;
/************************************************************************************ CTR3 field value is updated */
/* Get CBR2 fields ************************************************************************************************/
pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = 0;
pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = 0;
/************************************************************************************ CBR2 field value is updated */
}
}
/**
* @brief Check nodes base addresses compatibility.
* @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations.
* @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations.
* @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations.
* @retval Return 0 when nodes addresses are compatible, 1 otherwise.
*/
static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1,
DMA_NodeTypeDef const *const pNode2,
DMA_NodeTypeDef const *const pNode3)
{
uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA);
uint32_t ref = 0U;
/* Check node 1 address */
if ((uint32_t)pNode1 != 0U)
{
ref = (uint32_t)pNode1;
}
/* Check node 2 address */
else if ((uint32_t)pNode2 != 0U)
{
ref = (uint32_t)pNode2;
}
/* Check node 3 address */
else if ((uint32_t)pNode3 != 0U)
{
ref = (uint32_t)pNode3;
}
else
{
/* Prevent MISRA-C2012-Rule-15.7 */
}
/* Check addresses compatibility */
if (temp != ((uint32_t)ref & DMA_CLBAR_LBA))
{
return 1U;
}
return 0U;
}
/**
* @brief Check nodes types compatibility.
* @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations.
* @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations.
* @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations.
* @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible.
*/
static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1,
DMA_NodeTypeDef const *const pNode2,
DMA_NodeTypeDef const *const pNode3)
{
uint32_t ref = 0U;
/* Check node 1 parameter */
if (pNode1 != NULL)
{
ref = pNode1->NodeInfo & NODE_TYPE_MASK;
}
/* Check node 2 parameter */
else if (pNode2 != NULL)
{
ref = pNode2->NodeInfo & NODE_TYPE_MASK;
}
/* Check node 3 parameter */
else if (pNode3 != NULL)
{
ref = pNode3->NodeInfo & NODE_TYPE_MASK;
}
else
{
/* Prevent MISRA-C2012-Rule-15.7 */
}
/* Check node 2 parameter */
if (pNode2 != NULL)
{
/* Check node type compatibility */
if (ref != (pNode2->NodeInfo & NODE_TYPE_MASK))
{
return 2U;
}
}
/* Check node 3 parameter */
if (pNode3 != NULL)
{
/* Check node type compatibility */
if (ref != (pNode3->NodeInfo & NODE_TYPE_MASK))
{
return 3U;
}
}
return 0U;
}
/**
* @brief Check nodes types compatibility.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
* configurations.
* @param cllr_mask : Pointer to CLLR register mask value.
* @param cllr_offset : Pointer to CLLR register offset value.
* @retval None.
*/
static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode,
uint32_t *const cllr_mask,
uint32_t *const cllr_offset)
{
/* Check node type */
if ((pNode->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)
{
/* Update CLLR register mask value */
if (cllr_mask != NULL)
{
*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 |
DMA_CLLR_UB2 | DMA_CLLR_ULL;
}
/* Update CLLR register offset */
if (cllr_offset != NULL)
{
*cllr_offset = NODE_CLLR_2D_DEFAULT_OFFSET;
}
}
/* Update CLLR and register number for linear addressing node */
else
{
/* Update CLLR register mask value */
if (cllr_mask != NULL)
{
*cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL;
}
/* Update CLLR register offset */
if (cllr_offset != NULL)
{
*cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET;
}
}
}
/**
* @brief Find node in queue.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers configurations.
* @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information.
* @retval Return 0 when node is found in selected queue, otherwise node is not found.
*/
static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList,
DMA_NodeTypeDef const *const pNode,
DMA_NodeInQInfoTypeDef *const NodeInfo)
{
uint32_t node_idx = 0U;
uint32_t currentnode_address = 0U;
uint32_t previousnode_address = 0U;
uint32_t cllr_offset = NodeInfo->cllr_offset;
/* Find last node in queue */
if (pNode == NULL)
{
/* Check that previous node is linked to the selected queue */
while (node_idx < pQList->NodeNumber)
{
/* Get head node address */
if (node_idx == 0U)
{
currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA;
}
/* Calculate nodes addresses */
else
{
previousnode_address = currentnode_address;
currentnode_address =
((DMA_NodeTypeDef *)(currentnode_address +
((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
}
/* Increment node index */
node_idx++;
}
}
/* Find selected node node in queue */
else
{
/* Check that previous node is linked to the selected queue */
while ((node_idx < pQList->NodeNumber) && (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA)))
{
/* Get head node address */
if (node_idx == 0U)
{
currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA;
}
/* Calculate nodes addresses */
else
{
previousnode_address = currentnode_address;
currentnode_address =
((DMA_NodeTypeDef *)(currentnode_address +
((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
}
/* Increment node index */
node_idx++;
}
}
/* Check stored address */
if (pNode != NULL)
{
if (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA))
{
return 1U;
}
}
/* Update current node position */
NodeInfo->currentnode_pos = node_idx;
/* Update previous node address */
NodeInfo->previousnode_addr = previousnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
/* Update current node address */
NodeInfo->currentnode_addr = currentnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
/* Update next node address */
if (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] != 0U)
{
NodeInfo->nextnode_addr = (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] &
DMA_CLLR_LA) | ((uint32_t)pQList->Head & DMA_CLBAR_LBA);
}
return 0U;
}
/**
* @brief Reset queue nodes.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information.
* @retval None.
*/
static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList,
DMA_NodeInQInfoTypeDef const *const NodeInfo)
{
uint32_t node_idx = 0U;
uint32_t currentnode_address = 0U;
uint32_t previousnode_address;
uint32_t cllr_offset = NodeInfo->cllr_offset;
/* Check that previous node is linked to the selected queue */
while (node_idx < pQList->NodeNumber)
{
/* Get head node address */
if (node_idx == 0U)
{
previousnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA;
currentnode_address = (pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA);
}
/* Calculate nodes addresses */
else
{
previousnode_address = currentnode_address;
currentnode_address =
((DMA_NodeTypeDef *)(currentnode_address +
((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA;
}
/* Reset node */
((DMA_NodeTypeDef *)(previousnode_address +
((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] = 0U;
/* Increment node index */
node_idx++;
}
}
/**
* @brief Fill source node registers values by destination nodes registers values.
* @param pSrcNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list source node registers
* configurations.
* @param pDestNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list destination node registers
* configurations.
* @retval None.
*/
static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode,
DMA_NodeTypeDef *const pDestNode)
{
/* Repeat for all register nodes */
for (uint32_t reg_idx = 0U; reg_idx < NODE_CLLR_IDX_POS; reg_idx++)
{
pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx];
}
/* Fill node information */
pDestNode->NodeInfo = pSrcNode->NodeInfo;
}
/**
* @brief Convert node to dynamic.
* @param ContextNodeAddr : The context node address.
* @param CurrentNodeAddr : The current node address to be converted.
* @param RegisterNumber : The register number to be converted.
* @retval None.
*/
static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr,
uint32_t CurrentNodeAddr,
uint32_t RegisterNumber)
{
uint32_t currentnode_reg_counter = 0U;
uint32_t contextnode_reg_counter = 0U;
uint32_t cllr_idx = RegisterNumber - 1U;
DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr;
DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr;
uint32_t update_link[NODE_CLLR_IDX_POS] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA,
DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL
};
/* Update ULL position according to register number */
update_link[cllr_idx] = update_link[NODE_CLLR_IDX_POS - 1U];
/* Repeat for all node registers */
while (contextnode_reg_counter != RegisterNumber)
{
/* Check if register values are equal (exception for CSAR, CDAR and CLLR registers) */
if ((context_node->LinkRegisters[contextnode_reg_counter] ==
current_node->LinkRegisters[currentnode_reg_counter]) &&
(contextnode_reg_counter != NODE_CSAR_DEFAULT_OFFSET) &&
(contextnode_reg_counter != NODE_CDAR_DEFAULT_OFFSET) &&
(contextnode_reg_counter != (RegisterNumber - 1U)))
{
/* Format the node according to unused registers */
DMA_List_FormatNode(current_node, currentnode_reg_counter, RegisterNumber, NODE_DYNAMIC_FORMAT);
/* Update CLLR index */
cllr_idx --;
/* Update CLLR fields */
current_node->LinkRegisters[cllr_idx] &= ~update_link[contextnode_reg_counter];
}
else
{
/* Update context node register fields with new values */
context_node->LinkRegisters[contextnode_reg_counter] = current_node->LinkRegisters[currentnode_reg_counter];
/* Update CLLR fields */
current_node->LinkRegisters[cllr_idx] |= update_link[contextnode_reg_counter];
/* Increment current node number register counter */
currentnode_reg_counter++;
}
/* Increment context node number register counter */
contextnode_reg_counter++;
}
/* Update node information */
MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((currentnode_reg_counter - 1U) << NODE_CLLR_IDX_POS));
/* Clear unused node fields */
DMA_List_ClearUnusedFields(current_node, currentnode_reg_counter);
}
/**
* @brief Convert node to static.
* @param ContextNodeAddr : The context node address.
* @param CurrentNodeAddr : The current node address to be converted.
* @param RegisterNumber : The register number to be converted.
* @retval None.
*/
static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr,
uint32_t CurrentNodeAddr,
uint32_t RegisterNumber)
{
uint32_t contextnode_reg_counter = 0U;
uint32_t cllr_idx;
uint32_t cllr_mask;
DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr;
DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr;
uint32_t update_link[NODE_CLLR_IDX_POS] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA,
DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL
};
/* Update ULL position according to register number */
update_link[RegisterNumber - 1U] = update_link[NODE_CLLR_IDX_POS - 1U];
/* Get context node CLLR information */
cllr_idx = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
cllr_mask = context_node->LinkRegisters[cllr_idx];
/* Repeat for all node registers */
while (contextnode_reg_counter != RegisterNumber)
{
/* Check if node field is dynamic */
if ((cllr_mask & update_link[contextnode_reg_counter]) == 0U)
{
/* Format the node according to unused registers */
DMA_List_FormatNode(current_node, contextnode_reg_counter, RegisterNumber, NODE_STATIC_FORMAT);
/* Update node field */
current_node->LinkRegisters[contextnode_reg_counter] = context_node->LinkRegisters[contextnode_reg_counter];
}
/* Increment context node number register counter */
contextnode_reg_counter++;
}
/* Update node information */
MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((RegisterNumber - 1U) << NODE_CLLR_IDX_POS));
}
/**
* @brief Format the node according to unused registers.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
* configurations.
* @param RegisterIdx : The first register index to be formatted.
* @param RegisterNumber : The number of node registers.
* @param Format : The format type.
* @retval None.
*/
static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode,
uint32_t RegisterIdx,
uint32_t RegisterNumber,
uint32_t Format)
{
if (Format == NODE_DYNAMIC_FORMAT)
{
/* Repeat for all registers to be formatted */
for (uint32_t reg_idx = RegisterIdx; reg_idx < (RegisterNumber - 1U); reg_idx++)
{
pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx + 1U];
}
}
else
{
/* Repeat for all registers to be formatted */
for (uint32_t reg_idx = (RegisterNumber - 2U); reg_idx > RegisterIdx; reg_idx--)
{
pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx - 1U];
}
}
}
/**
* @brief Clear unused register fields.
* @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers
* configurations.
* @param FirstUnusedField : The first unused field to be cleared.
* @retval None.
*/
static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode,
uint32_t FirstUnusedField)
{
/* Repeat for all unused fields */
for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_CLLR_IDX_POS; reg_idx++)
{
pNode->LinkRegisters[reg_idx] = 0U;
}
}
/**
* @brief Update CLLR for all dynamic queue nodes.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param LastNode_IsCircular : The first circular node is the last queue node or not.
* @retval None.
*/
static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
uint32_t LastNode_IsCircular)
{
uint32_t previous_cllr_offset;
uint32_t current_cllr_offset = 0U;
uint32_t previousnode_addr;
uint32_t currentnode_addr = (uint32_t)pQList->Head;
uint32_t cllr_mask;
uint32_t node_idx = 0U;
/* Repeat for all register nodes */
while (node_idx < pQList->NodeNumber)
{
/* Get head node address */
if (node_idx == 0U)
{
/* Get current node information */
current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
}
/* Calculate nodes addresses */
else
{
/* Get previous node information */
previousnode_addr = currentnode_addr;
previous_cllr_offset = current_cllr_offset;
/* Get current node information */
currentnode_addr = (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA) +
((uint32_t)pQList->Head & DMA_CLBAR_LBA);
current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
/* Calculate CLLR register value to be updated */
cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & ~DMA_CLLR_LA) |
(((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA);
/* Set new CLLR value to previous node */
((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] = cllr_mask;
}
/* Increment node index */
node_idx++;
}
/* Check queue circularity */
if (pQList->FirstCircularNode != 0U)
{
/* First circular queue is not last queue node */
if (LastNode_IsCircular == 0U)
{
/* Get CLLR node information */
DMA_List_GetCLLRNodeInfo(((DMA_NodeTypeDef *)currentnode_addr), &cllr_mask, NULL);
/* Update CLLR register for last circular node */
((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] =
((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask;
}
/* First circular queue is last queue node */
else
{
/* Disable CLLR updating */
((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL;
}
}
else
{
/* Clear CLLR register for last node */
((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = 0U;
}
}
/**
* @brief Update CLLR for all static queue nodes.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @param operation : The operation type.
* @retval None.
*/
static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList,
uint32_t operation)
{
uint32_t currentnode_addr = (uint32_t)pQList->Head;
uint32_t current_cllr_offset = ((uint32_t)pQList->Head->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
uint32_t cllr_default_offset;
uint32_t cllr_default_mask;
uint32_t cllr_mask;
uint32_t node_idx = 0U;
/* Get CLLR node information */
DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_default_mask, &cllr_default_offset);
/* Repeat for all register nodes (Bypass last queue node) */
while (node_idx < pQList->NodeNumber)
{
if (operation == UPDATE_CLLR_POSITION)
{
/* Get CLLR value */
cllr_mask = ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset];
}
else
{
/* Calculate CLLR value */
cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & DMA_CLLR_LA) |
cllr_default_mask;
}
/* Set new CLLR value to default position */
if ((node_idx == (pQList->NodeNumber - 1U)) && (pQList->FirstCircularNode == NULL))
{
((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = 0U;
}
else
{
((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = cllr_mask;
}
/* Update current node address with next node address */
currentnode_addr = (currentnode_addr & DMA_CLBAR_LBA) | (cllr_mask & DMA_CLLR_LA);
/* Update current CLLR offset with next CLLR offset */
current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS;
/* Increment node index */
node_idx++;
}
}
/**
* @brief Clean linked-list queue variable.
* @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information.
* @retval None.
*/
static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList)
{
/* Clear head node */
pQList->Head = NULL;
/* Clear first circular queue node */
pQList->FirstCircularNode = NULL;
/* Reset node number */
pQList->NodeNumber = 0U;
/* Reset queue state */
pQList->State = HAL_DMA_QUEUE_STATE_RESET;
/* Reset queue error code */
pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE;
/* Reset queue type */
pQList->Type = QUEUE_TYPE_STATIC;
}
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c
|
C
|
apache-2.0
| 172,500
|
/**
******************************************************************************
* @file stm32u5xx_hal_dsi.c
* @author MCD Application Team
* @brief DSI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DSI peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The DSI HAL driver can be used as follows:
(#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi;
(#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API:
(##) Enable the DSI interface clock
(##) NVIC configuration if you need to use interrupt process
(+++) Configure the DSI interrupt priority
(+++) Enable the NVIC DSI IRQ Channel
(#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and
TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit().
*** Configuration ***
=========================
[..]
(#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted
command mode.
(#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host.
(#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode.
(#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer().
(#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop().
Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively
to write DSI short packets, long packets and to read DSI packets.
(#) The DSI Host Offers two Low power modes :
(++) Low Power Mode on data lanes only: Only DSI data lanes are shut down.
It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData()
and HAL_DSI_ExitULPMData()
(++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes.
It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM()
and HAL_DSI_ExitULPM()
(#) To control DSI state you can use the following function: HAL_DSI_GetState()
*** Error management ***
========================
[..]
(#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor()
When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve
the error code by calling function HAL_DSI_GetError()
*** DSI HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DSI HAL driver.
(+) __HAL_DSI_ENABLE: Enable the DSI Host.
(+) __HAL_DSI_DISABLE: Disable the DSI Host.
(+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper.
(+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper.
(+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL.
(+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL.
(+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator.
(+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator.
(+) __HAL_DSI_GET_FLAG: Get the DSI pending flags.
(+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags.
(+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts.
(+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts.
(+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not.
[..]
(@) You can refer to the DSI HAL driver header file for more useful macros
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function HAL_DSI_RegisterCallback() to register a callback.
[..]
Function HAL_DSI_RegisterCallback() allows to register following callbacks:
(+) TearingEffectCallback : DSI Tearing Effect Callback.
(+) EndOfRefreshCallback : DSI End Of Refresh Callback.
(+) ErrorCallback : DSI Error Callback
(+) MspInitCallback : DSI MspInit.
(+) MspDeInitCallback : DSI MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
[..]
Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default
weak function.
HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
This function allows to reset following callbacks:
(+) TearingEffectCallback : DSI Tearing Effect Callback.
(+) EndOfRefreshCallback : DSI End Of Refresh Callback.
(+) ErrorCallback : DSI Error Callback
(+) MspInitCallback : DSI MspInit.
(+) MspDeInitCallback : DSI MspDeInit.
[..]
By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit()
or HAL_DSI_Init() function.
[..]
When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_DSI_MODULE_ENABLED
#if defined(DSI)
/** @addtogroup DSI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @addtogroup DSI_Private_Constants
* @{
*/
#define DSI_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */
#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
#define DSI_ERROR_PBU_MASK DSI_ISR1_PBUE
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0,
uint32_t Data1);
static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
uint32_t ChannelID,
uint32_t Mode,
uint32_t Param1,
uint32_t Param2);
static void DSI_ConfigBandControl(DSI_HandleTypeDef *hdsi);
static void DSI_SetWrapperPLLTuning(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
/* Private functions ---------------------------------------------------------*/
/** @defgroup DSI_Private_Functions DSI Private Functions
* @{
*/
/**
* @brief Generic DSI packet header configuration
* @param DSIx Pointer to DSI register base
* @param ChannelID Virtual channel ID of the header packet
* @param DataType Packet data type of the header packet
* This parameter can be any value of :
* @arg DSI_SHORT_WRITE_PKT_Data_Type
* @arg DSI_LONG_WRITE_PKT_Data_Type
* @arg DSI_SHORT_READ_PKT_Data_Type
* @arg DSI_MAX_RETURN_PKT_SIZE
* @param Data0 Word count LSB
* @param Data1 Word count MSB
* @retval None
*/
static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
uint32_t ChannelID,
uint32_t DataType,
uint32_t Data0,
uint32_t Data1)
{
/* Update the DSI packet header with new information */
DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U));
}
/**
* @brief write short DCS or short Generic command
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param ChannelID Virtual channel ID.
* @param Mode DSI short packet data type.
* This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
* @param Param1 DSC command or first generic parameter.
* This parameter can be any value of @arg DSI_DCS_Command or a
* generic command code.
* @param Param2 DSC parameter or second generic parameter.
* @retval HAL status
*/
static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
uint32_t ChannelID,
uint32_t Mode,
uint32_t Param1,
uint32_t Param2)
{
uint32_t tickstart;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for Command FIFO Empty */
while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Configure the packet to send a short DCS command with 0 or 1 parameter */
/* Update the DSI packet header with new information */
hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U));
return HAL_OK;
}
/**
* @brief Configure Band Control Frequency and LPX Offset
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
static void DSI_ConfigBandControl(DSI_HandleTypeDef *hdsi)
{
/* Set Band Control Frequency for clock lane */
hdsi->Instance->DPCBCR &= ~DSI_DPCBCR;
hdsi->Instance->DPCBCR |= (hdsi->Init.PHYFrequencyRange << DSI_DPCBCR_Pos);
/* Set the slew rate for clock lane */
hdsi->Instance->DPCSRCR = DSI_DPHY_SLEW_HS_TX_SPEED;
/* Set Band Control Frequency for Data Lane0 */
hdsi->Instance->DPDL0BCR &= ~DSI_DPDL0BCR;
hdsi->Instance->DPDL0BCR = (hdsi->Init.PHYFrequencyRange << DSI_DPDL0BCR_Pos);
/* Set the slew rate for data Lane0 */
hdsi->Instance->DPDL0SRCR = DSI_DPHY_SLEW_HS_TX_SPEED;
/* Set Band Control Frequency for Data Lane1 */
hdsi->Instance->DPDL1BCR &= ~DSI_DPDL1BCR;
hdsi->Instance->DPDL1BCR = (hdsi->Init.PHYFrequencyRange << DSI_DPDL1BCR_Pos);
/* Set Slew rate for data Lane1 */
hdsi->Instance->DPDL1SRCR = DSI_DPHY_SLEW_HS_TX_SPEED;
/* Set HS prepare offset for data lanes */
hdsi->Instance->DPDL0HSOCR &= ~DSI_DPDL0HSOCR;
hdsi->Instance->DPDL1HSOCR &= ~DSI_DPDL1HSOCR;
if ((hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_100MHZ_120MHZ) || \
(hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_120MHZ_160MHZ) || \
(hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_240MHZ_320MHZ))
{
hdsi->Instance->DPDL0HSOCR = (DSI_HS_PREPARE_OFFSET0 << DSI_DPDL0HSOCR_Pos);
hdsi->Instance->DPDL1HSOCR = (DSI_HS_PREPARE_OFFSET0 << DSI_DPDL1HSOCR_Pos);
}
else if ((hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_80MHZ_100MHZ) || \
(hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_160MHZ_200MHZ) || \
(hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_200MHZ_240MHZ) || \
(hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_320MHZ_390MHZ))
{
hdsi->Instance->DPDL0HSOCR = (DSI_HS_PREPARE_OFFSET1 << DSI_DPDL0HSOCR_Pos);
hdsi->Instance->DPDL1HSOCR = (DSI_HS_PREPARE_OFFSET1 << DSI_DPDL1HSOCR_Pos);
}
else if ((hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_390MHZ_450MHZ) || \
(hdsi->Init.PHYFrequencyRange == DSI_DPHY_FRANGE_450MHZ_510MHZ))
{
hdsi->Instance->DPDL0HSOCR = (DSI_HS_PREPARE_OFFSET2 << DSI_DPDL0HSOCR_Pos);
hdsi->Instance->DPDL1HSOCR = (DSI_HS_PREPARE_OFFSET2 << DSI_DPDL1HSOCR_Pos);
}
else
{
/* Nothing to do */
}
/* Set LPXO value for data lanes */
hdsi->Instance->DPDL0LPXOCR &= ~DSI_DPDL0LPXOCR;
hdsi->Instance->DPDL1LPXOCR &= ~DSI_DPDL1LPXOCR;
hdsi->Instance->DPDL0LPXOCR = hdsi->Init.PHYLowPowerOffset;
hdsi->Instance->DPDL1LPXOCR = hdsi->Init.PHYLowPowerOffset;
}
/**
* @brief Set Wrapper PLL Tuning and Charge Pump
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains
* the PLL Clock structure definition for the DSI.
* @retval HAL status
*/
static void DSI_SetWrapperPLLTuning(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
{
/* Set the VCO Frequency */
hdsi->Instance->WRPCR &= ~(DSI_WRPCR_BC);
hdsi->Instance->WRPCR |= (PLLInit->PLLVCORange << DSI_WRPCR_BC_Pos);
hdsi->Instance->WPTR &= ~(DSI_WPTR_LPF | DSI_WPTR_CP);
/* Set PLL Tuning */
hdsi->Instance->WPTR |= (PLLInit->PLLTuning << DSI_WPTR_LPF_Pos);
/* Set PLL_Charge Value */
hdsi->Instance->WPTR |= (PLLInit->PLLChargePump << DSI_WPTR_CP_Pos);
}
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DSI_Exported_Functions
* @{
*/
/** @defgroup DSI_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DSI
(+) De-initialize the DSI
@endverbatim
* @{
*/
/**
* @brief Initializes the DSI according to the specified
* parameters in the DSI_InitTypeDef and create the associated handle.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains
* the PLL Clock structure definition for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
{
uint32_t tickstart;
/* Check the DSI handle allocation */
if (hdsi == NULL)
{
return HAL_ERROR;
}
/* Check function parameters */
assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
assert_param(IS_DSI_DPHY_BAND_CTL_FRANGE(hdsi->Init.PHYFrequencyRange));
assert_param(IS_DSI_DPHY_LOW_POWER_OFFSET(hdsi->Init.PHYLowPowerOffset));
assert_param(IS_DSI_DPHY_VCO_FREQUENCY_RANGE(PLLInit->PLLVCORange));
assert_param(IS_DSI_PLL_TUNING(PLLInit->PLLTuning));
assert_param(IS_DSI_PLL_CHARGEPUMP(PLLInit->PLLChargePump));
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
if (hdsi->State == HAL_DSI_STATE_RESET)
{
/* Reset the DSI callback to the legacy weak callbacks */
hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
if (hdsi->MspInitCallback == NULL)
{
hdsi->MspInitCallback = HAL_DSI_MspInit;
}
/* Initialize the low level hardware */
hdsi->MspInitCallback(hdsi);
}
#else
if (hdsi->State == HAL_DSI_STATE_RESET)
{
/* Initialize the low level hardware */
HAL_DSI_MspInit(hdsi);
}
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Change DSI peripheral state */
hdsi->State = HAL_DSI_STATE_BUSY;
/**************** Turn on the Reference Bias and enable the DSI PLL ****************/
/* bias power up */
hdsi->Instance->BCFGR |= DSI_BCFGR_PWRUP;
/* Requires min of 2ms delay, 2ms delay is inserted */
HAL_Delay(2);
/* Set the PLL division factors */
hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \
((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \
((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos));
/************************ Set D-PHY Band Control registers ******************************/
/* Set Band Control Frequency and LPX Offset */
DSI_ConfigBandControl(hdsi);
/* Set PLL Tuning */
DSI_SetWrapperPLLTuning(hdsi, PLLInit);
/* Enable the DSI PLL */
__HAL_DSI_PLL_ENABLE(hdsi);
/* Requires min of 400us delay before reading the PLLLS flag */
/* 1ms delay is inserted that is the minimum HAL delay granularity */
HAL_Delay(1);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for the lock of the PLL */
while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/*************************** Set the PHY parameters ***************************/
/* D-PHY clock and digital enable*/
hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
/* Clock lane configuration */
hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
/* Configure the number of active data lanes */
hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
/************************ Set the DSI clock parameters ************************/
/* Set the TX escape clock division factor */
hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
/****************************** Error management *****************************/
/* Disable all error interrupts and reset the Error Mask */
hdsi->Instance->IER[0U] = 0U;
hdsi->Instance->IER[1U] = 0U;
hdsi->ErrorMsk = 0U;
/* Initialize the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
/* Initialize the DSI state*/
hdsi->State = HAL_DSI_STATE_READY;
return HAL_OK;
}
/**
* @brief De-initializes the DSI peripheral registers to their default reset
* values.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
{
/* Check the DSI handle allocation */
if (hdsi == NULL)
{
return HAL_ERROR;
}
/* Change DSI peripheral state */
hdsi->State = HAL_DSI_STATE_BUSY;
/* Disable the DSI wrapper */
__HAL_DSI_WRAPPER_DISABLE(hdsi);
/* Disable the DSI host */
__HAL_DSI_DISABLE(hdsi);
/* D-PHY clock and digital disable */
hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
/* Turn off the DSI PLL */
__HAL_DSI_PLL_DISABLE(hdsi);
/* Disable the reference bias */
hdsi->Instance->BCFGR &= ~DSI_BCFGR_PWRUP;
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
if (hdsi->MspDeInitCallback == NULL)
{
hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;
}
/* DeInit the low level hardware */
hdsi->MspDeInitCallback(hdsi);
#else
/* DeInit the low level hardware */
HAL_DSI_MspDeInit(hdsi);
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/* Initialize the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
/* Initialize the DSI state*/
hdsi->State = HAL_DSI_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Enable the error monitor flags
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param ActiveErrors indicates which error interrupts will be enabled.
* This parameter can be any combination of @arg DSI_Error_Data_Type.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
{
/* Process locked */
__HAL_LOCK(hdsi);
hdsi->Instance->IER[0U] = 0U;
hdsi->Instance->IER[1U] = 0U;
/* Store active errors to the handle */
hdsi->ErrorMsk = ActiveErrors;
if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
}
if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
}
if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
}
if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
}
if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
}
if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
}
if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
}
if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
}
if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
}
if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
}
if ((ActiveErrors & HAL_DSI_ERROR_PBU) != 0U)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_PBU_MASK;
}
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Initializes the DSI MSP.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
__weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_MspInit could be implemented in the user file
*/
}
/**
* @brief De-initializes the DSI MSP.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_MspDeInit could be implemented in the user file
*/
}
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DSI Callback
* To be used instead of the weak predefined callback
* @param hdsi dsi handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
* @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
* @arg HAL_DSI_ERROR_CB_ID Error Callback ID
* @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
* @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
pDSI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdsi);
if (hdsi->State == HAL_DSI_STATE_READY)
{
switch (CallbackID)
{
case HAL_DSI_TEARING_EFFECT_CB_ID :
hdsi->TearingEffectCallback = pCallback;
break;
case HAL_DSI_ENDOF_REFRESH_CB_ID :
hdsi->EndOfRefreshCallback = pCallback;
break;
case HAL_DSI_ERROR_CB_ID :
hdsi->ErrorCallback = pCallback;
break;
case HAL_DSI_MSPINIT_CB_ID :
hdsi->MspInitCallback = pCallback;
break;
case HAL_DSI_MSPDEINIT_CB_ID :
hdsi->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hdsi->State == HAL_DSI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DSI_MSPINIT_CB_ID :
hdsi->MspInitCallback = pCallback;
break;
case HAL_DSI_MSPDEINIT_CB_ID :
hdsi->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdsi);
return status;
}
/**
* @brief Unregister a DSI Callback
* DSI callback is redirected to the weak predefined callback
* @param hdsi dsi handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID
* @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID
* @arg HAL_DSI_ERROR_CB_ID Error Callback ID
* @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID
* @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdsi);
if (hdsi->State == HAL_DSI_STATE_READY)
{
switch (CallbackID)
{
case HAL_DSI_TEARING_EFFECT_CB_ID :
hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */
break;
case HAL_DSI_ENDOF_REFRESH_CB_ID :
hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */
break;
case HAL_DSI_ERROR_CB_ID :
hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_DSI_MSPINIT_CB_ID :
hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */
break;
case HAL_DSI_MSPDEINIT_CB_ID :
hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */
break;
default :
/* Update the error code */
hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hdsi->State == HAL_DSI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_DSI_MSPINIT_CB_ID :
hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */
break;
case HAL_DSI_MSPDEINIT_CB_ID :
hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */
break;
default :
/* Update the error code */
hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdsi);
return status;
}
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup DSI_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides function allowing to:
(+) Handle DSI interrupt request
@endverbatim
* @{
*/
/**
* @brief Handles DSI interrupt request.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
{
uint32_t ErrorStatus0;
uint32_t ErrorStatus1;
/* Tearing Effect Interrupt management ***************************************/
if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
{
if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U)
{
/* Clear the Tearing Effect Interrupt Flag */
__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
/* Tearing Effect Callback */
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
/*Call registered Tearing Effect callback */
hdsi->TearingEffectCallback(hdsi);
#else
/*Call legacy Tearing Effect callback*/
HAL_DSI_TearingEffectCallback(hdsi);
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
}
}
/* End of Refresh Interrupt management ***************************************/
if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U)
{
if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U)
{
/* Clear the End of Refresh Interrupt Flag */
__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
/* End of Refresh Callback */
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
/*Call registered End of refresh callback */
hdsi->EndOfRefreshCallback(hdsi);
#else
/*Call Legacy End of refresh callback */
HAL_DSI_EndOfRefreshCallback(hdsi);
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
}
}
/* Error Interrupts management ***********************************************/
if (hdsi->ErrorMsk != 0U)
{
ErrorStatus0 = hdsi->Instance->ISR[0U];
ErrorStatus0 &= hdsi->Instance->IER[0U];
ErrorStatus1 = hdsi->Instance->ISR[1U];
ErrorStatus1 &= hdsi->Instance->IER[1U];
if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
}
if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
}
if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
}
if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
}
if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
}
if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
}
if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
}
if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
}
if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
}
if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
}
if ((ErrorStatus1 & DSI_ERROR_PBU_MASK) != 0U)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_PBU;
}
/* Check only selected errors */
if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
{
/* DSI error interrupt callback */
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
/*Call registered Error callback */
hdsi->ErrorCallback(hdsi);
#else
/*Call Legacy Error callback */
HAL_DSI_ErrorCallback(hdsi);
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
}
}
}
/**
* @brief Tearing Effect DSI callback.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_TearingEffectCallback could be implemented in the user file
*/
}
/**
* @brief End of Refresh DSI callback.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
*/
}
/**
* @brief Operation Error DSI callback.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdsi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_ErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DSI_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the Generic interface read-back Virtual Channel ID
(+) Select video mode and configure the corresponding parameters
(+) Configure command transmission mode: High-speed or Low-power
(+) Configure the flow control
(+) Configure the DSI PHY timer
(+) Configure the DSI HOST timeout
(+) Configure the DSI HOST timeout
(+) Start/Stop the DSI module
(+) Refresh the display in command mode
(+) Controls the display color mode in Video mode
(+) Control the display shutdown in Video mode
(+) write short DCS or short Generic command
(+) write long DCS or long Generic command
(+) Read command (DCS or generic)
(+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
(+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
(+) Start/Stop test pattern generation
(+) Slew-Rate And Delay Tuning
(+) Low-Power Reception Filter Tuning
(+) Activate an additional current path on all lanes to meet the SDDTx parameter
(+) Custom lane pins configuration
(+) Set custom timing for the PHY
(+) Force the Clock/Data Lane in TX Stop Mode
(+) Force LP Receiver in Low-Power Mode
(+) Force Data Lanes in RX Mode after a BTA
(+) Enable a pull-down on the lanes to prevent from floating states when unused
(+) Switch off the contention detection on data lanes
@endverbatim
* @{
*/
/**
* @brief Configure the Generic interface read-back Virtual Channel ID.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param VirtualChannelIdRx Virtual channel ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetGenericVCIDRX(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelIdRx)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Update the GVCID register */
hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCIDRX;
hdsi->Instance->GVCIDR |= VirtualChannelIdRx << DSI_GVCIDR_VCIDRX_Pos;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Configure the Virtual channel ID for transmission.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param VirtualChannelIdTx Virtual channel ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetGenericVCIDTX(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelIdTx)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Update the GVCID register */
hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCIDTX;
hdsi->Instance->GVCIDR |= VirtualChannelIdTx << DSI_GVCIDR_VCIDTX_Pos;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Configure the Generic interface read-back Virtual Channel ID.
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param VirtualChannelID Virtual channel ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Update the GVCIDR register with the Tx and Rx Virtual channel ID */
hdsi->Instance->GVCIDR &= ~(DSI_GVCIDR_VCIDRX | DSI_GVCIDR_VCIDTX);
hdsi->Instance->GVCIDR |= ((VirtualChannelID << DSI_GVCIDR_VCIDRX_Pos) | \
(VirtualChannelID << DSI_GVCIDR_VCIDTX_Pos));
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Select video mode and configure the corresponding parameters
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
* the DSI video mode configuration parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Check the parameters */
assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
/* Check the LooselyPacked variant only in 18-bit mode */
if (VidCfg->ColorCoding == DSI_RGB666)
{
assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
}
/* Select video mode by resetting CMDM and DSIM bits */
hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
/* Configure the video mode transmission type */
hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
hdsi->Instance->VMCR |= VidCfg->Mode;
/* Configure the video packet size */
hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
hdsi->Instance->VPCR |= VidCfg->PacketSize;
/* Set the chunks number to be transmitted through the DSI link */
hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
/* Set the size of the null packet */
hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
/* Select the virtual channel for the LTDC interface traffic */
hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
/* Configure the polarity of control signals */
hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
/* Select the color coding for the host */
hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
/* Select the color coding for the wrapper */
hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U);
/* Enable/disable the loosely packed variant to 18-bit configuration */
if (VidCfg->ColorCoding == DSI_RGB666)
{
hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
}
/* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
/* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
/* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
/* Set the Vertical Synchronization Active (VSA) */
hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
/* Set the Vertical Back Porch (VBP)*/
hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
/* Set the Vertical Front Porch (VFP)*/
hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
/* Set the Vertical Active period*/
hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
hdsi->Instance->VVACR |= VidCfg->VerticalActive;
/* Configure the command transmission mode */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
/* Low power largest packet size */
hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U);
/* Low power VACT largest packet size */
hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
/* Enable LP transition in HFP period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
/* Enable LP transition in HBP period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
/* Enable LP transition in VACT period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
/* Enable LP transition in VFP period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
/* Enable LP transition in VBP period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
/* Enable LP transition in vertical sync period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
/* Enable the request for an acknowledge response at the end of a frame */
hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Select adapted command mode and configure the corresponding parameters
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Check the parameters */
assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
/* Select command mode by setting CMDM and DSIM bits */
hdsi->Instance->MCR |= DSI_MCR_CMDM;
hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
/* Select the virtual channel for the LTDC interface traffic */
hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
/* Configure the polarity of control signals */
hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
/* Select the color coding for the host */
hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
/* Select the color coding for the wrapper */
hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U);
/* Configure the maximum allowed size for write memory command */
hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
hdsi->Instance->LCCR |= CmdCfg->CommandSize;
/* Configure the tearing effect source and polarity and select the refresh mode */
hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh |
CmdCfg->VSyncPol);
/* Configure the tearing effect acknowledge request */
hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
/* Enable the Tearing Effect interrupt */
__HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
/* Enable the End of Refresh interrupt */
__HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Configure command transmission mode: High-speed or Low-power
* and enable/disable acknowledge request after packet transmission
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains
* the DSI command transmission mode configuration parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
{
/* Process locked */
__HAL_LOCK(hdsi);
assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
/* Select High-speed or Low-power for command transmission */
hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \
DSI_CMCR_GSW1TX | \
DSI_CMCR_GSW2TX | \
DSI_CMCR_GSR0TX | \
DSI_CMCR_GSR1TX | \
DSI_CMCR_GSR2TX | \
DSI_CMCR_GLWTX | \
DSI_CMCR_DSW0TX | \
DSI_CMCR_DSW1TX | \
DSI_CMCR_DSR0TX | \
DSI_CMCR_DLWTX | \
DSI_CMCR_MRDPS);
hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP | \
LPCmd->LPGenShortWriteOneP | \
LPCmd->LPGenShortWriteTwoP | \
LPCmd->LPGenShortReadNoP | \
LPCmd->LPGenShortReadOneP | \
LPCmd->LPGenShortReadTwoP | \
LPCmd->LPGenLongWrite | \
LPCmd->LPDcsShortWriteNoP | \
LPCmd->LPDcsShortWriteOneP | \
LPCmd->LPDcsShortReadNoP | \
LPCmd->LPDcsLongWrite | \
LPCmd->LPMaxReadPacket);
/* Configure the acknowledge request after each packet transmission */
hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Configure the flow control parameters
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param FlowControl flow control feature(s) to be enabled.
* This parameter can be any combination of @arg DSI_FlowControl.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Check the parameters */
assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
/* Set the DSI Host Protocol Configuration Register */
hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
hdsi->Instance->PCR |= FlowControl;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Configure the DSI PHY timer parameters
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param PhyTimers DSI_PHY_TimerTypeDef structure that contains
* the DSI PHY timing parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
{
uint32_t maxTime;
/* Process locked */
__HAL_LOCK(hdsi);
/* Insert LPX Offset into the timings */
PhyTimers->ClockLaneHS2LPTime = PhyTimers->ClockLaneHS2LPTime + hdsi->Init.PHYLowPowerOffset;
PhyTimers->ClockLaneLP2HSTime = PhyTimers->ClockLaneLP2HSTime + (3U * hdsi->Init.PHYLowPowerOffset);
PhyTimers->DataLaneLP2HSTime = PhyTimers->DataLaneLP2HSTime + (2U * hdsi->Init.PHYLowPowerOffset);
maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime :
PhyTimers->ClockLaneHS2LPTime;
/* Clock lane timer configuration */
/* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
High-Speed transmission.
To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
to Low-Power and from Low-Power to High-Speed.
This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration
Register (DSI_CLTCR).
But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
*/
hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U));
/* Data lane timer configuration */
hdsi->Instance->DLTCR &= ~(DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
hdsi->Instance->DLTCR |= (PhyTimers->DataLaneLP2HSTime | ((PhyTimers->DataLaneHS2LPTime) << 16U));
hdsi->Instance->DLTRCR &= ~DSI_DLTRCR_MRD_TIME;
hdsi->Instance->DLTRCR |= PhyTimers->DataLaneMaxReadTime;
/* Configure the wait period to request HS transmission after a stop state */
hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Configure the DSI HOST timeout parameters
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains
* the DSI host timeout parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Set the timeout clock division factor */
hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U);
/* High-speed transmission timeout */
hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U);
/* Low-power reception timeout */
hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
/* High-speed read timeout */
hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
/* Low-power read timeout */
hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
/* High-speed write timeout */
hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
/* High-speed write presp mode */
hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
/* Low-speed write timeout */
hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
/* BTA timeout */
hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Start the DSI module
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Enable the DSI host */
__HAL_DSI_ENABLE(hdsi);
/* Enable the DSI wrapper */
__HAL_DSI_WRAPPER_ENABLE(hdsi);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Stop the DSI module
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Disable the DSI host */
__HAL_DSI_DISABLE(hdsi);
/* Disable the DSI wrapper */
__HAL_DSI_WRAPPER_DISABLE(hdsi);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Refresh the display in command mode
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Update the display */
hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Controls the display color mode in Video mode
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param ColorMode Color mode (full or 8-colors).
* This parameter can be any value of @arg DSI_Color_Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Check the parameters */
assert_param(IS_DSI_COLOR_MODE(ColorMode));
/* Update the display color mode */
hdsi->Instance->WCR &= ~DSI_WCR_COLM;
hdsi->Instance->WCR |= ColorMode;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Control the display shutdown in Video mode
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param Shutdown Shut-down (Display-ON or Display-OFF).
* This parameter can be any value of @arg DSI_ShutDown
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Check the parameters */
assert_param(IS_DSI_SHUT_DOWN(Shutdown));
/* Update the display Shutdown */
hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
hdsi->Instance->WCR |= Shutdown;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief write short DCS or short Generic command
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param ChannelID Virtual channel ID.
* @param Mode DSI short packet data type.
* This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type.
* @param Param1 DSC command or first generic parameter.
* This parameter can be any value of @arg DSI_DCS_Command or a
* generic command code.
* @param Param2 DSC parameter or second generic parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
uint32_t ChannelID,
uint32_t Mode,
uint32_t Param1,
uint32_t Param2)
{
HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
/* Process locked */
__HAL_LOCK(hdsi);
status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return status;
}
/**
* @brief write long DCS or long Generic command
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param ChannelID Virtual channel ID.
* @param Mode DSI long packet data type.
* This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type.
* @param NbParams Number of parameters.
* @param Param1 DSC command or first generic parameter.
* This parameter can be any value of @arg DSI_DCS_Command or a
* generic command code
* @param ParametersTable Pointer to parameter values table.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
uint32_t ChannelID,
uint32_t Mode,
uint32_t NbParams,
uint32_t Param1,
uint8_t *ParametersTable)
{
uint32_t uicounter;
uint32_t nbBytes;
uint32_t count;
uint32_t tickstart;
uint32_t fifoword;
uint8_t *pparams = ParametersTable;
/* Process locked */
__HAL_LOCK(hdsi);
/* Check the parameters */
assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for Command FIFO Empty */
while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
/* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
fifoword = Param1;
nbBytes = (NbParams < 3U) ? NbParams : 3U;
for (count = 0U; count < nbBytes; count++)
{
fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count)));
}
hdsi->Instance->GPDR = fifoword;
uicounter = NbParams - nbBytes;
pparams += nbBytes;
/* Set the Next parameters on the write FIFO command*/
while (uicounter != 0U)
{
nbBytes = (uicounter < 4U) ? uicounter : 4U;
fifoword = 0U;
for (count = 0U; count < nbBytes; count++)
{
fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count));
}
hdsi->Instance->GPDR = fifoword;
uicounter -= nbBytes;
pparams += nbBytes;
}
/* Configure the packet to send a long DCS command */
DSI_ConfigPacketHeader(hdsi->Instance,
ChannelID,
Mode,
((NbParams + 1U) & 0x00FFU),
(((NbParams + 1U) & 0xFF00U) >> 8U));
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Read command (DCS or generic)
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param ChannelNbr Virtual channel ID
* @param Array pointer to a buffer to store the payload of a read back operation.
* @param Size Data size to be read (in byte).
* @param Mode DSI read packet data type.
* This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type.
* @param DCSCmd DCS get/read command.
* @param ParametersTable Pointer to parameter values table.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
uint32_t ChannelNbr,
uint8_t *Array,
uint32_t Size,
uint32_t Mode,
uint32_t DCSCmd,
uint8_t *ParametersTable)
{
uint32_t tickstart;
uint8_t *pdata = Array;
uint32_t datasize = Size;
uint32_t fifoword;
uint32_t nbbytes;
uint32_t count;
/* Process locked */
__HAL_LOCK(hdsi);
/* Check the parameters */
assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
if (datasize > 2U)
{
/* set max return packet size */
if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
(((datasize) >> 8U) & 0xFFU)) != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
/* Configure the packet to read command */
if (Mode == DSI_DCS_SHORT_PKT_READ)
{
DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
}
else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
{
DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
}
else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
{
DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
}
else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
{
DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Get tick */
tickstart = HAL_GetTick();
/* If DSI fifo is not empty, read requested bytes */
while (((int32_t)(datasize)) > 0)
{
if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
{
fifoword = hdsi->Instance->GPDR;
nbbytes = (datasize < 4U) ? datasize : 4U;
for (count = 0U; count < nbbytes; count++)
{
*pdata = (uint8_t)(fifoword >> (8U * count));
pdata++;
datasize--;
}
}
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
/* Software workaround to avoid HAL_TIMEOUT when a DSI read command is */
/* issued to the panel and the read data is not captured by the DSI Host */
/* which returns Packet Size Error. */
/* Need to ensure that the Read command has finished before checking PSE */
if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U)
{
if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
* (only data lanes are in ULPM)
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
{
uint32_t tickstart;
/* Process locked */
__HAL_LOCK(hdsi);
/* ULPS Request on Data Lanes */
hdsi->Instance->PUCR |= DSI_PUCR_URDL;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until the D-PHY active lanes enter into ULPM */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
* (only data lanes are in ULPM)
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
{
uint32_t tickstart;
/* Process locked */
__HAL_LOCK(hdsi);
/* Exit ULPS on Data Lanes */
hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until all active lanes exit ULPM */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* wait for 1 ms*/
HAL_Delay(1U);
/* De-assert the ULPM requests and the ULPM exit bits */
hdsi->Instance->PUCR = 0U;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
* (both data and clock lanes are in ULPM)
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
{
uint32_t tickstart;
/* Process locked */
__HAL_LOCK(hdsi);
/* Clock lane configuration: no more HS request */
hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
/* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLL3);
/* ULPS Request on Clock and Data Lanes */
hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until all active lanes exit ULPM */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Turn off the DSI PLL */
__HAL_DSI_PLL_DISABLE(hdsi);
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
* (both data and clock lanes are in ULPM)
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
{
uint32_t tickstart;
/* Process locked */
__HAL_LOCK(hdsi);
/* Turn on the DSI PLL */
__HAL_DSI_PLL_ENABLE(hdsi);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for the lock of the PLL */
while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
/* Exit ULPS on Clock and Data Lanes */
hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until all active lanes exit ULPM */
if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 |
DSI_PSR_UANC))
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
return HAL_TIMEOUT;
}
}
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* wait for 1 ms */
HAL_Delay(1U);
/* De-assert the ULPM requests and the ULPM exit bits */
hdsi->Instance->PUCR = 0U;
/* Switch the lane byte clock source in the RCC from system PLL to D-PHY */
__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
/* Restore clock lane configuration to HS */
hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Start test pattern generation
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param Mode Pattern generator mode
* This parameter can be one of the following values:
* 0 : Color bars (horizontal or vertical)
* 1 : BER pattern (vertical only)
* @param Orientation Pattern generator orientation
* This parameter can be one of the following values:
* 0 : Vertical color bars
* 1 : Horizontal color bars
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Configure pattern generator mode and orientation */
hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U));
/* Enable pattern generator by setting PGE bit */
hdsi->Instance->VMCR |= DSI_VMCR_PGE;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Stop test pattern generation
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Disable pattern generator by clearing PGE bit */
hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Custom lane pins configuration
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param CustomLane Function to be applied on selected lane.
* This parameter can be any value of @arg DSI_CustomLane
* @param Lane select between clock or data lane 0 or data lane 1.
* This parameter can be any value of @arg DSI_Lane_Select
* @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Check function parameters */
assert_param(IS_DSI_LANE(Lane));
assert_param(IS_FUNCTIONAL_STATE(State));
switch (CustomLane)
{
case DSI_SWAP_LANE_PINS:
if (Lane == DSI_CLK_LANE)
{
/* Swap pins on clock lane */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
}
else if (Lane == DSI_DATA_LANE0)
{
/* Swap pins on data lane 0 */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
}
else if (Lane == DSI_DATA_LANE1)
{
/* Swap pins on data lane 1 */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
break;
default:
break;
}
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @brief Force the Clock/Data Lane in TX Stop Mode
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @param Lane select between clock or data lanes.
* This parameter can be any value of @arg DSI_Lane_Group
* @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(State));
if (Lane == DSI_CLOCK_LANE)
{
/* Force/Unforce the Clock Lane in TX Stop Mode */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
}
else if (Lane == DSI_DATA_LANES)
{
/* Force/Unforce the Data Lanes in TX Stop Mode */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hdsi);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup DSI_Group4 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DSI state.
(+) Get error code.
@endverbatim
* @{
*/
/**
* @brief Return the DSI state
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL state
*/
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
{
return hdsi->State;
}
/**
* @brief Return the DSI error code
* @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval DSI Error Code
*/
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
{
/* Get the error code */
return hdsi->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DSI */
#endif /* HAL_DSI_MODULE_ENABLED */
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c
|
C
|
apache-2.0
| 81,364
|
/**
******************************************************************************
* @file stm32u5xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two diffenrents
interrupt pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
#define EXTI_MODE_OFFSET 0x04U /* byte offset between IMR/EMR registers */
#define EXTI_CONFIG_OFFSET 0x08U /* byte offset between Rising/Falling configuration registers */
#define EXTI_PRIVCFGR_OFFSET 0x04U /* byte offset between PRIVCFGR1/PRIVCFGR2 registers */
#define EXTI_SECCFGR_OFFSET 0x04U /* byte offset between SECCFGR1/SECCFGR2 registers */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0U)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store rising trigger mode */
*regaddr = regval;
/* Configure falling trigger */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store falling trigger mode */
*regaddr = regval;
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
}
}
/* Configure interrupt mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* Configure event mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configiguration structure */
pExtiConfig->Line = hexti->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* 1] Get core mode : interrupt */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0U)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else
{
pExtiConfig->Mode = EXTI_MODE_NONE;
}
/* Get event mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0U)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0U)
{
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Get default Trigger and GPIOSel configuration */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0U)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
/* Get falling configuration */
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0U)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3U - (linepos & 0x03U)))) >> 24U);
}
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* 1] Clear interrupt mode */
regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear event mode */
regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0U)
{
regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL];
regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U)));
EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval;
}
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicaated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->RisingCallback = pPendingCbfn;
hexti->FallingCallback = pPendingCbfn;
break;
case HAL_EXTI_RISING_CB_ID:
hexti->RisingCallback = pPendingCbfn;
break;
case HAL_EXTI_FALLING_CB_ID:
hexti->FallingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
uint32_t offset;
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
/* Get rising edge pending bit */
regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0U)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call rising callback */
if (hexti->RisingCallback != NULL)
{
hexti->RisingCallback();
}
}
/* Get falling edge pending bit */
regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0U)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call rising callback */
if (hexti->FallingCallback != NULL)
{
hexti->FallingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING
* @arg @ref EXTI_TRIGGER_FALLING
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check the parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
if (Edge != EXTI_TRIGGER_RISING)
{
/* Get falling edge pending bit */
regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
}
else
{
/* Get rising edge pending bit */
regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
}
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING
* @arg @ref EXTI_TRIGGER_FALLING
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check the parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
if (Edge != EXTI_TRIGGER_RISING)
{
/* Get falling edge pending register address */
regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
}
else
{
/* Get falling edge pending register address */
regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
}
/* Clear Pending bit */
*regaddr = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check the parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = maskline;
}
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions
* @brief EXTI attributes management functions.
*
@verbatim
===============================================================================
##### EXTI attributes functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Configure the EXTI line attribute(s).
* @note Available attributes are to secure EXTI line and set EXT line as privileged.
* Default state is not secure and unprivileged access allowed.
* @note Secure and non-secure attributes can only be set from the secure
* state when the system implements the security (TZEN=1).
* @note Security and privilege attributes can be set independently.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @param LineAttributes can be one or a combination of the following values:
* @arg @ref EXTI_LINE_PRIV Privileged-only access
* @arg @ref EXTI_LINE_NPRIV Privileged/Non-privileged access
* @arg @ref EXTI_LINE_SEC Secure-only access
* @arg @ref EXTI_LINE_NSEC Secure/Non-secure access
* @retval None
*/
void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
assert_param(IS_EXTI_LINE_ATTRIBUTES(LineAttributes));
/* compute line register offset and line mask */
offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (ExtiLine & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* Configure privilege or non-privilege attributes */
regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((LineAttributes & EXTI_LINE_PRIV) == EXTI_LINE_PRIV)
{
regval |= maskline;
}
else if ((LineAttributes & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)
{
regval &= ~maskline;
}
else
{
/* do nothing */
}
/* Store privilege or non-privilege attribute */
*regaddr = regval;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Configure secure or non-secure attributes */
regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((LineAttributes & EXTI_LINE_SEC) == EXTI_LINE_SEC)
{
regval |= maskline;
}
else if ((LineAttributes & EXTI_LINE_NSEC) == EXTI_LINE_NSEC)
{
regval &= ~maskline;
}
else
{
/* do nothing */
}
/* Store secure or non-secure attribute */
*regaddr = regval;
#endif /* __ARM_FEATURE_CMSE */
}
/**
* @brief Get the EXTI line attribute(s).
* @note Secure and non-secure attributes are only available from secure state
* when the system implements the security (TZEN=1)
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @param pLineAttributes: pointer to return line attributes.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes)
{
__IO uint32_t *regaddr;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
uint32_t attributes;
/* Check null pointer */
if (pLineAttributes == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Compute line register offset and line mask */
offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (ExtiLine & EXTI_PIN_MASK);
maskline = (1UL << linepos);
/* Get privilege or non-privilege attribute */
regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset));
if ((*regaddr & maskline) != 0U)
{
attributes = EXTI_LINE_PRIV;
}
else
{
attributes = EXTI_LINE_NPRIV;
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Get secure or non-secure attribute */
regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset));
if ((*regaddr & maskline) != 0U)
{
attributes |= EXTI_LINE_SEC;
}
else
{
attributes |= EXTI_LINE_NSEC;
}
#endif /* __ARM_FEATURE_CMSE */
/* return value */
*pLineAttributes = attributes;
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c
|
C
|
apache-2.0
| 23,174
|
/**
******************************************************************************
* @file stm32u5xx_hal_fdcan.c
* @author MCD Application Team
* @brief FDCAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Flexible DataRate Controller Area Network
* (FDCAN) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Configuration and Control functions
* + Peripheral State and Error functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function.
(#) If needed , configure the reception filters and optional features using
the following configuration functions:
(++) HAL_FDCAN_ConfigFilter
(++) HAL_FDCAN_ConfigGlobalFilter
(++) HAL_FDCAN_ConfigExtendedIdMask
(++) HAL_FDCAN_ConfigRxFifoOverwrite
(++) HAL_FDCAN_ConfigRamWatchdog
(++) HAL_FDCAN_ConfigTimestampCounter
(++) HAL_FDCAN_EnableTimestampCounter
(++) HAL_FDCAN_DisableTimestampCounter
(++) HAL_FDCAN_ConfigTimeoutCounter
(++) HAL_FDCAN_EnableTimeoutCounter
(++) HAL_FDCAN_DisableTimeoutCounter
(++) HAL_FDCAN_ConfigTxDelayCompensation
(++) HAL_FDCAN_EnableTxDelayCompensation
(++) HAL_FDCAN_DisableTxDelayCompensation
(++) HAL_FDCAN_EnableISOMode
(++) HAL_FDCAN_DisableISOMode
(++) HAL_FDCAN_EnableEdgeFiltering
(++) HAL_FDCAN_DisableEdgeFiltering
(#) Start the FDCAN module using HAL_FDCAN_Start function. At this level
the node is active on the bus: it can send and receive messages.
(#) The following Tx control functions can only be called when the FDCAN
module is started:
(++) HAL_FDCAN_AddMessageToTxFifoQ
(++) HAL_FDCAN_AbortTxRequest
(#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to
get Tx buffer location used to place the Tx request thanks to
HAL_FDCAN_GetLatestTxFifoQRequestBuffer API.
It is then possible to abort later on the corresponding Tx Request using
HAL_FDCAN_AbortTxRequest API.
(#) When a message is received into the FDCAN message RAM, it can be
retrieved using the HAL_FDCAN_GetRxMessage function.
(#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering
it to initialization mode and re-enabling access to configuration
registers through the configuration functions listed here above.
(#) All other control functions can be called any time after initialization
phase, no matter if the FDCAN module is started or stopped.
*** Polling mode operation ***
==============================
[..]
(#) Reception and transmission states can be monitored via the following
functions:
(++) HAL_FDCAN_IsTxBufferMessagePending
(++) HAL_FDCAN_GetRxFifoFillLevel
(++) HAL_FDCAN_GetTxFifoFreeLevel
*** Interrupt mode operation ***
================================
[..]
(#) There are two interrupt lines: line 0 and 1.
By default, all interrupts are assigned to line 0. Interrupt lines
can be configured using HAL_FDCAN_ConfigInterruptLines function.
(#) Notifications are activated using HAL_FDCAN_ActivateNotification
function. Then, the process can be controlled through one of the
available user callbacks: HAL_FDCAN_xxxCallback.
*** Callback registration ***
=============================================
The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
to register an interrupt callback.
Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
(+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
(+) HighPriorityMessageCallback : High Priority Message Callback.
(+) TimestampWraparoundCallback : Timestamp Wraparound Callback.
(+) TimeoutOccurredCallback : Timeout Occurred Callback.
(+) ErrorCallback : Error Callback.
(+) MspInitCallback : FDCAN MspInit.
(+) MspDeInitCallback : FDCAN MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
TxBufferCompleteCallback, TxBufferAbortCallback and ErrorStatusCallback use dedicated
register callbacks : respectively @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
@ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
@ref HAL_FDCAN_RegisterTxBufferCompleteCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback()
and @ref HAL_FDCAN_RegisterErrorStatusCallback().
Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
(+) HighPriorityMessageCallback : High Priority Message Callback.
(+) TimestampWraparoundCallback : Timestamp Wraparound Callback.
(+) TimeoutOccurredCallback : Timeout Occurred Callback.
(+) ErrorCallback : Error Callback.
(+) MspInitCallback : FDCAN MspInit.
(+) MspDeInitCallback : FDCAN MspDeInit.
For specific callbacks TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
TxBufferCompleteCallback and TxBufferAbortCallback, use dedicated
unregister callbacks : respectively @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(),
@ref HAL_FDCAN_UnRegisterRxFifo0Callback(), @ref HAL_FDCAN_UnRegisterRxFifo1Callback(),
@ref HAL_FDCAN_UnRegisterTxBufferCompleteCallback(), @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback()
and @ref HAL_FDCAN_UnRegisterErrorStatusCallback().
By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
all callbacks are set to the corresponding weak functions:
examples @ref HAL_FDCAN_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
these callbacks are null (not registered beforehand).
if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
or @ref HAL_FDCAN_Init() function.
When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
#if defined(FDCAN1)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup FDCAN FDCAN
* @brief FDCAN HAL module driver
* @{
*/
#ifdef HAL_FDCAN_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup FDCAN_Private_Constants
* @{
*/
#define FDCAN_TIMEOUT_VALUE 10U
#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFN)
#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0N)
#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1N)
#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA)
#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO)
#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */
#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */
#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */
#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */
#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */
#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */
#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */
#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */
#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */
#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */
#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */
#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */
#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */
#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */
#define SRAMCAN_FLS_NBR (28U) /* Max. Filter List Standard Number */
#define SRAMCAN_FLE_NBR ( 8U) /* Max. Filter List Extended Number */
#define SRAMCAN_RF0_NBR ( 3U) /* RX FIFO 0 Elements Number */
#define SRAMCAN_RF1_NBR ( 3U) /* RX FIFO 1 Elements Number */
#define SRAMCAN_TEF_NBR ( 3U) /* TX Event FIFO Elements Number */
#define SRAMCAN_TFQ_NBR ( 3U) /* TX FIFO/Queue Elements Number */
#define SRAMCAN_FLS_SIZE ( 1U * 4U) /* Filter Standard Element Size in bytes */
#define SRAMCAN_FLE_SIZE ( 2U * 4U) /* Filter Extended Element Size in bytes */
#define SRAMCAN_RF0_SIZE (18U * 4U) /* RX FIFO 0 Elements Size in bytes */
#define SRAMCAN_RF1_SIZE (18U * 4U) /* RX FIFO 1 Elements Size in bytes */
#define SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */
#define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */
#define SRAMCAN_FLSSA ((uint32_t)0) /* Filter List Standard Start
Address */
#define SRAMCAN_FLESA ((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start
Address */
#define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
#define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
#define SRAMCAN_TEFSA ((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start
Address */
#define SRAMCAN_TFQSA ((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start
Address */
#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @addtogroup FDCAN_Private_Variables
* @{
*/
static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
uint32_t BufferIndex);
/* Exported functions --------------------------------------------------------*/
/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions
* @{
*/
/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the FDCAN.
(+) De-initialize the FDCAN.
(+) Enter FDCAN peripheral in power down mode.
(+) Exit power down mode.
(+) Register callbacks.
(+) Unregister callbacks.
@endverbatim
* @{
*/
/**
* @brief Initializes the FDCAN peripheral according to the specified
* parameters in the FDCAN_InitTypeDef structure.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
{
uint32_t tickstart;
/* Check FDCAN handle */
if (hfdcan == NULL)
{
return HAL_ERROR;
}
/* Check function parameters */
assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
assert_param(IS_FDCAN_CKDIV(hfdcan->Init.ClockDivider));
assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat));
assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode));
assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission));
assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause));
assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException));
assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler));
assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth));
assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1));
assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2));
if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
{
assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler));
assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth));
assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1));
assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2));
}
assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, SRAMCAN_FLS_NBR));
assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, SRAMCAN_FLE_NBR));
assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode));
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
if (hfdcan->State == HAL_FDCAN_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hfdcan->Lock = HAL_UNLOCKED;
/* Reset callbacks to legacy functions */
hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak
TxBufferCompleteCallback */
hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak
TxBufferAbortCallback */
hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak
HighPriorityMessageCallback */
hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak
TimestampWraparoundCallback */
hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak
TimeoutOccurredCallback */
hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */
hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
if (hfdcan->MspInitCallback == NULL)
{
hfdcan->MspInitCallback = HAL_FDCAN_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware: CLOCK, NVIC */
hfdcan->MspInitCallback(hfdcan);
}
#else
if (hfdcan->State == HAL_FDCAN_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hfdcan->Lock = HAL_UNLOCKED;
/* Init the low level hardware: CLOCK, NVIC */
HAL_FDCAN_MspInit(hfdcan);
}
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
/* Exit from Sleep mode */
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
/* Get tick */
tickstart = HAL_GetTick();
/* Check Sleep mode acknowledge */
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
{
if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
/* Change FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_ERROR;
return HAL_ERROR;
}
}
/* Request initialisation */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until the INIT bit into CCCR register is set */
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
/* Change FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_ERROR;
return HAL_ERROR;
}
}
/* Enable configuration change */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
/* Configure Clock divider */
FDCAN_CONFIG->CKDIV = hfdcan->Init.ClockDivider;
/* Set the no automatic retransmission */
if (hfdcan->Init.AutoRetransmission == ENABLE)
{
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
}
else
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
}
/* Set the transmit pause feature */
if (hfdcan->Init.TransmitPause == ENABLE)
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
}
else
{
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
}
/* Set the Protocol Exception Handling */
if (hfdcan->Init.ProtocolException == ENABLE)
{
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
}
else
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
}
/* Set FDCAN Frame Format */
MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
/* Reset FDCAN Operation Mode */
CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
/* Set FDCAN Operating Mode:
| Normal | Restricted | Bus | Internal | External
| | Operation | Monitoring | LoopBack | LoopBack
CCCR.TEST | 0 | 0 | 0 | 1 | 1
CCCR.MON | 0 | 0 | 1 | 1 | 0
TEST.LBCK | 0 | 0 | 0 | 1 | 1
CCCR.ASM | 0 | 1 | 0 | 0 | 0
*/
if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
{
/* Enable Restricted Operation mode */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
}
else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
{
if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
{
/* Enable write access to TEST register */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
/* Enable LoopBack mode */
SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
{
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
}
}
else
{
/* Enable bus monitoring mode */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
}
}
else
{
/* Nothing to do: normal mode */
}
/* Set the nominal bit timing register */
hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
(((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \
(((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \
(((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
/* If FD operation with BRS is selected, set the data bit timing register */
if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
{
hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
(((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \
(((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \
(((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
}
/* Select between Tx FIFO and Tx Queue operation modes */
SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
/* Calculate each RAM block address */
FDCAN_CalcultateRamBlockAddresses(hfdcan);
/* Initialize the Latest Tx request buffer index */
hfdcan->LatestTxFifoQRequest = 0U;
/* Initialize the error code */
hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
/* Initialize the FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Deinitializes the FDCAN peripheral registers to their default reset values.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan)
{
/* Check FDCAN handle */
if (hfdcan == NULL)
{
return HAL_ERROR;
}
/* Check function parameters */
assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance));
/* Stop the FDCAN module: return value is voluntary ignored */
(void)HAL_FDCAN_Stop(hfdcan);
/* Disable Interrupt lines */
CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1));
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
if (hfdcan->MspDeInitCallback == NULL)
{
hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: CLOCK, NVIC */
hfdcan->MspDeInitCallback(hfdcan);
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_FDCAN_MspDeInit(hfdcan);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
/* Reset the FDCAN ErrorCode */
hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
/* Change FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_RESET;
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the FDCAN MSP.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the FDCAN MSP.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Enter FDCAN peripheral in sleep mode.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
{
uint32_t tickstart;
/* Request clock stop */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until FDCAN is ready for power down */
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U)
{
if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
/* Change FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_ERROR;
return HAL_ERROR;
}
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Exit power down mode.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
{
uint32_t tickstart;
/* Reset clock stop request */
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until FDCAN exits sleep mode */
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
{
if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
/* Change FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_ERROR;
return HAL_ERROR;
}
}
/* Enter normal operation */
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
/* Return function status */
return HAL_OK;
}
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/**
* @brief Register a FDCAN CallBack.
* To be used instead of the weak predefined callback
* @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
* the configuration information for FDCAN module
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
* @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
* @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
* @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
* @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
* @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
switch (CallbackID)
{
case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
hfdcan->TxFifoEmptyCallback = pCallback;
break;
case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
hfdcan->HighPriorityMessageCallback = pCallback;
break;
case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
hfdcan->TimestampWraparoundCallback = pCallback;
break;
case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
hfdcan->TimeoutOccurredCallback = pCallback;
break;
case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
hfdcan->ErrorCallback = pCallback;
break;
case HAL_FDCAN_MSPINIT_CB_ID :
hfdcan->MspInitCallback = pCallback;
break;
case HAL_FDCAN_MSPDEINIT_CB_ID :
hfdcan->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
{
switch (CallbackID)
{
case HAL_FDCAN_MSPINIT_CB_ID :
hfdcan->MspInitCallback = pCallback;
break;
case HAL_FDCAN_MSPDEINIT_CB_ID :
hfdcan->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a FDCAN CallBack.
* FDCAN callback is redirected to the weak predefined callback
* @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains
* the configuration information for FDCAN module
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID
* @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID
* @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID
* @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID
* @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID
* @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
switch (CallbackID)
{
case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID :
hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback;
break;
case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID :
hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback;
break;
case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID :
hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback;
break;
case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID :
hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback;
break;
case HAL_FDCAN_ERROR_CALLBACK_CB_ID :
hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback;
break;
case HAL_FDCAN_MSPINIT_CB_ID :
hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
break;
case HAL_FDCAN_MSPDEINIT_CB_ID :
hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
break;
default :
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hfdcan->State == HAL_FDCAN_STATE_RESET)
{
switch (CallbackID)
{
case HAL_FDCAN_MSPINIT_CB_ID :
hfdcan->MspInitCallback = HAL_FDCAN_MspInit;
break;
case HAL_FDCAN_MSPDEINIT_CB_ID :
hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit;
break;
default :
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Register Tx Event Fifo FDCAN Callback
* To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
* @param hfdcan FDCAN handle
* @param pCallback pointer to the Tx Event Fifo Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
pFDCAN_TxEventFifoCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->TxEventFifoCallback = pCallback;
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief UnRegister the Tx Event Fifo FDCAN Callback
* Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback
* @param hfdcan FDCAN handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan)
{
HAL_StatusTypeDef status = HAL_OK;
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Register Rx Fifo 0 FDCAN Callback
* To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback
* @param hfdcan FDCAN handle
* @param pCallback pointer to the Rx Fifo 0 Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
pFDCAN_RxFifo0CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->RxFifo0Callback = pCallback;
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief UnRegister the Rx Fifo 0 FDCAN Callback
* Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback
* @param hfdcan FDCAN handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan)
{
HAL_StatusTypeDef status = HAL_OK;
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Register Rx Fifo 1 FDCAN Callback
* To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback
* @param hfdcan FDCAN handle
* @param pCallback pointer to the Rx Fifo 1 Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
pFDCAN_RxFifo1CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->RxFifo1Callback = pCallback;
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief UnRegister the Rx Fifo 1 FDCAN Callback
* Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback
* @param hfdcan FDCAN handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan)
{
HAL_StatusTypeDef status = HAL_OK;
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Register Tx Buffer Complete FDCAN Callback
* To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
* @param hfdcan FDCAN handle
* @param pCallback pointer to the Tx Buffer Complete Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->TxBufferCompleteCallback = pCallback;
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief UnRegister the Tx Buffer Complete FDCAN Callback
* Tx Buffer Complete FDCAN Callback is redirected to
* the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
* @param hfdcan FDCAN handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan)
{
HAL_StatusTypeDef status = HAL_OK;
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback */
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Register Tx Buffer Abort FDCAN Callback
* To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
* @param hfdcan FDCAN handle
* @param pCallback pointer to the Tx Buffer Abort Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->TxBufferAbortCallback = pCallback;
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief UnRegister the Tx Buffer Abort FDCAN Callback
* Tx Buffer Abort FDCAN Callback is redirected to
* the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
* @param hfdcan FDCAN handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan)
{
HAL_StatusTypeDef status = HAL_OK;
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Register Error Status FDCAN Callback
* To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
* @param hfdcan FDCAN handle
* @param pCallback pointer to the Error Status Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
pFDCAN_ErrorStatusCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->ErrorStatusCallback = pCallback;
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief UnRegister the Error Status FDCAN Callback
* Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback
* @param hfdcan FDCAN handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan)
{
HAL_StatusTypeDef status = HAL_OK;
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
}
else
{
/* Update the error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
* @brief FDCAN Configuration functions.
*
@verbatim
==============================================================================
##### Configuration functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) HAL_FDCAN_ConfigFilter : Configure the FDCAN reception filters
(+) HAL_FDCAN_ConfigGlobalFilter : Configure the FDCAN global filter
(+) HAL_FDCAN_ConfigExtendedIdMask : Configure the extended ID mask
(+) HAL_FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO operation mode
(+) HAL_FDCAN_ConfigRamWatchdog : Configure the RAM watchdog
(+) HAL_FDCAN_ConfigTimestampCounter : Configure the timestamp counter
(+) HAL_FDCAN_EnableTimestampCounter : Enable the timestamp counter
(+) HAL_FDCAN_DisableTimestampCounter : Disable the timestamp counter
(+) HAL_FDCAN_GetTimestampCounter : Get the timestamp counter value
(+) HAL_FDCAN_ResetTimestampCounter : Reset the timestamp counter to zero
(+) HAL_FDCAN_ConfigTimeoutCounter : Configure the timeout counter
(+) HAL_FDCAN_EnableTimeoutCounter : Enable the timeout counter
(+) HAL_FDCAN_DisableTimeoutCounter : Disable the timeout counter
(+) HAL_FDCAN_GetTimeoutCounter : Get the timeout counter value
(+) HAL_FDCAN_ResetTimeoutCounter : Reset the timeout counter to its start value
(+) HAL_FDCAN_ConfigTxDelayCompensation : Configure the transmitter delay compensation
(+) HAL_FDCAN_EnableTxDelayCompensation : Enable the transmitter delay compensation
(+) HAL_FDCAN_DisableTxDelayCompensation : Disable the transmitter delay compensation
(+) HAL_FDCAN_EnableISOMode : Enable ISO 11898-1 protocol mode
(+) HAL_FDCAN_DisableISOMode : Disable ISO 11898-1 protocol mode
(+) HAL_FDCAN_EnableEdgeFiltering : Enable edge filtering during bus integration
(+) HAL_FDCAN_DisableEdgeFiltering : Disable edge filtering during bus integration
@endverbatim
* @{
*/
/**
* @brief Configure the FDCAN reception filter according to the specified
* parameters in the FDCAN_FilterTypeDef structure.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that
* contains the filter configuration information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
{
uint32_t FilterElementW1;
uint32_t FilterElementW2;
uint32_t *FilterAddress;
HAL_FDCAN_StateTypeDef state = hfdcan->State;
if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
{
/* Check function parameters */
assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType));
assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig));
if (sFilterConfig->IdType == FDCAN_STANDARD_ID)
{
/* Check function parameters */
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U)));
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU));
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU));
assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType));
/* Build filter element */
FilterElementW1 = ((sFilterConfig->FilterType << 30U) |
(sFilterConfig->FilterConfig << 27U) |
(sFilterConfig->FilterID1 << 16U) |
sFilterConfig->FilterID2);
/* Calculate filter address */
FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLS_SIZE));
/* Write filter element to the message RAM */
*FilterAddress = FilterElementW1;
}
else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */
{
/* Check function parameters */
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U)));
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU));
assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU));
assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType));
/* Build first word of filter element */
FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1);
/* Build second word of filter element */
FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2);
/* Calculate filter address */
FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * SRAMCAN_FLE_SIZE));
/* Write filter element to the message RAM */
*FilterAddress = FilterElementW1;
FilterAddress++;
*FilterAddress = FilterElementW2;
}
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @brief Configure the FDCAN global filter.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param NonMatchingStd Defines how received messages with 11-bit IDs that
* do not match any element of the filter list are treated.
* This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
* @param NonMatchingExt Defines how received messages with 29-bit IDs that
* do not match any element of the filter list are treated.
* This parameter can be a value of @arg FDCAN_Non_Matching_Frames.
* @param RejectRemoteStd Filter or reject all the remote 11-bit IDs frames.
* This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
* @param RejectRemoteExt Filter or reject all the remote 29-bit IDs frames.
* This parameter can be a value of @arg FDCAN_Reject_Remote_Frames.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
uint32_t NonMatchingStd,
uint32_t NonMatchingExt,
uint32_t RejectRemoteStd,
uint32_t RejectRemoteExt)
{
/* Check function parameters */
assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd));
assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt));
assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd));
assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt));
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Configure global filter */
MODIFY_REG(hfdcan->Instance->RXGFC, (FDCAN_RXGFC_ANFS |
FDCAN_RXGFC_ANFE |
FDCAN_RXGFC_RRFS |
FDCAN_RXGFC_RRFE),
((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos) |
(NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) |
(RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) |
(RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos)));
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Configure the extended ID mask.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param Mask Extended ID Mask.
This parameter must be a number between 0 and 0x1FFFFFFF
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
{
/* Check function parameters */
assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU));
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Configure the extended ID mask */
hfdcan->Instance->XIDAM = Mask;
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Configure the Rx FIFO operation mode.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param RxFifo Rx FIFO.
* This parameter can be one of the following values:
* @arg FDCAN_RX_FIFO0: Rx FIFO 0
* @arg FDCAN_RX_FIFO1: Rx FIFO 1
* @param OperationMode operation mode.
* This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode)
{
/* Check function parameters */
assert_param(IS_FDCAN_RX_FIFO(RxFifo));
assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode));
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
if (RxFifo == FDCAN_RX_FIFO0)
{
/* Select FIFO 0 Operation Mode */
MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F0OM, (OperationMode << FDCAN_RXGFC_F0OM_Pos));
}
else /* RxFifo == FDCAN_RX_FIFO1 */
{
/* Select FIFO 1 Operation Mode */
MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_F1OM, (OperationMode << FDCAN_RXGFC_F1OM_Pos));
}
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Configure the RAM watchdog.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param CounterStartValue Start value of the Message RAM Watchdog Counter,
* This parameter must be a number between 0x00 and 0xFF,
* with the reset value of 0x00 the counter is disabled.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue)
{
/* Check function parameters */
assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU));
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Configure the RAM watchdog counter start value */
MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Configure the timestamp counter.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param TimestampPrescaler Timestamp Counter Prescaler.
* This parameter can be a value of @arg FDCAN_Timestamp_Prescaler.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler)
{
/* Check function parameters */
assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler));
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Configure prescaler */
MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Enable the timestamp counter.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param TimestampOperation Timestamp counter operation.
* This parameter can be a value of @arg FDCAN_Timestamp.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation)
{
/* Check function parameters */
assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation));
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Enable timestamp counter */
MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Disable the timestamp counter.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Disable timestamp counter */
CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Get the timestamp counter value.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval Timestamp counter value
*/
uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
{
return (uint16_t)(hfdcan->Instance->TSCV);
}
/**
* @brief Reset the timestamp counter to zero.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
{
if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL)
{
/* Reset timestamp counter.
Actually any write operation to TSCV clears the counter */
CLEAR_REG(hfdcan->Instance->TSCV);
}
else
{
/* Update error code.
Unable to reset external counter */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Configure the timeout counter.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param TimeoutOperation Timeout counter operation.
* This parameter can be a value of @arg FDCAN_Timeout_Operation.
* @param TimeoutPeriod Start value of the timeout down-counter.
* This parameter must be a number between 0x0000 and 0xFFFF
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
uint32_t TimeoutPeriod)
{
/* Check function parameters */
assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU));
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Select timeout operation and configure period */
MODIFY_REG(hfdcan->Instance->TOCC,
(FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Enable the timeout counter.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Enable timeout counter */
SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Disable the timeout counter.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Disable timeout counter */
CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Get the timeout counter value.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval Timeout counter value
*/
uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
{
return (uint16_t)(hfdcan->Instance->TOCV);
}
/**
* @brief Reset the timeout counter to its start value.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
{
if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS)
{
/* Reset timeout counter to start value */
CLEAR_REG(hfdcan->Instance->TOCV);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code.
Unable to reset counter: controlled only by FIFO empty state */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
}
/**
* @brief Configure the transmitter delay compensation.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param TdcOffset Transmitter Delay Compensation Offset.
* This parameter must be a number between 0x00 and 0x7F.
* @param TdcFilter Transmitter Delay Compensation Filter Window Length.
* This parameter must be a number between 0x00 and 0x7F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
uint32_t TdcFilter)
{
/* Check function parameters */
assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU));
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Configure TDC offset and filter window */
hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos));
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Enable the transmitter delay compensation.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Enable transmitter delay compensation */
SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Disable the transmitter delay compensation.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Disable transmitter delay compensation */
CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Enable ISO 11898-1 protocol mode.
* CAN FD frame format is according to ISO 11898-1 standard.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Disable Non ISO protocol mode */
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Disable ISO 11898-1 protocol mode.
* CAN FD frame format is according to Bosch CAN FD specification V1.0.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Enable Non ISO protocol mode */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Enable edge filtering during bus integration.
* Two consecutive dominant tq are required to detect an edge for hard synchronization.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Enable edge filtering */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Disable edge filtering during bus integration.
* One dominant tq is required to detect an edge for hard synchronization.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Disable edge filtering */
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @}
*/
/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
* @brief Control functions
*
@verbatim
==============================================================================
##### Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) HAL_FDCAN_Start : Start the FDCAN module
(+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers
(+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding
transmission request
(+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
(+) HAL_FDCAN_AbortTxRequest : Abort transmission request
(+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx FIFO zone into the message RAM
(+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone
into the message RAM
(+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status
(+) HAL_FDCAN_GetProtocolStatus : Get protocol status
(+) HAL_FDCAN_GetErrorCounters : Get error counter values
(+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending
on the selected Tx buffer
(+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level
(+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level
(+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode
(+) HAL_FDCAN_ExitRestrictedOperationMode : Exit Restricted Operation Mode
@endverbatim
* @{
*/
/**
* @brief Start the FDCAN module.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
{
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Change FDCAN peripheral state */
hfdcan->State = HAL_FDCAN_STATE_BUSY;
/* Request leave initialisation */
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
/* Reset the FDCAN ErrorCode */
hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
return HAL_ERROR;
}
}
/**
* @brief Stop the FDCAN module and enable access to configuration registers.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
{
uint32_t Counter = 0U;
if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
{
/* Request initialisation */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
/* Wait until the INIT bit into CCCR register is set */
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
{
/* Check for the Timeout */
if (Counter > FDCAN_TIMEOUT_VALUE)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
/* Change FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_ERROR;
return HAL_ERROR;
}
/* Increment counter */
Counter++;
}
/* Reset counter */
Counter = 0U;
/* Exit from Sleep mode */
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
/* Wait until FDCAN exits sleep mode */
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
{
/* Check for the Timeout */
if (Counter > FDCAN_TIMEOUT_VALUE)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
/* Change FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_ERROR;
return HAL_ERROR;
}
/* Increment counter */
Counter++;
}
/* Enable configuration change */
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
/* Reset Latest Tx FIFO/Queue Request Buffer Index */
hfdcan->LatestTxFifoQRequest = 0U;
/* Change FDCAN peripheral state */
hfdcan->State = HAL_FDCAN_STATE_READY;
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
return HAL_ERROR;
}
}
/**
* @brief Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
* @param pTxData pointer to a buffer containing the payload of the Tx frame.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
uint8_t *pTxData)
{
uint32_t PutIndex;
/* Check function parameters */
assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
if (pTxHeader->IdType == FDCAN_STANDARD_ID)
{
assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
}
else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
{
assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
}
assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
{
/* Check that the Tx FIFO/Queue is not full */
if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
return HAL_ERROR;
}
else
{
/* Retrieve the Tx FIFO PutIndex */
PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
/* Add the message to the Tx FIFO/Queue */
FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
/* Activate the corresponding transmission request */
hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
/* Store the Latest Tx FIFO/Queue Request Buffer Index */
hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
}
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
return HAL_ERROR;
}
}
/**
* @brief Get Tx buffer index of latest Tx FIFO/Queue request
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval Tx buffer index of last Tx FIFO/Queue request
* - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
* - 0 if no Tx FIFO/Queue request have been submitted.
*/
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
{
/* Return Last Tx FIFO/Queue Request Buffer */
return hfdcan->LatestTxFifoQRequest;
}
/**
* @brief Abort transmission request
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param BufferIndex buffer index.
* This parameter can be any combination of @arg FDCAN_Tx_location.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex)
{
/* Check function parameters */
assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndex));
if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
{
/* Add cancellation request */
hfdcan->Instance->TXBCR = BufferIndex;
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
return HAL_ERROR;
}
}
/**
* @brief Get an FDCAN frame from the Rx FIFO zone into the message RAM.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param RxLocation Location of the received message to be read.
* This parameter can be a value of @arg FDCAN_Rx_location.
* @param pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure.
* @param pRxData pointer to a buffer where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
{
uint32_t *RxAddress;
uint8_t *pData;
uint32_t ByteCounter;
uint32_t GetIndex;
HAL_FDCAN_StateTypeDef state = hfdcan->State;
/* Check function parameters */
assert_param(IS_FDCAN_RX_FIFO(RxLocation));
if (state == HAL_FDCAN_STATE_BUSY)
{
if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
{
/* Check that the Rx FIFO 0 is not empty */
if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
return HAL_ERROR;
}
else
{
/* Calculate Rx FIFO 0 element address */
GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE));
}
}
else /* Rx element is assigned to the Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
return HAL_ERROR;
}
else
{
/* Calculate Rx FIFO 1 element address */
GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE));
}
}
/* Retrieve IdType */
pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
/* Retrieve Identifier */
if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
{
pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
}
else /* Extended ID element */
{
pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
}
/* Retrieve RxFrameType */
pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
/* Retrieve ErrorStateIndicator */
pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
/* Increment RxAddress pointer to second word of Rx FIFO element */
RxAddress++;
/* Retrieve RxTimestamp */
pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
/* Retrieve DataLength */
pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
/* Retrieve BitRateSwitch */
pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
/* Retrieve FDFormat */
pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
/* Retrieve FilterIndex */
pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
/* Retrieve NonMatchingFrame */
pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
/* Increment RxAddress pointer to payload of Rx FIFO element */
RxAddress++;
/* Retrieve Rx payload */
pData = (uint8_t *)RxAddress;
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16U]; ByteCounter++)
{
pRxData[ByteCounter] = pData[ByteCounter];
}
if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
{
/* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
hfdcan->Instance->RXF0A = GetIndex;
}
else /* Rx element is assigned to the Rx FIFO 1 */
{
/* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
hfdcan->Instance->RXF1A = GetIndex;
}
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
return HAL_ERROR;
}
}
/**
* @brief Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent)
{
uint32_t *TxEventAddress;
uint32_t GetIndex;
HAL_FDCAN_StateTypeDef state = hfdcan->State;
if (state == HAL_FDCAN_STATE_BUSY)
{
/* Check that the Tx event FIFO is not empty */
if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U)
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
return HAL_ERROR;
}
/* Calculate Tx event FIFO element address */
GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos);
TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * SRAMCAN_TEF_SIZE));
/* Retrieve IdType */
pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD;
/* Retrieve Identifier */
if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
{
pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
}
else /* Extended ID element */
{
pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID);
}
/* Retrieve TxFrameType */
pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR);
/* Retrieve ErrorStateIndicator */
pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI);
/* Increment TxEventAddress pointer to second word of Tx Event FIFO element */
TxEventAddress++;
/* Retrieve TxTimestamp */
pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
/* Retrieve DataLength */
pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
/* Retrieve BitRateSwitch */
pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
/* Retrieve FDFormat */
pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF);
/* Retrieve EventType */
pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
/* Retrieve MessageMarker */
pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U);
/* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
hfdcan->Instance->TXEFA = GetIndex;
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
return HAL_ERROR;
}
}
/**
* @brief Get high priority message status.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
{
HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI);
HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX);
/* Return function status */
return HAL_OK;
}
/**
* @brief Get protocol status.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
{
uint32_t StatusReg;
/* Read the protocol status register */
StatusReg = READ_REG(hfdcan->Instance->PSR);
/* Fill the protocol status structure */
ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC);
ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos);
ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT);
ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos);
ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos);
ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos);
ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos);
ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos);
ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos);
ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos);
ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos);
/* Return function status */
return HAL_OK;
}
/**
* @brief Get error counter values.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
{
uint32_t CountersReg;
/* Read the error counters register */
CountersReg = READ_REG(hfdcan->Instance->ECR);
/* Fill the error counters structure */
ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos);
ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos);
ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos);
ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos);
/* Return function status */
return HAL_OK;
}
/**
* @brief Check if a transmission request is pending on the selected Tx buffer.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param TxBufferIndex Tx buffer index.
* This parameter can be any combination of @arg FDCAN_Tx_location.
* @retval Status
* - 0 : No pending transmission request on TxBufferIndex list
* - 1 : Pending transmission request on TxBufferIndex.
*/
uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
{
/* Check function parameters */
assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex));
/* Check pending transmission request on the selected buffer */
if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
{
return 0;
}
return 1;
}
/**
* @brief Return Rx FIFO fill level.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param RxFifo Rx FIFO.
* This parameter can be one of the following values:
* @arg FDCAN_RX_FIFO0: Rx FIFO 0
* @arg FDCAN_RX_FIFO1: Rx FIFO 1
* @retval Rx FIFO fill level.
*/
uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
{
uint32_t FillLevel;
/* Check function parameters */
assert_param(IS_FDCAN_RX_FIFO(RxFifo));
if (RxFifo == FDCAN_RX_FIFO0)
{
FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL;
}
else /* RxFifo == FDCAN_RX_FIFO1 */
{
FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL;
}
/* Return Rx FIFO fill level */
return FillLevel;
}
/**
* @brief Return Tx FIFO free level: number of consecutive free Tx FIFO
* elements starting from Tx FIFO GetIndex.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval Tx FIFO free level.
*/
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
{
uint32_t FreeLevel;
FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL;
/* Return Tx FIFO free level */
return FreeLevel;
}
/**
* @brief Check if the FDCAN peripheral entered Restricted Operation Mode.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval Status
* - 0 : Normal FDCAN operation.
* - 1 : Restricted Operation Mode active.
*/
uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
{
uint32_t OperationMode;
/* Get Operation Mode */
OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos);
return OperationMode;
}
/**
* @brief Exit Restricted Operation Mode.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
{
HAL_FDCAN_StateTypeDef state = hfdcan->State;
if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
{
/* Exit Restricted Operation mode */
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @}
*/
/** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management
* @brief Interrupts management
*
@verbatim
==============================================================================
##### Interrupts management #####
==============================================================================
[..] This section provides functions allowing to:
(+) HAL_FDCAN_ConfigInterruptLines : Assign interrupts to either Interrupt line 0 or 1
(+) HAL_FDCAN_ActivateNotification : Enable interrupts
(+) HAL_FDCAN_DeactivateNotification : Disable interrupts
(+) HAL_FDCAN_IRQHandler : Handles FDCAN interrupt request
@endverbatim
* @{
*/
/**
* @brief Assign interrupts to either Interrupt line 0 or 1.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param ITList indicates which interrupts group will be assigned to the selected interrupt line.
* This parameter can be any combination of @arg FDCAN_Interrupts_Group.
* @param InterruptLine Interrupt line.
* This parameter can be a value of @arg FDCAN_Interrupt_Line.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine)
{
HAL_FDCAN_StateTypeDef state = hfdcan->State;
/* Check function parameters */
assert_param(IS_FDCAN_IT_GROUP(ITList));
assert_param(IS_FDCAN_IT_LINE(InterruptLine));
if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
{
/* Assign list of interrupts to the selected line */
if (InterruptLine == FDCAN_INTERRUPT_LINE0)
{
CLEAR_BIT(hfdcan->Instance->ILS, ITList);
}
else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */
{
SET_BIT(hfdcan->Instance->ILS, ITList);
}
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @brief Enable interrupts.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param ActiveITs indicates which interrupts will be enabled.
* This parameter can be any combination of @arg FDCAN_Interrupts.
* @param BufferIndexes Tx Buffer Indexes.
* This parameter can be any combination of @arg FDCAN_Tx_location.
* This parameter is ignored if ActiveITs does not include one of the following:
* - FDCAN_IT_TX_COMPLETE
* - FDCAN_IT_TX_ABORT_COMPLETE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
uint32_t BufferIndexes)
{
HAL_FDCAN_StateTypeDef state = hfdcan->State;
uint32_t ITs_lines_selection;
/* Check function parameters */
assert_param(IS_FDCAN_IT(ActiveITs));
if ((ActiveITs & (FDCAN_IT_TX_COMPLETE | FDCAN_IT_TX_ABORT_COMPLETE)) != 0U)
{
assert_param(IS_FDCAN_TX_LOCATION_LIST(BufferIndexes));
}
if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
{
/* Get interrupts line selection */
ITs_lines_selection = hfdcan->Instance->ILS;
/* Enable Interrupt lines */
if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_MISC) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
{
/* Enable Interrupt line 0 */
SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
}
if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_MISC) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
(((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
{
/* Enable Interrupt line 1 */
SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
}
if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
{
/* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
but interrupt will only occur if TC is enabled in IE register */
SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
}
if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
{
/* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
but interrupt will only occur if TCF is enabled in IE register */
SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
}
/* Enable the selected interrupts */
__HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @brief Disable interrupts.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param InactiveITs indicates which interrupts will be disabled.
* This parameter can be any combination of @arg FDCAN_Interrupts.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs)
{
HAL_FDCAN_StateTypeDef state = hfdcan->State;
uint32_t ITs_enabled;
uint32_t ITs_lines_selection;
/* Check function parameters */
assert_param(IS_FDCAN_IT(InactiveITs));
if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
{
/* Disable the selected interrupts */
__HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs);
if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
{
/* Disable Tx Buffer Transmission Interrupts */
CLEAR_REG(hfdcan->Instance->TXBTIE);
}
if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
{
/* Disable Tx Buffer Cancellation Finished Interrupt */
CLEAR_REG(hfdcan->Instance->TXBCIE);
}
/* Get interrupts enabled and interrupts line selection */
ITs_enabled = hfdcan->Instance->IE;
ITs_lines_selection = hfdcan->Instance->ILS;
/* Check if some interrupts are still enabled on interrupt line 0 */
if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
{
/* Do nothing */
}
else /* no more interrupts enabled on interrupt line 0 */
{
/* Disable interrupt line 0 */
CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
}
/* Check if some interrupts are still enabled on interrupt line 1 */
if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
(((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
&& (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
{
/* Do nothing */
}
else /* no more interrupts enabled on interrupt line 1 */
{
/* Disable interrupt line 1 */
CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
}
/* Return function status */
return HAL_OK;
}
else
{
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
return HAL_ERROR;
}
}
/**
* @brief Handles FDCAN interrupt request.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
{
uint32_t TxEventFifoITs;
uint32_t RxFifo0ITs;
uint32_t RxFifo1ITs;
uint32_t Errors;
uint32_t ErrorStatusITs;
uint32_t TransmittedBuffers;
uint32_t AbortedBuffers;
TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
TxEventFifoITs &= hfdcan->Instance->IE;
RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
RxFifo0ITs &= hfdcan->Instance->IE;
RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
RxFifo1ITs &= hfdcan->Instance->IE;
Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
Errors &= hfdcan->Instance->IE;
ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
ErrorStatusITs &= hfdcan->Instance->IE;
/* High Priority Message interrupt management *******************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
{
/* Clear the High Priority Message flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->HighPriorityMessageCallback(hfdcan);
#else
/* High Priority Message Callback */
HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Transmission Abort interrupt management **********************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
{
/* List of aborted monitored buffers */
AbortedBuffers = hfdcan->Instance->TXBCF;
AbortedBuffers &= hfdcan->Instance->TXBCIE;
/* Clear the Transmission Cancellation flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
#else
/* Transmission Cancellation Callback */
HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Tx event FIFO interrupts management **************************************/
if (TxEventFifoITs != 0U)
{
/* Clear the Tx Event FIFO flags */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
#else
/* Tx Event FIFO Callback */
HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
/* Rx FIFO 0 interrupts management ******************************************/
if (RxFifo0ITs != 0U)
{
/* Clear the Rx FIFO 0 flags */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
#else
/* Rx FIFO 0 Callback */
HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
/* Rx FIFO 1 interrupts management ******************************************/
if (RxFifo1ITs != 0U)
{
/* Clear the Rx FIFO 1 flags */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
#else
/* Rx FIFO 1 Callback */
HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
/* Tx FIFO empty interrupt management ***************************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
{
/* Clear the Tx FIFO empty flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TxFifoEmptyCallback(hfdcan);
#else
/* Tx FIFO empty Callback */
HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Transmission Complete interrupt management *******************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
{
/* List of transmitted monitored buffers */
TransmittedBuffers = hfdcan->Instance->TXBTO;
TransmittedBuffers &= hfdcan->Instance->TXBTIE;
/* Clear the Transmission Complete flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
#else
/* Transmission Complete Callback */
HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Timestamp Wraparound interrupt management ********************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
{
/* Clear the Timestamp Wraparound flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TimestampWraparoundCallback(hfdcan);
#else
/* Timestamp Wraparound Callback */
HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Timeout Occurred interrupt management ************************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
{
/* Clear the Timeout Occurred flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->TimeoutOccurredCallback(hfdcan);
#else
/* Timeout Occurred Callback */
HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/* Message RAM access failure interrupt management **************************/
if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
{
if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
{
/* Clear the Message RAM access failure flag */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
/* Update error code */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
}
}
/* Error Status interrupts management ***************************************/
if (ErrorStatusITs != 0U)
{
/* Clear the Error flags */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
#else
/* Error Status Callback */
HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
/* Error interrupts management **********************************************/
if (Errors != 0U)
{
/* Clear the Error flags */
__HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
/* Update error code */
hfdcan->ErrorCode |= Errors;
}
if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
{
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hfdcan->ErrorCallback(hfdcan);
#else
/* Error Callback */
HAL_FDCAN_ErrorCallback(hfdcan);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
}
/**
* @}
*/
/** @defgroup FDCAN_Exported_Functions_Group5 Callback functions
* @brief FDCAN Callback functions
*
@verbatim
==============================================================================
##### Callback functions #####
==============================================================================
[..]
This subsection provides the following callback functions:
(+) HAL_FDCAN_TxEventFifoCallback
(+) HAL_FDCAN_RxFifo0Callback
(+) HAL_FDCAN_RxFifo1Callback
(+) HAL_FDCAN_TxFifoEmptyCallback
(+) HAL_FDCAN_TxBufferCompleteCallback
(+) HAL_FDCAN_TxBufferAbortCallback
(+) HAL_FDCAN_HighPriorityMessageCallback
(+) HAL_FDCAN_TimestampWraparoundCallback
(+) HAL_FDCAN_TimeoutOccurredCallback
(+) HAL_FDCAN_ErrorCallback
(+) HAL_FDCAN_ErrorStatusCallback
@endverbatim
* @{
*/
/**
* @brief Tx Event callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signalled.
* This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
* @retval None
*/
__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
UNUSED(TxEventFifoITs);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
*/
}
/**
* @brief Rx FIFO 0 callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signalled.
* This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts.
* @retval None
*/
__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
UNUSED(RxFifo0ITs);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
*/
}
/**
* @brief Rx FIFO 1 callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signalled.
* This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
* @retval None
*/
__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
UNUSED(RxFifo1ITs);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
*/
}
/**
* @brief Tx FIFO Empty callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
*/
}
/**
* @brief Transmission Complete callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param BufferIndexes Indexes of the transmitted buffers.
* This parameter can be any combination of @arg FDCAN_Tx_location.
* @retval None
*/
__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
UNUSED(BufferIndexes);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
*/
}
/**
* @brief Transmission Cancellation callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param BufferIndexes Indexes of the aborted buffers.
* This parameter can be any combination of @arg FDCAN_Tx_location.
* @retval None
*/
__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
UNUSED(BufferIndexes);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
*/
}
/**
* @brief Timestamp Wraparound callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
*/
}
/**
* @brief Timeout Occurred callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
*/
}
/**
* @brief High Priority Message callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
*/
}
/**
* @brief Error callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval None
*/
__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief Error status callback.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param ErrorStatusITs indicates which Error Status interrupts are signaled.
* This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts.
* @retval None
*/
__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
UNUSED(ErrorStatusITs);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup FDCAN_Exported_Functions_Group6 Peripheral State functions
* @brief FDCAN Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State functions #####
==============================================================================
[..]
This subsection provides functions allowing to :
(+) HAL_FDCAN_GetState() : Return the FDCAN state.
(+) HAL_FDCAN_GetError() : Return the FDCAN error code if any.
@endverbatim
* @{
*/
/**
* @brief Return the FDCAN state
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL state
*/
HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
{
/* Return FDCAN state */
return hfdcan->State;
}
/**
* @brief Return the FDCAN error code
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval FDCAN Error Code
*/
uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
{
/* Return FDCAN error code */
return hfdcan->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
* @{
*/
/**
* @brief Calculate each RAM block start address and size
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval none
*/
static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
{
uint32_t RAMcounter;
uint32_t SramCanInstanceBase = SRAMCAN_BASE;
/* Standard filter list start address */
hfdcan->msgRam.StandardFilterSA = SramCanInstanceBase + SRAMCAN_FLSSA;
/* Standard filter elements number */
MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_RXGFC_LSS_Pos));
/* Extended filter list start address */
hfdcan->msgRam.ExtendedFilterSA = SramCanInstanceBase + SRAMCAN_FLESA;
/* Extended filter elements number */
MODIFY_REG(hfdcan->Instance->RXGFC, FDCAN_RXGFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_RXGFC_LSE_Pos));
/* Rx FIFO 0 start address */
hfdcan->msgRam.RxFIFO0SA = SramCanInstanceBase + SRAMCAN_RF0SA;
/* Rx FIFO 1 start address */
hfdcan->msgRam.RxFIFO1SA = SramCanInstanceBase + SRAMCAN_RF1SA;
/* Tx event FIFO start address */
hfdcan->msgRam.TxEventFIFOSA = SramCanInstanceBase + SRAMCAN_TEFSA;
/* Tx FIFO/queue start address */
hfdcan->msgRam.TxFIFOQSA = SramCanInstanceBase + SRAMCAN_TFQSA;
/* Flush the allocated Message RAM area */
for (RAMcounter = SramCanInstanceBase; RAMcounter < (SramCanInstanceBase + SRAMCAN_SIZE); RAMcounter += 4U)
{
*(uint32_t *)(RAMcounter) = 0x00000000U;
}
}
/**
* @brief Copy Tx message to the message RAM.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
* @param pTxData pointer to a buffer containing the payload of the Tx frame.
* @param BufferIndex index of the buffer to be configured.
* @retval none
*/
static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
uint32_t BufferIndex)
{
uint32_t TxElementW1;
uint32_t TxElementW2;
uint32_t *TxAddress;
uint32_t ByteCounter;
/* Build first word of Tx header element */
if (pTxHeader->IdType == FDCAN_STANDARD_ID)
{
TxElementW1 = (pTxHeader->ErrorStateIndicator |
FDCAN_STANDARD_ID |
pTxHeader->TxFrameType |
(pTxHeader->Identifier << 18U));
}
else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
{
TxElementW1 = (pTxHeader->ErrorStateIndicator |
FDCAN_EXTENDED_ID |
pTxHeader->TxFrameType |
pTxHeader->Identifier);
}
/* Build second word of Tx header element */
TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
pTxHeader->TxEventFifoControl |
pTxHeader->FDFormat |
pTxHeader->BitRateSwitch |
pTxHeader->DataLength);
/* Calculate Tx element address */
TxAddress = (uint32_t *)(hfdcan->msgRam.TxFIFOQSA + (BufferIndex * SRAMCAN_TFQ_SIZE));
/* Write Tx element header to the message RAM */
*TxAddress = TxElementW1;
TxAddress++;
*TxAddress = TxElementW2;
TxAddress++;
/* Write Tx payload to the message RAM */
for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16U]; ByteCounter += 4U)
{
*TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
((uint32_t)pTxData[ByteCounter + 1U] << 8U) |
(uint32_t)pTxData[ByteCounter]);
TxAddress++;
}
}
/**
* @}
*/
#endif /* HAL_FDCAN_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
#endif /* FDCAN1 */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c
|
C
|
apache-2.0
| 121,951
|
/**
******************************************************************************
* @file stm32u5xx_hal_flash.c
* @author MCD Application Team
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
* + Program operations functions
* + Memory Control functions
* + Peripheral Errors functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### FLASH peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB C-Bus accesses to the Flash memory.
It implements the erase and program Flash memory operations and the read
and write protection mechanisms.
[..] The Flash memory interface implements the TrustZone security features (TZ) supported
by ARM Cortex-M33 core (CM33).
[..] The FLASH main features are:
(+) Flash memory read operations
(+) Flash memory program/erase operations
(+) Read / write protections
(+) Option bytes programming
(+) TrustZone aware
(+) Watermark-based area protection including the secure hide area
(+) Block-based page protection
(+) Error code correction (ECC) : Data in flash are 137-bits word
(9 bits added per quad-word)
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
memory of all STM32U5xx devices.
(#) Flash Memory IO Programming functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Program functions: quad-words and burst program (8 quad-words)
(++) There are two modes of programming :
(+++) Polling mode using HAL_FLASH_Program() function
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
(#) Interrupts and flags management functions :
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
(++) Callback functions are called when the flash operations are finished :
HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
HAL_FLASH_OperationErrorCallback()
(++) Get error flag status by calling HAL_GetError()
(#) Option bytes management functions :
(++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
HAL_FLASH_OB_Lock() functions
(++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
In this case, a reset is generated
[..]
In addition to these functions, this driver includes a set of macros allowing
to handle the following operations:
(+) Set the latency
(+) Enable/Disable the Flash power-down during low-power run and sleep modes
(+) Enable/Disable the Flash interrupts
(+) Monitor the Flash flags status
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
/**
* @brief Variable used for Program/Erase sectors under interruption
*/
FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
.ErrorCode = HAL_FLASH_ERROR_NONE, \
.ProcedureOnGoing = 0U, \
.Address = 0U, \
.Bank = FLASH_BANK_1, \
.Page = 0U, \
.NbPagesToErase = 0U
};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
* @{
*/
static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress);
static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
===============================================================================
##### Programming operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the FLASH
program operations.
@endverbatim
* @{
*/
/**
* @brief Program a quad-word or a burst of 8 quad-words at a specified address.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address specifies the address to be programmed.
* This parameter shall be aligned to the Flash word (128 bits)
* @param DataAddress specifies the address of data to be programmed.
* This parameter shall be 32-bit aligned
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress)
{
HAL_StatusTypeDef status;
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status == HAL_OK)
{
/* Set current operation type */
pFlash.ProcedureOnGoing = TypeProgram;
/* Access to SECCR or NSCR depends on operation type */
reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD)
{
/* Program a quad-word (128-bit) at a specified address */
FLASH_Program_QuadWord(Address, DataAddress);
}
else
{
/* Program a burst of 8 quad-words at a specified address */
FLASH_Program_Burst(Address, DataAddress);
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG (and BWR Bit in Burst programming mode) */
CLEAR_BIT((*reg_cr), (TypeProgram & ~(FLASH_NON_SECURE_MASK)));
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
/* return status */
return status;
}
/**
* @brief Program a quad-word or a burst of 8 quad-words at a specified address with interrupt enabled.
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address specifies the address to be programmed.
* This parameter shall be aligned to the Flash word (128 bits)
* @param DataAddress specifies the address of data to be programmed.
* This parameter shall be 32-bit aligned
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress)
{
HAL_StatusTypeDef status;
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
else
{
/* Set internal variables used by the IRQ handler */
pFlash.ProcedureOnGoing = TypeProgram;
pFlash.Address = Address;
/* Access to SECCR or NSCR depends on operation type */
reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
/* Enable End of Operation and Error interrupts */
(*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR);
if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD)
{
/* Program a quad-word (128-bit) at a specified address */
FLASH_Program_QuadWord(Address, DataAddress);
}
else
{
/* Program a burst of 8 quad-words at a specified address */
FLASH_Program_Burst(Address, DataAddress);
}
}
return status;
}
/**
* @brief Handle FLASH interrupt request.
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
{
uint32_t param = 0U;
uint32_t error;
__IO uint32_t *reg_cr;
__IO uint32_t *reg_sr;
/* Access to CR and SR registers depends on operation type */
reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR);
/* Save Flash errors */
error = (*reg_sr) & FLASH_FLAG_SR_ERRORS;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
error |= (FLASH->NSSR & FLASH_FLAG_OPTWERR);
#endif /* __ARM_FEATURE_CMSE */
/* Set parameter of the callback */
if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_PAGES)
{
param = pFlash.Page;
}
else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
{
param = pFlash.Bank;
}
else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD)
{
param = pFlash.Address;
}
else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_BURST)
{
param = pFlash.Address;
}
else
{
/* Empty statement (to be compliant MISRA 15.7) */
}
/* Clear operation bit on the on-going procedure */
CLEAR_BIT((*reg_cr), (pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK)));
/* Check FLASH operation error flags */
if (error != 0U)
{
/* Save the error code */
pFlash.ErrorCode |= error;
/* Clear error programming flags */
(*reg_sr) = error;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
if ((error & FLASH_FLAG_OPTWERR) != 0U)
{
FLASH->NSSR = FLASH_FLAG_OPTWERR;
}
#endif /* __ARM_FEATURE_CMSE */
/* Stop the procedure ongoing */
pFlash.ProcedureOnGoing = 0U;
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(param);
}
/* Check FLASH End of Operation flag */
if (((*reg_sr) & FLASH_FLAG_EOP) != 0U)
{
/* Clear FLASH End of Operation pending bit */
(*reg_sr) = FLASH_FLAG_EOP;
if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_PAGES)
{
/* Nb of pages to erase can be decreased */
pFlash.NbPagesToErase--;
/* Check if there are still pages to erase */
if (pFlash.NbPagesToErase != 0U)
{
/* Increment page number */
pFlash.Page++;
FLASH_PageErase(pFlash.Page, pFlash.Bank);
}
else
{
/* No more pages to Erase */
pFlash.ProcedureOnGoing = 0U;
param = 0xFFFFFFFFU;
}
}
else
{
/*Clear the procedure ongoing*/
pFlash.ProcedureOnGoing = 0U;
}
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(param);
}
if (pFlash.ProcedureOnGoing == 0U)
{
/* Disable End of Operation and Error interrupts */
(*reg_cr) &= ~(FLASH_IT_EOP | FLASH_IT_OPERR);
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
}
/**
* @brief FLASH end of operation interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Page Erase: Page which has been erased
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
}
/**
* @brief FLASH operation error interrupt callback.
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Page Erase: Page number which returned an error
* Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief Management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
memory operations.
@endverbatim
* @{
*/
/**
* @brief Unlock the FLASH control register access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
HAL_StatusTypeDef status = HAL_OK;
if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->NSKEYR, FLASH_KEY1);
WRITE_REG(FLASH->NSKEYR, FLASH_KEY2);
/* verify Flash is unlocked */
if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U)
{
status = HAL_ERROR;
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
if (status == HAL_OK)
{
if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U)
{
/* Authorize the FLASH Registers access */
WRITE_REG(FLASH->SECKEYR, FLASH_KEY1);
WRITE_REG(FLASH->SECKEYR, FLASH_KEY2);
/* verify Flash is unlocked */
if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U)
{
status = HAL_ERROR;
}
}
}
#endif /* __ARM_FEATURE_CMSE */
return status;
}
/**
* @brief Lock the FLASH control register access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Set the LOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->NSCR, FLASH_NSCR_LOCK);
/* verify Flash is locked */
if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U)
{
status = HAL_OK;
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
if (status == HAL_OK)
{
SET_BIT(FLASH->SECCR, FLASH_SECCR_LOCK);
/* verify Flash is locked */
if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U)
{
status = HAL_OK;
}
}
#endif /* __ARM_FEATURE_CMSE */
return status;
}
/**
* @brief Unlock the FLASH Option Bytes Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U)
{
/* Authorizes the Option Byte register programming */
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
/* Verify that the Option Bytes are unlocked */
if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U)
{
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief Lock the FLASH Option Bytes Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK);
/* Verify that the Option Bytes are locked */
if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U)
{
return HAL_OK;
}
return HAL_ERROR;
}
/**
* @brief Launch the option byte loading.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
/* Set the bit to force the option byte reloading */
SET_BIT(FLASH->NSCR, FLASH_NSCR_OBL_LAUNCH);
/* We should not reach here : Option byte launch generates Option byte reset
so return error */
return HAL_ERROR;
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
===============================================================================
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permits to get in run-time Errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode The returned value can be:
* @arg HAL_FLASH_ERROR_NONE: No error set
* @arg HAL_FLASH_ERROR_OP: FLASH Operation error
* @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
* @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
* @arg HAL_FLASH_ERROR_OPTW: FLASH Option modification error
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY and WDW flags to be reset.
Even if the FLASH operation fails, the BUSY & WDW flags will be reset, and an error flag will be set */
uint32_t timeout = HAL_GetTick() + Timeout;
uint32_t error;
__IO uint32_t *reg_sr;
/* Access to SECSR or NSSR registers depends on operation type */
reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR);
while (((*reg_sr) & (FLASH_FLAG_BSY | FLASH_FLAG_WDW)) != 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
if (HAL_GetTick() >= timeout)
{
return HAL_TIMEOUT;
}
}
}
/* Check FLASH operation error flags */
error = ((*reg_sr) & FLASH_FLAG_SR_ERRORS);
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
error |= (FLASH->NSSR & FLASH_FLAG_OPTWERR);
#endif /* __ARM_FEATURE_CMSE */
if (error != 0U)
{
/*Save the error code*/
pFlash.ErrorCode |= error;
/* Clear error programming flags */
(*reg_sr) = error;
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
if ((error & FLASH_FLAG_OPTWERR) != 0U)
{
FLASH->NSSR = FLASH_FLAG_OPTWERR;
}
#endif /* __ARM_FEATURE_CMSE */
return HAL_ERROR;
}
/* Check FLASH End of Operation flag */
if (((*reg_sr) & FLASH_FLAG_EOP) != 0U)
{
/* Clear FLASH End of Operation pending bit */
(*reg_sr) = FLASH_FLAG_EOP;
}
/* If there is no error flag set */
return HAL_OK;
}
/**
* @brief Program a quad-word (128-bit) at a specified address.
* @param Address specifies the address to be programmed.
* @param DataAddress specifies the address of data to be programmed.
* @retval None
*/
static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress)
{
uint8_t index = 4;
uint32_t *dest_addr = (uint32_t *)Address;
uint32_t *src_addr = (uint32_t *)DataAddress;
uint32_t primask_bit;
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Access to SECCR or NSCR registers depends on operation type */
reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
/* Set PG bit */
SET_BIT((*reg_cr), FLASH_NSCR_PG);
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the quad-word */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
index--;
} while (index != 0U);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @brief Program a burst of 8x quad-words at a specified address.
* @param Address: specifies the address to be programmed.
* @param DataAddress: specifies the address where the data are stored.
* @retval None
*/
static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress)
{
uint8_t burst_index = FLASH_NB_WORDS_IN_BURST;
uint32_t *dest_addr = (uint32_t *)Address;
uint32_t *src_addr = (uint32_t *)DataAddress;
uint32_t primask_bit;
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
/* Access to SECCR or NSCR registers depends on operation type */
reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
/* Set PG and BWR bits */
SET_BIT((*reg_cr), (FLASH_NSCR_PG | FLASH_NSCR_BWR));
/* Enter critical section: Disable interrupts to avoid any interruption during the loop */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Program the burst */
do
{
*dest_addr = *src_addr;
dest_addr++;
src_addr++;
burst_index--;
} while (burst_index != 0U);
/* Exit critical section: restore previous priority mask */
__set_PRIMASK(primask_bit);
}
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c
|
C
|
apache-2.0
| 23,285
|
/**
******************************************************************************
* @file stm32u5xx_hal_flash_ex.c
* @author MCD Application Team
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extended peripheral:
* + Extended programming operations functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### Flash Extended features #####
==============================================================================
[..] Comparing to other previous devices, the FLASH interface for STM32U5xx
devices contains the following additional features
(+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
capability (RWW)
(+) Dual bank memory organization
(+) Watermark-based secure area including the secure hide areas
(+) Block-based secure pages
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure and program the FLASH memory
of all STM32U5xx devices. It includes:
(#) Flash Memory Erase functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Erase function: page Erase and Bank/Mass Erase
(++) There are two modes of erase :
(+++) Polling Mode using HAL_FLASHEx_Erase()
(+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
(#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to:
(++) Configure the write protection for each area
(++) Set the Read protection Level
(++) Program the user Option Bytes
(++) Configure the watermark security for each area including the secure hide areas
(++) Configure the boot lock (BOOT_LOCK)
(++) Configure the Boot addresses
(#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to:
(++) Get the value of a write protection area
(++) Know if the read protection is activated
(++) Get the value of the user Option Bytes
(++) Get the configuration of a watermark security area including the secure hide areas
(++) Get the boot lock (BOOT_LOCK) configuration
(++) Get the value of a boot address
(#) Block-based secure / privilege area configuration function: Use HAL_FLASHEx_ConfigBBAttributes()
(++) Bit-field allowing to secure or un-secure each page
(++) Bit-field allowing to privilege or un-privilege each page
(#) Get the block-based secure / privilege area configuration function: Use HAL_FLASHEx_GetBBSec()
(++) Return the configuration of the block-based security and privilege for all the pages
(#) Activation of the secure hide area function: Use HAL_FLASHEx_EnableSecHideProtection()
(++) Deny the access to the secure hide area
(#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode()
(++) FLASH register can be protected against non-privilege accesses
(#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode()
(++) Return if the FLASH registers are protected against non-privilege accesses
(#) Security inversion configuration function: Use HAL_FLASHEx_ConfigSecInversion()
(++) FLASH secure state can be override
(#) Get the security inversion configuration function: Use HAL_FLASHEx_GetSecInversion()
(++) Return if FLASH secure state is override
(#) Enable bank low-power mode function: Use HAL_FLASHEx_EnablePowerDown()
(++) Enable low-power mode for Flash Bank 1 and/or Bank 2
(#) Enable low-power read mode function: Use HAL_FLASHEx_ConfigLowPowerRead()
(++) Enable low-power read mode for Flash memory
(#) Get the low-power read mode configuration function: Use HAL_FLASHEx_GetLowPowerRead()
(++) Return if FLASH is in low-power read mode or normal read mode
(#) Get Flash operation function: Use HAL_FLASHEx_GetOperation()
(++) Return information about the on-going Flash operation. After a
system reset, return information about the interrupted Flash operation, if any.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup FLASHEx FLASHEx
* @brief FLASH Extended HAL module driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
* @{
*/
static void FLASH_MassErase(uint32_t Banks);
static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset,
FunctionalState WRPLock);
static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage,
uint32_t WMHDPEndPage);
static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig);
#endif /* __ARM_FEATURE_CMSE */
static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr);
static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset,
FunctionalState *WRPLock);
static uint32_t FLASH_OB_GetRDP(void);
static uint32_t FLASH_OB_GetUser(void);
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage,
uint32_t *WMHDPEndPage);
static uint32_t FLASH_OB_GetBootLock(void);
#endif /* __ARM_FEATURE_CMSE */
static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr);
static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2);
/**
* @}
*/
/* Exported functions -------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
* @{
*/
/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
* @brief Extended IO operation functions
*
@verbatim
===============================================================================
##### Extended programming operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the Extended FLASH
programming operations Operations.
@endverbatim
* @{
*/
/**
* @brief Perform a mass erase or erase the specified FLASH memory pages.
* @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
*
* @param[out] PageError pointer to variable that contains the configuration
* information on faulty page in case of error (0xFFFFFFFF means that all
* the pages have been correctly erased).
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
HAL_StatusTypeDef status;
uint32_t page_index;
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status == HAL_OK)
{
/* Current operation type */
pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
/* Access to SECCR or NSCR depends on operation type */
reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR);
if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
{
/* Mass erase to be done */
FLASH_MassErase(pEraseInit->Banks);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
else
{
/*Initialization of PageError variable*/
*PageError = 0xFFFFFFFFU;
for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
{
FLASH_PageErase(page_index, pEraseInit->Banks);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status != HAL_OK)
{
/* In case of error, stop erase procedure and return the faulty page */
*PageError = page_index;
break;
}
}
}
/* If the erase operation is completed, disable the associated bits */
CLEAR_BIT((*reg_cr), (pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK)));
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
/**
* @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
* @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
HAL_StatusTypeDef status;
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
else
{
/* Set internal variables used by the IRQ handler */
pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
pFlash.Bank = pEraseInit->Banks;
/* Access to SECCR or NSCR depends on operation type */
reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR);
/* Enable End of Operation and Error interrupts */
(*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR);
if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
{
/* Mass erase to be done */
FLASH_MassErase(pEraseInit->Banks);
}
else
{
/* Erase by page to be done */
pFlash.NbPagesToErase = pEraseInit->NbPages;
pFlash.Page = pEraseInit->Page;
/* Erase first page and wait for IT */
FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
}
}
return status;
}
/**
* @brief Program Option bytes.
* @param pOBInit pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
* @note To configure any option bytes, the option lock bit OPTLOCK must be
* cleared with the call of HAL_FLASH_OB_Unlock() function.
* @note New option bytes configuration will be taken into account in two cases:
* - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
* - after a power reset (BOR reset or exit from Standby/Shutdown modes)
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
{
HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Reset error code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status == HAL_OK)
{
/* Write protection configuration */
if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
{
/* Configure of Write protection on the selected area */
FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset, pOBInit->WRPLock);
}
/* Read protection configuration */
if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
{
/* Configure the Read protection level */
FLASH_OB_RDPConfig(pOBInit->RDPLevel);
}
/* Read protection key configuration */
if ((pOBInit->OptionType & OPTIONBYTE_RDPKEY) != 0U)
{
/* Configure the Read protection key */
FLASH_OB_RDPKeyConfig(pOBInit->RDPKeyType, pOBInit->RDPKey1, pOBInit->RDPKey2);
}
/* User Configuration */
if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
{
/* Configure the user option bytes */
FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Watermark secure configuration */
if ((pOBInit->OptionType & OPTIONBYTE_WMSEC) != 0U)
{
/* Configure the watermark-based secure area */
FLASH_OB_WMSECConfig(pOBInit->WMSecConfig, pOBInit->WMSecStartPage, pOBInit->WMSecEndPage,
pOBInit->WMHDPEndPage);
}
/* Unique boot entry point configuration */
if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U)
{
/* Configure the unique boot entry point */
FLASH_OB_BootLockConfig(pOBInit->BootLock);
}
#endif /* __ARM_FEATURE_CMSE */
/* Boot address configuration */
if ((pOBInit->OptionType & OPTIONBYTE_BOOTADDR) != 0U)
{
/* Configure the boot address */
FLASH_OB_BootAddrConfig(pOBInit->BootAddrConfig, pOBInit->BootAddr);
}
/* Set OPTSTRT Bit */
SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTSTRT);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
/**
* @brief Get the Option bytes configuration.
* @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the
* configuration information.
* @note The fields pOBInit->WRPArea, pOBInit->WMSecConfig and pOBInit->BootAddrConfig
* should indicate which area/address is requested for the WRP, WM Security or
* Boot Address, else no information will be returned
*
* @retval None
*/
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
{
pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
(pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
{
pOBInit->OptionType |= OPTIONBYTE_WRP;
/* Get write protection on the selected area */
FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset), &(pOBInit->WRPLock));
}
/* Get Read protection level */
pOBInit->RDPLevel = FLASH_OB_GetRDP();
/* Get the user option bytes */
pOBInit->USERConfig = FLASH_OB_GetUser();
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Get the configuration of the watermark secure area for the selected area */
if ((pOBInit->WMSecConfig == OB_WMSEC_AREA1) || (pOBInit->WMSecConfig == OB_WMSEC_AREA2))
{
pOBInit->OptionType |= OPTIONBYTE_WMSEC;
FLASH_OB_GetWMSEC(&(pOBInit->WMSecConfig), &(pOBInit->WMSecStartPage), &(pOBInit->WMSecEndPage),
&(pOBInit->WMHDPEndPage));
}
pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK;
/* Get the configuration of the unique boot entry point */
pOBInit->BootLock = FLASH_OB_GetBootLock();
#endif /* __ARM_FEATURE_CMSE */
/* Get the value of the selected boot address */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1) ||
(pOBInit->BootAddrConfig == OB_BOOTADDR_SEC0))
#else
if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1))
#endif /* __ARM_FEATURE_CMSE */
{
pOBInit->OptionType |= OPTIONBYTE_BOOTADDR;
FLASH_OB_GetBootAddr(pOBInit->BootAddrConfig, &(pOBInit->BootAddr));
}
}
/**
* @brief Configure the block-based secure area.
*
* @param pBBAttributes pointer to an FLASH_BBAttributesTypeDef structure that
* contains the configuration information for the programming.
*
* @note The field pBBAttributes->Bank should indicate which area is requested
* for the block-based attributes.
* @note The field pBBAttributes->BBAttributesType should indicate which
* block-base attribute type is requested: Secure or Privilege.
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
{
HAL_StatusTypeDef status;
uint8_t index;
__IO uint32_t *reg;
/* Check the parameters */
assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status == HAL_OK)
{
/* Set the first Block-Based register to write */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
{
if (pBBAttributes->Bank == FLASH_BANK_1)
{
reg = &(FLASH->SECBB1R1);
}
else
{
reg = &(FLASH->SECBB2R1);
}
}
else
#endif /* __ARM_FEATURE_CMSE */
{
if (pBBAttributes->Bank == FLASH_BANK_1)
{
reg = &(FLASH->PRIVBB1R1);
}
else
{
reg = &(FLASH->PRIVBB2R1);
}
}
/* Modify the register values and check that new attributes are taken in account */
for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
{
*reg = pBBAttributes->BBAttributes_array[index];
if ((*reg) != pBBAttributes->BBAttributes_array[index])
{
status = HAL_ERROR;
}
reg++;
}
/* ISB instruction is called to be sure next instructions are performed with correct attributes */
__ISB();
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
/**
* @brief Return the block-based attributes.
*
* @param pBBAttributes [in/out] pointer to an FLASH_BBAttributesTypeDef structure
* that contains the configuration information.
* @note The field pBBAttributes->Bank should indicate which area is requested
* for the block-based attributes.
* @note The field pBBAttributes->BBAttributesType should indicate which
* block-base attribute type is requested: Secure or Privilege.
*
* @retval None
*/
void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
{
uint8_t index;
__IO uint32_t *reg;
/* Check the parameters */
assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType));
/* Set the first Block-Based register to read */
if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
{
if (pBBAttributes->Bank == FLASH_BANK_1)
{
reg = &(FLASH->SECBB1R1);
}
else
{
reg = &(FLASH->SECBB2R1);
}
}
else
{
if (pBBAttributes->Bank == FLASH_BANK_1)
{
reg = &(FLASH->PRIVBB1R1);
}
else
{
reg = &(FLASH->PRIVBB2R1);
}
}
/* Read the register values */
for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
{
pBBAttributes->BBAttributes_array[index] = (*reg);
reg++;
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Activation of the protection of the secure hide area.
*
* @param Banks indicate the bank concerned by the activation
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: Bank1 to be protected
* @arg FLASH_BANK_2: Bank2 to be protected
* @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected
*
* @retval None
*/
void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks)
{
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
if ((Banks & FLASH_BANK_1) != 0U)
{
SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP1_ACCDIS);
}
if ((Banks & FLASH_BANK_2) != 0U)
{
SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP2_ACCDIS);
}
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/** @addtogroup FLASHEx_Exported_Functions_Group2 FLASHEx Exported Functions Group2
* @{
*/
/**
* @brief Configuration of the privilege attribute.
*
* @param PrivMode indicate privilege mode configuration
* This parameter can be one of the following values:
* @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged
* or unprivileged access
* @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied
* to unprivileged access
* @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged
* or unprivileged access
* @arg FLASH_NSPRIV_DENIED: access to non-secure Flash registers is denied
* to unprivilege access
*
* @retval None
*/
void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode)
{
/* Check the parameters */
assert_param(IS_FLASH_CFGPRIVMODE(PrivMode));
MODIFY_REG(FLASH->PRIVCFGR, (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV), PrivMode);
}
/**
* @brief Return the value of the privilege attribute.
*
* @retval It indicates the privilege mode configuration.
* This return value can be one of the following values:
* @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged
* or unprivileged access
* @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied
* to unprivileged access
* @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged
* or unprivileged access
* @arg FLASH_NSPRIV_DENIED: access to Flash registers is denied
* to unprivilege accessP
*/
uint32_t HAL_FLASHEx_GetPrivMode(void)
{
return (FLASH->PRIVCFGR & (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV));
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Configuration of the security inversion.
*
* @param SecInvState indicate the flash security state configuration
* This parameter can be one of the following values:
* @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
* @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState)
{
HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_FLASH_CFGSECINV(SecInvState));
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status == HAL_OK)
{
MODIFY_REG(FLASH->SECCR, FLASH_SECCR_INV, SecInvState);
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
/**
* @brief Return the value of the security inversion.
*
* @retval It indicates the flash security state configuration
* This return value can be one of the following values:
* @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
* @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
*/
uint32_t HAL_FLASHEx_GetSecInversion(void)
{
return (FLASH->SECCR & FLASH_SECCR_INV);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Enable the Power-down Mode for Flash Banks
* @param Banks indicate which bank to put in power-down mode
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: Flash Bank 1
* @arg FLASH_BANK_2: Flash Bank 2
* @arg FLASH_BANK_BOTH: Flash Bank 1 and Bank 2
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
/* Request power-down mode for Bank 1 */
if ((Banks & FLASH_BANK_1) != 0U)
{
/* Check PD1 and PDREQ1 bits (Bank 1 is not in power-down mode and not being
already under power-down request) */
if ((FLASH->NSSR & FLASH_NSSR_PD1) != 0U)
{
status = HAL_ERROR;
}
else if ((FLASH->ACR & FLASH_ACR_PDREQ1) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Unlock PDREQ1 bit */
WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_1);
WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_2);
/* Set PDREQ1 in FLASH_ACR register */
SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1);
/* Check PD1 bit */
tickstart = HAL_GetTick();
while (((FLASH->NSSR & FLASH_NSSR_PD1) != FLASH_NSSR_PD1))
{
if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
/* Request power-down mode for Bank 2 */
if ((Banks & FLASH_BANK_2) != 0U)
{
/* Check PD2 and PDREQ2 bits (Bank 2 is not in power-down mode and not being
already under power-down request) */
if ((FLASH->NSSR & FLASH_NSSR_PD2) != 0U)
{
status = HAL_ERROR;
}
else if ((FLASH->ACR & FLASH_ACR_PDREQ2) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Unlock PDREQ2 bit */
WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_1);
WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_2);
/* Set PDREQ2 in FLASH_ACR register */
SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2);
/* Check PD2 bit */
tickstart = HAL_GetTick();
while (((FLASH->NSSR & FLASH_NSSR_PD2) != FLASH_NSSR_PD2))
{
if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
return status;
}
/**
* @brief Configuration of the Low-Power read Mode.
*
* @param ConfigLPM indicate the Low-Power read Mode configuration.
* This parameter can be one of the following values:
* @arg FLASH_LPM_ENABLE: Flash is in low-power read mode
* @arg FLASH_LPM_DISABLE: Flash is in normal read mode
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_FLASH_CFGLPM(ConfigLPM));
/* Set LPM Bit in FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LPM, ConfigLPM);
/* Check that low power read mode has been activated */
if (READ_BIT(FLASH->ACR, FLASH_ACR_LPM) != ConfigLPM)
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Return the value of the Low-Power read Mode.
*
* @retval It indicates the flash low-power read mode configuration
* This return value can be one of the following values:
* @arg FLASH_LPM_ENABLE: Flash is in low-power read mode
* @arg FLASH_LPM_DISABLE: Flash is in normal read mode
*/
uint32_t HAL_FLASHEx_GetLowPowerRead(void)
{
return (FLASH->ACR & FLASH_ACR_LPM);
}
/**
* @brief Return the on-going Flash Operation. After a system reset, return
* the interrupted Flash operation, if any.
* @param pFlashOperation [out] pointer to a FLASH_OperationTypeDef structure
* that contains the Flash operation information.
*
* @retval None
*/
void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation)
{
uint32_t opsr_reg = FLASH->OPSR;
/* Get Flash operation Type */
pFlashOperation->OperationType = opsr_reg & FLASH_OPSR_CODE_OP;
/* Get Flash operation memory */
pFlashOperation->FlashArea = opsr_reg & (FLASH_OPSR_SYSF_OP | FLASH_OPSR_BK_OP);
/* Get Flash operation address */
pFlashOperation->Address = opsr_reg & FLASH_OPSR_ADDR_OP;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup FLASHEx_Private_Functions
* @{
*/
/**
* @brief Mass erase of FLASH memory.
* @param Banks Banks to be erased
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: Bank1 to be erased
* @arg FLASH_BANK_2: Bank2 to be erased
* @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
* @retval None
*/
static void FLASH_MassErase(uint32_t Banks)
{
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_BANK(Banks));
/* Access to SECCR or NSCR registers depends on operation type */
reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
/* Set the Mass Erase Bit for the bank 1 and proceed to erase */
if ((Banks & FLASH_BANK_1) != 0U)
{
SET_BIT((*reg_cr), FLASH_NSCR_MER1 | FLASH_NSCR_STRT);
}
/* Set the Mass Erase Bit for the bank 2 and proceed to erase */
if ((Banks & FLASH_BANK_2) != 0U)
{
SET_BIT((*reg_cr), FLASH_NSCR_MER2 | FLASH_NSCR_STRT);
}
}
/**
* @brief Erase the specified FLASH memory page.
* @param Page FLASH page to erase
* This parameter must be a value between 0 and (max number of pages in the bank - 1)
* @param Banks Bank(s) where the page will be erased
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: Page in bank 1 to be erased
* @arg FLASH_BANK_2: Page in bank 2 to be erased
* @retval None
*/
void FLASH_PageErase(uint32_t Page, uint32_t Banks)
{
__IO uint32_t *reg_cr;
/* Check the parameters */
assert_param(IS_FLASH_PAGE(Page));
assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
/* Access to SECCR or NSCR registers depends on operation type */
reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
if ((Banks & FLASH_BANK_1) != 0U)
{
CLEAR_BIT((*reg_cr), FLASH_NSCR_BKER);
}
else
{
SET_BIT((*reg_cr), FLASH_NSCR_BKER);
}
/* Proceed to erase the page */
MODIFY_REG((*reg_cr), (FLASH_NSCR_PNB | FLASH_NSCR_PER | FLASH_NSCR_STRT), \
((Page << FLASH_NSCR_PNB_Pos) | FLASH_NSCR_PER | FLASH_NSCR_STRT));
}
/**
* @brief Configure the write protection of the desired pages.
*
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase Flash memory if the CPU debug
* features are connected (JTAG or single wire) or boot code is being
* executed from RAM or System flash, even if WRP is not activated.
* @note To configure the WRP options, the option lock bit OPTLOCK must be
* cleared with the call of the HAL_FLASH_OB_Unlock() function.
* @note To validate the WRP options, the option bytes must be reloaded
* through the call of the HAL_FLASH_OB_Launch() function.
*
* @param WRPArea specifies the area to be configured.
* This parameter can be one of the following values:
* @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
* @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
* @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A
* @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B
*
* @param WRPStartOffset specifies the start page of the write protected area
* This parameter can be page number between 0 and (max number of pages in the bank - 1)
*
* @param WRPEndOffset specifies the end page of the write protected area
* This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
*
* @param WRPLock enables the lock of the write protected area
* This parameter can be set to ENABLE or DISABLE
*
* @retval None
*/
static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset,
FunctionalState WRPLock)
{
/* Check the parameters */
assert_param(IS_OB_WRPAREA(WRPArea));
assert_param(IS_FLASH_PAGE(WRPStartOffset));
assert_param(IS_FLASH_PAGE(WRPEndOffset));
assert_param(IS_FUNCTIONAL_STATE(WRPLock));
/* Configure the write protected area */
if (WRPArea == OB_WRPAREA_BANK1_AREAA)
{
FLASH->WRP1AR = (((uint32_t)(~WRPLock) << FLASH_WRP1AR_UNLOCK_Pos) | \
(WRPEndOffset << FLASH_WRP1AR_WRP1A_PEND_Pos) | \
WRPStartOffset);
}
else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
{
FLASH->WRP1BR = (((uint32_t)(~WRPLock) << FLASH_WRP1BR_UNLOCK_Pos) | \
(WRPEndOffset << FLASH_WRP1BR_WRP1B_PEND_Pos) | \
WRPStartOffset);
}
else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
{
FLASH->WRP2AR = (((uint32_t)(~WRPLock) << FLASH_WRP2AR_UNLOCK_Pos) | \
(WRPEndOffset << FLASH_WRP2AR_WRP2A_PEND_Pos) | \
WRPStartOffset);
}
else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
{
FLASH->WRP2BR = (((uint32_t)(~WRPLock) << FLASH_WRP2BR_UNLOCK_Pos) | \
(WRPEndOffset << FLASH_WRP2BR_WRP2B_PEND_Pos) | \
WRPStartOffset);
}
else
{
/* Empty statement (to be compliant MISRA 15.7) */
}
}
/**
* @brief Set the read protection level.
*
* @note To configure the RDP level, the option lock bit OPTLOCK must be
* cleared with the call of the HAL_FLASH_OB_Unlock() function.
* @note To validate the RDP level, the option bytes must be reloaded
* through the call of the HAL_FLASH_OB_Launch() function.
* @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
* to go back to other levels !!!
*
* @param RDPLevel specifies the read protection level.
* This parameter can be one of the following values:
* @arg OB_RDP_LEVEL_0: No protection
* @arg OB_RDP_LEVEL_0_5: No debug access to secure area
* @arg OB_RDP_LEVEL_1: Read protection of the memory
* @arg OB_RDP_LEVEL_2: Full chip protection
*
* @retval None
*/
static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
{
/* Check the parameters */
assert_param(IS_OB_RDP_LEVEL(RDPLevel));
/* Configure the RDP level in the option bytes register */
MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
}
/**
* @brief Set the read protection key.
* @param RDPKeyType specifies the read protection key type.
* This parameter can be one of the following values:
* @arg OB_RDP_KEY_OEM1: OEM1 key
* @arg OB_RDP_KEY_OEM2: OEM2 key
* @param RDPKey1 specifies the RDP key 1.
* @param RDPKey2 specifies the RDP key 2.
* @retval None
*/
static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2)
{
/* Check the parameters */
assert_param(IS_OB_RDP_KEY_TYPE(RDPKeyType));
/* Configure the RDP OEM key */
if (RDPKeyType == OB_RDP_KEY_OEM1)
{
WRITE_REG(FLASH->OEM1KEYR1, RDPKey1);
WRITE_REG(FLASH->OEM1KEYR2, RDPKey2);
}
else
{
WRITE_REG(FLASH->OEM2KEYR1, RDPKey1);
WRITE_REG(FLASH->OEM2KEYR2, RDPKey2);
}
}
/**
* @brief Program the FLASH User Option Byte.
*
* @note To configure the user option bytes, the option lock bit OPTLOCK must
* be cleared with the call of the HAL_FLASH_OB_Unlock() function.
* @note To validate the user option bytes, the option bytes must be reloaded
* through the call of the HAL_FLASH_OB_Launch() function.
* @param UserType: The FLASH User Option Bytes to be modified.
* This parameter can be a combination of @ref FLASH_OB_USER_Type
* @param UserConfig The selected User Option Bytes values.
* This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
* @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
* @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
* @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
* @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
* @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
* @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC,
* @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST,
* @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
* @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV,
* @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN
* @retval None
*/
static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
{
uint32_t optr_reg_val = 0;
uint32_t optr_reg_mask = 0;
/* Check the parameters */
assert_param(IS_OB_USER_TYPE(UserType));
if ((UserType & OB_USER_BOR_LEV) != 0U)
{
/* BOR level option byte should be modified */
assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
/* Set value and mask for BOR level option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
optr_reg_mask |= FLASH_OPTR_BOR_LEV;
}
if ((UserType & OB_USER_NRST_STOP) != 0U)
{
/* nRST_STOP option byte should be modified */
assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
/* Set value and mask for nRST_STOP option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
optr_reg_mask |= FLASH_OPTR_nRST_STOP;
}
if ((UserType & OB_USER_NRST_STDBY) != 0U)
{
/* nRST_STDBY option byte should be modified */
assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
/* Set value and mask for nRST_STDBY option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
}
if ((UserType & OB_USER_NRST_SHDW) != 0U)
{
/* nRST_SHDW option byte should be modified */
assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
/* Set value and mask for nRST_SHDW option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
}
if ((UserType & OB_USER_SRAM134_RST) != 0U)
{
/* SRAM134_RST option byte should be modified */
assert_param(IS_OB_USER_SRAM134_RST(UserConfig & FLASH_OPTR_SRAM134_RST));
/* Set value and mask for SRAM134_RST option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM134_RST);
optr_reg_mask |= FLASH_OPTR_SRAM134_RST;
}
if ((UserType & OB_USER_IWDG_SW) != 0U)
{
/* IWDG_SW option byte should be modified */
assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
/* Set value and mask for IWDG_SW option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
optr_reg_mask |= FLASH_OPTR_IWDG_SW;
}
if ((UserType & OB_USER_IWDG_STOP) != 0U)
{
/* IWDG_STOP option byte should be modified */
assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
/* Set value and mask for IWDG_STOP option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
}
if ((UserType & OB_USER_IWDG_STDBY) != 0U)
{
/* IWDG_STDBY option byte should be modified */
assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
/* Set value and mask for IWDG_STDBY option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
}
if ((UserType & OB_USER_WWDG_SW) != 0U)
{
/* WWDG_SW option byte should be modified */
assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
/* Set value and mask for WWDG_SW option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
optr_reg_mask |= FLASH_OPTR_WWDG_SW;
}
if ((UserType & OB_USER_SWAP_BANK) != 0U)
{
/* SWAP_BANK option byte should be modified */
assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTR_SWAP_BANK));
/* Set value and mask for SWAP_BANK option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_SWAP_BANK);
optr_reg_mask |= FLASH_OPTR_SWAP_BANK;
}
if ((UserType & OB_USER_DUALBANK) != 0U)
{
/* DUALBANK option byte should be modified */
assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
/* Set value and mask for DUALBANK option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
optr_reg_mask |= FLASH_OPTR_DUALBANK;
}
if ((UserType & OB_USER_BKPRAM_ECC) != 0U)
{
/* BKPRAM_ECC option byte should be modified */
assert_param(IS_OB_USER_BKPRAM_ECC(UserConfig & FLASH_OPTR_BKPRAM_ECC));
/* Set value and mask for BKPRAM_ECC option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_BKPRAM_ECC);
optr_reg_mask |= FLASH_OPTR_BKPRAM_ECC;
}
if ((UserType & OB_USER_SRAM3_ECC) != 0U)
{
/* SRAM3_ECC option byte should be modified */
assert_param(IS_OB_USER_SRAM3_ECC(UserConfig & FLASH_OPTR_SRAM3_ECC));
/* Set value and mask for SRAM3_ECC option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM3_ECC);
optr_reg_mask |= FLASH_OPTR_SRAM3_ECC;
}
if ((UserType & OB_USER_SRAM2_ECC) != 0U)
{
/* SRAM2_ECC option byte should be modified */
assert_param(IS_OB_USER_SRAM2_ECC(UserConfig & FLASH_OPTR_SRAM2_ECC));
/* Set value and mask for SRAM2_ECC option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_ECC);
optr_reg_mask |= FLASH_OPTR_SRAM2_ECC;
}
if ((UserType & OB_USER_SRAM2_RST) != 0U)
{
/* SRAM2_RST option byte should be modified */
assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
/* Set value and mask for SRAM2_RST option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
}
if ((UserType & OB_USER_NSWBOOT0) != 0U)
{
/* nSWBOOT0 option byte should be modified */
assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
/* Set value and mask for nSWBOOT0 option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
}
if ((UserType & OB_USER_NBOOT0) != 0U)
{
/* nBOOT0 option byte should be modified */
assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
/* Set value and mask for nBOOT0 option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
optr_reg_mask |= FLASH_OPTR_nBOOT0;
}
if ((UserType & OB_USER_PA15_PUPEN) != 0U)
{
/* PA15_PUPEN option byte should be modified */
assert_param(IS_OB_USER_PA15_PUPEN(UserConfig & FLASH_OPTR_PA15_PUPEN));
/* Set value and mask for nBOOT0 option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_PA15_PUPEN);
optr_reg_mask |= FLASH_OPTR_PA15_PUPEN;
}
if ((UserType & OB_USER_IO_VDD_HSLV) != 0U)
{
/* IO_VDD_HSLV option byte should be modified */
assert_param(IS_OB_USER_IO_VDD_HSLV(UserConfig & FLASH_OPTR_IO_VDD_HSLV));
/* Set value and mask for IO_VDD_HSLV option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDD_HSLV);
optr_reg_mask |= FLASH_OPTR_IO_VDD_HSLV;
}
if ((UserType & OB_USER_IO_VDDIO2_HSLV) != 0U)
{
/* IO_VDDIO2_HSLV option byte should be modified */
assert_param(IS_OB_USER_IO_VDDIO2_HSLV(UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV));
/* Set value and mask for IO_VDDIO2_HSLV option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV);
optr_reg_mask |= FLASH_OPTR_IO_VDDIO2_HSLV;
}
if ((UserType & OB_USER_TZEN) != 0U)
{
/* TZEN option byte should be modified */
assert_param(IS_OB_USER_TZEN(UserConfig & FLASH_OPTR_TZEN));
/* Set value and mask for TZEN option byte */
optr_reg_val |= (UserConfig & FLASH_OPTR_TZEN);
optr_reg_mask |= FLASH_OPTR_TZEN;
}
/* Configure the option bytes register */
MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Configure the watermarked-based secure area.
*
* @param WMSecConfig specifies the area to be configured.
* This parameter can be a combination of the following values:
* @arg OB_WMSEC_AREA1 or @arg OB_WMSEC_AREA2: Select Flash Secure Area 1 or Area 2
* @arg OB_WMSEC_SECURE_AREA_CONFIG: configure Flash Secure Area
* @arg OB_WMSEC_HDP_AREA_CONFIG: configure Flash secure hide Area
* @arg OB_WMSEC_HDP_AREA_ENABLE: enable secure hide Area in Secure Area
* @arg OB_WMSEC_HDP_AREA_DISABLE: disable secure hide Area in Secure Area
*
* @param WMSecStartPage specifies the start page of the secure area
* This parameter can be page number between 0 and (max number of pages in the bank - 1)
*
* @param WMSecEndPage specifies the end page of the secure area
* This parameter can be page number between WMSecStartPage and (max number of pages in the bank - 1)
*
* @param WMHDPEndPage specifies the end page of the secure hide area
* This parameter can be a page number between WMSecStartPage and WMSecEndPage
*
* @retval None
*/
static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage,
uint32_t WMHDPEndPage)
{
uint32_t tmp_secwm1 = 0U;
uint32_t tmp_secwm2 = 0U;
/* Check the parameters */
assert_param(IS_OB_WMSEC_CONFIG(WMSecConfig));
assert_param(IS_OB_WMSEC_AREA_EXCLUSIVE(WMSecConfig & 0x3U));
assert_param(IS_FLASH_PAGE(WMSecStartPage));
assert_param(IS_FLASH_PAGE(WMSecEndPage));
assert_param(IS_FLASH_PAGE(WMHDPEndPage));
/* Read SECWM registers */
if ((WMSecConfig & OB_WMSEC_AREA1) != 0U)
{
tmp_secwm1 = FLASH->SECWM1R1;
tmp_secwm2 = FLASH->SECWM1R2;
}
else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U)
{
tmp_secwm1 = FLASH->SECWM2R1;
tmp_secwm2 = FLASH->SECWM2R2;
}
else
{
/* Nothing to do */
}
/* Configure Secure Area */
if ((WMSecConfig & OB_WMSEC_SECURE_AREA_CONFIG) != 0U)
{
tmp_secwm1 = ((WMSecEndPage << FLASH_SECWM1R1_SECWM1_PEND_Pos) | WMSecStartPage);
}
/* Configure Secure Hide Area */
if ((WMSecConfig & OB_WMSEC_HDP_AREA_CONFIG) != 0U)
{
tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1_PEND);
tmp_secwm2 |= (WMHDPEndPage << FLASH_SECWM1R2_HDP1_PEND_Pos);
}
/* Enable Secure Hide Area */
if ((WMSecConfig & OB_WMSEC_HDP_AREA_ENABLE) != 0U)
{
tmp_secwm2 |= FLASH_SECWM1R2_HDP1EN;
}
/* Disable Secure Hide Area */
if ((WMSecConfig & OB_WMSEC_HDP_AREA_DISABLE) != 0U)
{
tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1EN);
}
/* Write SECWM registers */
if ((WMSecConfig & OB_WMSEC_AREA1) != 0U)
{
FLASH->SECWM1R1 = tmp_secwm1;
FLASH->SECWM1R2 = tmp_secwm2;
}
else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U)
{
FLASH->SECWM2R1 = tmp_secwm1;
FLASH->SECWM2R2 = tmp_secwm2;
}
else
{
/* Nothing to do */
}
}
/**
* @brief Configure the boot lock.
*
* @param BootLockConfig specifies the activation of the BOOT_LOCK.
* This parameter can be one of the following values:
* @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
* @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
*
* @retval None
*/
static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig)
{
/* Check the parameters */
assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
/* Configure the option bytes register */
MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_BOOT_LOCK, BootLockConfig);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Configure the boot address.
*
* @param BootAddrConfig specifies the area to be configured.
* This parameter can be one of the following values:
* @arg OB_BOOTADDR_NS0: Non-secure boot address 0
* @arg OB_BOOTADDR_NS1: Non-secure boot address 1
* @arg OB_BOOTADDR_SEC0: Secure boot address 0
*
* @param BootAddr: specifies the address used for the boot
* This parameter can be page number between 0 and 0xFFFFFF00
*
* @retval None
*/
static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr)
{
/* Check the parameters */
assert_param(IS_OB_BOOTADDR_CONFIG(BootAddrConfig));
if (BootAddrConfig == OB_BOOTADDR_NS0)
{
FLASH->NSBOOTADD0R = BootAddr;
}
else if (BootAddrConfig == OB_BOOTADDR_NS1)
{
FLASH->NSBOOTADD1R = BootAddr;
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
else if (BootAddrConfig == OB_BOOTADDR_SEC0)
{
MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_SECBOOTADD0, BootAddr);
}
#endif /* __ARM_FEATURE_CMSE */
else
{
/* Empty statement (to be compliant MISRA 15.7) */
}
}
/**
* @brief Return the FLASH Write Protection Option Bytes value.
*
* @param[in] WRPArea specifies the area to be returned.
* This parameter can be one of the following values:
* @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
* @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
* @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A
* @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B
*
* @param[out] WRPStartOffset specifies the address where to copied the start page
* of the write protected area
*
* @param[out] WRPEndOffset specifies the address where to copied the end page of
* the write protected area
*
* @param[out] WRPLock specifies the lock status of the write protected area.
* The returned value can be ENABLE or DISABLE
*
* @retval None
*/
static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset,
FunctionalState *WRPLock)
{
/* Get the configuration of the write protected area */
if (WRPArea == OB_WRPAREA_BANK1_AREAA)
{
*WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PSTRT);
*WRPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PEND) >> FLASH_WRP1AR_WRP1A_PEND_Pos);
*WRPLock = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_UNLOCK) != 0U) ? DISABLE : ENABLE;
}
else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
{
*WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PSTRT);
*WRPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PEND) >> FLASH_WRP1BR_WRP1B_PEND_Pos);
*WRPLock = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_UNLOCK) != 0U) ? DISABLE : ENABLE;
}
else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
{
*WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PSTRT);
*WRPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PEND) >> FLASH_WRP2AR_WRP2A_PEND_Pos);
*WRPLock = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_UNLOCK) != 0U) ? DISABLE : ENABLE;
}
else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
{
*WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PSTRT);
*WRPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PEND) >> FLASH_WRP2BR_WRP2B_PEND_Pos);
*WRPLock = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_UNLOCK) != 0U) ? DISABLE : ENABLE;
}
else
{
/* Empty statement (to be compliant MISRA 15.7) */
}
}
/**
* @brief Return the FLASH Read Protection level.
* @retval FLASH ReadOut Protection Level.
* This return value can be one of the following values:
* @arg OB_RDP_LEVEL_0: No protection
* @arg OB_RDP_LEVEL_0_5: No debug access to secure area
* @arg OB_RDP_LEVEL_1: Read protection of the memory
* @arg OB_RDP_LEVEL_2: Full chip protection
*/
static uint32_t FLASH_OB_GetRDP(void)
{
uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_0_5) && (rdp_level != OB_RDP_LEVEL_2))
{
return (OB_RDP_LEVEL_1);
}
else
{
return rdp_level;
}
}
/**
* @brief Return the FLASH User Option Byte value.
* @retval The FLASH User Option Bytes values.
* The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
* @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
* @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
* @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
* @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
* @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
* @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC,
* @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST,
* @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
* @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV,
* @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN
*/
static uint32_t FLASH_OB_GetUser(void)
{
uint32_t user_config = READ_REG(FLASH->OPTR);
CLEAR_BIT(user_config, FLASH_OPTR_RDP);
return user_config;
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Return the watermarked-based secure area configuration.
*
* @param WMSecConfig [in/out] specifies the area to be returned.
* This parameter can be one of the following values:
* @arg OB_WMSEC_AREA1: select Flash Secure Area 1
* @arg OB_WMSEC_AREA2: select Flash Secure Area 2
* When return from the function, this parameter will be a combinaison of the following values:
* @arg OB_WMSEC_AREAA or @arg OB_WMSEC_AREAB: selected Flash Secure Area A or Area B
* @arg OB_WMSEC_HDP_AREA_ENABLE: Secure Hide Area in Secure Area enabled
* @arg OB_WMSEC_HDP_AREA_DISABLE: Secure Hide Area in Secure Area disabled
*
* @param WMSecStartPage [out] specifies the start page of the secure area
*
* @param WMSecEndPage [out] specifies the end page of the secure area
*
* @param WMHDPEndPage [out] specifies the end page of the secure hide area
*
*
* @retval None
*/
static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage,
uint32_t *WMHDPEndPage)
{
uint32_t tmp_secwm1 = 0U;
uint32_t tmp_secwm2 = 0U;
/* Check the parameters */
assert_param(IS_OB_WMSEC_CONFIG(*WMSecConfig));
assert_param(IS_FLASH_BANK_EXCLUSIVE((*WMSecConfig) & 0x3U));
/* Read SECWM registers */
if (((*WMSecConfig) & OB_WMSEC_AREA1) != 0U)
{
tmp_secwm1 = FLASH->SECWM1R1;
tmp_secwm2 = FLASH->SECWM1R2;
}
else if (((*WMSecConfig) & OB_WMSEC_AREA2) != 0U)
{
tmp_secwm1 = FLASH->SECWM2R1;
tmp_secwm2 = FLASH->SECWM2R2;
}
else
{
/* Empty statement (to be compliant MISRA 15.7) */
}
/* Configuration of secure area */
*WMSecStartPage = (tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PSTRT);
*WMSecEndPage = ((tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PEND) >> FLASH_SECWM1R1_SECWM1_PEND_Pos);
/* Configuration of secure hide area */
*WMHDPEndPage = ((tmp_secwm2 & FLASH_SECWM1R2_HDP1_PEND) >> FLASH_SECWM1R2_HDP1_PEND_Pos);
if ((tmp_secwm2 & FLASH_SECWM1R2_HDP1EN) == 0U)
{
*WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_DISABLE);
}
else
{
*WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_ENABLE);
}
}
/**
* @brief Return the boot lock configuration.
*
* @retval Value of Boot Lock configuration.
* It can be one of the following values:
* @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
* @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
*/
static uint32_t FLASH_OB_GetBootLock(void)
{
return (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_BOOT_LOCK);
}
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Return the boot address.
*
* @param[in] BootAddrConfig specifies the area to be returned.
* This parameter can be one of the following values:
* @arg OB_BOOTADDR_NS0: Non-secure boot address 0
* @arg OB_BOOTADDR_NS1: Non-secure boot address 1
* @arg OB_BOOTADDR_SEC0: Secure boot address 0
*
* @param[out] BootAddr specifies the boot address value
*
* @retval None
*/
static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr)
{
if (BootAddrConfig == OB_BOOTADDR_NS0)
{
*BootAddr = (FLASH->NSBOOTADD0R & FLASH_NSBOOTADD0R_NSBOOTADD0);
}
else if (BootAddrConfig == OB_BOOTADDR_NS1)
{
*BootAddr = (FLASH->NSBOOTADD1R & FLASH_NSBOOTADD1R_NSBOOTADD1);
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
else if (BootAddrConfig == OB_BOOTADDR_SEC0)
{
*BootAddr = (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_SECBOOTADD0);
}
#endif /* __ARM_FEATURE_CMSE */
else
{
/* Empty statement (to be compliant MISRA 15.7) */
}
}
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c
|
C
|
apache-2.0
| 58,667
|
/**
******************************************************************************
* @file stm32u5xx_hal_fmac.c
* @author MCD Application Team
* @brief FMAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FMAC peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
* + Callback functions
* + IRQ handler management
* + Peripheral State and Error functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*
* @verbatim
================================================================================
##### How to use this driver #####
================================================================================
[..]
The FMAC HAL driver can be used as follows:
(#) Initialize the FMAC low level resources by implementing the HAL_FMAC_MspInit():
(++) Enable the FMAC interface clock using __HAL_RCC_FMAC_CLK_ENABLE().
(++) In case of using interrupts (e.g. access configured as FMAC_BUFFER_ACCESS_IT):
(+++) Configure the FMAC interrupt priority using HAL_NVIC_SetPriority().
(+++) Enable the FMAC IRQ handler using HAL_NVIC_EnableIRQ().
(+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler().
(++) In case of using DMA to control data transfer (e.g. access configured
as FMAC_BUFFER_ACCESS_DMA):
(+++) Enable the DMA interface clock using __HAL_RCC_DMA1_CLK_ENABLE()
or __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance.
(+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE().
(+++) If the initialization of the internal buffers (coefficients, input,
output) is done via DMA, configure and enable one DMA channel for
managing data transfer from memory to memory (preload channel).
(+++) If the input buffer is accessed via DMA, configure and enable one
DMA channel for managing data transfer from memory to peripheral
(input channel).
(+++) If the output buffer is accessed via DMA, configure and enable
one DMA channel for managing data transfer from peripheral to
memory (output channel).
(+++) Associate the initialized DMA handle(s) to the FMAC DMA handle(s)
using __HAL_LINKDMA().
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the enabled DMA channel(s) using HAL_NVIC_SetPriority()
and HAL_NVIC_EnableIRQ().
(#) Initialize the FMAC HAL using HAL_FMAC_Init(). This function
resorts to HAL_FMAC_MspInit() for low-level initialization.
(#) Configure the FMAC processing (filter) using HAL_FMAC_FilterConfig()
or HAL_FMAC_FilterConfig_DMA().
This function:
(++) Defines the memory area within the FMAC internal memory
(input, coefficients, output) and the associated threshold (input, output).
(++) Configures the filter and its parameters:
(+++) Finite Impulse Response (FIR) filter (also known as convolution).
(+++) Infinite Impulse Response (IIR) filter (direct form 1).
(++) Choose the way to access to the input and output buffers: none, polling,
DMA, IT. "none" means the input and/or output data will be handled by
another IP (ADC, DAC, etc.).
(++) Enable the error interruptions in the input access and/or the output
access is done through IT/DMA. If an error occurs, the interruption
will be triggered in loop. In order to recover, the user will have
to reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT;
the error status will be kept, but no more interrupt will be triggered.
(++) Write the provided coefficients into the internal memory using polling
mode ( HAL_FMAC_FilterConfig() ) or DMA ( HAL_FMAC_FilterConfig_DMA() ).
In the DMA case, HAL_FMAC_FilterConfigCallback() is called when
the handling is over.
(#) Optionally, the user can enable the error interruption related to
saturation by calling __HAL_FMAC_ENABLE_IT. This helps in debugging the
filter. If a saturation occurs, the interruption will be triggered in loop.
In order to recover, the user will have to:
(++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if
the user wishes to continue all the same.
(++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
(#) Optionally, preload input (FIR, IIR) and output (IIR) data using
HAL_FMAC_FilterPreload() or HAL_FMAC_FilterPreload_DMA().
In the DMA case, HAL_FMAC_FilterPreloadCallback() is called when
the handling is over.
This step is optional as the filter can be started without preloaded
data.
(#) Start the FMAC processing (filter) using HAL_FMAC_FilterStart().
This function also configures the output buffer that will be filled from
the circular internal output buffer. The function returns immediately
without updating the provided buffer. The IP processing will be active until
HAL_FMAC_FilterStop() is called.
(#) If the input internal buffer is accessed via DMA, HAL_FMAC_HalfGetDataCallback()
will be called to indicate that half of the input buffer has been handled.
(#) If the input internal buffer is accessed via DMA or interrupt, HAL_FMAC_GetDataCallback()
will be called to require new input data. It will be provided through
HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode.
(#) If the output internal buffer is accessed via DMA, HAL_FMAC_HalfOutputDataReadyCallback()
will be called to indicate that half of the output buffer has been handled.
(#) If the output internal buffer is accessed via DMA or interrupt,
HAL_FMAC_OutputDataReadyCallback() will be called to require a new output
buffer. It will be provided through HAL_FMAC_ConfigFilterOutputBuffer()
if the DMA isn't in circular mode.
(#) In all modes except none, provide new input data to be processed via HAL_FMAC_AppendFilterData().
This function should only be called once the previous input data has been handled
(the preloaded input data isn't concerned).
(#) In all modes except none, provide a new output buffer to be filled via
HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous
user's output buffer has been filled.
(#) In polling mode, handle the input and output data using HAL_FMAC_PollFilterData().
This function:
(++) Write the user's input data (provided via HAL_FMAC_AppendFilterData())
into the FMAC input memory area.
(++) Read the FMAC output memory area and write it into the user's output buffer.
It will return either when:
(++) the user's output buffer is filled.
(++) the user's input buffer has been handled.
The unused data (unread input data or free output data) will not be saved.
The user will have to use the updated input and output sizes to keep track
of them.
(#) Stop the FMAC processing (filter) using HAL_FMAC_FilterStop().
(#) Call HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function
resorts to HAL_FMAC_MspDeInit() for low-level de-initialization.
##### Callback registration #####
==================================
[..]
The compilation define USE_HAL_FMAC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use Function HAL_FMAC_RegisterCallback() to register a user callback.
Function HAL_FMAC_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : Error Callback.
(+) HalfGetDataCallback : Get Half Data Callback.
(+) GetDataCallback : Get Data Callback.
(+) HalfOutputDataReadyCallback : Half Output Data Ready Callback.
(+) OutputDataReadyCallback : Output Data Ready Callback.
(+) FilterConfigCallback : Filter Configuration Callback.
(+) FilterPreloadCallback : Filter Preload Callback.
(+) MspInitCallback : FMAC MspInit.
(+) MspDeInitCallback : FMAC MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : Error Callback.
(+) HalfGetDataCallback : Get Half Data Callback.
(+) GetDataCallback : Get Data Callback.
(+) HalfOutputDataReadyCallback : Half Output Data Ready Callback.
(+) OutputDataReadyCallback : Output Data Ready Callback.
(+) FilterConfigCallback : Filter Configuration Callback.
(+) FilterPreloadCallback : Filter Preload Callback.
(+) MspInitCallback : FMAC MspInit.
(+) MspDeInitCallback : FMAC MspDeInit.
[..]
By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
examples GetDataCallback(), OutputDataReadyCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the HAL_FMAC_Init()
and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_FMAC_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_FMAC_STATE_READY or HAL_FMAC_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_FMAC_RegisterCallback() before calling HAL_FMAC_DeInit()
or HAL_FMAC_Init() function.
[..]
When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
*
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
#if defined(FMAC)
#ifdef HAL_FMAC_MODULE_ENABLED
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup FMAC FMAC
* @brief FMAC HAL driver module
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup FMAC_Private_Constants FMAC Private Constants
* @{
*/
#define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
#define MAX_PRELOAD_INDEX 0xFFU
#define PRELOAD_ACCESS_DMA 0x00U
#define PRELOAD_ACCESS_POLLING 0x01U
#define POLLING_DISABLED 0U
#define POLLING_ENABLED 1U
#define POLLING_NOT_STOPPED 0U
#define POLLING_STOPPED 1U
/* FMAC polling-based communications time-out value */
#define HAL_FMAC_TIMEOUT_VALUE 1000U
/* FMAC reset time-out value */
#define HAL_FMAC_RESET_TIMEOUT_VALUE 500U
/* DMA Read Requests Enable */
#define FMAC_DMA_REN FMAC_CR_DMAREN
/* DMA Write Channel Enable */
#define FMAC_DMA_WEN FMAC_CR_DMAWEN
/* FMAC Execution Enable */
#define FMAC_START FMAC_PARAM_START
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup FMAC_Private_Macros FMAC Private Macros
* @{
*/
/**
* @brief Get the X1 memory area size.
* @param __HANDLE__ FMAC handle.
* @retval X1_BUF_SIZE
*/
#define FMAC_GET_X1_SIZE(__HANDLE__) \
((((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_X1_BUF_SIZE)) >> (FMAC_X1BUFCFG_X1_BUF_SIZE_Pos))
/**
* @brief Get the X1 watermark.
* @param __HANDLE__ FMAC handle.
* @retval FULL_WM
*/
#define FMAC_GET_X1_FULL_WM(__HANDLE__) \
(((__HANDLE__)->Instance->X1BUFCFG) & (FMAC_X1BUFCFG_FULL_WM))
/**
* @brief Get the X2 memory area size.
* @param __HANDLE__ FMAC handle.
* @retval X2_BUF_SIZE
*/
#define FMAC_GET_X2_SIZE(__HANDLE__) \
((((__HANDLE__)->Instance->X2BUFCFG) & (FMAC_X2BUFCFG_X2_BUF_SIZE)) >> (FMAC_X2BUFCFG_X2_BUF_SIZE_Pos))
/**
* @brief Get the Y memory area size.
* @param __HANDLE__ FMAC handle.
* @retval Y_BUF_SIZE
*/
#define FMAC_GET_Y_SIZE(__HANDLE__) \
((((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_Y_BUF_SIZE)) >> (FMAC_YBUFCFG_Y_BUF_SIZE_Pos))
/**
* @brief Get the Y watermark.
* @param __HANDLE__ FMAC handle.
* @retval EMPTY_WM
*/
#define FMAC_GET_Y_EMPTY_WM(__HANDLE__) \
(((__HANDLE__)->Instance->YBUFCFG) & (FMAC_YBUFCFG_EMPTY_WM))
/**
* @brief Get the start bit state.
* @param __HANDLE__ FMAC handle.
* @retval START
*/
#define FMAC_GET_START_BIT(__HANDLE__) \
((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
/**
* @brief Get the threshold matching the watermark.
* @param __WM__ Watermark value.
* @retval THRESHOLD
*/
#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
((__WM__) == FMAC_THRESHOLD_2)? 2U: \
((__WM__) == FMAC_THRESHOLD_4)? 4U:8U)
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Global variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
uint8_t PreloadAccess);
static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess);
static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size);
static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
uint16_t *pInputSize);
static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
uint16_t *pOutputSize);
static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite);
static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead);
static void FMAC_DMAHalfGetData(DMA_HandleTypeDef *hdma);
static void FMAC_DMAGetData(DMA_HandleTypeDef *hdma);
static void FMAC_DMAHalfOutputDataReady(DMA_HandleTypeDef *hdma);
static void FMAC_DMAOutputDataReady(DMA_HandleTypeDef *hdma);
static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma);
static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma);
static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
/* Functions Definition ------------------------------------------------------*/
/** @defgroup FMAC_Exported_Functions FMAC Exported Functions
* @{
*/
/** @defgroup FMAC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the FMAC peripheral and the associated handle
(+) DeInitialize the FMAC peripheral
(+) Initialize the FMAC MSP (MCU Specific Package)
(+) De-Initialize the FMAC MSP
(+) Register a User FMAC Callback
(+) Unregister a FMAC CallBack
[..]
@endverbatim
* @{
*/
/**
* @brief Initialize the FMAC peripheral and the associated handle.
* @param hfmac pointer to a FMAC_HandleTypeDef structure.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac)
{
HAL_StatusTypeDef status;
/* Check the FMAC handle allocation */
if (hfmac == NULL)
{
return HAL_ERROR;
}
/* Check the instance */
assert_param(IS_FMAC_ALL_INSTANCE(hfmac->Instance));
if (hfmac->State == HAL_FMAC_STATE_RESET)
{
/* Initialize lock resource */
hfmac->Lock = HAL_UNLOCKED;
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
/* Register the default callback functions */
hfmac->ErrorCallback = HAL_FMAC_ErrorCallback;
hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback;
hfmac->GetDataCallback = HAL_FMAC_GetDataCallback;
hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback;
hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback;
hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback;
hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback;
if (hfmac->MspInitCallback == NULL)
{
hfmac->MspInitCallback = HAL_FMAC_MspInit;
}
/* Init the low level hardware */
hfmac->MspInitCallback(hfmac);
#else
/* Init the low level hardware */
HAL_FMAC_MspInit(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
/* Reset pInput and pOutput */
hfmac->FilterParam = 0U;
FMAC_ResetDataPointers(hfmac);
/* Reset FMAC unit (internal pointers) */
if (FMAC_Reset(hfmac) == HAL_ERROR)
{
/* Update FMAC error code and FMAC peripheral state */
hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
status = HAL_ERROR;
}
else
{
/* Update FMAC error code and FMAC peripheral state */
hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
hfmac->State = HAL_FMAC_STATE_READY;
status = HAL_OK;
}
__HAL_UNLOCK(hfmac);
return status;
}
/**
* @brief De-initialize the FMAC peripheral.
* @param hfmac pointer to a FMAC structure.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac)
{
/* Check the FMAC handle allocation */
if (hfmac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_FMAC_ALL_INSTANCE(hfmac->Instance));
/* Change FMAC peripheral state */
hfmac->State = HAL_FMAC_STATE_BUSY;
/* Set FMAC error code to none */
hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
/* Reset pInput and pOutput */
hfmac->FilterParam = 0U;
FMAC_ResetDataPointers(hfmac);
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
if (hfmac->MspDeInitCallback == NULL)
{
hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;
}
/* DeInit the low level hardware */
hfmac->MspDeInitCallback(hfmac);
#else
/* DeInit the low level hardware: CLOCK, NVIC, DMA */
HAL_FMAC_MspDeInit(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
/* Change FMAC peripheral state */
hfmac->State = HAL_FMAC_STATE_RESET;
/* Always release Lock in case of de-initialization */
__HAL_UNLOCK(hfmac);
return HAL_OK;
}
/**
* @brief Initialize the FMAC MSP.
* @param hfmac FMAC handle.
* @retval None
*/
__weak void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfmac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FMAC_MspInit can be implemented in the user file
*/
}
/**
* @brief De-initialize the FMAC MSP.
* @param hfmac FMAC handle.
* @retval None
*/
__weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfmac);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_FMAC_MspDeInit can be implemented in the user file
*/
}
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User FMAC Callback.
* @note The User FMAC Callback is to be used instead of the weak predefined callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param CallbackID ID of the callback to be registered.
* This parameter can be one of the following values:
* @arg @ref HAL_FMAC_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_FMAC_HALF_GET_DATA_CB_ID Get Half Data Callback ID
* @arg @ref HAL_FMAC_GET_DATA_CB_ID Get Data Callback ID
* @arg @ref HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID Half Output Data Ready Callback ID
* @arg @ref HAL_FMAC_OUTPUT_DATA_READY_CB_ID Output Data Ready Callback ID
* @arg @ref HAL_FMAC_FILTER_CONFIG_CB_ID Filter Configuration Callback ID
* @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
* @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
* @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
* @param pCallback pointer to the Callback function.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
pFMAC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the FMAC handle allocation */
if (hfmac == NULL)
{
return HAL_ERROR;
}
if (pCallback == NULL)
{
/* Update the error code */
hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
__HAL_LOCK(hfmac);
if (hfmac->State == HAL_FMAC_STATE_READY)
{
switch (CallbackID)
{
case HAL_FMAC_ERROR_CB_ID :
hfmac->ErrorCallback = pCallback;
break;
case HAL_FMAC_HALF_GET_DATA_CB_ID :
hfmac->HalfGetDataCallback = pCallback;
break;
case HAL_FMAC_GET_DATA_CB_ID :
hfmac->GetDataCallback = pCallback;
break;
case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
hfmac->HalfOutputDataReadyCallback = pCallback;
break;
case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
hfmac->OutputDataReadyCallback = pCallback;
break;
case HAL_FMAC_FILTER_CONFIG_CB_ID :
hfmac->FilterConfigCallback = pCallback;
break;
case HAL_FMAC_FILTER_PRELOAD_CB_ID :
hfmac->FilterPreloadCallback = pCallback;
break;
case HAL_FMAC_MSPINIT_CB_ID :
hfmac->MspInitCallback = pCallback;
break;
case HAL_FMAC_MSPDEINIT_CB_ID :
hfmac->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hfmac->State == HAL_FMAC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_FMAC_MSPINIT_CB_ID :
hfmac->MspInitCallback = pCallback;
break;
case HAL_FMAC_MSPDEINIT_CB_ID :
hfmac->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
__HAL_UNLOCK(hfmac);
return status;
}
/**
* @brief Unregister a FMAC CallBack.
* @note The FMAC callback is redirected to the weak predefined callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module
* @param CallbackID ID of the callback to be unregistered.
* This parameter can be one of the following values:
* @arg @ref HAL_FMAC_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_FMAC_HALF_GET_DATA_CB_ID Get Half Data Callback ID
* @arg @ref HAL_FMAC_GET_DATA_CB_ID Get Data Callback ID
* @arg @ref HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID Half Output Data Ready Callback ID
* @arg @ref HAL_FMAC_OUTPUT_DATA_READY_CB_ID Output Data Ready Callback ID
* @arg @ref HAL_FMAC_FILTER_CONFIG_CB_ID Filter Configuration Callback ID
* @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
* @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
* @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the FMAC handle allocation */
if (hfmac == NULL)
{
return HAL_ERROR;
}
__HAL_LOCK(hfmac);
if (hfmac->State == HAL_FMAC_STATE_READY)
{
switch (CallbackID)
{
case HAL_FMAC_ERROR_CB_ID :
hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_FMAC_HALF_GET_DATA_CB_ID :
hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */
break;
case HAL_FMAC_GET_DATA_CB_ID :
hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */
break;
case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak
HalfOutputDataReadyCallback */
break;
case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak
OutputDataReadyCallback */
break;
case HAL_FMAC_FILTER_CONFIG_CB_ID :
hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak
FilterConfigCallback */
break;
case HAL_FMAC_FILTER_PRELOAD_CB_ID :
hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallba */
break;
case HAL_FMAC_MSPINIT_CB_ID :
hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_FMAC_MSPDEINIT_CB_ID :
hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
/* Update the error code */
hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hfmac->State == HAL_FMAC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_FMAC_MSPINIT_CB_ID :
hfmac->MspInitCallback = HAL_FMAC_MspInit;
break;
case HAL_FMAC_MSPDEINIT_CB_ID :
hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;
break;
default :
/* Update the error code */
hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hfmac->ErrorCode |= HAL_FMAC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
__HAL_UNLOCK(hfmac);
return status;
}
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup FMAC_Exported_Functions_Group2 Peripheral Control functions
* @brief Control functions.
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Configure the FMAC peripheral: memory area, filter type and parameters,
way to access to the input and output memory area (none, polling, IT, DMA).
(+) Start the FMAC processing (filter).
(+) Handle the input data that will be provided into FMAC.
(+) Handle the output data provided by FMAC.
(+) Stop the FMAC processing (filter).
@endverbatim
* @{
*/
/**
* @brief Configure the FMAC filter.
* @note The configuration is done according to the parameters
* specified in the FMAC_FilterConfigTypeDef structure.
* The provided data will be loaded using polling mode.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
* contains the FMAC configuration information.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
{
return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_POLLING));
}
/**
* @brief Configure the FMAC filter.
* @note The configuration is done according to the parameters
* specified in the FMAC_FilterConfigTypeDef structure.
* The provided data will be loaded using DMA.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
* contains the FMAC configuration information.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
{
return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_DMA));
}
/**
* @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
* @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
* The provided data will be loaded using polling mode.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput Preloading of the first elements of the input buffer (X1).
* If not needed (no data available when starting), it should be set to NULL.
* @param InputSize Size of the input vector.
* As pInput is used for preloading data, it cannot be bigger than the input memory area.
* @param pOutput [IIR] Preloading of the first elements of the output vector (Y).
* If not needed, it should be set to NULL.
* @param OutputSize Size of the output vector.
* As pOutput is used for preloading data, it cannot be bigger than the output memory area.
* @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
* (each call filling partly the buffers). In case of overflow (too much data provided through
* all these calls), an error will be returned.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize)
{
return (FMAC_FilterPreload(hfmac, pInput, InputSize, pOutput, OutputSize, PRELOAD_ACCESS_POLLING));
}
/**
* @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
* @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
* The provided data will be loaded using DMA.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput Preloading of the first elements of the input buffer (X1).
* If not needed (no data available when starting), it should be set to NULL.
* @param InputSize Size of the input vector.
* As pInput is used for preloading data, it cannot be bigger than the input memory area.
* @param pOutput [IIR] Preloading of the first elements of the output vector (Y).
* If not needed, it should be set to NULL.
* @param OutputSize Size of the output vector.
* As pOutput is used for preloading data, it cannot be bigger than the output memory area.
* @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
* (each call filling partly the buffers). In case of overflow (too much data provided through
* all these calls), an error will be returned.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize)
{
return (FMAC_FilterPreload(hfmac, pInput, InputSize, pOutput, OutputSize, PRELOAD_ACCESS_DMA));
}
/**
* @brief Start the FMAC processing according to the existing FMAC configuration.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pOutput pointer to buffer where output data of FMAC processing will be stored
* in the next steps.
* If it is set to NULL, the output will not be read and it will be up to
* an external IP to empty the output buffer.
* @param pOutputSize pointer to the size of the output buffer. The number of read data will be written here.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
{
uint32_t tmpcr = 0U;
HAL_StatusTypeDef status;
/* Check the START bit state */
if (FMAC_GET_START_BIT(hfmac) != 0U)
{
return HAL_ERROR;
}
/* Check that a valid configuration was done previously */
if (hfmac->FilterParam == 0U)
{
return HAL_ERROR;
}
/* Check handle state is ready */
if (hfmac->State == HAL_FMAC_STATE_READY)
{
/* Change the FMAC state */
hfmac->State = HAL_FMAC_STATE_BUSY;
/* CR: Configure the input access (error interruptions enabled only for IT or DMA) */
if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA)
{
tmpcr |= FMAC_DMA_WEN;
}
else if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_IT)
{
tmpcr |= FMAC_IT_WIEN;
}
else
{
/* nothing to do */
}
/* CR: Configure the output access (error interruptions enabled only for IT or DMA) */
if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA)
{
tmpcr |= FMAC_DMA_REN;
}
else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT)
{
tmpcr |= FMAC_IT_RIEN;
}
else
{
/* nothing to do */
}
/* CR: Write the configuration */
MODIFY_REG(hfmac->Instance->CR, \
FMAC_IT_RIEN | FMAC_IT_WIEN | FMAC_DMA_REN | FMAC_CR_DMAWEN, \
tmpcr);
/* Register the new output buffer */
status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize);
if (status == HAL_OK)
{
/* PARAM: Start the filter ( this can generate interrupts before the end of the HAL_FMAC_FilterStart ) */
WRITE_REG(hfmac->Instance->PARAM, (uint32_t)(hfmac->FilterParam));
}
/* Reset the busy flag (do not overwrite the possible write and read flag) */
hfmac->State = HAL_FMAC_STATE_READY;
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Provide a new input buffer that will be loaded into the FMAC input memory area.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput New input vector (additional input data).
* @param pInputSize Size of the input vector (if all the data can't be
* written, it will be updated with the number of data read from FMAC).
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
{
HAL_StatusTypeDef status;
/* Check the function parameters */
if ((pInput == NULL) || (pInputSize == NULL))
{
return HAL_ERROR;
}
if (*pInputSize == 0U)
{
return HAL_ERROR;
}
/* Check the START bit state */
if (FMAC_GET_START_BIT(hfmac) == 0U)
{
return HAL_ERROR;
}
/* Check the FMAC configuration */
if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_NONE)
{
return HAL_ERROR;
}
/* Check whether the previous input vector has been handled */
if ((hfmac->pInputSize != NULL) && (hfmac->InputCurrentSize < * (hfmac->pInputSize)))
{
return HAL_ERROR;
}
/* Check that FMAC was initialized and that no writing is already ongoing */
if (hfmac->WrState == HAL_FMAC_STATE_READY)
{
/* Register the new input buffer */
status = FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize);
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Provide a new output buffer to be filled with the data computed by FMAC unit.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pOutput New output vector.
* @param pOutputSize Size of the output vector (if the vector can't
* be entirely filled, pOutputSize will be updated with the number
* of data read from FMAC).
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
{
HAL_StatusTypeDef status;
/* Check the function parameters */
if ((pOutput == NULL) || (pOutputSize == NULL))
{
return HAL_ERROR;
}
if (*pOutputSize == 0U)
{
return HAL_ERROR;
}
/* Check the START bit state */
if (FMAC_GET_START_BIT(hfmac) == 0U)
{
return HAL_ERROR;
}
/* Check the FMAC configuration */
if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
{
return HAL_ERROR;
}
/* Check whether the previous output vector has been handled */
if ((hfmac->pOutputSize != NULL) && (hfmac->OutputCurrentSize < * (hfmac->pOutputSize)))
{
return HAL_ERROR;
}
/* Check that FMAC was initialized and that not reading is already ongoing */
if (hfmac->RdState == HAL_FMAC_STATE_READY)
{
/* Register the new output buffer */
status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize);
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Handle the input and/or output data in polling mode
* @note This function writes the previously provided user's input data and
* fills the previously provided user's output buffer,
* according to the existing FMAC configuration (polling mode only).
* The function returns when the input data has been handled or
* when the output data is filled. The possible unused data isn't
* kept. It will be up to the user to handle it. The previously
* provided pInputSize and pOutputSize will be used to indicate to the
* size of the read/written data to the user.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param Timeout timeout value.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout)
{
uint32_t tickstart;
uint8_t inpolling;
uint8_t inpollingover = POLLING_NOT_STOPPED;
uint8_t outpolling;
uint8_t outpollingover = POLLING_NOT_STOPPED;
HAL_StatusTypeDef status;
/* Check the START bit state */
if (FMAC_GET_START_BIT(hfmac) == 0U)
{
return HAL_ERROR;
}
/* Check the configuration */
/* Get the input and output mode (if no buffer was previously provided, nothing will be read/written) */
if ((hfmac->InputAccess == FMAC_BUFFER_ACCESS_POLLING) && (hfmac->pInput != NULL))
{
inpolling = POLLING_ENABLED;
}
else
{
inpolling = POLLING_DISABLED;
}
if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_POLLING) && (hfmac->pOutput != NULL))
{
outpolling = POLLING_ENABLED;
}
else
{
outpolling = POLLING_DISABLED;
}
/* Check the configuration */
if ((inpolling == POLLING_DISABLED) && (outpolling == POLLING_DISABLED))
{
return HAL_ERROR;
}
/* Check handle state is ready */
if (hfmac->State == HAL_FMAC_STATE_READY)
{
/* Change the FMAC state */
hfmac->State = HAL_FMAC_STATE_BUSY;
/* Get tick */
tickstart = HAL_GetTick();
/* Loop on reading and writing until timeout */
while ((HAL_GetTick() - tickstart) < Timeout)
{
/* X1: Check the mode: polling or none */
if (inpolling != POLLING_DISABLED)
{
FMAC_WriteDataIncrementPtr(hfmac, MAX_FILTER_DATA_SIZE_TO_HANDLE);
if (hfmac->InputCurrentSize == *(hfmac->pInputSize))
{
inpollingover = POLLING_STOPPED;
}
}
/* Y: Check the mode: polling or none */
if (outpolling != POLLING_DISABLED)
{
FMAC_ReadDataIncrementPtr(hfmac, MAX_FILTER_DATA_SIZE_TO_HANDLE);
if (hfmac->OutputCurrentSize == *(hfmac->pOutputSize))
{
outpollingover = POLLING_STOPPED;
}
}
/* Exit if there isn't data to handle anymore on one side or another */
if ((inpollingover != POLLING_NOT_STOPPED) || (outpollingover != POLLING_NOT_STOPPED))
{
break;
}
}
/* Change the FMAC state; update the input and output sizes; reset the indexes */
if (inpolling != POLLING_DISABLED)
{
(*(hfmac->pInputSize)) = hfmac->InputCurrentSize;
FMAC_ResetInputStateAndDataPointers(hfmac);
}
if (outpolling != POLLING_DISABLED)
{
(*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize;
FMAC_ResetOutputStateAndDataPointers(hfmac);
}
/* Reset the busy flag (do not overwrite the possible write and read flag) */
hfmac->State = HAL_FMAC_STATE_READY;
if ((HAL_GetTick() - tickstart) >= Timeout)
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
status = HAL_ERROR;
}
else
{
status = HAL_OK;
}
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Stop the FMAC processing.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac)
{
HAL_StatusTypeDef status;
/* Check handle state is ready */
if (hfmac->State == HAL_FMAC_STATE_READY)
{
/* Change the FMAC state */
hfmac->State = HAL_FMAC_STATE_BUSY;
/* Set the START bit to 0 (stop the previously configured filter) */
CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START);
/* Disable the interrupts in order to avoid crossing cases */
CLEAR_BIT(hfmac->Instance->CR, FMAC_DMA_REN | FMAC_DMA_WEN | FMAC_IT_RIEN | FMAC_IT_WIEN);
/* In case of IT, update the sizes */
if ((hfmac->InputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pInput != NULL))
{
(*(hfmac->pInputSize)) = hfmac->InputCurrentSize;
}
if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL))
{
(*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize;
}
/* Reset FMAC unit (internal pointers) */
if (FMAC_Reset(hfmac) == HAL_ERROR)
{
/* Update FMAC error code and FMAC peripheral state */
hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
status = HAL_ERROR;
}
else
{
/* Reset the data pointers */
FMAC_ResetDataPointers(hfmac);
status = HAL_OK;
}
/* Reset the busy flag */
hfmac->State = HAL_FMAC_STATE_READY;
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @}
*/
/** @defgroup FMAC_Exported_Functions_Group3 Callback functions
* @brief Callback functions.
*
@verbatim
==============================================================================
##### Callback functions #####
==============================================================================
[..] This section provides Interruption and DMA callback functions:
(+) DMA or Interrupt: the user's input data is half written (DMA only)
or completely written.
(+) DMA or Interrupt: the user's output buffer is half filled (DMA only)
or completely filled.
(+) DMA or Interrupt: error handling.
@endverbatim
* @{
*/
/**
* @brief FMAC error callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @retval None
*/
__weak void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfmac);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_FMAC_ErrorCallback can be implemented in the user file.
*/
}
/**
* @brief FMAC get half data callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @retval None
*/
__weak void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfmac);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_FMAC_HalfGetDataCallback can be implemented in the user file.
*/
}
/**
* @brief FMAC get data callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @retval None
*/
__weak void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfmac);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_FMAC_GetDataCallback can be implemented in the user file.
*/
}
/**
* @brief FMAC half output data ready callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @retval None
*/
__weak void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfmac);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_FMAC_HalfOutputDataReadyCallback can be implemented in the user file.
*/
}
/**
* @brief FMAC output data ready callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @retval None
*/
__weak void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfmac);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_FMAC_OutputDataReadyCallback can be implemented in the user file.
*/
}
/**
* @brief FMAC filter configuration callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @retval None
*/
__weak void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfmac);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_FMAC_FilterConfigCallback can be implemented in the user file.
*/
}
/**
* @brief FMAC filter preload callback.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @retval None
*/
__weak void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfmac);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_FMAC_FilterPreloadCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup FMAC_Exported_Functions_Group4 IRQ handler management
* @brief IRQ handler.
*
@verbatim
==============================================================================
##### IRQ handler management #####
==============================================================================
[..] This section provides IRQ handler function.
@endverbatim
* @{
*/
/**
* @brief Handle FMAC interrupt request.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @retval None
*/
void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac)
{
uint32_t itsource;
/* Check if the read interrupt is enabled and if Y buffer empty flag isn't set */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_RIEN);
if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0U))
{
/* Read some data if possible (Y size is used as a pseudo timeout in order
to not get stuck too long under IT if FMAC keeps on processing input
data reloaded via DMA for instance). */
if (hfmac->pOutput != NULL)
{
FMAC_ReadDataIncrementPtr(hfmac, (uint16_t)FMAC_GET_Y_SIZE(hfmac));
}
/* Indicate that data is ready to be read */
if ((hfmac->pOutput == NULL) || (hfmac->OutputCurrentSize == *(hfmac->pOutputSize)))
{
/* Reset the pointers to indicate new data will be needed */
FMAC_ResetOutputStateAndDataPointers(hfmac);
/* Call the output data ready callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->OutputDataReadyCallback(hfmac);
#else
HAL_FMAC_OutputDataReadyCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
}
/* Check if the write interrupt is enabled and if X1 buffer full flag isn't set */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_WIEN);
if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0U))
{
/* Write some data if possible (X1 size is used as a pseudo timeout in order
to not get stuck too long under IT if FMAC keep on processing input
data whereas its output emptied via DMA for instance). */
if (hfmac->pInput != NULL)
{
FMAC_WriteDataIncrementPtr(hfmac, (uint16_t)FMAC_GET_X1_SIZE(hfmac));
}
/* Indicate that new data will be needed */
if ((hfmac->pInput == NULL) || (hfmac->InputCurrentSize == *(hfmac->pInputSize)))
{
/* Reset the pointers to indicate new data will be needed */
FMAC_ResetInputStateAndDataPointers(hfmac);
/* Call the get data callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->GetDataCallback(hfmac);
#else
HAL_FMAC_GetDataCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
}
/* Check if the overflow error interrupt is enabled and if overflow error flag is raised */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_OVFLIEN);
if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0U))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
}
/* Check if the underflow error interrupt is enabled and if underflow error flag is raised */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_UNFLIEN);
if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0U))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
}
/* Check if the saturation error interrupt is enabled and if saturation error flag is raised */
itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_SATIEN);
if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0U))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
}
/* Call the error callback if an error occurred */
if (hfmac->ErrorCode != HAL_FMAC_ERROR_NONE)
{
/* Call the error callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->ErrorCallback(hfmac);
#else
HAL_FMAC_ErrorCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
}
/**
* @}
*/
/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State and Error functions
* @brief Peripheral State and Error functions.
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
==============================================================================
[..] This subsection provides functions allowing to
(+) Check the FMAC state
(+) Get error code
@endverbatim
* @{
*/
/**
* @brief Return the FMAC state.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @retval HAL_FMAC_StateTypeDef FMAC state
*/
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac)
{
/* Return FMAC state */
return hfmac->State;
}
/**
* @brief Return the FMAC peripheral error.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @note The returned error is a bit-map combination of possible errors.
* @retval uint32_t Error bit-map based on @ref FMAC_Error_Code
*/
uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac)
{
/* Return FMAC error code */
return hfmac->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup FMAC_Private_Functions FMAC Private Functions
* @{
*/
/**
==============================================================================
##### FMAC Private Functions #####
==============================================================================
*/
/**
* @brief Perform a reset of the FMAC unit.
* @param hfmac FMAC handle.
* @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac)
{
uint32_t tickstart;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Perform the reset */
SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET);
/* Wait until flag is reset */
while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U)
{
if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE)
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
return HAL_OK;
}
/**
* @brief Reset the data pointers of the FMAC unit.
* @param hfmac FMAC handle.
* @retval None
*/
static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac)
{
FMAC_ResetInputStateAndDataPointers(hfmac);
FMAC_ResetOutputStateAndDataPointers(hfmac);
}
/**
* @brief Reset the input data pointers of the FMAC unit.
* @param hfmac FMAC handle.
* @retval None
*/
static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
{
hfmac->pInput = NULL;
hfmac->pInputSize = NULL;
hfmac->InputCurrentSize = 0U;
hfmac->WrState = HAL_FMAC_STATE_READY;
}
/**
* @brief Reset the output data pointers of the FMAC unit.
* @param hfmac FMAC handle.
* @retval None
*/
static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
{
hfmac->pOutput = NULL;
hfmac->pOutputSize = NULL;
hfmac->OutputCurrentSize = 0U;
hfmac->RdState = HAL_FMAC_STATE_READY;
}
/**
* @brief Configure the FMAC filter.
* @note The configuration is done according to the parameters
* specified in the FMAC_FilterConfigTypeDef structure.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that
* contains the FMAC configuration information.
* @param PreloadAccess access mode used for the preload (polling or DMA).
* @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
uint8_t PreloadAccess)
{
uint32_t tickstart;
uint32_t tmpcr;
HAL_StatusTypeDef status;
#if defined(USE_FULL_ASSERT)
uint32_t x2size;
#endif /* USE_FULL_ASSERT */
/* Check the parameters */
assert_param(IS_FMAC_THRESHOLD(pConfig->InputThreshold));
assert_param(IS_FMAC_THRESHOLD(pConfig->OutputThreshold));
assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->InputAccess));
assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->OutputAccess));
assert_param(IS_FMAC_CLIP_STATE(pConfig->Clip));
assert_param(IS_FMAC_FILTER_FUNCTION(pConfig->Filter));
assert_param(IS_FMAC_PARAM_P(pConfig->Filter, pConfig->P));
assert_param(IS_FMAC_PARAM_Q(pConfig->Filter, pConfig->Q));
assert_param(IS_FMAC_PARAM_R(pConfig->Filter, pConfig->R));
/* Check the START bit state */
if (FMAC_GET_START_BIT(hfmac) != 0U)
{
return HAL_ERROR;
}
/* Check handle state is ready */
if (hfmac->State != HAL_FMAC_STATE_READY)
{
return HAL_ERROR;
}
/* Change the FMAC state */
hfmac->State = HAL_FMAC_STATE_BUSY;
/* Get tick */
tickstart = HAL_GetTick();
/* Indicate that there is no valid configuration done */
hfmac->FilterParam = 0U;
/* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */
if (pConfig->InputBufferSize != 0U)
{
MODIFY_REG(hfmac->Instance->X1BUFCFG, \
(FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \
(((((uint32_t)(pConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \
((((uint32_t)(pConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & \
FMAC_X1BUFCFG_X1_BUF_SIZE)));
}
/* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
if (pConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE)
{
/* Check the parameter */
assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), pConfig->InputThreshold, pConfig->InputAccess));
MODIFY_REG(hfmac->Instance->X1BUFCFG, \
FMAC_X1BUFCFG_FULL_WM, \
((pConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM));
}
/* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */
if (pConfig->CoeffBufferSize != 0U)
{
MODIFY_REG(hfmac->Instance->X2BUFCFG, \
(FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \
(((((uint32_t)(pConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \
((((uint32_t)(pConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) &\
FMAC_X2BUFCFG_X2_BUF_SIZE)));
}
/* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
if (pConfig->OutputBufferSize != 0U)
{
MODIFY_REG(hfmac->Instance->YBUFCFG, \
(FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \
(((((uint32_t)(pConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \
((((uint32_t)(pConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE)));
}
/* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */
if (pConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE)
{
/* Check the parameter */
assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), pConfig->OutputThreshold, pConfig->OutputAccess));
MODIFY_REG(hfmac->Instance->YBUFCFG, \
FMAC_YBUFCFG_EMPTY_WM, \
((pConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM));
}
/* FMAC_CR: Configure the clip feature */
tmpcr = pConfig->Clip & FMAC_CR_CLIPEN;
/* FMAC_CR: If IT or DMA will be used, enable error interrupts.
* Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */
if ((pConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) ||
(pConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT))
{
tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN;
}
/* FMAC_CR: write the value */
WRITE_REG(hfmac->Instance->CR, tmpcr);
/* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */
hfmac->InputAccess = pConfig->InputAccess;
hfmac->OutputAccess = pConfig->OutputAccess;
/* Check whether the configured X2 is big enough for the filter */
#if defined(USE_FULL_ASSERT)
x2size = FMAC_GET_X2_SIZE(hfmac);
#endif /* USE_FULL_ASSERT */
assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= pConfig->P)) || \
((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
(x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q))));
/* Build the PARAM value that will be used when starting the filter */
hfmac->FilterParam = (FMAC_PARAM_START | pConfig->Filter | \
((((uint32_t)(pConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \
((((uint32_t)(pConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \
((((uint32_t)(pConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R));
/* Initialize the coefficient buffer if required (pCoeffA for FIR only) */
if ((pConfig->pCoeffB != NULL) && (pConfig->CoeffBSize != 0U))
{
/* FIR/IIR: The provided coefficients should match X2 size */
assert_param(((uint32_t)pConfig->CoeffASize + (uint32_t)pConfig->CoeffBSize) <= x2size);
/* FIR/IIR: The size of pCoeffB should match the parameter P */
assert_param(pConfig->CoeffBSize >= pConfig->P);
/* pCoeffA should be provided for IIR but not for FIR */
/* IIR : if pCoeffB is provided, pCoeffA should also be there */
/* IIR: The size of pCoeffA should match the parameter Q */
assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) &&
(pConfig->pCoeffA == NULL) && (pConfig->CoeffASize == 0U)) ||
((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) &&
(pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U) &&
(pConfig->CoeffASize >= pConfig->Q)));
/* Write number of values to be loaded, the data load function and start the operation */
WRITE_REG(hfmac->Instance->PARAM, \
(((uint32_t)(pConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \
((uint32_t)(pConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \
FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START));
if (PreloadAccess == PRELOAD_ACCESS_POLLING)
{
/* Load the buffer into the internal memory */
FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffB), pConfig->CoeffBSize);
/* Load pCoeffA if needed */
if ((pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U))
{
/* Load the buffer into the internal memory */
FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffA), pConfig->CoeffASize);
}
/* Wait for the end of the writing */
if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
return HAL_ERROR;
}
/* Change the FMAC state */
hfmac->State = HAL_FMAC_STATE_READY;
}
else
{
hfmac->pInput = pConfig->pCoeffA;
hfmac->InputCurrentSize = pConfig->CoeffASize;
/* Set the FMAC DMA transfer complete callback */
hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
/* Set the DMA error callback */
hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
/* Enable the DMA stream managing FMAC preload data write */
if ((hfmac->hdmaPreload->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hfmac->hdmaPreload->LinkedListQueue != NULL) && (hfmac->hdmaPreload->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
(uint32_t)(2UL * pConfig->CoeffBSize); /* Set DMA data size */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)pConfig->pCoeffB; /* Set DMA source address */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pConfig->pCoeffB, \
(uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * pConfig->CoeffBSize));
}
if (status != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
}
}
else
{
/* Change the FMAC state */
hfmac->State = HAL_FMAC_STATE_READY;
}
return HAL_OK;
}
/**
* @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
* @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput Preloading of the first elements of the input buffer (X1).
* If not needed (no data available when starting), it should be set to NULL.
* @param InputSize Size of the input vector.
* As pInput is used for preloading data, it cannot be bigger than the input memory area.
* @param pOutput [IIR] Preloading of the first elements of the output vector (Y).
* If not needed, it should be set to NULL.
* @param OutputSize Size of the output vector.
* As pOutput is used for preloading data, it cannot be bigger than the output memory area.
* @param PreloadAccess access mode used for the preload (polling or DMA).
* @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
* (each call filling partly the buffers). In case of overflow (too much data provided through
* all these calls), an error will be returned.
* @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess)
{
uint32_t tickstart;
HAL_StatusTypeDef status;
/* Check the START bit state */
if (FMAC_GET_START_BIT(hfmac) != 0U)
{
return HAL_ERROR;
}
/* Check that a valid configuration was done previously */
if (hfmac->FilterParam == 0U)
{
return HAL_ERROR;
}
/* Check the preload input buffers isn't too big */
if ((InputSize > FMAC_GET_X1_SIZE(hfmac)) && (pInput != NULL))
{
return HAL_ERROR;
}
/* Check the preload output buffer isn't too big */
if ((OutputSize > FMAC_GET_Y_SIZE(hfmac)) && (pOutput != NULL))
{
return HAL_ERROR;
}
/* Check handle state is ready */
if (hfmac->State != HAL_FMAC_STATE_READY)
{
return HAL_ERROR;
}
/* Change the FMAC state */
hfmac->State = HAL_FMAC_STATE_BUSY;
/* Get tick */
tickstart = HAL_GetTick();
/* Preload the input buffer if required */
if ((pInput != NULL) && (InputSize != 0U))
{
/* Write number of values to be loaded, the data load function and start the operation */
WRITE_REG(hfmac->Instance->PARAM, \
(((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START));
if (PreloadAccess == PRELOAD_ACCESS_POLLING)
{
/* Load the buffer into the internal memory */
FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize);
/* Wait for the end of the writing */
if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
return HAL_ERROR;
}
}
else
{
hfmac->pInput = pOutput;
hfmac->InputCurrentSize = OutputSize;
/* Set the FMAC DMA transfer complete callback */
hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
/* Set the DMA error callback */
hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
/* Enable the DMA stream managing FMAC preload data write */
if ((hfmac->hdmaPreload->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hfmac->hdmaPreload->LinkedListQueue != NULL) && (hfmac->hdmaPreload->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
(uint32_t)(2UL * InputSize); /* Set DMA data size */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)pInput; /* Set DMA source address */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, \
(uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * InputSize));
}
if (status != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
}
}
/* Preload the output buffer if required */
if ((pOutput != NULL) && (OutputSize != 0U))
{
/* Write number of values to be loaded, the data load function and start the operation */
WRITE_REG(hfmac->Instance->PARAM, \
(((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
if (PreloadAccess == PRELOAD_ACCESS_POLLING)
{
/* Load the buffer into the internal memory */
FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize);
/* Wait for the end of the writing */
if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
return HAL_ERROR;
}
}
else
{
hfmac->pInput = NULL;
hfmac->InputCurrentSize = 0U;
/* Set the FMAC DMA transfer complete callback */
hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
/* Set the DMA error callback */
hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
/* Enable the DMA stream managing FMAC preload data write */
if ((hfmac->hdmaPreload->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hfmac->hdmaPreload->LinkedListQueue != NULL) && (hfmac->hdmaPreload->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
(uint32_t)(2UL * OutputSize); /* Set DMA data size */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)pOutput; /* Set DMA source address */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, \
(uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * OutputSize));
}
if (status != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
}
}
/* Update the error codes */
if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
}
if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
}
if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT))
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
}
/* Change the FMAC state */
hfmac->State = HAL_FMAC_STATE_READY;
/* Return function status */
if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
{
status = HAL_OK;
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Write data into FMAC internal memory through WDATA and increment input buffer pointer.
* @note This function is only used with preload functions.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param ppData pointer to pointer to the data buffer.
* @param Size size of the data buffer.
* @retval None
*/
static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size)
{
uint8_t index;
/* Load the buffer into the internal memory */
for (index = Size; index > 0U; index--)
{
WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(*ppData))) & FMAC_WDATA_WDATA));
(*ppData)++;
}
}
/**
* @brief Handle FMAC Function Timeout.
* @param hfmac FMAC handle.
* @param Tickstart Tick start value.
* @param Timeout Timeout duration.
* @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag changes */
while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
{
if ((HAL_GetTick() - Tickstart) > Timeout)
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief Register the new input buffer, update DMA configuration if needed and change the FMAC state.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pInput New input vector (additional input data).
* @param pInputSize Size of the input vector (if all the data can't be
* written, it will be updated with the number of data read from FMAC).
* @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
uint16_t *pInputSize)
{
HAL_StatusTypeDef status;
/* Change the FMAC state */
hfmac->WrState = HAL_FMAC_STATE_BUSY_WR;
/* Reset the current size */
hfmac->InputCurrentSize = 0U;
/* Handle the pointer depending on the input access */
if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA)
{
hfmac->pInput = NULL;
hfmac->pInputSize = NULL;
/* Set the FMAC DMA transfer complete callback */
hfmac->hdmaIn->XferHalfCpltCallback = FMAC_DMAHalfGetData;
hfmac->hdmaIn->XferCpltCallback = FMAC_DMAGetData;
/* Set the DMA error callback */
hfmac->hdmaIn->XferErrorCallback = FMAC_DMAError;
/* Enable the DMA stream managing FMAC input data write */
if ((hfmac->hdmaIn->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hfmac->hdmaIn->LinkedListQueue != NULL) && (hfmac->hdmaIn->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hfmac->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
(uint32_t)(2UL * (*pInputSize)); /* Set DMA data size */
hfmac->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)pInput; /* Set DMA source address */
hfmac->hdmaIn->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hfmac->Instance->WDATA;/* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hfmac->hdmaIn);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hfmac->hdmaIn, (uint32_t)pInput, \
(uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * (*pInputSize)));
}
if (status != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
/* Update the input data information (polling, IT) */
hfmac->pInput = pInput;
hfmac->pInputSize = pInputSize;
}
return HAL_OK;
}
/**
* @brief Register the new output buffer, update DMA configuration if needed and change the FMAC state.
* @param hfmac pointer to a FMAC_HandleTypeDef structure that contains
* the configuration information for FMAC module.
* @param pOutput New output vector.
* @param pOutputSize Size of the output vector (if the vector can't
* be entirely filled, pOutputSize will be updated with the number
* of data read from FMAC).
* @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
uint16_t *pOutputSize)
{
HAL_StatusTypeDef status;
/* Reset the current size */
hfmac->OutputCurrentSize = 0U;
/* Check whether a valid pointer was provided */
if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0U))
{
/* The user will have to provide a valid configuration later */
hfmac->pOutput = NULL;
hfmac->pOutputSize = NULL;
hfmac->RdState = HAL_FMAC_STATE_READY;
}
/* Handle the pointer depending on the input access */
else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA)
{
hfmac->pOutput = NULL;
hfmac->pOutputSize = NULL;
hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
/* Set the FMAC DMA transfer complete callback */
hfmac->hdmaOut->XferHalfCpltCallback = FMAC_DMAHalfOutputDataReady;
hfmac->hdmaOut->XferCpltCallback = FMAC_DMAOutputDataReady;
/* Set the DMA error callback */
hfmac->hdmaOut->XferErrorCallback = FMAC_DMAError;
/* Enable the DMA stream managing FMAC output data read */
if ((hfmac->hdmaOut->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hfmac->hdmaOut->LinkedListQueue != NULL) && (hfmac->hdmaOut->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hfmac->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
(uint32_t)(4UL * (*pOutputSize)); /* Set DMA data size */
hfmac->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)&hfmac->Instance->RDATA;/* Set DMA source address */
hfmac->hdmaOut->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)pOutput; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hfmac->hdmaOut);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hfmac->hdmaOut, (uint32_t)&hfmac->Instance->RDATA, \
(uint32_t)pOutput, (uint32_t)(4UL * (*pOutputSize)));
}
if (status != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
}
else if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
{
hfmac->pOutput = NULL;
hfmac->pOutputSize = NULL;
hfmac->RdState = HAL_FMAC_STATE_READY;
}
else
{
/* Update the output data information (polling, IT) */
hfmac->pOutput = pOutput;
hfmac->pOutputSize = pOutputSize;
hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
}
return HAL_OK;
}
/**
* @brief Read available output data until Y EMPTY is set.
* @param hfmac FMAC handle.
* @param MaxSizeToRead Maximum number of data to read (this serves as a timeout
* if FMAC continuously writes into the output buffer).
* @retval None
*/
static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead)
{
uint16_t maxsize;
uint16_t threshold;
uint32_t tmpvalue;
/* Check if there is data to read */
if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0U)
{
return;
}
/* Get the maximum index (no wait allowed, no overstepping of the output buffer) */
if ((hfmac->OutputCurrentSize + MaxSizeToRead) > *(hfmac->pOutputSize))
{
maxsize = *(hfmac->pOutputSize);
}
else
{
maxsize = hfmac->OutputCurrentSize + MaxSizeToRead;
}
/* Read until there is no more room or no more data */
do
{
/* If there is no more room, return */
if (!(hfmac->OutputCurrentSize < maxsize))
{
return;
}
/* Read the available data */
tmpvalue = ((READ_REG(hfmac->Instance->RDATA))& FMAC_RDATA_RDATA);
*(hfmac->pOutput) = (int16_t)tmpvalue;
hfmac->pOutput++;
hfmac->OutputCurrentSize++;
} while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0U);
/* Y buffer empty flag has just be raised, read the threshold */
threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_Y_EMPTY_WM(hfmac)) - 1U;
/* Update the maximum size if needed (limited data available) */
if ((hfmac->OutputCurrentSize + threshold) < maxsize)
{
maxsize = hfmac->OutputCurrentSize + threshold;
}
/* Read the available data */
while (hfmac->OutputCurrentSize < maxsize)
{
tmpvalue = ((READ_REG(hfmac->Instance->RDATA))& FMAC_RDATA_RDATA);
*(hfmac->pOutput) = (int16_t)tmpvalue;
hfmac->pOutput++;
hfmac->OutputCurrentSize++;
}
}
/**
* @brief Write available input data until X1 FULL is set.
* @param hfmac FMAC handle.
* @param MaxSizeToWrite Maximum number of data to write (this serves as a timeout
* if FMAC continuously empties the input buffer).
* @retval None
*/
static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite)
{
uint16_t maxsize;
uint16_t threshold;
/* Check if there is room in FMAC */
if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0U)
{
return;
}
/* Get the maximum index (no wait allowed, no overstepping of the output buffer) */
if ((hfmac->InputCurrentSize + MaxSizeToWrite) > *(hfmac->pInputSize))
{
maxsize = *(hfmac->pInputSize);
}
else
{
maxsize = hfmac->InputCurrentSize + MaxSizeToWrite;
}
/* Write until there is no more room or no more data */
do
{
/* If there is no more room, return */
if (!(hfmac->InputCurrentSize < maxsize))
{
return;
}
/* Write the available data */
WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
hfmac->pInput++;
hfmac->InputCurrentSize++;
} while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0U);
/* X1 buffer full flag has just be raised, read the threshold */
threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_X1_FULL_WM(hfmac)) - 1U;
/* Update the maximum size if needed (limited data available) */
if ((hfmac->InputCurrentSize + threshold) < maxsize)
{
maxsize = hfmac->InputCurrentSize + threshold;
}
/* Write the available data */
while (hfmac->InputCurrentSize < maxsize)
{
WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
hfmac->pInput++;
hfmac->InputCurrentSize++;
}
}
/**
* @brief DMA FMAC Input Data process half complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void FMAC_DMAHalfGetData(DMA_HandleTypeDef *hdma)
{
FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Call half get data callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->HalfGetDataCallback(hfmac);
#else
HAL_FMAC_HalfGetDataCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA FMAC Input Data process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void FMAC_DMAGetData(DMA_HandleTypeDef *hdma)
{
FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Reset the pointers to indicate new data will be needed */
FMAC_ResetInputStateAndDataPointers(hfmac);
/* Call get data callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->GetDataCallback(hfmac);
#else
HAL_FMAC_GetDataCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA FMAC Output Data process half complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void FMAC_DMAHalfOutputDataReady(DMA_HandleTypeDef *hdma)
{
FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Call half output data ready callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->HalfOutputDataReadyCallback(hfmac);
#else
HAL_FMAC_HalfOutputDataReadyCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA FMAC Output Data process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void FMAC_DMAOutputDataReady(DMA_HandleTypeDef *hdma)
{
FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Reset the pointers to indicate new data will be needed */
FMAC_ResetOutputStateAndDataPointers(hfmac);
/* Call output data ready callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->OutputDataReadyCallback(hfmac);
#else
HAL_FMAC_OutputDataReadyCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA FMAC Filter Configuration process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status;
uint8_t index;
FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* If needed, write CoeffA and exit */
if (hfmac->pInput != NULL)
{
/* Set the FMAC DMA transfer complete callback */
hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
/* Set the DMA error callback */
hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
/* Enable the DMA stream managing FMAC preload data write */
if ((hfmac->hdmaPreload->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hfmac->hdmaPreload->LinkedListQueue != NULL) && (hfmac->hdmaPreload->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
(uint32_t)(2UL * hfmac->InputCurrentSize);/* Set DMA data size */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)hfmac->pInput; /* Set DMA source address */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
}
else
{
/* Return error status */
status = HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)hfmac->pInput, \
(uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * hfmac->InputCurrentSize));
}
if (status == HAL_OK)
{
hfmac->pInput = NULL;
hfmac->InputCurrentSize = 0U;
return;
}
/* If not exited, there was an error: set FMAC handle state to error */
hfmac->State = HAL_FMAC_STATE_ERROR;
}
else
{
/* Wait for the end of the writing */
for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
{
if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
{
break;
}
}
/* If 'START' is still set, there was a timeout: set FMAC handle state to timeout */
if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
{
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
}
else
{
/* Change the FMAC state */
hfmac->State = HAL_FMAC_STATE_READY;
/* Call output data ready callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->FilterConfigCallback(hfmac);
#else
HAL_FMAC_FilterConfigCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
return;
}
}
/* If not exited, there was an error: set FMAC handle error code to DMA error */
hfmac->ErrorCode |= HAL_FMAC_ERROR_DMA;
/* Call user callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->ErrorCallback(hfmac);
#else
HAL_FMAC_ErrorCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
/**
* @brief DMA FMAC Filter Configuration process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status;
uint8_t index;
FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Wait for the end of the X1 writing */
for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
{
if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
{
break;
}
}
/* If 'START' is still set, there was an error: set FMAC handle state to error */
if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
{
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
}
/* If needed, preload Y buffer */
else if ((hfmac->pInput != NULL) && (hfmac->InputCurrentSize != 0U))
{
/* Write number of values to be loaded, the data load function and start the operation */
WRITE_REG(hfmac->Instance->PARAM, \
(((uint32_t)(hfmac->InputCurrentSize) << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
/* Set the FMAC DMA transfer complete callback */
hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
/* Set the DMA error callback */
hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
/* Enable the DMA stream managing FMAC preload data write */
if ((hfmac->hdmaPreload->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hfmac->hdmaPreload->LinkedListQueue != NULL) && (hfmac->hdmaPreload->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] =
(uint32_t)(2UL * hfmac->InputCurrentSize);/* Set DMA data size */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)hfmac->pInput; /* Set DMA source address */
hfmac->hdmaPreload->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hfmac->Instance->WDATA; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hfmac->hdmaPreload);
}
else
{
/* Return error status */
status = HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)hfmac->pInput, \
(uint32_t)&hfmac->Instance->WDATA, (uint32_t)(2UL * hfmac->InputCurrentSize));
}
if (status == HAL_OK)
{
hfmac->pInput = NULL;
hfmac->InputCurrentSize = 0U;
return;
}
/* If not exited, there was an error */
hfmac->ErrorCode = HAL_FMAC_ERROR_DMA;
hfmac->State = HAL_FMAC_STATE_ERROR;
}
else
{
/* nothing to do */
}
if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
{
/* Change the FMAC state */
hfmac->State = HAL_FMAC_STATE_READY;
/* Call output data ready callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->FilterPreloadCallback(hfmac);
#else
HAL_FMAC_FilterPreloadCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
else
{
/* Call user callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->ErrorCallback(hfmac);
#else
HAL_FMAC_ErrorCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
}
/**
* @brief DMA FMAC communication error callback.
* @param hdma DMA handle.
* @retval None
*/
static void FMAC_DMAError(DMA_HandleTypeDef *hdma)
{
FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Set FMAC handle state to error */
hfmac->State = HAL_FMAC_STATE_ERROR;
/* Set FMAC handle error code to DMA error */
hfmac->ErrorCode |= HAL_FMAC_ERROR_DMA;
/* Call user callback */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
hfmac->ErrorCallback(hfmac);
#else
HAL_FMAC_ErrorCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_FMAC_MODULE_ENABLED */
#endif /* FMAC */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c
|
C
|
apache-2.0
| 96,661
|
/**
******************************************************************************
* @file stm32u5xx_hal_gfxmmu.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* functionalities of the Graphic MMU (GFXMMU) peripheral:
* + Initialization and De-initialization.
* + LUT configuration.
* + Force flush and/or invalidate of cache.
* + Modify physical buffer addresses.
* + Modify cache and pre-fetch parameters.
* + Error management.
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** Initialization ***
======================
[..]
(#) As prerequisite, fill in the HAL_GFXMMU_MspInit() :
(++) Enable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
(++) If interrupts are used, enable and configure GFXMMU global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(#) Configure the number of blocks per line, default value, physical
buffer addresses, cache and pre-fetch parameters and interrupts
using the HAL_GFXMMU_Init() function.
*** LUT configuration ***
=========================
[..]
(#) Use HAL_GFXMMU_DisableLutLines() to deactivate all LUT lines (or a
range of lines).
(#) Use HAL_GFXMMU_ConfigLut() to copy LUT from flash to look up RAM.
(#) Use HAL_GFXMMU_ConfigLutLine() to configure one line of LUT.
*** Force flush and/or invalidate of cache ***
==============================================
[..]
(#) Use HAL_GFXMMU_ConfigForceCache() to flush and/or invalidate cache.
*** Modify physical buffer addresses ***
=======================================
[..]
(#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses.
*** Modify cache and pre-fetch parameters ***
=============================================
[..]
(#) Use HAL_GFXMMU_ModifyCachePrefetch() to modify cache and pre-fetch
parameters.
*** Error management ***
========================
[..]
(#) If interrupts are used, HAL_GFXMMU_IRQHandler() will be called when
an error occurs. This function will call HAL_GFXMMU_ErrorCallback().
Use HAL_GFXMMU_GetError() to get the error code.
*** De-initialization ***
=========================
[..]
(#) As prerequisite, fill in the HAL_GFXMMU_MspDeInit() :
(++) Disable GFXMMU clock interface with __HAL_RCC_GFXMMU_CLK_ENABLE().
(++) If interrupts has been used, disable GFXMMU global interrupt with
HAL_NVIC_DisableIRQ().
(#) De-initialize GFXMMU using the HAL_GFXMMU_DeInit() function.
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions HAL_GFXMMU_RegisterCallback() to register a user callback.
[..]
Function HAL_GFXMMU_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : GFXMMU error.
(+) MspInitCallback : GFXMMU MspInit.
(+) MspDeInitCallback : GFXMMU MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
[..]
Use function HAL_GFXMMU_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
HAL_GFXMMU_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
This function allows to reset following callbacks:
(+) ErrorCallback : GFXMMU error.
(+) MspInitCallback : GFXMMU MspInit.
(+) MspDeInitCallback : GFXMMU MspDeInit.
[..]
By default, after the HAL_GFXMMU_Init and if the state is HAL_GFXMMU_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples HAL_GFXMMU_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_GFXMMU_Init
and HAL_GFXMMU_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_GFXMMU_Init and HAL_GFXMMU_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_GFXMMU_RegisterCallback before calling HAL_GFXMMU_DeInit
or HAL_GFXMMU_Init function.
[..]
When the compilation define USE_HAL_GFXMMU_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_GFXMMU_MODULE_ENABLED
#if defined(GFXMMU)
/** @defgroup GFXMMU GFXMMU
* @brief GFXMMU HAL driver module
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define GFXMMU_LUTXL_FVB_OFFSET 8U
#define GFXMMU_LUTXL_LVB_OFFSET 16U
#define GFXMMU_CR_ITS_MASK 0x1FU
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GFXMMU_Exported_Functions GFXMMU Exported Functions
* @{
*/
/** @defgroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize the GFXMMU.
(+) De-initialize the GFXMMU.
@endverbatim
* @{
*/
/**
* @brief Initialize the GFXMMU according to the specified parameters in the
* GFXMMU_InitTypeDef structure and initialize the associated handle.
* @param hgfxmmu GFXMMU handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check GFXMMU handle */
if (hgfxmmu == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_BLOCKS_PER_LINE(hgfxmmu->Init.BlocksPerLine));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf0Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf1Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf2Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(hgfxmmu->Init.Buffers.Buf3Address));
assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.CachePrefetch.Activation));
assert_param(IS_FUNCTIONAL_STATE(hgfxmmu->Init.Interrupts.Activation));
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
/* Call GFXMMU MSP init function */
if (hgfxmmu->MspInitCallback == NULL)
{
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
}
hgfxmmu->MspInitCallback(hgfxmmu);
#else
/* Call GFXMMU MSP init function */
HAL_GFXMMU_MspInit(hgfxmmu);
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
/* Configure blocks per line, cache and interrupts parameters on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
GFXMMU_CR_AMEIE | GFXMMU_CR_192BM | GFXMMU_CR_CE | GFXMMU_CR_CL |
GFXMMU_CR_CLB | GFXMMU_CR_FC | GFXMMU_CR_PD | GFXMMU_CR_OC |
GFXMMU_CR_OB);
hgfxmmu->Instance->CR |= (hgfxmmu->Init.BlocksPerLine);
if (hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK(hgfxmmu->Init.CachePrefetch.CacheLock));
assert_param(IS_GFXMMU_PREFETCH(hgfxmmu->Init.CachePrefetch.Prefetch));
assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(hgfxmmu->Init.CachePrefetch.OutterBufferability));
assert_param(IS_GFXMMU_OUTTER_CACHABILITY(hgfxmmu->Init.CachePrefetch.OutterCachability));
hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
hgfxmmu->Init.CachePrefetch.CacheLock |
hgfxmmu->Init.CachePrefetch.Prefetch |
hgfxmmu->Init.CachePrefetch.OutterBufferability |
hgfxmmu->Init.CachePrefetch.OutterCachability);
if (hgfxmmu->Init.CachePrefetch.CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(hgfxmmu->Init.CachePrefetch.CacheLockBuffer));
assert_param(IS_GFXMMU_CACHE_FORCE(hgfxmmu->Init.CachePrefetch.CacheForce));
hgfxmmu->Instance->CR |= (hgfxmmu->Init.CachePrefetch.CacheLockBuffer |
hgfxmmu->Init.CachePrefetch.CacheForce);
}
}
if (hgfxmmu->Init.Interrupts.Activation == ENABLE)
{
assert_param(IS_GFXMMU_INTERRUPTS(hgfxmmu->Init.Interrupts.UsedInterrupts));
hgfxmmu->Instance->CR |= hgfxmmu->Init.Interrupts.UsedInterrupts;
}
/* Configure default value on GFXMMU_DVR register */
hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue;
/* Configure physical buffer addresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address;
hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address;
hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address;
hgfxmmu->Instance->B3CR = hgfxmmu->Init.Buffers.Buf3Address;
/* Force invalidate cache if cache is enabled */
if (hgfxmmu->Init.CachePrefetch.Activation == ENABLE)
{
hgfxmmu->Instance->CCR |= GFXMMU_CACHE_FORCE_INVALIDATE;
}
/* Reset GFXMMU error code */
hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
/* Set GFXMMU to ready state */
hgfxmmu->State = HAL_GFXMMU_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief De-initialize the GFXMMU.
* @param hgfxmmu GFXMMU handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check GFXMMU handle */
if (hgfxmmu == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
/* Disable all interrupts on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_B0OIE | GFXMMU_CR_B1OIE | GFXMMU_CR_B2OIE | GFXMMU_CR_B3OIE |
GFXMMU_CR_AMEIE);
/* Call GFXMMU MSP de-init function */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
if (hgfxmmu->MspDeInitCallback == NULL)
{
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
}
hgfxmmu->MspDeInitCallback(hgfxmmu);
#else
HAL_GFXMMU_MspDeInit(hgfxmmu);
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
/* Set GFXMMU to reset state */
hgfxmmu->State = HAL_GFXMMU_STATE_RESET;
}
/* Return function status */
return status;
}
/**
* @brief Initialize the GFXMMU MSP.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_GFXMMU_MspInit could be implemented in the user file.
*/
}
/**
* @brief De-initialize the GFXMMU MSP.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_GFXMMU_MspDeInit could be implemented in the user file.
*/
}
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
/**
* @brief Register a user GFXMMU callback
* to be used instead of the weak predefined callback.
* @param hgfxmmu GFXMMU handle.
* @param CallbackID ID of the callback to be registered.
* This parameter can be one of the following values:
* @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
* @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
* @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
* @param pCallback pointer to the callback function.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID,
pGFXMMU_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
else
{
if (HAL_GFXMMU_STATE_READY == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_ERROR_CB_ID :
hgfxmmu->ErrorCallback = pCallback;
break;
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = pCallback;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = pCallback;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = pCallback;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Unregister a user GFXMMU callback.
* GFXMMU callback is redirected to the weak predefined callback.
* @param hgfxmmu GFXMMU handle.
* @param CallbackID ID of the callback to be unregistered.
* This parameter can be one of the following values:
* @arg @ref HAL_GFXMMU_ERROR_CB_ID error callback ID.
* @arg @ref HAL_GFXMMU_MSPINIT_CB_ID MSP init callback ID.
* @arg @ref HAL_GFXMMU_MSPDEINIT_CB_ID MSP de-init callback ID.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgfxmmu,
HAL_GFXMMU_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (HAL_GFXMMU_STATE_READY == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_ERROR_CB_ID :
hgfxmmu->ErrorCallback = HAL_GFXMMU_ErrorCallback;
break;
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (HAL_GFXMMU_STATE_RESET == hgfxmmu->State)
{
switch (CallbackID)
{
case HAL_GFXMMU_MSPINIT_CB_ID :
hgfxmmu->MspInitCallback = HAL_GFXMMU_MspInit;
break;
case HAL_GFXMMU_MSPDEINIT_CB_ID :
hgfxmmu->MspDeInitCallback = HAL_GFXMMU_MspDeInit;
break;
default :
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update the error code */
hgfxmmu->ErrorCode |= GFXMMU_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup GFXMMU_Exported_Functions_Group2 Operations functions
* @brief GFXMMU operation functions
*
@verbatim
==============================================================================
##### Operation functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Configure LUT.
(+) Force flush and/or invalidate of cache.
(+) Modify physical buffer addresses.
(+) Modify cache and pre-fetch parameters.
(+) Manage error.
@endverbatim
* @{
*/
/**
* @brief This function allows to copy LUT from flash to look up RAM.
* @param hgfxmmu GFXMMU handle.
* @param FirstLine First line enabled on LUT.
* This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
* @param LinesNumber Number of lines enabled on LUT.
* This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
* @param Address Start address of LUT in flash.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber,
uint32_t Address)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
/* Check GFXMMU state and coherent parameters */
if ((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
{
status = HAL_ERROR;
}
else
{
uint32_t current_address;
uint32_t current_line;
uint32_t lutxl_address;
uint32_t lutxh_address;
/* Initialize local variables */
current_address = Address;
current_line = 0U;
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
/* Copy LUT from flash to look up RAM */
while (current_line < LinesNumber)
{
*((uint32_t *)lutxl_address) = *((uint32_t *)current_address);
current_address += 4U;
*((uint32_t *)lutxh_address) = *((uint32_t *)current_address);
current_address += 4U;
lutxl_address += 8U;
lutxh_address += 8U;
current_line++;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to disable a range of LUT lines.
* @param hgfxmmu GFXMMU handle.
* @param FirstLine First line to disable on LUT.
* This parameter must be a number between Min_Data = 0 and Max_Data = 1023.
* @param LinesNumber Number of lines to disable on LUT.
* This parameter must be a number between Min_Data = 1 and Max_Data = 1024.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
uint32_t FirstLine,
uint32_t LinesNumber)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(FirstLine));
assert_param(IS_GFXMMU_LUT_LINES_NUMBER(LinesNumber));
/* Check GFXMMU state and coherent parameters */
if ((hgfxmmu->State != HAL_GFXMMU_STATE_READY) || ((FirstLine + LinesNumber) > 1024U))
{
status = HAL_ERROR;
}
else
{
uint32_t current_line;
uint32_t lutxl_address;
uint32_t lutxh_address;
/* Initialize local variables */
current_line = 0U;
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * FirstLine]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * FirstLine) + 1U]);
/* Disable LUT lines */
while (current_line < LinesNumber)
{
*((uint32_t *)lutxl_address) = 0U;
*((uint32_t *)lutxh_address) = 0U;
lutxl_address += 8U;
lutxh_address += 8U;
current_line++;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to configure one line of LUT.
* @param hgfxmmu GFXMMU handle.
* @param lutLine LUT line parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_LUT_LINE(lutLine->LineNumber));
assert_param(IS_GFXMMU_LUT_LINE_STATUS(lutLine->LineStatus));
assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->FirstVisibleBlock));
assert_param(IS_GFXMMU_LUT_BLOCK(lutLine->LastVisibleBlock));
assert_param(IS_GFXMMU_LUT_LINE_OFFSET(lutLine->LineOffset));
/* Check GFXMMU state */
if (hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
uint32_t lutxl_address;
uint32_t lutxh_address;
/* Initialize local variables */
lutxl_address = (uint32_t) &(hgfxmmu->Instance->LUT[2U * lutLine->LineNumber]);
lutxh_address = (uint32_t) &(hgfxmmu->Instance->LUT[(2U * lutLine->LineNumber) + 1U]);
/* Configure LUT line */
if (lutLine->LineStatus == GFXMMU_LUT_LINE_ENABLE)
{
/* Enable and configure LUT line */
*((uint32_t *)lutxl_address) = (lutLine->LineStatus |
(lutLine->FirstVisibleBlock << GFXMMU_LUTXL_FVB_OFFSET) |
(lutLine->LastVisibleBlock << GFXMMU_LUTXL_LVB_OFFSET));
*((uint32_t *)lutxh_address) = (uint32_t) lutLine->LineOffset;
}
else
{
/* Disable LUT line */
*((uint32_t *)lutxl_address) = 0U;
*((uint32_t *)lutxh_address) = 0U;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to force flush and/or invalidate of cache.
* @param hgfxmmu GFXMMU handle.
* @param ForceParam Force cache parameter.
* This parameter can be a values combination of @ref GFXMMU_CacheForceParam.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_CACHE_FORCE_ACTION(ForceParam));
/* Check GFXMMU state and cache status */
if (((hgfxmmu->Instance->CR & GFXMMU_CR_CE) != GFXMMU_CR_CE) || (hgfxmmu->State != HAL_GFXMMU_STATE_READY))
{
status = HAL_ERROR;
}
else
{
/* Force flush and/or invalidate cache on GFXMMU_CCR register */
hgfxmmu->Instance->CCR |= ForceParam;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to modify physical buffer addresses.
* @param hgfxmmu GFXMMU handle.
* @param Buffers Buffers parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf0Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf1Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf2Address));
assert_param(IS_GFXMMU_BUFFER_ADDRESS(Buffers->Buf3Address));
/* Check GFXMMU state */
if (hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Modify physical buffer addresses on GFXMMU_BxCR registers */
hgfxmmu->Instance->B0CR = Buffers->Buf0Address;
hgfxmmu->Instance->B1CR = Buffers->Buf1Address;
hgfxmmu->Instance->B2CR = Buffers->Buf2Address;
hgfxmmu->Instance->B3CR = Buffers->Buf3Address;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to modify cache and pre-fetch parameters.
* @param hgfxmmu GFXMMU handle.
* @param CachePrefetch Cache and pre-fetch parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
GFXMMU_CachePrefetchTypeDef *CachePrefetch)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_FUNCTIONAL_STATE(CachePrefetch->Activation));
/* Check parameters */
assert_param(IS_GFXMMU_ALL_INSTANCE(hgfxmmu->Instance));
/* Check GFXMMU state */
if (hgfxmmu->State != HAL_GFXMMU_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Modify cache and pre-fetch parameters on GFXMMU_CR register */
hgfxmmu->Instance->CR &= ~(GFXMMU_CR_CE | GFXMMU_CR_CL | GFXMMU_CR_CLB | GFXMMU_CR_FC |
GFXMMU_CR_PD | GFXMMU_CR_OC | GFXMMU_CR_OB);
if (CachePrefetch->Activation == ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK(CachePrefetch->CacheLock));
assert_param(IS_GFXMMU_PREFETCH(CachePrefetch->Prefetch));
assert_param(IS_GFXMMU_OUTTER_BUFFERABILITY(CachePrefetch->OutterBufferability));
assert_param(IS_GFXMMU_OUTTER_CACHABILITY(CachePrefetch->OutterCachability));
hgfxmmu->Instance->CR |= (GFXMMU_CR_CE |
CachePrefetch->CacheLock |
CachePrefetch->Prefetch |
CachePrefetch->OutterBufferability |
CachePrefetch->OutterCachability);
if (CachePrefetch->CacheLock == GFXMMU_CACHE_LOCK_ENABLE)
{
assert_param(IS_GFXMMU_CACHE_LOCK_BUFFER(CachePrefetch->CacheLockBuffer));
assert_param(IS_GFXMMU_CACHE_FORCE(CachePrefetch->CacheForce));
hgfxmmu->Instance->CR |= (CachePrefetch->CacheLockBuffer |
CachePrefetch->CacheForce);
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function handles the GFXMMU interrupts.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu)
{
uint32_t flags, interrupts, error;
/* Read current flags and interrupts and determine which error occurs */
flags = hgfxmmu->Instance->SR;
interrupts = (hgfxmmu->Instance->CR & GFXMMU_CR_ITS_MASK);
error = (flags & interrupts);
if (error != 0U)
{
/* Clear flags on GFXMMU_FCR register */
hgfxmmu->Instance->FCR = error;
/* Update GFXMMU error code */
hgfxmmu->ErrorCode |= error;
/* Call GFXMMU error callback */
#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
hgfxmmu->ErrorCallback(hgfxmmu);
#else
HAL_GFXMMU_ErrorCallback(hgfxmmu);
#endif /* USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1 */
}
}
/**
* @brief Error callback.
* @param hgfxmmu GFXMMU handle.
* @retval None.
*/
__weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgfxmmu);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_GFXMMU_ErrorCallback could be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup GFXMMU_Exported_Functions_Group3 State functions
* @brief GFXMMU state functions
*
@verbatim
==============================================================================
##### State functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Get GFXMMU handle state.
(+) Get GFXMMU error code.
@endverbatim
* @{
*/
/**
* @brief This function allows to get the current GFXMMU handle state.
* @param hgfxmmu GFXMMU handle.
* @retval GFXMMU state.
*/
HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu)
{
/* Return GFXMMU handle state */
return hgfxmmu->State;
}
/**
* @brief This function allows to get the current GFXMMU error code.
* @param hgfxmmu GFXMMU handle.
* @retval GFXMMU error code.
*/
uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu)
{
uint32_t error_code;
/* Enter in critical section */
__disable_irq();
/* Store and reset GFXMMU error code */
error_code = hgfxmmu->ErrorCode;
hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE;
/* Exit from critical section */
__enable_irq();
/* Return GFXMMU error code */
return error_code;
}
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
#endif /* GFXMMU */
#endif /* HAL_GFXMMU_MODULE_ENABLED */
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxmmu.c
|
C
|
apache-2.0
| 31,053
|
/**
******************************************************************************
* @file stm32u5xx_hal_gpio.c
* @author MCD Application Team
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
(++) Input mode
(++) Analog mode
(++) Output mode
(++) Alternate function mode
(++) External interrupt/event lines
(+) During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
(+) All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
(+) The external interrupt/event controller consists of up to 39 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure.
(++) In alternate mode is selection, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup GPIO_Private_Defines GPIO Private Defines
* @{
*/
#define GPIO_MODE (0x00000003U)
#define EXTI_MODE (0x10000000U)
#define GPIO_MODE_IT (0x00010000U)
#define GPIO_MODE_EVT (0x00020000U)
#define RISING_EDGE (0x00100000U)
#define FALLING_EDGE (0x00200000U)
#define GPIO_OUTPUT_TYPE (0x00000010U)
#define GPIO_NUMBER (16U)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Variables GPIO Private Variables
* @{
*/
/* LPGPIO Mapping */
static const LPGPIO_MapTypeDef LPGPIO_Map[GPIO_NUMBER] =
{
/* LPGPIO Pins Port Pin */
/* Pin 0:*/ {GPIOA, 1},
/* Pin 1:*/ {GPIOA, 3},
/* Pin 2:*/ {GPIOA, 6},
/* Pin 3:*/ {GPIOB, 1},
/* Pin 4:*/ {GPIOB, 10},
/* Pin 5:*/ {GPIOC, 2},
/* Pin 6:*/ {GPIOD, 13},
/* Pin 7:*/ {GPIOD, 2},
/* Pin 8:*/ {GPIOC, 10},
/* Pin 9:*/ {GPIOB, 0},
/* Pin 10:*/ {GPIOC, 12},
/* Pin 11:*/ {GPIOB, 3},
/* Pin 12:*/ {GPIOB, 4},
/* Pin 13:*/ {GPIOE, 0},
/* Pin 14:*/ {GPIOE, 2},
/* Pin 15:*/ {GPIOE, 3},
};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Initialize the GPIOx/LPGPIOx peripheral according to the specified parameters in the pGPIO_Init.
* @note If GPIOx/LPGPIOx peripheral pin is used in EXTI_MODE and the pin is secure in case
* the system implements the security (TZEN=1), it is up to the secure application to
* insure that the corresponding EXTI line is set secure.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the corresponding
* peripheral for STM32U5 family
* @param pGPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
{
uint32_t tmp;
uint32_t iocurrent;
uint32_t pin_position;
uint32_t position = 0U;
GPIO_TypeDef *p_gpio;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(pGPIO_Init->Pin));
assert_param(IS_GPIO_MODE(pGPIO_Init->Mode));
/* Save GPIO port address */
p_gpio = GPIOx;
/* Configure the port pins */
while (((pGPIO_Init->Pin) >> position) != 0U)
{
/* Get current io position */
iocurrent = (pGPIO_Init->Pin) & (1UL << position);
/* Save Pin Position */
pin_position = position;
if (iocurrent != 0U)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if (GPIOx == LPGPIO1)
{
/* MODER configuration */
tmp = GPIOx->MODER;
tmp &= ~(LPGPIO_MODER_MOD0 << position);
tmp |= ((pGPIO_Init->Mode & GPIO_MODE_OUTPUT_PP) << position);
GPIOx->MODER = tmp;
/* Save GPIO Port and pin index */
p_gpio = LPGPIO_Map[position].GPIO_PORT;
pin_position = LPGPIO_Map[position].Pin_Pos;
/* Configure Alternate function mapped with the current IO */
tmp = p_gpio->AFR[(pin_position) >> 3U];
tmp &= ~(0x0FUL << (((pin_position) & 0x07U) * 4U));
tmp |= ((GPIO_AF11_LPGPIO & 0x0FUL) << (((pin_position) & 0x07U) * 4U));
p_gpio->AFR[(pin_position) >> 3U] = tmp;
/* Configure IO Direction mode (Alternate) */
tmp = p_gpio->MODER;
tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U));
tmp |= ((GPIO_MODE_AF_PP & 0x0FUL) << (pin_position * 2U));
p_gpio->MODER = tmp;
}
else if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(pGPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
tmp = GPIOx->AFR[position >> 3U];
tmp &= ~(0x0FUL << ((position & 0x07U) * 4U));
tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * 4U));
GPIOx->AFR[position >> 3U] = tmp;
/* Configure IO Direction mode (Alternate) */
tmp = p_gpio->MODER;
tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U));
tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * 2U));
p_gpio->MODER = tmp;
}
else
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
tmp = p_gpio->MODER;
tmp &= ~(GPIO_MODER_MODE0 << (pin_position * 2U));
tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * 2U));
p_gpio->MODER = tmp;
}
/* In case of Output or Alternate function mode selection */
if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed));
/* Configure the IO Speed */
tmp = p_gpio->OSPEEDR;
tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * 2U));
tmp |= (pGPIO_Init->Speed << (pin_position * 2U));
p_gpio->OSPEEDR = tmp;
/* Configure the IO Output Type */
tmp = p_gpio->OTYPER;
tmp &= ~(GPIO_OTYPER_OT0 << pin_position);
tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << pin_position);
p_gpio->OTYPER = tmp;
}
if (pGPIO_Init->Mode != GPIO_MODE_ANALOG)
{
/* Check the Pull parameters */
assert_param(IS_GPIO_PULL(pGPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
tmp = p_gpio->PUPDR;
tmp &= ~(GPIO_PUPDR_PUPD0 << (pin_position * 2U));
tmp |= ((pGPIO_Init->Pull) << (pin_position * 2U));
p_gpio->PUPDR = tmp;
}
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
{
tmp = EXTI->EXTICR[position >> 2U];
tmp &= ~((0x0FUL) << (8U * (position & 0x03U)));
tmp |= (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)));
EXTI->EXTICR[position >> 2U] = tmp;
/* Clear Rising Falling edge configuration */
tmp = EXTI->RTSR1;
tmp &= ~((uint32_t)iocurrent);
if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
tmp |= iocurrent;
}
EXTI->RTSR1 = tmp;
tmp = EXTI->FTSR1;
tmp &= ~((uint32_t)iocurrent);
if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{
tmp |= iocurrent;
}
EXTI->FTSR1 = tmp;
/* Clear EXTI line configuration */
tmp = EXTI->EMR1;
tmp &= ~((uint32_t)iocurrent);
if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
tmp |= iocurrent;
}
EXTI->EMR1 = tmp;
tmp = EXTI->IMR1;
tmp &= ~((uint32_t)iocurrent);
if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
tmp |= iocurrent;
}
EXTI->IMR1 = tmp;
}
}
position++;
}
}
/**
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t tmp;
uint32_t iocurrent;
uint32_t pin_position;
uint32_t position = 0U;
GPIO_TypeDef *p_gpio;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Save GPIO port address */
p_gpio = GPIOx;
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0U)
{
/* Get current io position */
iocurrent = (GPIO_Pin) & (1UL << position);
/*Save Pin Position */
pin_position = position;
if (iocurrent != 0U)
{
/* In case of LPGPIO port selected */
if (GPIOx == LPGPIO1)
{
/* Configure LP/IO in Input Mode */
p_gpio = LPGPIO_Map[pin_position].GPIO_PORT;
pin_position = LPGPIO_Map[position].Pin_Pos;
LPGPIO1->MODER &= ~(1U << pin_position);
}
else
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = EXTI->EXTICR[position >> 2U];
tmp &= ((0x0FUL) << (8U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U))))
{
/* Clear EXTI line configuration */
EXTI->IMR1 &= ~(iocurrent);
EXTI->EMR1 &= ~(iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
tmp = (0x0FUL) << (8U * (position & 0x03U));
EXTI->EXTICR[position >> 2U] &= ~tmp;
}
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO in Analog Mode */
p_gpio->MODER |= (GPIO_MODER_MODE0 << (pin_position * 2U));
/* Configure the default Alternate Function in current IO */
p_gpio->AFR[pin_position >> 3U] &= ~(0x0FUL << ((pin_position & 0x07U) * 4U));
/* Configure the default value for IO Speed */
p_gpio->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * 2U));
/* Configure the default value IO Output Type */
p_gpio->OTYPER &= ~(GPIO_OTYPER_OT0 << pin_position);
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
p_gpio->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (pin_position * 2U));
}
position++;
}
}
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2
* @brief GPIO/LPGPIO Read, Write, Toggle, Lock and EXTI management functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Read the specified input port pin.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0U)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Set or clear the selected data port bit.
* @note This function uses GPIOx_BSRR/LPGPIOx_BSRR and GPIOx_BRR/LPGPIOx_BRR registers to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
/**
* @brief Toggle the specified GPIO pin.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
* @param GPIO_Pin specifies the pin to be toggled.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t odr;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
* @brief Lock GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
* @param GPIO_Pin: specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t iocurrent;
uint32_t pin_locked;
uint32_t pin_position;
uint32_t position = 0U;
GPIO_TypeDef *p_gpio;
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Save GPIO port address */
p_gpio = GPIOx;
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0U)
{
/* Get current io position */
iocurrent = GPIO_Pin & (1UL << position);
if (iocurrent != 0U)
{
/* In case of LPGPIO Port */
if (GPIOx == LPGPIO1)
{
/* Save GPIO Port and pin index */
p_gpio = LPGPIO_Map[position].GPIO_PORT;
pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos));
/* Save gpio pin locked */
pin_locked = p_gpio->LCKR;
/* Apply lock key write sequence */
tmp |= (pin_locked | pin_position);
}
else
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Save GPIO Pin pos*/
pin_position = (1UL << position);
/* Save gpio pin locked */
pin_locked = p_gpio->LCKR;
/* Apply lock key write sequence */
tmp |= (pin_locked | pin_position);
}
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
p_gpio->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
p_gpio->LCKR = pin_position;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
p_gpio->LCKR = tmp;
/* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = p_gpio->LCKR;
/* read again in order to confirm lock is active */
if ((p_gpio->LCKR & GPIO_LCKR_LCKK) != GPIO_LCKR_LCKK)
{
return HAL_ERROR;
}
}
position++;
}
return HAL_OK;
}
/**
* @brief Enable speed optimization for several pin of dedicated port.
* @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
* datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
* be kept at reset value.
* @note It must be used only if the I/O supply voltage is below 2.7 V.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t iocurrent;
uint32_t pin_position;
uint32_t position = 0U;
GPIO_TypeDef *p_gpio;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Save GPIO port address */
p_gpio = GPIOx;
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0U)
{
/* Get current io position */
iocurrent = GPIO_Pin & (1UL << position);
if (iocurrent != 0U)
{
/* In case of LPGPIO Port */
if (GPIOx == LPGPIO1)
{
/* Get GPIO pin position */
position = POSITION_VAL(GPIO_Pin);
/* Save GPIO Port and pin index */
p_gpio = LPGPIO_Map[position].GPIO_PORT;
pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos));
}
else
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Save GPIO pin pos */
pin_position = (1UL << position);
}
/* Set HSLVR gpio pin */
SET_BIT(p_gpio->HSLVR, pin_position);
}
position++;
}
}
/**
* @brief Disable speed optimization for several pin of dedicated port.
* @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding
* datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must
* be kept at reset value.
* @note It must be used only if the I/O supply voltage is below 2.7 V.
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t iocurrent;
uint32_t pin_position;
uint32_t position = 0U;
GPIO_TypeDef *p_gpio;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Save GPIO port address */
p_gpio = GPIOx;
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0U)
{
/* Get current io position */
iocurrent = GPIO_Pin & (1UL << position);
if (iocurrent != 0U)
{
/* In case of LPGPIO Port */
if (GPIOx == LPGPIO1)
{
/* Get GPIO pin position */
position = POSITION_VAL(GPIO_Pin);
/* Save GPIO Port and pin index */
p_gpio = LPGPIO_Map[position].GPIO_PORT;
pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos));
}
else
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Save GPIO pin pos */
pin_position = (1UL << position);
}
/* Clear HSLVR gpio pin */
CLEAR_BIT(p_gpio->HSLVR, pin_position);
}
position++;
}
}
/**
* @brief Handle EXTI interrupt request.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U)
{
__HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
}
if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U)
{
__HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
}
}
/**
* @brief EXTI line rising detection callback.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
*/
}
/**
* @brief EXTI line falling detection callback.
* @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file
*/
}
/**
* @}
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions
* @brief GPIO attributes management functions.
*
@verbatim
===============================================================================
##### IO attributes functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Configure the GPIO pins attributes.
* @note Available attributes are to secure GPIO pin(s), so this function is
* only available in secure
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
* @param GPIO_Pin: specifies the pin(s) to configure the secure attribute
* @param PinAttributes: specifies the pin(s) to be set in secure mode, other being set non secured.
* @retval None
*/
void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes)
{
uint32_t iocurrent;
uint32_t pin_position;
uint32_t position = 0U;
GPIO_TypeDef *p_gpio;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ATTRIBUTES(PinAttributes));
/* Save GPIO port address */
p_gpio = GPIOx;
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0U)
{
/* Get current io position */
iocurrent = GPIO_Pin & (1UL << position);
/* Save pin position */
pin_position = position;
if (iocurrent != 0U)
{
/* In case of LPGPIO Port */
if (GPIOx == LPGPIO1)
{
/* Save GPIO Port and pin index */
p_gpio = LPGPIO_Map[position].GPIO_PORT;
pin_position = LPGPIO_Map[position].Pin_Pos;
}
else
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
}
/* Configure the IO secure attribute */
MODIFY_REG(p_gpio->SECCFGR, (GPIO_SECCFGR_SEC0 << pin_position), (PinAttributes << pin_position));
}
position++;
}
}
/**
* @brief Get the GPIO pins attributes.
* @note Available attributes are to secure GPIO pin(s), so this function is
* only available in secure
* @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding
* peripheral for STM32U5 family
* @param GPIO_Pin: specifies the single pin to get the secure attribute from
* @param pPinAttributes: pointer to return the pin attributes.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes)
{
uint32_t iocurrent;
uint32_t pin_position;
uint32_t position = 0U;
GPIO_TypeDef *p_gpio;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin) && (GPIO_Pin != GPIO_PIN_ALL));
/* Check null pointer */
if (pPinAttributes == NULL)
{
return HAL_ERROR;
}
/* Get secure attribute of the port pin */
while ((GPIO_Pin >> position) != 0U)
{
/* Get current io position */
iocurrent = GPIO_Pin & (1UL << position);
if (iocurrent != 0U)
{
/* In case of LPGPIO Port */
if (GPIOx == LPGPIO1)
{
/* Save GPIO Port and pin index */
p_gpio = LPGPIO_Map[position].GPIO_PORT;
pin_position = LPGPIO_Map[position].Pin_Pos;
}
else
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Save GPIO port address */
p_gpio = GPIOx;
pin_position = (1UL << position);
}
/* Get the IO secure attribute */
if ((p_gpio->SECCFGR & (GPIO_SECCFGR_SEC0 << pin_position)) != 0U)
{
*pPinAttributes = GPIO_PIN_SEC;
}
else
{
*pPinAttributes = GPIO_PIN_NSEC;
}
break;
}
position++;
}
return HAL_OK;
}
/**
* @}
*/
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c
|
C
|
apache-2.0
| 31,484
|
/**
******************************************************************************
* @file stm32u5xx_hal_gpu2d.c
* @author MCD Application Team
* @brief GPU2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the GPU2D peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
******************************************************************************
* @attention
*
* Copyright (c) 2022 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Peripheral control is exclusively done by the accompanying middleware library.
*** Interrupt mode IO operation ***
===================================
[..]
(#) Configure the GPU2D hardware to perform graphics operation using the Third Party MW
Library APIs.
(#) Submit command List to the hardware.
(#) Wait indefinitely for the completion of submitted Command List by GPU2D hardware.
(#) Use HAL_GPU2D_IRQHandler() called under GPU2D_IRQHandler() interrupt subroutine.
(#) At the end of Command List execution HAL_GPU2D_IRQHandler() function is executed
and user can add his own function by customization of function pointer
(#) CommandListCpltCallback (member of GPU2D handle structure) to notify the upper level
about the completion of Command List execution.
(#) Callback HAL_GPU2D_CommandListCpltCallback is invoked when the GPU2D hardware executes
the programmed command list (Command List execution completion).
(++) This callback is called when the compilation defines USE_HAL_GPU2D_REGISTER_CALLBACKS
is set to 0 or not defined.
(++) This callback should be implemented in the application side. It should notify
the upper level that the programmed command list is completed.
(#) To control the GPU2D state, use the following function: HAL_GPU2D_GetState().
(#) To read the GPU2D error code, use the following function: HAL_GPU2D_GetError().
*** GPU2D HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in GPU2D HAL driver :
(+) __HAL_GPU2D_RESET_HANDLE_STATE: Reset GPU2D handle state.
(+) __HAL_GPU2D_GET_FLAG: Get the GPU2D pending flags.
(+) __HAL_GPU2D_CLEAR_FLAG: Clear the GPU2D pending flags.
(+) __HAL_GPU2D_GET_IT_SOURCE: Check whether the specified GPU2D interrupt is enabled or not.
*** Callback registration ***
===================================
[..]
(#) The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use function @ref HAL_GPU2D_RegisterCallback() to register a user callback.
(#) Function @ref HAL_GPU2D_RegisterCallback() allows to register following callbacks:
(+) CommandListCpltCallback : callback for Command List completion.
(+) MspInitCallback : GPU2D MspInit.
(+) MspDeInitCallback : GPU2D MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(#) Use function @ref HAL_GPU2D_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_GPU2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) CommandListCpltCallback : callback for Command List completion.
(+) MspInitCallback : GPU2D MspInit.
(+) MspDeInitCallback : GPU2D MspDeInit.
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_GPU2D_RegisterCallback before calling @ref HAL_GPU2D_DeInit
or @ref HAL_GPU2D_Init function.
When The compilation define USE_HAL_GPU2D_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
[..]
(@) You can refer to the GPU2D HAL driver header file for more useful macros
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
#ifdef HAL_GPU2D_MODULE_ENABLED
#if defined (GPU2D)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup GPU2D GPU2D
* @brief GPU2D HAL module driver
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup GPU2D_Private_Macros GPU2D Private Macros
* @{
*/
/** @defgroup GPU2D_Write_Read Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in GPU2D register
* @param __INSTANCE__ GPU2D Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define GPU2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(*(__IO uint32_t *)(__INSTANCE__\
+ __REG__), __VALUE__)
/**
* @brief Read a value in GPU2D register
* @param __INSTANCE__ GPU2D Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define GPU2D_ReadReg(__INSTANCE__, __REG__) READ_REG(*(__IO uint32_t *)(__INSTANCE__ + __REG__))
/**
* @}
*/
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPU2D_Exported_Functions GPU2D Exported Functions
* @{
*/
/** @defgroup GPU2D_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the GPU2D
(+) De-initialize the GPU2D
@endverbatim
* @{
*/
/**
* @brief Initialize the GPU2D according to the specified
* parameters in the GPU2D_InitTypeDef and create the associated handle.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_GPU2D_Init(GPU2D_HandleTypeDef *hgpu2d)
{
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
if (hgpu2d->State == HAL_GPU2D_STATE_RESET)
{
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers in HAL_GPU2D_STATE_RESET only */
hgpu2d->CommandListCpltCallback = HAL_GPU2D_CommandListCpltCallback;
if (hgpu2d->MspInitCallback == NULL)
{
hgpu2d->MspInitCallback = HAL_GPU2D_MspInit;
}
/* Init the low level hardware */
hgpu2d->MspInitCallback(hgpu2d);
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
/* Init the low level hardware */
HAL_GPU2D_MspInit(hgpu2d);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Allocate lock resource and initialize it */
hgpu2d->Lock = HAL_UNLOCKED;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/* Reset the CommandListCpltCallback handler */
hgpu2d->CommandListCpltCallback = NULL;
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Update error code */
hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE;
/* Initialize the GPU2D state*/
hgpu2d->State = HAL_GPU2D_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hgpu2d);
return HAL_OK;
}
/**
* @brief Deinitializes the GPU2D peripheral registers to their default reset
* values.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
HAL_StatusTypeDef HAL_GPU2D_DeInit(GPU2D_HandleTypeDef *hgpu2d)
{
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
/* Process locked */
__HAL_LOCK(hgpu2d);
if (hgpu2d->State == HAL_GPU2D_STATE_READY)
{
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
if (hgpu2d->MspDeInitCallback == NULL)
{
hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit;
}
/* DeInit the low level hardware */
hgpu2d->MspDeInitCallback(hgpu2d);
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
/* Carry on with de-initialization of low level hardware */
HAL_GPU2D_MspDeInit(hgpu2d);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
}
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/* Reset the CommandListCpltCallback handler */
hgpu2d->CommandListCpltCallback = NULL;
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/* Update error code */
hgpu2d->ErrorCode = HAL_GPU2D_ERROR_NONE;
/* Reset the GPU2D state*/
hgpu2d->State = HAL_GPU2D_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hgpu2d);
return HAL_OK;
}
/**
* @brief Initializes the GPU2D MSP.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
__weak void HAL_GPU2D_MspInit(GPU2D_HandleTypeDef *hgpu2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_MspInit can be implemented in the user file.
*/
}
/**
* @brief DeInitializes the GPU2D MSP.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
__weak void HAL_GPU2D_MspDeInit(GPU2D_HandleTypeDef *hgpu2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_MspDeInit can be implemented in the user file.
*/
}
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User GPU2D callback
* To be used instead of the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID
* @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID
* @param pCallback pointer to the callback function
* @note Weak predefined callback is defined for HAL_GPU2D_MSPINIT_CB_ID and HAL_GPU2D_MSPDEINIT_CB_ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_GPU2D_RegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID,
pGPU2D_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
/* Check the pCallback parameter is valid or not */
if (pCallback == NULL)
{
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
else
{
if ((hgpu2d->State == HAL_GPU2D_STATE_READY)
|| (hgpu2d->State == HAL_GPU2D_STATE_RESET))
{
switch (CallbackID)
{
case HAL_GPU2D_MSPINIT_CB_ID:
hgpu2d->MspInitCallback = pCallback;
break;
case HAL_GPU2D_MSPDEINIT_CB_ID:
hgpu2d->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
}
/* Release lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
/**
* @brief Unregister a GPU2D callback
* GPU2D Callback is redirected to the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_GPU2D_MSPINIT_CB_ID GPU2D MspInit callback ID
* @arg @ref HAL_GPU2D_MSPDEINIT_CB_ID GPU2D MspDeInit callback ID
* @note Callback pointers will be set to legacy weak predefined callbacks for HAL_GPU2D_MSPINIT_CB_ID and
* HAL_GPU2D_MSPDEINIT_CB_ID
* @retval status
*/
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCallback(GPU2D_HandleTypeDef *hgpu2d, HAL_GPU2D_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
if ((HAL_GPU2D_STATE_READY == hgpu2d->State)
|| (HAL_GPU2D_STATE_RESET == hgpu2d->State))
{
switch (CallbackID)
{
case HAL_GPU2D_MSPINIT_CB_ID:
hgpu2d->MspInitCallback = HAL_GPU2D_MspInit; /* Legacy weak Msp Init */
break;
case HAL_GPU2D_MSPDEINIT_CB_ID:
hgpu2d->MspDeInitCallback = HAL_GPU2D_MspDeInit; /* Legacy weak Msp DeInit */
break;
default :
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
/* Release lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
/**
* @brief Register GPU2D Command List Complete Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @param pCallback pointer to the Command List Complete Callback function
* @note Weak predefined callback is defined for Command List Complete
* @retval status
*/
HAL_StatusTypeDef HAL_GPU2D_RegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d,
pGPU2D_CommandListCpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
/* Check the CallbackID is valid or not */
if (pCallback == NULL)
{
/* Update the error code */
hgpu2d->ErrorCode |= HAL_GPU2D_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
else
{
if ((HAL_GPU2D_STATE_READY == hgpu2d->State)
|| (HAL_GPU2D_STATE_RESET == hgpu2d->State))
{
hgpu2d->CommandListCpltCallback = pCallback;
}
else
{
status = HAL_ERROR;
}
}
/* Release lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
/**
* @brief Unregister a GPU2D Command List Complete Callback
* GPU2D Command List Complete Callback is redirected to the weak (surcharged) predefined callback
* @param hgpu2d GPU2D handle
* @note Callback pointer will be invalidate (NULL value)
* @retval status
*/
HAL_StatusTypeDef HAL_GPU2D_UnRegisterCommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the GPU2D handle validity */
if (hgpu2d == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hgpu2d);
if ((hgpu2d->State == HAL_GPU2D_STATE_READY)
|| (hgpu2d->State == HAL_GPU2D_STATE_RESET))
{
hgpu2d->CommandListCpltCallback = NULL; /* Invalidate the Callback pointer */
}
else
{
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hgpu2d);
return status;
}
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
/**
* @}
*/
/** @defgroup GPU2D_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Read GPU2D Register value.
(+) Write a value to GPU2D Register.
(+) handle GPU2D interrupt request.
(+) Command List Complete Transfer Complete callback.
@endverbatim
* @{
*/
/**
* @brief Read GPU2D Register. Helper function for the higher-level library.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @param offset The register offset from GPU2D base address to read.
* @retval Register value
*/
uint32_t HAL_GPU2D_ReadRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset)
{
uint32_t value;
/* Check the GPU2D handle validity */
assert_param(hgpu2d != NULL);
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
assert_param(IS_GPU2D_OFFSET(offset));
/* No locking is required since reading a register is an atomic operation
* and doesn't incur a state change in hal_gpu2d. */
value = GPU2D_ReadReg(hgpu2d->Instance, offset);
return value;
}
/**
* @brief Write a value to GPU2D Register. Helper function for the higher-level library.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @param offset The register offset from GPU2D base address to write.
* @param value The value to be written to provided register.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_GPU2D_WriteRegister(GPU2D_HandleTypeDef *hgpu2d, uint32_t offset, uint32_t value)
{
/* Check the GPU2D handle validity */
assert_param(hgpu2d != NULL);
/* Check the parameters */
assert_param(IS_GPU2D_ALL_INSTANCE(hgpu2d->Instance));
assert_param(IS_GPU2D_OFFSET(offset));
/* No locking is required since writing a register is an atomic operation
* and doesn't incur a state change in hal_gpu2d. */
GPU2D_WriteReg(hgpu2d->Instance, offset, value);
return HAL_OK;
}
/**
* @brief Handle GPU2D interrupt request.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
void HAL_GPU2D_IRQHandler(GPU2D_HandleTypeDef *hgpu2d)
{
uint32_t isr_flags = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_ITCTRL);
/* Command List Complete Interrupt management */
if ((isr_flags & GPU2D_FLAG_CLC) != 0U)
{
uint32_t last_cl_id;
/* Clear the completion flag */
__HAL_GPU2D_CLEAR_FLAG(hgpu2d, GPU2D_FLAG_CLC);
last_cl_id = GPU2D_ReadReg(hgpu2d->Instance, GPU2D_CLID);
/* Command List Complete Callback */
#if (USE_HAL_GPU2D_REGISTER_CALLBACKS == 1)
if (hgpu2d->CommandListCpltCallback != NULL)
{
hgpu2d->CommandListCpltCallback(hgpu2d, last_cl_id);
}
#else /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 0 */
HAL_GPU2D_CommandListCpltCallback(hgpu2d, last_cl_id);
#endif /* USE_HAL_GPU2D_REGISTER_CALLBACKS = 1 */
}
}
/**
* @brief Handle GPU2D Error interrupt request.
* @param hgpu2d Pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
void HAL_GPU2D_ER_IRQHandler(GPU2D_HandleTypeDef *hgpu2d)
{
HAL_GPU2D_ErrorCallback(hgpu2d);
}
/**
* @brief Command List Complete callback.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @param CmdListID Command list ID that got completed.
* @retval None
*/
__weak void HAL_GPU2D_CommandListCpltCallback(GPU2D_HandleTypeDef *hgpu2d, uint32_t CmdListID)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
UNUSED(CmdListID);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_CommandListCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Error handler callback.
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval None
*/
__weak void HAL_GPU2D_ErrorCallback(GPU2D_HandleTypeDef *hgpu2d)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hgpu2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_GPU2D_ErrorCallback can be implemented in the user file.
The default implementation stops the execution as an error is considered
fatal and non recoverable.
*/
/* Infinite loop */
for (;;);
}
/**
* @}
*/
/** @defgroup GPU2D_Exported_Functions_Group3 Peripheral State and Error functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to:
(+) Get the GPU2D state
(+) Get the GPU2D error code
@endverbatim
* @{
*/
/**
* @brief Return the GPU2D state
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for the GPU2D.
* @retval GPU2D state
*/
HAL_GPU2D_StateTypeDef HAL_GPU2D_GetState(GPU2D_HandleTypeDef const *const hgpu2d)
{
return hgpu2d->State;
}
/**
* @brief Return the GPU2D error code
* @param hgpu2d pointer to a GPU2D_HandleTypeDef structure that contains
* the configuration information for GPU2D.
* @retval GPU2D Error Code
*/
uint32_t HAL_GPU2D_GetError(GPU2D_HandleTypeDef const *const hgpu2d)
{
return hgpu2d->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* GPU2D */
#endif /* HAL_GPU2D_MODULE_ENABLED */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpu2d.c
|
C
|
apache-2.0
| 23,629
|
/**
******************************************************************************
* @file stm32u5xx_hal_gtzc.c
* @author MCD Application Team
* @brief GTZC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of GTZC peripheral:
* + TZSC Initialization and Configuration functions
* + TZSC-MPCWM Initialization and Configuration functions
* + MPCBB Initialization and Configuration functions
* + TZSC, TZSC-MPCWM and MPCBB Lock functions
* + TZIC Initialization and Configuration functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### GTZC main features #####
==============================================================================
[..]
(+) Global TrustZone Controller (GTZC) composed of three sub-blocks:
(++) TZSC: TrustZone security controller
This sub-block defines the secure/privileged state of master and slave
peripherals. It also controls the secure/privileged state of subregions
for the watermark memory peripheral controller (MPCWM).
(++) MPCBB: Block-Based memory protection controller
This sub-block defines the secure/privileged state of all blocks
(512-byte pages) of the associated SRAM.
(++) TZIC: TrustZone illegal access controller
This sub-block gathers all illegal access events in the system and
generates a secure interrupt towards NVIC.
(+) These sub-blocks are used to configure TrustZone system security in
a product having bus agents with programmable-security and privileged
attributes (securable) such as:
(++) on-chip RAM with programmable secure and/or privilege blocks (pages)
(++) AHB and APB peripherals with programmable security and/or privilege access
(++) AHB master granted as secure and/or privilege
(++) off-chip memories with secure and/or privilege areas
[..]
(+) TZIC accessible only with secure privileged transactions.
(+) Secure and non-secure access supported for privileged and unprivileged
part of TZSC and MPCBB
(+) Set of registers to define product security settings:
(++) Secure and privilege blocks for internal memories
(++) Secure and privilege regions for external memories
(++) Secure and privileged access mode for securable peripherals
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The GTZC HAL driver can be used as follows:
(#) Configure or get back securable peripherals attributes using
HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
(#) Configure or get back MPCWM memories attributes using
HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes()
(#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
HAL_GTZC_TZSC_GetLock()
(#) Configure or get back MPCBB memories complete configuration using
HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem()
(#) Configure or get back MPCBB memories attributes using
HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes()
(#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() /
HAL_GTZC_MPCBB_GetLock()
(#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() /
HAL_GTZC_MPCBB_GetLockConfig()
(#) Illegal access detection can be configured through TZIC sub-block using
following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
(#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
HAL_GTZC_TZIC_ClearFlag() functions
(#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler()
and user can add his own code using HAL_GTZC_TZIC_Callback()
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup GTZC GTZC
* @brief GTZC HAL module driver
* @{
*/
#ifdef HAL_GTZC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup GTZC_Private_Constants GTZC Private Constants
* @{
*/
/* Definitions for TZSC_MPCWM */
#define TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */
#define TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */
#define TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
#define TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */
#define TZSC_MPCWM5_MEM_SIZE 0x10000000U /* 256MB max size */
#if defined (HSPI1)
#define TZSC_MPCWM6_MEM_SIZE 0x10000000U /* 256MB max size */
#endif /* HSPI1 */
/* Definitions for GTZC TZSC & TZIC ALL register values */
/* TZSC1 / TZIC1 instances */
#if defined(STM32U599xx) || defined(STM32U595xx) || defined(STM32U5A9xx) || defined (STM32U5A5xx)
#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL)
#define TZSC1_SECCFGR2_ALL (0x000007FFUL)
#define TZSC1_SECCFGR3_ALL (0x0FFFFFFFUL)
#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL)
#define TZSC1_PRIVCFGR2_ALL (0x000007FFUL)
#define TZSC1_PRIVCFGR3_ALL (0x0FFFFFFFUL)
#define TZIC1_IER1_ALL (0x00EFFFFFUL)
#define TZIC1_IER2_ALL (0x000007FFUL)
#define TZIC1_IER3_ALL (0x0FFFFFFFUL)
#define TZIC1_IER4_ALL (0xFF1FC01FUL)
#define TZIC1_FCR1_ALL (0x00EFFFFFUL)
#define TZIC1_FCR2_ALL (0x000007FFUL)
#define TZIC1_FCR3_ALL (0x0FFFFFFFUL)
#define TZIC1_FCR4_ALL (0xFF1FC01FUL)
#else
#define TZSC1_SECCFGR1_ALL (0x001FFFFFUL)
#define TZSC1_SECCFGR2_ALL (0x000001FFUL)
#define TZSC1_SECCFGR3_ALL (0x007FFFFFUL)
#define TZSC1_PRIVCFGR1_ALL (0x001FFFFFUL)
#define TZSC1_PRIVCFGR2_ALL (0x000001FFUL)
#define TZSC1_PRIVCFGR3_ALL (0x007FFFFFUL)
#define TZIC1_IER1_ALL (0x001FFFFFUL)
#define TZIC1_IER2_ALL (0x000001FFUL)
#define TZIC1_IER3_ALL (0x007FFFFFUL)
#define TZIC1_IER4_ALL (0x3F0FC01FUL)
#define TZIC1_FCR1_ALL (0x001FFFFFUL)
#define TZIC1_FCR2_ALL (0x000001FFUL)
#define TZIC1_FCR3_ALL (0x007FFFFFUL)
#define TZIC1_FCR4_ALL (0x3F0FC01FUL)
#endif /* STM32U599xx || STM32U595xx || STM32U5A9xx || STM32U5A5xx */
/* TZSC2 / TZIC2 instances */
#define TZSC2_SECCFGR1_ALL (0x00001BFFUL)
#define TZSC2_PRIVCFGR1_ALL (0x00001BFFUL)
#define TZIC2_IER1_ALL (0x00001BFFUL)
#define TZIC2_IER2_ALL (0x0300C07FUL)
#define TZIC2_FCR1_ALL (0x00001BFFUL)
#define TZIC2_FCR2_ALL (0x0300C07FUL)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GTZC_Private_Macros GTZC Private Macros
* @{
*/
#define IS_ADDRESS_IN(mem, address)\
( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
&& ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
|| ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
&& ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
#define IS_ADDRESS_IN_S(mem, address)\
( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
&& ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
#define IS_ADDRESS_IN_NS(mem, address)\
( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
&& ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
#define GTZC_BASE_ADDRESS(mem)\
( mem ## _BASE )
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GTZC_Exported_Functions GTZC Exported Functions
* @{
*/
/** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions
* @brief TZSC Configuration functions
*
@verbatim
==============================================================================
##### TZSC Configuration functions #####
==============================================================================
[..]
This section provides functions allowing to configure TZSC
TZSC: TrustZone Security Controller
@endverbatim
* @{
*/
/**
* @brief Configure TZSC on a single peripheral or on all peripherals.
* @note Secure and non-secure attributes can only be set from the secure
* state when the system implements the security (TZEN=1).
* @note Privilege and non-privilege attributes can only be set from the
* privilege state when TZEN=0 or TZEN=1
* @note Security and privilege attributes can be set independently.
* @note Default state is non-secure and unprivileged access allowed.
* @param PeriphId Peripheral identifier
* This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
* Use GTZC_PERIPH_ALL to select all peripherals.
* @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
uint32_t PeriphAttributes)
{
uint32_t register_address;
/* check entry parameters */
if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
|| (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
|| (((PeriphId & GTZC_PERIPH_ALL) != 0U)
&& (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
{
/* special case where same attributes are applied to all peripherals */
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* secure configuration */
if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
{
SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
SET_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL);
}
else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
{
CLEAR_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
CLEAR_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
CLEAR_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
CLEAR_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL);
}
else
{
/* do nothing */
}
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* privilege configuration */
if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
{
SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
SET_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL);
}
else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
{
CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
CLEAR_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL);
}
else
{
/* do nothing */
}
}
else
{
/* common case where only one peripheral is configured */
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* secure configuration */
register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1)
+ (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
{
SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
}
else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
{
CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
}
else
{
/* do nothing */
}
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* privilege configuration */
register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1)
+ (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
{
SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
}
else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
{
CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
}
else
{
/* do nothing */
}
}
return HAL_OK;
}
/**
* @brief Get TZSC configuration on a single peripheral or on all peripherals.
* @param PeriphId Peripheral identifier.
* This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
* Use GTZC_PERIPH_ALL to select all peripherals.
* @param PeriphAttributes Peripheral attribute pointer.
* This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes.
* If PeriphId target a single peripheral, pointer on a single element.
* If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of
* GTZC_TZSC_PERIPH_NUMBER elements is to be provided.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
uint32_t *PeriphAttributes)
{
uint32_t i;
uint32_t reg_value;
uint32_t register_address;
/* check entry parameters */
if ((PeriphAttributes == NULL)
|| (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
|| (((PeriphId & GTZC_PERIPH_ALL) != 0U)
&& (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
{
/* get secure configuration: read each register and deploy each bit value
* of corresponding index in the destination array
*/
reg_value = READ_REG(GTZC_TZSC1->SECCFGR1);
for (i = 0U; i < 32U; i++)
{
if (((reg_value & (1UL << i)) >> i) != 0U)
{
PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
}
else
{
PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
}
}
reg_value = READ_REG(GTZC_TZSC1->SECCFGR2);
for (i = 32U; i < 64U; i++)
{
if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
{
PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
}
else
{
PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
}
}
reg_value = READ_REG(GTZC_TZSC1->SECCFGR3);
for (i = 64U; i < 96U; i++)
{
if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
{
PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
}
else
{
PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
}
}
reg_value = READ_REG(GTZC_TZSC2->SECCFGR1);
for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
{
if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U)
{
PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
}
else
{
PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
}
}
/* get privilege configuration: read each register and deploy each bit value
* of corresponding index in the destination array
*/
reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1);
for (i = 0U; i < 32U; i++)
{
if (((reg_value & (1UL << i)) >> i) != 0U)
{
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
}
else
{
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
}
}
reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2);
for (i = 32U; i < 64U; i++)
{
if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
{
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
}
else
{
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
}
}
reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3);
for (i = 64U; i < 96U; i++)
{
if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
{
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
}
else
{
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
}
}
reg_value = READ_REG(GTZC_TZSC2->PRIVCFGR1);
for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
{
if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U)
{
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
}
else
{
PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
}
}
}
else
{
/* common case where only one peripheral is configured */
/* secure configuration */
register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1)
+ (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
if (((READ_BIT(*(__IO uint32_t *)register_address,
1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
!= 0U)
{
*PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
}
else
{
*PeriphAttributes = GTZC_TZSC_PERIPH_NSEC;
}
/* privilege configuration */
register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1)
+ (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
if (((READ_BIT(*(__IO uint32_t *)register_address,
1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
!= 0U)
{
*PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
}
else
{
*PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV;
}
}
return HAL_OK;
}
/**
* @}
*/
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions
* @brief MPCWM Configuration functions
*
@verbatim
==============================================================================
##### MPCWM Configuration functions #####
==============================================================================
[..]
This section provides functions allowing to configure MPCWM
MPCWM is Memory Protection Controller WaterMark
@endverbatim
* @{
*/
/**
* @brief Configure a TZSC-MPCWM area.
* @param MemBaseAddress WM identifier.
* @param pMPCWM_Desc TZSC-MPCWM descriptor pointer.
* The structure description is available in @ref GTZC_Exported_Types.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
const MPCWM_ConfigTypeDef *pMPCWM_Desc)
{
uint32_t register_address;
uint32_t reg_value;
uint32_t size;
/* granularity value depends on selected memory */
uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
/* check entry parameters */
if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
|| (((MemBaseAddress == FMC_BANK3) || (MemBaseAddress == BKPSRAM_BASE))
&& (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
|| ((pMPCWM_Desc->Offset % granularity) != 0U)
|| ((pMPCWM_Desc->Length % granularity) != 0U))
{
return HAL_ERROR;
}
/* check descriptor content vs. memory capacity */
switch (MemBaseAddress)
{
case OCTOSPI1_BASE:
size = TZSC_MPCWM1_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
{
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
}
else
{
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
* (Parameter already checked)
*/
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
}
break;
case FMC_BANK1:
size = TZSC_MPCWM1_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
{
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
}
else
{
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
* (Parameter already checked)
*/
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
}
break;
case FMC_BANK3:
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
* (Parameter already checked)
*/
size = TZSC_MPCWM3_MEM_SIZE;
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
break;
case BKPSRAM_BASE:
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
* (Parameter already checked)
*/
size = TZSC_MPCWM4_MEM_SIZE;
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
break;
case OCTOSPI2_BASE:
size = TZSC_MPCWM5_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
{
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
}
else
{
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
* (Parameter already checked)
*/
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
}
break;
#if defined (HSPI1)
case HSPI1_BASE:
size = TZSC_MPCWM6_MEM_SIZE;
if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
{
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR);
}
else
{
/* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
* (Parameter already checked)
*/
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR);
}
break;
#endif /* HSPI1 */
default:
return HAL_ERROR;
break;
}
if ((pMPCWM_Desc->Offset > size)
|| ((pMPCWM_Desc->Offset
+ pMPCWM_Desc->Length)
> size))
{
return HAL_ERROR;
}
/* Write watermark start and length value */
reg_value = ((pMPCWM_Desc->Offset / granularity)
<< GTZC_TZSC_MPCWMR_SUBZ_START_Pos) & GTZC_TZSC_MPCWMR_SUBZ_START_Msk;
reg_value |= ((pMPCWM_Desc->Length / granularity)
<< GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk;
MODIFY_REG(*(__IO uint32_t *)register_address, GTZC_TZSC_MPCWMR_SUBZ_START_Msk | \
GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk, reg_value);
/* Write watermark configuration value */
reg_value = (pMPCWM_Desc->Attribute << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) | \
pMPCWM_Desc->Lock | \
pMPCWM_Desc->AreaStatus;
MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SEC | \
GTZC_TZSC_MPCWM_CFGR_SRLOCK | GTZC_TZSC_MPCWM_CFGR_SREN), \
reg_value);
return HAL_OK;
}
/**
* @brief Get a TZSC-MPCWM area configuration.
* @param MemBaseAddress WM identifier.
* @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
* The structure description is available in @ref GTZC_Exported_Types.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,
MPCWM_ConfigTypeDef *pMPCWM_Desc)
{
uint32_t register_address;
uint32_t reg_value;
uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
/* firstly take care of the first area, present on all MPCWM sub-blocks */
switch (MemBaseAddress)
{
case OCTOSPI1_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR);
break;
case FMC_BANK1:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR);
break;
case FMC_BANK3:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR);
break;
case BKPSRAM_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR);
break;
case OCTOSPI2_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR);
break;
#if defined (HSPI1)
case HSPI1_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR);
break;
#endif /* HSPI1 */
default:
return HAL_ERROR;
break;
}
/* read register and update the descriptor for first area*/
reg_value = READ_REG(*(__IO uint32_t *)register_address);
pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1;
pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
>> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
pMPCWM_Desc[0].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
>> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
/* read configuration register and update the descriptor for first area*/
reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
if ((MemBaseAddress != FMC_BANK3) && (MemBaseAddress != BKPSRAM_BASE))
{
/* Here MemBaseAddress = OCTOSPI1_BASE, OCTOSPI2_BASE
* or FMC_BANK1 (already checked)
* Now take care of the second area, present on these sub-blocks
*/
switch (MemBaseAddress)
{
case OCTOSPI1_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
break;
case FMC_BANK1:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
break;
case OCTOSPI2_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR);
break;
#if defined (HSPI1)
case HSPI1_BASE:
register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR);
break;
#endif /* HSPI1 */
default:
return HAL_ERROR;
break;
}
/* read register and update the descriptor for second area*/
reg_value = READ_REG(*(__IO uint32_t *)register_address);
pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2;
pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
>> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
pMPCWM_Desc[1].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
>> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
/* read configuration register and update the descriptor for second area*/
reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
pMPCWM_Desc[1].Attribute = reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
GTZC_TZSC_MPCWM_CFGR_SEC);
pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions
* @brief TZSC Lock functions
*
@verbatim
==============================================================================
##### TZSC Lock functions #####
==============================================================================
[..]
This section provides functions allowing to manage the TZSC (TrustZone
Security Controller) lock. It includes lock enable, and current value read.
@endverbatim
* @{
*/
/**
* @brief Lock TZSC configuration.
* @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx
* registers until next reset
* @param TZSC_Instance TZSC sub-block instance.
*/
void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
{
SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
}
/**
* @brief Get TZSC configuration lock state.
* @param TZSC_Instance TZSC sub-block instance.
* @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
*/
uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance)
{
return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
}
/**
* @}
*/
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions
* @brief MPCBB Configuration functions
*
@verbatim
==============================================================================
##### MPCBB Configuration functions #####
==============================================================================
[..]
This section provides functions allowing to configure MPCBB
MPCBB is Memory Protection Controller Block Base
@endverbatim
* @{
*/
/**
* @brief Set a complete MPCBB configuration on the SRAM passed as parameter.
* @param MemBaseAddress MPCBB identifier.
* @param pMPCBB_desc pointer to MPCBB descriptor.
* The structure description is available in @ref GTZC_Exported_Types.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
const MPCBB_ConfigTypeDef *pMPCBB_desc)
{
GTZC_MPCBB_TypeDef *mpcbb_ptr;
uint32_t mem_size;
uint32_t size_in_superblocks;
uint32_t i;
/* check entry parameters */
#if defined (SRAM5_BASE)
if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)))
|| ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
&& (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
|| ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
&& (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
{
return HAL_ERROR;
}
#else
if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)))
|| ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
&& (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
|| ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
&& (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
{
return HAL_ERROR;
}
#endif /* SRAM5_BASE */
if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB1;
mem_size = GTZC_MEM_SIZE(SRAM1);
}
else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB2;
mem_size = GTZC_MEM_SIZE(SRAM2);
}
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB3;
mem_size = GTZC_MEM_SIZE(SRAM3);
}
#if defined (SRAM5_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB4;
mem_size = GTZC_MEM_SIZE(SRAM4);
}
else
{
/* Here MemBaseAddress is inside SRAM5 (parameter already checked) */
mpcbb_ptr = GTZC_MPCBB5;
mem_size = GTZC_MEM_SIZE(SRAM5);
}
#else
else
{
/* Here MemBaseAddress is inside SRAM4 (parameter already checked) */
mpcbb_ptr = GTZC_MPCBB4;
mem_size = GTZC_MEM_SIZE(SRAM4);
}
#endif /* SRAM5_BASE */
/* translate mem_size in number of super-blocks */
size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
/* write PRIVCFGR register information */
for (i = 0U; i < size_in_superblocks; i++)
{
WRITE_REG(mpcbb_ptr->PRIVCFGR[i],
pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]);
}
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
uint32_t size_mask;
uint32_t reg_value;
/* write SECCFGR register information */
for (i = 0U; i < size_in_superblocks; i++)
{
WRITE_REG(mpcbb_ptr->SECCFGR[i],
pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
}
#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
if (size_in_superblocks >= 32U)
{
size_mask = 0xFFFFFFFFU;
MODIFY_REG(mpcbb_ptr->CFGLOCKR2, 0x000FFFFFUL, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1]);
}
else
#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
{
size_mask = (1UL << (size_in_superblocks & 0x1FU)) - 1U;
}
/* limitation: code not portable with memory > 512K */
MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
/* write InvertSecureState and SecureRWIllegalMode properties */
reg_value = pMPCBB_desc->InvertSecureState;
reg_value |= pMPCBB_desc->SecureRWIllegalMode;
/* write configuration and lock register information */
MODIFY_REG(mpcbb_ptr->CR,
GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
return HAL_OK;
}
/**
* @brief Get a complete MPCBB configuration on the SRAM passed as parameter.
* @param MemBaseAddress MPCBB identifier.
* @param pMPCBB_desc pointer to a MPCBB descriptor.
* The structure description is available in @ref GTZC_Exported_Types.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
MPCBB_ConfigTypeDef *pMPCBB_desc)
{
GTZC_MPCBB_TypeDef *mpcbb_ptr;
uint32_t mem_size;
uint32_t size_in_superblocks;
uint32_t i;
/* check entry parameters */
if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
&& !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
#if defined (SRAM5_BASE)
&& !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
#endif /* SRAM5_BASE */
)
{
return HAL_ERROR;
}
/* read InvertSecureState and SecureRWIllegalMode properties */
/* assume their Position/Mask is identical for all sub-blocks */
if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB1;
mem_size = GTZC_MEM_SIZE(SRAM1);
}
else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB2;
mem_size = GTZC_MEM_SIZE(SRAM2);
}
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB3;
mem_size = GTZC_MEM_SIZE(SRAM3);
}
#if defined (SRAM5_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
mpcbb_ptr = GTZC_MPCBB4;
mem_size = GTZC_MEM_SIZE(SRAM4);
}
else
{
mpcbb_ptr = GTZC_MPCBB5;
mem_size = GTZC_MEM_SIZE(SRAM5);
}
#else
else
{
mpcbb_ptr = GTZC_MPCBB4;
mem_size = GTZC_MEM_SIZE(SRAM4);
}
#endif /* SRAM5_BASE */
/* translate mem_size in number of super-blocks */
size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
uint32_t reg_value;
uint32_t size_mask;
/* read configuration and lock register information */
reg_value = READ_REG(mpcbb_ptr->CR);
pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
if (size_in_superblocks >= 32U)
{
size_mask = 0xFFFFFFFFU;
#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1] = READ_REG(mpcbb_ptr->CFGLOCKR2)
& 0x000FFFFFUL;
#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
}
else
{
size_mask = (1UL << size_in_superblocks) - 1U;
}
/* limitation: code not portable with memory > 512K */
pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1)
& size_mask;
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* read SECCFGR / PRIVCFGR registers information */
for (i = 0U; i < size_in_superblocks; i++)
{
pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i];
pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i];
}
return HAL_OK;
}
/**
* @brief Set a MPCBB attribute configuration on the SRAM passed as parameter
* for a number of blocks.
* @param MemAddress MPCBB identifier, and start block to configure
* (must be 512 Bytes aligned).
* @param NbBlocks Number of blocks to configure
* (Block size is 512 Bytes).
* @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
* with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
* and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
uint32_t NbBlocks,
const uint32_t *pMemAttributes)
{
GTZC_MPCBB_TypeDef *mpcbb_ptr;
uint32_t base_address;
uint32_t end_address;
uint32_t block_start;
uint32_t offset_reg_start;
uint32_t offset_bit_start;
uint32_t i;
uint32_t do_attr_change;
/* firstly check that MemAddress is well 512 Bytes aligned */
if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
{
return HAL_ERROR;
}
/* check entry parameters and deduce physical base address */
end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB1;
base_address = SRAM1_BASE_NS;
}
else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB1;
base_address = SRAM1_BASE_S;
}
else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB2;
base_address = SRAM2_BASE_NS;
}
else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB2;
base_address = SRAM2_BASE_S;
}
else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB3;
base_address = SRAM3_BASE_NS;
}
else if (((IS_ADDRESS_IN_S(SRAM3, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM3, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB3;
base_address = SRAM3_BASE_S;
}
else if (((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM4, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB4;
base_address = SRAM4_BASE_NS;
}
else if (((IS_ADDRESS_IN_S(SRAM4, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM4, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB4;
base_address = SRAM4_BASE_S;
}
#if defined (SRAM5_BASE)
else if (((IS_ADDRESS_IN_NS(SRAM5, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM5, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB5;
base_address = SRAM5_BASE_NS;
}
else if (((IS_ADDRESS_IN_S(SRAM5, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM5, end_address))) != 0U)
{
mpcbb_ptr = GTZC_MPCBB5;
base_address = SRAM5_BASE_S;
}
#endif /* SRAM5_BASE */
else
{
return HAL_ERROR;
}
/* get start coordinates of the configuration */
block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
offset_reg_start = block_start / 32U;
offset_bit_start = block_start % 32U;
for (i = 0U; i < NbBlocks; i++)
{
/* Indicate change done for protection attributes */
do_attr_change = 0U;
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* secure configuration */
if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC)
{
SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
do_attr_change = 1U;
}
else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC)
{
CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
do_attr_change = 1U;
}
else
{
/* nothing to do */
}
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/* privilege configuration */
if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV)
{
SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
}
else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV)
{
CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U));
}
else
{
/* if no change is done for security and privilege attributes: break the loop */
if (do_attr_change == 0U)
{
break;
}
}
offset_bit_start++;
if (offset_bit_start == 32U)
{
offset_bit_start = 0U;
offset_reg_start++;
}
}
/* an unexpected value in pMemAttributes array leads to error status */
if (i != NbBlocks)
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Get a MPCBB attribute configuration on the SRAM passed as parameter
* for a number of blocks.
* @param MemAddress MPCBB identifier, and start block to get configuration
* (must be 512 Bytes aligned).
* @param NbBlocks Number of blocks to get configuration.
* @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
* with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
* and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
uint32_t NbBlocks,
uint32_t *pMemAttributes)
{
GTZC_MPCBB_TypeDef *mpcbb_ptr;
uint32_t base_address;
uint32_t end_address;
uint32_t block_start;
uint32_t offset_reg_start;
uint32_t offset_bit_start;
uint32_t i;
/* firstly check that MemAddress is well 512 Bytes aligned */
if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
{
return HAL_ERROR;
}
/* check entry parameters and deduce physical base address */
end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM1, end_address)))
{
mpcbb_ptr = GTZC_MPCBB1_NS;
base_address = SRAM1_BASE_NS;
}
else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM1, end_address)))
{
mpcbb_ptr = GTZC_MPCBB1_S;
base_address = SRAM1_BASE_S;
}
else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM2, end_address)))
{
mpcbb_ptr = GTZC_MPCBB2_NS;
base_address = SRAM2_BASE_NS;
}
else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM2, end_address)))
{
mpcbb_ptr = GTZC_MPCBB2_S;
base_address = SRAM2_BASE_S;
}
else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM3, end_address)))
{
mpcbb_ptr = GTZC_MPCBB3_NS;
base_address = SRAM3_BASE_NS;
}
else if ((IS_ADDRESS_IN_S(SRAM3, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM3, end_address)))
{
mpcbb_ptr = GTZC_MPCBB3_S;
base_address = SRAM3_BASE_S;
}
else if ((IS_ADDRESS_IN_NS(SRAM4, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM4, end_address)))
{
mpcbb_ptr = GTZC_MPCBB4_NS;
base_address = SRAM4_BASE_NS;
}
else if ((IS_ADDRESS_IN_S(SRAM4, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM4, end_address)))
{
mpcbb_ptr = GTZC_MPCBB4_S;
base_address = SRAM4_BASE_S;
}
#if defined (SRAM5_BASE)
else if ((IS_ADDRESS_IN_NS(SRAM5, MemAddress))
&& (IS_ADDRESS_IN_NS(SRAM5, end_address)))
{
mpcbb_ptr = GTZC_MPCBB5_NS;
base_address = SRAM5_BASE_NS;
}
else if ((IS_ADDRESS_IN_S(SRAM5, MemAddress))
&& (IS_ADDRESS_IN_S(SRAM5, end_address)))
{
mpcbb_ptr = GTZC_MPCBB5_S;
base_address = SRAM5_BASE_S;
}
#endif /* SRAM5_BASE */
else
{
return HAL_ERROR;
}
/* get start coordinates of the configuration */
block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
offset_reg_start = block_start / 32U;
offset_bit_start = block_start % 32U;
for (i = 0U; i < NbBlocks; i++)
{
pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U))
>> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK;
pMemAttributes[i] |= (READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1UL << (offset_bit_start % 32U))
>> (offset_bit_start % 32U)) | GTZC_ATTR_PRIV_MASK;
offset_bit_start++;
if (offset_bit_start == 32U)
{
offset_bit_start = 0U;
offset_reg_start++;
}
}
return HAL_OK;
}
#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
* @brief Lock MPCBB super-blocks on the SRAM passed as parameter.
* @param MemAddress MPCBB start-address of super-block to configure
* (must be 16KBytes aligned).
* @param NbSuperBlocks Number of super-blocks to configure.
* @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
* with for each element:
* value 0 super-block is unlocked, value 1 super-block is locked
* (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
* GTZC_MCPBB_SUPERBLOCK_LOCKED values).
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
const uint32_t *pLockAttributes)
{
__IO uint32_t *reg_mpcbb;
uint32_t base_address;
uint32_t superblock_start;
uint32_t offset_bit_start;
uint32_t i = 0U;
/* firstly check that MemAddress is well 16KBytes aligned */
if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
{
return HAL_ERROR;
}
/* check entry parameters */
if ((IS_ADDRESS_IN(SRAM1, MemAddress))
&& (IS_ADDRESS_IN(SRAM1, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM1);
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
}
else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
&& (IS_ADDRESS_IN(SRAM2, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM2);
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
}
else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
&& (IS_ADDRESS_IN(SRAM3, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM3);
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
}
else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
&& (IS_ADDRESS_IN(SRAM4, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM4);
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1;
}
#if defined (SRAM5_BASE)
else if ((IS_ADDRESS_IN(SRAM5, MemAddress))
&& (IS_ADDRESS_IN(SRAM5, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM5);
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1;
}
#endif /* SRAM5_BASE */
else
{
return HAL_ERROR;
}
/* get start coordinates of the configuration */
superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
offset_bit_start = superblock_start % 32U;
/* First 32 super-blocks */
while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U))
{
if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
{
SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
}
else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
{
CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
}
else
{
break;
}
offset_bit_start++;
i++;
}
#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
if ((NbSuperBlocks > 32U) || (superblock_start >= 32U))
{
/* Point to second configuration lock register */
reg_mpcbb++;
/* Remaining super-blocks */
for (; i < NbSuperBlocks; i++)
{
if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
{
SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
}
else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
{
CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
}
else
{
break;
}
offset_bit_start++;
}
}
#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
/* an unexpected value in pLockAttributes array leads to an error status */
if (i != NbSuperBlocks)
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter.
* @param MemAddress MPCBB start-address of super-block to get configuration
* (must be 16KBytes aligned).
* @param NbSuperBlocks Number of super-blocks to get configuration.
* @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
* with for each element:
* value 0 super-block is unlocked, value 1 super-block is locked
* (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
* GTZC_MCPBB_SUPERBLOCK_LOCKED values).
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
uint32_t NbSuperBlocks,
uint32_t *pLockAttributes)
{
__IO uint32_t *reg_mpcbb;
uint32_t base_address;
uint32_t superblock_start;
uint32_t offset_bit_start;
uint32_t i = 0U;
/* firstly check that MemAddress is well 16KBytes aligned */
if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
{
return HAL_ERROR;
}
/* check entry parameters */
if ((IS_ADDRESS_IN(SRAM1, MemAddress))
&& (IS_ADDRESS_IN(SRAM1, (MemAddress
+ (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM1);
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
}
else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
&& (IS_ADDRESS_IN(SRAM2, (MemAddress
+ (NbSuperBlocks
* GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM2);
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
}
else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
&& (IS_ADDRESS_IN(SRAM3, (MemAddress
+ (NbSuperBlocks
* GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM3);
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
}
else if ((IS_ADDRESS_IN(SRAM4, MemAddress))
&& (IS_ADDRESS_IN(SRAM4, (MemAddress
+ (NbSuperBlocks
* GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM4);
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1;
}
#if defined (SRAM5_BASE)
else if ((IS_ADDRESS_IN(SRAM5, MemAddress))
&& (IS_ADDRESS_IN(SRAM5, (MemAddress
+ (NbSuperBlocks
* GTZC_MPCBB_SUPERBLOCK_SIZE)
- 1U))))
{
base_address = GTZC_BASE_ADDRESS(SRAM5);
reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1;
}
#endif /* SRAM5_BASE */
else
{
return HAL_ERROR;
}
/* Get start coordinates of the configuration */
superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
offset_bit_start = superblock_start % 32U;
while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U))
{
pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U)))
>> (offset_bit_start % 32U);
offset_bit_start++;
i++;
}
#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk)
if ((NbSuperBlocks > 32U) || (superblock_start >= 32U))
{
/* Point to second configuration lock register */
reg_mpcbb++;
/* Remaining super-blocks */
for (; i < NbSuperBlocks; i++)
{
pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U)))
>> (offset_bit_start % 32U);
offset_bit_start++;
}
}
#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */
return HAL_OK;
}
/**
* @brief Lock a MPCBB configuration on the SRAM base address passed as parameter.
* @note This functions locks the control register of the MPCBB until next reset.
* @param MemBaseAddress MPCBB identifier.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
{
/* check entry parameters */
if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#if defined (SRAM5_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
{
SET_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#endif /* SRAM5_BASE */
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
* @param MemBaseAddress MPCBB identifier.
* @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON).
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
uint32_t *pLockState)
{
/* check entry parameters */
if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#if defined (SRAM5_BASE)
else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress))
{
*pLockState = READ_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
}
#endif /* SRAM5_BASE */
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions
* @brief TZIC Configuration and Control functions
*
@verbatim
==============================================================================
##### TZIC Configuration and Control functions #####
==============================================================================
[..]
This section provides functions allowing to configure and control TZIC
TZIC is Trust Zone Interrupt Controller
@endverbatim
* @{
*/
/**
* @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals.
* @param PeriphId Peripheral identifier.
* This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
* Use GTZC_PERIPH_ALL to select all peripherals.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
{
uint32_t register_address;
/* check entry parameters */
if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
|| (((PeriphId & GTZC_PERIPH_ALL) != 0U)
&& (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
{
/* same configuration is applied to all peripherals */
WRITE_REG(GTZC_TZIC1->IER1, 0U);
WRITE_REG(GTZC_TZIC1->IER2, 0U);
WRITE_REG(GTZC_TZIC1->IER3, 0U);
WRITE_REG(GTZC_TZIC1->IER4, 0U);
WRITE_REG(GTZC_TZIC2->IER1, 0U);
WRITE_REG(GTZC_TZIC2->IER2, 0U);
}
else
{
/* common case where only one peripheral is configured */
register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1)
+ (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
}
return HAL_OK;
}
/**
* @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals.
* @param PeriphId Peripheral identifier.
* This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
* Use GTZC_PERIPH_ALL to select all peripherals.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
{
uint32_t register_address;
/* check entry parameters */
if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
|| (((PeriphId & GTZC_PERIPH_ALL) != 0U)
&& (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
{
/* same configuration is applied to all peripherals */
WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL);
WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL);
WRITE_REG(GTZC_TZIC1->IER3, TZIC1_IER3_ALL);
WRITE_REG(GTZC_TZIC1->IER4, TZIC1_IER4_ALL);
WRITE_REG(GTZC_TZIC2->IER1, TZIC2_IER1_ALL);
WRITE_REG(GTZC_TZIC2->IER2, TZIC2_IER2_ALL);
}
else
{
/* common case where only one peripheral is configured */
register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1)
+ (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
}
return HAL_OK;
}
/**
* @brief Get TZIC flag on a single TZIC peripheral or on all peripherals.
* @param PeriphId Peripheral identifier.
* This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
* Use GTZC_PERIPH_ALL to select all peripherals.
* @param pFlag Pointer to the flags.
* If PeriphId target a single peripheral, pointer on a single element.
* If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array
* of GTZC_TZIC_PERIPH_NUMBER elements.
* Element content is either GTZC_TZIC_NO_ILA_EVENT
* or GTZC_TZSC_ILA_EVENT_PENDING.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
{
uint32_t i;
uint32_t reg_value;
uint32_t register_address;
/* check entry parameters */
if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
|| (((PeriphId & GTZC_PERIPH_ALL) != 0U)
&& (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
{
/* special case where it is applied to all peripherals */
reg_value = READ_REG(GTZC_TZIC1->SR1);
for (i = 0U; i < 32U; i++)
{
pFlag[i] = (reg_value & (1UL << i)) >> i;
}
reg_value = READ_REG(GTZC_TZIC1->SR2);
for (i = 32U; i < 64U; i++)
{
pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
}
reg_value = READ_REG(GTZC_TZIC1->SR3);
for (i = 64U; i < 96U; i++)
{
pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
}
reg_value = READ_REG(GTZC_TZIC1->SR4);
for (i = 96U; i < 128U; i++)
{
pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U);
}
reg_value = READ_REG(GTZC_TZIC2->SR1);
for (i = 128U; i < 160U; i++)
{
pFlag[i] = (reg_value & (1UL << (i - 128U))) >> (i - 128U);
}
reg_value = READ_REG(GTZC_TZIC2->SR2);
for (i = 160U; i < GTZC_TZIC_PERIPH_NUMBER; i++)
{
pFlag[i] = (reg_value & (1UL << (i - 160U))) >> (i - 160U);
}
}
else
{
/* common case where only one peripheral is concerned */
register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->SR1)
+ (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
*pFlag = READ_BIT(*(__IO uint32_t *)register_address,
1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
}
return HAL_OK;
}
/**
* @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals.
* @param PeriphId Peripheral identifier.
* This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
* Use GTZC_PERIPH_ALL to select all peripherals.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
{
uint32_t register_address;
/* check entry parameters */
if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
|| (((PeriphId & GTZC_PERIPH_ALL) != 0U)
&& (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U)))
{
return HAL_ERROR;
}
if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
{
/* same configuration is applied to all peripherals */
WRITE_REG(GTZC_TZIC1->FCR1, TZIC1_FCR1_ALL);
WRITE_REG(GTZC_TZIC1->FCR2, TZIC1_FCR2_ALL);
WRITE_REG(GTZC_TZIC1->FCR3, TZIC1_FCR3_ALL);
WRITE_REG(GTZC_TZIC1->FCR4, TZIC1_FCR4_ALL);
WRITE_REG(GTZC_TZIC2->FCR1, TZIC2_FCR1_ALL);
WRITE_REG(GTZC_TZIC2->FCR2, TZIC2_FCR2_ALL);
}
else
{
/* common case where only one peripheral is configured */
register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->FCR1)
+ (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId));
SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions
* @brief IRQ related functions
*
@verbatim
==============================================================================
##### TZIC IRQ Handler and Callback functions #####
==============================================================================
[..]
This section provides functions allowing to treat ISR and provide user callback
@endverbatim
* @{
*/
/**
* @brief This function handles GTZC TZIC interrupt request.
* @retval None.
*/
void HAL_GTZC_IRQHandler(void)
{
uint32_t position;
uint32_t flag;
uint32_t ier_itsources;
uint32_t sr_flags;
/*********************************************************************/
/****************************** TZIC1 ******************************/
/*********************************************************************/
/* Get current IT Flags and IT sources value on 1st register of TZIC1 */
ier_itsources = READ_REG(GTZC_TZIC1_S->IER1);
sr_flags = READ_REG(GTZC_TZIC1_S->SR1);
/* Get Mask interrupt and then clear them */
flag = ier_itsources & sr_flags;
if (flag != 0U)
{
WRITE_REG(GTZC_TZIC1_S->FCR1, flag);
/* Loop on flag to check, which ones have been raised */
position = 0U;
while ((flag >> position) != 0U)
{
if ((flag & (1UL << position)) != 0U)
{
HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG1 | position);
}
/* Position bit to be updated */
position++;
}
}
/* Get current IT Flags and IT sources value on 2nd register of TZIC1 */
ier_itsources = READ_REG(GTZC_TZIC1_S->IER2);
sr_flags = READ_REG(GTZC_TZIC1_S->SR2);
/* Get Mask interrupt and then clear them */
flag = ier_itsources & sr_flags;
if (flag != 0U)
{
WRITE_REG(GTZC_TZIC1_S->FCR2, flag);
/* Loop on flag to check, which ones have been raised */
position = 0U;
while ((flag >> position) != 0U)
{
if ((flag & (1UL << position)) != 0U)
{
HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG2 | position);
}
/* Position bit to be updated */
position++;
}
}
/* Get current IT Flags and IT sources value on 3rd register of TZIC1 */
ier_itsources = READ_REG(GTZC_TZIC1_S->IER3);
sr_flags = READ_REG(GTZC_TZIC1_S->SR3);
/* Get Mask interrupt and then clear them */
flag = ier_itsources & sr_flags;
if (flag != 0U)
{
WRITE_REG(GTZC_TZIC1_S->FCR3, flag);
/* Loop on flag to check, which ones have been raised */
position = 0U;
while ((flag >> position) != 0U)
{
if ((flag & (1UL << position)) != 0U)
{
HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG3 | position);
}
/* Position bit to be updated */
position++;
}
}
/* Get current IT Flags and IT sources value on 4th register of TZIC1 */
ier_itsources = READ_REG(GTZC_TZIC1_S->IER4);
sr_flags = READ_REG(GTZC_TZIC1_S->SR4);
/* Get Mask interrupt and then clear them */
flag = ier_itsources & sr_flags;
if (flag != 0U)
{
WRITE_REG(GTZC_TZIC1_S->FCR4, flag);
/* Loop on flag to check, which ones have been raised */
position = 0U;
while ((flag >> position) != 0U)
{
if ((flag & (1UL << position)) != 0U)
{
HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG4 | position);
}
/* Position bit to be updated */
position++;
}
}
/*********************************************************************/
/****************************** TZIC2 ******************************/
/*********************************************************************/
/* Get current IT Flags and IT sources value on 1st register of TZIC2 */
ier_itsources = READ_REG(GTZC_TZIC2_S->IER1);
sr_flags = READ_REG(GTZC_TZIC2_S->SR1);
/* Get Mask interrupt and then clear them */
flag = ier_itsources & sr_flags;
if (flag != 0U)
{
WRITE_REG(GTZC_TZIC2_S->FCR1, flag);
/* Loop on flag to check, which ones have been raised */
position = 0U;
while ((flag >> position) != 0U)
{
if ((flag & (1UL << position)) != 0U)
{
HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG1 | position);
}
/* Position bit to be updated */
position++;
}
}
/* Get current IT Flags and IT sources value on 2nd register of TZIC2 */
ier_itsources = READ_REG(GTZC_TZIC2_S->IER2);
sr_flags = READ_REG(GTZC_TZIC2_S->SR2);
/* Get Mask interrupt and then clear them */
flag = ier_itsources & sr_flags;
if (flag != 0U)
{
WRITE_REG(GTZC_TZIC2_S->FCR2, flag);
/* Loop on flag to check, which ones have been raised */
position = 0U;
while ((flag >> position) != 0U)
{
if ((flag & (1UL << position)) != 0U)
{
HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG2 | position);
}
/* Position bit to be updated */
position++;
}
}
}
/**
* @brief GTZC TZIC sub-block interrupt callback.
* @param PeriphId Peripheral identifier triggering the illegal access.
* This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId
* @retval None.
*/
__weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(PeriphId);
/* NOTE: This function should not be modified. When the callback is needed,
* the HAL_GTZC_TZIC_Callback is to be implemented in the user file
*/
}
/**
* @}
*/
#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @}
*/
#endif /*HAL_GTZC_MODULE_ENABLED*/
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c
|
C
|
apache-2.0
| 69,989
|
/**
******************************************************************************
* @file stm32u5xx_hal_hash.c
* @author MCD Application Team
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
* + Initialization and de-initialization methods
* + HASH or HMAC processing in polling mode
* + HASH or HMAC processing in interrupt mode
* + HASH or HMAC processing in DMA mode
* + Peripheral State methods
* + HASH or HMAC processing suspension/resumption
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The HASH HAL driver can be used as follows:
(#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
(##) Enable the HASH interface clock using __HASH_CLK_ENABLE()
(##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT())
(+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
(+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API
(##) When resorting to DMA-based APIs (e.g. HAL_HASH_xxx_Start_DMA())
(+++) Enable the DMAx interface clock using
__DMAx_CLK_ENABLE()
(+++) Configure and enable one DMA channel to manage data transfer from
memory to peripheral (input channel). Managing data transfer from
peripheral to memory can be performed only using CPU.
(+++) Associate the initialized DMA handle to the HASH DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
interrupt on the DMA channel: use
HAL_NVIC_SetPriority() and
HAL_NVIC_EnableIRQ()
(#)Initialize the HASH HAL using HAL_HASH_Init(). This function:
(##) resorts to HAL_HASH_MspInit() for low-level initialization,
(##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit.
(#)Three processing schemes are available:
(##) Polling mode: processing APIs are blocking functions
i.e. they process the data and wait till the digest computation is finished,
e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC
(##) Interrupt mode: processing APIs are not blocking functions
i.e. they process the data under interrupt,
e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC
(##) DMA mode: processing APIs are not blocking functions and the CPU is
not used for data transfer i.e. the data transfer is ensured by DMA,
e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA()
for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish()
is then required to retrieve the digest.
(#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is
initialized and processes the buffer fed in input. When the input data have all been
fed to the Peripheral, the digest computation can start.
(#)Multi-buffer processing is possible in polling, interrupt and DMA modes.
(##) In polling mode, only multi-buffer HASH processing is possible.
API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one.
User must resort to HAL_HASH_xxx_Accumulate_End() to enter the last one and retrieve as
well the computed digest.
(##) In interrupt mode, API HAL_HASH_xxx_Accumulate_IT() must be called for each input buffer,
except for the last one.
User must resort to HAL_HASH_xxx_Accumulate_End_IT() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
(+++) HASH processing: once initialization is done, MDMAT bit must be set
through __HAL_HASH_SET_MDMAT() macro.
From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer through the
same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASH_xxx_Finish().
(+++) HMAC processing (requires to resort to extended functions):
after initialization, the key and the first input buffer are entered
in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
starts step 2.
The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
point, the HMAC processing is still carrying out step 2.
Then, step 2 for the last input buffer and step 3 are carried out by a single call
to HAL_HMACEx_xxx_Step2_3_DMA().
The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish().
(#)Context swapping.
(##) Two APIs are available to suspend HASH or HMAC processing:
(+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode),
(+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA.
(##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows
to save in memory the Peripheral context. This context can be restored afterwards
to resume the HASH processing thanks to HAL_HASH_ContextRestoring().
(##) Once the HASH Peripheral has been restored to the same configuration as that at suspension
time, processing can be restarted with the same API call (same API, same handle,
same parameters) as done before the suspension. Relevant parameters to restart at
the proper location are internally saved in the HASH handle.
(#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
*** Remarks on message length ***
===================================
[..]
(#) HAL in interruption mode (interruptions driven)
(##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
This is why, for driver implementation simplicity's sake, user is requested to enter a message the
length of which is a multiple of 4 bytes.
(##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
to specify which bits to discard at the end of the complete message to process only the message bits
and not extra bits.
(##) If user needs to perform a hash computation of a large input buffer that is spread around various places
in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it becomes
necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
It is advised to the user to
(+++) achieve the first formatting operation by software then enter the data
(+++) while the Peripheral is processing the first input set, carry out the second formatting
operation by software, to be ready when DINIS occurs.
(+++) repeat step 2 until the whole message is processed.
[..]
(#) HAL in DMA mode
(##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis.
The same field described above in HASH_STR is used to specify which bits to discard at the end of the
DMA transfer to process only the message bits and not extra bits. Due to hardware implementation,
this is possible only at the end of the complete message. When several DMA transfers are needed to
enter the message, this is not applicable at the end of the intermediary transfers.
(##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive
chunks of data by software while the DMA transfer and processing is on-going for the first parts of
the message. Due to the 32-bit alignment required for the DMA transfer, it is underlined that the
software formatting operation is more complex than in the IT mode.
*** Callback registration ***
===================================
[..]
(#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use function HAL_HASH_RegisterCallback() to register a user callback.
(#) Function HAL_HASH_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : callback for input completion.
(+) DgstCpltCallback : callback for digest computation completion.
(+) ErrorCallback : callback for error.
(+) MspInitCallback : HASH MspInit.
(+) MspDeInitCallback : HASH MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) InCpltCallback : callback for input completion.
(+) DgstCpltCallback : callback for digest computation completion.
(+) ErrorCallback : callback for error.
(+) MspInitCallback : HASH MspInit.
(+) MspDeInitCallback : HASH MspDeInit.
(#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback()
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_HASH_Init
and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit
or HAL_HASH_Init function.
When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#if defined (HASH)
/** @defgroup HASH HASH
* @brief HASH HAL module driver.
* @{
*/
#ifdef HAL_HASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup HASH_Private_Constants HASH Private Constants
* @{
*/
/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status
* @{
*/
#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000U) /*!< DCAL not set after input data written in DIN register */
#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001U) /*!< DCAL set after input data written in DIN register */
/**
* @}
*/
/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers
* @{
*/
#define HASH_NUMBER_OF_CSR_REGISTERS 54U /*!< Number of Context Swap Registers */
/**
* @}
*/
/** @defgroup HASH_TimeOut_Value HASH TimeOut Value
* @{
*/
#define HASH_TIMEOUTVALUE 1000U /*!< Time-out value */
/**
* @}
*/
/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit
* @{
*/
#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20U /*!< Number of words below which DMA suspension is aborted */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup HASH_Private_Functions HASH Private Functions
* @{
*/
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void HASH_DMAError(DMA_HandleTypeDef *hdma);
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
uint32_t Timeout);
static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
/**
* @}
*/
/** @defgroup HASH_Exported_Functions HASH Exported Functions
* @{
*/
/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization, configuration and call-back functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the HASH according to the specified parameters
in the HASH_InitTypeDef and create the associated handle
(+) DeInitialize the HASH peripheral
(+) Initialize the HASH MCU Specific Package (MSP)
(+) DeInitialize the HASH MSP
[..] This section provides as well call back functions definitions for user
code to manage:
(+) Input data transfer to Peripheral completion
(+) Calculated digest retrieval completion
(+) Error management
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH according to the specified parameters in the
HASH_HandleTypeDef and create the associated handle.
* @note Only MDMAT and DATATYPE bits of HASH Peripheral are set by HAL_HASH_Init(),
* other configuration bits are set by HASH or HMAC processing APIs.
* @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for
* multi-buffer HASH processing, user needs to resort to
* __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the
* relevant APIs manage themselves the MDMAT bit.
* @param hhash HASH handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
{
/* Check the hash handle allocation */
if (hhash == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
if (hhash->State == HAL_HASH_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hhash->Lock = HAL_UNLOCKED;
/* Reset Callback pointers in HAL_HASH_STATE_RESET only */
hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation
completion callback */
hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
if (hhash->MspInitCallback == NULL)
{
hhash->MspInitCallback = HAL_HASH_MspInit;
}
/* Init the low level hardware */
hhash->MspInitCallback(hhash);
}
#else
if (hhash->State == HAL_HASH_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hhash->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_HASH_MspInit(hhash);
}
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
hhash->HashInCount = 0;
hhash->HashBuffSize = 0;
hhash->HashITCounter = 0;
hhash->NbWordsAlreadyPushed = 0;
/* Reset digest calculation bridle (MDMAT bit control) */
hhash->DigestCalculationDisable = RESET;
/* Set phase to READY */
hhash->Phase = HAL_HASH_PHASE_READY;
/* Reset suspension request flag */
hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
/* Set the data type bit */
MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
/* Reset MDMAT bit */
__HAL_HASH_RESET_MDMAT();
/* Reset HASH handle status */
hhash->Status = HAL_OK;
/* Set the HASH state to Ready */
hhash->State = HAL_HASH_STATE_READY;
/* Initialise the error code */
hhash->ErrorCode = HAL_HASH_ERROR_NONE;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the HASH peripheral.
* @param hhash HASH handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
{
/* Check the HASH handle allocation */
if (hhash == NULL)
{
return HAL_ERROR;
}
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Set the default HASH phase */
hhash->Phase = HAL_HASH_PHASE_READY;
/* Reset HashInCount, HashITCounter and HashBuffSize */
hhash->HashInCount = 0;
hhash->HashBuffSize = 0;
hhash->HashITCounter = 0;
/* Reset digest calculation bridle (MDMAT bit control) */
hhash->DigestCalculationDisable = RESET;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
if (hhash->MspDeInitCallback == NULL)
{
hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
}
/* DeInit the low level hardware */
hhash->MspDeInitCallback(hhash);
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_HASH_MspDeInit(hhash);
#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
/* Reset HASH handle status */
hhash->Status = HAL_OK;
/* Set the HASH state to Ready */
hhash->State = HAL_HASH_STATE_RESET;
/* Initialise the error code */
hhash->ErrorCode = HAL_HASH_ERROR_NONE;
/* Reset multi buffers accumulation flag */
hhash->Accumulation = 0U;
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the HASH MSP.
* @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* NOTE : This function should not be modified; when the callback is needed,
HAL_HASH_MspInit() can be implemented in the user file.
*/
}
/**
* @brief DeInitialize the HASH MSP.
* @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* NOTE : This function should not be modified; when the callback is needed,
HAL_HASH_MspDeInit() can be implemented in the user file.
*/
}
/**
* @brief Input data transfer complete call back.
* @note HAL_HASH_InCpltCallback() is called when the complete input message
* has been fed to the Peripheral. This API is invoked only when input data are
* entered under interruption or through DMA.
* @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
* HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
* to the Peripheral.
* @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* NOTE : This function should not be modified; when the callback is needed,
HAL_HASH_InCpltCallback() can be implemented in the user file.
*/
}
/**
* @brief Digest computation complete call back.
* @note HAL_HASH_DgstCpltCallback() is used under interruption, is not
* relevant with DMA.
* @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* NOTE : This function should not be modified; when the callback is needed,
HAL_HASH_DgstCpltCallback() can be implemented in the user file.
*/
}
/**
* @brief Error callback.
* @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...)
* to retrieve the error type.
* @param hhash HASH handle.
* @retval None
*/
__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* NOTE : This function should not be modified; when the callback is needed,
HAL_HASH_ErrorCallback() can be implemented in the user file.
*/
}
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User HASH Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hhash HASH handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
* @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
* @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
* @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
* @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
pHASH_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hhash);
if (HAL_HASH_STATE_READY == hhash->State)
{
switch (CallbackID)
{
case HAL_HASH_INPUTCPLT_CB_ID :
hhash->InCpltCallback = pCallback;
break;
case HAL_HASH_DGSTCPLT_CB_ID :
hhash->DgstCpltCallback = pCallback;
break;
case HAL_HASH_ERROR_CB_ID :
hhash->ErrorCallback = pCallback;
break;
case HAL_HASH_MSPINIT_CB_ID :
hhash->MspInitCallback = pCallback;
break;
case HAL_HASH_MSPDEINIT_CB_ID :
hhash->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (HAL_HASH_STATE_RESET == hhash->State)
{
switch (CallbackID)
{
case HAL_HASH_MSPINIT_CB_ID :
hhash->MspInitCallback = pCallback;
break;
case HAL_HASH_MSPDEINIT_CB_ID :
hhash->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hhash);
return status;
}
/**
* @brief Unregister a HASH Callback
* HASH Callback is redirected to the weak (surcharged) predefined callback
* @param hhash HASH handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID
* @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID
* @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID
* @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID
* @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hhash);
if (HAL_HASH_STATE_READY == hhash->State)
{
switch (CallbackID)
{
case HAL_HASH_INPUTCPLT_CB_ID :
hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */
break;
case HAL_HASH_DGSTCPLT_CB_ID :
hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation
completion callback */
break;
case HAL_HASH_ERROR_CB_ID :
hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */
break;
case HAL_HASH_MSPINIT_CB_ID :
hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
break;
case HAL_HASH_MSPDEINIT_CB_ID :
hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
break;
default :
/* Update the error code */
hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (HAL_HASH_STATE_RESET == hhash->State)
{
switch (CallbackID)
{
case HAL_HASH_MSPINIT_CB_ID :
hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */
break;
case HAL_HASH_MSPDEINIT_CB_ID :
hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
break;
default :
/* Update the error code */
hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hhash);
return status;
}
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
* @brief HASH processing functions using polling mode.
*
@verbatim
===============================================================================
##### Polling mode HASH processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in polling mode
the hash value using one of the following algorithms:
(+) MD5
(++) HAL_HASH_MD5_Start()
(++) HAL_HASH_MD5_Accmlt()
(++) HAL_HASH_MD5_Accmlt_End()
(+) SHA1
(++) HAL_HASH_SHA1_Start()
(++) HAL_HASH_SHA1_Accmlt()
(++) HAL_HASH_SHA1_Accmlt_End()
[..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
[..] In case of multi-buffer HASH processing (a single digest is computed while
several buffers are fed to the Peripheral), the user can resort to successive calls
to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call
to HAL_HASH_xxx_Accumulate_End().
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
}
/**
* @brief If not already done, initialize the HASH peripheral in MD5 mode then
* processes pInBuffer.
* @note Consecutive calls to HAL_HASH_MD5_Accmlt() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASH_MD5_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Accmlt_End()
* to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
}
/**
* @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA1 mode then
* processes pInBuffer.
* @note Consecutive calls to HAL_HASH_SHA1_Accmlt() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASH_SHA1_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Accmlt_End()
* to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
}
/**
* @}
*/
/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
* @brief HASH processing functions using interrupt mode.
*
@verbatim
===============================================================================
##### Interruption mode HASH processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in interrupt mode
the hash value using one of the following algorithms:
(+) MD5
(++) HAL_HASH_MD5_Start_IT()
(++) HAL_HASH_MD5_Accmlt_IT()
(++) HAL_HASH_MD5_Accmlt_End_IT()
(+) SHA1
(++) HAL_HASH_SHA1_Start_IT()
(++) HAL_HASH_SHA1_Accmlt_IT()
(++) HAL_HASH_SHA1_Accmlt_End_IT()
[..] API HAL_HASH_IRQHandler() manages each HASH interruption.
[..] Note that HAL_HASH_IRQHandler() manages as well HASH Peripheral interruptions when in
HMAC processing mode.
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
}
/**
* @brief If not already done, initialize the HASH peripheral in MD5 mode then
* processes pInBuffer in interruption mode.
* @note Consecutive calls to HAL_HASH_MD5_Accmlt_IT() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASH_MD5_Accmlt_End_IT().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End_IT() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt_IT() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
}
/**
* @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA1 mode then
* processes pInBuffer in interruption mode.
* @note Consecutive calls to HAL_HASH_SHA1_Accmlt_IT() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASH_SHA1_Accmlt_End_IT().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End_IT() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt_IT() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief Handle HASH interrupt request.
* @param hhash HASH handle.
* @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well.
* @note In case of error reported during the HASH interruption processing,
* HAL_HASH_ErrorCallback() API is called so that user code can
* manage the error. The error type is available in hhash->Status field.
* @retval None
*/
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
{
hhash->Status = HASH_IT(hhash);
if (hhash->Status != HAL_OK)
{
hhash->ErrorCode |= HAL_HASH_ERROR_IT;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->ErrorCallback(hhash);
#else
HAL_HASH_ErrorCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/* After error handling by code user, reset HASH handle HAL status */
hhash->Status = HAL_OK;
}
}
/**
* @}
*/
/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
* @brief HASH processing functions using DMA mode.
*
@verbatim
===============================================================================
##### DMA mode HASH processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
the hash value using one of the following algorithms:
(+) MD5
(++) HAL_HASH_MD5_Start_DMA()
(++) HAL_HASH_MD5_Finish()
(+) SHA1
(++) HAL_HASH_SHA1_Start_DMA()
(++) HAL_HASH_SHA1_Finish()
[..] When resorting to DMA mode to enter the data in the Peripheral, user must resort
to HAL_HASH_xxx_Start_DMA() then read the resulting digest with
HAL_HASH_xxx_Finish().
[..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be
reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally
retrieved thanks to HAL_HASH_xxx_Finish().
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer
* to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must
* be called to retrieve the computed digest.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
* @brief Return the computed digest in MD5 mode.
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in
* HMAC MD5 mode.
* @param hhash HASH handle.
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
* @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer
* to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must
* be called to retrieve the computed digest.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief Return the computed digest in SHA1 mode.
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in
* HMAC SHA1 mode.
* @param hhash HASH handle.
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
* @}
*/
/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
* @brief HMAC processing functions using polling mode.
*
@verbatim
===============================================================================
##### Polling mode HMAC processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in polling mode
the HMAC value using one of the following algorithms:
(+) MD5
(++) HAL_HMAC_MD5_Start()
(+) SHA1
(++) HAL_HMAC_SHA1_Start()
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
}
/**
* @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
}
/**
* @}
*/
/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
* @brief HMAC processing functions using interrupt mode.
*
@verbatim
===============================================================================
##### Interrupt mode HMAC processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in interrupt mode
the HMAC value using one of the following algorithms:
(+) MD5
(++) HAL_HMAC_MD5_Start_IT()
(+) SHA1
(++) HAL_HMAC_SHA1_Start_IT()
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then
* read the computed digest in interrupt mode.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
}
/**
* @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then
* read the computed digest in interrupt mode.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
}
/**
* @}
*/
/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
* @brief HMAC processing functions using DMA modes.
*
@verbatim
===============================================================================
##### DMA mode HMAC processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
the HMAC value using one of the following algorithms:
(+) MD5
(++) HAL_HMAC_MD5_Start_DMA()
(+) SHA1
(++) HAL_HMAC_SHA1_Start_DMA()
[..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing,
user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest
with HAL_HASH_xxx_Finish().
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve
* the computed digest.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note If MDMAT bit is set before calling this function (multi-buffer
* HASH processing case), the input buffer size (in bytes) must be
* a multiple of 4 otherwise, the HASH digest computation is corrupted.
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
* @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve
* the computed digest.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note If MDMAT bit is set before calling this function (multi-buffer
* HASH processing case), the input buffer size (in bytes) must be
* a multiple of 4 otherwise, the HASH digest computation is corrupted.
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
* @}
*/
/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State methods #####
===============================================================================
[..]
This section permits to get in run-time the state and the peripheral handle
status of the peripheral:
(+) HAL_HASH_GetState()
(+) HAL_HASH_GetStatus()
[..]
Additionally, this subsection provides functions allowing to save and restore
the HASH or HMAC processing context in case of calculation suspension:
(+) HAL_HASH_ContextSaving()
(+) HAL_HASH_ContextRestoring()
[..]
This subsection provides functions allowing to suspend the HASH processing
(+) when input are fed to the Peripheral by software
(++) HAL_HASH_SwFeed_ProcessSuspend()
(+) when input are fed to the Peripheral by DMA
(++) HAL_HASH_DMAFeed_ProcessSuspend()
@endverbatim
* @{
*/
/**
* @brief Return the HASH handle state.
* @note The API yields the current state of the handle (BUSY, READY,...).
* @param hhash HASH handle.
* @retval HAL HASH state
*/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
{
return hhash->State;
}
/**
* @brief Return the HASH HAL status.
* @note The API yields the HAL status of the handle: it is the result of the
* latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT).
* @param hhash HASH handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
{
return hhash->Status;
}
/**
* @brief Save the HASH context in case of processing suspension.
* @param hhash HASH handle.
* @param pMemBuffer pointer to the memory buffer where the HASH context
* is saved.
* @note The IMR, STR, CR then all the CSR registers are saved
* in that order. Only the r/w bits are read to be restored later on.
* @note By default, all the context swap registers (there are
* HASH_NUMBER_OF_CSR_REGISTERS of those) are saved.
* @note pMemBuffer points to a buffer allocated by the user. The buffer size
* must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
* @retval None
*/
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
{
uint32_t mem_ptr = (uint32_t)pMemBuffer;
uint32_t csr_ptr = (uint32_t)HASH->CSR;
uint32_t i;
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* Save IMR register content */
*(uint32_t *)(mem_ptr) = READ_BIT(HASH->IMR, HASH_IT_DINI | HASH_IT_DCI);
mem_ptr += 4U;
/* Save STR register content */
*(uint32_t *)(mem_ptr) = READ_BIT(HASH->STR, HASH_STR_NBLW);
mem_ptr += 4U;
/* Save CR register content */
*(uint32_t *)(mem_ptr) = READ_BIT(HASH->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO |
HASH_CR_LKEY | HASH_CR_MDMAT);
mem_ptr += 4U;
/* By default, save all CSRs registers */
for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
{
*(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr);
mem_ptr += 4U;
csr_ptr += 4U;
}
}
/**
* @brief Restore the HASH context in case of processing resumption.
* @param hhash HASH handle.
* @param pMemBuffer pointer to the memory buffer where the HASH context
* is stored.
* @note The IMR, STR, CR then all the CSR registers are restored
* in that order. Only the r/w bits are restored.
* @note By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS
* of those) are restored (all of them have been saved by default
* beforehand).
* @retval None
*/
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
{
uint32_t mem_ptr = (uint32_t)pMemBuffer;
uint32_t csr_ptr = (uint32_t)HASH->CSR;
uint32_t i;
/* Prevent unused argument(s) compilation warning */
UNUSED(hhash);
/* Restore IMR register content */
WRITE_REG(HASH->IMR, (*(uint32_t *)(mem_ptr)));
mem_ptr += 4U;
/* Restore STR register content */
WRITE_REG(HASH->STR, (*(uint32_t *)(mem_ptr)));
mem_ptr += 4U;
/* Restore CR register content */
WRITE_REG(HASH->CR, (*(uint32_t *)(mem_ptr)));
mem_ptr += 4U;
/* Reset the HASH processor before restoring the Context
Swap Registers (CSR) */
__HAL_HASH_INIT();
/* By default, restore all CSR registers */
for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
{
WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr)));
mem_ptr += 4U;
csr_ptr += 4U;
}
}
/**
* @brief Initiate HASH processing suspension when in polling or interruption mode.
* @param hhash HASH handle.
* @note Set the handle field SuspendRequest to the appropriate value so that
* the on-going HASH processing is suspended as soon as the required
* conditions are met. Note that the actual suspension is carried out
* by the functions HASH_WriteData() in polling mode and HASH_IT() in
* interruption mode.
* @retval None
*/
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
{
/* Set Handle Suspend Request field */
hhash->SuspendRequest = HAL_HASH_SUSPEND;
}
/**
* @brief Suspend the HASH processing when in DMA mode.
* @param hhash HASH handle.
* @note When suspension attempt occurs at the very end of a DMA transfer and
* all the data have already been entered in the Peripheral, hhash->State is
* set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is
* recommended to wrap-up the processing in reading the digest as usual.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
{
uint32_t tmp_remaining_DMATransferSize_inWords;
uint32_t tmp_initial_DMATransferSize_inWords;
if (hhash->State == HAL_HASH_STATE_READY)
{
return HAL_ERROR;
}
else
{
/* Make sure there is enough time to suspend the processing */
/* DMA3 used, DMA_CBR1_BNDT in bytes*/
tmp_remaining_DMATransferSize_inWords = ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CBR1) \
& DMA_CBR1_BNDT) / 4U;
if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
{
/* No suspension attempted since almost to the end of the transferred data. */
/* Best option for user code is to wrap up low priority message hashing */
return HAL_ERROR;
}
/* Clear the DMAE bit to disable the DMA interface */
CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
/* Wait until the last DMA transfer is complete (DMAS = 0 in the HASH_SR register) */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DMAS, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* At this point, DMA interface is disabled and no transfer is on-going */
/* Retrieve from the DMA handle how many words remain to be written */
/* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */
tmp_remaining_DMATransferSize_inWords = ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CBR1) \
& DMA_CBR1_BNDT) / 4U;
tmp_remaining_DMATransferSize_inWords += ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CSR) \
& DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos;
/* Disable DMA channel */
/* Note that the Abort function will
- Clear the transfer error flags
- Unlock
- Set the State
*/
if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK)
{
return HAL_ERROR;
}
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
{
return HAL_ERROR;
}
/* Wait until the hash processor is ready (no block is being processed), that is wait for DINIS=1 in HASH_SR */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DINIS, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
}
if (tmp_remaining_DMATransferSize_inWords == 0U)
{
/* All the DMA transfer is actually done. Suspension occurred at the very end
of the transfer. Either the digest computation is about to start (HASH case)
or processing is about to move from one step to another (HMAC case).
In both cases, the processing can't be suspended at this point. It is
safer to
- retrieve the low priority block digest before starting the high
priority block processing (HASH case)
- re-attempt a new suspension (HMAC case)
*/
return HAL_ERROR;
}
else
{
/* Compute how many words were supposed to be transferred by DMA */
tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount % 4U) != 0U) ? \
((hhash->HashInCount + 3U) / 4U) : (hhash->HashInCount / 4U));
/* Accordingly, update the input pointer that points at the next word to be
transferred to the Peripheral by DMA */
hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
/* And store in HashInCount the remaining size to transfer (in bytes) */
hhash->HashInCount = 4U * tmp_remaining_DMATransferSize_inWords;
}
/* Set State as suspended */
hhash->State = HAL_HASH_STATE_SUSPENDED;
return HAL_OK;
}
}
/**
* @brief Return the HASH handle error code.
* @param hhash pointer to a HASH_HandleTypeDef structure.
* @retval HASH Error Code
*/
uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
{
/* Return HASH Error Code */
return hhash->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup HASH_Private_Functions HASH Private Functions
* @{
*/
/**
* @brief DMA HASH Input Data transfer completion callback.
* @param hdma DMA handle.
* @note In case of HMAC processing, HASH_DMAXferCplt() initiates
* the next DMA transfer for the following HMAC step.
* @retval None
*/
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
uint32_t inputaddr;
uint32_t buffersize;
HAL_StatusTypeDef status = HAL_OK;
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
/* Disable the DMA transfer */
CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U)
{
/* If no HMAC processing, input data transfer is now over */
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
/* Call Input data transfer complete call back */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->InCpltCallback(hhash);
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
}
else
{
/* HMAC processing: depending on the current HMAC step and whether or
not multi-buffer processing is on-going, the next step is initiated
and MDMAT bit is set. */
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
{
/* This is the end of HMAC processing */
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
/* Call Input data transfer complete call back
(note that the last DMA transfer was that of the key
for the outer HASH operation). */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->InCpltCallback(hhash);
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
return;
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
{
inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */
buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
/* In case of suspension request, save the new starting parameters */
hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */
hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */
hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
/* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */
if (hhash->DigestCalculationDisable != RESET)
{
/* Digest calculation is disabled: Step 2 must start with MDMAT bit set,
no digest calculation will be triggered at the end of the input buffer feeding to the Peripheral */
__HAL_HASH_SET_MDMAT();
}
}
else /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/
{
if (hhash->DigestCalculationDisable != RESET)
{
/* No automatic move to Step 3 as a new message buffer will be fed to the Peripheral
(case of multi-buffer HMAC processing):
DCAL must not be set.
Phase remains in Step 2, MDMAT remains set at this point.
Change the HASH state to ready and call Input data transfer complete call back. */
hhash->State = HAL_HASH_STATE_READY;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->InCpltCallback(hhash);
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
return ;
}
else
{
/* Digest calculation is not disabled (case of single buffer input or last buffer
of multi-buffer HMAC processing) */
inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */
buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */
/* In case of suspension request, save the new starting parameters */
hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */
hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */
hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */
}
}
/* Configure the Number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(buffersize);
/* Set the HASH DMA transfer completion call back */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
/* Enable the DMA In DMA channel */
if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL))
{
/* Set DMA data size */
hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\
= (((buffersize % 4U) != 0U) ? (buffersize + (4U - (buffersize % 4U))) : (buffersize));
/* Set DMA source address */
hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr;
/* Set DMA destination address */
hhash->hdmain->LinkedListQueue->Head->\
LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&HASH->DIN;
status = HAL_DMAEx_List_Start_IT(hhash->hdmain);
}
else
{
/* Update HASH state machine to error */
hhash->State = HAL_HASH_STATE_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
(((buffersize % 4U) != 0U) ? (buffersize + (4U - (buffersize % 4U))) : (buffersize)));
}
if (status != HAL_OK)
{
/* Update HASH state machine to error */
hhash->State = HAL_HASH_STATE_ERROR;
}
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
/* Return function status */
if (status != HAL_OK)
{
/* Update HASH state machine to error */
hhash->State = HAL_HASH_STATE_ERROR;
}
else
{
/* Change HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
}
}
}
return;
}
/**
* @brief DMA HASH communication error callback.
* @param hdma DMA handle.
* @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that
* can contain user code to manage the error.
* @retval None
*/
static void HASH_DMAError(DMA_HandleTypeDef *hdma)
{
HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
/* Set HASH state to ready to prevent any blocking issue in user code
present in HAL_HASH_ErrorCallback() */
hhash->State = HAL_HASH_STATE_READY;
/* Set HASH handle status to error */
hhash->Status = HAL_ERROR;
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->ErrorCallback(hhash);
#else
HAL_HASH_ErrorCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
/* After error handling by code user, reset HASH handle HAL status */
hhash->Status = HAL_OK;
}
}
/**
* @brief Feed the input buffer to the HASH Peripheral.
* @param hhash HASH handle.
* @param pInBuffer pointer to input buffer.
* @param Size the size of input buffer in bytes.
* @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether
* or not the HASH processing must be suspended. If this is the case, the
* processing is suspended when possible and the Peripheral feeding point reached at
* suspension time is stored in the handle for resumption later on.
* @retval HAL status
*/
static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
uint32_t buffercounter;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U)
{
/* Write input data 4 bytes at a time */
HASH->DIN = *(uint32_t *)inputaddr;
inputaddr += 4U;
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size))
{
/* wait for flag BUSY not set before Wait for DINIS = 1*/
if (buffercounter >= 64U)
{
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
}
}
/* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
in the input buffer */
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
/* Reset SuspendRequest */
hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
/* Depending whether the key or the input data were fed to the Peripheral, the feeding point
reached at suspension time is not saved in the same handle fields */
if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
{
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
hhash->HashInCount = Size - (buffercounter + 4U);
}
else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
hhash->HashKeyCount = Size - (buffercounter + 4U);
}
else
{
/* Unexpected phase: unlock process and report error */
hhash->State = HAL_HASH_STATE_READY;
__HAL_UNLOCK(hhash);
return HAL_ERROR;
}
/* Set the HASH state to Suspended and exit to stop entering data */
hhash->State = HAL_HASH_STATE_SUSPENDED;
return HAL_OK;
} /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) */
} /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
} /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
/* At this point, all the data have been entered to the Peripheral: exit */
return HAL_OK;
}
/**
* @brief Retrieve the message digest.
* @param pMsgDigest pointer to the computed digest.
* @param Size message digest size in bytes.
* @retval None
*/
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
{
uint32_t msgdigest = (uint32_t)pMsgDigest;
switch (Size)
{
/* Read the message digest */
case 16: /* MD5 */
*(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
break;
case 20: /* SHA1 */
*(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
break;
case 28: /* SHA224 */
*(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
break;
case 32: /* SHA256 */
*(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
msgdigest += 4U;
*(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
break;
default:
break;
}
}
/**
* @brief Handle HASH processing Timeout.
* @param hhash HASH handle.
* @param Flag specifies the HASH flag to check.
* @param Status the Flag status (SET or RESET).
* @param Timeout Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
/* Wait until flag is set */
if (Status == RESET)
{
while (__HAL_HASH_GET_FLAG(Flag) == RESET)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Set State to Ready to be able to restart later on */
hhash->State = HAL_HASH_STATE_READY;
/* Store time out issue in handle status */
hhash->Status = HAL_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
}
}
}
}
else
{
while (__HAL_HASH_GET_FLAG(Flag) != RESET)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Set State to Ready to be able to restart later on */
hhash->State = HAL_HASH_STATE_READY;
/* Store time out issue in handle status */
hhash->Status = HAL_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hhash);
return HAL_TIMEOUT;
}
}
}
}
return HAL_OK;
}
/**
* @brief HASH processing in interruption mode.
* @param hhash HASH handle.
* @note HASH_IT() regularly reads hhash->SuspendRequest to check whether
* or not the HASH processing must be suspended. If this is the case, the
* processing is suspended when possible and the Peripheral feeding point reached at
* suspension time is stored in the handle for resumption later on.
* @retval HAL status
*/
static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
{
if (hhash->State == HAL_HASH_STATE_BUSY)
{
/* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
if (hhash->HashITCounter == 0U)
{
/* Disable Interrupts */
__HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* HASH state set back to Ready to prevent any issue in user code
present in HAL_HASH_ErrorCallback() */
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
else if (hhash->HashITCounter == 1U)
{
/* This is the first call to HASH_IT, the first input data are about to be
entered in the Peripheral. A specific processing is carried out at this point to
start-up the processing. */
hhash->HashITCounter = 2U;
}
else
{
/* Cruise speed reached, HashITCounter remains equal to 3 until the end of
the HASH processing or the end of the current step for HMAC processing. */
hhash->HashITCounter = 3U;
}
/* If digest is ready */
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
{
/* Read the digest */
HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
/* Disable Interrupts */
__HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
/* Reset HASH state machine */
hhash->Phase = HAL_HASH_PHASE_READY;
/* Call digest computation complete call back */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->DgstCpltCallback(hhash);
#else
HAL_HASH_DgstCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
return HAL_OK;
}
/* If Peripheral ready to accept new data */
if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
if ((hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND))
{
/* Disable Interrupts */
__HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Reset SuspendRequest */
hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_SUSPENDED;
return HAL_OK;
}
/* Enter input data in the Peripheral through HASH_Write_Block_Data() call and
check whether the digest calculation has been triggered */
if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
{
/* Call Input data transfer complete call back
(called at the end of each step for HMAC) */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->InCpltCallback(hhash);
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
{
/* Wait until Peripheral is not busy anymore */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
/* Disable Interrupts */
__HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
return HAL_TIMEOUT;
}
/* Initialization start for HMAC STEP 2 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */
__HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */
hhash->HashInCount = hhash->HashBuffSize; /* Set the input data size (in bytes) */
hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */
hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start
of a new phase */
__HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
{
/* Wait until Peripheral is not busy anymore */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
/* Disable Interrupts */
__HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
return HAL_TIMEOUT;
}
/* Initialization start for HMAC STEP 3 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */
__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */
hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */
hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */
hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start
of a new phase */
__HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */
}
else
{
/* Nothing to do */
}
} /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */
} /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/
/* Return function status */
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Write a block of data in HASH Peripheral in interruption mode.
* @param hhash HASH handle.
* @note HASH_Write_Block_Data() is called under interruption by HASH_IT().
* @retval HAL status
*/
static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
{
uint32_t inputaddr;
uint32_t buffercounter;
uint32_t inputcounter;
uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
/* If there are more than 64 bytes remaining to be entered */
if (hhash->HashInCount > 64U)
{
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Write the Input block in the Data IN register
(16 32-bit words, or 64 bytes are entered) */
for (buffercounter = 0U; buffercounter < 64U; buffercounter += 4U)
{
HASH->DIN = *(uint32_t *)inputaddr;
inputaddr += 4U;
}
/* If this is the start of input data entering, an additional word
must be entered to start up the HASH processing */
if (hhash->HashITCounter == 2U)
{
HASH->DIN = *(uint32_t *)inputaddr;
if (hhash->HashInCount >= 68U)
{
/* There are still data waiting to be entered in the Peripheral.
Decrement buffer counter and set pointer to the proper
memory location for the next data entering round. */
hhash->HashInCount -= 68U;
hhash->pHashInBuffPtr += 68U;
}
else
{
/* All the input buffer has been fed to the HW. */
hhash->HashInCount = 0U;
}
}
else
{
/* 64 bytes have been entered and there are still some remaining:
Decrement buffer counter and set pointer to the proper
memory location for the next data entering round.*/
hhash->HashInCount -= 64U;
hhash->pHashInBuffPtr += 64U;
}
}
else
{
/* 64 or less bytes remain to be entered. This is the last
data entering round. */
/* Get the buffer address */
inputaddr = (uint32_t)hhash->pHashInBuffPtr;
/* Get the buffer counter */
inputcounter = hhash->HashInCount;
/* Disable Interrupts */
__HAL_HASH_DISABLE_IT(HASH_IT_DINI);
/* Write the Input block in the Data IN register */
for (buffercounter = 0U; buffercounter < ((inputcounter + 3U) / 4U); buffercounter++)
{
HASH->DIN = *(uint32_t *)inputaddr;
inputaddr += 4U;
}
if (hhash->Accumulation == 1U)
{
/* Field accumulation is set, API only feeds data to the Peripheral and under interruption.
The digest computation will be started when the last buffer data are entered. */
/* Reset multi buffers accumulation flag */
hhash->Accumulation = 0U;
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
/* Call Input data transfer complete call back */
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
hhash->InCpltCallback(hhash);
#else
HAL_HASH_InCpltCallback(hhash);
#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
}
else
{
/* Start the Digest calculation */
__HAL_HASH_START_DIGEST();
/* Return indication that digest calculation has started:
this return value triggers the call to Input data transfer
complete call back as well as the proper transition from
one step to another in HMAC mode. */
ret = HASH_DIGEST_CALCULATION_STARTED;
}
/* Reset buffer counter */
hhash->HashInCount = 0;
}
/* Return whether or digest calculation has started */
return ret;
}
/**
* @brief HMAC processing in polling mode.
* @param hhash HASH handle.
* @param Timeout Timeout value.
* @retval HAL status
*/
static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
{
/* Ensure first that Phase is correct */
if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2)
&& (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
/* Process Unlock */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_ERROR;
}
/* HMAC Step 1 processing */
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1)
{
/************************** STEP 1 ******************************************/
/* Configure the Number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
/* Write input buffer in Data register */
hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
if (hhash->Status != HAL_OK)
{
return hhash->Status;
}
/* Check whether or not key entering process has been suspended */
if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Stop right there and return function status */
return HAL_OK;
}
/* No processing suspension at this point: set DCAL bit. */
__HAL_HASH_START_DIGEST();
/* Wait for BUSY flag to be cleared */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Move from Step 1 to Step 2 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2;
}
/* HMAC Step 2 processing.
After phase check, HMAC_Processing() may
- directly start up from this point in resumption case
if the same Step 2 processing was suspended previously
- or fall through from the Step 1 processing carried out hereabove */
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
{
/************************** STEP 2 ******************************************/
/* Configure the Number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);
/* Write input buffer in Data register */
hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount);
if (hhash->Status != HAL_OK)
{
return hhash->Status;
}
/* Check whether or not data entering process has been suspended */
if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Stop right there and return function status */
return HAL_OK;
}
/* No processing suspension at this point: set DCAL bit. */
__HAL_HASH_START_DIGEST();
/* Wait for BUSY flag to be cleared */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Move from Step 2 to Step 3 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3;
/* In case Step 1 phase was suspended then resumed,
set again Key input buffers and size before moving to
next step */
hhash->pHashKeyBuffPtr = hhash->Init.pKey;
hhash->HashKeyCount = hhash->Init.KeySize;
}
/* HMAC Step 3 processing.
After phase check, HMAC_Processing() may
- directly start up from this point in resumption case
if the same Step 3 processing was suspended previously
- or fall through from the Step 2 processing carried out hereabove */
if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
{
/************************** STEP 3 ******************************************/
/* Configure the Number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
/* Write input buffer in Data register */
hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount);
if (hhash->Status != HAL_OK)
{
return hhash->Status;
}
/* Check whether or not key entering process has been suspended */
if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Stop right there and return function status */
return HAL_OK;
}
/* No processing suspension at this point: start the Digest calculation. */
__HAL_HASH_START_DIGEST();
/* Wait for DCIS flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Read the message digest */
HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
/* Reset HASH state machine */
hhash->Phase = HAL_HASH_PHASE_READY;
}
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
/* Process Unlock */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the HASH peripheral, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest.
* @param Timeout Timeout value.
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
uint32_t Timeout, uint32_t Algorithm)
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* Initiate HASH processing in case of start or resumption */
if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hhash);
/* Check if initialization phase has not been already performed */
if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Configure the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(Size);
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
}
else if (hhash->Phase == HAL_HASH_PHASE_PROCESS)
{
/* if the Peripheral has already been initialized, two cases are possible */
/* Process resumption time ... */
if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
/* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
to the API input parameters but to those saved beforehand by HASH_WriteData()
when the processing was suspended */
pInBuffer_tmp = hhash->pHashInBuffPtr;
Size_tmp = hhash->HashInCount;
}
/* ... or multi-buffer HASH processing end */
else
{
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
pInBuffer_tmp = pInBuffer;
Size_tmp = Size;
/* Configure the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(Size);
}
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
}
else
{
/* Phase error */
hhash->State = HAL_HASH_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_ERROR;
}
/* Write input buffer in Data register */
hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
if (hhash->Status != HAL_OK)
{
return hhash->Status;
}
/* If the process has not been suspended, carry on to digest calculation */
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
/* Start the Digest calculation */
__HAL_HASH_START_DIGEST();
/* Wait for DCIS flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Read the message digest */
HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
/* Reset HASH state machine */
hhash->Phase = HAL_HASH_PHASE_READY;
}
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief If not already done, initialize the HASH peripheral then
* processes pInBuffer.
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */
uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* Make sure the input buffer size (in bytes) is a multiple of 4 */
if ((Size % 4U) != 0U)
{
return HAL_ERROR;
}
/* Initiate HASH processing in case of start or resumption */
if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hhash);
/* If resuming the HASH processing */
if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
to the API input parameters but to those saved beforehand by HASH_WriteData()
when the processing was suspended */
pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */
Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */
}
else
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
input parameters of HASH_WriteData() */
pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */
Size_tmp = Size; /* Size_tmp contains the input data size in bytes */
/* Check if initialization phase has already be performed */
if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
}
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
}
/* Write input buffer in Data register */
hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp);
if (hhash->Status != HAL_OK)
{
return hhash->Status;
}
/* If the process has not been suspended, move the state to Ready */
if (hhash->State != HAL_HASH_STATE_SUSPENDED)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
}
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief If not already done, initialize the HASH peripheral then
* processes pInBuffer in interruption mode.
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
uint32_t SizeVar = Size;
/* Make sure the input buffer size (in bytes) is a multiple of 4 */
if ((Size % 4U) != 0U)
{
return HAL_ERROR;
}
/* Initiate HASH processing in case of start or resumption */
if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hhash);
/* If resuming the HASH processing */
if (hhash->State == HAL_HASH_STATE_SUSPENDED)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
}
else
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Check if initialization phase has already be performed */
if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
hhash->HashITCounter = 1;
}
else
{
hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
}
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
/* If DINIS is equal to 0 (for example if an incomplete block has been previously
fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
Therefore, first words are manually entered until DINIS raises, or until there
is not more data to enter. */
while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U))
{
/* Write input data 4 bytes at a time */
HASH->DIN = *(uint32_t *)inputaddr;
inputaddr += 4U;
SizeVar -= 4U;
}
/* If DINIS is still not set or if all the data have been fed, stop here */
if ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) || (SizeVar == 0U))
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_READY;
/* Process Unlock */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_OK;
}
/* otherwise, carry on in interrupt-mode */
hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
to be fed to the Peripheral */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at
the next interruption */
/* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
the information describing where the HASH process is stopped.
These variables are used later on to resume the HASH processing at the
correct location. */
}
/* Set multi buffers accumulation flag */
hhash->Accumulation = 1U;
/* Process Unlock */
__HAL_UNLOCK(hhash);
/* Enable Data Input interrupt */
__HAL_HASH_ENABLE_IT(HASH_IT_DINI);
/* Return function status */
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Initialize the HASH peripheral, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest.
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
uint32_t polling_step = 0U;
uint32_t initialization_skipped = 0U;
uint32_t SizeVar = Size;
/* If State is ready or suspended, start or resume IT-based HASH processing */
if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hhash);
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Initialize IT counter */
hhash->HashITCounter = 1;
/* Check if initialization phase has already be performed */
if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Configure the number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(SizeVar);
hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data
to be fed to the Peripheral */
hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at
the next interruption */
/* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
the information describing where the HASH process is stopped.
These variables are used later on to resume the HASH processing at the
correct location. */
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
}
else
{
initialization_skipped = 1; /* info user later on in case of multi-buffer */
}
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
/* If DINIS is equal to 0 (for example if an incomplete block has been previously
fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
Therefore, first words are manually entered until DINIS raises. */
while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U))
{
polling_step = 1U; /* note that some words are entered before enabling the interrupt */
/* Write input data 4 bytes at a time */
HASH->DIN = *(uint32_t *)inputaddr;
inputaddr += 4U;
SizeVar -= 4U;
}
if (polling_step == 1U)
{
if (SizeVar == 0U)
{
/* If all the data have been entered at this point, it only remains to
read the digest */
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
/* Start the Digest calculation */
__HAL_HASH_START_DIGEST();
/* Process Unlock */
__HAL_UNLOCK(hhash);
/* Enable Interrupts */
__HAL_HASH_ENABLE_IT(HASH_IT_DCI);
/* Return function status */
return HAL_OK;
}
else if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
/* It remains data to enter and the Peripheral is ready to trigger DINIE,
carry on as usual.
Update HashInCount and pHashInBuffPtr accordingly. */
hhash->HashInCount = SizeVar;
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
__HAL_HASH_SET_NBVALIDBITS(
SizeVar); /* Update the configuration of the number of valid bits in last word of the message */
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
if (initialization_skipped == 1U)
{
hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
}
}
else
{
/* DINIS is not set but it remains a few data to enter (not enough for a full word).
Manually enter the last bytes before enabling DCIE. */
__HAL_HASH_SET_NBVALIDBITS(SizeVar);
HASH->DIN = *(uint32_t *)inputaddr;
/* Start the Digest calculation */
hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */
__HAL_HASH_START_DIGEST();
/* Process Unlock */
__HAL_UNLOCK(hhash);
/* Enable Interrupts */
__HAL_HASH_ENABLE_IT(HASH_IT_DCI);
/* Return function status */
return HAL_OK;
}
} /* if (polling_step == 1) */
/* Process Unlock */
__HAL_UNLOCK(hhash);
/* Enable Interrupts */
__HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Return function status */
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Initialize the HASH peripheral then initiate a DMA transfer
* to feed the input buffer to the Peripheral.
* @note If MDMAT bit is set before calling this function (multi-buffer
* HASH processing case), the input buffer size (in bytes) must be
* a multiple of 4 otherwise, the HASH digest computation is corrupted.
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
uint32_t inputaddr;
uint32_t inputSize;
HAL_StatusTypeDef status ;
HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set
(case of multi-buffer HASH processing) */
assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
/* If State is ready or suspended, start or resume polling-based HASH processing */
if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) ||
/* Check phase coherency. Phase must be
either READY (fresh start)
or PROCESS (multi-buffer HASH management) */
((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hhash);
/* If not a resumption case */
if (hhash->State == HAL_HASH_STATE_READY)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Check if initialization phase has already been performed.
If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
API is processing a new input data message in case of multi-buffer HASH
computation. */
if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
/* Set the phase */
hhash->Phase = HAL_HASH_PHASE_PROCESS;
}
/* Configure the Number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(Size);
inputaddr = (uint32_t)pInBuffer; /* DMA transfer start address */
inputSize = Size; /* DMA transfer size (in bytes) */
/* In case of suspension request, save the starting parameters */
hhash->pHashInBuffPtr = pInBuffer; /* DMA transfer start address */
hhash->HashInCount = Size; /* DMA transfer size (in bytes) */
}
/* If resumption case */
else
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Resumption case, inputaddr and inputSize are not set to the API input parameters
but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
processing was suspended */
inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */
inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */
}
/* Set the HASH DMA transfer complete callback */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
/* Set the DMA error callback */
hhash->hdmain->XferErrorCallback = HASH_DMAError;
/* Store number of words already pushed to manage proper DMA processing suspension */
hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
/* Enable the DMA In DMA channel */
if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\
= (((inputSize % 4U) != 0U) ? (inputSize + (4U - (inputSize % 4U))) : (inputSize)); /* Set DMA data size */
hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]\
= inputaddr; /* Set DMA source address */
hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]\
= (uint32_t)&HASH->DIN; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hhash->hdmain);
}
else
{
/* Return error status */
status = HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
(((inputSize % 4U) != 0U) ? (inputSize + (4U - (inputSize % 4U))) : (inputSize)));
}
if (status != HAL_OK)
{
/* Return error status */
status = HAL_ERROR;
}
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
/* Process Unlock */
__HAL_UNLOCK(hhash);
/* Return function status */
if (status != HAL_OK)
{
/* Update HASH state machine to error */
hhash->State = HAL_HASH_STATE_ERROR;
}
return status;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Return the computed digest.
* @note The API waits for DCIS to be set then reads the computed digest.
* @param hhash HASH handle.
* @param pOutBuffer pointer to the computed digest.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
if (hhash->State == HAL_HASH_STATE_READY)
{
/* Check parameter */
if (pOutBuffer == NULL)
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hhash);
/* Change the HASH state to busy */
hhash->State = HAL_HASH_STATE_BUSY;
/* Wait for DCIS flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Read the message digest */
HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH());
/* Change the HASH state to ready */
hhash->State = HAL_HASH_STATE_READY;
/* Reset HASH state machine */
hhash->Phase = HAL_HASH_PHASE_READY;
/* Process UnLock */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest.
* @param Timeout Timeout value.
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
uint32_t Timeout, uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* If State is ready or suspended, start or resume polling-based HASH processing */
if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U)
|| (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hhash);
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Check if initialization phase has already be performed */
if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
if (hhash->Init.KeySize > 64U)
{
MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
/* Set the phase to Step 1 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
/* Resort to hhash internal fields to feed the Peripheral.
Parameters will be updated in case of suspension to contain the proper
information at resumption time. */
hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input
parameter for Step 2 */
hhash->HashInCount = Size; /* Input data size, HMAC_Processing input
parameter for Step 2 */
hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process*/
hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step
1 and Step 3 */
hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1
and Step 3 */
}
/* Carry out HMAC processing */
return HMAC_Processing(hhash, Timeout);
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest.
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer,
uint32_t Algorithm)
{
HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* If State is ready or suspended, start or resume IT-based HASH processing */
if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U)
|| (pOutBuffer == NULL))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hhash);
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Initialize IT counter */
hhash->HashITCounter = 1;
/* Check if initialization phase has already be performed */
if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
if (hhash->Init.KeySize > 64U)
{
MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
/* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
to feed the Peripheral whatever the HMAC step.
Lines below are set to start HMAC Step 1 processing where key is entered first. */
hhash->HashInCount = hhash->Init.KeySize; /* Key size */
hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */
/* Store input and output parameters in handle fields to manage steps transition
or possible HMAC suspension/resumption */
hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
hhash->pHashMsgBuffPtr = pInBuffer; /* Input message address */
hhash->HashBuffSize = Size; /* Input message size (in bytes) */
hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */
/* Configure the number of valid bits in last word of the key */
__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
/* Set the phase to Step 1 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
}
else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Restart IT-based HASH processing after Step 1 or Step 3 suspension */
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
{
/* Restart IT-based HASH processing after Step 2 suspension */
}
else
{
/* Error report as phase incorrect */
/* Process Unlock */
__HAL_UNLOCK(hhash);
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
/* Process Unlock */
__HAL_UNLOCK(hhash);
/* Enable Interrupts */
__HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
/* Return function status */
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Initialize the HASH peripheral in HMAC mode then initiate the required
* DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must
* be a multiple of 4 otherwise, the HASH digest computation is corrupted.
* Only the length of the last buffer of the thread doesn't have to be a
* multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param Algorithm HASH algorithm.
* @retval HAL status
*/
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
{
uint32_t inputaddr;
uint32_t inputSize;
HAL_StatusTypeDef status ;
HAL_HASH_StateTypeDef State_tmp = hhash->State;
/* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
/* If State is ready or suspended, start or resume DMA-based HASH processing */
if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
/* Check input parameters */
if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) ||
/* Check phase coherency. Phase must be
either READY (fresh start)
or one of HMAC PROCESS steps (multi-buffer HASH management) */
((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
{
hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hhash);
/* If not a case of resumption after suspension */
if (hhash->State == HAL_HASH_STATE_READY)
{
/* Check whether or not initialization phase has already be performed */
if (hhash->Phase == HAL_HASH_PHASE_READY)
{
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
At the same time, ensure MDMAT bit is cleared. */
if (hhash->Init.KeySize > 64U)
{
MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
}
else
{
MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
}
/* Store input aparameters in handle fields to manage steps transition
or possible HMAC suspension/resumption */
hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */
hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */
hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */
hhash->HashBuffSize = Size; /* input data size (in bytes) */
/* Set DMA input parameters */
inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */
inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */
/* Configure the number of valid bits in last word of the key */
__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
/* Set the phase to Step 1 */
hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
}
else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
{
/* Process a new input data message in case of multi-buffer HMAC processing
(this is not a resumption case) */
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Save input parameters to be able to manage possible suspension/resumption */
hhash->HashInCount = Size; /* Input message address */
hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */
/* Set DMA input parameters */
inputaddr = (uint32_t)pInBuffer; /* Input message address */
inputSize = Size; /* Input message size in bytes */
if (hhash->DigestCalculationDisable == RESET)
{
/* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
__HAL_HASH_RESET_MDMAT();
__HAL_HASH_SET_NBVALIDBITS(inputSize);
}
}
else
{
/* Phase not aligned with handle READY state */
__HAL_UNLOCK(hhash);
/* Return function status */
return HAL_ERROR;
}
}
else
{
/* Resumption case (phase may be Step 1, 2 or 3) */
/* Change the HASH state */
hhash->State = HAL_HASH_STATE_BUSY;
/* Set DMA input parameters at resumption location;
inputaddr and inputSize are not set to the API input parameters
but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the
processing was suspended. */
inputaddr = (uint32_t)(hhash->pHashInBuffPtr); /* Input message address */
inputSize = hhash->HashInCount; /* Input message size in bytes */
}
/* Set the HASH DMA transfer complete callback */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
/* Set the DMA error callback */
hhash->hdmain->XferErrorCallback = HASH_DMAError;
/* Store number of words already pushed to manage proper DMA processing suspension */
hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
/* Enable the DMA In DMA channel */
if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL))
{
/* Enable the DMA channel */
hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\
= (((inputSize % 4U) != 0U) ? (inputSize + (4U - (inputSize % 4U))) : (inputSize)); /* Set DMA data size */
hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]\
= inputaddr; /* Set DMA source address */
hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]\
= (uint32_t)&HASH->DIN; /* Set DMA destination address */
status = HAL_DMAEx_List_Start_IT(hhash->hdmain);
}
else
{
/* Return error status */
status = HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
(((inputSize % 4U) != 0U) ? (inputSize + (4U - (inputSize % 4U))) : (inputSize)));
}
if (status != HAL_OK)
{
/* Return error status */
status = HAL_ERROR;
}
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
/* Process Unlocked */
__HAL_UNLOCK(hhash);
/* Return function status */
if (status != HAL_OK)
{
/* Update HASH state machine to error */
hhash->State = HAL_HASH_STATE_ERROR;
}
/* Return function status */
return status;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
#endif /* HAL_HASH_MODULE_ENABLED */
/**
* @}
*/
#endif /* HASH*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c
|
C
|
apache-2.0
| 133,712
|
/**
******************************************************************************
* @file stm32u5xx_hal_hash_ex.c
* @author MCD Application Team
* @brief Extended HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral for SHA-224 and SHA-256
* algorithms:
* + HASH or HMAC processing in polling mode
* + HASH or HMAC processing in interrupt mode
* + HASH or HMAC processing in DMA mode
* Additionally, this file provides functions to manage HMAC
* multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224
* and SHA-256.
*
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### HASH peripheral extended features #####
===============================================================================
[..]
The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly
the same way as for SHA-1 or MD-5 algorithms.
(#) Three modes are available.
(##) Polling mode: processing APIs are blocking functions
i.e. they process the data and wait till the digest computation is finished,
e.g. HAL_HASHEx_xxx_Start()
(##) Interrupt mode: processing APIs are not blocking functions
i.e. they process the data under interrupt,
e.g. HAL_HASHEx_xxx_Start_IT()
(##) DMA mode: processing APIs are not blocking functions and the CPU is
not used for data transfer i.e. the data transfer is ensured by DMA,
e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to
HAL_HASHEx_xxx_Finish() is then required to retrieve the digest.
(#)Multi-buffer processing is possible in polling, interrupt and DMA modes.
(##) In polling mode, only multi-buffer HASH processing is possible.
API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one.
User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as
well the computed digest.
(##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
except for the last one.
User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
(+++) HASH processing: once initialization is done, MDMAT bit must be set through
__HAL_HASH_SET_MDMAT() macro.
From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
macro then wrap-up the HASH processing in feeding the last input buffer through the
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASHEx_xxx_Finish().
(+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to
extended functions): after initialization, the key and the first input buffer are entered
in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
starts step 2.
The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this
point, the HMAC processing is still carrying out step 2.
Then, step 2 for the last input buffer and step 3 are carried out by a single call
to HAL_HMACEx_xxx_Step2_3_DMA().
The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for
MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#if defined (HASH)
/** @defgroup HASHEx HASHEx
* @brief HASH HAL extended module driver.
* @{
*/
#ifdef HAL_HASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions
* @{
*/
/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
* @brief HASH extended processing functions using polling mode.
*
@verbatim
===============================================================================
##### Polling mode HASH extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in polling mode
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start()
(++) HAL_HASHEx_SHA224_Accmlt()
(++) HAL_HASHEx_SHA224_Accmlt_End()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start()
(++) HAL_HASHEx_SHA256_Accmlt()
(++) HAL_HASHEx_SHA256_Accmlt_End()
[..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start().
[..] In case of multi-buffer HASH processing (a single digest is computed while
several buffers are fed to the Peripheral), the user can resort to successive calls
to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call
to HAL_HASHEx_xxx_Accumulate_End().
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA224 mode then
* processes pInBuffer.
* @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA224_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Accmlt_End()
* to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA256 mode then
* processes pInBuffer.
* @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA256_Accmlt_End().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Accmlt_End()
* to read it, feeding at the same time the last input buffer to the Peripheral.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
* @brief HASH extended processing functions using interrupt mode.
*
@verbatim
===============================================================================
##### Interruption mode HASH extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in interrupt mode
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start_IT()
(++) HAL_HASHEx_SHA224_Accmlt_IT()
(++) HAL_HASHEx_SHA224_Accmlt_End_IT()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start_IT()
(++) HAL_HASHEx_SHA256_Accmlt_IT()
(++) HAL_HASHEx_SHA256_Accmlt_End_IT()
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA224 mode then
* processes pInBuffer in interruption mode.
* @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt_IT() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA224_Accmlt_End_IT().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End_IT() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt_IT() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then
* read the computed digest in interruption mode.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief If not already done, initialize the HASH peripheral in SHA256 mode then
* processes pInBuffer in interruption mode.
* @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt_IT() can be used to feed
* several input buffers back-to-back to the Peripheral that will yield a single
* HASH signature once all buffers have been entered. Wrap-up of input
* buffers feeding and retrieval of digest is done by a call to
* HAL_HASHEx_SHA256_Accmlt_End_IT().
* @note Field hhash->Phase of HASH handle is tested to check whether or not
* the Peripheral has already been initialized.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End_IT() is able
* to manage the ending buffer with a length in bytes not a multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes, must be a multiple of 4.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt_IT() API.
* @note Digest is available in pOutBuffer.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
* @brief HASH extended processing functions using DMA mode.
*
@verbatim
===============================================================================
##### DMA mode HASH extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
the hash value using one of the following algorithms:
(+) SHA224
(++) HAL_HASHEx_SHA224_Start_DMA()
(++) HAL_HASHEx_SHA224_Finish()
(+) SHA256
(++) HAL_HASHEx_SHA256_Start_DMA()
(++) HAL_HASHEx_SHA256_Finish()
[..] When resorting to DMA mode to enter the data in the Peripheral, user must resort
to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with
HAL_HASHEx_xxx_Finish().
[..] In case of multi-buffer HASH processing, MDMAT bit must first be set before
the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be
reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally
retrieved thanks to HAL_HASHEx_xxx_Finish().
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
* to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must
* be called to retrieve the computed digest.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Return the computed digest in SHA224 mode.
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in
* HMAC SHA224 mode.
* @param hhash HASH handle.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
* @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer
* to feed the input buffer to the Peripheral.
* @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must
* be called to retrieve the computed digest.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief Return the computed digest in SHA256 mode.
* @note The API waits for DCIS to be set then reads the computed digest.
* @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in
* HMAC SHA256 mode.
* @param hhash HASH handle.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
{
return HASH_Finish(hhash, pOutBuffer, Timeout);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @brief HMAC extended processing functions using polling mode.
*
@verbatim
===============================================================================
##### Polling mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in polling mode
the HMAC value using one of the following algorithms:
(+) SHA224
(++) HAL_HMACEx_SHA224_Start()
(+) SHA256
(++) HAL_HMACEx_SHA256_Start()
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
* read the computed digest.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @param Timeout Timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer, uint32_t Timeout)
{
return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
* @brief HMAC extended processing functions using interruption mode.
*
@verbatim
===============================================================================
##### Interrupt mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in interrupt mode
the HMAC value using one of the following algorithms:
(+) SHA224
(++) HAL_HMACEx_SHA224_Start_IT()
(+) SHA256
(++) HAL_HMACEx_SHA256_Start_IT()
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
* read the computed digest in interrupt mode.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then
* read the computed digest in interrupt mode.
* @note Digest is available in pOutBuffer.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size,
uint8_t *pOutBuffer)
{
return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
* @brief HMAC extended processing functions using DMA mode.
*
@verbatim
===============================================================================
##### DMA mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
the HMAC value using one of the following algorithms:
(+) SHA224
(++) HAL_HMACEx_SHA224_Start_DMA()
(+) SHA256
(++) HAL_HMACEx_SHA256_Start_DMA()
[..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing,
user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest
with HAL_HASHEx_xxx_Finish().
@endverbatim
* @{
*/
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve
* the computed digest.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note If MDMAT bit is set before calling this function (multi-buffer
* HASH processing case), the input buffer size (in bytes) must be
* a multiple of 4 otherwise, the HASH digest computation is corrupted.
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
* DMA transfers to feed the key and the input buffer to the Peripheral.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note If MDMAT bit is set before calling this function (multi-buffer
* HASH processing case), the input buffer size (in bytes) must be
* a multiple of 4 otherwise, the HASH digest computation is corrupted.
* For the processing of the last buffer of the thread, MDMAT bit must
* be reset and the buffer length (in bytes) doesn't have to be a
* multiple of 4.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (buffer to be hashed).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
* @brief HMAC extended processing functions in multi-buffer DMA mode.
*
@verbatim
===============================================================================
##### Multi-buffer DMA mode HMAC extended processing functions #####
===============================================================================
[..] This section provides functions to manage HMAC multi-buffer
DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms.
(+) MD5
(++) HAL_HMACEx_MD5_Step1_2_DMA()
(++) HAL_HMACEx_MD5_Step2_DMA()
(++) HAL_HMACEx_MD5_Step2_3_DMA()
(+) SHA1
(++) HAL_HMACEx_SHA1_Step1_2_DMA()
(++) HAL_HMACEx_SHA1_Step2_DMA()
(++) HAL_HMACEx_SHA1_Step2_3_DMA()
(+) SHA256
(++) HAL_HMACEx_SHA224_Step1_2_DMA()
(++) HAL_HMACEx_SHA224_Step2_DMA()
(++) HAL_HMACEx_SHA224_Step2_3_DMA()
(+) SHA256
(++) HAL_HMACEx_SHA256_Step1_2_DMA()
(++) HAL_HMACEx_SHA256_Step2_DMA()
(++) HAL_HMACEx_SHA256_Step2_3_DMA()
[..] User must first start-up the multi-buffer DMA-based HMAC computation in
calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and
intiates step 2 with the first input buffer.
[..] The following buffers are next fed to the Peripheral with a call to the API
HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls
to this API.
[..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to
HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input
buffer to the Peripheral then carries out step 3.
[..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or
SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256.
[..] If only two buffers need to be consecutively processed, a call to
HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA()
is sufficient.
@endverbatim
* @{
*/
/**
* @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
* @brief MD5 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
return HAL_ERROR;
}
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
* @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
* then carries out HMAC step 3.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
}
/**
* @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief SHA1 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
return HAL_ERROR;
}
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
* then carries out HMAC step 3.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
}
/**
* @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief SHA224 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
return HAL_ERROR;
}
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
* then carries out HMAC step 3.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
}
/**
* @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode.
* @note Step 1 consists in writing the inner hash function key in the Peripheral,
* step 2 consists in writing the message text.
* @note The API carries out the HMAC step 1 then starts step 2 with
* the first buffer entered to the Peripheral. DCAL bit is not automatically set after
* the message buffer feeding, allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = SET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief SHA256 HMAC step 2 in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the Peripheral.
* @note The API carries on the HMAC step 2, applied to the buffer entered as input
* parameter. DCAL bit is not automatically set after the message buffer feeding,
* allowing other messages DMA transfers to occur.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the
* HASH digest computation is corrupted.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
if (hhash->DigestCalculationDisable != SET)
{
return HAL_ERROR;
}
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode.
* @note Step 2 consists in writing the message text in the Peripheral,
* step 3 consists in writing the outer hash function key.
* @note The API wraps up the HMAC step 2 in processing the buffer entered as input
* parameter (the input buffer must be the last one of the multi-buffer thread)
* then carries out HMAC step 3.
* @note Same key is used for the inner and the outer hash functions; pointer to key and
* key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize.
* @note Once the DMA transfers are finished (indicated by hhash->State set back
* to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve
* the computed digest.
* @param hhash HASH handle.
* @param pInBuffer pointer to the input buffer (message buffer).
* @param Size length of the input buffer in bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
{
hhash->DigestCalculationDisable = RESET;
return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_HASH_MODULE_ENABLED */
/**
* @}
*/
#endif /* HASH*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c
|
C
|
apache-2.0
| 48,293
|
/**
******************************************************************************
* @file stm32u5xx_hal_hcd.c
* @author MCD Application Team
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#)Declare a HCD_HandleTypeDef handle structure, for example:
HCD_HandleTypeDef hhcd;
(#)Fill parameters of Init structure in HCD handle
(#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
(#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
(##) Enable the HCD/USB Low Level interface clock using the following macros
(+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
(+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
(+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
(##) Initialize the related GPIO clocks
(##) Configure HCD pin-out
(##) Configure HCD NVIC interrupt
(#)Associate the Upper USB Host stack to the HAL HCD Driver:
(##) hhcd.pData = phost;
(#)Enable HCD transmission and reception:
(##) HAL_HCD_Start();
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_HCD_MODULE_ENABLED
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/** @defgroup HCD HCD
* @brief HCD HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup HCD_Private_Functions HCD Private Functions
* @{
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HCD_Exported_Functions HCD Exported Functions
* @{
*/
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
@endverbatim
* @{
*/
/**
* @brief Initialize the host driver.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
#if defined (STM32U575xx) || defined (STM32U585xx)
USB_OTG_GlobalTypeDef *USBx;
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
/* Check the HCD handle allocation */
if (hhcd == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
#if defined (STM32U575xx) || defined (STM32U585xx)
USBx = hhcd->Instance;
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
if (hhcd->State == HAL_HCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hhcd->Lock = HAL_UNLOCKED;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->SOFCallback = HAL_HCD_SOF_Callback;
hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback;
if (hhcd->MspInitCallback == NULL)
{
hhcd->MspInitCallback = HAL_HCD_MspInit;
}
/* Init the low level hardware */
hhcd->MspInitCallback(hhcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_HCD_MspInit(hhcd);
#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
}
hhcd->State = HAL_HCD_STATE_BUSY;
#if defined (STM32U575xx) || defined (STM32U585xx)
/* Disable DMA mode for FS instance */
if ((USBx->CID & (0x1U << 8)) == 0U)
{
hhcd->Init.dma_enable = 0U;
}
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
/* Init the Core (common init.) */
(void)USB_CoreInit(hhcd->Instance, hhcd->Init);
/* Force Host Mode*/
(void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
/* Init Host */
(void)USB_HostInit(hhcd->Instance, hhcd->Init);
hhcd->State = HAL_HCD_STATE_READY;
return HAL_OK;
}
/**
* @brief Initialize a host channel.
* @param hhcd HCD handle
* @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @param epnum Endpoint number.
* This parameter can be a value from 1 to 15
* @param dev_address Current device address
* This parameter can be a value from 0 to 255
* @param speed Current device speed.
* This parameter can be one of these values:
* HCD_DEVICE_SPEED_HIGH: High speed mode,
* HCD_DEVICE_SPEED_FULL: Full speed mode,
* HCD_DEVICE_SPEED_LOW: Low speed mode
* @param ep_type Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type,
* EP_TYPE_ISOC: Isochronous type,
* EP_TYPE_BULK: Bulk type,
* EP_TYPE_INTR: Interrupt type
* @param mps Max Packet Size.
* This parameter can be a value from 0 to32K
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps)
{
HAL_StatusTypeDef status;
__HAL_LOCK(hhcd);
hhcd->hc[ch_num].do_ping = 0U;
hhcd->hc[ch_num].dev_addr = dev_address;
hhcd->hc[ch_num].max_packet = mps;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].ep_type = ep_type;
hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
if ((epnum & 0x80U) == 0x80U)
{
hhcd->hc[ch_num].ep_is_in = 1U;
}
else
{
hhcd->hc[ch_num].ep_is_in = 0U;
}
hhcd->hc[ch_num].speed = speed;
status = USB_HC_Init(hhcd->Instance,
ch_num,
epnum,
dev_address,
speed,
ep_type,
mps);
__HAL_UNLOCK(hhcd);
return status;
}
/**
* @brief Halt a host channel.
* @param hhcd HCD handle
* @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
{
HAL_StatusTypeDef status = HAL_OK;
__HAL_LOCK(hhcd);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_UNLOCK(hhcd);
return status;
}
/**
* @brief DeInitialize the host driver.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
{
/* Check the HCD handle allocation */
if (hhcd == NULL)
{
return HAL_ERROR;
}
hhcd->State = HAL_HCD_STATE_BUSY;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
if (hhcd->MspDeInitCallback == NULL)
{
hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware */
hhcd->MspDeInitCallback(hhcd);
#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_HCD_MspDeInit(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
__HAL_HCD_DISABLE(hhcd);
hhcd->State = HAL_HCD_STATE_RESET;
return HAL_OK;
}
/**
* @brief Initialize the HCD MSP.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the HCD MSP.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @brief HCD IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to manage the USB Host Data
Transfer
@endverbatim
* @{
*/
/**
* @brief Submit a new URB for processing.
* @param hhcd HCD handle
* @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @param direction Channel number.
* This parameter can be one of these values:
* 0 : Output / 1 : Input
* @param ep_type Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type/
* EP_TYPE_ISOC: Isochronous type/
* EP_TYPE_BULK: Bulk type/
* EP_TYPE_INTR: Interrupt type/
* @param token Endpoint Type.
* This parameter can be one of these values:
* 0: HC_PID_SETUP / 1: HC_PID_DATA1
* @param pbuff pointer to URB data
* @param length Length of URB data
* @param do_ping activate do ping protocol (for high speed only).
* This parameter can be one of these values:
* 0 : do ping inactive / 1 : do ping active
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
uint8_t direction,
uint8_t ep_type,
uint8_t token,
uint8_t *pbuff,
uint16_t length,
uint8_t do_ping)
{
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
if (token == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
hhcd->hc[ch_num].do_ping = do_ping;
}
else
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
/* Manage Data Toggle */
switch (ep_type)
{
case EP_TYPE_CTRL:
if ((token == 1U) && (direction == 0U)) /*send data */
{
if (length == 0U)
{
/* For Status OUT stage, Length==0, Status Out PID = 1 */
hhcd->hc[ch_num].toggle_out = 1U;
}
/* Set the Data Toggle bit as per the Flag */
if (hhcd->hc[ch_num].toggle_out == 0U)
{
/* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
/* Put the PID 1 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
break;
case EP_TYPE_BULK:
if (direction == 0U)
{
/* Set the Data Toggle bit as per the Flag */
if (hhcd->hc[ch_num].toggle_out == 0U)
{
/* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
/* Put the PID 1 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
else
{
if (hhcd->hc[ch_num].toggle_in == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
break;
case EP_TYPE_INTR:
if (direction == 0U)
{
/* Set the Data Toggle bit as per the Flag */
if (hhcd->hc[ch_num].toggle_out == 0U)
{
/* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
/* Put the PID 1 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
else
{
if (hhcd->hc[ch_num].toggle_in == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
break;
case EP_TYPE_ISOC:
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
break;
default:
break;
}
hhcd->hc[ch_num].xfer_buff = pbuff;
hhcd->hc[ch_num].xfer_len = length;
hhcd->hc[ch_num].urb_state = URB_IDLE;
hhcd->hc[ch_num].xfer_count = 0U;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].state = HC_IDLE;
return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable);
}
/**
* @brief Handle HCD interrupt request.
* @param hhcd HCD handle
* @retval None
*/
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i;
uint32_t interrupt;
/* Ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
{
/* Avoid spurious interrupt */
if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
{
return;
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
}
/* Handle Host Disconnect Interrupts */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
{
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
{
/* Flush USB Fifo */
(void)USB_FlushTxFifo(USBx, 0x10U);
(void)USB_FlushRxFifo(USBx);
/* Restore FS Clock */
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
/* Handle Host Port Disconnect Interrupt */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->DisconnectCallback(hhcd);
#else
HAL_HCD_Disconnect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
}
/* Handle Host Port Interrupts */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
{
HCD_Port_IRQHandler(hhcd);
}
/* Handle Host SOF Interrupt */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
{
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->SOFCallback(hhcd);
#else
HAL_HCD_SOF_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
}
/* Handle Rx Queue Level Interrupts */
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
HCD_RXQLVL_IRQHandler(hhcd);
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
/* Handle Host channel Interrupt */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
for (i = 0U; i < hhcd->Init.Host_channels; i++)
{
if ((interrupt & (1UL << (i & 0xFU))) != 0U)
{
if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
{
HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
}
else
{
HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
}
}
}
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
}
}
}
/**
* @brief SOF callback.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_SOF_Callback could be implemented in the user file
*/
}
/**
* @brief Connection Event callback.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Connect_Callback could be implemented in the user file
*/
}
/**
* @brief Disconnection Event callback.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
}
/**
* @brief Port Enabled Event callback.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
}
/**
* @brief Port Disabled Event callback.
* @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
}
/**
* @brief Notify URB state change callback.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @param urb_state:
* This parameter can be one of these values:
* URB_IDLE/
* URB_DONE/
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
* URB_STALL/
* @retval None
*/
__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
UNUSED(chnum);
UNUSED(urb_state);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
*/
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User USB HCD Callback
* To be used instead of the weak predefined callback
* @param hhcd USB HCD handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
* @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
* @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
* @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID
* @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID
* @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd,
HAL_HCD_CallbackIDTypeDef CallbackID,
pHCD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hhcd);
if (hhcd->State == HAL_HCD_STATE_READY)
{
switch (CallbackID)
{
case HAL_HCD_SOF_CB_ID :
hhcd->SOFCallback = pCallback;
break;
case HAL_HCD_CONNECT_CB_ID :
hhcd->ConnectCallback = pCallback;
break;
case HAL_HCD_DISCONNECT_CB_ID :
hhcd->DisconnectCallback = pCallback;
break;
case HAL_HCD_PORT_ENABLED_CB_ID :
hhcd->PortEnabledCallback = pCallback;
break;
case HAL_HCD_PORT_DISABLED_CB_ID :
hhcd->PortDisabledCallback = pCallback;
break;
case HAL_HCD_MSPINIT_CB_ID :
hhcd->MspInitCallback = pCallback;
break;
case HAL_HCD_MSPDEINIT_CB_ID :
hhcd->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hhcd->State == HAL_HCD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_HCD_MSPINIT_CB_ID :
hhcd->MspInitCallback = pCallback;
break;
case HAL_HCD_MSPDEINIT_CB_ID :
hhcd->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hhcd);
return status;
}
/**
* @brief Unregister an USB HCD Callback
* USB HCD callback is redirected to the weak predefined callback
* @param hhcd USB HCD handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID
* @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID
* @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID
* @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID
* @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID
* @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hhcd);
/* Setup Legacy weak Callbacks */
if (hhcd->State == HAL_HCD_STATE_READY)
{
switch (CallbackID)
{
case HAL_HCD_SOF_CB_ID :
hhcd->SOFCallback = HAL_HCD_SOF_Callback;
break;
case HAL_HCD_CONNECT_CB_ID :
hhcd->ConnectCallback = HAL_HCD_Connect_Callback;
break;
case HAL_HCD_DISCONNECT_CB_ID :
hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback;
break;
case HAL_HCD_PORT_ENABLED_CB_ID :
hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback;
break;
case HAL_HCD_PORT_DISABLED_CB_ID :
hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback;
break;
case HAL_HCD_MSPINIT_CB_ID :
hhcd->MspInitCallback = HAL_HCD_MspInit;
break;
case HAL_HCD_MSPDEINIT_CB_ID :
hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
break;
default :
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hhcd->State == HAL_HCD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_HCD_MSPINIT_CB_ID :
hhcd->MspInitCallback = HAL_HCD_MspInit;
break;
case HAL_HCD_MSPDEINIT_CB_ID :
hhcd->MspDeInitCallback = HAL_HCD_MspDeInit;
break;
default :
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hhcd);
return status;
}
/**
* @brief Register USB HCD Host Channel Notify URB Change Callback
* To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
* @param hhcd HCD handle
* @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd,
pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hhcd);
if (hhcd->State == HAL_HCD_STATE_READY)
{
hhcd->HC_NotifyURBChangeCallback = pCallback;
}
else
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hhcd);
return status;
}
/**
* @brief Unregister the USB HCD Host Channel Notify URB Change Callback
* USB HCD Host Channel Notify URB Change Callback is redirected
* to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hhcd);
if (hhcd->State == HAL_HCD_STATE_READY)
{
hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */
}
else
{
/* Update the error code */
hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hhcd);
return status;
}
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @brief Management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the HCD data
transfers.
@endverbatim
* @{
*/
/**
* @brief Start the host driver.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
{
__HAL_LOCK(hhcd);
/* Enable port power */
(void)USB_DriveVbus(hhcd->Instance, 1U);
/* Enable global interrupt */
__HAL_HCD_ENABLE(hhcd);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
/**
* @brief Stop the host driver.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
{
__HAL_LOCK(hhcd);
(void)USB_StopHost(hhcd->Instance);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
/**
* @brief Reset the host port.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
{
return (USB_ResetPort(hhcd->Instance));
}
/**
* @}
*/
/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the HCD handle state.
* @param hhcd HCD handle
* @retval HAL state
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
{
return hhcd->State;
}
/**
* @brief Return URB state for a channel.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval URB state.
* This parameter can be one of these values:
* URB_IDLE/
* URB_DONE/
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
* URB_STALL
*/
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].urb_state;
}
/**
* @brief Return the last host transfer size.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval last transfer size in byte
*/
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].xfer_count;
}
/**
* @brief Return the Host Channel state.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval Host channel state
* This parameter can be one of these values:
* HC_IDLE/
* HC_XFRC/
* HC_HALTED/
* HC_NYET/
* HC_NAK/
* HC_STALL/
* HC_XACTERR/
* HC_BBLERR/
* HC_DATATGLERR
*/
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].state;
}
/**
* @brief Return the current Host frame number.
* @param hhcd HCD handle
* @retval Current Host frame number
*/
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
{
return (USB_GetCurrentFrame(hhcd->Instance));
}
/**
* @brief Return the Host enumeration speed.
* @param hhcd HCD handle
* @retval Enumeration speed
*/
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
{
return (USB_GetHostSpeed(hhcd->Instance));
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup HCD_Private_Functions
* @{
*/
/**
* @brief Handle Host Channel IN interrupt requests.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t ch_num = (uint32_t)chnum;
uint32_t tmpreg;
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
hhcd->hc[ch_num].state = HC_BBLERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
hhcd->hc[ch_num].state = HC_STALL;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
hhcd->hc[ch_num].state = HC_DATATGLERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else
{
/* ... */
}
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
{
if (hhcd->Init.dma_enable != 0U)
{
hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \
(USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
}
hhcd->hc[ch_num].state = HC_XFRC;
hhcd->hc[ch_num].ErrCnt = 0U;
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC))
{
USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
hhcd->hc[ch_num].urb_state = URB_DONE;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
/* ... */
}
if (hhcd->Init.dma_enable == 1U)
{
if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U)
{
hhcd->hc[ch_num].toggle_in ^= 1U;
}
}
else
{
hhcd->hc[ch_num].toggle_in ^= 1U;
}
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
if (hhcd->hc[ch_num].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
}
else if (hhcd->hc[ch_num].state == HC_STALL)
{
hhcd->hc[ch_num].urb_state = URB_STALL;
}
else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
(hhcd->hc[ch_num].state == HC_DATATGLERR))
{
hhcd->hc[ch_num].ErrCnt++;
if (hhcd->hc[ch_num].ErrCnt > 2U)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
}
else
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
/* re-activate the channel */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
}
}
else if (hhcd->hc[ch_num].state == HC_NAK)
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
/* re-activate the channel */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
}
else if (hhcd->hc[ch_num].state == HC_BBLERR)
{
hhcd->hc[ch_num].ErrCnt++;
hhcd->hc[ch_num].urb_state = URB_ERROR;
}
else
{
/* ... */
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
{
hhcd->hc[ch_num].ErrCnt = 0U;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
hhcd->hc[ch_num].ErrCnt = 0U;
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].state = HC_NAK;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
}
else
{
/* ... */
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
else
{
/* ... */
}
}
/**
* @brief Handle Host Channel OUT interrupt requests.
* @param hhcd HCD handle
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t ch_num = (uint32_t)chnum;
uint32_t tmpreg;
uint32_t num_packets;
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
if (hhcd->hc[ch_num].do_ping == 1U)
{
hhcd->hc[ch_num].do_ping = 0U;
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
{
hhcd->hc[ch_num].ErrCnt = 0U;
/* transaction completed with NYET state, update do ping state */
if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
{
hhcd->hc[ch_num].do_ping = 1U;
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
hhcd->hc[ch_num].state = HC_XFRC;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
{
hhcd->hc[ch_num].state = HC_NYET;
hhcd->hc[ch_num].do_ping = 1U;
hhcd->hc[ch_num].ErrCnt = 0U;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
{
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
hhcd->hc[ch_num].state = HC_STALL;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].state = HC_NAK;
if (hhcd->hc[ch_num].do_ping == 0U)
{
if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH)
{
hhcd->hc[ch_num].do_ping = 1U;
}
}
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
{
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].state = HC_XACTERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
}
else
{
hhcd->hc[ch_num].ErrCnt++;
if (hhcd->hc[ch_num].ErrCnt > 2U)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
}
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
{
hhcd->hc[ch_num].state = HC_DATATGLERR;
(void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
}
else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
{
if (hhcd->hc[ch_num].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
{
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].toggle_out ^= 1U;
}
if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U))
{
num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
if ((num_packets & 1U) != 0U)
{
hhcd->hc[ch_num].toggle_out ^= 1U;
}
}
}
}
else if (hhcd->hc[ch_num].state == HC_NAK)
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
}
else if (hhcd->hc[ch_num].state == HC_NYET)
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
}
else if (hhcd->hc[ch_num].state == HC_STALL)
{
hhcd->hc[ch_num].urb_state = URB_STALL;
}
else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
(hhcd->hc[ch_num].state == HC_DATATGLERR))
{
hhcd->hc[ch_num].ErrCnt++;
if (hhcd->hc[ch_num].ErrCnt > 2U)
{
hhcd->hc[ch_num].ErrCnt = 0U;
hhcd->hc[ch_num].urb_state = URB_ERROR;
}
else
{
hhcd->hc[ch_num].urb_state = URB_NOTREADY;
/* re-activate the channel */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
}
}
else
{
/* ... */
}
__HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
/* ... */
}
}
/**
* @brief Handle Rx Queue Level interrupt requests.
* @param hhcd HCD handle
* @retval none
*/
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t pktsts;
uint32_t pktcnt;
uint32_t GrxstspReg;
uint32_t xferSizePktCnt;
uint32_t tmpreg;
uint32_t ch_num;
GrxstspReg = hhcd->Instance->GRXSTSP;
ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
switch (pktsts)
{
case GRXSTS_PKTSTS_IN:
/* Read the data into the host buffer. */
if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
{
if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len)
{
(void)USB_ReadPacket(hhcd->Instance,
hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
/* manage multiple Xfer */
hhcd->hc[ch_num].xfer_buff += pktcnt;
hhcd->hc[ch_num].xfer_count += pktcnt;
/* get transfer size packet count */
xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U))
{
/* re-activate the channel when more packets are expected */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
hhcd->hc[ch_num].toggle_in ^= 1U;
}
}
else
{
hhcd->hc[ch_num].urb_state = URB_ERROR;
}
}
break;
case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
break;
case GRXSTS_PKTSTS_IN_XFER_COMP:
case GRXSTS_PKTSTS_CH_HALTED:
default:
break;
}
}
/**
* @brief Handle Host Port interrupt requests.
* @param hhcd HCD handle
* @retval None
*/
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0;
__IO uint32_t hprt0_dup;
/* Handle Host Port Interrupts */
hprt0 = USBx_HPRT0;
hprt0_dup = USBx_HPRT0;
hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
/* Check whether Port Connect detected */
if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
{
if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
{
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->ConnectCallback(hhcd);
#else
HAL_HCD_Connect_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
hprt0_dup |= USB_OTG_HPRT_PCDET;
}
/* Check whether Port Enable Changed */
if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
{
hprt0_dup |= USB_OTG_HPRT_PENCHNG;
if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
{
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
{
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
{
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
}
else
{
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
}
}
else
{
if (hhcd->Init.speed == HCD_SPEED_FULL)
{
USBx_HOST->HFIR = 60000U;
}
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->PortEnabledCallback(hhcd);
#else
HAL_HCD_PortEnabled_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->PortDisabledCallback(hhcd);
#else
HAL_HCD_PortDisabled_Callback(hhcd);
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
}
/* Check for an overcurrent */
if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
{
hprt0_dup |= USB_OTG_HPRT_POCCHNG;
}
/* Clear Port Interrupts */
USBx_HPRT0 = hprt0_dup;
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_HCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c
|
C
|
apache-2.0
| 48,433
|
/**
******************************************************************************
* @file stm32u5xx_hal_i2c.c
* @author MCD Application Team
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The I2C HAL driver can be used as follows:
(#) Declare a I2C_HandleTypeDef handle structure, for example:
I2C_HandleTypeDef hi2c;
(#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
(##) Enable the I2Cx interface clock
(##) I2C pins configuration
(+++) Enable the clock for the I2C GPIOs
(+++) Configure I2C pins as alternate function open-drain
(##) NVIC configuration if you need to use interrupt process
(+++) Configure the I2Cx interrupt priority
(+++) Enable the NVIC I2C IRQ Channel
(##) DMA Configuration if you need to use DMA process
(+++) Declare a DMA_HandleTypeDef handle structure for
the transmit or receive channel
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx channel
(+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
the DMA Tx or Rx channel
(#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
(GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
(+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
(+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
(+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
(+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
*** Polling mode IO MEM operation ***
=====================================
[..]
(+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
(+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
*** Interrupt mode IO operation ***
===================================
[..]
(+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
(+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
(+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
(+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
(+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
(+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
(+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
(+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode or DMA mode IO sequential operation ***
==========================================================
[..]
(@) These interfaces allow to manage a sequential transfer with a repeated start condition
when a direction change during transfer
[..]
(+) A specific option field manage the different steps of a sequential transfer
(+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
start condition, address and data to transfer without a final stop condition,
an then permit a call the same master sequential interface several times
(like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to
transfer
if no direction change and without a final stop condition in both cases
(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to
transfer
if no direction change and with a final stop condition in both cases
(++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
after several call of the same master sequential interface several times
(link with option I2C_FIRST_AND_NEXT_FRAME).
Usage can, transfer several bytes one by one using
HAL_I2C_Master_Seq_Transmit_IT
or HAL_I2C_Master_Seq_Receive_IT
or HAL_I2C_Master_Seq_Transmit_DMA
or HAL_I2C_Master_Seq_Receive_DMA
with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
Receive sequence permit to call the opposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
(++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
each call of the same master sequential
interface.
Usage can, transfer several bytes one by one with a restart with slave address between
each bytes using
HAL_I2C_Master_Seq_Transmit_IT
or HAL_I2C_Master_Seq_Receive_IT
or HAL_I2C_Master_Seq_Transmit_DMA
or HAL_I2C_Master_Seq_Receive_DMA
with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
generation of STOP condition.
(+) Different sequential I2C interfaces are listed below:
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
(+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
(++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
(++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
HAL_I2C_DisableListen_IT()
(+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
add their own code to check the Address Match Code and the transmission direction request by master
(Write/Read).
(+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
(++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
(+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
(++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
(++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode IO MEM operation ***
=======================================
[..]
(+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
HAL_I2C_Mem_Write_IT()
(+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
HAL_I2C_Mem_Read_IT()
(+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
(+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Master_Transmit_DMA()
(+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
(+) Receive in master mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Master_Receive_DMA()
(+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
(+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Slave_Transmit_DMA()
(+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
(+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
HAL_I2C_Slave_Receive_DMA()
(+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** DMA mode IO MEM operation ***
=================================
[..]
(+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
HAL_I2C_Mem_Write_DMA()
(+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
HAL_I2C_Mem_Read_DMA()
(+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
*** I2C HAL driver macros list ***
==================================
[..]
Below the list of most used macros in I2C HAL driver.
(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
(+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
(+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
(+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
to register an interrupt callback.
[..]
Function HAL_I2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
(+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
(+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
(+) ListenCpltCallback : callback for end of listen mode.
(+) MemTxCpltCallback : callback for Memory transmission end of transfer.
(+) MemRxCpltCallback : callback for Memory reception end of transfer.
(+) ErrorCallback : callback for error detection.
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
[..]
Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
weak function.
HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
(+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
(+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
(+) ListenCpltCallback : callback for end of listen mode.
(+) MemTxCpltCallback : callback for Memory transmission end of transfer.
(+) MemRxCpltCallback : callback for Memory reception end of transfer.
(+) ErrorCallback : callback for error detection.
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
[..]
By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
or HAL_I2C_Init() function.
[..]
When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
[..]
(@) You can refer to the I2C HAL driver header file for more useful macros
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup I2C I2C
* @brief I2C HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup I2C_Private_Define I2C Private Define
* @{
*/
#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
#define MAX_NBYTE_SIZE 255U
#define SLAVE_ADDR_SHIFT 7U
#define SLAVE_ADDR_MSK 0x06U
/* Private define for @ref PreviousState usage */
#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
(uint32_t)HAL_I2C_STATE_BUSY_RX) & \
(uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
/*!< Mask State define, keep only RX and TX bits */
#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
/*!< Default Value */
#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
(uint32_t)HAL_I2C_MODE_MASTER))
/*!< Master Busy TX, combinaison of State LSB and Mode enum */
#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
(uint32_t)HAL_I2C_MODE_MASTER))
/*!< Master Busy RX, combinaison of State LSB and Mode enum */
#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
(uint32_t)HAL_I2C_MODE_SLAVE))
/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
(uint32_t)HAL_I2C_MODE_SLAVE))
/*!< Slave Busy RX, combinaison of State LSB and Mode enum */
#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
(uint32_t)HAL_I2C_MODE_MEM))
/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
(uint32_t)HAL_I2C_MODE_MEM))
/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
/* Private define to centralize the enable/disable of Interrupts */
#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
@ref I2C_XFER_LISTEN_IT */
#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
@ref I2C_XFER_LISTEN_IT */
#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
and @ref I2C_XFER_RX_IT */
#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
and NACK treatment */
#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Macro to get remaining data to transfer on DMA side */
#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__))
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions to handle DMA transfer */
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
/* Private functions to handle IT transfer */
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
/* Private functions to handle IT transfer */
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart);
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart);
/* Private functions for I2C transfer IRQ handler */
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
/* Private functions to handle flags during polling transfer */
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart);
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
/* Private function to treat different error callback */
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
/* Private function to handle start, restart or stop a transfer */
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request);
/* Private function to Convert Specific options */
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup I2C_Exported_Functions I2C Exported Functions
* @{
*/
/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
deinitialize the I2Cx peripheral:
(+) User must Implement HAL_I2C_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
(+) Call the function HAL_I2C_Init() to configure the selected device with
the selected configuration:
(++) Clock Timing
(++) Own Address 1
(++) Addressing mode (Master, Slave)
(++) Dual Addressing mode
(++) Own Address 2
(++) Own Address 2 Mask
(++) General call mode
(++) Nostretch mode
(+) Call the function HAL_I2C_DeInit() to restore the default configuration
of the selected I2Cx peripheral.
@endverbatim
* @{
*/
/**
* @brief Initializes the I2C according to the specified parameters
* in the I2C_InitTypeDef and initialize the associated handle.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
if (hi2c == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/* Init the I2C Callback settings */
hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
if (hi2c->MspInitCallback == NULL)
{
hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
(hi2c->Init.OwnAddress2Masks << 8));
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
return HAL_OK;
}
/**
* @brief DeInitialize the I2C peripheral.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
if (hi2c == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the I2C Peripheral Clock */
__HAL_I2C_DISABLE(hi2c);
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
if (hi2c->MspDeInitCallback == NULL)
{
hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
hi2c->MspDeInitCallback(hi2c);
#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_I2C_MspDeInit(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_RESET;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Release Lock */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Initialize the I2C MSP.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the I2C MSP.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspDeInit could be implemented in the user file
*/
}
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User I2C Callback
* To be used instead of the weak predefined callback
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
* @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
* @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
* @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
* @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
* @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
* @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
* @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
* @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
* @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
pI2C_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
switch (CallbackID)
{
case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
hi2c->MasterTxCpltCallback = pCallback;
break;
case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
hi2c->MasterRxCpltCallback = pCallback;
break;
case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
hi2c->SlaveTxCpltCallback = pCallback;
break;
case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
hi2c->SlaveRxCpltCallback = pCallback;
break;
case HAL_I2C_LISTEN_COMPLETE_CB_ID :
hi2c->ListenCpltCallback = pCallback;
break;
case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
hi2c->MemTxCpltCallback = pCallback;
break;
case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
hi2c->MemRxCpltCallback = pCallback;
break;
case HAL_I2C_ERROR_CB_ID :
hi2c->ErrorCallback = pCallback;
break;
case HAL_I2C_ABORT_CB_ID :
hi2c->AbortCpltCallback = pCallback;
break;
case HAL_I2C_MSPINIT_CB_ID :
hi2c->MspInitCallback = pCallback;
break;
case HAL_I2C_MSPDEINIT_CB_ID :
hi2c->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_I2C_STATE_RESET == hi2c->State)
{
switch (CallbackID)
{
case HAL_I2C_MSPINIT_CB_ID :
hi2c->MspInitCallback = pCallback;
break;
case HAL_I2C_MSPDEINIT_CB_ID :
hi2c->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hi2c);
return status;
}
/**
* @brief Unregister an I2C Callback
* I2C callback is redirected to the weak predefined callback
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* This parameter can be one of the following values:
* @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
* @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
* @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
* @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
* @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
* @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
* @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
* @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
* @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
* @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
switch (CallbackID)
{
case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
break;
case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
break;
case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
break;
case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
break;
case HAL_I2C_LISTEN_COMPLETE_CB_ID :
hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
break;
case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
break;
case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
break;
case HAL_I2C_ERROR_CB_ID :
hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_I2C_ABORT_CB_ID :
hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_I2C_MSPINIT_CB_ID :
hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
break;
case HAL_I2C_MSPDEINIT_CB_ID :
hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_I2C_STATE_RESET == hi2c->State)
{
switch (CallbackID)
{
case HAL_I2C_MSPINIT_CB_ID :
hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
break;
case HAL_I2C_MSPDEINIT_CB_ID :
hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hi2c);
return status;
}
/**
* @brief Register the Slave Address Match I2C Callback
* To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pCallback pointer to the Address Match Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
hi2c->AddrCallback = pCallback;
}
else
{
/* Update the error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hi2c);
return status;
}
/**
* @brief UnRegister the Slave Address Match I2C Callback
* Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
}
else
{
/* Update the error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hi2c);
return status;
}
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the I2C data
transfers.
(#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode : The communication is performed using Interrupts
or DMA. These functions return the status of the transfer startup.
The end of the data processing will be indicated through the
dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
(#) Blocking mode functions are :
(++) HAL_I2C_Master_Transmit()
(++) HAL_I2C_Master_Receive()
(++) HAL_I2C_Slave_Transmit()
(++) HAL_I2C_Slave_Receive()
(++) HAL_I2C_Mem_Write()
(++) HAL_I2C_Mem_Read()
(++) HAL_I2C_IsDeviceReady()
(#) No-Blocking mode functions with Interrupt are :
(++) HAL_I2C_Master_Transmit_IT()
(++) HAL_I2C_Master_Receive_IT()
(++) HAL_I2C_Slave_Transmit_IT()
(++) HAL_I2C_Slave_Receive_IT()
(++) HAL_I2C_Mem_Write_IT()
(++) HAL_I2C_Mem_Read_IT()
(++) HAL_I2C_Master_Seq_Transmit_IT()
(++) HAL_I2C_Master_Seq_Receive_IT()
(++) HAL_I2C_Slave_Seq_Transmit_IT()
(++) HAL_I2C_Slave_Seq_Receive_IT()
(++) HAL_I2C_EnableListen_IT()
(++) HAL_I2C_DisableListen_IT()
(++) HAL_I2C_Master_Abort_IT()
(#) No-Blocking mode functions with DMA are :
(++) HAL_I2C_Master_Transmit_DMA()
(++) HAL_I2C_Master_Receive_DMA()
(++) HAL_I2C_Slave_Transmit_DMA()
(++) HAL_I2C_Slave_Receive_DMA()
(++) HAL_I2C_Mem_Write_DMA()
(++) HAL_I2C_Mem_Read_DMA()
(++) HAL_I2C_Master_Seq_Transmit_DMA()
(++) HAL_I2C_Master_Seq_Receive_DMA()
(++) HAL_I2C_Slave_Seq_Transmit_DMA()
(++) HAL_I2C_Slave_Seq_Receive_DMA()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_I2C_MasterTxCpltCallback()
(++) HAL_I2C_MasterRxCpltCallback()
(++) HAL_I2C_SlaveTxCpltCallback()
(++) HAL_I2C_SlaveRxCpltCallback()
(++) HAL_I2C_MemTxCpltCallback()
(++) HAL_I2C_MemRxCpltCallback()
(++) HAL_I2C_AddrCallback()
(++) HAL_I2C_ListenCpltCallback()
(++) HAL_I2C_ErrorCallback()
(++) HAL_I2C_AbortCpltCallback()
@endverbatim
* @{
*/
/**
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_GENERATE_START_WRITE);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_GENERATE_START_WRITE);
}
while (hi2c->XferCount > 0U)
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferCount--;
hi2c->XferSize--;
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_NO_STARTSTOP);
}
}
}
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_GENERATE_START_READ);
}
while (hi2c->XferCount > 0U)
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferSize--;
hi2c->XferCount--;
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_NO_STARTSTOP);
}
}
}
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Transmits in slave mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout)
{
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Wait until ADDR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* If 10bit addressing mode is selected */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
/* Wait until ADDR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Wait until DIR flag is set Transmitter mode */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
while (hi2c->XferCount > 0U)
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferCount--;
}
/* Wait until AF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Clear AF flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Wait until STOP flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Clear STOP flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive in slave mode an amount of data in blocking mode
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout)
{
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferISR = NULL;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Wait until ADDR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Wait until DIR flag is reset Receiver mode */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
while (hi2c->XferCount > 0U)
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Store Last receive data if any */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
{
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferCount--;
hi2c->XferSize--;
}
return HAL_ERROR;
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferCount--;
hi2c->XferSize--;
}
/* Wait until STOP flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Clear STOP flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size)
{
uint32_t xfermode;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
/* Check if the Autonomous mode is enabled */
if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_WRITE);
}
else
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size)
{
uint32_t xfermode;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
/* Check if the Autonomous mode is enabled */
if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_READ);
}
else
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_IT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_IT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size)
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
if (hi2c->XferSize > 0U)
{
if (hi2c->hdmatx != NULL)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
/* Set the DMA error callback */
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hi2c->hdmatx->XferHalfCpltCallback = NULL;
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmatx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
= (uint32_t)&hi2c->Instance->TXDR;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
hi2c->XferSize);
}
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
/* Check if the Autonomous mode is enabled */
if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
I2C_GENERATE_NO_START_WRITE);
}
else
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
}
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR and NACK interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
/* Update Transfer ISR function pointer */
hi2c->XferISR = I2C_Master_ISR_IT;
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size)
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
if (hi2c->XferSize > 0U)
{
if (hi2c->hdmarx != NULL)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
/* Set the DMA error callback */
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hi2c->hdmarx->XferHalfCpltCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmarx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
= (uint32_t)&hi2c->Instance->RXDR;
/* Set DMA destination address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
hi2c->XferSize);
}
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address */
/* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
/* Check if the Autonomous mode is enabled */
if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
I2C_GENERATE_NO_START_READ);
}
else
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
}
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR and NACK interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
/* Update Transfer ISR function pointer */
hi2c->XferISR = I2C_Master_ISR_IT;
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef dmaxferstatus;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_DMA;
if (hi2c->hdmatx != NULL)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
/* Set the DMA error callback */
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hi2c->hdmatx->XferHalfCpltCallback = NULL;
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmatx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
= (uint32_t)&hi2c->Instance->TXDR;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
hi2c->XferSize);
}
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef dmaxferstatus;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_DMA;
if (hi2c->hdmarx != NULL)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
/* Set the DMA error callback */
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hi2c->hdmarx->XferHalfCpltCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmarx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
= (uint32_t)&hi2c->Instance->RXDR;
/* Set DMA destination address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
hi2c->XferSize);
}
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
do
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferCount--;
hi2c->XferSize--;
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_NO_STARTSTOP);
}
}
} while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Read an amount of data in blocking mode from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_GENERATE_START_READ);
}
do
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferSize--;
hi2c->XferCount--;
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_NO_STARTSTOP);
}
}
} while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
!= HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
!= HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (hi2c->hdmatx != NULL)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
/* Set the DMA error callback */
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hi2c->hdmatx->XferHalfCpltCallback = NULL;
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmatx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
= (uint32_t)&hi2c->Instance->TXDR;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
hi2c->XferSize);
}
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR and NACK interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
* @param Size Amount of data to be read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = I2C_AUTOEND_MODE;
}
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (hi2c->hdmarx != NULL)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
/* Set the DMA error callback */
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hi2c->hdmarx->XferHalfCpltCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmarx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
= (uint32_t)&hi2c->Instance->RXDR;
/* Set DMA destination address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
hi2c->XferSize);
}
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR and NACK interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Checks if target device is ready for communication.
* @note This function is used with Memory devices
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param Trials Number of trials
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout)
{
uint32_t tickstart;
__IO uint32_t I2C_Trials = 0UL;
FlagStatus tmp1;
FlagStatus tmp2;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
do
{
/* Generate Start */
hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
while ((tmp1 == RESET) && (tmp2 == RESET))
{
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
}
/* Check if the NACKF flag has not been set */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
{
/* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Device is ready */
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
/* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Clear STOP Flag, auto generated with autoend*/
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
/* Check if the maximum allowed number of trials has been reached */
if (I2C_Trials == Trials)
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
/* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
/* Increment Trials */
I2C_Trials++;
} while (I2C_Trials < Trials);
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Master_ISR_IT;
/* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = hi2c->XferOptions;
}
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
(IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
else
{
/* Convert OTHER_xxx XferOptions if any */
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
}
/* Send Slave Address and set NBYTES to write */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Master_ISR_DMA;
/* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = hi2c->XferOptions;
}
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
(IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
else
{
/* Convert OTHER_xxx XferOptions if any */
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
}
if (hi2c->XferSize > 0U)
{
if (hi2c->hdmatx != NULL)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
/* Set the DMA error callback */
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hi2c->hdmatx->XferHalfCpltCallback = NULL;
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmatx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
= (uint32_t)&hi2c->Instance->TXDR;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
hi2c->XferSize);
}
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address and set NBYTES to write */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR and NACK interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
/* Update Transfer ISR function pointer */
hi2c->XferISR = I2C_Master_ISR_IT;
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_READ;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Master_ISR_IT;
/* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = hi2c->XferOptions;
}
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
(IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
else
{
/* Convert OTHER_xxx XferOptions if any */
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
}
/* Send Slave Address and set NBYTES to read */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_READ;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Master_ISR_DMA;
/* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
xfermode = hi2c->XferOptions;
}
/* If transfer direction not change and there is no request to start another frame,
do not generate Restart Condition */
/* Mean Previous state is same as current state */
if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
(IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
else
{
/* Convert OTHER_xxx XferOptions if any */
I2C_ConvertOtherXferOptions(hi2c);
/* Update xfermode accordingly if no reload is necessary */
if (hi2c->XferCount <= MAX_NBYTE_SIZE)
{
xfermode = hi2c->XferOptions;
}
}
if (hi2c->XferSize > 0U)
{
if (hi2c->hdmarx != NULL)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
/* Set the DMA error callback */
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hi2c->hdmarx->XferHalfCpltCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmarx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
= (uint32_t)&hi2c->Instance->RXDR;
/* Set DMA destination address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
}
else
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
hi2c->XferSize);
}
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Send Slave Address and set NBYTES to read */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR and NACK interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
/* Update Transfer ISR function pointer */
hi2c->XferISR = I2C_Master_ISR_IT;
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
/* Process Locked */
__HAL_LOCK(hi2c);
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave RX state to TX state */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
/* Abort DMA Xfer if any */
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
if (hi2c->hdmarx != NULL)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
}
}
hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave RX state to TX state */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
/* Abort DMA Xfer if any */
if (hi2c->hdmarx != NULL)
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
}
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
/* Abort DMA Xfer if any */
if (hi2c->hdmatx != NULL)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
}
}
else
{
/* Nothing to do */
}
hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_DMA;
if (hi2c->hdmatx != NULL)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
/* Set the DMA error callback */
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hi2c->hdmatx->XferHalfCpltCallback = NULL;
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmatx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
= (uint32_t)&hi2c->Instance->TXDR;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
hi2c->XferSize);
}
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Reset XferSize */
hi2c->XferSize = 0;
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
/* Process Locked */
__HAL_LOCK(hi2c);
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave TX state to RX state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
/* Abort DMA Xfer if any */
if (hi2c->hdmatx != NULL)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
}
}
hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
if ((pData == NULL) || (Size == 0U))
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
/* Process Locked */
__HAL_LOCK(hi2c);
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave TX state to RX state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
/* Abort DMA Xfer if any */
if (hi2c->hdmatx != NULL)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
}
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
/* Abort DMA Xfer if any */
if (hi2c->hdmarx != NULL)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
}
}
else
{
/* Nothing to do */
}
hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferSize = hi2c->XferCount;
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_DMA;
if (hi2c->hdmarx != NULL)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
/* Set the DMA error callback */
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
/* Set the unused DMA callbacks to NULL */
hi2c->hdmarx->XferHalfCpltCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmarx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
= (uint32_t)&hi2c->Instance->RXDR;
/* Set DMA destination address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
hi2c->XferSize);
}
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Reset XferSize */
hi2c->XferSize = 0;
}
else
{
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Update I2C error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Enable DMA Request */
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Enable the Address listen mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
{
if (hi2c->State == HAL_I2C_STATE_READY)
{
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->XferISR = I2C_Slave_ISR_IT;
/* Enable the Address Match interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable the Address listen mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp;
/* Disable Address listen mode only if a transfer is not ongoing */
if (hi2c->State == HAL_I2C_STATE_LISTEN)
{
tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
/* Disable the Address Match interrupt */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Abort a master I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{
if (hi2c->Mode == HAL_I2C_MODE_MASTER)
{
/* Process Locked */
__HAL_LOCK(hi2c);
/* Disable Interrupts and Store Previous state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Set State at HAL_I2C_STATE_ABORT */
hi2c->State = HAL_I2C_STATE_ABORT;
/* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
/* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
return HAL_OK;
}
else
{
/* Wrong usage of abort function */
/* This function should be used only in case of abort monitored by master device */
return HAL_ERROR;
}
}
/**
* @}
*/
/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/**
* @brief This function handles I2C event interrupt request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
{
/* Get current IT Flags and IT sources value */
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
/* I2C events treatment -------------------------------------*/
if (hi2c->XferISR != NULL)
{
hi2c->XferISR(hi2c, itflags, itsources);
}
}
/**
* @brief This function handles I2C error interrupt request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
{
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
uint32_t tmperror;
/* I2C Bus error interrupt occurred ------------------------------------*/
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
/* Clear BERR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
}
/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
/* Clear OVR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
}
/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
/* Clear ARLO flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
}
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
/* Call the Error Callback in case of Error detected */
if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
{
I2C_ITError(hi2c, tmperror);
}
}
/**
* @brief Master Tx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Master Rx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
*/
}
/** @brief Slave Tx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Slave Rx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Slave Address Match callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
* @param AddrMatchCode Address Match Code
* @retval None
*/
__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
UNUSED(TransferDirection);
UNUSED(AddrMatchCode);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_AddrCallback() could be implemented in the user file
*/
}
/**
* @brief Listen Complete callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_ListenCpltCallback() could be implemented in the user file
*/
}
/**
* @brief Memory Tx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MemTxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Memory Rx Transfer completed callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MemRxCpltCallback could be implemented in the user file
*/
}
/**
* @brief I2C error callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief I2C abort callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_AbortCpltCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @brief Peripheral State, Mode and Error functions
*
@verbatim
===============================================================================
##### Peripheral State, Mode and Error functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the I2C handle state.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
{
/* Return I2C handle state */
return hi2c->State;
}
/**
* @brief Returns the I2C Master, Slave, Memory or no mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL mode
*/
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
{
return hi2c->Mode;
}
/**
* @brief Return the I2C error code.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval I2C Error Code
*/
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
{
return hi2c->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup I2C_Private_Functions
* @{
*/
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param ITFlags Interrupt flags to handle.
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
uint16_t devaddress;
uint32_t tmpITFlags = ITFlags;
/* Process Locked */
__HAL_LOCK(hi2c);
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Set corresponding Error Code */
/* No need to generate STOP, it is automatically done */
/* Error callback will be send during stop flag treatment */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferSize--;
hi2c->XferCount--;
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferSize--;
hi2c->XferCount--;
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
hi2c->XferOptions, I2C_NO_STARTSTOP);
}
else
{
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
else
{
/* Call TxCpltCallback() if no stop mode is set */
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
{
/* Call I2C Master Sequential complete process */
I2C_ITMasterSeqCplt(hi2c);
}
else
{
/* Wrong size Status regarding TCR flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->XferCount == 0U)
{
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
{
/* Generate a stop condition in case of no transfer option */
if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
}
else
{
/* Call I2C Master Sequential complete process */
I2C_ITMasterSeqCplt(hi2c);
}
}
}
else
{
/* Wrong size Status regarding TC flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
else
{
/* Nothing to do */
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param ITFlags Interrupt flags to handle.
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t tmpITFlags = ITFlags;
/* Process locked */
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
{
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
}
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
}
else
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
}
}
else
{
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
}
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
if (hi2c->XferCount > 0U)
{
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferSize--;
hi2c->XferCount--;
}
if ((hi2c->XferCount == 0U) && \
(tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
}
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
I2C_ITAddrCplt(hi2c, tmpITFlags);
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
/* Check if all Data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
{
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferCount--;
hi2c->XferSize--;
}
else
{
if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
{
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
}
}
}
else
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param ITFlags Interrupt flags to handle.
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
uint16_t devaddress;
uint32_t xfermode;
/* Process Locked */
__HAL_LOCK(hi2c);
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Set corresponding Error Code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
/* No need to generate STOP, it is automatically done */
/* But enable STOP interrupt, to treat it */
/* Error callback will be send during stop flag treatment */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
/* Disable TC interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
if (hi2c->XferCount != 0U)
{
/* Recover Slave address */
devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
xfermode = hi2c->XferOptions;
}
else
{
xfermode = I2C_AUTOEND_MODE;
}
}
/* Set the new XferSize in Nbytes register */
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
/* Enable DMA Request */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
}
else
{
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
}
}
else
{
/* Call TxCpltCallback() if no stop mode is set */
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
{
/* Call I2C Master Sequential complete process */
I2C_ITMasterSeqCplt(hi2c);
}
else
{
/* Wrong size Status regarding TCR flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->XferCount == 0U)
{
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
{
/* Generate a stop condition in case of no transfer option */
if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
}
else
{
/* Call I2C Master Sequential complete process */
I2C_ITMasterSeqCplt(hi2c);
}
}
}
else
{
/* Wrong size Status regarding TC flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
}
else
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param ITFlags Interrupt flags to handle.
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t treatdmanack = 0U;
HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
/* So clear Flag NACKF only */
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
{
/* Split check of hdmarx, for MISRA compliance */
if (hi2c->hdmarx != NULL)
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
{
if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
{
treatdmanack = 1U;
}
}
}
/* Split check of hdmatx, for MISRA compliance */
if (hi2c->hdmatx != NULL)
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
{
if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
{
treatdmanack = 1U;
}
}
}
if (treatdmanack == 1U)
{
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
}
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
}
else
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
}
}
else
{
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
/* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
tmpstate = hi2c->State;
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
{
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
}
}
else
{
/* Only Clear NACK Flag, no DMA treatment is pending */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
I2C_ITAddrCplt(hi2c, ITFlags);
}
else
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Master sends target device address followed by internal memory address for write request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Master sends target device address followed by internal memory address for read request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TC flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief I2C Address complete process callback.
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint8_t transferdirection;
uint16_t slaveaddrcode;
uint16_t ownadd1code;
uint16_t ownadd2code;
/* Prevent unused argument(s) compilation warning */
UNUSED(ITFlags);
/* In case of Listen state, need to inform upper layer of address match code event */
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
transferdirection = I2C_GET_DIR(hi2c);
slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
/* If 10bits addressing mode is selected */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
{
slaveaddrcode = ownadd1code;
hi2c->AddrEventCount++;
if (hi2c->AddrEventCount == 2U)
{
/* Reset Address Event counter */
hi2c->AddrEventCount = 0U;
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call Slave Addr callback */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
else
{
slaveaddrcode = ownadd2code;
/* Disable ADDR Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call Slave Addr callback */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/* else 7 bits addressing mode is selected */
else
{
/* Disable ADDR Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call Slave Addr callback */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/* Else clear address flag only */
else
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
}
}
/**
* @brief I2C Master sequential complete process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
{
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
/* No Generate Stop, to permit restart mode */
/* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
hi2c->XferISR = NULL;
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterTxCpltCallback(hi2c);
#else
HAL_I2C_MasterTxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/* hi2c->State == HAL_I2C_STATE_BUSY_RX */
else
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
hi2c->XferISR = NULL;
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
#else
HAL_I2C_MasterRxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/**
* @brief I2C Slave sequential complete process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
}
else
{
/* Do nothing */
}
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->SlaveTxCpltCallback(hi2c);
#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->SlaveRxCpltCallback(hi2c);
#else
HAL_I2C_SlaveRxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
/* Nothing to do */
}
}
/**
* @brief I2C Master complete process.
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmperror;
uint32_t tmpITFlags = ITFlags;
__IO uint32_t tmpreg;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable Interrupts and Store Previous state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Reset handle parameters */
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Set acknowledge error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
/* Fetch Last receive data if any */
if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
tmpreg = (uint8_t)hi2c->Instance->RXDR;
UNUSED(tmpreg);
}
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
/* Call the corresponding callback to inform upper layer of End of Transfer */
if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
/* hi2c->State == HAL_I2C_STATE_BUSY_TX */
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MemTxCpltCallback(hi2c);
#else
HAL_I2C_MemTxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterTxCpltCallback(hi2c);
#else
HAL_I2C_MasterTxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/* hi2c->State == HAL_I2C_STATE_BUSY_RX */
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MemRxCpltCallback(hi2c);
#else
HAL_I2C_MemRxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterRxCpltCallback(hi2c);
#else
HAL_I2C_MasterRxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
else
{
/* Nothing to do */
}
}
/**
* @brief I2C Slave complete process.
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable Interrupts and Store Previous state */
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
else
{
/* Do nothing */
}
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
if (hi2c->hdmatx != NULL)
{
hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
}
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
if (hi2c->hdmarx != NULL)
{
hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
}
}
else
{
/* Do nothing */
}
/* Store Last receive data if any */
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
if ((hi2c->XferSize > 0U))
{
hi2c->XferSize--;
hi2c->XferCount--;
}
}
/* All data are not transferred, so set error code accordingly */
if (hi2c->XferCount != 0U)
{
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
if (hi2c->State == HAL_I2C_STATE_LISTEN)
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
}
}
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
/* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
I2C_ITSlaveSeqCplt(hi2c);
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->ListenCpltCallback(hi2c);
#else
HAL_I2C_ListenCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->SlaveRxCpltCallback(hi2c);
#else
HAL_I2C_SlaveRxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->SlaveTxCpltCallback(hi2c);
#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/**
* @brief I2C Listen complete process.
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
/* Reset handle parameters */
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
/* Store Last receive data if any */
if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
if ((hi2c->XferSize > 0U))
{
hi2c->XferSize--;
hi2c->XferCount--;
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
}
/* Disable all Interrupts*/
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->ListenCpltCallback(hi2c);
#else
HAL_I2C_ListenCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/**
* @brief I2C interrupts error process.
* @param hi2c I2C handle.
* @param ErrorCode Error code to handle.
* @retval None
*/
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
uint32_t tmppreviousstate;
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferCount = 0U;
/* Set new error code */
hi2c->ErrorCode |= ErrorCode;
/* Disable Interrupts */
if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
(tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
(tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
/* Disable all interrupts, except interrupts related to LISTEN state */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->XferISR = I2C_Slave_ISR_IT;
}
else
{
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
/* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
{
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
}
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
tmppreviousstate = hi2c->PreviousState;
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
}
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
else
{
I2C_TreatErrorCallback(hi2c);
}
}
/* Abort DMA RX transfer if any */
else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
}
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
{
/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
else
{
I2C_TreatErrorCallback(hi2c);
}
}
else
{
I2C_TreatErrorCallback(hi2c);
}
}
/**
* @brief I2C Error callback treatment.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
{
if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AbortCpltCallback(hi2c);
#else
HAL_I2C_AbortCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->PreviousState = I2C_STATE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->ErrorCallback(hi2c);
#else
HAL_I2C_ErrorCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/**
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
{
hi2c->Instance->TXDR = 0x00U;
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
}
}
/**
* @brief DMA I2C master transmit process complete callback.
* @param hdma DMA handle
* @retval None
*/
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef dmaxferstatus = HAL_OK;
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
/* If last transfer, enable STOP interrupt */
if (hi2c->XferCount == 0U)
{
/* Enable STOP interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
}
/* else prepare a new DMA transfer and enable TCReload interrupt */
else
{
/* Update Buffer pointer */
hi2c->pBuffPtr += hi2c->XferSize;
/* Set the XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
}
/* Enable the DMA channel */
if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmatx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
/* Set DMA destination address */
hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
}
else
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
hi2c->XferSize);
}
if (dmaxferstatus != HAL_OK)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
}
else
{
/* Enable TC interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
}
}
}
/**
* @brief DMA I2C slave transmit process complete callback.
* @param hdma DMA handle
* @retval None
*/
static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmpoptions = hi2c->XferOptions;
if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
}
else
{
/* No specific action, Master fully manage the generation of STOP condition */
/* Mean that this generation can arrive at any time, at the end or during DMA process */
/* So STOP condition should be manage through Interrupt treatment */
}
}
/**
* @brief DMA I2C master receive process complete callback.
* @param hdma DMA handle
* @retval None
*/
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef dmaxferstatus = HAL_OK;
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
/* If last transfer, enable STOP interrupt */
if (hi2c->XferCount == 0U)
{
/* Enable STOP interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
}
/* else prepare a new DMA transfer and enable TCReload interrupt */
else
{
/* Update Buffer pointer */
hi2c->pBuffPtr += hi2c->XferSize;
/* Set the XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
}
/* Enable the DMA channel */
if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hi2c->hdmarx->LinkedListQueue != NULL)
{
/* Set DMA data size */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
/* Set DMA source address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR;
/* Set DMA destination address */
hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
}
else
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
hi2c->XferSize);
}
if (dmaxferstatus != HAL_OK)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
}
else
{
/* Enable TC interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
}
}
}
/**
* @brief DMA I2C slave receive process complete callback.
* @param hdma DMA handle
* @retval None
*/
static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmpoptions = hi2c->XferOptions;
if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
(tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
}
else
{
/* No specific action, Master fully manage the generation of STOP condition */
/* Mean that this generation can arrive at any time, at the end or during DMA process */
/* So STOP condition should be manage through Interrupt treatment */
}
}
/**
* @brief DMA I2C communication error callback.
* @param hdma DMA handle
* @retval None
*/
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Disable Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
}
/**
* @brief DMA I2C communication abort callback
* (To be called at end of DMA Abort procedure).
* @param hdma DMA handle.
* @retval None
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Reset AbortCpltCallback */
if (hi2c->hdmatx != NULL)
{
hi2c->hdmatx->XferAbortCallback = NULL;
}
if (hi2c->hdmarx != NULL)
{
hi2c->hdmarx->XferAbortCallback = NULL;
}
I2C_TreatErrorCallback(hi2c);
}
/**
* @brief This function handles I2C Communication Timeout. It waits
* until a flag is no longer in the specified status.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Flag Specifies the I2C flag to check.
* @param Status The actual Flag status (SET or RESET).
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
}
return HAL_OK;
}
/**
* @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
}
return HAL_OK;
}
/**
* @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
{
/* Check if an error is detected */
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
/* Check if an RXNE is pending */
/* Store Last receive data if any */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
{
/* Return HAL_OK */
/* The Reading of data from RXDR will be done in caller function */
return HAL_OK;
}
else
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
}
else
{
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief This function handles errors detection during an I2C Communication.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t itflag = hi2c->Instance->ISR;
uint32_t error_code = 0;
uint32_t tickstart = Tickstart;
uint32_t tmp1;
HAL_I2C_ModeTypeDef tmp2;
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
{
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Wait until STOP Flag is set or timeout occurred */
/* AutoEnd should be initiate after AF */
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
tmp2 = hi2c->Mode;
/* In case of I2C still busy, try to regenerate a STOP manually */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
(tmp1 != I2C_CR2_STOP) && \
(tmp2 != HAL_I2C_MODE_SLAVE))
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
/* Update Tick with new reference */
tickstart = HAL_GetTick();
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
status = HAL_ERROR;
}
}
}
}
}
/* In case STOP Flag is detected, clear it */
if (status == HAL_OK)
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
error_code |= HAL_I2C_ERROR_AF;
status = HAL_ERROR;
}
/* Refresh Content of Status register */
itflag = hi2c->Instance->ISR;
/* Then verify if an additional errors occurs */
/* Check if a Bus error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
{
error_code |= HAL_I2C_ERROR_BERR;
/* Clear BERR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
status = HAL_ERROR;
}
/* Check if an Over-Run/Under-Run error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
{
error_code |= HAL_I2C_ERROR_OVR;
/* Clear OVR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
status = HAL_ERROR;
}
/* Check if an Arbitration Loss error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
{
error_code |= HAL_I2C_ERROR_ARLO;
/* Clear ARLO flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
status = HAL_ERROR;
}
if (status != HAL_OK)
{
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->ErrorCode |= error_code;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
}
return status;
}
/**
* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
* @param hi2c I2C handle.
* @param DevAddress Specifies the slave address to be programmed.
* @param Size Specifies the number of bytes to be programmed.
* This parameter must be a value between 0 and 255.
* @param Mode New state of the I2C START condition generation.
* This parameter can be one of the following values:
* @arg @ref I2C_RELOAD_MODE Enable Reload mode .
* @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
* @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
* @param Request New state of the I2C START condition generation.
* This parameter can be one of the following values:
* @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
* @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
* @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, \
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
/**
* @brief Manage the enabling of Interrupts.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
* @retval None
*/
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
(hi2c->XferISR == I2C_Slave_ISR_DMA))
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
/* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
}
if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
}
}
else
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
/* Enable ERR, STOP, NACK, and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
}
/* Enable interrupts only at the end */
/* to avoid the risk of I2C interrupt handle execution before */
/* all interrupts requested done */
__HAL_I2C_ENABLE_IT(hi2c, tmpisr);
}
/**
* @brief Manage the disabling of Interrupts.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
* @retval None
*/
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Disable TC and TXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
/* Disable TC and RXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
}
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
/* Disable ADDR, NACK and STOP interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
if (InterruptRequest == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
if (InterruptRequest == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
}
/* Disable interrupts only at the end */
/* to avoid a breaking situation like at "t" time */
/* all disable interrupts request are not done */
__HAL_I2C_DISABLE_IT(hi2c, tmpisr);
}
/**
* @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
{
/* if user set XferOptions to I2C_OTHER_FRAME */
/* it request implicitly to generate a restart condition */
/* set XferOptions to I2C_FIRST_FRAME */
if (hi2c->XferOptions == I2C_OTHER_FRAME)
{
hi2c->XferOptions = I2C_FIRST_FRAME;
}
/* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
/* it request implicitly to generate a restart condition */
/* then generate a stop condition at the end of transfer */
/* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
{
hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
}
else
{
/* Nothing to do */
}
}
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c
|
C
|
apache-2.0
| 238,492
|
/**
******************************************************************************
* @file stm32u5xx_hal_i2c_ex.c
* @author MCD Application Team
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Filter Mode Functions
* + WakeUp Mode Functions
* + FastModePlus Functions
* + Autonomous Mode Functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32U5xx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
(+) Configure Autonomous mode
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
(++) HAL_I2CEx_EnableWakeUp()
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_ConfigFastModePlus()
(#) Set or get or clear the autonomous mode configuration using these functions :
(++) HAL_I2CEx_SetConfigAutonomousMode()
(++) HAL_I2CEx_GetConfigAutonomousMode()
(++) HAL_I2CEx_ClearConfigAutonomousMode()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @brief Filter Mode Functions
*
@verbatim
===============================================================================
##### Filter Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
@endverbatim
* @{
*/
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @brief WakeUp Mode Functions
*
@verbatim
===============================================================================
##### WakeUp Mode Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Wake Up Feature
@endverbatim
* @{
*/
/**
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @brief Fast Mode Plus Functions
*
@verbatim
===============================================================================
##### Fast Mode Plus Functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Configure I2C Fast Mode Plus.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param FastModePlus New state of the Fast Mode Plus.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_FASTMODEPLUS(FastModePlus));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
if (FastModePlus == I2C_FASTMODEPLUS_ENABLE)
{
/* Set I2Cx FMP bit */
hi2c->Instance->CR1 |= (I2C_CR1_FMP);
}
else
{
/* Reset I2Cx FMP bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_FMP);
}
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/** @defgroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions
* @brief Autonomous Mode Functions
*
@verbatim
===============================================================================
##### Autonomous Mode functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Autonomous Mode
@endverbatim
* @{
*/
/**
* @brief Set Autonomous Mode configuration
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains
* the configuration information of the autonomous mode for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig)
{
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Check the parameters */
assert_param(IS_I2C_TRIG_SOURCE(hi2c->Instance, sConfig->TriggerSelection));
assert_param(IS_I2C_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity));
/* Disable the selected I2C peripheral to be able to configure AUTOCR */
__HAL_I2C_DISABLE(hi2c);
/* I2Cx AUTOCR Configuration */
WRITE_REG(hi2c->Instance->AUTOCR,
(sConfig->TriggerState | \
((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) | \
sConfig->TriggerPolarity));
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief Get Autonomous Mode configuration
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains
* the configuration information of the autonomous mode for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, I2C_AutonomousModeConfTypeDef *sConfig)
{
uint32_t autocr_tmp;
autocr_tmp = hi2c->Instance->AUTOCR;
sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN);
if (IS_I2C_GRP2_INSTANCE(hi2c->Instance))
{
sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP2);
}
else
{
sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP1);
}
sConfig->TriggerPolarity = (autocr_tmp & I2C_AUTOCR_TRIGPOL);
return HAL_OK;
}
/**
* @brief Clear Autonomous Mode configuration
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c)
{
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral to be able to clear AUTOCR */
__HAL_I2C_DISABLE(hi2c);
CLEAR_REG(hi2c->Instance->AUTOCR);
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c
|
C
|
apache-2.0
| 13,864
|
/**
******************************************************************************
* @file stm32u5xx_hal_icache.c
* @author MCD Application Team
* @brief ICACHE HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Instruction Cache (ICACHE).
* + Initialization and Configuration
* + Invalidate functions
* + Monitoring management
* + Memory address remap management
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### ICACHE main features #####
==============================================================================
[..]
The Instruction Cache (ICACHE) is introduced on C-AHB code bus of
Cortex-M33 processor to improve performance when fetching instruction
and data from both internal and external memories. It allows close to
zero wait states performance.
(+) The ICACHE provides two performance counters (Hit and Miss),
cache invalidate maintenance operation, error management and TrustZone
security support.
(+) The ICACHE provides additionally the possibility to remap input address
falling into up to four memory regions (used to remap aliased code in
external memories to the internal Code region, for execution)
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The ICACHE HAL driver can be used as follows:
(#) Optionally configure the Instruction Cache mode with
@ref HAL_ICACHE_ConfigAssociativityMode() if the default configuration
does not suit the application requirements.
(#) Enable and disable the Instruction Cache with respectively
@ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable().
Use @ref HAL_ICACHE_IsEnabled() to get the Instruction Cache status.
(#) Initiate the cache maintenance invalidation procedure with either
@ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT()
(interrupt mode). When interrupt mode is used, the callback function
@ref HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate
procedure is complete. The function @ref HAL_ICACHE_WaitForInvalidateComplete()
may be called to wait for the end of the invalidate procedure automatically
initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable().
The cache operation is bypassed during the invalidation procedure.
(#) Use the performance monitoring counters for Hit and Miss with the following
functions: @ref HAL_ICACHE_Monitor_Start(), @ref HAL_ICACHE_Monitor_Stop(),
@ref HAL_ICACHE_Monitor_Reset(), @ref HAL_ICACHE_Monitor_GetHitValue() and
@ref HAL_ICACHE_Monitor_GetMissValue()
(#) Enable and disable up to four regions to remap input address from external
memories to the internal Code region for execution with
@ref HAL_ICACHE_EnableRemapRegion() and @ref HAL_ICACHE_DisableRemapRegion()
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup ICACHE ICACHE
* @brief HAL ICACHE module driver
* @{
*/
#ifdef HAL_ICACHE_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants
* @{
*/
#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */
#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup ICACHE_Private_Macros ICACHE Private Macros
* @{
*/
#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \
((__MODE__) == ICACHE_2WAYS))
#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \
((__TYPE__) == ICACHE_MONITOR_HIT) || \
((__TYPE__) == ICACHE_MONITOR_MISS))
#define IS_ICACHE_REGION_NUMBER(__NUMBER__) ((__NUMBER__) < 4U)
#define IS_ICACHE_REGION_SIZE(__SIZE__) (((__SIZE__) == ICACHE_REGIONSIZE_2MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_4MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_8MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_16MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_32MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_64MB) || \
((__SIZE__) == ICACHE_REGIONSIZE_128MB))
#define IS_ICACHE_REGION_TRAFFIC_ROUTE(__TRAFFICROUTE__) (((__TRAFFICROUTE__) == ICACHE_MASTER1_PORT) || \
((__TRAFFICROUTE__) == ICACHE_MASTER2_PORT))
#define IS_ICACHE_REGION_OUTPUT_BURST_TYPE(__OUTPUTBURSTTYPE_) (((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_WRAP) || \
((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_INCR))
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions
* @{
*/
/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions
* @brief Initialization and control functions
*
@verbatim
==============================================================================
##### Initialization and control functions #####
==============================================================================
[..]
This section provides functions allowing to initialize and control the
Instruction Cache (mode, invalidate procedure, performance counters).
@endverbatim
* @{
*/
/**
* @brief Configure the Instruction Cache cache associativity mode selection.
* @param AssociativityMode Associativity mode selection
* This parameter can be one of the following values:
* @arg ICACHE_1WAY 1-way cache (direct mapped cache)
* @arg ICACHE_2WAYS 2-ways set associative cache (default)
* @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode));
/* Check cache is not enabled */
if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
status = HAL_ERROR;
}
else
{
MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode);
}
return status;
}
/**
* @brief DeInitialize the Instruction Cache.
* @retval HAL status (HAL_OK/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_DeInit(void)
{
HAL_StatusTypeDef status;
/* Disable cache with reset value for 2-ways set associative mode */
WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);
/* Stop monitor and reset monitor values */
(void)HAL_ICACHE_Monitor_Stop(ICACHE_MONITOR_HIT_MISS);
(void)HAL_ICACHE_Monitor_Reset(ICACHE_MONITOR_HIT_MISS);
/* No remapped regions */
(void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_0);
(void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_1);
(void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_2);
(void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_3);
/* Wait for end of invalidate cache procedure */
status = HAL_ICACHE_WaitForInvalidateComplete();
/* Clear any pending flags */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);
return status;
}
/**
* @brief Enable the Instruction Cache.
* @note This function always returns HAL_OK even if there is any ongoing
* cache operation. The Instruction Cache is bypassed until the
* cache operation completes.
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Enable(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_EN);
return HAL_OK;
}
/**
* @brief Disable the Instruction Cache.
* @note This function waits for the cache being disabled but
* not for the end of the automatic cache invalidation procedure.
* @retval HAL status (HAL_OK/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_Disable(void)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Make sure BSYENDF is reset before to disable the instruction cache */
/* as it automatically starts a cache invalidation procedure */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for instruction cache being disabled */
while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE)
{
/* New check to avoid false timeout detection in case of preemption */
if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
status = HAL_TIMEOUT;
break;
}
}
}
return status;
}
/**
* @brief Check whether the Instruction Cache is enabled or not.
* @retval Status (0: disabled, 1: enabled)
*/
uint32_t HAL_ICACHE_IsEnabled(void)
{
return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL);
}
/**
* @brief Invalidate the Instruction Cache.
* @note This function waits for the end of cache invalidation procedure
* and clears the associated BSYENDF flag.
* @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_Invalidate(void)
{
HAL_StatusTypeDef status;
/* Check no ongoing operation */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Make sure BSYENDF is reset before to start cache invalidation */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Launch cache invalidation */
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
status = HAL_ICACHE_WaitForInvalidateComplete();
}
return status;
}
/**
* @brief Invalidate the Instruction Cache with interrupt.
* @note This function launches cache invalidation and returns.
* User application shall resort to interrupt generation to check
* the end of the cache invalidation with the BSYENDF flag and the
* HAL_ICACHE_InvalidateCompleteCallback() callback.
* @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check no ongoing operation */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Make sure BSYENDF is reset before to start cache invalidation */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Enable end of cache invalidation interrupt */
SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
/* Launch cache invalidation */
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
}
return status;
}
/**
* @brief Wait for the end of the Instruction Cache invalidate procedure.
* @note This function checks and clears the BSYENDF flag when set.
* @retval HAL status (HAL_OK/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Check if ongoing invalidation operation */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for end of cache invalidation */
while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
{
if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE)
{
/* New check to avoid false timeout detection in case of preemption */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
{
status = HAL_TIMEOUT;
break;
}
}
}
}
/* Clear BSYENDF */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
return status;
}
/**
* @brief Start the Instruction Cache performance monitoring.
* @param MonitorType Monitoring type
* This parameter can be one of the following values:
* @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
* @arg ICACHE_MONITOR_HIT Hit monitoring
* @arg ICACHE_MONITOR_MISS Miss monitoring
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType)
{
/* Check the parameters */
assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
SET_BIT(ICACHE->CR, MonitorType);
return HAL_OK;
}
/**
* @brief Stop the Instruction Cache performance monitoring.
* @note Stopping the monitoring does not reset the values.
* @param MonitorType Monitoring type
* This parameter can be one of the following values:
* @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
* @arg ICACHE_MONITOR_HIT Hit monitoring
* @arg ICACHE_MONITOR_MISS Miss monitoring
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType)
{
/* Check the parameters */
assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
CLEAR_BIT(ICACHE->CR, MonitorType);
return HAL_OK;
}
/**
* @brief Reset the Instruction Cache performance monitoring values.
* @param MonitorType Monitoring type
* This parameter can be one of the following values:
* @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
* @arg ICACHE_MONITOR_HIT Hit monitoring
* @arg ICACHE_MONITOR_MISS Miss monitoring
* @retval HAL status (HAL_OK)
*/
HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType)
{
/* Check the parameters */
assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
/* Force/Release reset */
SET_BIT(ICACHE->CR, (MonitorType << 2U));
CLEAR_BIT(ICACHE->CR, (MonitorType << 2U));
return HAL_OK;
}
/**
* @brief Get the Instruction Cache performance Hit monitoring value.
* @note Upon reaching the 32-bit maximum value, monitor does not wrap.
* @retval Hit monitoring value
*/
uint32_t HAL_ICACHE_Monitor_GetHitValue(void)
{
return (ICACHE->HMONR);
}
/**
* @brief Get the Instruction Cache performance Miss monitoring value.
* @note Upon reaching the 32-bit maximum value, monitor does not wrap.
* @retval Miss monitoring value
*/
uint32_t HAL_ICACHE_Monitor_GetMissValue(void)
{
return (ICACHE->MMONR);
}
/**
* @}
*/
/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions
* @brief IRQ and callback functions
*
@verbatim
==============================================================================
##### IRQ and callback functions #####
==============================================================================
[..]
This section provides functions allowing to handle ICACHE global interrupt
and the associated callback functions.
@endverbatim
* @{
*/
/**
* @brief Handle the Instruction Cache interrupt request.
* @note This function should be called under the ICACHE_IRQHandler().
* @note This function respectively disables the interrupt and clears the
* flag of any pending flag before calling the associated user callback.
* @retval None
*/
void HAL_ICACHE_IRQHandler(void)
{
/* Get current interrupt flags and interrupt sources value */
uint32_t itflags = READ_REG(ICACHE->SR);
uint32_t itsources = READ_REG(ICACHE->IER);
/* Check Instruction cache Error interrupt flag */
if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U)
{
/* Disable error interrupt */
CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
/* Clear ERR pending flag */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
/* Instruction cache error interrupt user callback */
HAL_ICACHE_ErrorCallback();
}
/* Check Instruction cache BusyEnd interrupt flag */
if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U)
{
/* Disable end of cache invalidation interrupt */
CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
/* Clear BSYENDF pending flag */
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Instruction cache busyend interrupt user callback */
HAL_ICACHE_InvalidateCompleteCallback();
}
}
/**
* @brief Cache invalidation complete callback.
*/
__weak void HAL_ICACHE_InvalidateCompleteCallback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file
*/
}
/**
* @brief Error callback.
*/
__weak void HAL_ICACHE_ErrorCallback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_ICACHE_ErrorCallback() should be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions
* @brief Memory remapped regions functions
*
@verbatim
==============================================================================
##### Memory remapped regions functions #####
==============================================================================
[..]
This section provides functions allowing to manage the remapping of
external memories to internal Code for execution.
@endverbatim
* @{
*/
/**
* @brief Configure and enable a region for memory remapping.
* @note The Instruction Cache and the region must be disabled.
* @param Region Region number
This parameter can be a value of @arg @ref ICACHE_Region
* @param pRegionConfig Pointer to structure of ICACHE region configuration parameters
* @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t *p_reg;
uint32_t value;
/* Check the parameters */
assert_param(IS_ICACHE_REGION_NUMBER(Region));
assert_param(IS_ICACHE_REGION_SIZE(pRegionConfig->Size));
assert_param(IS_ICACHE_REGION_TRAFFIC_ROUTE(pRegionConfig->TrafficRoute));
assert_param(IS_ICACHE_REGION_OUTPUT_BURST_TYPE(pRegionConfig->OutputBurstType));
/* Check cache is not enabled */
if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Get region control register address */
p_reg = &(ICACHE->CRR0) + (1U * Region);
/* Check region is not already enabled */
if ((*p_reg & ICACHE_CRRx_REN) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */
/* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */
/* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */
/* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */
/* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */
/* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */
/* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */
value = ((pRegionConfig->BaseAddress & 0x1FFFFFFFU) >> 21U) & \
(0xFFU & ~(pRegionConfig->Size - 1U));
value |= ((pRegionConfig->RemapAddress >> 5U) & \
((uint32_t)(0x7FFU & ~(pRegionConfig->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos));
value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \
pRegionConfig->OutputBurstType;
*p_reg = (value | ICACHE_CRRx_REN);
}
}
return status;
}
/**
* @brief Disable the memory remapping for a predefined region.
* @param Region Region number
This parameter can be a value of @arg @ref ICACHE_Region
* @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t *p_reg;
/* Check the parameters */
assert_param(IS_ICACHE_REGION_NUMBER(Region));
/* Check cache is not enabled */
if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Get region control register address */
p_reg = &(ICACHE->CRR0) + (1U * Region);
*p_reg &= ~ICACHE_CRRx_REN;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_ICACHE_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c
|
C
|
apache-2.0
| 21,560
|
/**
******************************************************************************
* @file stm32u5xx_hal_irda.c
* @author MCD Application Team
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA (Infrared Data Association) Peripheral
* (IRDA)
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The IRDA HAL driver can be used as follows:
(#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda).
(#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API
in setting the associated USART or UART in IRDA mode:
(++) Enable the USARTx/UARTx interface clock.
(++) USARTx/UARTx pins configuration:
(+++) Enable the clock for the USARTx/UARTx GPIOs.
(+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
(++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
and HAL_IRDA_Receive_IT() APIs):
(+++) Configure the USARTx/UARTx interrupt priority.
(+++) Enable the NVIC USARTx/UARTx IRQ handle.
(+++) The specific IRDA interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
(++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
and HAL_IRDA_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx channel.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer
complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
the normal or low power mode and the clock prescaler in the hirda handle Init structure.
(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customized HAL_IRDA_MspInit() API.
-@@- The specific IRDA interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
(#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
(+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
(+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
*** Interrupt mode IO operation ***
===================================
[..]
(+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT()
(+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
(+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT()
(+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
(+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
(+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
(+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback()
(+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_IRDA_TxCpltCallback()
(+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA()
(+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback()
(+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_IRDA_RxCpltCallback()
(+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_IRDA_ErrorCallback()
*** IRDA HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IRDA HAL driver.
(+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
(+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
(+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
(+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
(+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
(+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
(+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled
[..]
(@) You can refer to the IRDA HAL driver header file for more useful macros
##### Callback registration #####
==================================
[..]
The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use Function HAL_IRDA_RegisterCallback() to register a user callback.
Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) ErrorCallback : Error Callback.
(+) AbortCpltCallback : Abort Complete Callback.
(+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
(+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
(+) MspInitCallback : IRDA MspInit.
(+) MspDeInitCallback : IRDA MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxHalfCpltCallback : Tx Half Complete Callback.
(+) TxCpltCallback : Tx Complete Callback.
(+) RxHalfCpltCallback : Rx Half Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) ErrorCallback : Error Callback.
(+) AbortCpltCallback : Abort Complete Callback.
(+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
(+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
(+) MspInitCallback : IRDA MspInit.
(+) MspDeInitCallback : IRDA MspDeInit.
[..]
By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
or HAL_IRDA_Init() function.
[..]
When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup IRDA IRDA
* @brief HAL IRDA module driver
* @{
*/
#ifdef HAL_IRDA_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IRDA_Private_Constants IRDA Private Constants
* @{
*/
#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */
#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
| USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IRDA_Private_Macros IRDA Private Macros
* @{
*/
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
* @param __PCLK__ IRDA clock source.
* @param __BAUD__ Baud rate set by the user.
* @param __PRESCALER__ IRDA clock prescaler value.
* @retval Division result
*/
#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\
+ ((__BAUD__)/2U)) / (__BAUD__))
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup IRDA_Private_Functions
* @{
*/
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
* @{
*/
/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USARTx
in asynchronous IRDA mode.
(+) For the asynchronous mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
(++) Power mode
(++) Prescaler setting
(++) Receiver/transmitter modes
[..]
The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures
(details for the procedures are available in reference manual).
@endverbatim
Depending on the frame length defined by the M1 and M0 bits (7-bit,
8-bit or 9-bit), the possible IRDA frame formats are listed in the
following table.
Table 1. IRDA frame format.
+-----------------------------------------------------------------------+
| M1 bit | M0 bit | PCE bit | IRDA frame |
|---------|---------|-----------|---------------------------------------|
| 0 | 0 | 0 | | SB | 8 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 1 | 0 | | SB | 9 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
|---------|---------|-----------|---------------------------------------|
| 1 | 0 | 0 | | SB | 7 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
| 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+-----------------------------------------------------------------------+
* @{
*/
/**
* @brief Initialize the IRDA mode according to the specified
* parameters in the IRDA_InitTypeDef and initialize the associated handle.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
if (hirda == NULL)
{
return HAL_ERROR;
}
/* Check the USART/UART associated to the IRDA handle */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
if (hirda->gState == HAL_IRDA_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hirda->Lock = HAL_UNLOCKED;
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
IRDA_InitCallbacksToDefault(hirda);
if (hirda->MspInitCallback == NULL)
{
hirda->MspInitCallback = HAL_IRDA_MspInit;
}
/* Init the low level hardware */
hirda->MspInitCallback(hirda);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_IRDA_MspInit(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
hirda->gState = HAL_IRDA_STATE_BUSY;
/* Disable the Peripheral to update the configuration registers */
__HAL_IRDA_DISABLE(hirda);
/* Set the IRDA Communication parameters */
if (IRDA_SetConfig(hirda) == HAL_ERROR)
{
return HAL_ERROR;
}
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- SCEN and HDSEL bits in the USART_CR3 register.*/
CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
hirda->Instance->CR3 |= USART_CR3_IREN;
/* Enable the Peripheral */
__HAL_IRDA_ENABLE(hirda);
/* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */
return (IRDA_CheckIdleState(hirda));
}
/**
* @brief DeInitialize the IRDA peripheral.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
if (hirda == NULL)
{
return HAL_ERROR;
}
/* Check the USART/UART associated to the IRDA handle */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
hirda->gState = HAL_IRDA_STATE_BUSY;
/* DeInit the low level hardware */
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
if (hirda->MspDeInitCallback == NULL)
{
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
}
/* DeInit the low level hardware */
hirda->MspDeInitCallback(hirda);
#else
HAL_IRDA_MspDeInit(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/* Disable the Peripheral */
__HAL_IRDA_DISABLE(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_RESET;
hirda->RxState = HAL_IRDA_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
/**
* @brief Initialize the IRDA MSP.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IRDA_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the IRDA MSP.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IRDA_MspDeInit can be implemented in the user file
*/
}
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User IRDA Callback
* To be used instead of the weak predefined callback
* @param hirda irda handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
* @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
* @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
* @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
* @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
* @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
* @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
* @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
* @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
pIRDA_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hirda);
if (hirda->gState == HAL_IRDA_STATE_READY)
{
switch (CallbackID)
{
case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
hirda->TxHalfCpltCallback = pCallback;
break;
case HAL_IRDA_TX_COMPLETE_CB_ID :
hirda->TxCpltCallback = pCallback;
break;
case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
hirda->RxHalfCpltCallback = pCallback;
break;
case HAL_IRDA_RX_COMPLETE_CB_ID :
hirda->RxCpltCallback = pCallback;
break;
case HAL_IRDA_ERROR_CB_ID :
hirda->ErrorCallback = pCallback;
break;
case HAL_IRDA_ABORT_COMPLETE_CB_ID :
hirda->AbortCpltCallback = pCallback;
break;
case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
hirda->AbortTransmitCpltCallback = pCallback;
break;
case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
hirda->AbortReceiveCpltCallback = pCallback;
break;
case HAL_IRDA_MSPINIT_CB_ID :
hirda->MspInitCallback = pCallback;
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
hirda->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hirda->gState == HAL_IRDA_STATE_RESET)
{
switch (CallbackID)
{
case HAL_IRDA_MSPINIT_CB_ID :
hirda->MspInitCallback = pCallback;
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
hirda->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hirda);
return status;
}
/**
* @brief Unregister an IRDA callback
* IRDA callback is redirected to the weak predefined callback
* @param hirda irda handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
* @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
* @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
* @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
* @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
* @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
* @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
* @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
* @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hirda);
if (HAL_IRDA_STATE_READY == hirda->gState)
{
switch (CallbackID)
{
case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_IRDA_TX_COMPLETE_CB_ID :
hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_IRDA_RX_COMPLETE_CB_ID :
hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_IRDA_ERROR_CB_ID :
hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_IRDA_ABORT_COMPLETE_CB_ID :
hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak
AbortTransmitCpltCallback */
break;
case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak
AbortReceiveCpltCallback */
break;
case HAL_IRDA_MSPINIT_CB_ID :
hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_IRDA_STATE_RESET == hirda->gState)
{
switch (CallbackID)
{
case HAL_IRDA_MSPINIT_CB_ID :
hirda->MspInitCallback = HAL_IRDA_MspInit;
break;
case HAL_IRDA_MSPDEINIT_CB_ID :
hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
break;
default :
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hirda);
return status;
}
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
* @brief IRDA Transmit and Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the IRDA data transfers.
[..]
IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
[..]
(#) There are two modes of transfer:
(++) Blocking mode: the communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) Non-Blocking mode: the communication is performed using Interrupts
or DMA, these API's return the HAL status.
The end of the data processing will be indicated through the
dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
will be executed respectively at the end of the Transmit or Receive process
The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected
(#) Blocking mode APIs are :
(++) HAL_IRDA_Transmit()
(++) HAL_IRDA_Receive()
(#) Non Blocking mode APIs with Interrupt are :
(++) HAL_IRDA_Transmit_IT()
(++) HAL_IRDA_Receive_IT()
(++) HAL_IRDA_IRQHandler()
(#) Non Blocking mode functions with DMA are :
(++) HAL_IRDA_Transmit_DMA()
(++) HAL_IRDA_Receive_DMA()
(++) HAL_IRDA_DMAPause()
(++) HAL_IRDA_DMAResume()
(++) HAL_IRDA_DMAStop()
(#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
(++) HAL_IRDA_TxHalfCpltCallback()
(++) HAL_IRDA_TxCpltCallback()
(++) HAL_IRDA_RxHalfCpltCallback()
(++) HAL_IRDA_RxCpltCallback()
(++) HAL_IRDA_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
(++) HAL_IRDA_Abort()
(++) HAL_IRDA_AbortTransmit()
(++) HAL_IRDA_AbortReceive()
(++) HAL_IRDA_Abort_IT()
(++) HAL_IRDA_AbortTransmit_IT()
(++) HAL_IRDA_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
(++) HAL_IRDA_AbortCpltCallback()
(++) HAL_IRDA_AbortTransmitCpltCallback()
(++) HAL_IRDA_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
Transfer is kept ongoing on IRDA side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
Error code is set to allow user to identify error type, and
HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
*/
/**
* @brief Send an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
pdata8bits = NULL;
pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */
}
else
{
pdata8bits = pData;
pdata16bits = NULL;
}
while (hirda->TxXferCount > 0U)
{
hirda->TxXferCount--;
if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
{
hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
pdata16bits++;
}
else
{
hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
pdata8bits++;
}
}
if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* At end of Tx process, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint16_t uhMask;
uint32_t tickstart;
/* Check that a Rx process is not already ongoing */
if (hirda->RxState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
/* Computation of the mask to apply to RDR register
of the UART associated to the IRDA */
IRDA_MASK_COMPUTATION(hirda);
uhMask = hirda->Mask;
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
pdata8bits = NULL;
pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
}
else
{
pdata8bits = pData;
pdata16bits = NULL;
}
/* Check data remaining to be received */
while (hirda->RxXferCount > 0U)
{
hirda->RxXferCount--;
if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
{
*pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
pdata16bits++;
}
else
{
*pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
pdata8bits++;
}
}
/* At end of Rx process, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->pTxBuffPtr = pData;
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the IRDA Transmit Data Register Empty Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
if (hirda->RxState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->pRxBuffPtr = pData;
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
/* Computation of the mask to apply to the RDR register
of the UART associated to the IRDA */
IRDA_MASK_COMPUTATION(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
if (hirda->Init.Parity != IRDA_PARITY_NONE)
{
/* Enable the IRDA Parity Error and Data Register not empty Interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
}
else
{
/* Enable the IRDA Data Register not empty Interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef status;
uint16_t nbByte = Size;
/* Check that a Tx process is not already ongoing */
if (hirda->gState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->pTxBuffPtr = pData;
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Set the IRDA DMA transfer complete callback */
hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
/* Set the IRDA DMA half transfer complete callback */
hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
/* Set the DMA error callback */
hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
/* Set the DMA abort callback */
hirda->hdmatx->XferAbortCallback = NULL;
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
nbByte = Size * 2U;
}
/* Check linked list mode */
if ((hirda->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hirda->hdmatx->LinkedListQueue != NULL) && (hirda->hdmatx->LinkedListQueue->Head != NULL))
{
/* Set DMA data size */
hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
/* Set DMA source address */
hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)hirda->pTxBuffPtr;
/* Set DMA destination address */
hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hirda->Instance->TDR;
/* Enable the IRDA transmit DMA channel */
status = HAL_DMAEx_List_Start_IT(hirda->hdmatx);
}
else
{
/* Update status */
status = HAL_ERROR;
}
}
else
{
/* Enable the IRDA transmit DMA channel */
status = HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, nbByte);
}
if (status == HAL_OK)
{
/* Clear the TC flag in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
}
else
{
/* Set error code to DMA */
hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Restore hirda->gState to ready */
hirda->gState = HAL_IRDA_STATE_READY;
return HAL_ERROR;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @note When the IRDA parity is enabled (PCE = 1), the received data contains
* the parity bit (MSB position).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef status;
uint16_t nbByte = Size;
/* Check that a Rx process is not already ongoing */
if (hirda->RxState == HAL_IRDA_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hirda);
hirda->pRxBuffPtr = pData;
hirda->RxXferSize = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Set the IRDA DMA transfer complete callback */
hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
/* Set the IRDA DMA half transfer complete callback */
hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
/* Set the DMA error callback */
hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
/* Set the DMA abort callback */
hirda->hdmarx->XferAbortCallback = NULL;
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
nbByte = Size * 2U;
}
/* Check linked list mode */
if ((hirda->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hirda->hdmarx->LinkedListQueue != NULL) && (hirda->hdmarx->LinkedListQueue->Head != NULL))
{
/* Set DMA data size */
hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte;
/* Set DMA source address */
hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)&hirda->Instance->RDR;
/* Set DMA destination address */
hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hirda->pRxBuffPtr;
/* Enable the DMA channel */
status = HAL_DMAEx_List_Start_IT(hirda->hdmarx);
}
else
{
/* Update status */
status = HAL_ERROR;
}
}
else
{
/* Enable the DMA channel */
status = HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, nbByte);
}
if (status == HAL_OK)
{
/* Process Unlocked */
__HAL_UNLOCK(hirda);
if (hirda->Init.Parity != IRDA_PARITY_NONE)
{
/* Enable the UART Parity Error Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
}
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
}
else
{
/* Set error code to DMA */
hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
/* Restore hirda->RxState to ready */
hirda->RxState = HAL_IRDA_STATE_READY;
return HAL_ERROR;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Pause the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
{
/* Process Locked */
__HAL_LOCK(hirda);
if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
/* Disable the IRDA DMA Tx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
}
if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Rx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
}
}
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
/**
* @brief Resume the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
{
/* Process Locked */
__HAL_LOCK(hirda);
if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
/* Enable the IRDA DMA Tx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
if (hirda->Init.Parity != IRDA_PARITY_NONE)
{
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
}
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the IRDA DMA Rx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
}
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
/**
* @brief Stop the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
{
/* The Lock is not implemented on this API to allow the user application
to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
the stream and the corresponding call back is executed. */
/* Stop IRDA DMA Tx request if ongoing */
if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel */
if (hirda->hdmatx != NULL)
{
if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
{
if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
{
/* Set error code to DMA */
hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
return HAL_TIMEOUT;
}
}
}
IRDA_EndTxTransfer(hirda);
}
}
/* Stop IRDA DMA Rx request if ongoing */
if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel */
if (hirda->hdmarx != NULL)
{
if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
{
if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
{
/* Set error code to DMA */
hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
return HAL_TIMEOUT;
}
}
}
IRDA_EndRxTransfer(hirda);
}
}
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (blocking mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = NULL;
if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
{
if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
{
/* Set error code to DMA */
hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
return HAL_TIMEOUT;
}
}
}
}
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = NULL;
if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
{
if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
{
/* Set error code to DMA */
hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
return HAL_TIMEOUT;
}
}
}
}
/* Reset Tx and Rx transfer counters */
hirda->TxXferCount = 0U;
hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
/* Restore hirda->gState and hirda->RxState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* Reset Handle ErrorCode to No Error */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (blocking mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = NULL;
if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
{
if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
{
/* Set error code to DMA */
hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
return HAL_TIMEOUT;
}
}
}
}
/* Reset Tx transfer counter */
hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (blocking mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = NULL;
if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
{
if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
{
/* Set error code to DMA */
hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
return HAL_TIMEOUT;
}
}
}
}
/* Reset Rx transfer counter */
hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
return HAL_OK;
}
/**
* @brief Abort ongoing transfers (Interrupt mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
{
uint32_t abortcplt = 1U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
if (hirda->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
Otherwise, set it to NULL */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
}
else
{
hirda->hdmatx->XferAbortCallback = NULL;
}
}
/* DMA Rx Handle is valid */
if (hirda->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
Otherwise, set it to NULL */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
}
else
{
hirda->hdmarx->XferAbortCallback = NULL;
}
}
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
if (hirda->hdmatx != NULL)
{
/* IRDA Tx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
hirda->hdmatx->XferAbortCallback = NULL;
}
else
{
abortcplt = 0U;
}
}
}
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
if (hirda->hdmarx != NULL)
{
/* IRDA Rx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
hirda->hdmarx->XferAbortCallback = NULL;
abortcplt = 1U;
}
else
{
abortcplt = 0U;
}
}
}
/* if no DMA abort complete callback execution is required => call user Abort Complete callback */
if (abortcplt == 1U)
{
/* Reset Tx and Rx transfer counters */
hirda->TxXferCount = 0U;
hirda->RxXferCount = 0U;
/* Reset errorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
/* Restore hirda->gState and hirda->RxState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort complete callback */
hirda->AbortCpltCallback(hirda);
#else
/* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
* @brief Abort ongoing Transmit transfer (Interrupt mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
/* Disable the IRDA DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
if (hirda->hdmatx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
/* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
}
}
else
{
/* Reset Tx transfer counter */
hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Transmit Complete Callback */
hirda->AbortTransmitCpltCallback(hirda);
#else
/* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Reset Tx transfer counter */
hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Transmit Complete Callback */
hirda->AbortTransmitCpltCallback(hirda);
#else
/* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
* @brief Abort ongoing Receive transfer (Interrupt mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
* - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
* - Set handle State to READY
* - At abort completion, call user abort complete callback
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
}
}
else
{
/* Reset Rx transfer counter */
hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
hirda->AbortReceiveCpltCallback(hirda);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Reset Rx transfer counter */
hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
hirda->AbortReceiveCpltCallback(hirda);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
* @brief Handle IRDA interrupt request.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
{
uint32_t isrflags = READ_REG(hirda->Instance->ISR);
uint32_t cr1its = READ_REG(hirda->Instance->CR1);
uint32_t cr3its;
uint32_t errorflags;
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
if (errorflags == 0U)
{
/* IRDA in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
{
IRDA_Receive_IT(hirda);
return;
}
}
/* If some errors occur */
cr3its = READ_REG(hirda->Instance->CR3);
if ((errorflags != 0U)
&& (((cr3its & USART_CR3_EIE) != 0U)
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))
{
/* IRDA parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
}
/* IRDA frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
}
/* IRDA noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
}
/* IRDA Over-Run interrupt occurred -----------------------------------------*/
if (((isrflags & USART_ISR_ORE) != 0U) &&
(((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
}
/* Call IRDA Error Call back function if need be --------------------------*/
if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
{
/* IRDA in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U))
{
IRDA_Receive_IT(hirda);
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
errorcode = hirda->ErrorCode;
if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
((errorcode & HAL_IRDA_ERROR_ORE) != 0U))
{
/* Blocking error : transfer is aborted
Set the IRDA state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
IRDA_EndRxTransfer(hirda);
/* Disable the IRDA DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel */
if (hirda->hdmarx != NULL)
{
/* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
}
}
else
{
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hirda->ErrorCallback(hirda);
#else
/* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hirda->ErrorCallback(hirda);
#else
/* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hirda->ErrorCallback(hirda);
#else
/* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
}
}
return;
} /* End if some error occurs */
/* IRDA in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U))
{
IRDA_Transmit_IT(hirda);
return;
}
/* IRDA in mode Transmitter (transmission end) -----------------------------*/
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
{
IRDA_EndTransmit_IT(hirda);
return;
}
}
/**
* @brief Tx Transfer completed callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_TxCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Tx Half Transfer completed callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Rx Transfer completed callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_RxCpltCallback can be implemented in the user file.
*/
}
/**
* @brief Rx Half Transfer complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file.
*/
}
/**
* @brief IRDA error callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_ErrorCallback can be implemented in the user file.
*/
}
/**
* @brief IRDA Abort Complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
*/
}
/**
* @brief IRDA Abort Complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
*/
}
/**
* @brief IRDA Abort Receive Complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
* @brief IRDA State and Errors functions
*
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to return the State of IrDA
communication process and also return Peripheral Errors occurred during communication process
(+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
of the IRDA peripheral handle.
(+) HAL_IRDA_GetError() checks in run-time errors that could occur during
communication.
@endverbatim
* @{
*/
/**
* @brief Return the IRDA handle state.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
uint32_t temp1;
uint32_t temp2;
temp1 = (uint32_t)hirda->gState;
temp2 = (uint32_t)hirda->RxState;
return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the IRDA handle error code.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval IRDA Error Code
*/
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
{
return hirda->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup IRDA_Private_Functions IRDA Private Functions
* @{
*/
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief Initialize the callbacks to their default values.
* @param hirda IRDA handle.
* @retval none
*/
void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
{
/* Init the IRDA Callback settings */
hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
}
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @brief Configure the IRDA peripheral.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
uint32_t tmpreg;
IRDA_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
uint32_t pclk;
/* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode));
assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler));
assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode));
assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler));
/*-------------------------- USART CR1 Configuration -----------------------*/
/* Configure the IRDA Word Length, Parity and transfer Mode:
Set the M bits according to hirda->Init.WordLength value
Set PCE and PS bits according to hirda->Init.Parity value
Set TE and RE bits according to hirda->Init.Mode value */
tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ;
MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
/*--------------------- USART clock PRESC Configuration ----------------*/
/* Configure
* - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */
MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
/*-------------------------- USART GTPR Configuration ----------------------*/
MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
/*-------------------------- USART BRR Configuration -----------------------*/
IRDA_GETCLOCKSOURCE(hirda, clocksource);
tmpreg = 0U;
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_HSI:
tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_LSE:
tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
default:
ret = HAL_ERROR;
break;
}
/* USARTDIV must be greater than or equal to 0d16 */
if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
{
hirda->Instance->BRR = (uint16_t)tmpreg;
}
else
{
ret = HAL_ERROR;
}
return ret;
}
/**
* @brief Check the IRDA Idle State.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
{
uint32_t tickstart;
/* Initialize the IRDA ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
/* Wait until TEACK flag is set */
if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
}
}
/* Check if the Receiver is enabled */
if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
{
/* Wait until REACK flag is set */
if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
{
/* Timeout occurred */
return HAL_TIMEOUT;
}
}
/* Initialize the IRDA state*/
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_OK;
}
/**
* @brief Handle IRDA Communication Timeout. It waits
* until a flag is no longer in the specified status.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param Flag Specifies the IRDA flag to check.
* @param Status The actual Flag status (SET or RESET)
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
/* At end of Tx process, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
}
/**
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* At end of Rx process, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
}
/**
* @brief DMA IRDA transmit process complete callback.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
{
hirda->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the IRDA CR3 register */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Enable the IRDA Transmit Complete Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
}
/* DMA Circular mode */
else
{
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Tx complete callback */
hirda->TxCpltCallback(hirda);
#else
/* Call legacy weak Tx complete callback */
HAL_IRDA_TxCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
/**
* @brief DMA IRDA transmit process half complete callback.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Tx Half complete callback */
hirda->TxHalfCpltCallback(hirda);
#else
/* Call legacy weak Tx complete callback */
HAL_IRDA_TxHalfCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA receive process complete callback.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
{
hirda->RxXferCount = 0U;
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the IRDA CR3 register */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
}
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Rx complete callback */
hirda->RxCpltCallback(hirda);
#else
/* Call legacy weak Rx complete callback */
HAL_IRDA_RxCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
/**
* @brief DMA IRDA receive process half complete callback.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/*Call registered Rx Half complete callback*/
hirda->RxHalfCpltCallback(hirda);
#else
/* Call legacy weak Rx Half complete callback */
HAL_IRDA_RxHalfCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA communication error callback.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
/* Stop IRDA DMA Tx request if ongoing */
if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
hirda->TxXferCount = 0U;
IRDA_EndTxTransfer(hirda);
}
}
/* Stop IRDA DMA Rx request if ongoing */
if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
hirda->RxXferCount = 0U;
IRDA_EndRxTransfer(hirda);
}
}
hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hirda->ErrorCallback(hirda);
#else
/* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
hirda->RxXferCount = 0U;
hirda->TxXferCount = 0U;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered user error callback */
hirda->ErrorCallback(hirda);
#else
/* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA Tx communication abort callback, when initiated by user
* (To be called at end of DMA Tx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Rx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
hirda->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if (hirda->hdmarx != NULL)
{
if (hirda->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hirda->TxXferCount = 0U;
hirda->RxXferCount = 0U;
/* Reset errorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
/* Restore hirda->gState and hirda->RxState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort complete callback */
hirda->AbortCpltCallback(hirda);
#else
/* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA Rx communication abort callback, when initiated by user
* (To be called at end of DMA Rx Abort procedure following user abort request).
* @note When this callback is executed, User Abort complete call back is called only if no
* Abort still ongoing for Tx DMA Handle.
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
hirda->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
if (hirda->hdmatx != NULL)
{
if (hirda->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hirda->TxXferCount = 0U;
hirda->RxXferCount = 0U;
/* Reset errorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
/* Restore hirda->gState and hirda->RxState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort complete callback */
hirda->AbortCpltCallback(hirda);
#else
/* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
* HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
* (This callback is executed at end of DMA Tx Abort procedure following user abort request,
* and leads to user Tx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Transmit Complete Callback */
hirda->AbortTransmitCpltCallback(hirda);
#else
/* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
* HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
* (This callback is executed at end of DMA Rx Abort procedure following user abort request,
* and leads to user Rx Abort Complete callback execution).
* @param hdma DMA handle.
* @retval None
*/
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
/* Restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Abort Receive Complete Callback */
hirda->AbortReceiveCpltCallback(hirda);
#else
/* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief Send an amount of data in interrupt mode.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_IRDA_Transmit_IT().
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
if (hirda->TxXferCount == 0U)
{
/* Disable the IRDA Transmit Data Register Empty Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
/* Enable the IRDA Transmit Complete Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
}
else
{
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
hirda->pTxBuffPtr += 2U;
}
else
{
hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
hirda->pTxBuffPtr++;
}
hirda->TxXferCount--;
}
}
}
/**
* @brief Wrap up transmission in non-blocking mode.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable the IRDA Transmit Complete Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
/* Tx process is ended, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Tx complete callback */
hirda->TxCpltCallback(hirda);
#else
/* Call legacy weak Tx complete callback */
HAL_IRDA_TxCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
* @brief Receive an amount of data in interrupt mode.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_IRDA_Receive_IT()
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
{
uint16_t *tmp;
uint16_t uhMask = hirda->Mask;
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
*tmp = (uint16_t)(uhdata & uhMask);
hirda->pRxBuffPtr += 2U;
}
else
{
*hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
hirda->pRxBuffPtr++;
}
hirda->RxXferCount--;
if (hirda->RxXferCount == 0U)
{
/* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
/* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Rx process is completed, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Call registered Rx complete callback */
hirda->RxCpltCallback(hirda);
#else
/* Call legacy weak Rx complete callback */
HAL_IRDA_RxCpltCallback(hirda);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
}
else
{
/* Clear RXNE interrupt flag */
__HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
}
}
/**
* @}
*/
#endif /* HAL_IRDA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_irda.c
|
C
|
apache-2.0
| 105,534
|
/**
******************************************************************************
* @file stm32u5xx_hal_iwdg.c
* @author MCD Application Team
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
* + Initialization and Start functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### IWDG Generic features #####
==============================================================================
[..]
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
active even if the main clock fails.
(+) Once the IWDG is started, the LSI is forced ON and both cannot be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded into the counter and the watchdog reset
is prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
(+) Debug mode: When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~131.04s
The IWDG timeout may vary due to LSI clock frequency dispersion.
STM32U5xx devices provide the capability to measure the LSI clock
frequency (LSI clock is internally connected to TIM16 CH1 input capture).
The measured value can be used to have an IWDG timeout with an
acceptable accuracy.
[..] Default timeout value (necessary for IWDG_SR status register update):
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
This frequency being subject to variations as mentioned above, the
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
below) may become too short or too long.
In such cases, this default timeout value can be tuned by redefining
the constant LSI_VALUE at user-application level (based, for instance,
on the measured LSI clock frequency as explained above).
##### How to use this driver #####
==============================================================================
[..]
(#) Register callback to treat Iwdg interrupt and MspInit using HAL_IWDG_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
HAL_IWDG_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts counting down.
(++) Enable write access to configuration registers:
IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR.
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function with exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
(++) Depending on Early Wakeup Interrupt parameter:
(+++) If EWI is set to disable, comparator is set to 0, interrupt is
disable & flag is clear.
(+++) Else modify EWCR register, setting comparator value, enable
interrupt & clear flag.
(++) Wait for status flags to be reset.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
*** IWDG HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IWDG HAL driver:
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
the reload register
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_IWDG_MODULE_ENABLED
/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register needs up to 5 LSI clock periods to be updated. However a
synchronisation is added on prescaled LSI clock rising edge, so we only
consider a highest prescaler cycle.
The timeout value is calculated using the highest prescaler (1024) and
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
The timeout value is multiplied by 1000 to be converted in milliseconds.
LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IWDG_Exported_Functions
* @{
*/
/** @addtogroup IWDG_Exported_Functions_Group1
* @brief Initialization and Start functions.
*
@verbatim
===============================================================================
##### Initialization and Start functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters in the
IWDG_InitTypeDef of associated handle.
(+) Manage Window option.
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
is reloaded in order to exit function with correct time base.
@endverbatim
* @{
*/
/**
* @brief Initialize the IWDG according to the specified parameters in the
* IWDG_InitTypeDef and start watchdog. Before exiting function,
* watchdog is refreshed in order to have correct time base.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart;
/* Check the IWDG handle allocation */
if (hiwdg == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
assert_param(IS_IWDG_EWI(hiwdg->Init.EWI));
#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers */
if (hiwdg->EwiCallback == NULL)
{
hiwdg->EwiCallback = HAL_IWDG_EarlyWakeupCallback;
}
if (hiwdg->MspInitCallback == NULL)
{
hiwdg->MspInitCallback = HAL_IWDG_MspInit;
}
/* Init the low level hardware */
hiwdg->MspInitCallback(hiwdg);
#else
/* Init the low level hardware */
HAL_IWDG_MspInit(hiwdg);
#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
/* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers by writing
0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the Prescaler & Reload values to work with */
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
hiwdg->Instance->RLR = hiwdg->Init.Reload;
if (hiwdg->Init.EWI == IWDG_EWI_DISABLE)
{
/* EWI comparator value different from 0,
* Disable the early wakeup interrupt
* acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register
* Set Watchdog Early Wakeup Comparator to 0x00
*/
hiwdg->Instance->EWCR = IWDG_EWCR_EWIC;
}
else
{
/* EWI comparator value different from 0,
* Enable the early wakeup interrupt
* acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register
* Set Watchdog Early Wakeup Comparator value
*/
hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI;
}
/* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
{
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
{
return HAL_TIMEOUT;
}
}
}
/* If window parameter is different than current value, modify window
register */
if (hiwdg->Instance->WINR != hiwdg->Init.Window)
{
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
even if window feature is disabled, Watchdog will be reloaded by writing
windows register */
hiwdg->Instance->WINR = hiwdg->Init.Window;
}
else
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the IWDG MSP.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @note When rewriting this function in user file, mechanism may be added
* to avoid multiple initialize when HAL_IWDG_Init function is called
* again to change parameters.
* @retval None
*/
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hiwdg);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IWDG_MspInit could be implemented in the user file
*/
}
#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User IWDG Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hiwdg IWDG handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_IWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
* @arg @ref HAL_IWDG_MSPINIT_CB_ID MspInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID,
pIWDG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
status = HAL_ERROR;
}
else
{
switch (CallbackID)
{
case HAL_IWDG_EWI_CB_ID:
hiwdg->EwiCallback = pCallback;
break;
case HAL_IWDG_MSPINIT_CB_ID:
hiwdg->MspInitCallback = pCallback;
break;
default:
status = HAL_ERROR;
break;
}
}
return status;
}
/**
* @brief Unregister a IWDG Callback
* IWDG Callback is redirected to the weak (surcharged) predefined callback
* @param hiwdg IWDG handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_IWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
* @arg @ref HAL_IWDG_MSPINIT_CB_ID MspInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_IWDG_UnRegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_IWDG_EWI_CB_ID:
hiwdg->EwiCallback = HAL_IWDG_EarlyWakeupCallback;
break;
case HAL_IWDG_MSPINIT_CB_ID:
hiwdg->MspInitCallback = HAL_IWDG_MspInit;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Refresh the IWDG.
@endverbatim
* @{
*/
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @brief Handle IWDG interrupt request.
* @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
* or data logging must be performed before the actual reset is generated.
* The EWI interrupt is enabled by calling HAL_IWDG_Init function with
* EWIMode set to IWDG_EWI_ENABLE.
* When the downcounter reaches the value 0x40, and EWI interrupt is
* generated and the corresponding Interrupt Service Routine (ISR) can
* be used to trigger specific actions (such as communications or data
* logging), before resetting the device.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval None
*/
void HAL_IWDG_IRQHandler(IWDG_HandleTypeDef *hiwdg)
{
/* Check if IWDG Early Wakeup Interrupt occurred */
if ((hiwdg->Instance->SR & IWDG_SR_EWIF) != 0x00u)
{
/* Clear the IWDG Early Wakeup flag */
hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC;
#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1)
/* Early Wakeup registered callback */
hiwdg->EwiCallback(hiwdg);
#else
/* Early Wakeup callback */
HAL_IWDG_EarlyWakeupCallback(hiwdg);
#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */
}
}
/**
* @brief IWDG Early Wakeup callback.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval None
*/
__weak void HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hiwdg);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IWDG_EarlyWakeupCallback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_IWDG_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c
|
C
|
apache-2.0
| 16,946
|
/**
******************************************************************************
* @file stm32u5xx_hal_lptim.c
* @author MCD Application Team
* @brief LPTIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
* + Initialization and de-initialization functions.
* + Start/Stop operation functions in polling mode.
* + Start/Stop operation functions in interrupt mode.
* + Reading operation functions.
* + Peripheral State functions.
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LPTIM HAL driver can be used as follows:
(#)Initialize the LPTIM low level resources by implementing the
HAL_LPTIM_MspInit():
(++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
(++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
(+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
(+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
(+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
(#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
configures mainly:
(++) The instance: LPTIM1, LPTIM2, LPTIM3 or LPTIM4.
(++) Clock: the counter clock.
(+++) Source : it can be either the ULPTIM input (IN1) or one of
the internal clock; (APB, LSE, LSI or MSI).
(+++) Prescaler: select the clock divider.
(++) UltraLowPowerClock : To be used only if the ULPTIM is selected
as counter clock source.
(+++) Polarity: polarity of the active edge for the counter unit
if the ULPTIM input is selected.
(+++) SampleTime: clock sampling time to configure the clock glitch
filter.
(++) Trigger: How the counter start.
(+++) Source: trigger can be software or one of the hardware triggers.
(+++) ActiveEdge : only for hardware trigger.
(+++) SampleTime : trigger sampling time to configure the trigger
glitch filter.
(++) OutputPolarity : 2 opposite polarities are possible.
(++) UpdateMode: specifies whether the update of the autoreload and
the compare values is done immediately or after the end of current
period.
(++) Input1Source: Source selected for input1 (GPIO or comparator output).
(++) Input2Source: Source selected for input2 (GPIO or comparator output).
Input2 is used only for encoder feature so is used only for LPTIM1 instance.
(#)Six modes are available:
(++) PWM Mode: To generate a PWM signal with specified period and pulse,
call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
mode.
(++) One Pulse Mode: To generate pulse with specified width in response
to a stimulus, call HAL_LPTIM_OnePulse_Start() or
HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
(++) Set once Mode: In this mode, the output changes the level (from
low level to high level if the output polarity is configured high, else
the opposite) when a compare match occurs. To start this mode, call
HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
interruption mode.
(++) Encoder Mode: To use the encoder interface call
HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
interruption mode. Only available for LPTIM1 instance.
(++) Time out Mode: an active edge on one selected trigger input rests
the counter. The first trigger event will start the timer, any
successive trigger event will reset the counter and the timer will
restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
(++) Counter Mode: counter can be used to count external events on
the LPTIM Input1 or it can be used to count internal clock cycles.
To start this mode, call HAL_LPTIM_Counter_Start() or
HAL_LPTIM_Counter_Start_IT() for interruption mode.
(#) User can stop any process by calling the corresponding API:
HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
already started in interruption mode.
(#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use Function HAL_LPTIM_RegisterCallback() to register a callback.
HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
[..]
Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
default weak function.
HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
These functions allow to register/unregister following callbacks:
(+) MspInitCallback : LPTIM Base Msp Init Callback.
(+) MspDeInitCallback : LPTIM Base Msp DeInit Callback.
(+) CompareMatchCallback : Compare match Callback.
(+) AutoReloadMatchCallback : Auto-reload match Callback.
(+) TriggerCallback : External trigger event detection Callback.
(+) CompareWriteCallback : Compare register write complete Callback.
(+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
(+) DirectionUpCallback : Up-counting direction change Callback.
(+) DirectionDownCallback : Down-counting direction change Callback.
(+) UpdateEventCallback : Update event detection Callback.
(+) RepCounterWriteCallback : Repetition counter register write complete Callback.
[..]
By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init/DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
[..]
Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup LPTIM LPTIM
* @brief LPTIM HAL module driver.
* @{
*/
#ifdef HAL_LPTIM_MODULE_ENABLED
#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup LPTIM_Private_Constants
* @{
*/
#define TIMEOUT 1000UL /* Timeout is 1s */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig);
static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig);
static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig);
static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig);
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
void LPTIM_DMAError(DMA_HandleTypeDef *hdma);
void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma);
void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
uint32_t length);
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
* @{
*/
/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize the LPTIM according to the specified parameters in the
LPTIM_InitTypeDef and initialize the associated handle.
(+) DeInitialize the LPTIM peripheral.
(+) Initialize the LPTIM MSP.
(+) DeInitialize the LPTIM MSP.
@endverbatim
* @{
*/
/**
* @brief Initialize the LPTIM according to the specified parameters in the
* LPTIM_InitTypeDef and initialize the associated handle.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
{
uint32_t tmpcfgr;
/* Check the LPTIM handle allocation */
if (hlptim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PERIOD(hlptim->Init.Period));
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
}
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter));
if (hlptim->State == HAL_LPTIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hlptim->Lock = HAL_UNLOCKED;
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
/* Reset interrupt callbacks to legacy weak callbacks */
LPTIM_ResetCallback(hlptim);
if (hlptim->MspInitCallback == NULL)
{
hlptim->MspInitCallback = HAL_LPTIM_MspInit;
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hlptim->MspInitCallback(hlptim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_LPTIM_MspInit(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
/* Set the repetition counter */
__HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter);
/* Wait for the completion of the write operation to the LPTIM_RCR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Set LPTIM Period */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, hlptim->Init.Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
}
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
}
/* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
/* Set initialization parameters */
tmpcfgr |= (hlptim->Init.Clock.Source |
hlptim->Init.Clock.Prescaler |
hlptim->Init.UpdateMode |
hlptim->Init.CounterSource);
/* Glitch filters for internal triggers and external inputs are configured
* only if an internal clock source is provided to the LPTIM
*/
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
hlptim->Init.UltraLowPowerClock.SampleTime);
}
/* Configure LPTIM external clock polarity and digital filter */
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
hlptim->Init.UltraLowPowerClock.SampleTime);
}
/* Configure LPTIM external trigger */
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
tmpcfgr |= (hlptim->Init.Trigger.Source |
hlptim->Init.Trigger.ActiveEdge |
hlptim->Init.Trigger.SampleTime);
}
/* Write to LPTIMx CFGR */
hlptim->Instance->CFGR = tmpcfgr;
/* Configure LPTIM input sources */
if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
{
/* Check LPTIM Input1 and Input2 sources */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
/* Configure LPTIM Input1 and Input2 sources */
hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
}
else
{
if ((hlptim->Instance == LPTIM3) || (hlptim->Instance == LPTIM4))
{
/* Check LPTIM3 Input1 source */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
/* Configure LPTIM3 Input1 source */
hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
}
}
/* Initialize the LPTIM channels state */
LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_READY);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the LPTIM peripheral.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
{
/* Check the LPTIM handle allocation */
if (hlptim == NULL)
{
return HAL_ERROR;
}
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
__HAL_LPTIM_ENABLE(hlptim);
if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
{
hlptim->Instance->CCMR1 = 0;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
__HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, 0);
/* Wait for the completion of the write operation to the LPTIM_CCR1 register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
{
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
__HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, 0);
/* Wait for the completion of the write operation to the LPTIM_CCR2 register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
__HAL_LPTIM_AUTORELOAD_SET(hlptim, 0);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the LPTIM Peripheral Clock */
__HAL_LPTIM_DISABLE(hlptim);
hlptim->Instance->CFGR = 0;
hlptim->Instance->CFGR2 = 0;
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
if (hlptim->MspDeInitCallback == NULL)
{
hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
}
/* DeInit the low level hardware: CLOCK, NVIC.*/
hlptim->MspDeInitCallback(hlptim);
#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_LPTIM_MspDeInit(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/* Change the LPTIM channels state */
LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_RESET);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hlptim);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the LPTIM MSP.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize LPTIM MSP.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
* @brief Start-Stop operation functions.
*
@verbatim
==============================================================================
##### LPTIM Start Stop operation functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Start the PWM mode.
(+) Stop the PWM mode.
(+) Start the One pulse mode.
(+) Stop the One pulse mode.
(+) Start the Set once mode.
(+) Stop the Set once mode.
(+) Start the Encoder mode.
(+) Stop the Encoder mode.
(+) Start the Timeout mode.
(+) Stop the Timeout mode.
(+) Start the Counter mode.
(+) Stop the Counter mode.
@endverbatim
* @{
*/
/**
* @brief Start the LPTIM PWM generation.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be enabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Check LPTIM channel state */
if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
/* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Enable LPTIM signal on the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the LPTIM PWM generation.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be disabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable LPTIM signal from the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the LPTIM PWM generation in interrupt mode.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be enabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Check LPTIM channel state */
if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
/* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Enable interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
LPTIM_IT_UPDATE);
break;
case LPTIM_CHANNEL_2:
/* Enable interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
LPTIM_IT_UPDATE);
break;
default:
break;
}
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* If external trigger source is used, then enable external trigger interrupt */
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Enable external trigger interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
__HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the LPTIM PWM generation in interrupt mode.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be disabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable LPTIM signal from the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Disable interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
LPTIM_IT_UPDATE);
break;
case LPTIM_CHANNEL_2:
/* Disable interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
LPTIM_IT_UPDATE);
break;
default:
break;
}
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* If external trigger source is used, then enable external trigger interrupt */
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Enable external trigger interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the LPTIM PWM generation in DMA mode.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be enabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @param pData The destination Buffer address
* @param Length The length of data to be transferred from LPTIM peripheral to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
uint32_t Length)
{
DMA_HandleTypeDef *hdma;
/* Check the parameters */
assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
/* Check LPTIM channel state */
if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
/* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Enable update event DMA request */
__HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Set the DMA update event callbacks */
hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
/* Set the DMA error callback */
hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
/* Enable the DMA Channel */
hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR1, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
break;
case LPTIM_CHANNEL_2:
/* Set the DMA update event callbacks */
hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
/* Set the DMA error callback */
hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
/* Enable the DMA Channel */
hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR2, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
break;
default:
break;
}
/* Enable LPTIM signal on the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the LPTIM PWM generation in DMA mode.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be disabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable update event DMA request */
__HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Disable update event DMA request */
(void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
break;
case LPTIM_CHANNEL_2:
/* Disable update event DMA request */
(void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
break;
default:
break;
}
/* Disable LPTIM signal from the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the LPTIM One pulse generation.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be enabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Check LPTIM channel state */
if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
/* Reset WAVE bit to set one pulse mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Enable LPTIM signal on the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the LPTIM One pulse generation.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be disabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable LPTIM signal on the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the LPTIM One pulse generation in interrupt mode.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be enabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Check LPTIM channel state */
if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
/* Reset WAVE bit to set one pulse mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Enable interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
LPTIM_IT_UPDATE);
break;
case LPTIM_CHANNEL_2:
/* Enable interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
LPTIM_IT_UPDATE);
break;
default:
break;
}
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* If external trigger source is used, then enable external trigger interrupt */
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Enable external trigger interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Enable LPTIM signal on the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the LPTIM One pulse generation in interrupt mode.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be disabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable LPTIM signal on the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Disable interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
LPTIM_IT_UPDATE);
break;
case LPTIM_CHANNEL_2:
/* Disable interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
LPTIM_IT_UPDATE);
break;
default:
break;
}
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* If external trigger source is used, then enable external trigger interrupt */
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Enable external trigger interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the LPTIM in Set once mode.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be enabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Check LPTIM channel state */
if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
/* Set WAVE bit to enable the set once mode */
hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Enable LPTIM signal on the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the LPTIM Set once mode.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be disabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable LPTIM signal on the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the LPTIM Set once mode in interrupt mode.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be enabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Check LPTIM channel state */
if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
/* Set WAVE bit to enable the set once mode */
hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Enable interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
break;
case LPTIM_CHANNEL_2:
/* Enable interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
break;
default:
break;
}
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* If external trigger source is used, then enable external trigger interrupt */
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Enable external trigger interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Enable LPTIM signal on the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
/* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the LPTIM Set once mode in interrupt mode.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be disabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable LPTIM signal on the corresponding output pin */
__HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Disable interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
break;
case LPTIM_CHANNEL_2:
/* Disable interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
break;
default:
break;
}
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* If external trigger source is used, then enable external trigger interrupt */
if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Enable external trigger interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the Encoder interface.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim)
{
uint32_t tmpcfgr;
/* Check the parameters */
assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
/* Clear CKPOL bits */
tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
/* Set Input polarity */
tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
/* Write to LPTIMx CFGR */
hlptim->Instance->CFGR = tmpcfgr;
/* Set ENC bit to enable the encoder interface */
hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the Encoder interface.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the Encoder interface in interrupt mode.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim)
{
uint32_t tmpcfgr;
/* Check the parameters */
assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Configure edge sensitivity for encoder mode */
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
/* Clear CKPOL bits */
tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
/* Set Input polarity */
tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
/* Write to LPTIMx CFGR */
hlptim->Instance->CFGR = tmpcfgr;
/* Set ENC bit to enable the encoder interface */
hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Enable "switch to up/down direction" interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the Encoder interface in interrupt mode.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Disable "switch to down/up direction" interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the Timeout function.
* @note The first trigger event will start the timer, any successive
* trigger event will reset the counter and the timer restarts.
* @param hlptim LPTIM handle
* @param Timeout Specifies the TimeOut value to reset the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PULSE(Timeout));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
/* Wait for the completion of the write operation to the LPTIM_CCR1 register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the Timeout function.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the Timeout function in interrupt mode.
* @note The first trigger event will start the timer, any successive
* trigger event will reset the counter and the timer restarts.
* @param hlptim LPTIM handle
* @param Timeout Specifies the TimeOut value to reset the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_PULSE(Timeout));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Enable Compare match CH1 interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
/* Wait for the completion of the write operation to the LPTIM_CCR1 register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the Timeout function in interrupt mode.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Disable Compare match CH1 interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the Counter mode.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
&& (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
/* Set clock prescaler to 0 */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
}
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the Counter mode.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Start the Counter mode in interrupt mode.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
&& (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
/* Set clock prescaler to 0 */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
}
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Enable interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stop the Counter mode in interrupt mode.
* @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
/* Disable interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the LPTIM Input Capture measurement.
* @param hlptim LPTIM Input Capture handle
* @param Channel LPTIM Channels to be enabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Check LPTIM channel state */
if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Enable capture */
__HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the LPTIM Input Capture measurement.
* @param hlptim LPTIM Input Capture handle
* @param Channel LPTIM Channels to be disabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Disable capture */
__HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the LPTIM Input Capture measurement in interrupt mode.
* @param hlptim LPTIM Input Capture handle
* @param Channel LPTIM Channels to be enabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Check LPTIM channel state */
if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Enable Capture/Compare 1 interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
break;
case LPTIM_CHANNEL_2:
/* Disable Capture/Compare 2 interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC2);
break;
default:
break;
}
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Enable capture */
__HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the LPTIM Input Capture measurement in interrupt mode.
* @param hlptim LPTIM Input Capture handle
* @param Channel LPTIM Channels to be disabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Disable Capture/Compare 1 interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
break;
case LPTIM_CHANNEL_2:
/* Disable Capture/Compare 2 interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC2);
break;
default:
return HAL_ERROR;
break;
}
/* Disable capture */
__HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Starts the LPTIM Input Capture measurement in DMA mode.
* @param hlptim LPTIM Input Capture handle
* @param Channel LPTIM Channels to be enabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
* @param pData The destination Buffer address
* @param Length The length of data to be transferred from LPTIM peripheral to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
uint32_t Length)
{
DMA_HandleTypeDef *hdma;
/* Check the parameters */
assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
/* Check LPTIM channel state */
if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Set the DMA capture callbacks */
hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMACaptureCplt;
hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
/* Enable the DMA Channel */
hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable Capture/Compare 1 DMA request */
__HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC1);
break;
case LPTIM_CHANNEL_2:
/* Set the DMA capture callbacks */
hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMACaptureCplt;
hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
/* Enable the DMA Channel */
hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable Capture/Compare 2 DMA request */
__HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC2);
break;
default:
break;
}
/* Wait for the completion of the write operation to the LPTIM_DIER register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim);
/* Enable capture */
__HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Stops the LPTIM Input Capture measurement in DMA mode.
* @param hlptim LPTIM Input Capture handle
* @param Channel LPTIM Channels to be disabled
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
switch (Channel)
{
case LPTIM_CHANNEL_1:
/* Disable Capture/Compare 1 DMA request */
__HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC1);
(void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
break;
case LPTIM_CHANNEL_2:
/* Disable Capture/Compare 2 DMA request */
__HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC2);
(void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
break;
default:
return HAL_ERROR;
break;
}
/* Disable capture */
__HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Set the LPTIM channel state */
LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
/* Set the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
* @brief Read operation functions.
*
@verbatim
==============================================================================
##### LPTIM Read operation functions #####
==============================================================================
[..] This section provides LPTIM Reading functions.
(+) Read the counter value.
(+) Read the period (Auto-reload) value.
(+) Read the pulse (Compare)value.
@endverbatim
* @{
*/
/**
* @brief Return the current counter value.
* @param hlptim LPTIM handle
* @retval Counter value.
*/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
return (hlptim->Instance->CNT);
}
/**
* @brief Return the current Autoreload (Period) value.
* @param hlptim LPTIM handle
* @retval Autoreload value.
*/
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
return (hlptim->Instance->ARR);
}
/**
* @brief Return the current Compare (Pulse) value.
* @param hlptim LPTIM handle
* @param Channel LPTIM Channel to be selected
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval Compare value.
*/
uint32_t HAL_LPTIM_ReadCapturedValue(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
uint32_t tmpccr;
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
switch (Channel)
{
case LPTIM_CHANNEL_1:
tmpccr = hlptim->Instance->CCR1;
break;
case LPTIM_CHANNEL_2:
tmpccr = hlptim->Instance->CCR2;
break;
default:
tmpccr = 0;
break;
}
return tmpccr;
}
/**
* @brief LPTimer Input Capture Get Offset(in counter step unit)
* @note The real capture value corresponding to the input capture trigger can be calculated using
* the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
* The Offset value is depending on the glitch filter value for the channel
* and the value of the prescaler for the kernel clock.
* Please check Errata Sheet V1_8 for more details under "variable latency
* on input capture channel" section.
* @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @param Channel This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval The offset value
*/
uint8_t HAL_LPTIM_IC_GetOffset(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
{
uint8_t offset ;
uint32_t prescaler;
uint32_t filter ;
/* Get prescaler value */
prescaler = LL_LPTIM_GetPrescaler(hlptim->Instance);
/* Get filter value */
filter = LL_LPTIM_IC_GetFilter(hlptim->Instance, Channel);
/* Get offset value */
offset = LL_LPTIM_IC_GET_OFFSET(prescaler, filter);
/* return offset value */
return offset;
}
/**
* @}
*/
/** @defgroup LPTIM_Exported_Functions_Group5 LPTIM Config function
* @brief Config channel
*
@verbatim
==============================================================================
##### LPTIM Config function #####
==============================================================================
[..] This section provides LPTIM Config function.
(+) Configure channel: Output Compare mode, Period, Polarity.
@endverbatim
* @{
*/
/**
* @brief
* @param hlptim LPTIM handle
* @param sConfig The output configuration structure
* @param Channel LPTIM Channel to be configured
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig,
uint32_t Channel)
{
HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_LPTIM_PULSE(sConfig->Pulse));
hlptim->State = HAL_LPTIM_STATE_BUSY;
switch (Channel)
{
case LPTIM_CHANNEL_1:
{
/* Check the parameters */
assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
/* Configure the LPTIM Channel 1 in Output Compare */
status = LPTIM_OC1_SetConfig(hlptim, sConfig);
if (status != HAL_OK)
{
return status;
}
break;
}
case LPTIM_CHANNEL_2:
{
/* Check the parameters */
assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
/* Configure the LPTIM Channel 2 in Output Compare */
status = LPTIM_OC2_SetConfig(hlptim, sConfig);
if (status != HAL_OK)
{
return status;
}
break;
}
default:
break;
}
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief
* @param hlptim LPTIM handle
* @param sConfig The input configuration structure
* @param Channel LPTIM Channel to be configured
* This parameter can be one of the following values:
* @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
* @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig,
uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler));
assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity));
assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter));
hlptim->State = HAL_LPTIM_STATE_BUSY;
switch (Channel)
{
case LPTIM_CHANNEL_1:
{
/* Check the parameters */
assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_IC1_SOURCE(hlptim->Instance, sConfig->ICInputSource));
/* Configure the LPTIM Channel 1 in Input Capture */
LPTIM_IC1_SetConfig(hlptim, sConfig);
break;
}
case LPTIM_CHANNEL_2:
{
/* Check the parameters */
assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
assert_param(IS_LPTIM_IC2_SOURCE(hlptim->Instance, sConfig->ICInputSource));
/* Configure the LPTIM Channel 2 in Input Capture */
LPTIM_IC2_SetConfig(hlptim, sConfig);
break;
}
default:
break;
}
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
* @brief LPTIM IRQ handler.
*
@verbatim
==============================================================================
##### LPTIM IRQ handler and callbacks #####
==============================================================================
[..] This section provides LPTIM IRQ handler and callback functions called within
the IRQ handler:
(+) LPTIM interrupt request handler
(+) Compare match Callback
(+) Auto-reload match Callback
(+) External trigger event detection Callback
(+) Compare register write complete Callback
(+) Auto-reload register write complete Callback
(+) Up-counting direction change Callback
(+) Down-counting direction change Callback
@endverbatim
* @{
*/
/**
* @brief Handle LPTIM interrupt request.
* @param hlptim LPTIM handle
* @retval None
*/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
{
/* Capture Compare 1 interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1) != RESET)
{
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1);
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
/* Input capture event */
if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC1SEL) != 0x00U)
{
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->IC_CaptureCallback(hlptim);
#else
HAL_LPTIM_IC_CaptureCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->CompareMatchCallback(hlptim);
#else
HAL_LPTIM_CompareMatchCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Capture Compare 2 interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2) != RESET)
{
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2);
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC2SEL) != 0x00U)
{
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->IC_CaptureCallback(hlptim);
#else
HAL_LPTIM_IC_CaptureCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->CompareMatchCallback(hlptim);
#else
HAL_LPTIM_CompareMatchCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Over Capture 1 interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1O) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1O) != RESET)
{
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1O);
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
/* Over capture event */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->IC_OverCaptureCallback(hlptim);
#else
HAL_LPTIM_IC_OverCaptureCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Over Capture 2 interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2O) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2O) != RESET)
{
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2O);
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
/* Over capture event */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->IC_OverCaptureCallback(hlptim);
#else
HAL_LPTIM_IC_OverCaptureCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Autoreload match interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
{
/* Clear Autoreload match flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
/* Autoreload match Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->AutoReloadMatchCallback(hlptim);
#else
HAL_LPTIM_AutoReloadMatchCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Trigger detected interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
{
/* Clear Trigger detected flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
/* Trigger detected callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->TriggerCallback(hlptim);
#else
HAL_LPTIM_TriggerCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Compare write interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP1OK) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP1OK) != RESET)
{
/* Clear Compare write flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
/* Compare write Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->CompareWriteCallback(hlptim);
#else
HAL_LPTIM_CompareWriteCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Compare write interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP2OK) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP2OK) != RESET)
{
/* Clear Compare write flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
/* Compare write Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->CompareWriteCallback(hlptim);
#else
HAL_LPTIM_CompareWriteCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Autoreload write interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
{
/* Clear Autoreload write flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Autoreload write Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->AutoReloadWriteCallback(hlptim);
#else
HAL_LPTIM_AutoReloadWriteCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Direction counter changed from Down to Up interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
{
/* Clear Direction counter changed from Down to Up flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
/* Direction counter changed from Down to Up Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->DirectionUpCallback(hlptim);
#else
HAL_LPTIM_DirectionUpCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Direction counter changed from Up to Down interrupt */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
{
/* Clear Direction counter changed from Up to Down flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
/* Direction counter changed from Up to Down Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->DirectionDownCallback(hlptim);
#else
HAL_LPTIM_DirectionDownCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Repetition counter underflowed (or contains zero) and the LPTIM counter
overflowed */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET)
{
/* Clear update event flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE);
/* Update event Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->UpdateEventCallback(hlptim);
#else
HAL_LPTIM_UpdateEventCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
/* Successful APB bus write to repetition counter register */
if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET)
{
if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET)
{
/* Clear successful APB bus write to repetition counter flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
/* Successful APB bus write to repetition counter Callback */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->RepCounterWriteCallback(hlptim);
#else
HAL_LPTIM_RepCounterWriteCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
}
/**
* @brief Compare match callback in non-blocking mode.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
*/
}
/**
* @brief Autoreload match callback in non-blocking mode.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
*/
}
/**
* @brief Trigger detected callback in non-blocking mode.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_TriggerCallback could be implemented in the user file
*/
}
/**
* @brief Compare write callback in non-blocking mode.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
*/
}
/**
* @brief Autoreload write callback in non-blocking mode.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
*/
}
/**
* @brief Direction counter changed from Down to Up callback in non-blocking mode.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
*/
}
/**
* @brief Direction counter changed from Up to Down callback in non-blocking mode.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
*/
}
/**
* @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_UpdateEventCallback could be implemented in the user file
*/
}
/**
* @brief Successful APB bus write to repetition counter register callback in non-blocking mode.
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file
*/
}
/**
* @brief Input Capture callback in non-blocking mode
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_IC_CaptureCallback could be implemented in the user file
*/
}
/**
* @brief Over Capture callback in non-blocking mode
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_IC_OverCaptureCallback could be implemented in the user file
*/
}
/**
* @brief Input Capture half complete callback in non-blocking mode
* @param hlptim LPTIM IC handle
* @retval None
*/
__weak void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_IC_CaptureHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Update event half complete callback in non-blocking mode
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_UpdateEventHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Error callback in non-blocking mode
* @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hlptim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LPTIM_ErrorCallback could be implemented in the user file
*/
}
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User LPTIM callback to be used instead of the weak predefined callback
* @param hlptim LPTIM handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
* @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
* @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
* @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
* @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
* @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
* @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
* @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
* @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
* @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
* @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
* @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
* @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
* @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
* @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
* @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
* @param pCallback pointer to the callback function
* @retval status
*/
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
HAL_LPTIM_CallbackIDTypeDef CallbackID,
pLPTIM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hlptim);
if (hlptim->State == HAL_LPTIM_STATE_READY)
{
switch (CallbackID)
{
case HAL_LPTIM_MSPINIT_CB_ID :
hlptim->MspInitCallback = pCallback;
break;
case HAL_LPTIM_MSPDEINIT_CB_ID :
hlptim->MspDeInitCallback = pCallback;
break;
case HAL_LPTIM_COMPARE_MATCH_CB_ID :
hlptim->CompareMatchCallback = pCallback;
break;
case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
hlptim->AutoReloadMatchCallback = pCallback;
break;
case HAL_LPTIM_TRIGGER_CB_ID :
hlptim->TriggerCallback = pCallback;
break;
case HAL_LPTIM_COMPARE_WRITE_CB_ID :
hlptim->CompareWriteCallback = pCallback;
break;
case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
hlptim->AutoReloadWriteCallback = pCallback;
break;
case HAL_LPTIM_DIRECTION_UP_CB_ID :
hlptim->DirectionUpCallback = pCallback;
break;
case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
hlptim->DirectionDownCallback = pCallback;
break;
case HAL_LPTIM_UPDATE_EVENT_CB_ID :
hlptim->UpdateEventCallback = pCallback;
break;
case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
hlptim->RepCounterWriteCallback = pCallback;
break;
case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
hlptim->UpdateEventHalfCpltCallback = pCallback;
break;
case HAL_LPTIM_IC_CAPTURE_CB_ID :
hlptim->IC_CaptureCallback = pCallback;
break;
case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
hlptim->IC_CaptureHalfCpltCallback = pCallback;
break;
case HAL_LPTIM_OVER_CAPTURE_CB_ID :
hlptim->IC_OverCaptureCallback = pCallback;
break;
case HAL_LPTIM_ERROR_CB_ID :
hlptim->ErrorCallback = pCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hlptim->State == HAL_LPTIM_STATE_RESET)
{
switch (CallbackID)
{
case HAL_LPTIM_MSPINIT_CB_ID :
hlptim->MspInitCallback = pCallback;
break;
case HAL_LPTIM_MSPDEINIT_CB_ID :
hlptim->MspDeInitCallback = pCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hlptim);
return status;
}
/**
* @brief Unregister a LPTIM callback
* LLPTIM callback is redirected to the weak predefined callback
* @param hlptim LPTIM handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
* @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
* @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
* @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
* @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
* @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
* @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
* @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
* @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
* @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
* @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
HAL_LPTIM_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hlptim);
if (hlptim->State == HAL_LPTIM_STATE_READY)
{
switch (CallbackID)
{
case HAL_LPTIM_MSPINIT_CB_ID :
/* Legacy weak MspInit Callback */
hlptim->MspInitCallback = HAL_LPTIM_MspInit;
break;
case HAL_LPTIM_MSPDEINIT_CB_ID :
/* Legacy weak Msp DeInit Callback */
hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
break;
case HAL_LPTIM_COMPARE_MATCH_CB_ID :
/* Legacy weak Compare match Callback */
hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
break;
case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
/* Legacy weak Auto-reload match Callback */
hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
break;
case HAL_LPTIM_TRIGGER_CB_ID :
/* Legacy weak External trigger event detection Callback */
hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
break;
case HAL_LPTIM_COMPARE_WRITE_CB_ID :
/* Legacy weak Compare register write complete Callback */
hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
break;
case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
/* Legacy weak Auto-reload register write complete Callback */
hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
break;
case HAL_LPTIM_DIRECTION_UP_CB_ID :
/* Legacy weak Up-counting direction change Callback */
hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
break;
case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
/* Legacy weak Down-counting direction change Callback */
hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
break;
case HAL_LPTIM_UPDATE_EVENT_CB_ID :
/* Legacy weak Update event detection Callback */
hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
break;
case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
/* Legacy weak Repetition counter register write complete Callback */
hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
break;
case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
/* Legacy weak Update event half complete detection Callback */
hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
break;
case HAL_LPTIM_IC_CAPTURE_CB_ID :
/* Legacy weak IC Capture Callback */
hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
break;
case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
/* Legacy weak IC Capture half complete Callback */
hlptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
break;
case HAL_LPTIM_OVER_CAPTURE_CB_ID :
/* Legacy weak IC over capture Callback */
hlptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hlptim->State == HAL_LPTIM_STATE_RESET)
{
switch (CallbackID)
{
case HAL_LPTIM_MSPINIT_CB_ID :
/* Legacy weak MspInit Callback */
hlptim->MspInitCallback = HAL_LPTIM_MspInit;
break;
case HAL_LPTIM_MSPDEINIT_CB_ID :
/* Legacy weak Msp DeInit Callback */
hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
break;
default :
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hlptim);
return status;
}
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup LPTIM_Group5 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
==============================================================================
##### Peripheral State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the LPTIM handle state.
* @param hlptim LPTIM handle
* @retval HAL state
*/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
{
/* Return LPTIM handle state */
return hlptim->State;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
/**
* @brief Reset interrupt callbacks to the legacy weak callbacks.
* @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @retval None
*/
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
{
/* Reset the LPTIM callback to the legacy weak callbacks */
lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
lptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
lptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
lptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
lptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
lptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
}
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @brief LPTimer Wait for flag set
* @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @param flag The lptim flag
* @retval HAL status
*/
static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
do
{
count--;
if (count == 0UL)
{
result = HAL_TIMEOUT;
}
} while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
return result;
}
/**
* @brief LPTIM DMA error callback
* @param hdma pointer to DMA handle.
* @retval None
*/
void LPTIM_DMAError(DMA_HandleTypeDef *hdma)
{
LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hlptim->State = HAL_LPTIM_STATE_READY;
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->ErrorCallback(hlptim);
#else
HAL_LPTIM_ErrorCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
/**
* @brief LPTIM DMA Capture complete callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
{
LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hlptim->State = HAL_LPTIM_STATE_READY;
if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
{
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
}
else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
{
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
}
else
{
/* nothing to do */
}
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->IC_CaptureCallback(hlptim);
#else
HAL_LPTIM_IC_CaptureCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief LPTIM DMA Capture half complete callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
{
LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hlptim->State = HAL_LPTIM_STATE_READY;
if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
{
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
}
else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
{
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
}
else
{
/* nothing to do */
}
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->IC_CaptureHalfCpltCallback(hlptim);
#else
HAL_LPTIM_IC_CaptureHalfCpltCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief LPTIM DMA Update event complete callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma)
{
LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hlptim->State = HAL_LPTIM_STATE_READY;
if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
{
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
}
else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
{
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
}
else
{
/* nothing to do */
}
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->UpdateEventCallback(hlptim);
#else
HAL_LPTIM_UpdateEventCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief LPTIM DMA Capture half complete callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma)
{
LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hlptim->State = HAL_LPTIM_STATE_READY;
if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
{
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
}
else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
{
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
}
else
{
/* nothing to do */
}
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
hlptim->UpdateEventHalfCpltCallback(hlptim);
#else
HAL_LPTIM_UpdateEventHalfCpltCallback(hlptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief LPTimer Output Compare 1 configuration
* @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @param sConfig The output configuration structure
* @retval None
*/
static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig)
{
uint32_t tmpccmr1;
uint32_t tmpcfgr;
tmpccmr1 = hlptim->Instance->CCMR1;
tmpccmr1 &= ~(LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_CC1SEL_Msk);
if (hlptim->Instance == LPTIM4)
{
tmpcfgr = hlptim->Instance->CFGR;
tmpcfgr &= ~LPTIM_CFGR_WAVPOL_Msk;
tmpcfgr |= sConfig->OCPolarity << LPTIM_CFGR_WAVPOL_Pos;
/* Write to CFGR register */
hlptim->Instance->CFGR = tmpcfgr;
}
else
{
tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC1P_Pos;
}
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
/* Write to CCR1 register */
__HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, sConfig->Pulse);
/* Wait for the completion of the write operation to the LPTIM_CCR1 register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Write to CCMR1 register */
hlptim->Instance->CCMR1 = tmpccmr1;
return HAL_OK;
}
/**
* @brief LPTimer Output Compare 2 configuration
* @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @param sConfig The output configuration structure
* @retval None
*/
static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_OC_ConfigTypeDef *sConfig)
{
uint32_t tmpccmr1;
tmpccmr1 = hlptim->Instance->CCMR1;
tmpccmr1 &= ~(LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_CC2SEL_Msk);
tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC2P_Pos;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
/* Write to CCR2 register */
__HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, sConfig->Pulse);
/* Wait for the completion of the write operation to the LPTIM_CCR2 register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
/* Write to CCMR1 register */
hlptim->Instance->CCMR1 = tmpccmr1;
return HAL_OK;
}
/**
* @brief LPTimer Input Capture 1 configuration
* @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @param sConfig The input configuration structure
* @retval None
*/
static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig)
{
uint32_t tmpccmr1;
uint32_t tmpcfgr2;
tmpccmr1 = hlptim->Instance->CCMR1;
tmpccmr1 &= ~(LPTIM_CCMR1_IC1PSC_Msk | LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_IC1F_Msk);
tmpccmr1 |= sConfig->ICPrescaler |
sConfig->ICPolarity |
sConfig->ICFilter |
LPTIM_CCMR1_CC1SEL;
tmpcfgr2 = hlptim->Instance->CFGR2;
tmpcfgr2 &= ~(LPTIM_CFGR2_IC1SEL_Msk);
tmpcfgr2 |= sConfig->ICInputSource;
/* Write to CCMR1 register */
hlptim->Instance->CCMR1 = tmpccmr1;
/* Write to CFGR2 register */
hlptim->Instance->CFGR2 = tmpcfgr2;
}
/**
* @brief LPTimer Input Capture 2 configuration
* @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @param sConfig The input configuration structure
* @retval None
*/
static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, LPTIM_IC_ConfigTypeDef *sConfig)
{
uint32_t tmpccmr1;
uint32_t tmpcfgr2;
tmpccmr1 = hlptim->Instance->CCMR1;
tmpccmr1 &= ~(LPTIM_CCMR1_IC2PSC_Msk | LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_IC2F_Msk);
tmpccmr1 |= (sConfig->ICPrescaler << (LPTIM_CCMR1_IC2PSC_Pos - LPTIM_CCMR1_IC1PSC_Pos)) |
(sConfig->ICPolarity << (LPTIM_CCMR1_CC2P_Pos - LPTIM_CCMR1_CC1P_Pos)) |
(sConfig->ICFilter << (LPTIM_CCMR1_IC2F_Pos - LPTIM_CCMR1_IC1F_Pos)) |
LPTIM_CCMR1_CC2SEL;
tmpcfgr2 = hlptim->Instance->CFGR2;
tmpcfgr2 &= ~(LPTIM_CFGR2_IC2SEL_Msk);
tmpcfgr2 |= sConfig->ICInputSource;
/* Write to CCMR1 register */
hlptim->Instance->CCMR1 = tmpccmr1;
/* Write to CFGR2 register */
hlptim->Instance->CFGR2 = tmpcfgr2;
}
/**
* @brief Start the DMA data transfer.
* @param hdma DMA handle
* @param src The source memory Buffer address.
* @param dst The destination memory Buffer address.
* @param length The size of a source block transfer in byte.
* @retval HAL status
*/
HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
uint32_t length)
{
HAL_StatusTypeDef status;
/* Enable the DMA channel */
if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
{
/* Enable the DMA channel */
hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)src;
hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)dst;
status = HAL_DMAEx_List_Start_IT(hdma);
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hdma, src, dst, length);
}
return status;
}
/**
* @}
*/
#endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 */
#endif /* HAL_LPTIM_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c
|
C
|
apache-2.0
| 116,806
|
/**
******************************************************************************
* @file stm32u5xx_hal_ltdc.c
* @author MCD Application Team
* @brief LTDC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LTDC peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LTDC HAL driver can be used as follows:
(#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef hltdc;
(#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API:
(##) Enable the LTDC interface clock
(##) NVIC configuration if you need to use interrupt process
(+++) Configure the LTDC interrupt priority
(+++) Enable the NVIC LTDC IRQ Channel
(#) Initialize the required configuration through the following parameters:
the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity,
Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function
*** Configuration ***
=========================
[..]
(#) Program the required configuration through the following parameters:
the pixel format, the blending factors, input alpha value, the window size
and the image size using HAL_LTDC_ConfigLayer() function for foreground
or/and background layer.
(#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and
HAL_LTDC_EnableCLUT functions.
(#) Optionally, enable the Dither using HAL_LTDC_EnableDither().
(#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying()
and HAL_LTDC_EnableColorKeying functions.
(#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent()
function
(#) If needed, reconfigure and change the pixel format value, the alpha value
value, the window size, the window position and the layer start address
for foreground or/and background layer using respectively the following
functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress().
(#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload.
This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload().
After calling the _NoReload functions to set different color/format/layer settings,
the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings.
Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if
an immediate reload is required.
Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if
the reload should be done in the next vertical blanking period,
this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
(#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
*** LTDC HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in LTDC HAL driver.
(+) __HAL_LTDC_ENABLE: Enable the LTDC.
(+) __HAL_LTDC_DISABLE: Disable the LTDC.
(+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer.
(+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer.
(+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration.
(+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags.
(+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags.
(+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts.
(+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
(+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
[..]
(@) You can refer to the LTDC HAL driver header file for more useful macros
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use function HAL_LTDC_RegisterCallback() to register a callback.
[..]
Function HAL_LTDC_RegisterCallback() allows to register following callbacks:
(+) LineEventCallback : LTDC Line Event Callback.
(+) ReloadEventCallback : LTDC Reload Event Callback.
(+) ErrorCallback : LTDC Error Callback
(+) MspInitCallback : LTDC MspInit.
(+) MspDeInitCallback : LTDC MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
[..]
Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default
weak function.
HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle
and the callback ID.
[..]
This function allows to reset following callbacks:
(+) LineEventCallback : LTDC Line Event Callback
(+) ReloadEventCallback : LTDC Reload Event Callback
(+) ErrorCallback : LTDC Error Callback
(+) MspInitCallback : LTDC MspInit
(+) MspDeInitCallback : LTDC MspDeInit.
[..]
By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit()
only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit()
or HAL_LTDC_Init() function.
[..]
When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_LTDC_MODULE_ENABLED
#if defined (LTDC)
/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
/* Private functions ---------------------------------------------------------*/
/** @defgroup LTDC_Exported_Functions LTDC Exported Functions
* @{
*/
/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the LTDC
(+) De-initialize the LTDC
@endverbatim
* @{
*/
/**
* @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
uint32_t tmp;
uint32_t tmp1;
/* Check the LTDC peripheral state */
if (hltdc == NULL)
{
return HAL_ERROR;
}
/* Check function parameters */
assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync));
assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync));
assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP));
assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP));
assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH));
assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW));
assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh));
assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth));
assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity));
assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity));
assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity));
assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity));
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
if (hltdc->State == HAL_LTDC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hltdc->Lock = HAL_UNLOCKED;
/* Reset the LTDC callback to the legacy weak callbacks */
hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */
hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */
hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */
if (hltdc->MspInitCallback == NULL)
{
hltdc->MspInitCallback = HAL_LTDC_MspInit;
}
/* Init the low level hardware */
hltdc->MspInitCallback(hltdc);
}
#else
if (hltdc->State == HAL_LTDC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hltdc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
}
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Configure the HS, VS, DE and PC polarity */
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
/* Set Synchronization size */
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
tmp = (hltdc->Init.HorizontalSync << 16U);
hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
/* Set Accumulated Back porch */
hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
tmp = (hltdc->Init.AccumulatedHBP << 16U);
hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
/* Set Accumulated Active Width */
hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
/* Set Total Width */
hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
tmp = (hltdc->Init.TotalWidth << 16U);
hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
/* Set the background color value */
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
/* Enable the Transfer Error and FIFO underrun interrupts */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
/* Enable LTDC by setting LTDCEN bit */
__HAL_LTDC_ENABLE(hltdc);
/* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
return HAL_OK;
}
/**
* @brief De-initialize the LTDC peripheral.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
{
uint32_t tickstart;
/* Check the LTDC peripheral state */
if (hltdc == NULL)
{
return HAL_ERROR;
}
/* Check function parameters */
assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
/* Disable LTDC Layer 1 */
__HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1);
#if defined(LTDC_Layer2_BASE)
/* Disable LTDC Layer 2 */
__HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2);
#endif /* LTDC_Layer2_BASE */
/* Reload during vertical blanking period */
__HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for VSYNC Interrupt */
while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE)
{
break;
}
}
/* Disable LTDC */
__HAL_LTDC_DISABLE(hltdc);
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
if (hltdc->MspDeInitCallback == NULL)
{
hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit;
}
/* DeInit the low level hardware */
hltdc->MspDeInitCallback(hltdc);
#else
/* DeInit the low level hardware */
HAL_LTDC_MspDeInit(hltdc);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Initialize the LTDC MSP.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_MspInit could be implemented in the user file
*/
}
/**
* @brief De-initialize the LTDC MSP.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_MspDeInit could be implemented in the user file
*/
}
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User LTDC Callback
* To be used instead of the weak predefined callback
* @param hltdc ltdc handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
* @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
* @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
pLTDC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hltdc);
if (hltdc->State == HAL_LTDC_STATE_READY)
{
switch (CallbackID)
{
case HAL_LTDC_LINE_EVENT_CB_ID :
hltdc->LineEventCallback = pCallback;
break;
case HAL_LTDC_RELOAD_EVENT_CB_ID :
hltdc->ReloadEventCallback = pCallback;
break;
case HAL_LTDC_ERROR_CB_ID :
hltdc->ErrorCallback = pCallback;
break;
case HAL_LTDC_MSPINIT_CB_ID :
hltdc->MspInitCallback = pCallback;
break;
case HAL_LTDC_MSPDEINIT_CB_ID :
hltdc->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hltdc->State == HAL_LTDC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_LTDC_MSPINIT_CB_ID :
hltdc->MspInitCallback = pCallback;
break;
case HAL_LTDC_MSPDEINIT_CB_ID :
hltdc->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hltdc);
return status;
}
/**
* @brief Unregister an LTDC Callback
* LTDC callback is redirected to the weak predefined callback
* @param hltdc ltdc handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID
* @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID
* @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID
* @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hltdc);
if (hltdc->State == HAL_LTDC_STATE_READY)
{
switch (CallbackID)
{
case HAL_LTDC_LINE_EVENT_CB_ID :
hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */
break;
case HAL_LTDC_RELOAD_EVENT_CB_ID :
hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */
break;
case HAL_LTDC_ERROR_CB_ID :
hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_LTDC_MSPINIT_CB_ID :
hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */
break;
case HAL_LTDC_MSPDEINIT_CB_ID :
hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */
break;
default :
/* Update the error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hltdc->State == HAL_LTDC_STATE_RESET)
{
switch (CallbackID)
{
case HAL_LTDC_MSPINIT_CB_ID :
hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */
break;
case HAL_LTDC_MSPDEINIT_CB_ID :
hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */
break;
default :
/* Update the error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hltdc);
return status;
}
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides function allowing to:
(+) Handle LTDC interrupt request
@endverbatim
* @{
*/
/**
* @brief Handle LTDC interrupt request.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
{
uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
uint32_t itsources = READ_REG(hltdc->Instance->IER);
/* Transfer Error Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
{
/* Disable the transfer Error interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
/* Clear the transfer error flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
/* Transfer error Callback */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* FIFO underrun Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
{
/* Disable the FIFO underrun interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
/* Clear the FIFO underrun flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
/* Transfer error Callback */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Line Interrupt management ************************************************/
if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
{
/* Disable the Line interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
/* Clear the Line interrupt flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
/* Line interrupt Callback */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered Line Event callback */
hltdc->LineEventCallback(hltdc);
#else
/*Call Legacy Line Event callback */
HAL_LTDC_LineEventCallback(hltdc);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Register reload Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
{
/* Disable the register reload interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
/* Clear the register reload flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
/* Reload interrupt Callback */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered reload Event callback */
hltdc->ReloadEventCallback(hltdc);
#else
/*Call Legacy Reload Event callback */
HAL_LTDC_ReloadEventCallback(hltdc);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
}
/**
* @brief Error LTDC callback.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief Line Event callback.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_LineEventCallback could be implemented in the user file
*/
}
/**
* @brief Reload Event callback.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the LTDC foreground or/and background parameters.
(+) Set the active layer.
(+) Configure the color keying.
(+) Configure the C-LUT.
(+) Enable / Disable the color keying.
(+) Enable / Disable the C-LUT.
(+) Update the layer position.
(+) Update the layer size.
(+) Update pixel format on the fly.
(+) Update transparency on the fly.
(+) Update address on the fly.
@endverbatim
* @{
*/
/**
* @brief Configure the LTDC Layer according to the specified
* parameters in the LTDC_InitTypeDef and create the associated handle.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
* the configuration information for the Layer.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Configure the color keying.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param RGBValue the color key value
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Configure the default color values */
LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Load the color lookup table.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param pCLUT pointer to the color lookup table address.
* @param CLUTSize the color lookup table size.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx)
{
uint32_t tmp;
uint32_t counter;
uint32_t *pcolorlut = pCLUT;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
for (counter = 0U; (counter < CLUTSize); counter++)
{
if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
{
tmp = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
}
else
{
tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
}
pcolorlut++;
/* Specifies the C-LUT address and RGB value */
LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp;
}
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Enable the color keying.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Enable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Disable the color keying.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Disable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Enable the color lookup table.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Enable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Disable the color lookup table.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Disable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Enable Dither.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
{
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Enable Dither by setting DTEN bit */
LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Disable Dither.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
{
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Disable Dither by setting DTEN bit */
LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Set the LTDC window size.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param XSize LTDC Pixel per line
* @param YSize LTDC Line number
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Check the parameters (Layers parameters)*/
assert_param(IS_LTDC_LAYER(LayerIdx));
assert_param(IS_LTDC_CFBLL(XSize));
assert_param(IS_LTDC_CFBLNBR(YSize));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* update horizontal stop */
pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
/* update vertical stop */
pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
/* Reconfigures the color frame buffer pitch in byte */
pLayerCfg->ImageWidth = XSize;
/* Reconfigures the frame buffer line number */
pLayerCfg->ImageHeight = YSize;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Set the LTDC window position.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param X0 LTDC window X offset
* @param Y0 LTDC window Y offset
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
assert_param(IS_LTDC_CFBLL(X0));
assert_param(IS_LTDC_CFBLNBR(Y0));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* update horizontal start/stop */
pLayerCfg->WindowX0 = X0;
pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
/* update vertical start/stop */
pLayerCfg->WindowY0 = Y0;
pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Reconfigure the pixel format.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Pixelformat new pixel format value.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Check the parameters */
assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Reconfigure the pixel format */
pLayerCfg->PixelFormat = Pixelformat;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Reconfigure the layer alpha value.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Alpha new alpha value.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Check the parameters */
assert_param(IS_LTDC_ALPHA(Alpha));
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Reconfigure the Alpha value */
pLayerCfg->Alpha = Alpha;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Reconfigure the frame buffer Address.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Address new address value.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Reconfigure the Address */
pLayerCfg->FBStartAdress = Address;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width
* that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to
* layer for which we want to read and display on screen only a portion 320x240 taken in the center
* of the buffer.
* The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous
* call to HAL_LTDC_ConfigLayer().
* @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default
* pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
* @param LayerIdx LTDC layer index concerned by the modification of line pitch.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
{
uint32_t tmp;
uint32_t pitchUpdate;
uint32_t pixelFormat;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* get LayerIdx used pixel format */
pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
tmp = 4U;
}
else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
{
tmp = 3U;
}
else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
(pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
(pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
(pixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
tmp = 2U;
}
else
{
tmp = 1U;
}
pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
/* Clear previously set standard pitch */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
/* Set the Reload type as immediate update of LTDC pitch configured above */
LTDC->SRCR |= LTDC_SRCR_IMR;
/* Set new line pitch value */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
/* Set the Reload type as immediate update of LTDC pitch configured above */
LTDC->SRCR |= LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Define the position of the line interrupt.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Line Line Interrupt Position.
* @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
{
/* Check the parameters */
assert_param(IS_LTDC_LIPOS(Line));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Disable the Line interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
/* Set the Line Interrupt position */
LTDC->LIPCR = (uint32_t)Line;
/* Enable the Line interrupt */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI);
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Reload LTDC Layers configuration.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param ReloadType This parameter can be one of the following values :
* LTDC_RELOAD_IMMEDIATE : Immediate Reload
* LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking
* @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
{
/* Check the parameters */
assert_param(IS_LTDC_RELOAD(ReloadType));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Enable the Reload interrupt */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);
/* Apply Reload type */
hltdc->Instance->SRCR = ReloadType;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Configure the LTDC Layer according to the specified without reloading
* parameters in the LTDC_InitTypeDef and create the associated handle.
* Variant of the function HAL_LTDC_ConfigLayer without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
* the configuration information for the Layer.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha));
assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Set the LTDC window size without reloading.
* Variant of the function HAL_LTDC_SetWindowSize without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param XSize LTDC Pixel per line
* @param YSize LTDC Line number
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Check the parameters (Layers parameters)*/
assert_param(IS_LTDC_LAYER(LayerIdx));
assert_param(IS_LTDC_CFBLL(XSize));
assert_param(IS_LTDC_CFBLNBR(YSize));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* update horizontal stop */
pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
/* update vertical stop */
pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
/* Reconfigures the color frame buffer pitch in byte */
pLayerCfg->ImageWidth = XSize;
/* Reconfigures the frame buffer line number */
pLayerCfg->ImageHeight = YSize;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Set the LTDC window position without reloading.
* Variant of the function HAL_LTDC_SetWindowPosition without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param X0 LTDC window X offset
* @param Y0 LTDC window Y offset
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
assert_param(IS_LTDC_CFBLL(X0));
assert_param(IS_LTDC_CFBLNBR(Y0));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* update horizontal start/stop */
pLayerCfg->WindowX0 = X0;
pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
/* update vertical start/stop */
pLayerCfg->WindowY0 = Y0;
pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Reconfigure the pixel format without reloading.
* Variant of the function HAL_LTDC_SetPixelFormat without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains
* the configuration information for the LTDC.
* @param Pixelformat new pixel format value.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Check the parameters */
assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Reconfigure the pixel format */
pLayerCfg->PixelFormat = Pixelformat;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Reconfigure the layer alpha value without reloading.
* Variant of the function HAL_LTDC_SetAlpha without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Alpha new alpha value.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Check the parameters */
assert_param(IS_LTDC_ALPHA(Alpha));
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Reconfigure the Alpha value */
pLayerCfg->Alpha = Alpha;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Reconfigure the frame buffer Address without reloading.
* Variant of the function HAL_LTDC_SetAddress without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Address new address value.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Reconfigure the Address */
pLayerCfg->FBStartAdress = Address;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width
* that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to
* layer for which we want to read and display on screen only a portion 320x240 taken in the center
* of the buffer.
* The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by
* previous call to HAL_LTDC_ConfigLayer().
* @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default
* pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
* Variant of the function HAL_LTDC_SetPitch without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
* @param LayerIdx LTDC layer index concerned by the modification of line pitch.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
{
uint32_t tmp;
uint32_t pitchUpdate;
uint32_t pixelFormat;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* get LayerIdx used pixel format */
pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
tmp = 4U;
}
else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
{
tmp = 3U;
}
else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
(pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
(pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
(pixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
tmp = 2U;
}
else
{
tmp = 1U;
}
pitchUpdate = ((LinePitchInPixels * tmp) << 16U);
/* Clear previously set standard pitch */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
/* Set new line pitch value */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Configure the color keying without reloading.
* Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param RGBValue the color key value
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Configure the default color values */
LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Enable the color keying without reloading.
* Variant of the function HAL_LTDC_EnableColorKeying without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Enable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Disable the color keying without reloading.
* Variant of the function HAL_LTDC_DisableColorKeying without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Disable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Enable the color lookup table without reloading.
* Variant of the function HAL_LTDC_EnableCLUT without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Disable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Disable the color lookup table without reloading.
* Variant of the function HAL_LTDC_DisableCLUT without immediate reload.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Disable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the LTDC handle state.
(+) Get the LTDC handle error code.
@endverbatim
* @{
*/
/**
* @brief Return the LTDC handle state.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL state
*/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
{
return hltdc->State;
}
/**
* @brief Return the LTDC handle error code.
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval LTDC Error Code
*/
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc)
{
return hltdc->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup LTDC_Private_Functions LTDC Private Functions
* @{
*/
/**
* @brief Configure the LTDC peripheral
* @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param pLayerCfg Pointer LTDC Layer Configuration structure
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval None
*/
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
uint32_t tmp;
uint32_t tmp1;
uint32_t tmp2;
/* Configure the horizontal start and stop position */
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
/* Configure the vertical start and stop position */
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
/* Specifies the pixel format */
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
/* Configure the default color values */
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
tmp2 = (pLayerCfg->Alpha0 << 24U);
LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED |
LTDC_LxDCCR_DCALPHA);
LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
/* Specifies the constant alpha value */
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
/* Specifies the blending factors */
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
/* Configure the color frame buffer start address */
LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
tmp = 4U;
}
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
{
tmp = 3U;
}
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
tmp = 2U;
}
else
{
tmp = 1U;
}
/* Configure the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \
(((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
/* Configure the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
/* Enable LTDC_Layer by setting LEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
}
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC */
#endif /* HAL_LTDC_MODULE_ENABLED */
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ltdc.c
|
C
|
apache-2.0
| 72,189
|
/**
******************************************************************************
* @file stm32u5xx_hal_ltdc_ex.c
* @author MCD Application Team
* @brief LTDC Extension HAL module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
#if defined (LTDC) && defined (DSI)
/** @defgroup LTDCEx LTDCEx
* @brief LTDC HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
* @{
*/
/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the LTDC
@endverbatim
* @{
*/
/**
* @brief Retrieve common parameters from DSI Video mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
* the DSI video mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarity is inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \
DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
VidCfg->VerticalActive - 1U;
hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
return HAL_OK;
}
/**
* @brief Retrieve common parameters from DSI Adapted command mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarities are inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \
DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC && DSI */
#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ltdc_ex.c
|
C
|
apache-2.0
| 6,079
|
/**
******************************************************************************
* @file stm32u5xx_hal_mdf.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* functionalities of the Multi-function Digital Filter (MDF)
* peripheral:
* + Initialization and de-initialization
* + Acquisition
* + Clock absence detection
* + Short circuit detection
* + Out-off limit detection
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** Initialization and de-initialization ***
============================================
[..]
(#) User has first to initialize MDF or ADF instance.
(#) As prerequisite, fill in the HAL_MDF_MspInit() :
(++) Enable MDFz or ADFz clock interface with __HAL_RCC_MDFz_CLK_ENABLE()
or __HAL_RCC_ADFz_CLK_ENABLE().
(++) Enable the clocks for the used GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
(++) Configure these pins in alternate mode using HAL_GPIO_Init().
(++) If interrupt mode is used, enable and configure MDFz_FLTx or ADFz
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(++) If DMA mode is used, initialize and configure DMA.
(#) Configure the common parameters (only for first MDF or ADF instance init),
serial interface parameters and filter bitstream selection by calling
HAL_MDF_Init() function.
[..]
(#) User can de-initialize MDF or ADF instance with HAL_MDF_DeInit() function.
*** Acquisition ***
===================
[..]
(#) Configure filter parameters and start acquisition using HAL_MDF_AcqStart(),
HAL_MDF_AcqStart_IT() or HAL_MDF_AcqStart_DMA().
(#) In polling mode :
(++) Use HAL_MDF_PollForAcq() to detect the end of acquisition.
Use HAL_MDF_GetAcqValue to get acquisition value.
(++) Only for MDF instance, use HAL_MDF_PollForSnapshotAcq() to detect
the end of snapshot acquisition.
Use HAL_MDF_GetSnapshotAcqValue to get snapshot acquisition value.
(++) Only for ADF instance, use HAL_MDF_PollForSndLvl() to detect and get
new sound level value and ambient noise value.
(++) Only for ADF instance, use HAL_MDF_PollForSad() to detect sound activity.
(#) In interrupt mode :
(++) HAL_MDF_AcqCpltCallback() will be called at the end of acquisition.
Use HAL_MDF_GetAcqValue to get acquisition value or use
HAL_MDF_GetSnapshotAcqValue to get snapshot acquisition value.
(++) Only for ADF instance, HAL_MDF_SndLvlCallback() will be called when new
sound level and ambient noise values are available.
(++) Only for ADF instance, HAL_MDF_SadCallback() will be called when
sound activity detection occurs.
(++) HAL_MDF_ErrorCallback() will be called if overflow, filter overrun or
saturation occurs.
Use HAL_MDF_GetErrorCode() to get the corresponding error.
(#) In DMA mode :
(++) HAL_MDF_AcqHalfCpltCallback() and HAL_MDF_AcqCpltCallback() will be called
respectively at the half acquisition and at the acquisition complete.
(++) Only for ADF instance, HAL_MDF_SndLvlCallback() will be called when new
sound level and ambient noise values are available.
(++) Only for ADF instance, HAL_MDF_SadCallback() will be called when
sound activity detection occurs.
(++) HAL_MDF_ErrorCallback() will be called if overflow, filter overrun,
saturation or DMA error occurs.
Use HAL_MDF_GetErrorCode() to get the corresponding error.
(#) Use HAL_MDF_GenerateTrgo() to generate pulse on TRGO signal.
(#) During acquisition, use HAL_MDF_SetDelay() and HAL_MDF_GetDelay() to respectively
set and get the delay on data source.
(#) During acquisition, use HAL_MDF_SetGain() and HAL_MDF_GetGain() to respectively
set and get the filter gain.
(#) During acquisition, use HAL_MDF_SetOffset() and HAL_MDF_GetOffset() to respectively
set and get the filter offset error compensation.
(#) During acquisition, only for MDF instance, use HAL_MDF_SetOffset() and HAL_MDF_GetOffset()
to respectively set and get the filter offset error compensation.
(#) Stop acquisition using HAL_MDF_AcqStop(), HAL_MDF_AcqStop_IT() or HAL_MDF_AcqStop_DMA().
*** Clock absence detection ***
===============================
[..]
(#) Clock absence detection is always enabled so no need to start clock absence detection
in polling mode.
Use HAL_MDF_CkabStart_IT() to start clock absence detection in interrupt mode.
(#) In polling mode, use HAL_MDF_PollForCkab() to detect the clock absence.
(#) In interrupt mode, HAL_MDF_ErrorCallback() will be called if clock absence detection
occurs.
Use HAL_MDF_GetErrorCode() to get the corresponding error.
(#) Stop clock absence detection in interrupt mode using HAL_MDF_CkabStop_IT().
*** Short circuit detection ***
===============================
[..]
(#) Only for MDF instance, start short circuit detection using HAL_MDF_ScdStart()
or HAL_MDF_ScdStart_IT().
(#) In polling mode, use HAL_MDF_PollForScd() to detect short circuit.
(#) In interrupt mode, HAL_MDF_ErrorCallback() will be called if short circuit detection
occurs.
Use HAL_MDF_GetErrorCode() to get the corresponding error.
(#) Stop short circuit detection using HAL_MDF_ScdStop() or HAL_MDF_ScdStop_IT().
*** Out-off limit detection ***
===============================
[..]
(#) Only for MDF instance, start out-off limit detection using HAL_MDF_OldStart()
or HAL_MDF_OldStart_IT().
(#) In polling mode, use HAL_MDF_PollForOld() to detect out-off limit and to get threshold
information.
(#) In interrupt mode, HAL_MDF_OldCallback() will be called if out-off limit detection occurs.
(#) Stop out-off limit detection using HAL_MDF_OldStop() or HAL_MDF_OldStop_IT().
*** generic functions ***
=========================
[..]
(#) HAL_MDF_IRQHandler will be called when MDF or ADF interrupt occurs.
(#) HAL_MDF_ErrorCallback will be called when MDF or ADF error occurs.
(#) Use HAL_MDF_GetState() to get the current MDF or ADF instance state.
(#) Use HAL_MDF_GetErrorCode() to get the current MDF or ADF instance error code.
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_MDF_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions HAL_MDF_RegisterCallback(), HAL_MDF_RegisterOldCallback()
or HAL_MDF_RegisterSndLvlCallback() to register a user callback.
[..]
Function HAL_MDF_RegisterCallback() allows to register following callbacks :
(+) AcqCpltCallback : Acquisition complete callback.
(+) AcqHalfCpltCallback : Acquisition half complete callback.
(+) SadCallback : Sound activity detection callback (only for ADF instance).
(+) ErrorCallback : Error callback.
(+) MspInitCallback : MSP init callback.
(+) MspDeInitCallback : MSP de-init callback.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
For MDF instance and for specific out-off limit detection callback use dedicated
register callback :
HAL_MDF_RegisterOldCallback().
[..]
For ADF instance and for specific sound level callback use dedicated register callback :
HAL_MDF_RegisterSndLvlCallback().
[..]
Use function HAL_MDF_UnRegisterCallback() to reset a callback to the default weak function.
[..]
HAL_MDF_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID.
[..]
This function allows to reset following callbacks :
(+) AcqCpltCallback : Acquisition complete callback.
(+) AcqHalfCpltCallback : Acquisition half complete callback.
(+) SadCallback : Sound activity detection callback (only for ADF instance).
(+) ErrorCallback : Error callback.
(+) MspInitCallback : MSP init callback.
(+) MspDeInitCallback : MSP de-init callback.
[..]
For MDF instance and for specific out-off limit detection callback use dedicated
unregister callback :
HAL_MDF_UnRegisterOldCallback().
[..]
For ADF instance and for specific sound level callback use dedicated unregister callback :
HAL_MDF_UnRegisterSndLvlCallback().
[..]
By default, after the call of init function and if the state is RESET
all callbacks are reset to the corresponding legacy weak functions :
examples HAL_MDF_AcqCpltCallback(), HAL_MDF_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak functions in the init and de-init only when these
callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the init and de-init keep and use
the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the init/de-init.
In that case first register the MspInit/MspDeInit user callbacks using
HAL_MDF_RegisterCallback() before calling init or de-init function.
[..]
When the compilation define USE_HAL_MDF_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak callbacks are used.
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup MDF MDF
* @brief MDF HAL module driver
* @{
*/
#ifdef HAL_MDF_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/** @defgroup MDF_Private_Typedefs MDF Private Typedefs
* @{
*/
/**
* @}
*/
/* Private define ------------------------------------------------------------*/
/** @defgroup MDF_Private_Constants MDF Private Constants
* @{
*/
#define MDF_INSTANCE_NUMBER 7U /* 6 instances for MDF1 and 1 instance for ADF1 */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup MDF_Private_Variables MDF Private Variables
* @{
*/
static uint32_t v_mdf1InstanceCounter = 0U;
static uint32_t v_adf1InstanceCounter = 0U;
static MDF_HandleTypeDef *a_mdfHandle[MDF_INSTANCE_NUMBER] = {NULL};
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup MDF_Private_Functions MDF Private Functions
* @{
*/
static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const pInstance);
static void MDF_AcqStart(MDF_HandleTypeDef *const hmdf, const MDF_FilterConfigTypeDef *const pFilterConfig);
static void MDF_DmaXferCpltCallback(DMA_HandleTypeDef *hdma);
static void MDF_DmaXferHalfCpltCallback(DMA_HandleTypeDef *hdma);
static void MDF_DmaErrorCallback(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup MDF_Exported_Functions MDF Exported Functions
* @{
*/
/** @defgroup MDF_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to :
(+) Initialize the MDF or ADF instance.
(+) De-initialize the MDF or ADF instance.
(+) Register and unregister callbacks.
@endverbatim
* @{
*/
/**
* @brief Initialize the MDF instance according to the specified parameters
* in the MDF_InitTypeDef structure and initialize the associated handle.
* @param hmdf MDF handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_Init(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check MDF handle */
if (hmdf == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check parameters */
assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance));
assert_param(IS_MDF_FILTER_BITSTREAM(hmdf->Init.FilterBistream));
assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.SerialInterface.Activation));
/* Check that instance has not been already initialized */
if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] != NULL)
{
status = HAL_ERROR;
}
else
{
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
/* Reset callback pointers to the weak predefined callbacks */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
hmdf->OldCallback = NULL;
hmdf->SndLvCallback = HAL_MDF_SndLvlCallback;
hmdf->SadCallback = HAL_MDF_SadCallback;
}
else /* MDF instance */
{
hmdf->OldCallback = HAL_MDF_OldCallback;
hmdf->SndLvCallback = NULL;
hmdf->SadCallback = NULL;
}
hmdf->AcqCpltCallback = HAL_MDF_AcqCpltCallback;
hmdf->AcqHalfCpltCallback = HAL_MDF_AcqHalfCpltCallback;
hmdf->ErrorCallback = HAL_MDF_ErrorCallback;
/* Call MDF MSP init function */
if (hmdf->MspInitCallback == NULL)
{
hmdf->MspInitCallback = HAL_MDF_MspInit;
}
hmdf->MspInitCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
/* Call MDF MSP init function */
HAL_MDF_MspInit(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
/* Configure common parameters only for first MDF or ADF instance */
if (((v_mdf1InstanceCounter == 0U) && IS_MDF_INSTANCE(hmdf->Instance)) ||
((v_adf1InstanceCounter == 0U) && IS_ADF_INSTANCE(hmdf->Instance)))
{
MDF_TypeDef *mdfBase;
/* Get MDF base according instance */
mdfBase = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1;
/* Check clock generator status */
if ((mdfBase->CKGCR & MDF_CKGCR_CCKACTIVE) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Configure number of interleaved filters for MDF instance */
if (IS_MDF_INSTANCE(hmdf->Instance))
{
assert_param(IS_MDF_INTERLEAVED_FILTERS(hmdf->Init.CommonParam.InterleavedFilters));
mdfBase->GCR &= ~(MDF_GCR_ILVNB);
mdfBase->GCR |= (hmdf->Init.CommonParam.InterleavedFilters << MDF_GCR_ILVNB_Pos);
}
/* Configure processing clock divider, output clock divider,
output clock pins and output clock generation trigger */
assert_param(IS_MDF_PROC_CLOCK_DIVIDER(hmdf->Init.CommonParam.ProcClockDivider));
assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.CommonParam.OutputClock.Activation));
mdfBase->CKGCR = 0U;
mdfBase->CKGCR |= ((hmdf->Init.CommonParam.ProcClockDivider - 1U) << MDF_CKGCR_PROCDIV_Pos);
if (hmdf->Init.CommonParam.OutputClock.Activation == ENABLE)
{
assert_param(IS_MDF_OUTPUT_CLOCK_PINS(hmdf->Init.CommonParam.OutputClock.Pins));
assert_param(IS_MDF_OUTPUT_CLOCK_DIVIDER(hmdf->Init.CommonParam.OutputClock.Divider));
assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.CommonParam.OutputClock.Trigger.Activation));
mdfBase->CKGCR |= (((hmdf->Init.CommonParam.OutputClock.Divider - 1U) << MDF_CKGCR_CCKDIV_Pos) |
hmdf->Init.CommonParam.OutputClock.Pins |
(hmdf->Init.CommonParam.OutputClock.Pins >> 4U));
if (hmdf->Init.CommonParam.OutputClock.Trigger.Activation == ENABLE)
{
if (IS_MDF_INSTANCE(hmdf->Instance))
{
assert_param(IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(hmdf->Init.CommonParam.OutputClock.Trigger.Source));
}
else /* ADF instance */
{
assert_param(IS_ADF_OUTPUT_CLOCK_TRIGGER_SOURCE(hmdf->Init.CommonParam.OutputClock.Trigger.Source));
}
assert_param(IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(hmdf->Init.CommonParam.OutputClock.Trigger.Edge));
mdfBase->CKGCR |= (hmdf->Init.CommonParam.OutputClock.Trigger.Source |
hmdf->Init.CommonParam.OutputClock.Trigger.Edge |
MDF_CKGCR_CKGMOD);
}
}
/* Activate clock generator */
mdfBase->CKGCR |= MDF_CKGCR_CKDEN;
}
}
/* Configure serial interface */
if ((status == HAL_OK) && (hmdf->Init.SerialInterface.Activation == ENABLE))
{
/* Check serial interface status */
if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U)
{
status = HAL_ERROR;
}
else
{
/* Configure mode, clock source and threshold */
assert_param(IS_MDF_SITF_MODE(hmdf->Init.SerialInterface.Mode));
assert_param(IS_MDF_SITF_CLOCK_SOURCE(hmdf->Init.SerialInterface.ClockSource));
assert_param(IS_MDF_SITF_THRESHOLD(hmdf->Init.SerialInterface.Threshold));
hmdf->Instance->SITFCR = 0U;
hmdf->Instance->SITFCR |= ((hmdf->Init.SerialInterface.Threshold << MDF_SITFCR_STH_Pos) |
hmdf->Init.SerialInterface.Mode | hmdf->Init.SerialInterface.ClockSource);
/* Activate serial interface */
hmdf->Instance->SITFCR |= MDF_SITFCR_SITFEN;
}
}
if (status == HAL_OK)
{
/* Configure filter bitstream */
hmdf->Instance->BSMXCR &= ~(MDF_BSMXCR_BSSEL);
hmdf->Instance->BSMXCR |= hmdf->Init.FilterBistream;
/* Update instance counter and table */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
v_adf1InstanceCounter++;
}
else /* MDF instance */
{
v_mdf1InstanceCounter++;
}
a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] = hmdf;
/* Update error code and state */
hmdf->ErrorCode = MDF_ERROR_NONE;
hmdf->State = HAL_MDF_STATE_READY;
}
}
}
/* Return function status */
return status;
}
/**
* @brief De-initialize the MDF instance.
* @param hmdf MDF handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_DeInit(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check MDF handle */
if (hmdf == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check parameters */
assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance));
/* Check that instance has not been already deinitialized */
if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] == NULL)
{
status = HAL_ERROR;
}
else
{
if (IS_MDF_INSTANCE(hmdf->Instance))
{
/* Disable short circuit detector if needed */
if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != 0U)
{
hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN);
}
/* Disable out-off limit detector if needed */
if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U)
{
hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN);
}
}
/* Disable sound activity detector if needed */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
{
hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
}
}
/* Disable filter if needed */
if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
{
hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
}
/* Disable serial interface if needed */
if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U)
{
hmdf->Instance->SITFCR &= ~(MDF_SITFCR_SITFEN);
}
/* Disable all interrupts and clear all pending flags */
hmdf->Instance->DFLTIER = 0U;
hmdf->Instance->DFLTISR = 0xFFFFFFFFU;
/* Disable clock generator only for last MDF or ADF instance deinitialization */
if (((v_mdf1InstanceCounter == 1U) && IS_MDF_INSTANCE(hmdf->Instance)) ||
((v_adf1InstanceCounter == 1U) && IS_ADF_INSTANCE(hmdf->Instance)))
{
MDF_TypeDef *p_mdf_base;
/* Get MDF base according instance */
p_mdf_base = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1;
/* Disable clock generator */
p_mdf_base->CKGCR &= ~(MDF_CKGCR_CKDEN);
}
/* Call MDF MSP deinit function */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
if (hmdf->MspDeInitCallback == NULL)
{
hmdf->MspDeInitCallback = HAL_MDF_MspDeInit;
}
hmdf->MspDeInitCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_MspDeInit(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
/* Update instance counter and table */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
v_adf1InstanceCounter--;
}
else /* MDF instance */
{
v_mdf1InstanceCounter--;
}
a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] = (MDF_HandleTypeDef *) NULL;
/* Update state */
hmdf->State = HAL_MDF_STATE_RESET;
}
}
/* Return function status */
return status;
}
/**
* @brief Initialize the MDF instance MSP.
* @param hmdf MDF handle.
* @retval None.
*/
__weak void HAL_MDF_MspInit(MDF_HandleTypeDef *hmdf)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdf);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_MDF_MspInit could be implemented in the user file */
}
/**
* @brief De-initialize the MDF instance MSP.
* @param hmdf MDF handle.
* @retval None.
*/
__weak void HAL_MDF_MspDeInit(MDF_HandleTypeDef *hmdf)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdf);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_MDF_MspDeInit could be implemented in the user file */
}
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
/**
* @brief Register a user MDF callback to be used instead of the weak predefined callback.
* @param hmdf MDF handle.
* @param CallbackID ID of the callback to be registered.
* This parameter can be one of the following values:
* @arg @ref HAL_MDF_ACQ_COMPLETE_CB_ID acquisition complete callback ID.
* @arg @ref HAL_MDF_ACQ_HALFCOMPLETE_CB_ID acquisition half complete callback ID.
* @arg @ref HAL_MDF_SAD_CB_ID sound activity detector callback ID (only for ADF instance).
* @arg @ref HAL_MDF_ERROR_CB_ID error callback ID.
* @arg @ref HAL_MDF_MSPINIT_CB_ID MSP init callback ID.
* @arg @ref HAL_MDF_MSPDEINIT_CB_ID MSP de-init callback ID.
* @param pCallback pointer to the callback function.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_RegisterCallback(MDF_HandleTypeDef *hmdf,
HAL_MDF_CallbackIDTypeDef CallbackID,
pMDF_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pCallback == NULL)
{
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
else
{
if (hmdf->State == HAL_MDF_STATE_READY)
{
switch (CallbackID)
{
case HAL_MDF_ACQ_COMPLETE_CB_ID :
hmdf->AcqCpltCallback = pCallback;
break;
case HAL_MDF_ACQ_HALFCOMPLETE_CB_ID :
hmdf->AcqHalfCpltCallback = pCallback;
break;
case HAL_MDF_SAD_CB_ID :
hmdf->SadCallback = pCallback;
break;
case HAL_MDF_ERROR_CB_ID :
hmdf->ErrorCallback = pCallback;
break;
case HAL_MDF_MSPINIT_CB_ID :
hmdf->MspInitCallback = pCallback;
break;
case HAL_MDF_MSPDEINIT_CB_ID :
hmdf->MspDeInitCallback = pCallback;
break;
default :
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else if (hmdf->State == HAL_MDF_STATE_RESET)
{
switch (CallbackID)
{
case HAL_MDF_MSPINIT_CB_ID :
hmdf->MspInitCallback = pCallback;
break;
case HAL_MDF_MSPDEINIT_CB_ID :
hmdf->MspDeInitCallback = pCallback;
break;
default :
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
}
/* Return function status */
return status;
}
/**
* @brief Unregister a user MDF callback.
* MDF callback is redirected to the weak predefined callback.
* @param hmdf MDF handle.
* @param CallbackID ID of the callback to be unregistered.
* This parameter can be one of the following values:
* @arg @ref HAL_MDF_ACQ_COMPLETE_CB_ID acquisition complete callback ID.
* @arg @ref HAL_MDF_ACQ_HALFCOMPLETE_CB_ID acquisition half complete callback ID.
* @arg @ref HAL_MDF_SAD_CB_ID sound activity detector callback ID (only for ADF instance).
* @arg @ref HAL_MDF_ERROR_CB_ID error callback ID.
* @arg @ref HAL_MDF_MSPINIT_CB_ID MSP init callback ID.
* @arg @ref HAL_MDF_MSPDEINIT_CB_ID MSP de-init callback ID.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_UnRegisterCallback(MDF_HandleTypeDef *hmdf,
HAL_MDF_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (hmdf->State == HAL_MDF_STATE_READY)
{
switch (CallbackID)
{
case HAL_MDF_ACQ_COMPLETE_CB_ID :
hmdf->AcqCpltCallback = HAL_MDF_AcqCpltCallback;
break;
case HAL_MDF_ACQ_HALFCOMPLETE_CB_ID :
hmdf->AcqHalfCpltCallback = HAL_MDF_AcqHalfCpltCallback;
break;
case HAL_MDF_SAD_CB_ID :
hmdf->SadCallback = HAL_MDF_SadCallback;
break;
case HAL_MDF_ERROR_CB_ID :
hmdf->ErrorCallback = HAL_MDF_ErrorCallback;
break;
case HAL_MDF_MSPINIT_CB_ID :
hmdf->MspInitCallback = HAL_MDF_MspInit;
break;
case HAL_MDF_MSPDEINIT_CB_ID :
hmdf->MspDeInitCallback = HAL_MDF_MspDeInit;
break;
default :
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else if (hmdf->State == HAL_MDF_STATE_RESET)
{
switch (CallbackID)
{
case HAL_MDF_MSPINIT_CB_ID :
hmdf->MspInitCallback = HAL_MDF_MspInit;
break;
case HAL_MDF_MSPDEINIT_CB_ID :
hmdf->MspDeInitCallback = HAL_MDF_MspDeInit;
break;
default :
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @brief Register specific MDF out-off limit detector callback
* to be used instead of the weak predefined callback.
* @param hmdf MDF handle.
* @param pCallback pointer to the out-off limit detector callback function.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_RegisterOldCallback(MDF_HandleTypeDef *hmdf,
pMDF_OldCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pCallback == NULL)
{
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
else
{
if (hmdf->State == HAL_MDF_STATE_READY)
{
hmdf->OldCallback = pCallback;
}
else
{
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
}
/* Return function status */
return status;
}
/**
* @brief Unregister the specific MDF out-off limit detector callback.
* MDF out-off limit detector callback is redirected to the weak predefined callback.
* @param hmdf MDF handle.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_UnRegisterOldCallback(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
if (hmdf->State == HAL_MDF_STATE_READY)
{
hmdf->OldCallback = HAL_MDF_OldCallback;
}
else
{
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @brief Register specific MDF sound level callback
* to be used instead of the weak predefined callback.
* @param hmdf MDF handle.
* @param pCallback pointer to the sound level callback function.
* @retval HAL status.
* @note This function must not be used with MDF instance.
*/
HAL_StatusTypeDef HAL_MDF_RegisterSndLvlCallback(MDF_HandleTypeDef *hmdf,
pMDF_SndLvlCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pCallback == NULL)
{
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
else
{
if (hmdf->State == HAL_MDF_STATE_READY)
{
hmdf->SndLvCallback = pCallback;
}
else
{
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
}
/* Return function status */
return status;
}
/**
* @brief Unregister the specific MDF sound level callback.
* MDF sound level callback is redirected to the weak predefined callback.
* @param hmdf MDF handle.
* @retval HAL status.
* @note This function must not be used with MDF instance.
*/
HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
if (hmdf->State == HAL_MDF_STATE_READY)
{
hmdf->SndLvCallback = HAL_MDF_SndLvlCallback;
}
else
{
/* Update error code and status */
hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
/* Return function status */
return status;
}
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup MDF_Exported_Functions_Group2 Acquisition functions
* @brief Acquisition functions
*
@verbatim
==============================================================================
##### Acquisition functions #####
==============================================================================
[..] This section provides functions allowing to :
(+) Start and stop acquisition in polling, interrupt or DMA mode.
(+) Wait and get acquisition values.
(+) Generate pulse on TRGO signal.
(+) Modify and get some filter parameters during acquisition.
(+) Wait and get sound level values for ADF instance.
(+) Detect sound activity for ADF instance.
@endverbatim
* @{
*/
/**
* @brief This function allows to start acquisition in polling mode.
* @param hmdf MDF handle.
* @param pFilterConfig Filter configuration parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pFilterConfig == NULL)
{
status = HAL_ERROR;
}
else
{
if (IS_ADF_INSTANCE(hmdf->Instance))
{
assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
}
else
{
assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
}
if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) &&
((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) ||
(pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) ||
(pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT)))
{
status = HAL_ERROR;
}
/* Check state */
else if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
/* Check filter status */
else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
{
status = HAL_ERROR;
}
else
{
/* For ADF instance, check SAD status */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
{
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
/* For MDF instance, check OLD status and main filter order */
assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode));
if (IS_MDF_INSTANCE(hmdf->Instance))
{
if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4))
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Configure filter and start acquisition */
hmdf->Instance->DFLTCR = 0U;
MDF_AcqStart(hmdf, pFilterConfig);
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to poll for available acquisition value.
* @param hmdf MDF handle.
* @param Timeout Timeout value in milliseconds.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
else
{
uint32_t tickstart = HAL_GetTick();
/* Wait for available acquisition value */
while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_RXNEF) != MDF_DFLTISR_RXNEF) && (status == HAL_OK))
{
/* Check the timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
}
}
}
/* Check if data overflow, saturation or reshape filter occurs */
uint32_t error_flags = (hmdf->Instance->DFLTISR & (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF));
if (error_flags != 0U)
{
/* Update error code */
if ((error_flags & MDF_DFLTISR_DOVRF) == MDF_DFLTISR_DOVRF)
{
hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
}
if ((error_flags & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF)
{
hmdf->ErrorCode |= MDF_ERROR_SATURATION;
}
if ((error_flags & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF)
{
hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN;
}
/* Clear corresponding flags */
hmdf->Instance->DFLTISR |= error_flags;
/* Call error callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->ErrorCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_ErrorCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
if (status == HAL_OK)
{
/* Update state only in asynchronous single shot mode */
if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_ACQMOD) == MDF_MODE_ASYNC_SINGLE)
{
hmdf->State = HAL_MDF_STATE_READY;
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to poll for available snapshot acquisition value.
* @param hmdf MDF handle.
* @param Timeout Timeout value in milliseconds.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
else
{
uint32_t tickstart = HAL_GetTick();
/* Wait for available snapshot acquisition value */
while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SSDRF) != MDF_DFLTISR_SSDRF) && (status == HAL_OK))
{
/* Check the timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
}
}
}
/* Check if snapshot overrun, saturation or reshape filter occurs */
uint32_t error_flags = (hmdf->Instance->DFLTISR & (MDF_DFLTISR_SSOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF));
if (error_flags != 0U)
{
/* Update error code */
if ((error_flags & MDF_DFLTISR_SSOVRF) == MDF_DFLTISR_SSOVRF)
{
hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
}
if ((error_flags & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF)
{
hmdf->ErrorCode |= MDF_ERROR_SATURATION;
}
if ((error_flags & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF)
{
hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN;
}
/* Clear corresponding flags */
hmdf->Instance->DFLTISR |= error_flags;
/* Call error callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->ErrorCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_ErrorCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to get acquisition value.
* @param hmdf MDF handle.
* @param pValue Acquisition value on 24 MSB.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_GetAcqValue(MDF_HandleTypeDef *hmdf, int32_t *pValue)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pValue == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
/* Get acquisition value */
*pValue = (int32_t) hmdf->Instance->DFLTDR;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to get snapshot acquisition value.
* @param hmdf MDF handle.
* @param pSnapshotParam Snapshot parameters.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_GetSnapshotAcqValue(MDF_HandleTypeDef *hmdf, MDF_SnapshotParamTypeDef *pSnapshotParam)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pSnapshotParam == NULL)
{
status = HAL_ERROR;
}
/* Check state */
else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
else
{
uint32_t snpsdr_value;
/* Read value of snapshot data register */
snpsdr_value = hmdf->Instance->SNPSDR;
/* Clear snapshot data ready flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSDRF;
/* Store value of decimation counter in snapshot parameter structure */
pSnapshotParam->DecimationCounter = (snpsdr_value & MDF_SNPSDR_MCICDC);
/* Check snapshot format */
if ((hmdf->Instance->DFLTCR & MDF_SNAPSHOT_16BITS) == MDF_SNAPSHOT_16BITS)
{
/* Store value of integrator counter in snapshot parameter structure */
pSnapshotParam->IntegratorCounter = ((snpsdr_value & MDF_SNPSDR_EXTSDR) >> MDF_SNPSDR_EXTSDR_Pos);
/* Store snapshot acquisition value (16MSB) in snapshot parameter structure */
snpsdr_value &= 0xFFFF0000U;
pSnapshotParam->Value = (int32_t) snpsdr_value;
}
else
{
/* Store snapshot acquisition value (23MSB) in snapshot parameter structure */
snpsdr_value &= 0xFFFFFE00U;
pSnapshotParam->Value = (int32_t) snpsdr_value;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to stop acquisition in polling mode.
* @param hmdf MDF handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
/* Check if state is ready and filter active */
if (hmdf->State == HAL_MDF_STATE_READY)
{
if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE)
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
}
else
{
/* Disable sound activity detector if needed for ADF instance */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
{
hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
}
}
}
if (status == HAL_OK)
{
/* Disable filter */
hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
/* Clear all potential pending flags */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF |
MDF_DFLTISR_SDDETF | MDF_DFLTISR_SDLVLF);
}
else
{
hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SSDRF | MDF_DFLTISR_SSOVRF |
MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF);
}
/* Update state */
hmdf->State = HAL_MDF_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to start acquisition in interrupt mode.
* @param hmdf MDF handle.
* @param pFilterConfig Filter configuration parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pFilterConfig == NULL)
{
status = HAL_ERROR;
}
else
{
if (IS_ADF_INSTANCE(hmdf->Instance))
{
assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
}
else
{
assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
}
if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) &&
((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) ||
(pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) ||
(pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT)))
{
status = HAL_ERROR;
}
/* Check state */
else if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
/* Check filter status */
else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
{
status = HAL_ERROR;
}
else
{
/* For ADF instance, check SAD status */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
{
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
/* For MDF instance, check OLD status and main filter order */
assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode));
if (IS_MDF_INSTANCE(hmdf->Instance))
{
if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4))
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
if (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT)
{
/* Enable snapshot overrun and data ready interrupts */
hmdf->Instance->DFLTIER |= (MDF_DFLTIER_SSOVRIE | MDF_DFLTIER_SSDRIE);
}
else
{
if ((IS_MDF_INSTANCE(hmdf->Instance)) || (pFilterConfig->SoundActivity.Activation == DISABLE) ||
(pFilterConfig->SoundActivity.DataMemoryTransfer != MDF_SAD_NO_MEMORY_TRANSFER))
{
/* Enable data overflow and fifo threshold interrupts */
hmdf->Instance->DFLTIER |= (MDF_DFLTIER_DOVRIE | MDF_DFLTIER_FTHIE);
}
}
if (pFilterConfig->ReshapeFilter.Activation == ENABLE)
{
/* Enable reshape filter overrun interrupt */
hmdf->Instance->DFLTIER |= MDF_DFLTIER_RFOVRIE;
}
/* Enable saturation interrupt */
hmdf->Instance->DFLTIER |= MDF_DFLTIER_SATIE;
if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE))
{
/* Enable sound level value ready and sound activity detection interrupts */
assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.SoundLevelInterrupt));
hmdf->Instance->DFLTIER |= (pFilterConfig->SoundActivity.SoundLevelInterrupt == ENABLE) ?
(MDF_DFLTIER_SDLVLIE | MDF_DFLTIER_SDDETIE) :
MDF_DFLTIER_SDDETIE;
}
/* Configure filter and start acquisition */
hmdf->Instance->DFLTCR = 0U;
MDF_AcqStart(hmdf, pFilterConfig);
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to stop acquisition in interrupt mode.
* @param hmdf MDF handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
/* Check if state is ready and filter active */
if (hmdf->State == HAL_MDF_STATE_READY)
{
if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE)
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
}
else
{
/* Disable sound activity detector if needed for ADF instance */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
{
hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
}
}
}
if (status == HAL_OK)
{
/* Disable filter */
hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
/* Disable interrupts and clear all potential pending flags */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_FTHIE | MDF_DFLTIER_DOVRIE | MDF_DFLTIER_SATIE |
MDF_DFLTIER_RFOVRIE | MDF_DFLTIER_SDDETIE | MDF_DFLTIER_SDLVLIE);
hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF |
MDF_DFLTISR_SDDETF | MDF_DFLTISR_SDLVLF);
}
else
{
hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_FTHIE | MDF_DFLTIER_DOVRIE | MDF_DFLTIER_SSDRIE |
MDF_DFLTIER_SSOVRIE | MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE);
hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SSDRF | MDF_DFLTISR_SSOVRF |
MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF);
}
/* Update state */
hmdf->State = HAL_MDF_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to start acquisition in DMA mode.
* @param hmdf MDF handle.
* @param pFilterConfig Filter configuration parameters.
* @param pDmaConfig DMA configuration parameters.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, MDF_FilterConfigTypeDef *pFilterConfig,
MDF_DmaConfigTypeDef *pDmaConfig)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if ((pFilterConfig == NULL) || (pDmaConfig == NULL))
{
status = HAL_ERROR;
}
else
{
assert_param(IS_FUNCTIONAL_STATE(pDmaConfig->MsbOnly));
if (IS_ADF_INSTANCE(hmdf->Instance))
{
assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
}
else
{
assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode));
}
if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) &&
((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) ||
(pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) ||
(pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT)))
{
status = HAL_ERROR;
}
else if (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT)
{
status = HAL_ERROR;
}
/* Check state */
else if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
/* Check filter status */
else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U)
{
status = HAL_ERROR;
}
else
{
/* For ADF instance, check SAD status */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
{
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
/* For MDF instance, check OLD status and main filter order */
assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode));
if (IS_MDF_INSTANCE(hmdf->Instance))
{
if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4))
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
uint32_t SrcAddress;
if (pFilterConfig->ReshapeFilter.Activation == ENABLE)
{
/* Enable reshape filter overrun interrupt */
hmdf->Instance->DFLTIER |= MDF_DFLTIER_RFOVRIE;
}
/* Enable saturation interrupt */
hmdf->Instance->DFLTIER |= MDF_DFLTIER_SATIE;
if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE))
{
/* Enable sound level value ready and sound activity detection interrupts */
assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.SoundLevelInterrupt));
hmdf->Instance->DFLTIER |= (pFilterConfig->SoundActivity.SoundLevelInterrupt == ENABLE) ?
(MDF_DFLTIER_SDLVLIE | MDF_DFLTIER_SDDETIE) :
MDF_DFLTIER_SDDETIE;
}
/* Enable MDF DMA requests */
hmdf->Instance->DFLTCR = MDF_DFLTCR_DMAEN;
/* Start DMA transfer */
hmdf->hdma->XferCpltCallback = MDF_DmaXferCpltCallback;
hmdf->hdma->XferHalfCpltCallback = MDF_DmaXferHalfCpltCallback;
hmdf->hdma->XferErrorCallback = MDF_DmaErrorCallback;
SrcAddress = (pDmaConfig->MsbOnly == ENABLE) ? (((uint32_t) &hmdf->Instance->DFLTDR) + 2U) :
(uint32_t) &hmdf->Instance->DFLTDR;
if ((hmdf->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hmdf->hdma->LinkedListQueue != NULL)
{
hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = pDmaConfig->DataLength;
hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = SrcAddress;
hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pDmaConfig->Address;
status = HAL_DMAEx_List_Start_IT(hmdf->hdma);
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_DMA_Start_IT(hmdf->hdma, SrcAddress, pDmaConfig->Address, pDmaConfig->DataLength);
}
if (status != HAL_OK)
{
/* Update state */
hmdf->State = HAL_MDF_STATE_ERROR;
status = HAL_ERROR;
}
else
{
/* Configure filter and start acquisition */
MDF_AcqStart(hmdf, pFilterConfig);
}
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to stop acquisition in DMA mode.
* @param hmdf MDF handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check if state is ready and filter active */
if (hmdf->State == HAL_MDF_STATE_READY)
{
if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE)
{
status = HAL_ERROR;
}
}
else
{
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
else
{
/* Stop the DMA transfer */
if (HAL_DMA_Abort(hmdf->hdma) != HAL_OK)
{
/* Update state */
hmdf->State = HAL_MDF_STATE_ERROR;
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
/* Disable sound activity detector if needed for ADF instance */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U)
{
hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN);
}
}
/* Disable filter */
hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN);
/* Disable interrupts and clear all potential pending flags */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE | MDF_DFLTIER_SDDETIE |
MDF_DFLTIER_SDLVLIE);
hmdf->Instance->DFLTISR |= (MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF | MDF_DFLTISR_SDDETF |
MDF_DFLTISR_SDLVLF);
}
else
{
hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE);
hmdf->Instance->DFLTISR |= (MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF);
}
/* Disable MDF DMA requests */
hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DMAEN);
/* Update state */
hmdf->State = HAL_MDF_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to generate pulse on TRGO signal.
* @param hmdf MDF handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_GenerateTrgo(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check state */
if (hmdf->State != HAL_MDF_STATE_READY)
{
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
MDF_TypeDef *p_mdf_base;
/* Get MDF base according instance */
p_mdf_base = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1;
/* Check if trigger output control is already active */
if ((p_mdf_base->GCR & MDF_GCR_TRGO) == MDF_GCR_TRGO)
{
status = HAL_ERROR;
}
else
{
/* Generate pulse on trigger output control signal */
p_mdf_base->GCR |= MDF_GCR_TRGO;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to set delay to apply on data source in number of samples.
* @param hmdf MDF handle.
* @param Delay Delay to apply on data source in number of samples.
* This parameter must be a number between Min_Data = 0 and Max_Data = 127.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_MDF_DELAY(Delay));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
else
{
/* Check if bitstream delay is already active */
if ((hmdf->Instance->DLYCR & MDF_DLYCR_SKPBF) == MDF_DLYCR_SKPBF)
{
status = HAL_ERROR;
}
else
{
/* Configure bitstream delay */
hmdf->Instance->DLYCR |= Delay;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to get current delay applied on data source in number of samples.
* @param hmdf MDF handle.
* @param pDelay Current delay applied on data source in number of samples.
* This value is between Min_Data = 0 and Max_Data = 127.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_GetDelay(MDF_HandleTypeDef *hmdf, uint32_t *pDelay)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pDelay == NULL)
{
status = HAL_ERROR;
}
/* Check state */
else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
else
{
/* Get current bitstream delay */
*pDelay = (hmdf->Instance->DLYCR & MDF_DLYCR_SKPDLY);
}
/* Return function status */
return status;
}
/**
* @brief This function allows to set filter gain.
* @param hmdf MDF handle.
* @param Gain Filter gain in step of around 3db (from -48db to 72dB).
* This parameter must be a number between Min_Data = -16 and Max_Data = 24.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_MDF_GAIN(Gain));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
else
{
uint32_t register_gain_value;
uint32_t tmp_register;
if (Gain < 0)
{
int32_t adjust_gain;
/* adjust gain value to set on register for negative value (offset of -16) */
adjust_gain = Gain - 16;
register_gain_value = ((uint32_t) adjust_gain & 0x3FU);
}
else
{
/* for positive value, no offset to apply */
register_gain_value = (uint32_t) Gain;
}
/* Set gain */
tmp_register = (hmdf->Instance->DFLTCICR & ~(MDF_DFLTCICR_SCALE));
hmdf->Instance->DFLTCICR = (tmp_register | (register_gain_value << MDF_DFLTCICR_SCALE_Pos));
}
/* Return function status */
return status;
}
/**
* @brief This function allows to get filter gain.
* @param hmdf MDF handle.
* @param pGain Filter gain in step of around 3db (from -48db to 72dB).
* This parameter is between Min_Data = -16 and Max_Data = 24.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_GetGain(MDF_HandleTypeDef *hmdf, int32_t *pGain)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pGain == NULL)
{
status = HAL_ERROR;
}
/* Check state */
else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
else
{
uint32_t register_gain_value;
/* Get current gain */
register_gain_value = ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_SCALE) >> MDF_DFLTCICR_SCALE_Pos);
if (register_gain_value > 31U)
{
/* adjust gain value to set on register for negative value (offset of +16) */
register_gain_value |= 0xFFFFFFC0U;
*pGain = (int32_t) register_gain_value + 16;
}
else
{
/* for positive value, no offset to apply */
*pGain = (int32_t) register_gain_value;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to set filter offset error compensation.
* @param hmdf MDF handle.
* @param Offset Filter offset error compensation.
* This parameter must be a number between Min_Data = -33554432 and Max_Data = 33554431.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
assert_param(IS_MDF_OFFSET(Offset));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
else
{
/* Set offset */
hmdf->Instance->OECCR = (uint32_t) Offset;
}
/* Return function status */
return status;
}
/**
* @brief This function allows to get filter offset error compensation.
* @param hmdf MDF handle.
* @param pOffset Filter offset error compensation.
* This value is between Min_Data = -33554432 and Max_Data = 33554431.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_GetOffset(MDF_HandleTypeDef *hmdf, int32_t *pOffset)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
if (pOffset == NULL)
{
status = HAL_ERROR;
}
/* Check state */
else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
else
{
uint32_t register_offset_value;
/* Get current offset */
register_offset_value = hmdf->Instance->OECCR;
if (register_offset_value > 33554431U)
{
/* Negative value */
register_offset_value |= 0xFC000000U;
*pOffset = (int32_t) register_offset_value;
}
else
{
/* Positive value */
*pOffset = (int32_t) register_offset_value;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to poll for sound level data.
* @param hmdf MDF handle.
* @param Timeout Timeout value in milliseconds.
* @param pSoundLevel Sound level.
This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
* @param pAmbientNoise Ambient noise.
This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
* @retval HAL status.
* @note This function must not be used with MDF instance.
*/
HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel,
uint32_t *pAmbientNoise)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_ADF_INSTANCE(hmdf->Instance));
if ((pSoundLevel == NULL) || (pAmbientNoise == NULL))
{
status = HAL_ERROR;
}
/* Check state */
else if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
/* Check SAD status */
else if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) == 0U)
{
status = HAL_ERROR;
}
else
{
uint32_t tickstart = HAL_GetTick();
/* Wait for available sound level data */
while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SDLVLF) != MDF_DFLTISR_SDLVLF) && (status == HAL_OK))
{
/* Check the timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
}
}
}
if (status == HAL_OK)
{
/* Get sound level */
*pSoundLevel = hmdf->Instance->SADSDLVR;
/* Get ambient noise */
*pAmbientNoise = hmdf->Instance->SADANLVR;
/* Clear sound level ready flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDLVLF;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to poll for sound activity detection.
* @param hmdf MDF handle.
* @param Timeout Timeout value in milliseconds.
* @retval HAL status.
* @note This function must not be used with MDF instance.
*/
HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_ADF_INSTANCE(hmdf->Instance));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
status = HAL_ERROR;
}
/* Check SAD status */
else if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) == 0U)
{
status = HAL_ERROR;
}
else
{
uint32_t tickstart = HAL_GetTick();
/* Wait for sound activity detection */
while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SDDETF) != MDF_DFLTISR_SDDETF) && (status == HAL_OK))
{
/* Check the timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
}
}
}
if (status == HAL_OK)
{
/* Clear sound activity detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDDETF;
}
}
/* Return function status */
return status;
}
/**
* @brief MDF acquisition complete callback.
* @param hmdf MDF handle.
* @retval None.
*/
__weak void HAL_MDF_AcqCpltCallback(MDF_HandleTypeDef *hmdf)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdf);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_MDF_AcqCpltCallback could be implemented in the user file */
}
/**
* @brief MDF acquisition half complete callback.
* @param hmdf MDF handle.
* @retval None.
*/
__weak void HAL_MDF_AcqHalfCpltCallback(MDF_HandleTypeDef *hmdf)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdf);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_MDF_AcqHalfCpltCallback could be implemented in the user file */
}
/**
* @brief MDF sound level callback.
* @param hmdf MDF handle.
* @param SoundLevel Sound level value computed by sound activity detector.
* This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
* @param AmbientNoise Ambient noise value computed by sound activity detector.
* This parameter can be a value between Min_Data = 0 and Max_Data = 32767.
* @retval None.
*/
__weak void HAL_MDF_SndLvlCallback(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdf);
UNUSED(SoundLevel);
UNUSED(AmbientNoise);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_MDF_SndLvlCallback could be implemented in the user file */
}
/**
* @brief MDF sound activity detector callback.
* @param hmdf MDF handle.
* @retval None.
*/
__weak void HAL_MDF_SadCallback(MDF_HandleTypeDef *hmdf)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdf);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_MDF_SadCallback could be implemented in the user file */
}
/**
* @}
*/
/** @defgroup MDF_Exported_Functions_Group3 Clock absence detection functions
* @brief Clock absence detection functions
*
@verbatim
==============================================================================
##### Clock absence detection functions #####
==============================================================================
[..] This section provides functions allowing to :
(+) Start and stop clock absence detection in interrupt mode.
(+) Detect clock absence.
@endverbatim
* @{
*/
/**
* @brief This function allows to poll for the clock absence detection.
* @param hmdf MDF handle.
* @param Timeout Timeout value in milliseconds.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_PollForCkab(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Check serial interface status and mode */
if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U)
{
status = HAL_ERROR;
}
else
{
if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE)
{
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
uint32_t tickstart = HAL_GetTick();
/* Wait for clock absence detection */
while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_CKABF) != MDF_DFLTISR_CKABF) && (status == HAL_OK))
{
/* Check the timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
}
}
}
if (status == HAL_OK)
{
/* Clear clock absence detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to start clock absence detection in interrupt mode.
* @param hmdf MDF handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_CkabStart_IT(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Check serial interface status and mode */
if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U)
{
status = HAL_ERROR;
}
else
{
if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE)
{
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
/* Clear clock absence detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
/* Check clock absence detection flag */
if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_CKABF) == MDF_DFLTISR_CKABF)
{
status = HAL_ERROR;
}
else
{
/* Enable clock absence detection interrupt */
hmdf->Instance->DFLTIER |= MDF_DFLTIER_CKABIE;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to stop clock absence detection in interrupt mode.
* @param hmdf MDF handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Check serial interface status and mode */
if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U)
{
status = HAL_ERROR;
}
else
{
if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE)
{
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
/* Disable clock absence detection interrupt */
hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_CKABIE);
/* Clear potential pending clock absence detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
}
/* Return function status */
return status;
}
/**
* @}
*/
/** @defgroup MDF_Exported_Functions_Group4 Short circuit detection functions
* @brief Short circuit detection functions
*
@verbatim
==============================================================================
##### Short circuit detection functions #####
==============================================================================
[..] This section provides functions available only for MDF instance
allowing to :
(+) Start and stop short circuit detection in polling and interrupt mode.
(+) Detect short circuit.
@endverbatim
* @{
*/
/**
* @brief This function allows to start short-circuit detection in polling mode.
* @param hmdf MDF handle.
* @param pScdConfig Short-circuit detector configuration parameters.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pScdConfig == NULL)
{
status = HAL_ERROR;
}
else
{
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
assert_param(IS_MDF_SCD_THRESHOLD(pScdConfig->Threshold));
assert_param(IS_MDF_BREAK_SIGNAL(pScdConfig->BreakSignal));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Check short-circuit detector status */
if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) == MDF_SCDCR_SCDACTIVE)
{
status = HAL_ERROR;
}
else
{
/* Configure threshold and break signal */
hmdf->Instance->SCDCR = (((pScdConfig->Threshold - 1U) << MDF_SCDCR_SCDT_Pos) |
(pScdConfig->BreakSignal << MDF_SCDCR_BKSCD_Pos));
/* Enable short-circuit detector */
hmdf->Instance->SCDCR |= MDF_SCDCR_SCDEN;
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to poll for the short-circuit detection.
* @param hmdf MDF handle.
* @param Timeout Timeout value in milliseconds.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_PollForScd(MDF_HandleTypeDef *hmdf, uint32_t Timeout)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Check short-circuit detector status */
if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE)
{
status = HAL_ERROR;
}
else
{
uint32_t tickstart = HAL_GetTick();
/* Wait for short-circuit detection */
while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SCDF) != MDF_DFLTISR_SCDF) && (status == HAL_OK))
{
/* Check the timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
}
}
}
if (status == HAL_OK)
{
/* Clear short-circuit detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to stop short-circuit detection in polling mode.
* @param hmdf MDF handle.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Check short-circuit detector status */
if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE)
{
status = HAL_ERROR;
}
else
{
/* Disable short-circuit detection */
hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN);
/* Clear potential pending short-circuit detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to start short-circuit detection in interrupt mode.
* @param hmdf MDF handle.
* @param pScdConfig Short-circuit detector configuration parameters.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, MDF_ScdConfigTypeDef *pScdConfig)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pScdConfig == NULL)
{
status = HAL_ERROR;
}
else
{
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
assert_param(IS_MDF_SCD_THRESHOLD(pScdConfig->Threshold));
assert_param(IS_MDF_BREAK_SIGNAL(pScdConfig->BreakSignal));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Check short-circuit detector status */
if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) == MDF_SCDCR_SCDACTIVE)
{
status = HAL_ERROR;
}
else
{
/* Configure threshold and break signal */
hmdf->Instance->SCDCR = (((pScdConfig->Threshold - 1U) << MDF_SCDCR_SCDT_Pos) |
(pScdConfig->BreakSignal << MDF_SCDCR_BKSCD_Pos));
/* Enable short-circuit detector interrupt */
hmdf->Instance->DFLTIER |= MDF_DFLTIER_SCDIE;
/* Enable short-circuit detector */
hmdf->Instance->SCDCR |= MDF_SCDCR_SCDEN;
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to stop short-circuit detection in interrupt mode.
* @param hmdf MDF handle.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Check short-circuit detector status */
if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE)
{
status = HAL_ERROR;
}
else
{
/* Disable short-circuit detection */
hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN);
/* Disable short-circuit detection interrupt */
hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SCDIE);
/* Clear potential pending short-circuit detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
}
}
/* Return function status */
return status;
}
/**
* @}
*/
/** @defgroup MDF_Exported_Functions_Group5 Out-off limit detection functions
* @brief Out-off limit detection functions
*
@verbatim
==============================================================================
##### Out-off limit detection functions #####
==============================================================================
[..] This section provides functions available only for MDF instance
allowing to :
(+) Start and stop out-off limit detection in polling and interrupt mode.
(+) Detect short circuit and get threshold information.
@endverbatim
* @{
*/
/**
* @brief This function allows to start out-off limit detection in polling mode.
* @param hmdf MDF handle.
* @param pOldConfig Out-off limit detector configuration parameters.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pOldConfig == NULL)
{
status = HAL_ERROR;
}
else
{
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
assert_param(IS_MDF_OLD_CIC_MODE(pOldConfig->OldCicMode));
assert_param(IS_MDF_OLD_DECIMATION_RATIO(pOldConfig->OldDecimationRatio));
assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->HighThreshold));
assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->LowThreshold));
assert_param(IS_MDF_OLD_EVENT_CONFIG(pOldConfig->OldEventConfig));
assert_param(IS_MDF_BREAK_SIGNAL(pOldConfig->BreakSignal));
if (pOldConfig->LowThreshold >= pOldConfig->HighThreshold)
{
status = HAL_ERROR;
}
else
{
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
/* Check out-off limit detector status */
if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) == MDF_OLDCR_OLDACTIVE)
{
status = HAL_ERROR;
}
else
{
/* Check filter status */
if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) == MDF_DFLTCR_DFLTACTIVE)
{
/* Check main filter order */
if ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_CICMOD) >= MDF_ONE_FILTER_SINC4)
{
status = HAL_ERROR;
}
}
else
{
/* Reset main filter order */
hmdf->Instance->DFLTCICR &= ~(MDF_DFLTCICR_CICMOD);
}
if (status == HAL_OK)
{
/* Configure OLD CIC mode, decimation ratio, event and break signal */
hmdf->Instance->OLDCR = (pOldConfig->OldCicMode | pOldConfig->OldEventConfig |
((pOldConfig->OldDecimationRatio - 1U) << MDF_OLDCR_ACICD_Pos) |
(pOldConfig->BreakSignal << MDF_OLDCR_BKOLD_Pos));
/* Configure low and high thresholds */
hmdf->Instance->OLDTHLR = (uint32_t) pOldConfig->LowThreshold;
hmdf->Instance->OLDTHHR = (uint32_t) pOldConfig->HighThreshold;
/* Enable out-off limit detector */
hmdf->Instance->OLDCR |= MDF_OLDCR_OLDEN;
}
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to poll for the out-off limit detection.
* @param hmdf MDF handle.
* @param Timeout Timeout value in milliseconds.
* @param pThresholdInfo Threshold information of out-off limit detection.
* This parameter can be a value of @ref MDF_OldThresholdInfo.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_PollForOld(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pThresholdInfo)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
if (pThresholdInfo == NULL)
{
status = HAL_ERROR;
}
else
{
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
/* Check out-off limit detector status */
if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE)
{
status = HAL_ERROR;
}
else
{
uint32_t tickstart = HAL_GetTick();
/* Wait for out-off limit detection */
while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_OLDF) != MDF_DFLTISR_OLDF) && (status == HAL_OK))
{
/* Check the timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_TIMEOUT;
}
}
}
if (status == HAL_OK)
{
/* Get threshold information */
if ((hmdf->Instance->DFLTISR & (MDF_DFLTISR_THLF | MDF_DFLTISR_THHF)) == 0U)
{
*pThresholdInfo = MDF_OLD_IN_THRESHOLDS;
}
else if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_THLF) == MDF_DFLTISR_THLF)
{
*pThresholdInfo = MDF_OLD_LOW_THRESHOLD;
}
else
{
*pThresholdInfo = MDF_OLD_HIGH_THRESHOLD;
}
/* Clear out-off limit detection flags */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to stop out-off limit detection in polling mode.
* @param hmdf MDF handle.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Check out-off limit detector status */
if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE)
{
status = HAL_ERROR;
}
else
{
/* Disable out-off limit detection */
hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN);
/* Clear potential pending out-off limit detection flags */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to start out-off limit detection in interrupt mode.
* @param hmdf MDF handle.
* @param pOldConfig Out-off limit detector configuration parameters.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, MDF_OldConfigTypeDef *pOldConfig)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
if (pOldConfig == NULL)
{
status = HAL_ERROR;
}
else
{
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
assert_param(IS_MDF_OLD_CIC_MODE(pOldConfig->OldCicMode));
assert_param(IS_MDF_OLD_DECIMATION_RATIO(pOldConfig->OldDecimationRatio));
assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->HighThreshold));
assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->LowThreshold));
assert_param(IS_MDF_OLD_EVENT_CONFIG(pOldConfig->OldEventConfig));
assert_param(IS_MDF_BREAK_SIGNAL(pOldConfig->BreakSignal));
if (pOldConfig->LowThreshold >= pOldConfig->HighThreshold)
{
status = HAL_ERROR;
}
else
{
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
}
if (status == HAL_OK)
{
/* Check out-off limit detector status */
if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) == MDF_OLDCR_OLDACTIVE)
{
status = HAL_ERROR;
}
else
{
/* Check filter status */
if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) == MDF_DFLTCR_DFLTACTIVE)
{
/* Check main filter order */
if ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_CICMOD) >= MDF_ONE_FILTER_SINC4)
{
status = HAL_ERROR;
}
}
else
{
/* Reset main filter order */
hmdf->Instance->DFLTCICR &= ~(MDF_DFLTCICR_CICMOD);
}
if (status == HAL_OK)
{
/* Configure OLD CIC mode, decimation ratio, event and break signal */
hmdf->Instance->OLDCR = (pOldConfig->OldCicMode | pOldConfig->OldEventConfig |
((pOldConfig->OldDecimationRatio - 1U) << MDF_OLDCR_ACICD_Pos) |
(pOldConfig->BreakSignal << MDF_OLDCR_BKOLD_Pos));
/* Configure low and high thresholds */
hmdf->Instance->OLDTHLR = (uint32_t) pOldConfig->LowThreshold;
hmdf->Instance->OLDTHHR = (uint32_t) pOldConfig->HighThreshold;
/* Enable out-off limit detector interrupt */
hmdf->Instance->DFLTIER |= MDF_DFLTIER_OLDIE;
/* Enable out-off limit detector */
hmdf->Instance->OLDCR |= MDF_OLDCR_OLDEN;
}
}
}
}
/* Return function status */
return status;
}
/**
* @brief This function allows to stop out-off limit detection in interrupt mode.
* @param hmdf MDF handle.
* @retval HAL status.
* @note This function must not be used with ADF instance.
*/
HAL_StatusTypeDef HAL_MDF_OldStop_IT(MDF_HandleTypeDef *hmdf)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check parameters */
assert_param(IS_MDF_INSTANCE(hmdf->Instance));
/* Check state */
if (hmdf->State != HAL_MDF_STATE_ACQUISITION)
{
if (hmdf->State != HAL_MDF_STATE_READY)
{
status = HAL_ERROR;
}
}
if (status == HAL_OK)
{
/* Check out-off limit detector status */
if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE)
{
status = HAL_ERROR;
}
else
{
/* Disable out-off limit detection */
hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN);
/* Disable out-off limit detector interrupt */
hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_OLDIE);
/* Clear potential pending out-off limit detection flags */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
}
}
/* Return function status */
return status;
}
/**
* @brief MDF out-off limit detector callback.
* @param hmdf MDF handle.
* @param ThresholdInfo Threshold information of out-off limit detection.
* This parameter can be a value of @ref MDF_OldThresholdInfo.
* @retval None.
*/
__weak void HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t ThresholdInfo)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdf);
UNUSED(ThresholdInfo);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_MDF_OldCallback could be implemented in the user file */
}
/**
* @}
*/
/** @defgroup MDF_Exported_Functions_Group6 Generic functions
* @brief Generic functions
*
@verbatim
==============================================================================
##### Generic functions #####
==============================================================================
[..] This section provides functions allowing to :
(+) Handle MDF interrupt.
(+) Inform user that error occurs.
(+) Get the current MDF instance state.
(+) Get the current MDF instance error code.
@endverbatim
* @{
*/
/**
* @brief This function handles the MDF interrupts.
* @param hmdf MDF handle.
* @retval None.
*/
void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf)
{
uint32_t tmp_reg1;
uint32_t tmp_reg2;
uint32_t interrupts;
/* Read current flags and interrupts and determine which ones occur */
tmp_reg1 = hmdf->Instance->DFLTIER;
tmp_reg2 = hmdf->Instance->DFLTISR;
interrupts = (tmp_reg1 & tmp_reg2);
/* Check if data overflow occurs */
if ((interrupts & MDF_DFLTISR_DOVRF) == MDF_DFLTISR_DOVRF)
{
/* Clear data overflow flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_DOVRF;
/* Update error code */
hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
/* Call error callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->ErrorCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_ErrorCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/* Check if snapshot overrun occurs */
else if ((interrupts & MDF_DFLTISR_SSOVRF) == MDF_DFLTISR_SSOVRF)
{
/* Clear snapshot overrun flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSOVRF;
/* Update error code */
hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW;
/* Call error callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->ErrorCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_ErrorCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/* Check if RXFIFO threshold occurs */
else if ((interrupts & MDF_DFLTISR_FTHF) == MDF_DFLTISR_FTHF)
{
/* Call acquisition complete callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->AcqCpltCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_AcqCpltCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
/* Update state only in asynchronous single shot mode */
if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_ACQMOD) == MDF_MODE_ASYNC_SINGLE)
{
hmdf->State = HAL_MDF_STATE_READY;
}
}
/* Check if snapshot data ready occurs */
else if ((interrupts & MDF_DFLTISR_SSDRF) == MDF_DFLTISR_SSDRF)
{
/* Clear snapshot data ready flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSDRF;
/* Call acquisition complete callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->AcqCpltCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_AcqCpltCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/* Check if reshape filter overrun occurs */
else if ((interrupts & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF)
{
/* Clear reshape filter overrun flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_RFOVRF;
/* Update error code */
hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN;
/* Call error callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->ErrorCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_ErrorCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/* Check if clock absence detection occurs */
else if ((interrupts & MDF_DFLTISR_CKABF) == MDF_DFLTISR_CKABF)
{
/* Clear clock absence detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF;
/* Update error code */
hmdf->ErrorCode |= MDF_ERROR_CLOCK_ABSENCE;
/* Call error callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->ErrorCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_ErrorCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/* Check if saturation occurs */
else if ((interrupts & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF)
{
/* Clear saturation flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SATF;
/* Update error code */
hmdf->ErrorCode |= MDF_ERROR_SATURATION;
/* Call error callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->ErrorCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_ErrorCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/* Check if short-circuit detection occurs */
else if ((interrupts & MDF_DFLTISR_SCDF) == MDF_DFLTISR_SCDF)
{
/* Clear short-circuit detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF;
/* Update error code */
hmdf->ErrorCode |= MDF_ERROR_SHORT_CIRCUIT;
/* Call error callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->ErrorCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_ErrorCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/* Check if out-off limit detection occurs */
else if ((interrupts & MDF_DFLTISR_OLDF) == MDF_DFLTISR_OLDF)
{
uint32_t threshold_info;
/* Get threshold information */
if ((hmdf->Instance->DFLTISR & (MDF_DFLTISR_THLF | MDF_DFLTISR_THHF)) == 0U)
{
threshold_info = MDF_OLD_IN_THRESHOLDS;
}
else if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_THLF) == MDF_DFLTISR_THLF)
{
threshold_info = MDF_OLD_LOW_THRESHOLD;
}
else
{
threshold_info = MDF_OLD_HIGH_THRESHOLD;
}
/* Clear out-off limit detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF;
/* Update error code */
hmdf->ErrorCode |= MDF_ERROR_OUT_OFF_LIMIT;
/* Call out-off limit detection callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->OldCallback(hmdf, threshold_info);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_OldCallback(hmdf, threshold_info);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/* Check if sound activity detection occurs */
else if ((interrupts & MDF_DFLTISR_SDDETF) == MDF_DFLTISR_SDDETF)
{
/* Clear sound activity detection flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDDETF;
/* Call sound activity detection callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->SadCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_SadCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
else
{
/* Check if sound level ready occurs */
if ((interrupts & MDF_DFLTISR_SDLVLF) == MDF_DFLTISR_SDLVLF)
{
uint32_t sound_level;
uint32_t ambient_noise;
/* Get sound level */
sound_level = hmdf->Instance->SADSDLVR;
/* Get ambient noise */
ambient_noise = hmdf->Instance->SADANLVR;
/* Clear sound level ready flag */
hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDLVLF;
/* Call sound level callback */
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->SndLvCallback(hmdf, sound_level, ambient_noise);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_SndLvlCallback(hmdf, sound_level, ambient_noise);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
}
}
/**
* @brief MDF error callback.
* @param hmdf MDF handle.
* @retval None.
*/
__weak void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdf);
/* NOTE : This function should not be modified, when the function is needed,
the HAL_MDF_ErrorCallback could be implemented in the user file */
}
/**
* @brief This function allows to get the current MDF state.
* @param hmdf MDF handle.
* @retval MDF state.
*/
HAL_MDF_StateTypeDef HAL_MDF_GetState(MDF_HandleTypeDef *hmdf)
{
/* Return MDF state */
return hmdf->State;
}
/**
* @brief This function allows to get the current MDF error.
* @param hmdf MDF handle.
* @retval MDF error code.
*/
uint32_t HAL_MDF_GetError(MDF_HandleTypeDef *hmdf)
{
/* Return MDF error code */
return hmdf->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup MDF_Private_Functions
* @brief Private functions
* @{
*/
/**
* @brief This function allows to get the handle number from instance.
* @param pInstance MDF instance.
* @retval Instance number.
*/
static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const pInstance)
{
uint32_t handle_number;
/* Get handle number from instance */
if (pInstance == MDF1_Filter0)
{
handle_number = 0U;
}
else if (pInstance == MDF1_Filter1)
{
handle_number = 1U;
}
else if (pInstance == MDF1_Filter2)
{
handle_number = 2U;
}
else if (pInstance == MDF1_Filter3)
{
handle_number = 3U;
}
else if (pInstance == MDF1_Filter4)
{
handle_number = 4U;
}
else if (pInstance == MDF1_Filter5)
{
handle_number = 5U;
}
else /* ADF1_Filter0 */
{
handle_number = 6U;
}
return handle_number;
}
/**
* @brief This function allows to configure filter and start acquisition.
* @param hmdf MDF handle.
* @param pFilterConfig Filter configuration parameters.
* @retval None.
*/
static void MDF_AcqStart(MDF_HandleTypeDef *const hmdf, const MDF_FilterConfigTypeDef *const pFilterConfig)
{
uint32_t register_gain_value;
/* Configure acquisition mode, discard samples, trigger and fifo threshold */
assert_param(IS_MDF_DISCARD_SAMPLES(pFilterConfig->DiscardSamples));
assert_param(IS_MDF_FIFO_THRESHOLD(pFilterConfig->FifoThreshold));
if ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_CONT) ||
(pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE))
{
/* Trigger parameters are not used */
hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold |
(pFilterConfig->DiscardSamples << MDF_DFLTCR_NBDIS_Pos));
}
else
{
/* Trigger parameters are used */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
assert_param(IS_ADF_TRIGGER_SOURCE(pFilterConfig->Trigger.Source));
}
else
{
assert_param(IS_MDF_TRIGGER_SOURCE(pFilterConfig->Trigger.Source));
}
assert_param(IS_MDF_TRIGGER_EDGE(pFilterConfig->Trigger.Edge));
hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold |
pFilterConfig->Trigger.Source | pFilterConfig->Trigger.Edge |
(pFilterConfig->DiscardSamples << MDF_DFLTCR_NBDIS_Pos));
}
/* Configure if needed snapshot format only for MDF instance */
if (IS_MDF_INSTANCE(hmdf->Instance) && (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT))
{
assert_param(IS_MDF_SNAPSHOT_FORMAT(pFilterConfig->SnapshotFormat));
hmdf->Instance->DFLTCR |= pFilterConfig->SnapshotFormat;
}
/* Configure data source, CIC mode, decimation ratio and gain */
if (IS_ADF_INSTANCE(hmdf->Instance))
{
assert_param(IS_ADF_DATA_SOURCE(pFilterConfig->DataSource));
assert_param(IS_ADF_CIC_MODE(pFilterConfig->CicMode));
}
else
{
assert_param(IS_MDF_DATA_SOURCE(pFilterConfig->DataSource));
}
assert_param(IS_MDF_DECIMATION_RATIO(pFilterConfig->DecimationRatio));
assert_param(IS_MDF_GAIN(pFilterConfig->Gain));
if (pFilterConfig->Gain < 0)
{
int32_t adjust_gain;
/* adjust gain value to set on register for negative value (offset of -16) */
adjust_gain = pFilterConfig->Gain - 16;
register_gain_value = ((uint32_t) adjust_gain & 0x3FU);
}
else
{
/* for positive value, no offset to apply */
register_gain_value = (uint32_t) pFilterConfig->Gain;
}
hmdf->Instance->DFLTCICR = (pFilterConfig->DataSource | pFilterConfig->CicMode |
((pFilterConfig->DecimationRatio - 1U) << MDF_DFLTCICR_MCICD_Pos) |
(register_gain_value << MDF_DFLTCICR_SCALE_Pos));
/* Configure bitstream delay */
assert_param(IS_MDF_DELAY(pFilterConfig->Delay));
hmdf->Instance->DLYCR = pFilterConfig->Delay;
/* Configure offset compensation only for MDF instance */
if (IS_MDF_INSTANCE(hmdf->Instance))
{
assert_param(IS_MDF_OFFSET(pFilterConfig->Offset));
hmdf->Instance->OECCR = (uint32_t) pFilterConfig->Offset;
}
/* Configure reshape filter */
assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->ReshapeFilter.Activation));
hmdf->Instance->DFLTRSFR = 0U;
if (pFilterConfig->ReshapeFilter.Activation == ENABLE)
{
/* Configure reshape filter decimation ratio */
assert_param(IS_MDF_RSF_DECIMATION_RATIO(pFilterConfig->ReshapeFilter.DecimationRatio));
hmdf->Instance->DFLTRSFR |= pFilterConfig->ReshapeFilter.DecimationRatio;
}
else
{
/* Bypass reshape filter */
hmdf->Instance->DFLTRSFR |= MDF_DFLTRSFR_RSFLTBYP;
}
/* Configure high-pass filter */
assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->HighPassFilter.Activation));
if (pFilterConfig->HighPassFilter.Activation == ENABLE)
{
/* Configure high-pass filter cut-off frequency */
assert_param(IS_MDF_HPF_CUTOFF_FREQ(pFilterConfig->HighPassFilter.CutOffFrequency));
hmdf->Instance->DFLTRSFR |= pFilterConfig->HighPassFilter.CutOffFrequency;
}
else
{
/* Bypass high-pass filter */
hmdf->Instance->DFLTRSFR |= MDF_DFLTRSFR_HPFBYP;
}
/* Configure integrator only for MDF instance */
if (IS_MDF_INSTANCE(hmdf->Instance))
{
assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->Integrator.Activation));
if (pFilterConfig->Integrator.Activation == ENABLE)
{
/* Configure integrator value and output division */
assert_param(IS_MDF_INTEGRATOR_VALUE(pFilterConfig->Integrator.Value));
assert_param(IS_MDF_INTEGRATOR_OUTPUT_DIV(pFilterConfig->Integrator.OutputDivision));
hmdf->Instance->DFLTINTR = (((pFilterConfig->Integrator.Value - 1U) << MDF_DFLTINTR_INTVAL_Pos) |
pFilterConfig->Integrator.OutputDivision);
}
else
{
/* Bypass integrator */
hmdf->Instance->DFLTINTR = 0U;
}
}
if (IS_ADF_INSTANCE(hmdf->Instance))
{
assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation));
if (pFilterConfig->SoundActivity.Activation == ENABLE)
{
/* Configure SAD mode, frame size, hysteresis, sound trigger event
and data memory transfer only for ADF instance */
assert_param(IS_MDF_SAD_MODE(pFilterConfig->SoundActivity.Mode));
assert_param(IS_MDF_SAD_FRAME_SIZE(pFilterConfig->SoundActivity.FrameSize));
if (pFilterConfig->SoundActivity.Mode != MDF_SAD_AMBIENT_NOISE_DETECTOR)
{
assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Hysteresis));
}
assert_param(IS_MDF_SAD_SOUND_TRIGGER(pFilterConfig->SoundActivity.SoundTriggerEvent));
assert_param(IS_MDF_SAD_DATA_MEMORY_TRANSFER(pFilterConfig->SoundActivity.DataMemoryTransfer));
if ((pFilterConfig->SoundActivity.Mode != MDF_SAD_AMBIENT_NOISE_DETECTOR) &&
(pFilterConfig->SoundActivity.Hysteresis == ENABLE))
{
hmdf->Instance->SADCR = (pFilterConfig->SoundActivity.Mode | pFilterConfig->SoundActivity.FrameSize |
MDF_SADCR_HYSTEN | pFilterConfig->SoundActivity.SoundTriggerEvent |
pFilterConfig->SoundActivity.DataMemoryTransfer);
}
else
{
hmdf->Instance->SADCR = (pFilterConfig->SoundActivity.Mode | pFilterConfig->SoundActivity.FrameSize |
pFilterConfig->SoundActivity.SoundTriggerEvent |
pFilterConfig->SoundActivity.DataMemoryTransfer);
}
/* Configure SAD minimum noise level, hangover window, learning frames,
ambient noise slope control and signal noise threshold only for ADF instance */
assert_param(IS_MDF_SAD_MIN_NOISE_LEVEL(pFilterConfig->SoundActivity.MinNoiseLevel));
assert_param(IS_MDF_SAD_HANGOVER_WINDOW(pFilterConfig->SoundActivity.HangoverWindow));
assert_param(IS_MDF_SAD_LEARNING_FRAMES(pFilterConfig->SoundActivity.LearningFrames));
assert_param(IS_MDF_SAD_SIGNAL_NOISE_THRESHOLD(pFilterConfig->SoundActivity.SignalNoiseThreshold));
if (pFilterConfig->SoundActivity.Mode != MDF_SAD_SOUND_DETECTOR)
{
assert_param(IS_MDF_SAD_AMBIENT_NOISE_SLOPE(pFilterConfig->SoundActivity.AmbientNoiseSlope));
hmdf->Instance->SADCFGR = ((pFilterConfig->SoundActivity.MinNoiseLevel << MDF_SADCFGR_ANMIN_Pos) |
pFilterConfig->SoundActivity.HangoverWindow |
pFilterConfig->SoundActivity.LearningFrames |
(pFilterConfig->SoundActivity.AmbientNoiseSlope << MDF_SADCFGR_ANSLP_Pos) |
pFilterConfig->SoundActivity.SignalNoiseThreshold);
}
else
{
hmdf->Instance->SADCFGR = ((pFilterConfig->SoundActivity.MinNoiseLevel << MDF_SADCFGR_ANMIN_Pos) |
pFilterConfig->SoundActivity.HangoverWindow |
pFilterConfig->SoundActivity.LearningFrames |
pFilterConfig->SoundActivity.SignalNoiseThreshold);
}
}
else
{
/* SAD is not used */
hmdf->Instance->SADCR = 0U;
hmdf->Instance->SADCFGR = 0U;
}
}
/* Update instance state */
hmdf->State = HAL_MDF_STATE_ACQUISITION;
/* Enable sound activity detector if needed only for ADF instance */
if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE))
{
hmdf->Instance->SADCR |= MDF_SADCR_SADEN;
}
/* Enable filter */
hmdf->Instance->DFLTCR |= MDF_DFLTCR_DFLTEN;
}
/**
* @brief This function handles DMA transfer complete callback.
* @param hdma DMA handle.
* @retval None.
*/
static void MDF_DmaXferCpltCallback(DMA_HandleTypeDef *hdma)
{
MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Check if DMA in circular mode */
if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR)
{
hmdf->State = HAL_MDF_STATE_READY;
}
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->AcqCpltCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_AcqCpltCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/**
* @brief This function handles DMA half transfer complete callback.
* @param hdma DMA handle.
* @retval None.
*/
static void MDF_DmaXferHalfCpltCallback(DMA_HandleTypeDef *hdma)
{
MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->AcqHalfCpltCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_AcqHalfCpltCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/**
* @brief This function handles DMA error callback.
* @param hdma DMA handle.
* @retval None.
*/
static void MDF_DmaErrorCallback(DMA_HandleTypeDef *hdma)
{
MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Update error code */
hmdf->ErrorCode |= MDF_ERROR_DMA;
#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1)
hmdf->ErrorCallback(hmdf);
#else /* USE_HAL_MDF_REGISTER_CALLBACKS */
HAL_MDF_ErrorCallback(hmdf);
#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */
}
/**
* @}
*/
#endif /* HAL_MDF_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mdf.c
|
C
|
apache-2.0
| 109,983
|
/**
******************************************************************************
* @file stm32u5xx_hal_mmc.c
* @author MCD Application Team
* @brief MMC card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + MMC card Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This driver implements a high level communication layer for read and write from/to
this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
the user in HAL_MMC_MspInit() function (MSP layer).
Basically, the MSP layer configuration should be the same as we provide in the
examples.
You can easily tailor this configuration according to hardware resources.
[..]
This driver is a generic layered driver for SDMMC memories which uses the HAL
SDMMC driver functions to interface with MMC and eMMC cards devices.
It is used as follows:
(#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
(##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
(##) SDMMC pins configuration for MMC card
(+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
and according to your pin assignment;
(##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
and HAL_MMC_WriteBlocks_IT() APIs).
(+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority();
(+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
(+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
and __HAL_MMC_DISABLE_IT() inside the communication process.
(+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
and __HAL_MMC_CLEAR_IT()
(##) No general propose DMA Configuration is needed, an Internal DMA for SDMMC Peripheral are used.
(#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
*** MMC Card Initialization and configuration ***
================================================
[..]
To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
(#) Initialize the SDMMC peripheral interface with default configuration.
The initialization process is done at 400KHz. You can change or adapt
this frequency by adjusting the "ClockDiv" field.
The MMC Card frequency (SDMMC_CK) is computed as follows:
SDMMC_CK = SDMMCCLK / (2 * ClockDiv)
In initialization mode and according to the MMC Card standard,
make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
This phase of initialization is done through SDMMC_Init() and
SDMMC_PowerState_ON() SDMMC low level APIs.
(#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
This phase allows the card initialization and identification
and check the MMC Card type (Standard Capacity or High Capacity)
The initialization flow is compatible with MMC standard.
This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
of plug-off plug-in.
(#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
frequency by adjusting the "ClockDiv" field.
In transfer mode and according to the MMC Card standard, make sure that the
SDMMC_CK frequency doesn't exceed 25MHz and 100MHz in High-speed mode switch.
(#) Select the corresponding MMC Card according to the address read with the step 2.
(#) Configure the MMC Card in wide bus mode: 4-bits data.
*** MMC Card Read operation ***
==============================
[..]
(+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
(+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the DMA transfer process through the MMC Rx interrupt event.
(+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
This function allows the read of 512 bytes blocks.
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Rx interrupt event.
*** MMC Card Write operation ***
===============================
[..]
(+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
This function support only 512-bytes block length (the block size should be
chosen as 512 bytes).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
(+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
This function support only 512-bytes block length (the block size should be
chosen as 512 byte).
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the DMA transfer process through the MMC Tx interrupt event.
(+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
This function allows the read of 512 bytes blocks.
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
After this, you have to ensure that the transfer is done correctly. The check is done
through HAL_MMC_GetCardState() function for MMC card state.
You could also check the IT transfer process through the MMC Tx interrupt event.
*** MMC card information ***
===========================
[..]
(+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
It returns useful information about the MMC card such as block size, card type,
block number ...
*** MMC card CSD register ***
============================
[..]
(+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register.
Some of the CSD parameters are useful for card initialization and identification.
*** MMC card CID register ***
============================
[..]
(+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
Some of the CID parameters are useful for card initialization and identification.
*** MMC HAL driver macros list ***
==================================
[..]
Below the list of most used macros in MMC HAL driver.
(+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
(+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
(+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
(+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
[..]
(@) You can refer to the MMC HAL driver header file for more useful macros
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_MMC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) Read_DMALnkLstBufCpltCallback : callback when the DMA reception of linked list node buffer is completed.
(+) Write_DMALnkLstBufCpltCallback : callback when the DMA transmission of linked list node buffer is completed.
(+) MspInitCallback : MMC MspInit.
(+) MspDeInitCallback : MMC MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) Read_DMADblBuf0CpltCallback : callback when the DMA reception of first buffer is completed.
(+) Read_DMADblBuf1CpltCallback : callback when the DMA reception of second buffer is completed.
(+) Write_DMADblBuf0CpltCallback : callback when the DMA transmission of first buffer is completed.
(+) Write_DMADblBuf1CpltCallback : callback when the DMA transmission of second buffer is completed.
(+) MspInitCallback : MMC MspInit.
(+) MspDeInitCallback : MMC MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_MMC_Init
and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit
or HAL_MMC_Init function.
When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup MMC MMC
* @brief MMC HAL module driver
* @{
*/
#ifdef HAL_MMC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup MMC_Private_Defines
* @{
*/
#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U)
#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
#define MMC_EXT_CSD_PWR_CL_26_INDEX 201
#define MMC_EXT_CSD_PWR_CL_52_INDEX 200
#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238
#define MMC_EXT_CSD_PWR_CL_26_POS 8
#define MMC_EXT_CSD_PWR_CL_52_POS 0
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16
#else
#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define MMC_EXT_CSD_PWR_CL_26_INDEX 203
#define MMC_EXT_CSD_PWR_CL_52_INDEX 202
#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239
#define MMC_EXT_CSD_PWR_CL_26_POS 24
#define MMC_EXT_CSD_PWR_CL_52_POS 16
#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24
#endif /* (VDD_VALUE) && (VDD_VALUE <= 1950U)*/
#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX 216
#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS 0
#define MMC_EXT_CSD_S_A_TIMEOUT_INDEX 217
#define MMC_EXT_CSD_S_A_TIMEOUT_POS 8
/* Frequencies used in the driver for clock divider calculation */
#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */
#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MMC_Private_Functions MMC Private Functions
* @{
*/
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
static void MMC_Write_IT(MMC_HandleTypeDef *hmmc);
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state);
static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state);
static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex,
uint32_t Timeout);
static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup MMC_Exported_Functions
* @{
*/
/** @addtogroup MMC_Exported_Functions_Group1
* @brief Initialization and de-initialization functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize the MMC
card device to be ready for use.
@endverbatim
* @{
*/
/**
* @brief Initializes the MMC according to the specified parameters in the
MMC_HandleTypeDef and create the associated handle.
* @param hmmc: Pointer to the MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
{
/* Check the MMC handle allocation */
if (hmmc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge));
assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave));
assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide));
assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv));
if (hmmc->State == HAL_MMC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hmmc->Lock = HAL_UNLOCKED;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_MMC_STATE_RESET only */
hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
hmmc->Read_DMALnkLstBufCpltCallback = HAL_MMCEx_Read_DMALnkLstBufCpltCallback;
hmmc->Write_DMALnkLstBufCpltCallback = HAL_MMCEx_Write_DMALnkLstBufCpltCallback;
if (hmmc->MspInitCallback == NULL)
{
hmmc->MspInitCallback = HAL_MMC_MspInit;
}
/* Init the low level hardware */
hmmc->MspInitCallback(hmmc);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_MMC_MspInit(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize the Card parameters */
if (HAL_MMC_InitCard(hmmc) == HAL_ERROR)
{
return HAL_ERROR;
}
/* Initialize the error code */
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the MMC operation */
hmmc->Context = MMC_CONTEXT_NONE;
/* Initialize the MMC state */
hmmc->State = HAL_MMC_STATE_READY;
/* Configure bus width */
if (hmmc->Init.BusWide != SDMMC_BUS_WIDE_1B)
{
if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK)
{
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief Initializes the MMC Card.
* @param hmmc: Pointer to MMC handle
* @note This function initializes the MMC card. It could be used when a card
re-initialization is needed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate;
MMC_InitTypeDef Init;
uint32_t sdmmc_clk;
/* Default SDMMC peripheral configuration for MMC card initialization */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
Init.BusWide = SDMMC_BUS_WIDE_1B;
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
/* Init Clock should be less or equal to 400Khz*/
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
if (sdmmc_clk == 0U)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
return HAL_ERROR;
}
Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ);
#if (USE_SD_TRANSCEIVER != 0U)
Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT;
#endif /* USE_SD_TRANSCEIVER */
/* Initialize SDMMC peripheral interface with default configuration */
(void)SDMMC_Init(hmmc->Instance, Init);
/* Set Power State to ON */
(void)SDMMC_PowerState_ON(hmmc->Instance);
/* wait 74 Cycles: required power up waiting time before starting
the MMC initialization sequence */
sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
/* Card initialization */
errorstate = MMC_InitCard(hmmc);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief De-Initializes the MMC card.
* @param hmmc: Pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
{
/* Check the MMC handle allocation */
if (hmmc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance));
hmmc->State = HAL_MMC_STATE_BUSY;
/* Set MMC power state to off */
MMC_PowerOFF(hmmc);
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
if (hmmc->MspDeInitCallback == NULL)
{
hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
}
/* DeInit the low level hardware */
hmmc->MspDeInitCallback(hmmc);
#else
/* De-Initialize the MSP layer */
HAL_MMC_MspDeInit(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_RESET;
return HAL_OK;
}
/**
* @brief Initializes the MMC MSP.
* @param hmmc: Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MMC_MspInit could be implemented in the user file
*/
}
/**
* @brief De-Initialize MMC MSP.
* @param hmmc: Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MMC_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @addtogroup MMC_Exported_Functions_Group2
* @brief Data transfer functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to manage the data
transfer from/to MMC card.
@endverbatim
* @{
*/
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @param hmmc: Pointer to MMC handle
* @param pData: pointer to the buffer that will contain the received data
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of MMC blocks to read
* @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count;
uint32_t data;
uint32_t dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS)
& 0x000000FFU) != 0x0U)
{
if ((NumberOfBlocks % 8U) != 0U)
{
/* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
return HAL_ERROR;
}
if ((BlockAdd % 8U) != 0U)
{
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
return HAL_ERROR;
}
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Read block(s) in polling mode */
if (NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Poll on SDMMC flags */
dataremaining = config.DataLength;
while (!__HAL_MMC_GET_FLAG(hmmc,
SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U))
{
/* Read data from SDMMC Rx FIFO */
for (count = 0U; count < 8U; count++)
{
data = SDMMC_ReadFIFO(hmmc->Instance);
*tempbuff = (uint8_t)(data & 0xFFU);
tempbuff++;
*tempbuff = (uint8_t)((data >> 8U) & 0xFFU);
tempbuff++;
*tempbuff = (uint8_t)((data >> 16U) & 0xFFU);
tempbuff++;
*tempbuff = (uint8_t)((data >> 24U) & 0xFFU);
tempbuff++;
}
dataremaining -= 32U;
}
if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
__SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
/* Send stop transmission command in case of multiblock read */
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Get error state */
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
return HAL_OK;
}
else
{
hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
return HAL_ERROR;
}
}
/**
* @brief Allows to write block(s) to a specified address in a card. The Data
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @param hmmc: Pointer to MMC handle
* @param pData: pointer to the buffer that will contain the data to transmit
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of MMC blocks to write
* @param Timeout: Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
uint32_t NumberOfBlocks, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count;
uint32_t data;
uint32_t dataremaining;
uint32_t add = BlockAdd;
uint8_t *tempbuff = pData;
if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
{
if ((NumberOfBlocks % 8U) != 0U)
{
/* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
return HAL_ERROR;
}
if ((BlockAdd % 8U) != 0U)
{
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
return HAL_ERROR;
}
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Write Blocks in Polling mode */
if (NumberOfBlocks > 1U)
{
hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Write block(s) in polling mode */
dataremaining = config.DataLength;
while (!__HAL_MMC_GET_FLAG(hmmc,
SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U))
{
/* Write data to SDMMC Tx FIFO */
for (count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tempbuff);
tempbuff++;
data |= ((uint32_t)(*tempbuff) << 8U);
tempbuff++;
data |= ((uint32_t)(*tempbuff) << 16U);
tempbuff++;
data |= ((uint32_t)(*tempbuff) << 24U);
tempbuff++;
(void)SDMMC_WriteFIFO(hmmc->Instance, &data);
}
dataremaining -= 32U;
}
if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
__SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
/* Send stop transmission command in case of multiblock write */
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
{
/* Send stop transmission command */
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
}
/* Get error state */
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
return HAL_OK;
}
else
{
hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
return HAL_ERROR;
}
}
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @note You could also check the IT transfer process through the MMC Rx
* interrupt event.
* @param hmmc: Pointer to MMC handle
* @param pData: Pointer to the buffer that will contain the received data
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
{
if ((NumberOfBlocks % 8U) != 0U)
{
/* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
return HAL_ERROR;
}
if ((BlockAdd % 8U) != 0U)
{
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
return HAL_ERROR;
}
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
hmmc->pRxBuffPtr = pData;
hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Read Blocks in IT mode */
if (NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
SDMMC_FLAG_RXFIFOHF));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Writes block(s) to a specified address in a card. The Data transfer
* is managed in interrupt mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @note You could also check the IT transfer process through the MMC Tx
* interrupt event.
* @param hmmc: Pointer to MMC handle
* @param pData: Pointer to the buffer that will contain the data to transmit
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
{
if ((NumberOfBlocks % 8U) != 0U)
{
/* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
return HAL_ERROR;
}
if ((BlockAdd % 8U) != 0U)
{
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
return HAL_ERROR;
}
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
hmmc->pTxBuffPtr = pData;
hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Write Blocks in Polling mode */
if (NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Enable transfer interrupts */
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
SDMMC_FLAG_TXFIFOHE));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @note You could also check the DMA transfer process through the MMC Rx
* interrupt event.
* @param hmmc: Pointer MMC handle
* @param pData: Pointer to the buffer that will contain the received data
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
{
if ((NumberOfBlocks % 8U) != 0U)
{
/* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
return HAL_ERROR;
}
if ((BlockAdd % 8U) != 0U)
{
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
return HAL_ERROR;
}
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
hmmc->pRxBuffPtr = pData;
hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMABASER = (uint32_t) pData ;
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Read Blocks in DMA mode */
if (NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add);
}
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode = errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Enable transfer interrupts */
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Writes block(s) to a specified address in a card. The Data transfer
* is managed by DMA mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @note You could also check the DMA transfer process through the MMC Tx
* interrupt event.
* @param hmmc: Pointer to MMC handle
* @param pData: Pointer to the buffer that will contain the data to transmit
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
if (NULL == pData)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
{
if ((NumberOfBlocks % 8U) != 0U)
{
/* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
return HAL_ERROR;
}
if ((BlockAdd % 8U) != 0U)
{
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
return HAL_ERROR;
}
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0U;
hmmc->pTxBuffPtr = pData;
hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMABASER = (uint32_t) pData ;
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Write Blocks in Polling mode */
if (NumberOfBlocks > 1U)
{
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
}
else
{
hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add);
}
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Enable transfer interrupts */
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Erases the specified memory area of the given MMC card.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @param hmmc: Pointer to MMC handle
* @param BlockStartAdd: Start Block address
* @param BlockEndAdd: End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
uint32_t errorstate;
uint32_t start_add = BlockStartAdd;
uint32_t end_add = BlockEndAdd;
if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if (end_add < start_add)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if (end_add > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS)
& 0x000000FFU) != 0x0U)
{
if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
{
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
return HAL_ERROR;
}
}
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check if the card command class supports erase command */
if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
start_add *= 512U;
end_add *= 512U;
}
/* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Send CMD38 ERASE */
errorstate = SDMMC_CmdErase(hmmc->Instance, 0UL);
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
hmmc->State = HAL_MMC_STATE_READY;
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief This function handles MMC card interrupt request.
* @param hmmc: Pointer to MMC handle
* @retval None
*/
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate;
uint32_t context = hmmc->Context;
/* Check for SDMMC interrupt flags */
if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
MMC_Read_IT(hmmc);
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND);
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \
SDMMC_IT_RXFIFOHF);
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
__SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
if ((context & MMC_CONTEXT_DMA) != 0U)
{
hmmc->Instance->DLEN = 0;
hmmc->Instance->DCTRL = 0;
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ;
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
if (((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->TxCpltCallback(hmmc);
#else
HAL_MMC_TxCpltCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
#else
HAL_MMC_RxCpltCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
else if ((context & MMC_CONTEXT_IT) != 0U)
{
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
#else
HAL_MMC_RxCpltCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
else
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->TxCpltCallback(hmmc);
#else
HAL_MMC_TxCpltCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
else
{
/* Nothing to do */
}
}
else if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U))
{
MMC_Write_IT(hmmc);
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL |
SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET)
{
/* Set Error code */
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
}
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
}
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
}
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
}
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
/* Disable all interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
__SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP;
hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT);
if ((context & MMC_CONTEXT_IT) != 0U)
{
/* Set the MMC state to ready to be able to start again the process */
hmmc->State = HAL_MMC_STATE_READY;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
else if ((context & MMC_CONTEXT_DMA) != 0U)
{
if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
/* Disable Internal DMA */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
/* Set the MMC state to ready to be able to start again the process */
hmmc->State = HAL_MMC_STATE_READY;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
else
{
/* Nothing to do */
}
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC);
if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->Write_DMALnkLstBufCpltCallback(hmmc);
#else
HAL_MMCEx_Write_DMALnkLstBufCpltCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->Read_DMALnkLstBufCpltCallback(hmmc);
#else
HAL_MMCEx_Read_DMALnkLstBufCpltCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
else
{
/* Nothing to do */
}
}
/**
* @brief return the MMC state
* @param hmmc: Pointer to mmc handle
* @retval HAL state
*/
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
{
return hmmc->State;
}
/**
* @brief Return the MMC error code
* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval MMC Error Code
*/
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
{
return hmmc->ErrorCode;
}
/**
* @brief Tx Transfer completed callbacks
* @param hmmc: Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_TxCpltCallback can be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks
* @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_RxCpltCallback can be implemented in the user file
*/
}
/**
* @brief MMC error callbacks
* @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_ErrorCallback can be implemented in the user file
*/
}
/**
* @brief MMC Abort callbacks
* @param hmmc: Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMC_AbortCallback can be implemented in the user file
*/
}
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User MMC Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hmmc : MMC handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
* @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
* @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
* @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
* @arg @ref HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Rx Linked List Node buffer Callback ID
* @arg @ref HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Tx Linked List Node buffer Callback ID
* @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
* @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId,
pMMC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hmmc);
if (hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
{
case HAL_MMC_TX_CPLT_CB_ID :
hmmc->TxCpltCallback = pCallback;
break;
case HAL_MMC_RX_CPLT_CB_ID :
hmmc->RxCpltCallback = pCallback;
break;
case HAL_MMC_ERROR_CB_ID :
hmmc->ErrorCallback = pCallback;
break;
case HAL_MMC_ABORT_CB_ID :
hmmc->AbortCpltCallback = pCallback;
break;
case HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID :
hmmc->Read_DMALnkLstBufCpltCallback = pCallback;
break;
case HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID :
hmmc->Write_DMALnkLstBufCpltCallback = pCallback;
break;
case HAL_MMC_MSP_INIT_CB_ID :
hmmc->MspInitCallback = pCallback;
break;
case HAL_MMC_MSP_DEINIT_CB_ID :
hmmc->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hmmc->State == HAL_MMC_STATE_RESET)
{
switch (CallbackId)
{
case HAL_MMC_MSP_INIT_CB_ID :
hmmc->MspInitCallback = pCallback;
break;
case HAL_MMC_MSP_DEINIT_CB_ID :
hmmc->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hmmc);
return status;
}
/**
* @brief Unregister a User MMC Callback
* MMC Callback is redirected to the weak (surcharged) predefined callback
* @param hmmc : MMC handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID
* @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID
* @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID
* @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID
* @arg @ref HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Rx Linked List Node buffer Callback ID
* @arg @ref HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID MMC DMA Tx Linked List Node buffer Callback ID
* @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID
* @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hmmc);
if (hmmc->State == HAL_MMC_STATE_READY)
{
switch (CallbackId)
{
case HAL_MMC_TX_CPLT_CB_ID :
hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback;
break;
case HAL_MMC_RX_CPLT_CB_ID :
hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback;
break;
case HAL_MMC_ERROR_CB_ID :
hmmc->ErrorCallback = HAL_MMC_ErrorCallback;
break;
case HAL_MMC_ABORT_CB_ID :
hmmc->AbortCpltCallback = HAL_MMC_AbortCallback;
break;
case HAL_MMC_READ_DMA_LNKLST_BUF_CPLT_CB_ID :
hmmc->Read_DMALnkLstBufCpltCallback = HAL_MMCEx_Read_DMALnkLstBufCpltCallback;
break;
case HAL_MMC_WRITE_DMA_LNKLST_BUF_CPLT_CB_ID :
hmmc->Write_DMALnkLstBufCpltCallback = HAL_MMCEx_Write_DMALnkLstBufCpltCallback;
break;
case HAL_MMC_MSP_INIT_CB_ID :
hmmc->MspInitCallback = HAL_MMC_MspInit;
break;
case HAL_MMC_MSP_DEINIT_CB_ID :
hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
break;
default :
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hmmc->State == HAL_MMC_STATE_RESET)
{
switch (CallbackId)
{
case HAL_MMC_MSP_INIT_CB_ID :
hmmc->MspInitCallback = HAL_MMC_MspInit;
break;
case HAL_MMC_MSP_DEINIT_CB_ID :
hmmc->MspDeInitCallback = HAL_MMC_MspDeInit;
break;
default :
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hmmc);
return status;
}
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup MMC_Exported_Functions_Group3
* @brief management functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the MMC card
operations and get the related information
@endverbatim
* @{
*/
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
* @param hmmc: Pointer to MMC handle
* @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that
* contains all CID register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
{
pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U);
pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U);
pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U));
pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU);
pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U);
pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U));
pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U);
pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U);
pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U);
pCID->Reserved2 = 1U;
return HAL_OK;
}
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
* @param hmmc: Pointer to MMC handle
* @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
{
uint32_t block_nbr = 0;
pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U);
pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U);
pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U);
pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U);
pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U);
pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU);
pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U);
pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U);
pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U);
pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U);
pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U);
pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U);
pCSD->Reserved2 = 0U; /*!< Reserved */
if (MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */
{
return HAL_ERROR;
}
if (hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD)
{
pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U));
pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U);
pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U);
pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U);
pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U);
pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U);
hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
hmmc->MmcCard.LogBlockSize = 512U;
}
else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD)
{
hmmc->MmcCard.BlockNbr = block_nbr;
hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr;
hmmc->MmcCard.BlockSize = 512U;
hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize;
}
else
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U);
pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U);
pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU);
pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U);
pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U);
pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U);
pCSD->MaxWrBlockLen = (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U);
pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U);
pCSD->Reserved3 = 0;
pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U);
pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U);
pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U);
pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U);
pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U);
pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U);
pCSD->ECC = (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U);
pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U);
pCSD->Reserved4 = 1;
return HAL_OK;
}
/**
* @brief Gets the MMC card info.
* @param hmmc: Pointer to MMC handle
* @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
* will contain the MMC card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
{
pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType);
pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class);
pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd);
pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr);
pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize);
pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
return HAL_OK;
}
/**
* @brief Returns information the information of the card which are stored on
* the Extended CSD register.
* @param hmmc Pointer to MMC handle
* @param pExtCSD Pointer to a memory area (512 bytes) that contains all
* Extended CSD register parameters
* @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count;
uint32_t *tmp_buf;
if (NULL == pExtCSD)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
if (hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_BUSY;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
/* Initiaize the destination pointer */
tmp_buf = pExtCSD;
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 512U;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
/* Send ExtCSD Read command to Card */
errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Poll on SDMMC flags */
while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR |
SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
{
/* Read data from SDMMC Rx FIFO */
for (count = 0U; count < 8U; count++)
{
*tmp_buf = SDMMC_ReadFIFO(hmmc->Instance);
tmp_buf++;
}
}
if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
__SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
/* Get error state */
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
}
return HAL_OK;
}
/**
* @brief Enables wide bus operation for the requested card if supported by
* card.
* @param hmmc: Pointer to MMC handle
* @param WideMode: Specifies the MMC card wide bus mode
* This parameter can be one of the following values:
* @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
* @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
* @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
{
uint32_t count;
SDMMC_InitTypeDef Init;
uint32_t errorstate;
uint32_t response = 0U;
/* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check and update the power class if needed */
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)
{
errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DDR);
}
else
{
errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_HIGH);
}
}
else
{
errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DEFAULT);
}
if (errorstate == HAL_MMC_ERROR_NONE)
{
if (WideMode == SDMMC_BUS_WIDE_8B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
}
else if (WideMode == SDMMC_BUS_WIDE_4B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
}
else if (WideMode == SDMMC_BUS_WIDE_1B)
{
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
}
else
{
/* WideMode is not a valid argument*/
errorstate = HAL_MMC_ERROR_PARAM;
}
/* Check for switch error and violation of the trial number of sending CMD 13 */
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
}
else
{
/* Configure the SDMMC peripheral */
Init = hmmc->Init;
Init.BusWide = WideMode;
(void)SDMMC_Init(hmmc->Instance, Init);
}
}
else if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else
{
/* Nothing to do */
}
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Configure the speed bus mode
* @param hmmc: Pointer to the MMC handle
* @param SpeedMode: Specifies the MMC card speed bus mode
* This parameter can be one of the following values:
* @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card
* @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed (MMC @ 26MHz)
* @arg SDMMC_SPEED_MODE_HIGH: High Speed (MMC @ 52 MHz)
* @arg SDMMC_SPEED_MODE_DDR: High Speed DDR (MMC DDR @ 52 MHz)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode)
{
uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK;
uint32_t device_type;
uint32_t errorstate;
/* Check the parameters */
assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Field DEVICE_TYPE [196 = 49*4] of Extended CSD register */
device_type = (hmmc->Ext_CSD[49] & 0x000000FFU);
switch (SpeedMode)
{
case SDMMC_SPEED_MODE_AUTO:
{
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
{
/* High Speed DDR mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
else
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U)
{
/* DDR mode not supported with CLKDIV = 0 */
errorstate = MMC_DDR_Mode(hmmc, ENABLE);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
}
}
else if ((device_type & 0x02U) != 0U)
{
/* High Speed mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
else
{
/* Nothing to do : keep current speed */
}
break;
}
case SDMMC_SPEED_MODE_DDR:
{
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U))
{
/* High Speed DDR mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
else
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U)
{
/* DDR mode not supported with CLKDIV = 0 */
errorstate = MMC_DDR_Mode(hmmc, ENABLE);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
}
}
else
{
/* High Speed DDR mode not allowed */
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
break;
}
case SDMMC_SPEED_MODE_HIGH:
{
if ((device_type & 0x02U) != 0U)
{
/* High Speed mode allowed */
errorstate = MMC_HighSpeed(hmmc, ENABLE);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
else
{
/* High Speed mode not allowed */
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
break;
}
case SDMMC_SPEED_MODE_DEFAULT:
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)
{
/* High Speed DDR mode activated */
errorstate = MMC_DDR_Mode(hmmc, DISABLE);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)
{
/* High Speed mode activated */
errorstate = MMC_HighSpeed(hmmc, DISABLE);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
}
break;
}
default:
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
status = HAL_ERROR;
break;
}
/* Verify that MMC card is ready to use after Speed mode switch*/
tickstart = HAL_GetTick();
while ((HAL_MMC_GetCardState(hmmc) != HAL_MMC_CARD_TRANSFER))
{
if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
return status;
}
/**
* @brief Gets the current mmc card data state.
* @param hmmc: pointer to MMC handle
* @retval Card state
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
{
uint32_t cardstate;
uint32_t errorstate;
uint32_t resp1 = 0U;
errorstate = MMC_SendStatus(hmmc, &resp1);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
cardstate = ((resp1 >> 9U) & 0x0FU);
return (HAL_MMC_CardStateTypeDef)cardstate;
}
/**
* @brief Abort the current transfer and disable the MMC.
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardStateTypeDef CardState;
/* DIsable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
/* If IDMA Context, disable Internal DMA */
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
hmmc->State = HAL_MMC_STATE_READY;
/* Initialize the MMC operation */
hmmc->Context = MMC_CONTEXT_NONE;
CardState = HAL_MMC_GetCardState(hmmc);
if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
}
if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Abort the current transfer and disable the MMC (IT mode).
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardStateTypeDef CardState;
/* DIsable All interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
/* If IDMA Context, disable Internal DMA */
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
CardState = HAL_MMC_GetCardState(hmmc);
hmmc->State = HAL_MMC_STATE_READY;
if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
}
if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->AbortCpltCallback(hmmc);
#else
HAL_MMC_AbortCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
return HAL_OK;
}
/**
* @brief Perform specific commands sequence for the different type of erase.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @param hmmc Pointer to MMC handle
* @param EraseType Specifies the type of erase to be performed
* This parameter can be one of the following values:
* @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36
* @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36
* @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36
* @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified
* by CMD35 & 36
* @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase
* @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks
* previously identified
* @param BlockStartAdd Start Block address
* @param BlockEndAdd End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType,
uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
uint32_t errorstate;
uint32_t start_add = BlockStartAdd;
uint32_t end_add = BlockEndAdd;
uint32_t tickstart = HAL_GetTick();
/* Check the erase type value is correct */
assert_param(IS_MMC_ERASE_TYPE(EraseType));
/* Check the coherence between start and end address */
if (end_add < start_add)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
return HAL_ERROR;
}
/* Check that the end address is not out of range of device memory */
if (end_add > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
{
if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
{
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
return HAL_ERROR;
}
}
/* Check if the card command class supports erase command */
if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
return HAL_ERROR;
}
/* Check the state of the driver */
if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check that the card is not locked */
if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* In case of low capacity card, the address is not block number but bytes */
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
start_add *= 512U;
end_add *= 512U;
}
/* Send CMD35 MMC_ERASE_GRP_START with start address as argument */
errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Send CMD36 MMC_ERASE_GRP_END with end address as argument */
errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Send CMD38 ERASE with erase type as argument */
errorstate = SDMMC_CmdErase(hmmc->Instance, EraseType);
if (errorstate == HAL_MMC_ERROR_NONE)
{
if ((EraseType == HAL_MMC_SECURE_ERASE) || (EraseType == HAL_MMC_SECURE_TRIM_STEP2))
{
/* Wait that the device is ready by checking the D0 line */
while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
{
errorstate = HAL_MMC_ERROR_TIMEOUT;
}
}
/* Clear the flag corresponding to end D0 bus line */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
}
}
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
/* Manage errors */
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
if (errorstate != HAL_MMC_ERROR_TIMEOUT)
{
return HAL_ERROR;
}
else
{
return HAL_TIMEOUT;
}
}
else
{
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Perform sanitize operation on the device.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @param hmmc Pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate;
uint32_t response = 0U;
uint32_t count;
uint32_t tickstart = HAL_GetTick();
/* Check the state of the driver */
if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Index : 165 - Value : 0x01 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03A50100U);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Wait that the device is ready by checking the D0 line */
while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT)
{
errorstate = HAL_MMC_ERROR_TIMEOUT;
}
}
/* Clear the flag corresponding to end D0 bus line */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
}
}
else if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else
{
/* Nothing to do */
}
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
/* Manage errors */
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
if (errorstate != HAL_MMC_ERROR_TIMEOUT)
{
return HAL_ERROR;
}
else
{
return HAL_TIMEOUT;
}
}
else
{
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure the Secure Removal Type (SRT) in the Extended CSD register.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
* @param hmmc Pointer to MMC handle
* @param SRTMode Specifies the type of erase to be performed
* This parameter can be one of the following values:
* @arg HAL_MMC_SRT_ERASE Information removed by an erase
* @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character
* followed by an erase
* @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character,
* its complement then a random character
* @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode)
{
uint32_t srt;
uint32_t errorstate;
uint32_t response = 0U;
uint32_t count;
/* Check the erase type value is correct */
assert_param(IS_MMC_SRT_TYPE(SRTMode));
/* Check the state of the driver */
if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Get the supported values by the device */
if (HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Check the value passed as parameter is supported by the device */
if ((SRTMode & srt) != 0U)
{
/* Index : 16 - Value : SRTMode */
srt |= ((POSITION_VAL(SRTMode)) << 4U);
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03100000U | (srt << 8U)));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
}
}
else if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else
{
/* Nothing to do */
}
}
}
else
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
}
else
{
errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
}
/* Manage errors */
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
else
{
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Gets the supported values of the the Secure Removal Type (SRT).
* @param hmmc pointer to MMC handle
* @param SupportedSRT pointer for supported SRT value
* This parameter is a bit field of the following values:
* @arg HAL_MMC_SRT_ERASE Information removed by an erase
* @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed
* by an erase
* @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character,
* its complement then a random character
* @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT)
{
/* Check the state of the driver */
if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Read field SECURE_REMOVAL_TYPE [16 = 4*4] of the Extended CSD register */
*SupportedSRT = (hmmc->Ext_CSD[4] & 0x0000000FU); /* Bits [3:0] of field 16 */
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Switch the device from Standby State to Sleep State.
* @param hmmc pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate,
sleep_timeout,
timeout,
count,
response = 0U ;
uint32_t tickstart = HAL_GetTick();
/* Check the state of the driver */
if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
/* Set the power-off notification to sleep notification : Ext_CSD[34] = 4 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220400U));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Field SLEEP_NOTIFICATION_TIME [216] */
sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX / 4)] >>
MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS) & 0x000000FFU);
/* Sleep/Awake Timeout = 10us * 2^SLEEP_NOTIFICATION_TIME */
/* In HAL, the tick interrupt occurs each ms */
if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
{
sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
}
timeout = (((1UL << sleep_timeout) / 100U) + 1U);
/* Wait that the device is ready by checking the D0 line */
while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
if ((HAL_GetTick() - tickstart) >= timeout)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
}
/* Clear the flag corresponding to end D0 bus line */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance,
(uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
/* Switch the device in stand-by mode */
(void)SDMMC_CmdSelDesel(hmmc->Instance, 0U);
/* Field S_A_TIEMOUT [217] */
sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >>
MMC_EXT_CSD_S_A_TIMEOUT_POS) & 0x000000FFU);
/* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */
/* In HAL, the tick interrupt occurs each ms */
if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
{
sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
}
timeout = (((1UL << sleep_timeout) / 10000U) + 1U);
if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
{
/* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */
errorstate = SDMMC_CmdSleepMmc(hmmc->Instance,
((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U)));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Wait that the device is ready by checking the D0 line */
while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
if ((HAL_GetTick() - tickstart) >= timeout)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
}
/* Clear the flag corresponding to end D0 bus line */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
}
}
else
{
errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
}
}
}
else
{
/* Nothing to do */
}
}
}
}
}
else
{
/* Nothing to do */
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
/* Manage errors */
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
if (errorstate != HAL_MMC_ERROR_TIMEOUT)
{
return HAL_ERROR;
}
else
{
return HAL_TIMEOUT;
}
}
else
{
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Switch the device from Sleep State to Standby State.
* @param hmmc pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc)
{
uint32_t errorstate;
uint32_t sleep_timeout;
uint32_t timeout;
uint32_t count;
uint32_t response = 0U;
uint32_t tickstart = HAL_GetTick();
/* Check the state of the driver */
if (hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
/* Field S_A_TIEMOUT [217] */
sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> MMC_EXT_CSD_S_A_TIMEOUT_POS) &
0x000000FFU);
/* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */
/* In HAL, the tick interrupt occurs each ms */
if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
{
sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
}
timeout = (((1UL << sleep_timeout) / 10000U) + 1U);
/* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and AWAKE as argument */
errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Wait that the device is ready by checking the D0 line */
while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
{
if ((HAL_GetTick() - tickstart) >= timeout)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
}
/* Clear the flag corresponding to end D0 bus line */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
if (errorstate == HAL_MMC_ERROR_NONE)
{
if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
{
/* Switch the device in transfer mode */
errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
if (errorstate == HAL_MMC_ERROR_NONE)
{
if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_TRANSFER)
{
/* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance,
(uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
}
else
{
/* NOthing to do */
}
}
}
else
{
errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
}
}
}
else
{
errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
}
}
}
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
/* Manage errors */
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
if (errorstate != HAL_MMC_ERROR_TIMEOUT)
{
return HAL_ERROR;
}
else
{
return HAL_TIMEOUT;
}
}
else
{
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/**
* @}
*/
/* Private function ----------------------------------------------------------*/
/** @addtogroup MMC_Private_Functions
* @{
*/
/**
* @brief Initializes the mmc card.
* @param hmmc: Pointer to MMC handle
* @retval MMC Card error state
*/
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
{
HAL_MMC_CardCSDTypeDef CSD;
uint32_t errorstate;
uint16_t mmc_rca = 2U;
MMC_InitTypeDef Init;
/* Check the power State */
if (SDMMC_GetPowerState(hmmc->Instance) == 0U)
{
/* Power off */
return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
}
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hmmc->Instance);
if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
else
{
/* Get Card identification number data */
hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
}
/* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */
/* MMC Card publishes its RCA. */
errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca);
if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
/* Get the MMC card RCA */
hmmc->MmcCard.RelCardAdd = mmc_rca;
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
else
{
/* Get Card Specific Data */
hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2);
hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3);
hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
}
/* Get the Card Class */
hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U);
/* Select the Card */
errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
/* Get CSD parameters */
if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK)
{
return hmmc->ErrorCode;
}
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
/* Get Extended CSD parameters */
if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK)
{
return hmmc->ErrorCode;
}
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
/* Configure the SDMMC peripheral */
Init = hmmc->Init;
Init.BusWide = SDMMC_BUS_WIDE_1B;
(void)SDMMC_Init(hmmc->Instance, Init);
/* All cards are initialized */
return HAL_MMC_ERROR_NONE;
}
/**
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores MMC information that will be needed in future
* in the MMC handle.
* @param hmmc: Pointer to MMC handle
* @retval error state
*/
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
{
__IO uint32_t count = 0U;
uint32_t response = 0U;
uint32_t validvoltage = 0U;
uint32_t errorstate;
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
while (validvoltage == 0U)
{
if (count++ == SDMMC_MAX_VOLT_TRIAL)
{
return HAL_MMC_ERROR_INVALID_VOLTRANGE;
}
/* SEND CMD1 APP_CMD with voltage range as argument */
errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE);
if (errorstate != HAL_MMC_ERROR_NONE)
{
return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
/* Get operating voltage*/
validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
}
/* When power routine is finished and command returns valid voltage */
if (((response & (0xFF000000U)) >> 24) == 0xC0U)
{
hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD;
}
else
{
hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD;
}
return HAL_MMC_ERROR_NONE;
}
/**
* @brief Turns the SDMMC output signals off.
* @param hmmc: Pointer to MMC handle
* @retval None
*/
static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
{
/* Set Power State to OFF */
(void)SDMMC_PowerState_OFF(hmmc->Instance);
}
/**
* @brief Returns the current card's status.
* @param hmmc: Pointer to MMC handle
* @param pCardStatus: pointer to the buffer that will contain the MMC card
* status (Card Status register)
* @retval error state
*/
static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
{
uint32_t errorstate;
if (pCardStatus == NULL)
{
return HAL_MMC_ERROR_PARAM;
}
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
}
/* Get MMC card status */
*pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
return HAL_MMC_ERROR_NONE;
}
/**
* @brief Reads extended CSD register to get the sectors number of the device
* @param hmmc: Pointer to MMC handle
* @param pFieldData: Pointer to the read buffer
* @param FieldIndex: Index of the field to be read
* @param Timeout: Specify timeout value
* @retval HAL status
*/
static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData,
uint16_t FieldIndex, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
uint32_t count;
uint32_t i = 0;
uint32_t tmp_data;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = 512U;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
/* Set Block Size for Card */
errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
if (errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
/* Poll on SDMMC flags */
while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
SDMMC_FLAG_DATAEND))
{
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
{
/* Read data from SDMMC Rx FIFO */
for (count = 0U; count < 8U; count++)
{
tmp_data = SDMMC_ReadFIFO(hmmc->Instance);
/* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */
/* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */
if ((i + count) == ((uint32_t)FieldIndex / 4U))
{
*pFieldData = tmp_data;
}
}
i += 8U;
}
if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
}
}
/* Get error state */
if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
{
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
}
else
{
/* Nothing to do */
}
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
return HAL_OK;
}
/**
* @brief Wrap up reading in non-blocking mode.
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval None
*/
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
{
uint32_t count;
uint32_t data;
uint8_t *tmp;
tmp = hmmc->pRxBuffPtr;
if (hmmc->RxXferSize >= 32U)
{
/* Read data from SDMMC Rx FIFO */
for (count = 0U; count < 8U; count++)
{
data = SDMMC_ReadFIFO(hmmc->Instance);
*tmp = (uint8_t)(data & 0xFFU);
tmp++;
*tmp = (uint8_t)((data >> 8U) & 0xFFU);
tmp++;
*tmp = (uint8_t)((data >> 16U) & 0xFFU);
tmp++;
*tmp = (uint8_t)((data >> 24U) & 0xFFU);
tmp++;
}
hmmc->pRxBuffPtr = tmp;
hmmc->RxXferSize -= 32U;
}
}
/**
* @brief Wrap up writing in non-blocking mode.
* @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval None
*/
static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
{
uint32_t count;
uint32_t data;
uint8_t *tmp;
tmp = hmmc->pTxBuffPtr;
if (hmmc->TxXferSize >= 32U)
{
/* Write data to SDMMC Tx FIFO */
for (count = 0U; count < 8U; count++)
{
data = (uint32_t)(*tmp);
tmp++;
data |= ((uint32_t)(*tmp) << 8U);
tmp++;
data |= ((uint32_t)(*tmp) << 16U);
tmp++;
data |= ((uint32_t)(*tmp) << 24U);
tmp++;
(void)SDMMC_WriteFIFO(hmmc->Instance, &data);
}
hmmc->pTxBuffPtr = tmp;
hmmc->TxXferSize -= 32U;
}
}
/**
* @brief Switches the MMC card to high speed mode.
* @param hmmc: MMC handle
* @param state: State of high speed mode
* @retval MMC Card error state
*/
static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
uint32_t response = 0U;
uint32_t count;
uint32_t sdmmc_clk;
SDMMC_InitTypeDef Init;
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE))
{
errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_DEFAULT);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 185 - Value : 0 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
}
}
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE))
{
errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_HIGH);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 185 - Value : 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
}
}
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
/* Configure high speed */
Init.ClockEdge = hmmc->Init.ClockEdge;
Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
Init.BusWide = (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS);
Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
if (state == DISABLE)
{
Init.ClockDiv = hmmc->Init.ClockDiv;
(void)SDMMC_Init(hmmc->Instance, Init);
CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
}
else
{
/* High Speed Clock should be less or equal to 52MHz*/
sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
if (sdmmc_clk == 0U)
{
errorstate = SDMMC_ERROR_INVALID_PARAMETER;
}
else
{
if (sdmmc_clk <= MMC_HIGH_SPEED_FREQ)
{
Init.ClockDiv = 0;
}
else
{
Init.ClockDiv = (sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ)) + 1U;
}
(void)SDMMC_Init(hmmc->Instance, Init);
SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
}
}
}
}
else if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else
{
/* Nothing to do */
}
}
return errorstate;
}
/**
* @brief Switches the MMC card to Double Data Rate (DDR) mode.
* @param hmmc: MMC handle
* @param state: State of DDR mode
* @retval MMC Card error state
*/
static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state)
{
uint32_t errorstate = HAL_MMC_ERROR_NONE;
uint32_t response = 0U;
uint32_t count;
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE))
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_HIGH);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 183 - Value : 1 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
}
}
else
{
errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_HIGH);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 183 - Value : 2 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
}
}
}
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE))
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_DDR);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 183 - Value : 5 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U);
}
}
else
{
errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_DDR);
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* Index : 183 - Value : 6 */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U);
}
}
}
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
/* Configure DDR mode */
if (state == DISABLE)
{
CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
}
else
{
SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
}
}
}
else if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else
{
/* Nothing to do */
}
}
return errorstate;
}
/**
* @brief Update the power class of the device.
* @param hmmc MMC handle
* @param Wide Wide of MMC bus
* @param Speed Speed of the MMC bus
* @retval MMC Card error state
*/
static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed)
{
uint32_t count;
uint32_t response = 0U;
uint32_t errorstate = HAL_MMC_ERROR_NONE;
uint32_t power_class;
uint32_t supported_pwr_class;
if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B))
{
power_class = 0U; /* Default value after power-on or software reset */
/* Read the PowerClass field of the Extended CSD register */
if (MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */
{
errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
}
else
{
power_class = ((power_class >> 24U) & 0x000000FFU);
}
/* Get the supported PowerClass field of the Extended CSD register */
if (Speed == SDMMC_SPEED_MODE_DDR)
{
/* Field PWR_CL_DDR_52_xxx [238 or 239] */
supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) &
0x000000FFU);
}
else if (Speed == SDMMC_SPEED_MODE_HIGH)
{
/* Field PWR_CL_52_xxx [200 or 202] */
supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_52_POS) &
0x000000FFU);
}
else
{
/* Field PWR_CL_26_xxx [201 or 203] */
supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_26_POS) &
0x000000FFU);
}
if (errorstate == HAL_MMC_ERROR_NONE)
{
if (Wide == SDMMC_BUS_WIDE_8B)
{
/* Bit [7:4]: power class for 8-bits bus configuration - Bit [3:0]: power class for 4-bits bus configuration */
supported_pwr_class = (supported_pwr_class >> 4U);
}
if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU))
{
/* Need to change current power class */
errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U)));
if (errorstate == HAL_MMC_ERROR_NONE)
{
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
count = SDMMC_MAX_TRIAL;
do
{
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
if (errorstate != HAL_MMC_ERROR_NONE)
{
break;
}
/* Get command response */
response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
count--;
} while (((response & 0x100U) == 0U) && (count != 0U));
/* Check the status after the switch command execution */
if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
{
/* Check the bit SWITCH_ERROR of the device status */
if ((response & 0x80U) != 0U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
}
else if (count == 0U)
{
errorstate = SDMMC_ERROR_TIMEOUT;
}
else
{
/* Nothing to do */
}
}
}
}
}
return errorstate;
}
/**
* @brief Read DMA Linked list node Transfer completed callbacks
* @param hmmc: MMC handle
* @retval None
*/
__weak void HAL_MMCEx_Read_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMCEx_Read_DMALnkLstBufCpltCallback can be implemented in the user file
*/
}
/**
* @brief Read DMA Linked list node Transfer completed callbacks
* @param hmmc: MMC handle
* @retval None
*/
__weak void HAL_MMCEx_Write_DMALnkLstBufCpltCallback(MMC_HandleTypeDef *hmmc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmmc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MMCEx_Write_DMALnkLstBufCpltCallback can be implemented in the user file
*/
}
/**
* @}
*/
#endif /* HAL_MMC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c
|
C
|
apache-2.0
| 135,356
|
/**
******************************************************************************
* @file stm32u5xx_hal_mmc_ex.c
* @author MCD Application Team
* @brief MMC card Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
* + Extended features functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The MMC Extension HAL driver can be used as follows:
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
(+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and
HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup MMCEx MMCEx
* @brief MMC Extended HAL module driver
* @{
*/
#ifdef HAL_MMC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup MMCEx_Exported_Functions
* @{
*/
/** @addtogroup MMCEx_Exported_Functions_Group1
* @brief Linked List management functions
*
@verbatim
===============================================================================
##### Linked List management functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the needed functions.
@endverbatim
* @{
*/
/**
* @brief Build Linked List node.
* @param pNode: Pointer to new node to add.
* @param pNodeConf: Pointer to configuration parameters for new node to add.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode,
MMC_DMALinkNodeConfTypeDef *pNodeConf)
{
if (SDMMC_DMALinkedList_BuildNode(pNode, pNodeConf) != SDMMC_ERROR_NONE)
{
return (HAL_ERROR);
}
else
{
return (HAL_OK);
}
}
/**
* @brief Insert Linked List node.
* @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
* @param pPrevNode: Pointer to previous node.
* @param pNewNode: Pointer to new node to insert.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_InsertNode(MMC_DMALinkedListTypeDef *pLinkedList,
MMC_DMALinkNodeTypeDef *pPrevNode,
MMC_DMALinkNodeTypeDef *pNewNode)
{
if (SDMMC_DMALinkedList_InsertNode(pLinkedList, pPrevNode, pNewNode) != SDMMC_ERROR_NONE)
{
return (HAL_ERROR);
}
else
{
return (HAL_OK);
}
}
/**
* @brief Remove Linked List node.
* @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
* @param pNode: Pointer to node to remove.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_RemoveNode(MMC_DMALinkedListTypeDef *pLinkedList,
MMC_DMALinkNodeTypeDef *pNode)
{
if (SDMMC_DMALinkedList_RemoveNode(pLinkedList, pNode) != SDMMC_ERROR_NONE)
{
return (HAL_ERROR);
}
else
{
return (HAL_OK);
}
}
/**
* @brief Lock Linked List node.
* @param pNode: Pointer to node to remove.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_LockNode(MMC_DMALinkNodeTypeDef *pNode)
{
if (SDMMC_DMALinkedList_LockNode(pNode) != SDMMC_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
return HAL_OK;
}
}
/**
* @brief Unlock Linked List node.
* @param pNode: Pointer to node to remove.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_UnlockNode(MMC_DMALinkNodeTypeDef *pNode)
{
if (SDMMC_DMALinkedList_UnlockNode(pNode) != SDMMC_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
return HAL_OK;
}
}
/**
* @brief Enable Circular mode for DMA Linked List mode.
* @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_EnableCircularMode(MMC_DMALinkedListTypeDef *pLinkedList)
{
if (SDMMC_DMALinkedList_EnableCircularMode(pLinkedList) != SDMMC_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
return HAL_OK;
}
}
/**
* @brief Disable Circular mode for DMA Linked List mode.
* @param pLinkedList: Pointer to the linkedlist that contains transfer nodes
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(MMC_DMALinkedListTypeDef *pLinkedList)
{
if (SDMMC_DMALinkedList_DisableCircularMode(pLinkedList) != SDMMC_ERROR_NONE)
{
return HAL_ERROR;
}
else
{
return HAL_OK;
}
}
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in linked list buffers.
* linked list should be prepared before call this function .
* @param hmmc: MMC handle
* @param pLinkedList: pointer to first linked list node
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t DmaBase0_reg;
uint32_t DmaBase1_reg;
uint32_t errorstate;
uint32_t add = BlockAdd;
if (hmmc->State == HAL_MMC_STATE_READY)
{
if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
{
if ((NumberOfBlocks % 8U) != 0U)
{
/* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
return HAL_ERROR;
}
if ((BlockAdd % 8U) != 0U)
{
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
return HAL_ERROR;
}
}
hmmc->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER;
hmmc->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE;
hmmc->Instance->IDMABAR = (uint32_t) pLinkedList->pHeadNode;
hmmc->Instance->IDMALAR = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA |
sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */
DmaBase0_reg = hmmc->Instance->IDMABASER;
DmaBase1_reg = hmmc->Instance->IDMABAR;
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_BUSY;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
/* Read Blocks in DMA mode */
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND |
SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Write block(s) to a specified address in a card. The transferred Data are stored linked list nodes buffers .
* linked list should be prepared before call this function .
* @param hmmc: MMC handle
* @param pLinkedList: pointer to first linked list node
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList,
uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t DmaBase0_reg;
uint32_t DmaBase1_reg;
uint32_t add = BlockAdd;
if (hmmc->State == HAL_MMC_STATE_READY)
{
if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
{
if ((NumberOfBlocks % 8U) != 0U)
{
/* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */
hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR;
return HAL_ERROR;
}
if ((BlockAdd % 8U) != 0U)
{
/* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED;
return HAL_ERROR;
}
}
hmmc->Instance->IDMABASER = (uint32_t) pLinkedList->pHeadNode->IDMABASER;
hmmc->Instance->IDMABSIZE = (uint32_t) pLinkedList->pHeadNode->IDMABSIZE;
hmmc->Instance->IDMABAR = (uint32_t) pLinkedList->pHeadNode;
hmmc->Instance->IDMALAR = (uint32_t) SDMMC_IDMALAR_ABR | SDMMC_IDMALAR_ULS | SDMMC_IDMALAR_ULA |
sizeof(SDMMC_DMALinkNodeTypeDef) ; /* Initial configuration */
DmaBase0_reg = hmmc->Instance->IDMABASER;
DmaBase1_reg = hmmc->Instance->IDMABAR;
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_BUSY;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE(hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
/* Write Blocks in DMA mode */
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
if (errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND |
SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_MMC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c
|
C
|
apache-2.0
| 13,788
|
/**
******************************************************************************
* @file stm32u5xx_hal_msp_template.c
* @author MCD Application Team
* @brief HAL MSP module.
* This file template is located in the HAL folder and should be copied
* to the user folder.
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup HAL_MSP HAL MSP module driver
* @brief HAL MSP module.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions
* @{
*/
/**
* @brief Initializes the Global MSP.
* @retval None
*/
void HAL_MspInit(void)
{
}
/**
* @brief DeInitializes the Global MSP.
* @retval None
*/
void HAL_MspDeInit(void)
{
}
/**
* @brief Initialize the PPP MSP.
* @retval None
*/
/*
void HAL_PPP_MspInit(void)
{
}
*/
/**
* @brief DeInitialize the PPP MSP.
* @retval None
*/
/*
void HAL_PPP_MspDeInit(void)
{
}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_msp_template.c
|
C
|
apache-2.0
| 2,370
|
/**
******************************************************************************
* @file stm32u5xx_hal_nand.c
* @author MCD Application Team
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
control NAND flash memories. It uses the FMC layer functions to interface
with NAND devices. This driver is used as follows:
(+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
with control and timing parameters for both common and attribute spaces.
(+) Read NAND flash memory maker and device IDs using the function
HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
structure declared by the function caller.
(+) Access NAND flash memory by read/write operations using the functions
HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
to read/write page(s)/spare area(s). These functions use specific device
information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
structure. The read/write address information is contained by the Nand_Address_Typedef
structure passed as parameter.
(+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
(+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
The erase block address information is contained in the Nand_Address_Typedef
structure passed as parameter.
(+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
(+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
feature or the function HAL_NAND_GetECC() to get the ECC correction code.
(+) You can monitor the NAND device HAL state by calling the function
HAL_NAND_GetState()
[..]
(@) This driver is a set of generic APIs which handle standard NAND flash operations.
If a NAND flash device contains different operations and/or implementations,
it should be implemented separately.
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_NAND_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_NAND_Init
and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
or HAL_NAND_Init function.
When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_NAND_MODULE_ENABLED
/** @defgroup NAND NAND
* @brief NAND HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private Constants ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### NAND Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize
the NAND memory
@endverbatim
* @{
*/
/**
* @brief Perform NAND memory Initialization sequence
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param ComSpace_Timing pointer to Common space timing structure
* @param AttSpace_Timing pointer to Attribute space timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
{
/* Check the NAND handle state */
if (hnand == NULL)
{
return HAL_ERROR;
}
if (hnand->State == HAL_NAND_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hnand->Lock = HAL_UNLOCKED;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
if (hnand->MspInitCallback == NULL)
{
hnand->MspInitCallback = HAL_NAND_MspInit;
}
hnand->ItCallback = HAL_NAND_ITCallback;
/* Init the low level hardware */
hnand->MspInitCallback(hnand);
#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
}
/* Initialize NAND control Interface */
(void)FMC_NAND_Init(hnand->Instance, &(hnand->Init));
/* Initialize NAND common space timing Interface */
(void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
/* Initialize NAND attribute space timing Interface */
(void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
/* Enable the NAND device */
__FMC_NAND_ENABLE(hnand->Instance);
/* Enable FMC Peripheral */
__FMC_ENABLE();
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
return HAL_OK;
}
/**
* @brief Perform NAND memory De-Initialization sequence
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
{
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
if (hnand->MspDeInitCallback == NULL)
{
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
}
/* DeInit the low level hardware */
hnand->MspDeInitCallback(hnand);
#else
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspDeInit(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Configure the NAND registers with their reset values */
(void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
/* Reset the NAND controller state */
hnand->State = HAL_NAND_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief NAND MSP Init
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_MspInit could be implemented in the user file
*/
}
/**
* @brief NAND MSP DeInit
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function handles NAND device interrupt request.
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
{
/* Check NAND interrupt Rising edge flag */
if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
{
/* NAND interrupt callback*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Rising edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
}
/* Check NAND interrupt Level flag */
if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
{
/* NAND interrupt callback*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Level pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
}
/* Check NAND interrupt Falling edge flag */
if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
{
/* NAND interrupt callback*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt Falling edge pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
}
/* Check NAND interrupt FIFO empty flag */
if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
{
/* NAND interrupt callback*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
hnand->ItCallback(hnand);
#else
HAL_NAND_ITCallback(hnand);
#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
/* Clear NAND interrupt FIFO empty pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
}
}
/**
* @brief NAND interrupt feature callback
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_ITCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
==============================================================================
##### NAND Input and Output functions #####
==============================================================================
[..]
This section provides functions allowing to use and control the NAND
memory
@endverbatim
* @{
*/
/**
* @brief Read the NAND memory electronic signature
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pNAND_ID NAND ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
{
__IO uint32_t data = 0;
__IO uint32_t data1 = 0;
uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* Send Read ID command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
__DSB();
/* Read the electronic signature from NAND flash */
if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
{
data = *(__IO uint32_t *)deviceaddress;
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
}
else
{
data = *(__IO uint32_t *)deviceaddress;
data1 = *((__IO uint32_t *)deviceaddress + 4);
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief NAND memory reset
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* Send NAND reset command */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Configure the device: Enter the physical parameters of the device
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
{
hnand->Config.PageSize = pDeviceConfig->PageSize;
hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
hnand->Config.BlockSize = pDeviceConfig->BlockSize;
hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
return HAL_OK;
}
/**
* @brief Read Page(s) from NAND memory block (8-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to destination read buffer
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numpagesread = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToRead;
uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send read page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Go back to read mode */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
*buff = *(uint8_t *)deviceaddress;
buff++;
}
/* Increment read pages number */
numpagesread++;
/* Decrement pages to read */
nbpages--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Read Page(s) from NAND memory block (16-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numpagesread = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToRead;
uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send read page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Go back to read mode */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Calculate PageSize */
if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
{
hnand->Config.PageSize = hnand->Config.PageSize / 2U;
}
else
{
/* Do nothing */
/* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
*buff = *(uint16_t *)deviceaddress;
buff++;
}
/* Increment read pages number */
numpagesread++;
/* Decrement pages to read */
nbpages--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Write Page(s) to NAND memory block (8-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send write page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
/* Write data to memory */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
*(__IO uint8_t *)deviceaddress = *buff;
buff++;
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Increment written pages number */
numpageswritten++;
/* Decrement pages to write */
nbpages--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Write Page(s) to NAND memory block (16-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Send write page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
/* Calculate PageSize */
if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
{
hnand->Config.PageSize = hnand->Config.PageSize / 2U;
}
else
{
/* Do nothing */
/* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
}
/* Write data to memory */
for (index = 0U; index < hnand->Config.PageSize; index++)
{
*(__IO uint16_t *)deviceaddress = *buff;
buff++;
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Increment written pages number */
numpageswritten++;
/* Decrement pages to write */
nbpages--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Read Spare area(s) from NAND memory (8-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numsparearearead = 0U;
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaToRead;
uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) read loop */
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Go back to read mode */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
*buff = *(uint8_t *)deviceaddress;
buff++;
}
/* Increment read spare areas number */
numsparearearead++;
/* Decrement spare areas to read */
nbspare--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Read Spare area(s) from NAND memory (16-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numsparearearead = 0U;
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaToRead;
uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
/* Spare area(s) read loop */
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Config.ExtraCommandEnable == ENABLE)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Go back to read mode */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
__DSB();
}
/* Get Data into Buffer */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
*buff = *(uint16_t *)deviceaddress;
buff++;
}
/* Increment read spare areas number */
numsparearearead++;
/* Decrement spare areas to read */
nbspare--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Write Spare area(s) to NAND memory (8-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numspareareawritten = 0U;
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* Page address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) write loop */
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
/* Write data to memory */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
*(__IO uint8_t *)deviceaddress = *buff;
buff++;
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Increment written spare areas number */
numspareareawritten++;
/* Decrement spare areas to write */
nbspare--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Write Spare area(s) to NAND memory (16-bits addressing)
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceaddress;
uint32_t numspareareawritten = 0U;
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* NAND raw address calculation */
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Column in page address */
columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
/* Spare area(s) write loop */
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* Cards with page size <= 512 bytes */
if ((hnand->Config.PageSize) <= 512U)
{
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
else /* (hnand->Config.PageSize) > 512 */
{
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
}
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
__DSB();
}
}
/* Write data to memory */
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
{
*(__IO uint16_t *)deviceaddress = *buff;
buff++;
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
{
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Increment written spare areas number */
numspareareawritten++;
/* Decrement spare areas to write */
nbspare--;
/* Increment the NAND address */
nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief NAND memory Block erase
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t deviceaddress;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnand);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* Send Erase block command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
__DSB();
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Increment the NAND memory address
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress pointer to NAND address structure
* @retval The new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t status = NAND_VALID_ADDRESS;
/* Increment page address */
pAddress->Page++;
/* Check NAND address is valid */
if (pAddress->Page == hnand->Config.BlockSize)
{
pAddress->Page = 0;
pAddress->Block++;
if (pAddress->Block == hnand->Config.PlaneSize)
{
pAddress->Block = 0;
pAddress->Plane++;
if (pAddress->Plane == (hnand->Config.PlaneNbr))
{
status = NAND_INVALID_ADDRESS;
}
}
}
return (status);
}
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NAND Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
* @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
pNAND_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hnand);
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
{
case HAL_NAND_MSP_INIT_CB_ID :
hnand->MspInitCallback = pCallback;
break;
case HAL_NAND_MSP_DEINIT_CB_ID :
hnand->MspDeInitCallback = pCallback;
break;
case HAL_NAND_IT_CB_ID :
hnand->ItCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hnand->State == HAL_NAND_STATE_RESET)
{
switch (CallbackId)
{
case HAL_NAND_MSP_INIT_CB_ID :
hnand->MspInitCallback = pCallback;
break;
case HAL_NAND_MSP_DEINIT_CB_ID :
hnand->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hnand);
return status;
}
/**
* @brief Unregister a User NAND Callback
* NAND Callback is redirected to the weak (surcharged) predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
* @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hnand);
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
{
case HAL_NAND_MSP_INIT_CB_ID :
hnand->MspInitCallback = HAL_NAND_MspInit;
break;
case HAL_NAND_MSP_DEINIT_CB_ID :
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
break;
case HAL_NAND_IT_CB_ID :
hnand->ItCallback = HAL_NAND_ITCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hnand->State == HAL_NAND_STATE_RESET)
{
switch (CallbackId)
{
case HAL_NAND_MSP_INIT_CB_ID :
hnand->MspInitCallback = HAL_NAND_MspInit;
break;
case HAL_NAND_MSP_DEINIT_CB_ID :
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hnand);
return status;
}
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
* @brief management functions
*
@verbatim
==============================================================================
##### NAND Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the NAND interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically NAND ECC feature.
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
{
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Enable ECC feature */
(void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Disables dynamically FMC_NAND ECC feature.
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
{
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Disable ECC feature */
(void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Disables dynamically NAND ECC feature.
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param ECCval pointer to ECC value
* @param Timeout maximum timeout to wait
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
{
HAL_StatusTypeDef status;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnand->State == HAL_NAND_STATE_READY)
{
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Get NAND ECC value */
status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @}
*/
/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### NAND State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the NAND controller
and the data flow.
@endverbatim
* @{
*/
/**
* @brief return the NAND state
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL state
*/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
{
return hnand->State;
}
/**
* @brief NAND memory read status
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval NAND status
*/
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
{
uint32_t data;
uint32_t deviceaddress;
UNUSED(hnand);
/* Identify the device address */
deviceaddress = NAND_DEVICE;
/* Send Read status operation command */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
/* Read status register data */
data = *(__IO uint8_t *)deviceaddress;
/* Return the status */
if ((data & NAND_ERROR) == NAND_ERROR)
{
return NAND_ERROR;
}
else if ((data & NAND_READY) == NAND_READY)
{
return NAND_READY;
}
else
{
return NAND_BUSY;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_NAND_MODULE_ENABLED */
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c
|
C
|
apache-2.0
| 72,431
|
/**
******************************************************************************
* @file stm32u5xx_hal_nor.c
* @author MCD Application Team
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
control NOR flash memories. It uses the FMC layer functions to interface
with NOR devices. This driver is used as follows:
(+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
with control and timing parameters for both normal and extended mode.
(+) Read NOR flash memory manufacturer code and device IDs using the function
HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
structure declared by the function caller.
(+) Access NOR flash memory by read/write data unit operations using the functions
HAL_NOR_Read(), HAL_NOR_Program().
(+) Perform NOR flash erase block/chip operations using the functions
HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
(+) Read the NOR flash CFI (common flash interface) IDs using the function
HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
structure declared by the function caller.
(+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
(+) You can monitor the NOR device HAL state by calling the function
HAL_NOR_GetState()
[..]
(@) This driver is a set of generic APIs which handle standard NOR flash operations.
If a NOR flash device contains different operations and/or implementations,
it should be implemented separately.
*** NOR HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in NOR HAL driver.
(+) NOR_WRITE : NOR memory write data to specified address
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_NOR_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_NOR_Init
and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
or HAL_NOR_Init function.
When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#ifdef HAL_NOR_MODULE_ENABLED
/** @defgroup NOR NOR
* @brief NOR driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup NOR_Private_Defines NOR Private Defines
* @{
*/
/* Constants to define address to set to write a command */
#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
/* Constants to define data to program a command */
#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
#define NOR_CMD_DATA_SECOND (uint16_t)0x0055
#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
#define NOR_CMD_DATA_CFI (uint16_t)0x0098
#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
#define NOR_CMD_CONFIRM (uint16_t)0x00D0
#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
/* Mask on NOR STATUS REGISTER */
#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
/* Address of the primary command set */
#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup NOR_Private_Variables NOR Private Variables
* @{
*/
static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup NOR_Exported_Functions NOR Exported Functions
* @{
*/
/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### NOR Initialization and de_initialization functions #####
==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize
the NOR memory
@endverbatim
* @{
*/
/**
* @brief Perform the NOR memory Initialization sequence
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param Timing pointer to NOR control timing structure
* @param ExtTiming pointer to NOR extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR handle parameter */
if (hnor == NULL)
{
return HAL_ERROR;
}
if (hnor->State == HAL_NOR_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hnor->Lock = HAL_UNLOCKED;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
if (hnor->MspInitCallback == NULL)
{
hnor->MspInitCallback = HAL_NOR_MspInit;
}
/* Init the low level hardware */
hnor->MspInitCallback(hnor);
#else
/* Initialize the low level hardware (MSP) */
HAL_NOR_MspInit(hnor);
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
}
/* Initialize NOR control Interface */
(void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
/* Initialize NOR timing Interface */
(void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
/* Initialize NOR extended mode timing Interface */
(void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
/* Initialize NOR Memory Data Width*/
if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
{
uwNORMemoryDataWidth = NOR_MEMORY_8B;
}
else
{
uwNORMemoryDataWidth = NOR_MEMORY_16B;
}
/* Enable FMC Peripheral */
__FMC_ENABLE();
/* Initialize the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE)
{
(void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_PROTECTED;
}
else
{
/* Get the value of the command set */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
status = HAL_NOR_ReturnToReadMode(hnor);
}
return status;
}
/**
* @brief Perform NOR memory De-Initialization sequence
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
{
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
if (hnor->MspDeInitCallback == NULL)
{
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
}
/* DeInit the low level hardware */
hnor->MspDeInitCallback(hnor);
#else
/* De-Initialize the low level hardware (MSP) */
HAL_NOR_MspDeInit(hnor);
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
/* Configure the NOR registers with their reset values */
(void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
/* Reset the NOR controller state */
hnor->State = HAL_NOR_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hnor);
return HAL_OK;
}
/**
* @brief NOR MSP Init
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval None
*/
__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NOR_MspInit could be implemented in the user file
*/
}
/**
* @brief NOR MSP DeInit
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval None
*/
__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NOR_MspDeInit could be implemented in the user file
*/
}
/**
* @brief NOR MSP Wait for Ready/Busy signal
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param Timeout Maximum timeout value
* @retval None
*/
__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
UNUSED(Timeout);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NOR_MspWait could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
==============================================================================
##### NOR Input and Output functions #####
==============================================================================
[..]
This section provides functions allowing to use and control the NOR memory
@endverbatim
* @{
*/
/**
* @brief Read NOR flash IDs
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param pNOR_ID pointer to NOR ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
if (state == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send read ID command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Read the NOR IDs */
pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
DEVICE_CODE1_ADDR);
pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
DEVICE_CODE2_ADDR);
pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
DEVICE_CODE3_ADDR);
}
/* Check the NOR controller state */
hnor->State = state;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Returns the NOR memory to Read mode.
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
if (state == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Check the NOR controller state */
hnor->State = state;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Read data from NOR memory
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param pAddress pointer to Device address
* @param pData pointer to read data
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
if (state == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Read the data */
*pData = (uint16_t)(*(__IO uint32_t *)pAddress);
}
/* Check the NOR controller state */
hnor->State = state;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Program data to NOR memory
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param pAddress Device address
* @param pData pointer to the data to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send program data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Write the data */
NOR_WRITE(pAddress, *pData);
}
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Reads a half-word buffer from the NOR memory.
* @param hnor pointer to the NOR handle
* @param uwAddress NOR memory internal address to read from.
* @param pData pointer to the buffer that receives the data read from the
* NOR memory.
* @param uwBufferSize number of Half word to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize)
{
uint32_t deviceaddress;
uint32_t size = uwBufferSize;
uint32_t address = uwAddress;
uint16_t *data = pData;
HAL_NOR_StateTypeDef state;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
if (state == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Read buffer */
while (size > 0U)
{
*data = *(__IO uint16_t *)address;
data++;
address += 2U;
size--;
}
}
/* Check the NOR controller state */
hnor->State = state;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Writes a half-word buffer to the NOR memory. This function must be used
only with S29GL128P NOR memory.
* @param hnor pointer to the NOR handle
* @param uwAddress NOR memory internal start write address
* @param pData pointer to source data buffer.
* @param uwBufferSize Size of the buffer to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize)
{
uint16_t *p_currentaddress;
const uint16_t *p_endaddress;
uint16_t *data = pData;
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Initialize variables */
p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
/* Write Buffer Load Command */
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
/* Write Buffer Load Command */
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
if (status != HAL_ERROR)
{
/* Load Data into NOR Buffer */
while (p_currentaddress <= p_endaddress)
{
NOR_WRITE(p_currentaddress, *data);
data++;
p_currentaddress ++;
}
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
}
else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
{
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
}
}
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Erase the specified block of the NOR memory
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param BlockAddress Block to erase address
* @param Address Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send block erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Erase the entire NOR chip.
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param Address Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
uint32_t deviceaddress;
HAL_StatusTypeDef status = HAL_OK;
UNUSED(Address);
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send NOR chip erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
}
else
{
/* Primary command set not supported by the driver */
status = HAL_ERROR;
}
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return status;
}
/**
* @brief Read NOR flash CFI IDs
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param pNOR_CFI pointer to NOR CFI IDs structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
/* Check the NOR controller state */
state = hnor->State;
if (state == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
else if (state == HAL_NOR_STATE_PROTECTED)
{
return HAL_ERROR;
}
else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Send read CFI query command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
/* read the NOR CFI information */
pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
/* Check the NOR controller state */
hnor->State = state;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NOR Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
pNOR_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hnor);
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_NOR_MSP_INIT_CB_ID :
hnor->MspInitCallback = pCallback;
break;
case HAL_NOR_MSP_DEINIT_CB_ID :
hnor->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hnor);
return status;
}
/**
* @brief Unregister a User NOR Callback
* NOR Callback is redirected to the weak (surcharged) predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
/* Process locked */
__HAL_LOCK(hnor);
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
case HAL_NOR_MSP_INIT_CB_ID :
hnor->MspInitCallback = HAL_NOR_MspInit;
break;
case HAL_NOR_MSP_DEINIT_CB_ID :
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hnor);
return status;
}
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
/**
* @}
*/
/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
* @brief management functions
*
@verbatim
==============================================================================
##### NOR Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the NOR interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically NOR write operation.
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Enable write operation */
(void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Disables dynamically NOR write operation.
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Disable write operation */
(void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_PROTECTED;
/* Process unlocked */
__HAL_UNLOCK(hnor);
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### NOR State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the NOR controller
and the data flow.
@endverbatim
* @{
*/
/**
* @brief return the NOR controller state
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval NOR controller state
*/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
{
return hnor->State;
}
/**
* @brief Returns the NOR operation status.
* @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param Address Device address
* @param Timeout NOR programming Timeout
* @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
* or HAL_NOR_STATUS_TIMEOUT
*/
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
uint16_t tmpsr1;
uint16_t tmpsr2;
uint32_t tickstart;
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
HAL_NOR_MspWait(hnor, Timeout);
/* Get the NOR memory operation status -------------------------------------*/
/* Get tick */
tickstart = HAL_GetTick();
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
status = HAL_NOR_STATUS_TIMEOUT;
}
}
/* Read NOR status register (DQ6 and DQ5) */
tmpsr1 = *(__IO uint16_t *)Address;
tmpsr2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
{
return HAL_NOR_STATUS_SUCCESS ;
}
if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
status = HAL_NOR_STATUS_ONGOING;
}
tmpsr1 = *(__IO uint16_t *)Address;
tmpsr2 = *(__IO uint16_t *)Address;
/* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
{
return HAL_NOR_STATUS_SUCCESS;
}
if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
{
return HAL_NOR_STATUS_ERROR;
}
}
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
do
{
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
tmpsr2 = *(__IO uint16_t *)(Address);
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
return HAL_NOR_STATUS_TIMEOUT;
}
}
} while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
tmpsr1 = *(__IO uint16_t *)(Address);
if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
{
/* Clear the Status Register */
NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
status = HAL_NOR_STATUS_ERROR;
}
else
{
status = HAL_NOR_STATUS_SUCCESS;
}
}
else
{
/* Primary command set not supported by the driver */
status = HAL_NOR_STATUS_ERROR;
}
/* Return the operation status */
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_NOR_MODULE_ENABLED */
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nor.c
|
C
|
apache-2.0
| 47,016
|
/**
******************************************************************************
* @file stm32u5xx_hal_opamp.c
* @author MCD Application Team
* @brief OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifier(s) peripheral:
* + OPAMP configuration
* + OPAMP calibration
* Thanks to
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### OPAMP Peripheral Features #####
==============================================================================
[..] The device integrates 1 or 2 operational amplifiers OPAMP1 & OPAMP2
(#) The OPAMP(s) provide(s) several exclusive running modes.
(++) Standalone mode
(++) Programmable Gain Amplifier (PGA) mode (Resistor feedback output)
(++) Follower mode
(#) Each OPAMP(s) can be configured in normal and low power mode with different speeds.
(#) The OPAMP(s) provide(s) calibration capabilities.
(++) Calibration aims at correcting some offset for running mode.
(++) The OPAMP uses either factory calibration settings OR user defined
calibration (trimming) settings (i.e. trimming mode).
(++) The user defined settings can be figured out using self calibration
handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
(++) HAL_OPAMP_SelfCalibrate:
(+++) Runs automatically the calibration.
(+++) Enables the user trimming mode
(+++) Updates the init structure with trimming values with fresh calibration
results.
The user may store the calibration results for larger
(ex monitoring the trimming as a function of temperature for instance)
(+++) HAL_OPAMPEx_SelfCalibrateAll
runs calibration of all OPAMPs in parallel to save search time.
(#) Running mode: Standalone mode
(++) Gain is set externally (gain depends on external loads).
(++) Follower mode also possible externally by connecting the inverting input to
the output.
(#) Running mode: Follower mode
(++) No Inverting Input is connected.
(#) Running mode: Programmable Gain Amplifier (PGA) mode
(Resistor feedback output)
(++) The OPAMP(s) output(s) can be internally connected to resistor feedback
output.
(++) OPAMP gain is either 2, 4, 8 or 16.
(#) The OPAMPs inverting input can be selected according to the Reference Manual
"OPAMP function description" chapter.
(#) The OPAMPs non inverting input can be selected according to the Reference Manual
"OPAMP function description" chapter.
##### How to use this driver #####
==============================================================================
[..]
*** Speed & power mode ***
============================================
[..] To run in low power mode with different speed:
(#) Configure the OPAMP using HAL_OPAMP_Init() function:
(++) Select OPAMP_POWERMODE_LOWPOWER_NORMALSPEED
(++) Select OPAMP_POWERMODE_LOWPOWER_HIGHSPEED
(++) Select OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED
(++) Select OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED
*** Calibration ***
============================================
[..] To run the OPAMP calibration self calibration:
(#) Start calibration using HAL_OPAMP_SelfCalibrate.
Store the calibration results.
*** Running mode ***
============================================
[..] To use the OPAMP, perform the following steps:
(#) Fill in the HAL_OPAMP_MspInit() to
(++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
(++) Configure the OPAMP input and output in analog mode using
HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
(#) Registrate Callbacks
(++) The compilation define USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
(++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+++) MspInitCallback : OPAMP MspInit.
(+++) MspDeInitCallback : OPAMP MspFeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+++) MspInitCallback : OPAMP MspInit.
(+++) MspDeInitCallback : OPAMP MspdeInit.
(+++) All Callbacks
(#) Configure the OPAMP using HAL_OPAMP_Init() function:
(++) Select the mode
(++) Select the inverting input
(++) Select the non-inverting input
(++) If PGA mode is enabled, Select if inverting input is connected.
(++) Select either factory or user defined trimming mode.
(++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
(typically values set by HAL_OPAMP_SelfCalibrate function).
(#) Enable the OPAMP using HAL_OPAMP_Start() function.
(#) Disable the OPAMP using HAL_OPAMP_Stop() function.
(#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
Caution: On STM32U5, HAL OPAMP lock is software lock only (not
hardware lock as on some other STM32 devices)
(#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.
*** Running mode: change of configuration while OPAMP ON ***
============================================
[..] To Re-configure OPAMP when OPAMP is ON (change on the fly)
(#) If needed, fill in the HAL_OPAMP_MspInit()
(++) This is the case for instance if you wish to use new OPAMP I/O
(#) Configure the OPAMP using HAL_OPAMP_Init() function:
(++) As in configure case, select first the parameters you wish to modify.
(#) Change from low power mode to normal power mode (& vice versa) requires
first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
alone.
@endverbatim
******************************************************************************
Table 1. OPAMPs inverting/non-inverting inputs for the STM32U5 devices:
+------------------------------------------------------------------------|
| | | OPAMP1 | OPAMP2 |
|-----------------|---------|----------------------|---------------------|
| Inverting Input | VM_SEL | | |
| | | IO0-> PA1 | IO0-> PA7 |
| | | LOW LEAKAGE IO (2) | LOW LEAKAGE IO (2) |
| | | Not connected | Not connected |
| (1) | | PGA mode only | PGA mode only |
|-----------------|---------|----------------------|---------------------|
| Non Inverting | VP_SEL | | |
| | | IO0-> PA0 (GPIO) | IO0-> PA6 (GPIO) |
| Input | | DAC1_OUT1 internal | DAC1_OUT2 internal |
+------------------------------------------------------------------------|
(1): NA in follower mode.
(2): Available on some package only (ex: BGA132 and BGA169).
Table 2. OPAMPs outputs for the STM32U5 devices:
+-------------------------------------------------------------------------------+
| | | OPAMP1 | OPAMP2 |
|-----------------|--------|-----------------------|----------------------------|
| Output | VOUT | - PA3 | - PB0 |
| | | - ADC1_IN8 if | - ADC1_IN15 & ADC4_IN18 if |
| | | connected internally | connected internally |
|-----------------|--------|-----------------------|----------------------------|
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup OPAMP OPAMP
* @brief OPAMP module driver
* @{
*/
#ifdef HAL_OPAMP_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup OPAMP_Private_Constants
* @{
*/
/* CSR register reset value */
#define OPAMP_CSR_RESET_VALUE ((uint32_t)0x00000000)
#define OPAMP_CSR_RESET_BITS (OPAMP_CSR_OPAEN | OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE |\
OPAMP_CSR_PGA_GAIN | OPAMP_CSR_VM_SEL | OPAMP_CSR_VP_SEL |\
OPAMP_CSR_CALON | OPAMP_CSR_USERTRIM | OPAMP_CSR_CALSEL |\
OPAMP_CSR_HSM)
/* CSR Init masks */
#define OPAMP_CSR_INIT_MASK_PGA (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_PGA_GAIN |\
OPAMP_CSR_VM_SEL | OPAMP_CSR_VP_SEL | OPAMP_CSR_USERTRIM |\
OPAMP_CSR_HSM)
#define OPAMP_CSR_INIT_MASK_FOLLOWER (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_VP_SEL |\
OPAMP_CSR_USERTRIM | OPAMP_CSR_HSM)
#define OPAMP_CSR_INIT_MASK_STANDALONE (OPAMP_CSR_OPALPM | OPAMP_CSR_OPAMODE| OPAMP_CSR_VP_SEL |\
OPAMP_CSR_VM_SEL | OPAMP_CSR_USERTRIM | OPAMP_CSR_HSM)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
* @{
*/
/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Initializes the OPAMP according to the specified
* parameters in the OPAMP_InitTypeDef and initialize the associated handle.
* @note If the selected opamp is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset.
* @param hopamp: OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t updateotrlpotr;
/* Check the OPAMP handle allocation and lock status */
/* Init not allowed if calibration is ongoing */
if (hopamp == NULL)
{
return HAL_ERROR;
}
else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
{
return HAL_ERROR;
}
else if (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
{
return HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
/* Set OPAMP parameters */
assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
if (hopamp->State == HAL_OPAMP_STATE_RESET)
{
if (hopamp->MspInitCallback == NULL)
{
hopamp->MspInitCallback = HAL_OPAMP_MspInit;
}
}
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
{
assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput));
}
if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
{
assert_param(IS_OPAMP_INVERTING_INPUT_PGA(hopamp->Init.InvertingInput));
}
if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
{
assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
}
assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
{
if ((hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
(hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
{
assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
}
else
{
assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePLowPower));
assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower));
}
}
if (hopamp->State == HAL_OPAMP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hopamp->Lock = HAL_UNLOCKED;
}
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
hopamp->MspInitCallback(hopamp);
#else
/* Call MSP init function */
HAL_OPAMP_MspInit(hopamp);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
/* Set operating mode */
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
if (hopamp->Init.Mode == OPAMP_PGA_MODE)
{
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \
hopamp->Init.PowerMode | \
hopamp->Init.Mode | \
hopamp->Init.PgaGain | \
hopamp->Init.InvertingInput | \
hopamp->Init.NonInvertingInput | \
hopamp->Init.UserTrimming);
}
if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
{
/* In Follower mode InvertingInput is Not Applicable */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_FOLLOWER, \
hopamp->Init.PowerMode | \
hopamp->Init.Mode | \
hopamp->Init.NonInvertingInput | \
hopamp->Init.UserTrimming);
}
if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE)
{
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \
hopamp->Init.PowerMode | \
hopamp->Init.Mode | \
hopamp->Init.InvertingInput | \
hopamp->Init.NonInvertingInput | \
hopamp->Init.UserTrimming);
}
if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
{
/* Set power mode and associated calibration parameters */
if ((hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_NORMALSPEED) && \
(hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_HIGHSPEED))
{
/* OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED or OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED */
/* Set calibration mode (factory or user) and values for */
/* transistors differential pair high (PMOS) and low (NMOS) for */
/* normal mode. */
updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \
| (hopamp->Init.TrimmingValueN));
MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
}
else
{
/* OPAMP_POWERMODE_LOWPOWER_HIGHSPEED or OPAMP_POWERMODE_LOWPOWER_NORMALSPEED */
/* transistors differential pair high (PMOS) and low (NMOS) for */
/* low power mode. */
updateotrlpotr = (((hopamp->Init.TrimmingValuePLowPower) << (OPAMP_INPUT_NONINVERTING)) \
| (hopamp->Init.TrimmingValueNLowPower));
MODIFY_REG(hopamp->Instance->LPOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
}
}
/* Set the power supply range to high for performance purpose */
/* The OPAMP_CSR_OPARANGE is common configuration for all OPAMPs */
/* bit OPAMP_CSR_OPARANGE applies for both OPAMPs */
MODIFY_REG(OPAMP1->CSR, OPAMP_CSR_OPARANGE, OPAMP_CSR_OPARANGE);
/* Update the OPAMP state*/
if (hopamp->State == HAL_OPAMP_STATE_RESET)
{
/* From RESET state to READY State */
hopamp->State = HAL_OPAMP_STATE_READY;
}
/* else: remain in READY or BUSY state (no update) */
return status;
}
}
/**
* @brief DeInitialize the OPAMP peripheral.
* @note Deinitialization can be performed if the OPAMP configuration is locked.
* (the lock is SW in U5)
* @param hopamp: OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the OPAMP handle allocation */
/* DeInit not allowed if calibration is ongoing */
if (hopamp == NULL)
{
status = HAL_ERROR;
}
else if (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
{
status = HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
/* Set OPAMP_CSR register to reset value */
/* Mind that OPAMP1_CSR_OPARANGE of CSR of OPAMP1 remains unchanged (applies to both OPAMPs) */
/* OPAMP shall be disabled first separately */
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAEN);
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_BITS, OPAMP_CSR_RESET_VALUE);
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
if (hopamp->MspDeInitCallback == NULL)
{
hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
}
/* DeInit the low level hardware */
hopamp->MspDeInitCallback(hopamp);
#else
/* DeInit the low level hardware: GPIO, CLOCK and NVIC */
HAL_OPAMP_MspDeInit(hopamp);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
/* Update the OPAMP state*/
hopamp->State = HAL_OPAMP_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hopamp);
}
return status;
}
/**
* @brief Initialize the OPAMP MSP.
* @param hopamp: OPAMP handle
* @retval None
*/
__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hopamp);
/* NOTE : This function should not be modified, when the callback is needed,
the function "HAL_OPAMP_MspInit()" must be implemented in the user file.
*/
}
/**
* @brief DeInitialize OPAMP MSP.
* @param hopamp: OPAMP handle
* @retval None
*/
__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hopamp);
/* NOTE : This function should not be modified, when the callback is needed,
the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the OPAMP
start, stop and calibration actions.
@endverbatim
* @{
*/
/**
* @brief Start the OPAMP.
* @param hopamp: OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
if (hopamp == NULL)
{
status = HAL_ERROR;
}
else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
{
status = HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
if (hopamp->State == HAL_OPAMP_STATE_READY)
{
/* Enable the selected opamp */
SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAEN);
/* Update the OPAMP state*/
/* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
hopamp->State = HAL_OPAMP_STATE_BUSY;
}
else
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Stop the OPAMP.
* @param hopamp: OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
/* Check if OPAMP calibration ongoing */
if (hopamp == NULL)
{
status = HAL_ERROR;
}
else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
{
status = HAL_ERROR;
}
else if (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
{
status = HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
if (hopamp->State == HAL_OPAMP_STATE_BUSY)
{
/* Disable the selected opamp */
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAEN);
/* Update the OPAMP state*/
/* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
hopamp->State = HAL_OPAMP_STATE_READY;
}
else
{
status = HAL_ERROR;
}
}
return status;
}
/**
* @brief Run the self calibration of one OPAMP.
* @note Calibration is performed in the mode specified in OPAMP init
* structure (mode normal or low-power). To perform calibration for
* both modes, repeat this function twice after OPAMP init structure
* accordingly updated.
* @note Calibration runs about 10 ms.
* @param hopamp handle
* @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t trimmingvaluen;
uint32_t trimmingvaluep;
uint32_t delta;
uint32_t opampmode;
__IO uint32_t *tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
if (hopamp == NULL)
{
status = HAL_ERROR;
}
else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
{
status = HAL_ERROR;
}
else
{
/* Check if OPAMP in calibration mode and calibration not yet enable */
if (hopamp->State == HAL_OPAMP_STATE_READY)
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
/* Save OPAMP mode as in */
/* the calibration is not working in PGA mode */
opampmode = READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE);
/* Use of standalone mode */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE);
/* user trimming values are used for offset calibration */
SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
/* Select trimming settings depending on power mode */
if ((hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
(hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
{
tmp_opamp_reg_trimming = &hopamp->Instance->OTR;
}
else
{
tmp_opamp_reg_trimming = &hopamp->Instance->LPOTR;
}
/* Enable calibration */
SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
/* 1st calibration - N */
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALSEL);
/* Enable the selected opamp */
SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAEN);
/* Init trimming counter */
/* Medium value */
trimmingvaluen = 16U;
delta = 8U;
while (delta != 0U)
{
/* Set candidate trimming */
/* OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED or OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED */
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
/* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
{
/* OPAMP_CSR_CALOUT is HIGH try higher trimming */
trimmingvaluen -= delta;
}
else
{
/* OPAMP_CSR_CALOUT is LOW try lower trimming */
trimmingvaluen += delta;
}
/* Divide range by 2 to continue dichotomy sweep */
delta >>= 1U;
}
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */
/* Set candidate trimming */
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
/* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U)
{
/* Trimming value is actually one value more */
trimmingvaluen++;
/* Set right trimming */
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
}
/* 2nd calibration - P */
SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALSEL);
/* Init trimming counter */
/* Medium value */
trimmingvaluep = 16U;
delta = 8U;
while (delta != 0U)
{
/* Set candidate trimming */
/* OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED or OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED */
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep << OPAMP_INPUT_NONINVERTING));
/* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
{
/* OPAMP_CSR_CALOUT is HIGH try higher trimming */
trimmingvaluep -= delta;
}
else
{
/* OPAMP_CSR_CALOUT is LOW try lower trimming */
trimmingvaluep += delta;
}
/* Divide range by 2 to continue dichotomy sweep */
delta >>= 1U;
}
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
/* Set candidate trimming */
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep << OPAMP_INPUT_NONINVERTING));
/* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
{
/* Trimming value is actually one value more */
trimmingvaluep++;
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep << OPAMP_INPUT_NONINVERTING));
}
/* Disable the OPAMP */
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_OPAEN);
/* Disable calibration & set normal mode (operating mode) */
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
/* Self calibration is successful */
/* Store calibration(user trimming) results in init structure. */
/* Set user trimming mode */
hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
/* Affect calibration parameters depending on mode normal/low power */
if ((hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_NORMALSPEED) && \
(hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_HIGHSPEED))
{
/* Write calibration result N */
hopamp->Init.TrimmingValueN = trimmingvaluen;
/* Write calibration result P */
hopamp->Init.TrimmingValueP = trimmingvaluep;
}
else
{
/* Write calibration result N */
hopamp->Init.TrimmingValueNLowPower = trimmingvaluen;
/* Write calibration result P */
hopamp->Init.TrimmingValuePLowPower = trimmingvaluep;
}
/* Restore OPAMP mode after calibration */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode);
}
else
{
/* OPAMP can not be calibrated from this mode */
status = HAL_ERROR;
}
}
return status;
}
/**
* @}
*/
/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the OPAMP data
transfers.
@endverbatim
* @{
*/
/**
* @brief Lock the selected OPAMP configuration.
* @note On STM32U5, HAL OPAMP lock is software lock only (in
* contrast of hardware lock available on some other STM32
* devices).
* @param hopamp: OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
/* OPAMP can be locked when enabled and running in normal mode */
/* It is meaningless otherwise */
if (hopamp == NULL)
{
status = HAL_ERROR;
}
else if (hopamp->State == HAL_OPAMP_STATE_BUSY)
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
/* OPAMP state changed to locked */
hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Return the OPAMP factory trimming value.
* @note On STM32U5 OPAMP, user can retrieve factory trimming if
* OPAMP has never been set to user trimming before.
* Therefore, this function must be called when OPAMP init
* parameter "UserTrimming" is set to trimming factory,
* and before OPAMP calibration (function
* "HAL_OPAMP_SelfCalibrate()").
* Otherwise, factory trimming value cannot be retrieved and
* error status is returned.
* @param hopamp : OPAMP handle
* @param trimmingoffset : Trimming offset (P or N)
* This parameter must be a value of @ref OPAMP_FactoryTrimming
* @note Calibration parameter retrieved is corresponding to the mode
* specified in OPAMP init structure (mode normal or low-power).
* To retrieve calibration parameters for both modes, repeat this
* function after OPAMP init structure accordingly updated.
* @retval Trimming value (P or N): range: 0->31
* or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
*
*/
HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
{
HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
__IO uint32_t *tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */
/* Check the OPAMP handle allocation */
/* Value can be retrieved in HAL_OPAMP_STATE_READY state */
if (hopamp == NULL)
{
return OPAMP_FACTORYTRIMMING_DUMMY;
}
/* Check the OPAMP handle allocation */
/* Value can be retrieved in HAL_OPAMP_STATE_READY state */
if (hopamp->State == HAL_OPAMP_STATE_READY)
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
/* Check the trimming mode */
if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM) != 0U)
{
/* This function must called when OPAMP init parameter "UserTrimming" */
/* is set to trimming factory, and before OPAMP calibration (function */
/* "HAL_OPAMP_SelfCalibrate()"). */
/* Otherwise, factory trimming value cannot be retrieved and error */
/* status is returned. */
trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY;
}
else
{
/* Select trimming settings depending on power mode */
if ((hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
(hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
{
tmp_opamp_reg_trimming = &OPAMP->OTR;
}
else
{
tmp_opamp_reg_trimming = &OPAMP->LPOTR;
}
/* Get factory trimming */
if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
{
/* OPAMP_FACTORYTRIMMING_P */
trimmingvalue = ((*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETP) >> OPAMP_INPUT_NONINVERTING;
}
else
{
/* OPAMP_FACTORYTRIMMING_N */
trimmingvalue = (*tmp_opamp_reg_trimming) & OPAMP_OTR_TRIMOFFSETN;
}
}
}
else
{
return OPAMP_FACTORYTRIMMING_DUMMY;
}
return trimmingvalue;
}
/**
* @}
*/
/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the OPAMP handle state.
* @param hopamp : OPAMP handle
* @retval HAL state
*/
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
{
/* Check the OPAMP handle allocation */
if (hopamp == NULL)
{
return HAL_OPAMP_STATE_RESET;
}
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
/* Return OPAMP handle state */
return hopamp->State;
}
/**
* @}
*/
/** @defgroup OPAMP_Exported_Functions_Group5 Peripheral Callback functions
* @brief Peripheral Callback functions
*
@verbatim
===============================================================================
##### Peripheral Callback functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User OPAMP Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hopamp : OPAMP handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MspInit callback ID
* @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MspDeInit callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID,
pOPAMP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hopamp);
if (hopamp->State == HAL_OPAMP_STATE_READY)
{
switch (CallbackID)
{
case HAL_OPAMP_MSP_INIT_CB_ID :
hopamp->MspInitCallback = pCallback;
break;
case HAL_OPAMP_MSP_DEINIT_CB_ID :
hopamp->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hopamp->State == HAL_OPAMP_STATE_RESET)
{
switch (CallbackID)
{
case HAL_OPAMP_MSP_INIT_CB_ID :
hopamp->MspInitCallback = pCallback;
break;
case HAL_OPAMP_MSP_DEINIT_CB_ID :
hopamp->MspDeInitCallback = pCallback;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hopamp);
return status;
}
/**
* @brief Unregister a User OPAMP Callback
* OPAMP Callback is redirected to the weak (surcharged) predefined callback
* @param hopamp : OPAMP handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MSP Init Callback ID
* @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MSP DeInit Callback ID
* @arg @ref HAL_OPAMP_ALL_CB_ID OPAMP All Callbacks
* @retval status
*/
HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hopamp);
if (hopamp->State == HAL_OPAMP_STATE_READY)
{
switch (CallbackID)
{
case HAL_OPAMP_MSP_INIT_CB_ID :
hopamp->MspInitCallback = HAL_OPAMP_MspInit;
break;
case HAL_OPAMP_MSP_DEINIT_CB_ID :
hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
break;
case HAL_OPAMP_ALL_CB_ID :
hopamp->MspInitCallback = HAL_OPAMP_MspInit;
hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hopamp->State == HAL_OPAMP_STATE_RESET)
{
switch (CallbackID)
{
case HAL_OPAMP_MSP_INIT_CB_ID :
hopamp->MspInitCallback = HAL_OPAMP_MspInit;
break;
case HAL_OPAMP_MSP_DEINIT_CB_ID :
hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit;
break;
default :
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* update return status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hopamp);
return status;
}
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_OPAMP_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp.c
|
C
|
apache-2.0
| 40,154
|
/**
******************************************************************************
* @file stm32u5xx_hal_opamp_ex.c
* @author MCD Application Team
* @brief Extended OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
* peripheral:
* + Extended Initialization and de-initialization functions
* + Extended Peripheral Control functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup OPAMPEx OPAMPEx
* @brief OPAMP Extended HAL module driver
* @{
*/
#ifdef HAL_OPAMP_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
* @{
*/
/** @addtogroup OPAMPEx_Exported_Functions_Group1
* @brief Extended operation functions
*
@verbatim
===============================================================================
##### Extended IO operation functions #####
===============================================================================
[..]
(+) OPAMP Self calibration.
@endverbatim
* @{
*/
/* 2 OPAMPS available */
/* 2 OPAMPS can be calibrated in parallel */
/**
* @brief Run the self calibration of the 2 OPAMPs in parallel.
* @note Trimming values (PMOS & NMOS) are updated and user trimming is
* enabled is calibration is successful.
* @note Calibration is performed in the mode specified in OPAMP init
* structure (mode normal or low-power). To perform calibration for
* both modes, repeat this function twice after OPAMP init structure
* accordingly updated.
* @note Calibration runs about 10 ms (5 dichotomy steps, repeated for P
* and N transistors: 10 steps with 1 ms for each step).
* @param hopamp1 handle
* @param hopamp2 handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t trimmingvaluen1;
uint32_t trimmingvaluep1;
uint32_t trimmingvaluen2;
uint32_t trimmingvaluep2;
/* Selection of register of trimming depending on power mode: OTR or LPOTR */
__IO uint32_t *tmp_opamp1_reg_trimming;
__IO uint32_t *tmp_opamp2_reg_trimming;
uint32_t delta;
uint32_t opampmode1;
uint32_t opampmode2;
if ((hopamp1 == NULL) || (hopamp2 == NULL))
{
status = HAL_ERROR;
}
/* Check if OPAMP in calibration mode and calibration not yet enable */
else if (hopamp1->State != HAL_OPAMP_STATE_READY)
{
status = HAL_ERROR;
}
else if (hopamp2->State != HAL_OPAMP_STATE_READY)
{
status = HAL_ERROR;
}
else
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
/* Save OPAMP mode as in */
/* the calibration is not working in PGA mode */
opampmode1 = READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE);
opampmode2 = READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE);
/* Use of standalone mode */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, OPAMP_STANDALONE_MODE);
/* user trimming values are used for offset calibration */
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
/* Select trimming settings depending on power mode */
if ((hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
(hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
{
tmp_opamp1_reg_trimming = &OPAMP1->OTR;
}
else
{
tmp_opamp1_reg_trimming = &OPAMP1->LPOTR;
}
if ((hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED) || \
(hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED))
{
tmp_opamp2_reg_trimming = &OPAMP2->OTR;
}
else
{
tmp_opamp2_reg_trimming = &OPAMP2->LPOTR;
}
/* Enable calibration */
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON);
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON);
/* 1st calibration - N */
CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL);
CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL);
/* Enable the selected opamp */
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAEN);
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAEN);
/* Init trimming counter */
/* Medium value */
trimmingvaluen1 = 16U;
trimmingvaluen2 = 16U;
delta = 8U;
while (delta != 0U)
{
/* Set candidate trimming */
/* OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED or OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED*/
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
/* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
{
/* OPAMP_CSR_CALOUT is HIGH try lower trimming */
trimmingvaluen1 -= delta;
}
else
{
/* OPAMP_CSR_CALOUT is LOW try higher trimming */
trimmingvaluen1 += delta;
}
if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
{
/* OPAMP_CSR_CALOUT is HIGH try lower trimming */
trimmingvaluen2 -= delta;
}
else
{
/* OPAMP_CSR_CALOUT is LOW try higher trimming */
trimmingvaluen2 += delta;
}
/* Divide range by 2 to continue dichotomy sweep */
delta >>= 1U;
}
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the OUTCAL bit to change from 0 to 1 */
/* Set candidate trimming */
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
/* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if ((READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U)
{
/* Trimming value is actually one value more */
trimmingvaluen1++;
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen1);
}
if ((READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT)) == 0U)
{
/* Trimming value is actually one value more */
trimmingvaluen2++;
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen2);
}
/* 2nd calibration - P */
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL);
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL);
/* Init trimming counter */
/* Medium value */
trimmingvaluep1 = 16U;
trimmingvaluep2 = 16U;
delta = 8U;
while (delta != 0U)
{
/* Set candidate trimming */
/* OPAMP_POWERMODE_NORMALPOWER_HIGHSPEED or OPAMP_POWERMODE_NORMALPOWER_NORMALSPEED*/
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1 << OPAMP_INPUT_NONINVERTING));
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2 << OPAMP_INPUT_NONINVERTING));
/* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
{
/* OPAMP_CSR_CALOUT is HIGH try higher trimming */
trimmingvaluep1 -= delta;
}
else
{
/* OPAMP_CSR_CALOUT is HIGH try lower trimming */
trimmingvaluep1 += delta;
}
if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
{
/* OPAMP_CSR_CALOUT is HIGH try higher trimming */
trimmingvaluep2 -= delta;
}
else
{
/* OPAMP_CSR_CALOUT is LOW try lower trimming */
trimmingvaluep2 += delta;
}
/* Divide range by 2 to continue dichotomy sweep */
delta >>= 1U;
}
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
/* Set candidate trimming */
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1 << OPAMP_INPUT_NONINVERTING));
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2 << OPAMP_INPUT_NONINVERTING));
/* OFFTRIMmax delay 1 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
if (READ_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
{
/* Trimming value is actually one value more */
trimmingvaluep1++;
MODIFY_REG(*tmp_opamp1_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep1 << OPAMP_INPUT_NONINVERTING));
}
if (READ_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
{
/* Trimming value is actually one value more */
trimmingvaluep2++;
MODIFY_REG(*tmp_opamp2_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep2 << OPAMP_INPUT_NONINVERTING));
}
/* Disable the OPAMPs */
CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAEN);
CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAEN);
/* Disable calibration & set normal mode (operating mode) */
CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON);
CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON);
/* Self calibration is successful */
/* Store calibration (user trimming) results in init structure. */
/* Set user trimming mode */
hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
/* Affect calibration parameters depending on mode normal/low power */
if ((hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_NORMALSPEED) && \
(hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_HIGHSPEED))
{
/* Write calibration result N */
hopamp1->Init.TrimmingValueN = trimmingvaluen1;
/* Write calibration result P */
hopamp1->Init.TrimmingValueP = trimmingvaluep1;
}
else
{
/* Write calibration result N */
hopamp1->Init.TrimmingValueNLowPower = trimmingvaluen1;
/* Write calibration result P */
hopamp1->Init.TrimmingValuePLowPower = trimmingvaluep1;
}
if ((hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_NORMALSPEED) && \
(hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER_HIGHSPEED))
{
/* Write calibration result N */
hopamp2->Init.TrimmingValueN = trimmingvaluen2;
/* Write calibration result P */
hopamp2->Init.TrimmingValueP = trimmingvaluep2;
}
else
{
/* Write calibration result N */
hopamp2->Init.TrimmingValueNLowPower = trimmingvaluen2;
/* Write calibration result P */
hopamp2->Init.TrimmingValuePLowPower = trimmingvaluep2;
}
/* Update OPAMP state */
hopamp1->State = HAL_OPAMP_STATE_READY;
hopamp2->State = HAL_OPAMP_STATE_READY;
/* Restore OPAMP mode after calibration */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode1);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_OPAMODE, opampmode2);
}
return status;
}
/**
* @}
*/
/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
(+) OPAMP unlock.
@endverbatim
* @{
*/
/**
* @brief Unlock the selected OPAMP configuration.
* @note This function must be called only when OPAMP is in state "locked".
* @param hopamp: OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
if (hopamp == NULL)
{
status = HAL_ERROR;
}
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
else if (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
/* OPAMP state changed to locked */
hopamp->State = HAL_OPAMP_STATE_BUSY;
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_OPAMP_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_opamp_ex.c
|
C
|
apache-2.0
| 14,484
|
/**
******************************************************************************
* @file stm32u5xx_hal_ospi.c
* @author MCD Application Team
* @brief OSPI HAL module driver.
This file provides firmware functions to manage the following
functionalities of the OctoSPI interface (OSPI).
+ Initialization and de-initialization functions
+ Hyperbus configuration
+ Indirect functional mode management
+ Memory-mapped functional mode management
+ Auto-polling functional mode management
+ Interrupts and flags management
+ DMA channel configuration for indirect functional mode
+ Errors management and abort functionality
+ IO manager configuration
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
*** Initialization ***
======================
[..]
As prerequisite, fill in the HAL_OSPI_MspInit() :
(+) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE().
(+) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET().
(+) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
(+) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init().
(+) If interrupt or DMA mode is used, enable and configure OctoSPI global
interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
(+) If DMA mode is used, enable the clocks for the OctoSPI DMA channel
with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure
DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
[..]
Configure the fifo threshold, the dual-quad mode, the memory type, the
device size, the CS high time, the free running clock, the clock mode,
the wrap size, the clock prescaler, the sample shifting, the hold delay
and the CS boundary using the HAL_OSPI_Init() function.
[..]
When using Hyperbus, configure the RW recovery time, the access time,
the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
function.
*** Indirect functional mode ***
================================
[..]
In regular mode, configure the command sequence using the HAL_OSPI_Command()
or HAL_OSPI_Command_IT() functions :
(+) Instruction phase : the mode used and if present the size, the instruction
opcode and the DTR mode.
(+) Address phase : the mode used and if present the size, the address
value and the DTR mode.
(+) Alternate-bytes phase : the mode used and if present the size, the
alternate bytes values and the DTR mode.
(+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
(+) Data phase : the mode used and if present the number of bytes and the DTR mode.
(+) Data strobe (DQS) mode : the activation (or not) of this mode
(+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
(+) Flash identifier : in dual-quad mode, indicates which flash is concerned
(+) Operation type : always common configuration
[..]
In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd()
function :
(+) Address space : indicate if the access will be done in register or memory
(+) Address size
(+) Number of data
(+) Data strobe (DQS) mode : the activation (or not) of this mode
[..]
If no data is required for the command (only for regular mode, not for
Hyperbus mode), it is sent directly to the memory :
(+) In polling mode, the output of the function is done when the transfer is complete.
(+) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete.
[..]
For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or
HAL_OSPI_Transmit_IT() after the command configuration :
(+) In polling mode, the output of the function is done when the transfer is complete.
(+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
(+) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and
HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
[..]
For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or
HAL_OSPI_Receive_IT() after the command configuration :
(+) In polling mode, the output of the function is done when the transfer is complete.
(+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
(+) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and
HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
====================================
[..]
Configure the command sequence by the same way than the indirect mode
[..]
Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling()
or HAL_OSPI_AutoPolling_IT() functions :
(+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
the polling interval and the automatic stop activation.
[..]
After the configuration :
(+) In polling mode, the output of the function is done when the status match is reached. The
automatic stop is activated to avoid an infinite loop.
(+) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached.
*** Memory-mapped functional mode ***
=====================================
[..]
Configure the command sequence by the same way than the indirect mode except
for the operation type in regular mode :
(+) Operation type equals to read configuration : the command configuration
applies to read access in memory-mapped mode
(+) Operation type equals to write configuration : the command configuration
applies to write access in memory-mapped mode
(+) Both read and write configuration should be performed before activating
memory-mapped mode
[..]
Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped()
functions :
(+) The timeout activation and the timeout period.
[..]
After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on
the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires.
*** Errors management and abort functionality ***
=================================================
[..]
HAL_OSPI_GetError() function gives the error raised during the last operation.
[..]
HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and
flushes the fifo :
(+) In polling mode, the output of the function is done when the transfer
complete bit is set and the busy bit cleared.
(+) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when
the transfer complete bit is set.
*** Control functions ***
=========================
[..]
HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver.
[..]
HAL_OSPI_SetTimeout() function configures the timeout value used in the driver.
[..]
HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral.
[..]
HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
*** IO manager configuration functions ***
==========================================
[..]
HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance.
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use function HAL_OSPI_RegisterCallback() to register a user callback,
it allows to register following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) FifoThresholdCallback : callback when the fifo threshold is reached.
(+) CmdCpltCallback : callback when a command without data is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
(+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
(+) StatusMatchCallback : callback when a status match occurs.
(+) TimeOutCallback : callback when the timeout perioed expires.
(+) MspInitCallback : OSPI MspInit.
(+) MspDeInitCallback : OSPI MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. It allows to reset following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) FifoThresholdCallback : callback when the fifo threshold is reached.
(+) CmdCpltCallback : callback when a command without data is completed.
(+) RxCpltCallback : callback when a reception transfer is completed.
(+) TxCpltCallback : callback when a transmission transfer is completed.
(+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
(+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
(+) StatusMatchCallback : callback when a status match occurs.
(+) TimeOutCallback : callback when the timeout perioed expires.
(+) MspInitCallback : OSPI MspInit.
(+) MspDeInitCallback : OSPI MspDeInit.
[..]
This function) takes as parameters the HAL peripheral handle and the Callback ID.
[..]
By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the HAL_OSPI_Init()
and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
[..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_OSPI_RegisterCallback() before calling HAL_OSPI_DeInit()
or HAL_OSPI_Init() function.
[..]
When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup OSPI OSPI
* @brief OSPI HAL module driver
* @{
*/
#ifdef HAL_OSPI_MODULE_ENABLED
/**
@cond 0
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!< Indirect write mode */
#define OSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)OCTOSPI_CR_FMODE_0) /*!< Indirect read mode */
#define OSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)OCTOSPI_CR_FMODE_1) /*!< Automatic polling mode */
#define OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)OCTOSPI_CR_FMODE) /*!< Memory-mapped mode */
#define OSPI_CFG_STATE_MASK 0x00000004U
#define OSPI_BUSY_STATE_MASK 0x00000008U
#define OSPI_NB_INSTANCE 2U
#define OSPI_IOM_NB_PORTS 2U
#define OSPI_IOM_PORT_MASK 0x1U
/* Private macro -------------------------------------------------------------*/
#define IS_OSPI_FUNCTIONAL_MODE(MODE) (((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
((MODE) == OSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
((MODE) == OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void OSPI_DMACplt(DMA_HandleTypeDef *hdma);
static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma);
static void OSPI_DMAError(DMA_HandleTypeDef *hdma);
static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
/**
@endcond
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup OSPI_Exported_Functions OSPI Exported Functions
* @{
*/
/** @defgroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to :
(+) Initialize the OctoSPI.
(+) De-initialize the OctoSPI.
@endverbatim
* @{
*/
/**
* @brief Initialize the OSPI mode according to the specified parameters
* in the OSPI_InitTypeDef and initialize the associated handle.
* @param hospi : OSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart = HAL_GetTick();
/* Check the OSPI handle allocation */
if (hospi == NULL)
{
status = HAL_ERROR;
/* No error code can be set set as the handler is null */
}
else
{
/* Check the parameters of the initialization structure */
assert_param(IS_OSPI_FIFO_THRESHOLD(hospi->Init.FifoThreshold));
assert_param(IS_OSPI_DUALQUAD_MODE(hospi->Init.DualQuad));
assert_param(IS_OSPI_MEMORY_TYPE(hospi->Init.MemoryType));
assert_param(IS_OSPI_DEVICE_SIZE(hospi->Init.DeviceSize));
assert_param(IS_OSPI_CS_HIGH_TIME(hospi->Init.ChipSelectHighTime));
assert_param(IS_OSPI_FREE_RUN_CLK(hospi->Init.FreeRunningClock));
assert_param(IS_OSPI_CLOCK_MODE(hospi->Init.ClockMode));
assert_param(IS_OSPI_WRAP_SIZE(hospi->Init.WrapSize));
assert_param(IS_OSPI_CLK_PRESCALER(hospi->Init.ClockPrescaler));
assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting));
assert_param(IS_OSPI_DHQC(hospi->Init.DelayHoldQuarterCycle));
assert_param(IS_OSPI_CS_BOUNDARY(hospi->Init.ChipSelectBoundary));
assert_param(IS_OSPI_DLYBYP(hospi->Init.DelayBlockBypass));
assert_param(IS_OSPI_MAXTRAN(hospi->Init.MaxTran));
/* Initialize error code */
hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
/* Check if the state is the reset state */
if (hospi->State == HAL_OSPI_STATE_RESET)
{
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/* Reset Callback pointers in HAL_OSPI_STATE_RESET only */
hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
if (hospi->MspInitCallback == NULL)
{
hospi->MspInitCallback = HAL_OSPI_MspInit;
}
/* Init the low level hardware */
hospi->MspInitCallback(hospi);
#else
/* Initialization of the low level hardware */
HAL_OSPI_MspInit(hospi);
#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/* Configure the default timeout for the OSPI memory access */
(void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
/* Configure memory type, device size, chip select high time, delay block bypass,
free running clock, clock mode */
MODIFY_REG(hospi->Instance->DCR1,
(OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_DLYBYP |
OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
(hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) |
((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) |
hospi->Init.DelayBlockBypass | hospi->Init.ClockMode));
/* Configure wrap size */
MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize);
/* Configure chip select boundary and maximum transfer */
hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) |
(hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos));
/* Configure refresh */
hospi->Instance->DCR4 = hospi->Init.Refresh;
/* Configure FIFO threshold */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos));
/* Wait till busy flag is reset */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
if (status == HAL_OK)
{
/* Configure clock prescaler */
MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER,
((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
/* Configure Dual Quad mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DMM, hospi->Init.DualQuad);
/* Configure sample shifting and delay hold quarter cycle */
MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC),
(hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
/* Enable OctoSPI */
__HAL_OSPI_ENABLE(hospi);
/* Enable free running clock if needed : must be done after OSPI enable */
if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE)
{
SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
}
/* Initialize the OSPI state */
if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
{
hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT;
}
else
{
hospi->State = HAL_OSPI_STATE_READY;
}
}
}
}
/* Return function status */
return status;
}
/**
* @brief Initialize the OSPI MSP.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_OSPI_MspInit can be implemented in the user file
*/
}
/**
* @brief De-Initialize the OSPI peripheral.
* @param hospi : OSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the OSPI handle allocation */
if (hospi == NULL)
{
status = HAL_ERROR;
/* No error code can be set set as the handler is null */
}
else
{
/* Disable OctoSPI */
__HAL_OSPI_DISABLE(hospi);
/* Disable free running clock if needed : must be done after OSPI disable */
CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
if (hospi->MspDeInitCallback == NULL)
{
hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
}
/* DeInit the low level hardware */
hospi->MspDeInitCallback(hospi);
#else
/* De-initialize the low-level hardware */
HAL_OSPI_MspDeInit(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/* Reset the driver state */
hospi->State = HAL_OSPI_STATE_RESET;
}
return status;
}
/**
* @brief DeInitialize the OSPI MSP.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_OSPI_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup OSPI_Exported_Functions_Group2 Input and Output operation functions
* @brief OSPI Transmit/Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to :
(+) Handle the interrupts.
(+) Handle the command sequence (regular and Hyperbus).
(+) Handle the Hyperbus configuration.
(+) Transmit data in blocking, interrupt or DMA mode.
(+) Receive data in blocking, interrupt or DMA mode.
(+) Manage the auto-polling functional mode.
(+) Manage the memory-mapped functional mode.
@endverbatim
* @{
*/
/**
* @brief Handle OSPI interrupt request.
* @param hospi : OSPI handle
* @retval None
*/
void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi)
{
__IO uint32_t *data_reg = &hospi->Instance->DR;
uint32_t flag = hospi->Instance->SR;
uint32_t itsource = hospi->Instance->CR;
uint32_t currentstate = hospi->State;
/* OctoSPI fifo threshold interrupt occurred -------------------------------*/
if (((flag & HAL_OSPI_FLAG_FT) != 0U) && ((itsource & HAL_OSPI_IT_FT) != 0U))
{
if (currentstate == HAL_OSPI_STATE_BUSY_TX)
{
/* Write a data in the fifo */
*((__IO uint8_t *)data_reg) = *hospi->pBuffPtr;
hospi->pBuffPtr++;
hospi->XferCount--;
}
else if (currentstate == HAL_OSPI_STATE_BUSY_RX)
{
/* Read a data from the fifo */
*hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
hospi->pBuffPtr++;
hospi->XferCount--;
}
else
{
/* Nothing to do */
}
if (hospi->XferCount == 0U)
{
/* All data have been received or transmitted for the transfer */
/* Disable fifo threshold interrupt */
__HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_FT);
}
/* Fifo threshold callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->FifoThresholdCallback(hospi);
#else
HAL_OSPI_FifoThresholdCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
/* OctoSPI transfer complete interrupt occurred ----------------------------*/
else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U))
{
if (currentstate == HAL_OSPI_STATE_BUSY_RX)
{
if ((hospi->XferCount > 0U) && ((flag & OCTOSPI_SR_FLEVEL) != 0U))
{
/* Read the last data received in the fifo */
*hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
hospi->pBuffPtr++;
hospi->XferCount--;
}
else if (hospi->XferCount == 0U)
{
/* Clear flag */
hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
/* Disable the interrupts */
__HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
/* RX complete callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->RxCpltCallback(hospi);
#else
HAL_OSPI_RxCpltCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else
{
/* Nothing to do */
}
}
else
{
/* Clear flag */
hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
/* Disable the interrupts */
__HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
if (currentstate == HAL_OSPI_STATE_BUSY_TX)
{
/* TX complete callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->TxCpltCallback(hospi);
#else
HAL_OSPI_TxCpltCallback(hospi);
#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else if (currentstate == HAL_OSPI_STATE_BUSY_CMD)
{
/* Command complete callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->CmdCpltCallback(hospi);
#else
HAL_OSPI_CmdCpltCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else if (currentstate == HAL_OSPI_STATE_ABORT)
{
if (hospi->ErrorCode == HAL_OSPI_ERROR_NONE)
{
/* Abort called by the user */
/* Abort complete callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
else
{
/* Abort due to an error (eg : DMA error) */
/* Error callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
else
{
/* Nothing to do */
}
}
}
/* OctoSPI status match interrupt occurred ---------------------------------*/
else if (((flag & HAL_OSPI_FLAG_SM) != 0U) && ((itsource & HAL_OSPI_IT_SM) != 0U))
{
/* Clear flag */
hospi->Instance->FCR = HAL_OSPI_FLAG_SM;
/* Check if automatic poll mode stop is activated */
if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0U)
{
/* Disable the interrupts */
__HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE);
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
}
/* Status match callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->StatusMatchCallback(hospi);
#else
HAL_OSPI_StatusMatchCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
/* OctoSPI transfer error interrupt occurred -------------------------------*/
else if (((flag & HAL_OSPI_FLAG_TE) != 0U) && ((itsource & HAL_OSPI_IT_TE) != 0U))
{
/* Clear flag */
hospi->Instance->FCR = HAL_OSPI_FLAG_TE;
/* Disable all interrupts */
__HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE));
/* Set error code */
hospi->ErrorCode = HAL_OSPI_ERROR_TRANSFER;
/* Check if the DMA is enabled */
if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer on the OctoSPI side */
CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
/* Disable the DMA transfer on the DMA side */
hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt;
if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK)
{
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
/* Error callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
else
{
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
/* Error callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
/* OctoSPI timeout interrupt occurred --------------------------------------*/
else if (((flag & HAL_OSPI_FLAG_TO) != 0U) && ((itsource & HAL_OSPI_IT_TO) != 0U))
{
/* Clear flag */
hospi->Instance->FCR = HAL_OSPI_FLAG_TO;
/* Timeout callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->TimeOutCallback(hospi);
#else
HAL_OSPI_TimeOutCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else
{
/* Nothing to do */
}
}
/**
* @brief Set the command configuration.
* @param hospi : OSPI handle
* @param cmd : structure that contains the command configuration information
* @param Timeout : Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout)
{
HAL_StatusTypeDef status;
uint32_t state;
uint32_t tickstart = HAL_GetTick();
/* Check the parameters of the command structure */
assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType));
if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
{
assert_param(IS_OSPI_FLASH_ID(cmd->FlashId));
}
assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
{
assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize));
assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
}
assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
{
assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
}
assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
{
assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize));
assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
}
assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
if (cmd->DataMode != HAL_OSPI_DATA_NONE)
{
if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
{
assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
}
assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles));
}
assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
/* Check the state of the driver */
state = hospi->State;
if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) ||
((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
|| (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) ||
(cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))))
{
/* Wait till busy flag is reset */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
if (status == HAL_OK)
{
/* Initialize error code */
hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
/* Configure the registers */
status = OSPI_ConfigCmd(hospi, cmd);
if (status == HAL_OK)
{
if (cmd->DataMode == HAL_OSPI_DATA_NONE)
{
/* When there is no data phase, the transfer start as soon as the configuration is done
so wait until TC flag is set to go back in idle state */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
}
else
{
/* Update the state */
if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
{
hospi->State = HAL_OSPI_STATE_CMD_CFG;
}
else if (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG)
{
if (hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG)
{
hospi->State = HAL_OSPI_STATE_CMD_CFG;
}
else
{
hospi->State = HAL_OSPI_STATE_READ_CMD_CFG;
}
}
else if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
{
if (hospi->State == HAL_OSPI_STATE_READ_CMD_CFG)
{
hospi->State = HAL_OSPI_STATE_CMD_CFG;
}
else
{
hospi->State = HAL_OSPI_STATE_WRITE_CMD_CFG;
}
}
else
{
/* Wrap configuration, no state change */
}
}
}
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
/* Return function status */
return status;
}
/**
* @brief Set the command configuration in interrupt mode.
* @param hospi : OSPI handle
* @param cmd : structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
{
HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
/* Check the parameters of the command structure */
assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType));
if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
{
assert_param(IS_OSPI_FLASH_ID(cmd->FlashId));
}
assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
{
assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize));
assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
}
assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
{
assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
}
assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
{
assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize));
assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
}
assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
if (cmd->DataMode != HAL_OSPI_DATA_NONE)
{
assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles));
}
assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
/* Check the state of the driver */
if ((hospi->State == HAL_OSPI_STATE_READY) && (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) &&
(cmd->DataMode == HAL_OSPI_DATA_NONE) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS))
{
/* Wait till busy flag is reset */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
if (status == HAL_OK)
{
/* Initialize error code */
hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
/* Clear flags related to interrupt */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
/* Configure the registers */
status = OSPI_ConfigCmd(hospi, cmd);
if (status == HAL_OK)
{
/* Update the state */
hospi->State = HAL_OSPI_STATE_BUSY_CMD;
/* Enable the transfer complete and transfer error interrupts */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_TE);
}
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
/* Return function status */
return status;
}
/**
* @brief Configure the Hyperbus parameters.
* @param hospi : OSPI handle
* @param cfg : Structure containing the Hyperbus configuration
* @param Timeout : Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout)
{
HAL_StatusTypeDef status;
uint32_t state;
uint32_t tickstart = HAL_GetTick();
/* Check the parameters of the hyperbus configuration structure */
assert_param(IS_OSPI_RW_RECOVERY_TIME(cfg->RWRecoveryTime));
assert_param(IS_OSPI_ACCESS_TIME(cfg->AccessTime));
assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency));
assert_param(IS_OSPI_LATENCY_MODE(cfg->LatencyMode));
/* Check the state of the driver */
state = hospi->State;
if ((state == HAL_OSPI_STATE_HYPERBUS_INIT) || (state == HAL_OSPI_STATE_READY))
{
/* Wait till busy flag is reset */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
if (status == HAL_OK)
{
/* Configure Hyperbus configuration Latency register */
WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) |
(cfg->AccessTime << OCTOSPI_HLCR_TACC_Pos) |
cfg->WriteZeroLatency | cfg->LatencyMode));
/* Update the state */
hospi->State = HAL_OSPI_STATE_READY;
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
/* Return function status */
return status;
}
/**
* @brief Set the Hyperbus command configuration.
* @param hospi : OSPI handle
* @param cmd : Structure containing the Hyperbus command
* @param Timeout : Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout)
{
HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
/* Check the parameters of the hyperbus command structure */
assert_param(IS_OSPI_ADDRESS_SPACE(cmd->AddressSpace));
assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
/* Check the state of the driver */
if ((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS))
{
/* Wait till busy flag is reset */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
if (status == HAL_OK)
{
/* Re-initialize the value of the functional mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U);
/* Configure the address space in the DCR1 register */
MODIFY_REG(hospi->Instance->DCR1, OCTOSPI_DCR1_MTYP_0, cmd->AddressSpace);
/* Configure the CCR and WCCR registers with the address size and the following configuration :
- DQS signal enabled (used as RWDS)
- DTR mode enabled on address and data
- address and data on 8 lines */
WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 |
cmd->AddressSize | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADMODE_2));
WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 |
cmd->AddressSize | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2));
/* Configure the DLR register with the number of data */
WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1U));
/* Configure the AR register with the address value */
WRITE_REG(hospi->Instance->AR, cmd->Address);
/* Update the state */
hospi->State = HAL_OSPI_STATE_CMD_CFG;
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
/* Return function status */
return status;
}
/**
* @brief Transmit an amount of data in blocking mode.
* @param hospi : OSPI handle
* @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
{
HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
__IO uint32_t *data_reg = &hospi->Instance->DR;
/* Check the data pointer allocation */
if (pData == NULL)
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
}
else
{
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
{
/* Configure counters and size */
hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
hospi->XferSize = hospi->XferCount;
hospi->pBuffPtr = pData;
/* Configure CR register with functional mode as indirect write */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
do
{
/* Wait till fifo threshold flag is set to send data */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_FT, SET, tickstart, Timeout);
if (status != HAL_OK)
{
break;
}
*((__IO uint8_t *)data_reg) = *hospi->pBuffPtr;
hospi->pBuffPtr++;
hospi->XferCount--;
} while (hospi->XferCount > 0U);
if (status == HAL_OK)
{
/* Wait till transfer complete flag is set to go back in idle state */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
if (status == HAL_OK)
{
/* Clear transfer complete flag */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
}
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
}
/* Return function status */
return status;
}
/**
* @brief Receive an amount of data in blocking mode.
* @param hospi : OSPI handle
* @param pData : pointer to data buffer
* @param Timeout : Timeout duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout)
{
HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
__IO uint32_t *data_reg = &hospi->Instance->DR;
uint32_t addr_reg = hospi->Instance->AR;
uint32_t ir_reg = hospi->Instance->IR;
/* Check the data pointer allocation */
if (pData == NULL)
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
}
else
{
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
{
/* Configure counters and size */
hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
hospi->XferSize = hospi->XferCount;
hospi->pBuffPtr = pData;
/* Configure CR register with functional mode as indirect read */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Trig the transfer by re-writing address or instruction register */
if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
WRITE_REG(hospi->Instance->IR, ir_reg);
}
}
do
{
/* Wait till fifo threshold or transfer complete flags are set to read received data */
status = OSPI_WaitFlagStateUntilTimeout(hospi, (HAL_OSPI_FLAG_FT | HAL_OSPI_FLAG_TC), SET, tickstart, Timeout);
if (status != HAL_OK)
{
break;
}
*hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
hospi->pBuffPtr++;
hospi->XferCount--;
} while (hospi->XferCount > 0U);
if (status == HAL_OK)
{
/* Wait till transfer complete flag is set to go back in idle state */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout);
if (status == HAL_OK)
{
/* Clear transfer complete flag */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
}
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
}
/* Return function status */
return status;
}
/**
* @brief Send an amount of data in non-blocking mode with interrupt.
* @param hospi : OSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the data pointer allocation */
if (pData == NULL)
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
}
else
{
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
{
/* Configure counters and size */
hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
hospi->XferSize = hospi->XferCount;
hospi->pBuffPtr = pData;
/* Configure CR register with functional mode as indirect write */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
/* Clear flags related to interrupt */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
/* Update the state */
hospi->State = HAL_OSPI_STATE_BUSY_TX;
/* Enable the transfer complete, fifo threshold and transfer error interrupts */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
}
/* Return function status */
return status;
}
/**
* @brief Receive an amount of data in non-blocking mode with interrupt.
* @param hospi : OSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t addr_reg = hospi->Instance->AR;
uint32_t ir_reg = hospi->Instance->IR;
/* Check the data pointer allocation */
if (pData == NULL)
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
}
else
{
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
{
/* Configure counters and size */
hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U;
hospi->XferSize = hospi->XferCount;
hospi->pBuffPtr = pData;
/* Configure CR register with functional mode as indirect read */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Clear flags related to interrupt */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
/* Update the state */
hospi->State = HAL_OSPI_STATE_BUSY_RX;
/* Enable the transfer complete, fifo threshold and transfer error interrupts */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
/* Trig the transfer by re-writing address or instruction register */
if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
WRITE_REG(hospi->Instance->IR, ir_reg);
}
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
}
/* Return function status */
return status;
}
/**
* @brief Send an amount of data in non-blocking mode with DMA.
* @param hospi : OSPI handle
* @param pData : pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
* @note If DMA peripheral access is configured as word, the number
* of data and the fifo threshold should be aligned on word
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t data_size = hospi->Instance->DLR + 1U;
DMA_QListTypeDef *p_queue = {NULL};
uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE;
/* Check the data pointer allocation */
if (pData == NULL)
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
}
else
{
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
{
if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
p_queue = hospi->hdma->LinkedListQueue;
if ((p_queue != NULL) && (p_queue->Head != NULL))
{
data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
}
else
{
/* Set Error Code */
hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
/* Return function status */
status = HAL_ERROR;
}
}
else
{
data_width = hospi->hdma->Init.DestDataWidth;
}
/* Configure counters and size */
if (data_width == DMA_DEST_DATAWIDTH_BYTE)
{
hospi->XferCount = data_size;
}
else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
{
if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U))
{
/* The number of data or the fifo threshold is not aligned on halfword
=> no transfer possible with DMA peripheral access configured as halfword */
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
}
else
{
hospi->XferCount = data_size;
}
}
else if (data_width == DMA_DEST_DATAWIDTH_WORD)
{
if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U))
{
/* The number of data or the fifo threshold is not aligned on word
=> no transfer possible with DMA peripheral access configured as word */
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
}
else
{
hospi->XferCount = data_size;
}
}
else
{
/* Nothing to do */
}
if (status == HAL_OK)
{
hospi->XferSize = hospi->XferCount;
hospi->pBuffPtr = pData;
/* Configure CR register with functional mode as indirect write */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
/* Clear flags related to interrupt */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
/* Update the state */
hospi->State = HAL_OSPI_STATE_BUSY_TX;
/* Set the DMA transfer complete callback */
hospi->hdma->XferCpltCallback = OSPI_DMACplt;
/* Set the DMA Half transfer complete callback */
hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt;
/* Set the DMA error callback */
hospi->hdma->XferErrorCallback = OSPI_DMAError;
/* Clear the DMA abort callback */
hospi->hdma->XferAbortCallback = NULL;
/* Enable the transmit DMA Channel */
if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hospi->hdma->LinkedListQueue != NULL)
{
/* Enable the DMA channel */
MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \
(DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_INCREMENTED | DMA_DINC_FIXED));
MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \
DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH);
/* Set DMA data size*/
p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hospi->XferSize;
/* Set DMA source address */
p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hospi->Instance->DR;
status = HAL_DMAEx_List_Start_IT(hospi->hdma);
}
else
{
/* Set Error Code */
hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
/* Change OSPI state */
hospi->State = HAL_OSPI_STATE_READY;
/* Return function status */
status = HAL_ERROR;
}
}
else
{
/* Configure the direction of the DMA */
MODIFY_REG(hospi->hdma->Instance->CTR1, (DMA_CTR1_SINC | DMA_CTR1_DINC), \
(DMA_SINC_INCREMENTED | DMA_DINC_FIXED));
MODIFY_REG(hospi->hdma->Instance->CTR2, DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH);
status = HAL_DMA_Start_IT(hospi->hdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize);
}
if (status == HAL_OK)
{
/* Enable the transfer error interrupt */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
/* Enable the DMA transfer by setting the DMAEN bit */
SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
hospi->State = HAL_OSPI_STATE_READY;
}
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
}
/* Return function status */
return status;
}
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
* @param hospi : OSPI handle
* @param pData : pointer to data buffer.
* @note This function is used only in Indirect Read Mode
* @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
* @note If DMA peripheral access is configured as word, the number
* of data and the fifo threshold should be aligned on word
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t data_size = hospi->Instance->DLR + 1U;
uint32_t addr_reg = hospi->Instance->AR;
uint32_t ir_reg = hospi->Instance->IR;
DMA_QListTypeDef *p_queue = {NULL};
uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE;
/* Check the data pointer allocation */
if (pData == NULL)
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
}
else
{
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
{
if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
p_queue = hospi->hdma->LinkedListQueue;
if ((p_queue != NULL) && (p_queue->Head != NULL))
{
data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2;
}
else
{
/* Set Error Code */
hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
/* Return function status */
status = HAL_ERROR;
}
}
else
{
data_width = hospi->hdma->Init.DestDataWidth;
}
/* Configure counters and size */
if (data_width == DMA_DEST_DATAWIDTH_BYTE)
{
hospi->XferCount = data_size;
}
else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD)
{
if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U))
{
/* The number of data or the fifo threshold is not aligned on halfword
=> no transfer possible with DMA peripheral access configured as halfword */
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
}
else
{
hospi->XferCount = data_size;
}
}
else if (data_width == DMA_DEST_DATAWIDTH_WORD)
{
if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U))
{
/* The number of data or the fifo threshold is not aligned on word
=> no transfer possible with DMA peripheral access configured as word */
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
status = HAL_ERROR;
}
else
{
hospi->XferCount = data_size;
}
}
else
{
/* Nothing to do */
}
if (status == HAL_OK)
{
hospi->XferSize = hospi->XferCount;
hospi->pBuffPtr = pData;
/* Configure CR register with functional mode as indirect read */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ);
/* Clear flags related to interrupt */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC);
/* Update the state */
hospi->State = HAL_OSPI_STATE_BUSY_RX;
/* Set the DMA transfer complete callback */
hospi->hdma->XferCpltCallback = OSPI_DMACplt;
/* Set the DMA Half transfer complete callback */
hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt;
/* Set the DMA error callback */
hospi->hdma->XferErrorCallback = OSPI_DMAError;
/* Clear the DMA abort callback */
hospi->hdma->XferAbortCallback = NULL;
/* Enable the transmit DMA Channel */
if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hospi->hdma->LinkedListQueue != NULL)
{
/* Enable the DMA channel */
MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \
(DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_FIXED | DMA_DINC_INCREMENTED));
MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \
DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY);
/* Set DMA data size */
p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hospi->XferSize;
/* Set DMA source address */
p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hospi->Instance->DR;
/* Set DMA destination address */
p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
status = HAL_DMAEx_List_Start_IT(hospi->hdma);
}
else
{
/* Set Error Code */
hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
/* Change OSPI state */
hospi->State = HAL_OSPI_STATE_READY;
/* Return function status */
status = HAL_ERROR;
}
}
else
{
/* Configure the direction of the DMA */
MODIFY_REG(hospi->hdma->Instance->CTR1, (DMA_CTR1_SINC | DMA_CTR1_DINC), \
(DMA_SINC_FIXED | DMA_DINC_INCREMENTED));
MODIFY_REG(hospi->hdma->Instance->CTR2, DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY);
status = HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize);
}
if (status == HAL_OK)
{
/* Enable the transfer error interrupt */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
/* Trig the transfer by re-writing address or instruction register */
if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
WRITE_REG(hospi->Instance->IR, ir_reg);
}
}
/* Enable the DMA transfer by setting the DMAEN bit */
SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
hospi->State = HAL_OSPI_STATE_READY;
}
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
}
/* Return function status */
return status;
}
/**
* @brief Configure the OSPI Automatic Polling Mode in blocking mode.
* @param hospi : OSPI handle
* @param cfg : structure that contains the polling configuration information.
* @param Timeout : Timeout duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
{
HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
uint32_t addr_reg = hospi->Instance->AR;
uint32_t ir_reg = hospi->Instance->IR;
#ifdef USE_FULL_ASSERT
uint32_t dlr_reg = hospi->Instance->DLR;
#endif /* USE_FULL_ASSERT */
/* Check the parameters of the autopolling configuration structure */
assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode));
assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
assert_param(IS_OSPI_INTERVAL(cfg->Interval));
assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
/* Check the state */
if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE))
{
/* Wait till busy flag is reset */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout);
if (status == HAL_OK)
{
/* Configure registers */
WRITE_REG(hospi->Instance->PSMAR, cfg->Match);
WRITE_REG(hospi->Instance->PSMKR, cfg->Mask);
WRITE_REG(hospi->Instance->PIR, cfg->Interval);
MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
(cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
/* Trig the transfer by re-writing address or instruction register */
if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
WRITE_REG(hospi->Instance->IR, ir_reg);
}
}
/* Wait till status match flag is set to go back in idle state */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_SM, SET, tickstart, Timeout);
if (status == HAL_OK)
{
/* Clear status match flag */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_SM);
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
}
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
/* Return function status */
return status;
}
/**
* @brief Configure the OSPI Automatic Polling Mode in non-blocking mode.
* @param hospi : OSPI handle
* @param cfg : structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg)
{
HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
uint32_t addr_reg = hospi->Instance->AR;
uint32_t ir_reg = hospi->Instance->IR;
#ifdef USE_FULL_ASSERT
uint32_t dlr_reg = hospi->Instance->DLR;
#endif /* USE_FULL_ASSERT */
/* Check the parameters of the autopolling configuration structure */
assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode));
assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
assert_param(IS_OSPI_INTERVAL(cfg->Interval));
assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
{
/* Wait till busy flag is reset */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
if (status == HAL_OK)
{
/* Configure registers */
WRITE_REG(hospi->Instance->PSMAR, cfg->Match);
WRITE_REG(hospi->Instance->PSMKR, cfg->Mask);
WRITE_REG(hospi->Instance->PIR, cfg->Interval);
MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
(cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
/* Clear flags related to interrupt */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_SM);
/* Update state */
hospi->State = HAL_OSPI_STATE_BUSY_AUTO_POLLING;
/* Enable the status match and transfer error interrupts */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE);
/* Trig the transfer by re-writing address or instruction register */
if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
WRITE_REG(hospi->Instance->IR, ir_reg);
}
}
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
/* Return function status */
return status;
}
/**
* @brief Configure the Memory Mapped mode.
* @param hospi : OSPI handle
* @param cfg : structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg)
{
HAL_StatusTypeDef status;
uint32_t tickstart = HAL_GetTick();
/* Check the parameters of the memory-mapped configuration structure */
assert_param(IS_OSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
{
/* Wait till busy flag is reset */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
if (status == HAL_OK)
{
/* Update state */
hospi->State = HAL_OSPI_STATE_BUSY_MEM_MAPPED;
if (cfg->TimeOutActivation == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)
{
assert_param(IS_OSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
/* Configure register */
WRITE_REG(hospi->Instance->LPTR, cfg->TimeOutPeriod);
/* Clear flags related to interrupt */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TO);
/* Enable the timeout interrupt */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TO);
}
/* Configure CR register with functional mode as memory-mapped */
MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE),
(cfg->TimeOutActivation | OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED));
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
/* Return function status */
return status;
}
/**
* @brief Transfer Error callback.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_OSPI_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief Abort completed callback.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_OSPI_AbortCpltCallback could be implemented in the user file
*/
}
/**
* @brief FIFO Threshold callback.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_OSPI_FIFOThresholdCallback could be implemented in the user file
*/
}
/**
* @brief Command completed callback.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_OSPI_CmdCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callback.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_OSPI_RxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Tx Transfer completed callback.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_OSPI_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Half Transfer completed callback.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_OSPI_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Tx Half Transfer completed callback.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_OSPI_TxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Status Match callback.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_OSPI_StatusMatchCallback could be implemented in the user file
*/
}
/**
* @brief Timeout callback.
* @param hospi : OSPI handle
* @retval None
*/
__weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_OSPI_TimeOutCallback could be implemented in the user file
*/
}
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User OSPI Callback
* To be used instead of the weak (surcharged) predefined callback
* @param hospi : OSPI handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID
* @arg @ref HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID
* @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID
* @arg @ref HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID
* @arg @ref HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID
* @arg @ref HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID
* @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID
* @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID
* @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID
* @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID
* @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID
* @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID
* @param pCallback : pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
pOSPI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hospi->State == HAL_OSPI_STATE_READY)
{
switch (CallbackID)
{
case HAL_OSPI_ERROR_CB_ID :
hospi->ErrorCallback = pCallback;
break;
case HAL_OSPI_ABORT_CB_ID :
hospi->AbortCpltCallback = pCallback;
break;
case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
hospi->FifoThresholdCallback = pCallback;
break;
case HAL_OSPI_CMD_CPLT_CB_ID :
hospi->CmdCpltCallback = pCallback;
break;
case HAL_OSPI_RX_CPLT_CB_ID :
hospi->RxCpltCallback = pCallback;
break;
case HAL_OSPI_TX_CPLT_CB_ID :
hospi->TxCpltCallback = pCallback;
break;
case HAL_OSPI_RX_HALF_CPLT_CB_ID :
hospi->RxHalfCpltCallback = pCallback;
break;
case HAL_OSPI_TX_HALF_CPLT_CB_ID :
hospi->TxHalfCpltCallback = pCallback;
break;
case HAL_OSPI_STATUS_MATCH_CB_ID :
hospi->StatusMatchCallback = pCallback;
break;
case HAL_OSPI_TIMEOUT_CB_ID :
hospi->TimeOutCallback = pCallback;
break;
case HAL_OSPI_MSP_INIT_CB_ID :
hospi->MspInitCallback = pCallback;
break;
case HAL_OSPI_MSP_DEINIT_CB_ID :
hospi->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hospi->State == HAL_OSPI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_OSPI_MSP_INIT_CB_ID :
hospi->MspInitCallback = pCallback;
break;
case HAL_OSPI_MSP_DEINIT_CB_ID :
hospi->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a User OSPI Callback
* OSPI Callback is redirected to the weak (surcharged) predefined callback
* @param hospi : OSPI handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID
* @arg @ref HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID
* @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID
* @arg @ref HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID
* @arg @ref HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID
* @arg @ref HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID
* @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID
* @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID
* @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID
* @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID
* @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID
* @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (hospi->State == HAL_OSPI_STATE_READY)
{
switch (CallbackID)
{
case HAL_OSPI_ERROR_CB_ID :
hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
break;
case HAL_OSPI_ABORT_CB_ID :
hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
break;
case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
break;
case HAL_OSPI_CMD_CPLT_CB_ID :
hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
break;
case HAL_OSPI_RX_CPLT_CB_ID :
hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
break;
case HAL_OSPI_TX_CPLT_CB_ID :
hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
break;
case HAL_OSPI_RX_HALF_CPLT_CB_ID :
hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
break;
case HAL_OSPI_TX_HALF_CPLT_CB_ID :
hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
break;
case HAL_OSPI_STATUS_MATCH_CB_ID :
hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
break;
case HAL_OSPI_TIMEOUT_CB_ID :
hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
break;
case HAL_OSPI_MSP_INIT_CB_ID :
hospi->MspInitCallback = HAL_OSPI_MspInit;
break;
case HAL_OSPI_MSP_DEINIT_CB_ID :
hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
break;
default :
/* Update the error code */
hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else if (hospi->State == HAL_OSPI_STATE_RESET)
{
switch (CallbackID)
{
case HAL_OSPI_MSP_INIT_CB_ID :
hospi->MspInitCallback = HAL_OSPI_MspInit;
break;
case HAL_OSPI_MSP_DEINIT_CB_ID :
hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
break;
default :
/* Update the error code */
hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
return status;
}
#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
/**
* @}
*/
/** @defgroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions
* @brief OSPI control and State functions
*
@verbatim
===============================================================================
##### Peripheral Control and State functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to :
(+) Check in run-time the state of the driver.
(+) Check the error code set during last operation.
(+) Abort any operation.
(+) Manage the Fifo threshold.
(+) Configure the timeout duration used in the driver.
@endverbatim
* @{
*/
/**
* @brief Abort the current transmission.
* @param hospi : OSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t state;
uint32_t tickstart = HAL_GetTick();
/* Check if the state is in one of the busy or configured states */
state = hospi->State;
if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U))
{
/* Check if the DMA is enabled */
if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer on the OctoSPI side */
CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
/* Disable the DMA transfer on the DMA side */
status = HAL_DMA_Abort(hospi->hdma);
if (status != HAL_OK)
{
hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
}
}
if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
{
/* Perform an abort of the OctoSPI */
SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
/* Wait until the transfer complete flag is set to go back in idle state */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout);
if (status == HAL_OK)
{
/* Clear transfer complete flag */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
/* Wait until the busy flag is reset to go back in idle state */
status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout);
if (status == HAL_OK)
{
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
}
}
}
else
{
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
/* Return function status */
return status;
}
/**
* @brief Abort the current transmission (non-blocking function)
* @param hospi : OSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t state;
/* Check if the state is in one of the busy or configured states */
state = hospi->State;
if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U))
{
/* Disable all interrupts */
__HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE));
/* Update state */
hospi->State = HAL_OSPI_STATE_ABORT;
/* Check if the DMA is enabled */
if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U)
{
/* Disable the DMA transfer on the OctoSPI side */
CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
/* Disable the DMA transfer on the DMA side */
hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt;
if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK)
{
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
/* Abort callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
else
{
if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
{
/* Clear transfer complete flag */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
/* Enable the transfer complete interrupts */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
/* Perform an abort of the OctoSPI */
SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
}
else
{
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
/* Abort callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
/* Return function status */
return status;
}
/** @brief Set OSPI Fifo threshold.
* @param hospi : OSPI handle.
* @param Threshold : Threshold of the Fifo.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the state */
if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0U)
{
/* Synchronize initialization structure with the new fifo threshold value */
hospi->Init.FifoThreshold = Threshold;
/* Configure new fifo threshold */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos));
}
else
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE;
}
/* Return function status */
return status;
}
/** @brief Get OSPI Fifo threshold.
* @param hospi : OSPI handle.
* @retval Fifo threshold
*/
uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi)
{
return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U);
}
/** @brief Set OSPI timeout.
* @param hospi : OSPI handle.
* @param Timeout : Timeout for the memory access.
* @retval None
*/
HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout)
{
hospi->Timeout = Timeout;
return HAL_OK;
}
/**
* @brief Return the OSPI error code.
* @param hospi : OSPI handle
* @retval OSPI Error Code
*/
uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi)
{
return hospi->ErrorCode;
}
/**
* @brief Return the OSPI handle state.
* @param hospi : OSPI handle
* @retval HAL state
*/
uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi)
{
/* Return OSPI handle state */
return hospi->State;
}
/**
* @}
*/
/** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function
* @brief OSPI IO Manager configuration function
*
@verbatim
===============================================================================
##### IO Manager configuration function #####
===============================================================================
[..]
This subsection provides a set of functions allowing to :
(+) Configure the IO manager.
@endverbatim
* @{
*/
/**
* @brief Configure the OctoSPI IO manager.
* @param hospi : OSPI handle
* @param cfg : Configuration of the IO Manager for the instance
* @param Timeout : Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t instance;
uint8_t index;
uint8_t ospi_enabled = 0U;
uint8_t other_instance;
OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE];
/* Prevent unused argument(s) compilation warning */
UNUSED(Timeout);
/* Check the parameters of the OctoSPI IO Manager configuration structure */
assert_param(IS_OSPIM_PORT(cfg->ClkPort));
assert_param(IS_OSPIM_DQS_PORT(cfg->DQSPort));
assert_param(IS_OSPIM_PORT(cfg->NCSPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort));
assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort));
if (hospi->Instance == (OCTOSPI_TypeDef *)OCTOSPI1)
{
instance = 0U;
other_instance = 1U;
}
else
{
instance = 1U;
other_instance = 0U;
}
/**************** Get current configuration of the instances ****************/
for (index = 0U; index < OSPI_NB_INSTANCE; index++)
{
if (OSPIM_GetConfig(index + 1U, &(IOM_cfg[index])) != HAL_OK)
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
}
}
if (status == HAL_OK)
{
/********** Disable both OctoSPI to configure OctoSPI IO Manager **********/
if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0U)
{
CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN);
ospi_enabled |= 0x1U;
}
if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0U)
{
CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN);
ospi_enabled |= 0x2U;
}
/***************** Deactivation of previous configuration *****************/
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN);
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
/* De-multiplexing should be performed */
CLEAR_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
if (other_instance == 1U)
{
SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKSRC);
if (IOM_cfg[other_instance].DQSPort != 0U)
{
SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSSRC);
}
if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
OCTOSPIM_PCR_IOLSRC_1);
}
if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
OCTOSPIM_PCR_IOHSRC_1);
}
}
}
else
{
if (IOM_cfg[instance].ClkPort != 0U)
{
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN);
if (IOM_cfg[instance].DQSPort != 0U)
{
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN);
}
if (IOM_cfg[instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
}
if (IOM_cfg[instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
}
}
}
/********************* Deactivation of other instance *********************/
if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) ||
(cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
(cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) &&
(cfg->DQSPort == IOM_cfg[other_instance].DQSPort) &&
(cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) &&
(cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
{
/* Multiplexing should be performed */
SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN);
}
else
{
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN);
if (IOM_cfg[other_instance].DQSPort != 0U)
{
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN);
}
CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN);
if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
OCTOSPIM_PCR_IOLEN);
}
if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
OCTOSPIM_PCR_IOHEN);
}
}
}
/******************** Activation of new configuration *********************/
MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC),
(OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
if (((cfg->Req2AckTime) >= 1U) && ((cfg->Req2AckTime) <= 256U))
{
if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos))
{
MODIFY_REG(OCTOSPIM->CR, OCTOSPIM_CR_REQ2ACK_TIME, ((cfg->Req2AckTime - 1U) << OCTOSPIM_CR_REQ2ACK_TIME_Pos));
}
else
{
/* Nothing to do */
}
}
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
if (cfg->DQSPort != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
}
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
}
else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
}
else
{
/* Nothing to do */
}
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
}
else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
}
else
{
/* Nothing to do */
}
}
else
{
MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC),
(OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
if (cfg->DQSPort != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC),
(OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
}
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
(OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U))));
}
else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
(OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U))));
}
else
{
/* Nothing to do */
}
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
(OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U))));
}
else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
(OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U))));
}
else
{
/* Nothing to do */
}
}
/******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/
if ((ospi_enabled & 0x1U) != 0U)
{
SET_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN);
}
if ((ospi_enabled & 0x2U) != 0U)
{
SET_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN);
}
}
/* Return function status */
return status;
}
/**
* @}
*/
/**
@cond 0
*/
/**
* @brief DMA OSPI process complete callback.
* @param hdma : DMA handle
* @retval None
*/
static void OSPI_DMACplt(DMA_HandleTypeDef *hdma)
{
OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
hospi->XferCount = 0;
/* Disable the DMA transfer on the OctoSPI side */
CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
/* Enable the OSPI transfer complete Interrupt */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
}
/**
* @brief DMA OSPI process half complete callback.
* @param hdma : DMA handle
* @retval None
*/
static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma)
{
OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
hospi->XferCount = (hospi->XferCount >> 1);
if (hospi->State == HAL_OSPI_STATE_BUSY_RX)
{
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->RxHalfCpltCallback(hospi);
#else
HAL_OSPI_RxHalfCpltCallback(hospi);
#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
else
{
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->TxHalfCpltCallback(hospi);
#else
HAL_OSPI_TxHalfCpltCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
/**
* @brief DMA OSPI communication error callback.
* @param hdma : DMA handle
* @retval None
*/
static void OSPI_DMAError(DMA_HandleTypeDef *hdma)
{
OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
hospi->XferCount = 0;
hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
/* Disable the DMA transfer on the OctoSPI side */
CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
/* Abort the OctoSPI */
if (HAL_OSPI_Abort_IT(hospi) != HAL_OK)
{
/* Disable the interrupts */
__HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
/* Error callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
/**
* @brief DMA OSPI abort complete callback.
* @param hdma : DMA handle
* @retval None
*/
static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
{
OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent);
hospi->XferCount = 0;
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_ABORT)
{
/* DMA abort called by OctoSPI abort */
if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
{
/* Clear transfer complete flag */
__HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
/* Enable the transfer complete interrupts */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
/* Perform an abort of the OctoSPI */
SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
}
else
{
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
/* Abort callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->AbortCpltCallback(hospi);
#else
HAL_OSPI_AbortCpltCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
}
}
else
{
/* DMA abort called due to a transfer error interrupt */
/* Update state */
hospi->State = HAL_OSPI_STATE_READY;
/* Error callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
hospi->ErrorCallback(hospi);
#else
HAL_OSPI_ErrorCallback(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
}
}
/**
* @brief Wait for a flag state until timeout.
* @param hospi : OSPI handle
* @param Flag : Flag checked
* @param State : Value of the flag expected
* @param Timeout : Duration of the timeout
* @param Tickstart : Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag,
FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is in expected state */
while ((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
/* New check to avoid false timeout detection in case of preemption */
if ((hospi->Instance->SR & Flag) != (uint32_t)State)
{
hospi->State = HAL_OSPI_STATE_ERROR;
hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
}
}
return HAL_OK;
}
/**
* @brief Configure the registers for the regular command mode.
* @param hospi : OSPI handle
* @param cmd : structure that contains the command configuration information
* @retval HAL status
*/
static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd)
{
HAL_StatusTypeDef status = HAL_OK;
__IO uint32_t *ccr_reg;
__IO uint32_t *tcr_reg;
__IO uint32_t *ir_reg;
__IO uint32_t *abr_reg;
/* Re-initialize the value of the functional mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U);
/* Configure the flash ID */
if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE)
{
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_MSEL, cmd->FlashId);
}
if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
{
ccr_reg = &(hospi->Instance->WCCR);
tcr_reg = &(hospi->Instance->WTCR);
ir_reg = &(hospi->Instance->WIR);
abr_reg = &(hospi->Instance->WABR);
}
else if (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG)
{
ccr_reg = &(hospi->Instance->WPCCR);
tcr_reg = &(hospi->Instance->WPTCR);
ir_reg = &(hospi->Instance->WPIR);
abr_reg = &(hospi->Instance->WPABR);
}
else
{
ccr_reg = &(hospi->Instance->CCR);
tcr_reg = &(hospi->Instance->TCR);
ir_reg = &(hospi->Instance->IR);
abr_reg = &(hospi->Instance->ABR);
}
/* Configure the CCR register with DQS and SIOO modes */
*ccr_reg = (cmd->DQSMode | cmd->SIOOMode);
if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
{
/* Configure the ABR register with alternate bytes value */
*abr_reg = cmd->AlternateBytes;
/* Configure the CCR register with alternate bytes communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE),
(cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize));
}
/* Configure the TCR register with the number of dummy cycles */
MODIFY_REG((*tcr_reg), OCTOSPI_TCR_DCYC, cmd->DummyCycles);
if (cmd->DataMode != HAL_OSPI_DATA_NONE)
{
if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
{
/* Configure the DLR register with the number of data */
hospi->Instance->DLR = (cmd->NbData - 1U);
}
}
if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
{
if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
{
if (cmd->DataMode != HAL_OSPI_DATA_NONE)
{
/* ---- Command with instruction, address and data ---- */
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
(cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
cmd->DataMode | cmd->DataDtrMode));
}
else
{
/* ---- Command with instruction and address ---- */
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
(cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
/* The DHQC bit is linked with DDTR bit which should be activated */
if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
(cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
{
MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE);
}
}
/* Configure the IR register with the instruction value */
*ir_reg = cmd->Instruction;
/* Configure the AR register with the address value */
hospi->Instance->AR = cmd->Address;
}
else
{
if (cmd->DataMode != HAL_OSPI_DATA_NONE)
{
/* ---- Command with instruction and data ---- */
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
(cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
cmd->DataMode | cmd->DataDtrMode));
}
else
{
/* ---- Command with only instruction ---- */
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE),
(cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
/* The DHQC bit is linked with DDTR bit which should be activated */
if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
(cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
{
MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE);
}
}
/* Configure the IR register with the instruction value */
*ir_reg = cmd->Instruction;
}
}
else
{
if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
{
if (cmd->DataMode != HAL_OSPI_DATA_NONE)
{
/* ---- Command with address and data ---- */
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
(cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
cmd->DataMode | cmd->DataDtrMode));
}
else
{
/* ---- Command with only address ---- */
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
(cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
}
/* Configure the AR register with the instruction value */
hospi->Instance->AR = cmd->Address;
}
else
{
/* ---- Invalid command configuration (no instruction, no address) ---- */
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
}
}
/* Return function status */
return status;
}
/**
* @brief Get the current IOM configuration for an OctoSPI instance.
* @param instance_nb : number of the instance
* @param cfg : configuration of the IO Manager for the instance
* @retval HAL status
*/
static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t reg;
uint32_t value = 0U;
uint32_t index;
if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL))
{
/* Invalid parameter -> error returned */
status = HAL_ERROR;
}
else
{
/* Initialize the structure */
cfg->ClkPort = 0U;
cfg->DQSPort = 0U;
cfg->NCSPort = 0U;
cfg->IOLowPort = 0U;
cfg->IOHighPort = 0U;
if (instance_nb == 2U)
{
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
{
value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC
| OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
}
else
{
value = OCTOSPIM_PCR_NCSSRC;
}
}
/* Get the information about the instance */
for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++)
{
reg = OCTOSPIM->PCR[index];
if ((reg & OCTOSPIM_PCR_CLKEN) != 0U)
{
/* The clock is enabled on this port */
if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC))
{
/* The clock correspond to the instance passed as parameter */
cfg->ClkPort = index + 1U;
}
}
if ((reg & OCTOSPIM_PCR_DQSEN) != 0U)
{
/* The DQS is enabled on this port */
if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC))
{
/* The DQS correspond to the instance passed as parameter */
cfg->DQSPort = index + 1U;
}
}
if ((reg & OCTOSPIM_PCR_NCSEN) != 0U)
{
/* The nCS is enabled on this port */
if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC))
{
/* The nCS correspond to the instance passed as parameter */
cfg->NCSPort = index + 1U;
}
}
if ((reg & OCTOSPIM_PCR_IOLEN) != 0U)
{
/* The IO Low is enabled on this port */
if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1))
{
/* The IO Low correspond to the instance passed as parameter */
if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U)
{
cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index + 1U));
}
else
{
cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index + 1U));
}
}
}
if ((reg & OCTOSPIM_PCR_IOHEN) != 0U)
{
/* The IO High is enabled on this port */
if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1))
{
/* The IO High correspond to the instance passed as parameter */
if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U)
{
cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index + 1U));
}
else
{
cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index + 1U));
}
}
}
}
}
/* Return function status */
return status;
}
/** @defgroup OSPI_Exported_Functions_Group5 Delay Block function
* @brief Delay block function
*
@verbatim
===============================================================================
##### Delay Block function #####
===============================================================================
[..]
This subsection provides a set of functions allowing to :
(+) Configure the delay block.
@endverbatim
* @{
*/
/**
* @brief Set the Delay Block configuration.
* @param hospi : OSPI handle.
* @param pdlyb_cfg: Pointer to DLYB configuration structure.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Enable OCTOSPI Free Running Clock (mandatory) */
SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
/* Update OCTOSPI state */
hospi->State = HAL_OSPI_STATE_BUSY_CMD;
if (hospi->Instance == OCTOSPI1)
{
/* Enable the DelayBlock */
LL_DLYB_Enable(DLYB_OCTOSPI1);
/* Set the Delay Block configuration */
LL_DLYB_SetDelay(DLYB_OCTOSPI1, pdlyb_cfg);
status = HAL_OK;
}
else if (hospi->Instance == OCTOSPI2)
{
/* Enable the DelayBlock */
LL_DLYB_Enable(DLYB_OCTOSPI2);
/* Set the Delay Block configuration */
LL_DLYB_SetDelay(DLYB_OCTOSPI2, pdlyb_cfg);
status = HAL_OK;
}
else
{
/* Nothing to do */
}
/* Abort the current OCTOSPI operation if exist */
(void)HAL_OSPI_Abort(hospi);
/* Disable Free Running Clock */
CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
/* Return function status */
return status;
}
/**
* @brief Get the Delay Block configuration.
* @param hospi : OSPI handle.
* @param pdlyb_cfg: Pointer to DLYB configuration structure.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg)
{
HAL_StatusTypeDef status = HAL_ERROR;
if (hospi->Instance == OCTOSPI1)
{
LL_DLYB_GetDelay(DLYB_OCTOSPI1, pdlyb_cfg);
status = HAL_OK;
}
else if (hospi->Instance == OCTOSPI2)
{
LL_DLYB_GetDelay(DLYB_OCTOSPI2, pdlyb_cfg);
status = HAL_OK;
}
else
{
/* Nothing to do */
}
/* Return function status */
return status;
}
/**
* @brief Get the Delay line length value.
* @param hospi : OSPI handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Enable OCTOSPI Free Running Clock (mandatory) */
SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
/* Update OCTOSPI state */
hospi->State = HAL_OSPI_STATE_BUSY_CMD;
if (hospi->Instance == OCTOSPI1)
{
/* Enable the DelayBlock */
LL_DLYB_Enable(DLYB_OCTOSPI1);
/* try to detect Period */
if (LL_DLYB_GetClockPeriod(DLYB_OCTOSPI1, pdlyb_cfg) == (uint32_t)SUCCESS)
{
status = HAL_OK;
}
/* Disable the DelayBlock */
LL_DLYB_Disable(DLYB_OCTOSPI1);
}
else if (hospi->Instance == OCTOSPI2)
{
/* Enable the DelayBlock */
LL_DLYB_Enable(DLYB_OCTOSPI2);
/* try to detect Period */
if (LL_DLYB_GetClockPeriod(DLYB_OCTOSPI2, pdlyb_cfg) == (uint32_t)SUCCESS)
{
status = HAL_OK;
}
/* Disable the DelayBlock */
LL_DLYB_Disable(DLYB_OCTOSPI2);
}
else
{
/* Nothing to do */
}
/* Abort the current OctoSPI operation if exist */
(void)HAL_OSPI_Abort(hospi);
/* Disable Free Running Clock */
CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
/* Return function status */
return status;
}
/**
@endcond
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_OSPI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c
|
C
|
apache-2.0
| 118,418
|
/**
******************************************************************************
* @file stm32u5xx_hal_otfdec.c
* @author MCD Application Team
* @brief OTFDEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the On-The-Fly Decryption/Encryption (OTFDEC)
* peripheral:
* + Initialization and de-initialization functions
* + Region setting/enable functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The OTFDEC HAL driver can be used as follows:
(#) Declare an OTFDEC_HandleTypeDef handle structure (eg. OTFDEC_HandleTypeDef hotfdec).
(#) Initialize the OTFDEC low level resources by implementing the HAL_OTFDEC_MspInit() API:
(++) Enable the OTFDEC interface clock.
(++) NVIC configuration if interrupts are used
(+++) Configure the OTFDEC interrupt priority.
(+++) Enable the NVIC OTFDEC IRQ handle.
(#) Initialize the OTFDEC peripheral by calling the HAL_OTFDEC_Init() API.
(#) In the case of encryption, enable ciphering mode for the peripheral
(#) For each region,
(++) Configure the region deciphering mode by calling the HAL_OTFDEC_RegionSetMode() API.
(++) Write the region Key by calling the HAL_OTFDEC_RegionSetKey() API. If desired,
read the key CRC by calling HAL_OTFDEC_RegionGetKeyCRC() API and compare the
result with the theoretically expected CRC.
(++) Initialize the OTFDEC region config structure with the Nonce, protected
region start and end addresses and firmware version, and wrap-up the region
configuration by calling HAL_OTFDEC_RegionConfig() API.
(#) At this point, the OTFDEC region configuration is done and the deciphering
or enciphering enabled. The region can be deciphered on the fly after
having made sure the OctoSPI is configured in memory-mapped mode or data can
be enciphered by calling HAL_OTFDEC_Cipher() API.
[..]
(@) Warning: the OTFDEC en/deciphering is based on a different endianness compared
to the AES-CTR as implemented in the AES peripheral. E.g., if the OTFEC
resorts to the Key (B0, B1, B2, B3) where Bi are 32-bit longwords and B0
is the Least Significant Word, the AES has to be configured with the Key
(B3, B2, B1, B0) to report the same result (with the same swapping applied
to the Initialization Vector).
[..]
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_OTFDEC_RegisterCallback()
to register an interrupt callback.
[..]
Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
(+) ErrorCallback : OTFDEC error callback
(+) MspInitCallback : OTFDEC Msp Init callback
(+) MspDeInitCallback : OTFDEC Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
weak function.
[..]
@ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) ErrorCallback : OTFDEC error callback
(+) MspInitCallback : OTFDEC Msp Init callback
(+) MspDeInitCallback : OTFDEC Msp DeInit callback
[..]
By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET
all callbacks are set to the corresponding weak functions:
example @ref HAL_OTFDEC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit()
or @ref HAL_OTFDEC_Init() function.
[..]
When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup OTFDEC OTFDEC
* @brief OTFDEC HAL module driver.
* @{
*/
#ifdef HAL_OTFDEC_MODULE_ENABLED
#if defined(OTFDEC1)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup OTFDEC_Exported_Functions
* @{
*/
/** @defgroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Initialize the OTFDEC peripheral and create the associated handle.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec)
{
/* Check the OTFDEC handle allocation */
if (hotfdec == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
if (hotfdec->State == HAL_OTFDEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
__HAL_UNLOCK(hotfdec);
#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
/* Init the OTFDEC Callback settings */
hotfdec->ErrorCallback = HAL_OTFDEC_ErrorCallback; /* Legacy weak callback */
if (hotfdec->MspInitCallback == NULL)
{
hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
hotfdec->MspInitCallback(hotfdec);
#else
/* Init the low level hardware */
HAL_OTFDEC_MspInit(hotfdec);
#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
}
/* Change the OTFDEC state */
hotfdec->State = HAL_OTFDEC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the OTFDEC peripheral.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec)
{
/* Check the OTFDEC handle allocation */
if (hotfdec == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
/* Change the OTFDEC state */
hotfdec->State = HAL_OTFDEC_STATE_BUSY;
#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
if (hotfdec->MspDeInitCallback == NULL)
{
hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: CLOCK, NVIC */
hotfdec->MspDeInitCallback(hotfdec);
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_OTFDEC_MspDeInit(hotfdec);
#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
/* Change the OTFDEC state */
hotfdec->State = HAL_OTFDEC_STATE_RESET;
/* Reset OTFDEC error status */
hotfdec->ErrorCode = HAL_OTFDEC_ERROR_NONE;
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the OTFDEC MSP.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval None
*/
__weak void HAL_OTFDEC_MspInit(OTFDEC_HandleTypeDef *hotfdec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hotfdec);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_OTFDEC_MspInit can be implemented in the user file.
*/
}
/**
* @brief DeInitialize OTFDEC MSP.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval None
*/
__weak void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hotfdec);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_OTFDEC_MspDeInit can be implemented in the user file.
*/
}
#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User OTFDEC Callback
* To be used instead of the weak predefined callback
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_OTFDEC_ERROR_CB_ID OTFDEC error callback ID
* @arg @ref HAL_OTFDEC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_OTFDEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID,
pOTFDEC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (hotfdec->State == HAL_OTFDEC_STATE_READY)
{
switch (CallbackID)
{
case HAL_OTFDEC_ERROR_CB_ID :
hotfdec->ErrorCallback = pCallback;
break;
case HAL_OTFDEC_MSPINIT_CB_ID :
hotfdec->MspInitCallback = pCallback;
break;
case HAL_OTFDEC_MSPDEINIT_CB_ID :
hotfdec->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_OTFDEC_STATE_RESET == hotfdec->State)
{
switch (CallbackID)
{
case HAL_OTFDEC_MSPINIT_CB_ID :
hotfdec->MspInitCallback = pCallback;
break;
case HAL_OTFDEC_MSPDEINIT_CB_ID :
hotfdec->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a OTFDEC Callback
* OTFDEC callback is redirected to the weak predefined callback
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_OTFDEC_ERROR_CB_ID OTFDEC error callback ID
* @arg @ref HAL_OTFDEC_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_OTFDEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (hotfdec->State == HAL_OTFDEC_STATE_READY)
{
switch (CallbackID)
{
case HAL_OTFDEC_ERROR_CB_ID :
hotfdec->ErrorCallback = HAL_OTFDEC_ErrorCallback;
break;
case HAL_OTFDEC_MSPINIT_CB_ID :
hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
break;
case HAL_OTFDEC_MSPDEINIT_CB_ID :
hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_OTFDEC_STATE_RESET == hotfdec->State)
{
switch (CallbackID)
{
case HAL_OTFDEC_MSPINIT_CB_ID :
hotfdec->MspInitCallback = HAL_OTFDEC_MspInit; /* Legacy weak MspInit */
break;
case HAL_OTFDEC_MSPDEINIT_CB_ID :
hotfdec->MspDeInitCallback = HAL_OTFDEC_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hotfdec->ErrorCode |= HAL_OTFDEC_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup OTFDEC_Exported_Functions_Group2 OTFDEC IRQ handler management
* @brief OTFDEC IRQ handler.
*
@verbatim
==============================================================================
##### OTFDEC IRQ handler management #####
==============================================================================
[..] This section provides OTFDEC IRQ handler function.
@endverbatim
* @{
*/
/**
* @brief Handle OTFDEC interrupt request.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval None
*/
void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec)
{
uint32_t isr_reg;
isr_reg = READ_REG(hotfdec->Instance->ISR);
if ((isr_reg & OTFDEC_ISR_SEIF) == OTFDEC_ISR_SEIF)
{
SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_SEIF);
hotfdec->ErrorCode |= HAL_OTFDEC_SECURITY_ERROR;
}
if ((isr_reg & OTFDEC_ISR_XONEIF) == OTFDEC_ISR_XONEIF)
{
SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_XONEIF);
hotfdec->ErrorCode |= HAL_OTFDEC_EXECUTE_ERROR;
}
if ((isr_reg & OTFDEC_ISR_KEIF) == OTFDEC_ISR_KEIF)
{
SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_KEIF);
hotfdec->ErrorCode |= HAL_OTFDEC_KEY_ERROR;
}
#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
hotfdec->ErrorCallback(hotfdec);
#else
HAL_OTFDEC_ErrorCallback(hotfdec);
#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
}
/**
* @brief OTFDEC error callback.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval None
*/
__weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hotfdec);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_OTFDEC_ErrorCallback can be implemented in the user file.
*/
}
/**
* @}
*/
/** @defgroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral control functions.
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection permits to configure the OTFDEC peripheral
@endverbatim
* @{
*/
/**
* @brief Lock region keys.
* @note Writes to this region KEYRx registers are ignored until next OTFDEC reset.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the keys of which are locked
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_KEYLOCK);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @brief Set region keys.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the keys of which are set
* @param pKey pointer at set of keys
* @note The API reads the key CRC computed by the peripheral and compares it with that
* theoretically expected. An error is reported if they are different.
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey)
{
OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
if (pKey == NULL)
{
return HAL_ERROR;
}
else
{
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Set Key */
WRITE_REG(region->REG_KEYR0, pKey[0]);
__DSB();
__ISB();
WRITE_REG(region->REG_KEYR1, pKey[1]);
__DSB();
__ISB();
WRITE_REG(region->REG_KEYR2, pKey[2]);
__DSB();
__ISB();
WRITE_REG(region->REG_KEYR3, pKey[3]);
/* Compute theoretically expected CRC and compare it with that reported by the peripheral */
if (HAL_OTFDEC_KeyCRCComputation(pKey) != HAL_OTFDEC_RegionGetKeyCRC(hotfdec, RegionIndex))
{
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
}
/**
* @brief Set region mode.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the mode of which is set
* @param mode This parameter can be only:
* @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES
All read accesses are decrypted (instruction or data)
* @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER
Only instruction accesses are decrypted with proprietary cipher activated
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode)
{
OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
assert_param(IS_OTFDEC_REGION_OPERATING_MODE(mode));
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Set mode */
MODIFY_REG(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_MODE, mode);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @brief Set region configuration.
* @note Region enciphering/deciphering is enabled at the end of this function
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region that is configured
* @param Config pointer on structure containing the region configuration parameters
* @param lock configuration lock enable or disable parameter
* This parameter can be one of the following values:
* @arg @ref OTFDEC_REG_CONFIGR_LOCK_DISABLE OTFDEC region configuration is not locked
* @arg @ref OTFDEC_REG_CONFIGR_LOCK_ENABLE OTFDEC region configuration is locked
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
{
OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
assert_param(IS_OTFDEC_REGION_CONFIG_LOCK(lock));
if (Config == NULL)
{
return HAL_ERROR;
}
else
{
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Set Nonce */
WRITE_REG(region->REG_NONCER0, Config->Nonce[0]);
WRITE_REG(region->REG_NONCER1, Config->Nonce[1]);
/* Write region protected area start and end addresses */
WRITE_REG(region->REG_START_ADDR, Config->StartAddress);
WRITE_REG(region->REG_END_ADDR, Config->EndAddress);
/* Write Version */
MODIFY_REG(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION,
(uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos);
/* Enable region deciphering or enciphering (depending of OTFDEC_CR ENC bit setting) */
SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
/* Lock the region configuration according to lock parameter value */
if (lock == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
{
SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE);
}
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
}
/**
* @brief Configure OTFDEC attributes.
* @note This function sets or resets regions privileged access protection.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param Attributes This parameter can be only:
* @arg @ref OTFDEC_ATTRIBUTE_PRIV Set privileged access protection
* @arg @ref OTFDEC_ATTRIBUTE_NPRIV Reset privileged access protection
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_ConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t Attributes)
{
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_ATTRIBUTE(Attributes));
/* Take Lock */
__HAL_LOCK(hotfdec);
MODIFY_REG(hotfdec->Instance->PRIVCFGR, OTFDEC_PRIVCFGR_PRIV, Attributes);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @brief Compute Key CRC
* @param pKey pointer at set of keys
* @retval CRC value
*/
uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
{
uint8_t crc7_poly = 0x7;
uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U};
uint8_t i;
uint8_t crc = 0;
uint32_t j;
uint32_t keyval;
uint32_t k;
uint32_t *temp = pKey;
for (j = 0U; j < 4U; j++)
{
keyval = *temp;
temp++;
if (j == 0U)
{
keyval ^= key_strobe[0];
}
else
{
keyval ^= (key_strobe[j] << 24) | ((uint32_t)crc << 16) | (key_strobe[j] << 8) | crc;
}
crc = 0;
for (i = 0; i < (uint8_t)32; i++)
{
k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31 - i)) & ((uint8_t)0xF)))) & 1U;
crc <<= 1;
if (k != 0U)
{
crc ^= crc7_poly;
}
}
crc ^= (uint8_t)0x55;
}
return (uint32_t) crc;
}
/**
* @brief Enable peripheral enciphering.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @note By default, deciphering mode is enabled at reset
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_EnableEnciphering(OTFDEC_HandleTypeDef *hotfdec)
{
/* Take Lock */
__HAL_LOCK(hotfdec);
SET_BIT(hotfdec->Instance->CR, OTFDEC_CR_ENC);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @brief Disable peripheral enciphering.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_DisableEnciphering(OTFDEC_HandleTypeDef *hotfdec)
{
/* Take Lock */
__HAL_LOCK(hotfdec);
CLEAR_BIT(hotfdec->Instance->CR, OTFDEC_CR_ENC);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @brief Cipher data.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the configuration of which is used to encipher
* @param input plain data
* @param output ciphered data
* @param size plain data size in words
* @param start_address starting address in the external memory area
where the enciphered data will be eventually stored
* @note Region configuration parameters and OTFDEC_CR ENC bit must be set.
* @note output pointer points at a temporary area in RAM to store the ciphered data. It is up to the user code
* to copy the ciphered data in external RAM once the enciphering process is over.
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
uint32_t *input, uint32_t *output, uint32_t size, uint32_t start_address)
{
uint32_t j;
__IO uint32_t *extMem_ptr = (uint32_t *)start_address;
uint32_t *in_ptr = input;
uint32_t *out_ptr = output;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
/* Prevent unused argument(s) compilation warning */
UNUSED(RegionIndex);
if ((input == NULL) || (output == NULL) || (size == 0U))
{
return HAL_ERROR;
}
else
{
/* Take Lock */
__HAL_LOCK(hotfdec);
for (j = 0; j < size; j++)
{
*extMem_ptr = *in_ptr;
in_ptr++;
*out_ptr = *extMem_ptr;
out_ptr++;
extMem_ptr++;
}
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
}
/**
* @brief Enable region processing (enciphering or deciphering).
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the enciphering or deciphering is enabled
* @note An error is reported when the configuration is locked.
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
if (READ_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
{
/* Configuration is locked, REG_EN bit can't be modified */
__HAL_UNLOCK(hotfdec);
return HAL_ERROR;
}
/* Enable region processing */
SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @brief Disable region processing (enciphering or deciphering).
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the enciphering or deciphering is disabled
* @note An error is reported when the configuration is locked.
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
if (READ_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
{
/* Configuration is locked, REG_EN bit can't be modified */
__HAL_UNLOCK(hotfdec);
return HAL_ERROR;
}
/* Disable region processing */
CLEAR_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions
* @brief Peripheral State functions.
*
@verbatim
==============================================================================
##### Peripheral State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the OTFDEC state.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @retval HAL state
*/
HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec)
{
return hotfdec->State;
}
/**
* @brief Get OTFDEC configuration attributes.
* @note This function returns whether or not the regions access protection is in privileged mode.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param Attributes pointer to attributes variable. This parameter can be only:
* @arg @ref OTFDEC_ATTRIBUTE_PRIV Set privileged access protection
* @arg @ref OTFDEC_ATTRIBUTE_NPRIV Reset privileged access protection
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_GetConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t *Attributes)
{
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
/* Take Lock */
__HAL_LOCK(hotfdec);
*Attributes = READ_BIT(hotfdec->Instance->PRIVCFGR, OTFDEC_PRIVCFGR_PRIV);
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
/**
* @brief Return region keys CRC.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the keys CRC of which is read
* @retval Key CRC
*/
uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
{
OTFDEC_Region_TypeDef *region;
uint32_t address;
uint32_t keycrc;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
keycrc = (READ_REG(region->REG_CONFIGR)) & OTFDEC_REG_CONFIGR_KEYCRC;
keycrc >>= OTFDEC_REG_CONFIGR_KEYCRC_Pos;
return keycrc;
}
/**
* @brief Return region configuration parameters.
* @param hotfdec pointer to an OTFDEC_HandleTypeDef structure that contains
* the configuration information for OTFDEC module
* @param RegionIndex index of region the configuration of which is read
* @param Config pointer on structure that will be filled up with the region configuration parameters
* @retval HAL state
*/
HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
OTFDEC_RegionConfigTypeDef *Config)
{
OTFDEC_Region_TypeDef *region;
uint32_t address;
/* Check the parameters */
assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
if (Config == NULL)
{
return HAL_ERROR;
}
else
{
/* Take Lock */
__HAL_LOCK(hotfdec);
address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
region = (OTFDEC_Region_TypeDef *)address;
/* Read Nonce */
Config->Nonce[0] = READ_REG(region->REG_NONCER0);
Config->Nonce[1] = READ_REG(region->REG_NONCER1);
/* Read Addresses */
Config->StartAddress = READ_REG(region->REG_START_ADDR);
Config->EndAddress = READ_REG(region->REG_END_ADDR);
/* Read Version */
Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) &
OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos;
/* Release Lock */
__HAL_UNLOCK(hotfdec);
/* Status is okay */
return HAL_OK;
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* OTFDEC1 */
#endif /* HAL_OTFDEC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c
|
C
|
apache-2.0
| 35,812
|
/**
******************************************************************************
* @file stm32u5xx_hal_pcd.c
* @author MCD Application Team
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The PCD HAL driver can be used as follows:
(#) Declare a PCD_HandleTypeDef handle structure, for example:
PCD_HandleTypeDef hpcd;
(#) Fill parameters of Init structure in HCD handle
(#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
(+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
(+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
(##) Configure PCD NVIC interrupt
(#)Associate the Upper USB device stack to the HAL PCD Driver:
(##) hpcd.pData = pdev;
(#)Enable PCD transmission and reception:
(##) HAL_PCD_Start();
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup PCD PCD
* @brief PCD HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup PCD_Private_Functions PCD Private Functions
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
@endverbatim
* @{
*/
/**
* @brief Initializes the PCD according to the specified
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
#if defined (STM32U575xx) || defined (STM32U585xx)
USB_OTG_GlobalTypeDef *USBx;
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
#if defined (STM32U575xx) || defined (STM32U585xx)
USBx = hpcd->Instance;
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
if (hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback = HAL_PCD_SOFCallback;
hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
hpcd->ResetCallback = HAL_PCD_ResetCallback;
hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
if (hpcd->MspInitCallback == NULL)
{
hpcd->MspInitCallback = HAL_PCD_MspInit;
}
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
#if defined (STM32U575xx) || defined (STM32U585xx)
/* Disable DMA mode for FS instance */
if ((USBx->CID & (0x1U << 8)) == 0U)
{
hpcd->Init.dma_enable = 0U;
}
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
{
hpcd->State = HAL_PCD_STATE_ERROR;
return HAL_ERROR;
}
/* Force Device Mode*/
(void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
hpcd->IN_ep[i].num = i;
hpcd->IN_ep[i].tx_fifo_num = i;
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
hpcd->IN_ep[i].maxpacket = 0U;
hpcd->IN_ep[i].xfer_buff = 0U;
hpcd->IN_ep[i].xfer_len = 0U;
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
hpcd->OUT_ep[i].is_in = 0U;
hpcd->OUT_ep[i].num = i;
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
hpcd->OUT_ep[i].maxpacket = 0U;
hpcd->OUT_ep[i].xfer_buff = 0U;
hpcd->OUT_ep[i].xfer_len = 0U;
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
{
hpcd->State = HAL_PCD_STATE_ERROR;
return HAL_ERROR;
}
hpcd->USB_Address = 0U;
hpcd->State = HAL_PCD_STATE_READY;
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1U)
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
}
(void)USB_DevDisconnect(hpcd->Instance);
return HAL_OK;
}
/**
* @brief DeInitializes the PCD peripheral.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
{
/* Check the PCD handle allocation */
if (hpcd == NULL)
{
return HAL_ERROR;
}
hpcd->State = HAL_PCD_STATE_BUSY;
/* Stop Device */
if (USB_StopDevice(hpcd->Instance) != HAL_OK)
{
return HAL_ERROR;
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
if (hpcd->MspDeInitCallback == NULL)
{
hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware */
hpcd->MspDeInitCallback(hpcd);
#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_PCD_MspDeInit(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
hpcd->State = HAL_PCD_STATE_RESET;
return HAL_OK;
}
/**
* @brief Initializes the PCD MSP.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes PCD MSP.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_MspDeInit could be implemented in the user file
*/
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User USB PCD Callback
* To be used instead of the weak predefined callback
* @param hpcd USB PCD handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
* @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
* @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
* @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
switch (CallbackID)
{
case HAL_PCD_SOF_CB_ID :
hpcd->SOFCallback = pCallback;
break;
case HAL_PCD_SETUPSTAGE_CB_ID :
hpcd->SetupStageCallback = pCallback;
break;
case HAL_PCD_RESET_CB_ID :
hpcd->ResetCallback = pCallback;
break;
case HAL_PCD_SUSPEND_CB_ID :
hpcd->SuspendCallback = pCallback;
break;
case HAL_PCD_RESUME_CB_ID :
hpcd->ResumeCallback = pCallback;
break;
case HAL_PCD_CONNECT_CB_ID :
hpcd->ConnectCallback = pCallback;
break;
case HAL_PCD_DISCONNECT_CB_ID :
hpcd->DisconnectCallback = pCallback;
break;
case HAL_PCD_MSPINIT_CB_ID :
hpcd->MspInitCallback = pCallback;
break;
case HAL_PCD_MSPDEINIT_CB_ID :
hpcd->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hpcd->State == HAL_PCD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_PCD_MSPINIT_CB_ID :
hpcd->MspInitCallback = pCallback;
break;
case HAL_PCD_MSPDEINIT_CB_ID :
hpcd->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister an USB PCD Callback
* USB PCD callback is redirected to the weak predefined callback
* @param hpcd USB PCD handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
* @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
* @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
* @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
/* Setup Legacy weak Callbacks */
if (hpcd->State == HAL_PCD_STATE_READY)
{
switch (CallbackID)
{
case HAL_PCD_SOF_CB_ID :
hpcd->SOFCallback = HAL_PCD_SOFCallback;
break;
case HAL_PCD_SETUPSTAGE_CB_ID :
hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
break;
case HAL_PCD_RESET_CB_ID :
hpcd->ResetCallback = HAL_PCD_ResetCallback;
break;
case HAL_PCD_SUSPEND_CB_ID :
hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
break;
case HAL_PCD_RESUME_CB_ID :
hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
break;
case HAL_PCD_CONNECT_CB_ID :
hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
break;
case HAL_PCD_DISCONNECT_CB_ID :
hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
break;
case HAL_PCD_MSPINIT_CB_ID :
hpcd->MspInitCallback = HAL_PCD_MspInit;
break;
case HAL_PCD_MSPDEINIT_CB_ID :
hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
break;
default :
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hpcd->State == HAL_PCD_STATE_RESET)
{
switch (CallbackID)
{
case HAL_PCD_MSPINIT_CB_ID :
hpcd->MspInitCallback = HAL_PCD_MspInit;
break;
case HAL_PCD_MSPDEINIT_CB_ID :
hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
break;
default :
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Register USB PCD Data OUT Stage Callback
* To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
* @param hpcd PCD handle
* @param pCallback pointer to the USB PCD Data OUT Stage Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->DataOutStageCallback = pCallback;
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister the USB PCD Data OUT Stage Callback
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Register USB PCD Data IN Stage Callback
* To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
* @param hpcd PCD handle
* @param pCallback pointer to the USB PCD Data IN Stage Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataInStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->DataInStageCallback = pCallback;
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister the USB PCD Data IN Stage Callback
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Register USB PCD Iso OUT incomplete Callback
* To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoOutIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->ISOOUTIncompleteCallback = pCallback;
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister the USB PCD Iso OUT incomplete Callback
* USB PCD Iso OUT incomplete Callback is redirected
* to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Register USB PCD Iso IN incomplete Callback
* To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoInIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->ISOINIncompleteCallback = pCallback;
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister the USB PCD Iso IN incomplete Callback
* USB PCD Iso IN incomplete Callback is redirected
* to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Register USB PCD BCD Callback
* To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
* @param hpcd PCD handle
* @param pCallback pointer to the USB PCD BCD Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->BCDCallback = pCallback;
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister the USB PCD BCD Callback
* USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Register USB PCD LPM Callback
* To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
* @param hpcd PCD handle
* @param pCallback pointer to the USB PCD LPM Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->LPMCallback = pCallback;
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
/**
* @brief Unregister the USB PCD LPM Callback
* USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpcd);
if (hpcd->State == HAL_PCD_STATE_READY)
{
hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */
}
else
{
/* Update the error code */
hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpcd);
return status;
}
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the PCD data
transfers.
@endverbatim
* @{
*/
/**
* @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
#if defined (STM32U575xx) || defined (STM32U585xx)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
__HAL_LOCK(hpcd);
#if defined (STM32U575xx) || defined (STM32U585xx)
if (hpcd->Init.battery_charging_enable == 1U)
{
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
}
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
__HAL_PCD_ENABLE(hpcd);
(void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Stop the USB device.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
{
#if defined (STM32U575xx) || defined (STM32U585xx)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
(void)USB_DevDisconnect(hpcd->Instance);
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
#if defined (STM32U575xx) || defined (STM32U585xx)
if (hpcd->Init.battery_charging_enable == 1U)
{
/* Disable USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
}
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
USB_OTG_EPTypeDef *ep;
uint32_t i;
uint32_t ep_intr;
uint32_t epint;
uint32_t epnum;
uint32_t fifoemptymsk;
uint32_t RegVal;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
{
/* avoid spurious interrupt */
if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
{
return;
}
/* store current frame number */
hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
{
/* incorrect mode, acknowledge the interrupt */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
/* Handle RxQLevel Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
RegVal = USBx->GRXSTSP;
ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
{
if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
{
(void)USB_ReadPacket(USBx, ep->xfer_buff,
(uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
}
}
else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
{
(void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
}
else
{
/* ... */
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
epnum = 0U;
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
while (ep_intr != 0U)
{
if ((ep_intr & 0x1U) != 0U)
{
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
(void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
}
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
/* Class B setup phase done for previous decoded setup */
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
}
if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
}
/* Clear OUT Endpoint disable interrupt */
if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
{
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
}
ep = &hpcd->OUT_ep[epnum];
if (ep->is_iso_incomplete == 1U)
{
ep->is_iso_incomplete = 0U;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
}
/* Clear Status Phase Received interrupt */
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
/* Clear OUT NAK interrupt */
if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
}
}
epnum++;
ep_intr >>= 1U;
}
}
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
{
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
epnum = 0U;
while (ep_intr != 0U)
{
if ((ep_intr & 0x1U) != 0U) /* In ITR */
{
epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
if (hpcd->Init.dma_enable == 1U)
{
hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
/* this is ZLP, so prepare EP0 for next setup */
if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))
{
/* prepare to rx more setup packets */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
}
if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
}
if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
}
if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
{
(void)USB_FlushTxFifo(USBx, epnum);
ep = &hpcd->IN_ep[epnum];
if (ep->is_iso_incomplete == 1U)
{
ep->is_iso_incomplete = 0U;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
}
if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
{
(void)PCD_WriteEmptyTxFifo(hpcd, epnum);
}
}
epnum++;
ep_intr >>= 1U;
}
}
/* Handle Resume Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
{
/* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
if (hpcd->LPM_State == LPM_L1)
{
hpcd->LPM_State = LPM_L0;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResumeCallback(hpcd);
#else
HAL_PCD_ResumeCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
}
/* Handle Suspend Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
{
if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
/* Handle LPM Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
if (hpcd->LPM_State == LPM_L0)
{
hpcd->LPM_State = LPM_L1;
hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
#else
HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SuspendCallback(hpcd);
#else
HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/* Handle Reset Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
(void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
{
USBx_INEP(i)->DIEPINT = 0xFB7FU;
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
}
USBx_DEVICE->DAINTMSK |= 0x10001U;
if (hpcd->Init.use_dedicated_ep1 != 0U)
{
USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
USB_OTG_DOEPMSK_XFRCM |
USB_OTG_DOEPMSK_EPDM;
USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
USB_OTG_DIEPMSK_XFRCM |
USB_OTG_DIEPMSK_EPDM;
}
else
{
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
USB_OTG_DOEPMSK_XFRCM |
USB_OTG_DOEPMSK_EPDM |
USB_OTG_DOEPMSK_OTEPSPRM |
USB_OTG_DOEPMSK_NAKM;
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
USB_OTG_DIEPMSK_XFRCM |
USB_OTG_DIEPMSK_EPDM;
}
/* Set Default Address to 0 */
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
/* setup EP0 to receive SETUP packets */
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
(uint8_t *)hpcd->Setup);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
}
/* Handle Enumeration done Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
{
(void)USB_ActivateSetup(hpcd->Instance);
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
/* Set USB Turnaround time */
(void)USB_SetTurnaroundTime(hpcd->Instance,
HAL_RCC_GetHCLKFreq(),
(uint8_t)hpcd->Init.speed);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
#else
HAL_PCD_ResetCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
/* Handle SOF Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SOFCallback(hpcd);
#else
HAL_PCD_SOFCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
}
/* Handle Global OUT NAK effective Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
{
USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
{
if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
{
/* Abort current transaction and disable the EP */
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
}
}
}
/* Handle Incomplete ISO IN Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
{
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
{
RegVal = USBx_INEP(epnum)->DIEPCTL;
if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
{
hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
/* Abort current transaction and disable the EP */
(void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
}
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
}
/* Handle Incomplete ISO OUT Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
{
RegVal = USBx_OUTEP(epnum)->DOEPCTL;
if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U)))
{
hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
break;
}
}
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
/* Handle Connection event Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ConnectCallback(hpcd);
#else
HAL_PCD_ConnectCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
}
/* Handle Disconnection event Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
{
RegVal = hpcd->Instance->GOTGINT;
if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DisconnectCallback(hpcd);
#else
HAL_PCD_DisconnectCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
hpcd->Instance->GOTGINT |= RegVal;
}
}
}
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @brief Data OUT stage callback.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implemented in the user file
*/
}
/**
* @brief Data IN stage callback
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DataInStageCallback could be implemented in the user file
*/
}
/**
* @brief Setup stage callback
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SetupStageCallback could be implemented in the user file
*/
}
/**
* @brief USB Start Of Frame callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SOFCallback could be implemented in the user file
*/
}
/**
* @brief USB Reset callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ResetCallback could be implemented in the user file
*/
}
/**
* @brief Suspend event callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SuspendCallback could be implemented in the user file
*/
}
/**
* @brief Resume event callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ResumeCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO OUT callback.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
*/
}
/**
* @brief Incomplete ISO IN callback.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
*/
}
/**
* @brief Connection event callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ConnectCallback could be implemented in the user file
*/
}
/**
* @brief Disconnection event callback.
* @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DisconnectCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
* @brief management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the PCD data
transfers.
@endverbatim
* @{
*/
/**
* @brief Connect the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
{
#if defined (STM32U575xx) || defined (STM32U585xx)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
__HAL_LOCK(hpcd);
#if defined (STM32U575xx) || defined (STM32U585xx)
if (hpcd->Init.battery_charging_enable == 1U)
{
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
}
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
(void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Disconnect the USB device.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
{
#if defined (STM32U575xx) || defined (STM32U585xx)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
__HAL_LOCK(hpcd);
(void)USB_DevDisconnect(hpcd->Instance);
#if defined (STM32U575xx) || defined (STM32U585xx)
if (hpcd->Init.battery_charging_enable == 1U)
{
/* Disable USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
}
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Set the USB Device address.
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
__HAL_LOCK(hpcd);
hpcd->USB_Address = address;
(void)USB_SetDevAddress(hpcd->Instance, address);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Open and configure an endpoint.
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @param ep_mps endpoint max packet size
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
ep->num = ep_addr & EP_ADDR_MSK;
ep->maxpacket = ep_mps;
ep->type = ep_type;
if (ep->is_in != 0U)
{
/* Assign a Tx FIFO */
ep->tx_fifo_num = ep->num;
}
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
{
ep->data_pid_start = 0U;
}
__HAL_LOCK(hpcd);
(void)USB_ActivateEndpoint(hpcd->Instance, ep);
__HAL_UNLOCK(hpcd);
return ret;
}
/**
* @brief Deactivate an endpoint.
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Receive an amount of data.
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
PCD_EPTypeDef *ep;
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 0U;
ep->num = ep_addr & EP_ADDR_MSK;
if (hpcd->Init.dma_enable == 1U)
{
ep->dma_addr = (uint32_t)pBuf;
}
if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
return HAL_OK;
}
/**
* @brief Get Received Data Size
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval Data Size
*/
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
}
/**
* @brief Send an amount of data
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
PCD_EPTypeDef *ep;
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 1U;
ep->num = ep_addr & EP_ADDR_MSK;
if (hpcd->Init.dma_enable == 1U)
{
ep->dma_addr = (uint32_t)pBuf;
}
if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
else
{
(void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
}
return HAL_OK;
}
/**
* @brief Set a STALL condition over an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
{
return HAL_ERROR;
}
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
ep->is_in = 0U;
}
ep->is_stall = 1U;
ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_EPSetStall(hpcd->Instance, ep);
if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Clear a STALL condition over in an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
{
return HAL_ERROR;
}
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 1U;
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
ep->is_stall = 0U;
ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_EPClearStall(hpcd->Instance, ep);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Abort an USB EP transaction.
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
HAL_StatusTypeDef ret;
PCD_EPTypeDef *ep;
if ((0x80U & ep_addr) == 0x80U)
{
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
}
else
{
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
}
/* Stop Xfer */
ret = USB_EPStopXfer(hpcd->Instance, ep);
return ret;
}
/**
* @brief Flush an endpoint
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
__HAL_LOCK(hpcd);
if ((ep_addr & 0x80U) == 0x80U)
{
(void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);
}
else
{
(void)USB_FlushRxFifo(hpcd->Instance);
}
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Activate remote wakeup signalling
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
return (USB_ActivateRemoteWakeup(hpcd->Instance));
}
/**
* @brief De-activate remote wakeup signalling.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
return (USB_DeActivateRemoteWakeup(hpcd->Instance));
}
/**
* @}
*/
/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the PCD handle state.
* @param hpcd PCD handle
* @retval HAL state
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
{
return hpcd->State;
}
/**
* @brief Set the USB Device high speed test mode.
* @param hpcd PCD handle
* @param testmode USB Device high speed test mode
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
switch (testmode)
{
case TEST_J:
case TEST_K:
case TEST_SE0_NAK:
case TEST_PACKET:
case TEST_FORCE_EN:
USBx_DEVICE->DCTL |= (uint32_t)testmode << 4;
break;
default:
break;
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup PCD_Private_Functions
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Check FIFO for the next packet to be loaded.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
USB_OTG_EPTypeDef *ep;
uint32_t len;
uint32_t len32b;
uint32_t fifoemptymsk;
ep = &hpcd->IN_ep[epnum];
if (ep->xfer_count > ep->xfer_len)
{
return HAL_ERROR;
}
len = ep->xfer_len - ep->xfer_count;
if (len > ep->maxpacket)
{
len = ep->maxpacket;
}
len32b = (len + 3U) / 4U;
while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&
(ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))
{
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;
if (len > ep->maxpacket)
{
len = ep->maxpacket;
}
len32b = (len + 3U) / 4U;
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
(uint8_t)hpcd->Init.dma_enable);
ep->xfer_buff += len;
ep->xfer_count += len;
}
if (ep->xfer_len <= ep->xfer_count)
{
fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
}
return HAL_OK;
}
/**
* @brief process EP OUT transfer complete interrupt.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_EPTypeDef *ep;
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (hpcd->Init.dma_enable == 1U)
{
if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
{
/* StupPktRcvd = 1 this is a setup packet */
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
}
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
{
/* StupPktRcvd = 1 this is a setup packet */
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
else
{
ep = &hpcd->OUT_ep[epnum];
/* out data packet received over EP */
ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
if (epnum == 0U)
{
if (ep->xfer_len == 0U)
{
/* this is ZLP, so prepare EP0 for next setup */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
else
{
ep->xfer_buff += ep->xfer_count;
}
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
else
{
/* ... */
}
}
else
{
if (gSNPSiD == USB_OTG_CORE_ID_310A)
{
/* StupPktRcvd = 1 this is a setup packet */
if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
else
{
if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
else
{
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
{
/* this is ZLP, so prepare EP0 for next setup */
(void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
return HAL_OK;
}
/**
* @brief process EP OUT setup packet received interrupt.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
/* Inform the upper layer that a setup packet is available */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
{
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
return HAL_OK;
}
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c
|
C
|
apache-2.0
| 63,254
|
/**
******************************************************************************
* @file stm32u5xx_hal_pcd_ex.c
* @author MCD Application Team
* @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Extended features functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Update FIFO configuration
@endverbatim
* @{
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* @brief Set Tx FIFO
* @param hpcd PCD handle
* @param fifo The number of Tx fifo
* @param size Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
uint8_t i;
uint32_t Tx_Offset;
/* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows:
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txm can use the space allocated for Txn.
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txn should be configured with the minimum space of 16 words
The FIFO is used optimally when used TxFIFOs are allocated in the top
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
Tx_Offset = hpcd->Instance->GRXFSIZ;
if (fifo == 0U)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
for (i = 0U; i < (fifo - 1U); i++)
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
}
return HAL_OK;
}
/**
* @brief Set Rx FIFO
* @param hpcd PCD handle
* @param size Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
hpcd->Instance->GRXFSIZ = size;
return HAL_OK;
}
/**
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 1U;
hpcd->LPM_State = LPM_L0;
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
/**
* @brief Deactivate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = 0U;
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
#if defined (STM32U575xx) || defined (STM32U585xx) || defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx)
/**
* @brief Handle BatteryCharging Process.
* @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
/* Wait for Min DCD Timeout */
HAL_Delay(300U);
#if defined (STM32U575xx) || defined (STM32U585xx)
/* Check Detect flag */
if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
/* Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
#if defined (STM32U575xx) || defined (STM32U585xx)
if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
#else
if ((USBx->GCCFG & USB_OTG_GCCFG_CHGDET) == 0U)
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
{
/* Case of Standard Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
HAL_Delay(50U);
#if defined (STM32U575xx) || defined (STM32U585xx)
if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
#else
if ((USBx->GCCFG & USB_OTG_GCCFG_FSVPLUS) == USB_OTG_GCCFG_FSVPLUS)
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
{
/* case Dedicated Charging Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* case Charging Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/* Battery Charging capability discovery finished */
(void)HAL_PCDEx_DeActivateBCD(hpcd);
/* Check for the Timeout, else start USB Device */
if ((HAL_GetTick() - tickstart) > 1000U)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/**
* @brief Activate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
#if defined (STM32U575xx) || defined (STM32U585xx)
/* Power Down USB transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
/* Enable Battery charging */
USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
hpcd->battery_charging_active = 1U;
return HAL_OK;
}
/**
* @brief Deactivate BatteryCharging feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
#if defined (STM32U575xx) || defined (STM32U585xx)
/* Disable Battery charging */
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
#endif /* defined (STM32U575xx) || defined (STM32U585xx) */
hpcd->battery_charging_active = 0U;
return HAL_OK;
}
#endif /* defined (STM32U575xx) || defined (STM32U585xx) || defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @brief Send LPM message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/**
* @brief Send BatteryCharging message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_BCD_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c
|
C
|
apache-2.0
| 10,634
|
/**
******************************************************************************
* @file stm32u5xx_hal_pka.c
* @author MCD Application Team
* @brief PKA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of public key accelerator(PKA):
* + Initialization and de-initialization functions
* + Start an operation
* + Retrieve the operation result
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The PKA HAL driver can be used as follows:
(#) Declare a PKA_HandleTypeDef handle structure, for example: PKA_HandleTypeDef hpka;
(#) Initialize the PKA low level resources by implementing the HAL_PKA_MspInit() API:
(##) Enable the PKA interface clock
(##) NVIC configuration if you need to use interrupt process
(+++) Configure the PKA interrupt priority
(+++) Enable the NVIC PKA IRQ Channel
(#) Initialize the PKA registers by calling the HAL_PKA_Init() API which trig
HAL_PKA_MspInit().
(#) Fill entirely the input structure corresponding to your operation:
For instance: PKA_ModExpInTypeDef for HAL_PKA_ModExp().
(#) Execute the operation (in polling or interrupt) and check the returned value.
(#) Retrieve the result of the operation (For instance, HAL_PKA_ModExp_GetResult for
HAL_PKA_ModExp operation). The function to gather the result is different for each
kind of operation. The correspondence can be found in the following section.
(#) Call the function HAL_PKA_DeInit() to restore the default configuration which trig
HAL_PKA_MspDeInit().
*** High level operation ***
=================================
[..]
(+) Input structure requires buffers as uint8_t array.
(+) Output structure requires buffers as uint8_t array.
(+) Modular exponentiation using:
(++) HAL_PKA_ModExp().
(++) HAL_PKA_ModExp_IT().
(++) HAL_PKA_ModExpFastMode().
(++) HAL_PKA_ModExpFastMode_IT().
(++) HAL_PKA_ModExpProtectMode().
(++) HAL_PKA_ModExpProtectMode_IT().
(++) HAL_PKA_ModExp_GetResult() to retrieve the result of the operation.
(+) RSA Chinese Remainder Theorem (CRT) using:
(++) HAL_PKA_RSACRTExp().
(++) HAL_PKA_RSACRTExp_IT().
(++) HAL_PKA_RSACRTExp_GetResult() to retrieve the result of the operation.
(+) ECC Point Check using:
(++) HAL_PKA_PointCheck().
(++) HAL_PKA_PointCheck_IT().
(++) HAL_PKA_PointCheck_IsOnCurve() to retrieve the result of the operation.
(+) ECDSA Sign
(++) HAL_PKA_ECDSASign().
(++) HAL_PKA_ECDSASign_IT().
(++) HAL_PKA_ECDSASign_GetResult() to retrieve the result of the operation.
(+) ECDSA Verify
(++) HAL_PKA_ECDSAVerif().
(++) HAL_PKA_ECDSAVerif_IT().
(++) HAL_PKA_ECDSAVerif_IsValidSignature() to retrieve the result of the operation.
(+) ECC Scalar Multiplication using:
(++) HAL_PKA_ECCMul().
(++) HAL_PKA_ECCMul_IT().
(++) HAL_PKA_ECCMul_GetResult() to retrieve the result of the operation.
(+) ECC double base ladder using:
(++) HAL_PKA_ECCDoubleBaseLadder().
(++) HAL_PKA_ECCDoubleBaseLadder_IT().
(++) HAL_PKA_ECCDoubleBaseLadder_GetResult() to retrieve the result of the operation.
(+) ECC projective to affine using:
(++) HAL_PKA_ECCProjective2Affine().
(++) HAL_PKA_ECCProjective2Affine_IT().
(++) HAL_PKA_ECCProjective2Affine_GetResult() to retrieve the result of the operation.
(+) ECC complete addition using:
(++) HAL_PKA_ECCCompleteAddition().
(++) HAL_PKA_ECCCompleteAddition_IT().
(++) HAL_PKA_ECCCompleteAddition_GetResult() to retrieve the result of the operation.
*** Low level operation ***
=================================
[..]
(+) Input structure requires buffers as uint32_t array.
(+) Output structure requires buffers as uint32_t array.
(+) Arithmetic addition using:
(++) HAL_PKA_Add().
(++) HAL_PKA_Add_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
The resulting size can be the input parameter or the input parameter size + 1 (overflow).
(+) Arithmetic subtraction using:
(++) HAL_PKA_Sub().
(++) HAL_PKA_Sub_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
(+) Arithmetic multiplication using:
(++) HAL_PKA_Mul().
(++) HAL_PKA_Mul_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
(+) Comparison using:
(++) HAL_PKA_Cmp().
(++) HAL_PKA_Cmp_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
(+) Modular addition using:
(++) HAL_PKA_ModAdd().
(++) HAL_PKA_ModAdd_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
(+) Modular subtraction using:
(++) HAL_PKA_ModSub().
(++) HAL_PKA_ModSub_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
(+) Modular inversion using:
(++) HAL_PKA_ModInv().
(++) HAL_PKA_ModInv_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
(+) Modular reduction using:
(++) HAL_PKA_ModRed().
(++) HAL_PKA_ModRed_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
(+) Montgomery multiplication using:
(++) HAL_PKA_MontgomeryMul().
(++) HAL_PKA_MontgomeryMul_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
*** Montgomery parameter ***
=================================
(+) For some operation, the computation of the Montgomery parameter is a prerequisite.
(+) Input structure requires buffers as uint8_t array.
(+) Output structure requires buffers as uint32_t array.(Only used inside PKA).
(+) You can compute the Montgomery parameter using:
(++) HAL_PKA_MontgomeryParam().
(++) HAL_PKA_MontgomeryParam_IT().
(++) HAL_PKA_MontgomeryParam_GetResult() to retrieve the result of the operation.
*** Polling mode operation ***
===================================
[..]
(+) When an operation is started in polling mode, the function returns when:
(++) A timeout is encounter.
(++) The operation is completed.
*** Interrupt mode operation ***
===================================
[..]
(+) Add HAL_PKA_IRQHandler to the IRQHandler of PKA.
(+) Enable the IRQ using HAL_NVIC_EnableIRQ().
(+) When an operation is started in interrupt mode, the function returns immediately.
(+) When the operation is completed, the callback HAL_PKA_OperationCpltCallback is called.
(+) When an error is encountered, the callback HAL_PKA_ErrorCallback is called.
(+) To stop any operation in interrupt mode, use HAL_PKA_Abort().
*** Utilities ***
===================================
[..]
(+) To clear the PKA RAM, use HAL_PKA_RAMReset().
(+) To get current state, use HAL_PKA_GetState().
(+) To get current error, use HAL_PKA_GetError().
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
Use Functions HAL_PKA_RegisterCallback()
to register an interrupt callback.
[..]
Function HAL_PKA_RegisterCallback() allows to register following callbacks:
(+) OperationCpltCallback : callback for End of operation.
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
Use function HAL_PKA_UnRegisterCallback to reset a callback to the default
weak function.
[..]
HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) OperationCpltCallback : callback for End of operation.
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
By default, after the HAL_PKA_Init() and when the state is HAL_PKA_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_PKA_OperationCpltCallback(), HAL_PKA_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the HAL_PKA_Init()/ HAL_PKA_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
If MspInit or MspDeInit are not null, the HAL_PKA_Init()/ HAL_PKA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in HAL_PKA_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_PKA_STATE_READY or HAL_PKA_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
using HAL_PKA_RegisterCallback() before calling HAL_PKA_DeInit()
or HAL_PKA_Init() function.
[..]
When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
/** @defgroup PKA PKA
* @brief PKA HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PKA_Private_Define PKA Private Define
* @{
*/
#define PKA_RAM_SIZE 1334U
/* Private macro -------------------------------------------------------------*/
#define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \
TAB[INDEX] = 0UL; \
TAB[INDEX + 1U] = 0UL; \
} while(0)
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup PKA_Private_Functions PKA Private Functions
* @{
*/
uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka);
HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart);
uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode);
uint32_t PKA_GetBitSize_u8(uint32_t byteNumber);
uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb);
uint32_t PKA_GetBitSize_u32(uint32_t wordNumber);
uint32_t PKA_GetArraySize_u8(uint32_t bitSize);
void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n);
void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n);
void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n);
HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout);
HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode);
void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in);
void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1);
void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2,
const uint8_t *pOp3);
void PKA_ECCDoubleBaseLadder_Set(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in);
void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in);
void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in);
HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PKA_Exported_Functions PKA Exported Functions
* @{
*/
/** @defgroup PKA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
deinitialize the PKAx peripheral:
(+) User must implement HAL_PKA_MspInit() function in which he configures
all related peripherals resources (CLOCK, IT and NVIC ).
(+) Call the function HAL_PKA_Init() to configure the device.
(+) Call the function HAL_PKA_DeInit() to restore the default configuration
of the selected PKAx peripheral.
@endverbatim
* @{
*/
/**
* @brief Initialize the PKA according to the specified
* parameters in the PKA_InitTypeDef and initialize the associated handle.
* @param hpka PKA handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka)
{
HAL_StatusTypeDef err = HAL_OK;
uint32_t tickstart;
/* Check the PKA handle allocation */
if (hpka != NULL)
{
/* Check the parameters */
assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance));
if (hpka->State == HAL_PKA_STATE_RESET)
{
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
/* Init the PKA Callback settings */
hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */
hpka->ErrorCallback = HAL_PKA_ErrorCallback; /* Legacy weak ErrorCallback */
if (hpka->MspInitCallback == NULL)
{
hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
hpka->MspInitCallback(hpka);
#else
/* Init the low level hardware */
HAL_PKA_MspInit(hpka);
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
}
/* Set the state to busy */
hpka->State = HAL_PKA_STATE_BUSY;
/* Reset the control register and enable the PKA */
hpka->Instance->CR = PKA_CR_EN;
/* Get current tick */
tickstart = HAL_GetTick();
/* Wait the INITOK flag Setting */
if (PKA_WaitOnFlagUntilTimeout(hpka, PKA_SR_INITOK, RESET, tickstart, 5000) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Reset any pending flag */
SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
/* Initialize the error code */
hpka->ErrorCode = HAL_PKA_ERROR_NONE;
/* Set the state to ready */
hpka->State = HAL_PKA_STATE_READY;
}
else
{
err = HAL_ERROR;
}
return err;
}
/**
* @brief DeInitialize the PKA peripheral.
* @param hpka PKA handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka)
{
HAL_StatusTypeDef err = HAL_OK;
/* Check the PKA handle allocation */
if (hpka != NULL)
{
/* Check the parameters */
assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance));
/* Set the state to busy */
hpka->State = HAL_PKA_STATE_BUSY;
/* Reset the control register */
/* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */
hpka->Instance->CR = 0;
/* Reset any pending flag */
SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
if (hpka->MspDeInitCallback == NULL)
{
hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
hpka->MspDeInitCallback(hpka);
#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_PKA_MspDeInit(hpka);
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
/* Reset the error code */
hpka->ErrorCode = HAL_PKA_ERROR_NONE;
/* Reset the state */
hpka->State = HAL_PKA_STATE_RESET;
}
else
{
err = HAL_ERROR;
}
return err;
}
/**
* @brief Initialize the PKA MSP.
* @param hpka PKA handle
* @retval None
*/
__weak void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpka);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PKA_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the PKA MSP.
* @param hpka PKA handle
* @retval None
*/
__weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpka);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PKA_MspDeInit can be implemented in the user file
*/
}
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User PKA Callback
* To be used instead of the weak predefined callback
* @param hpka Pointer to a PKA_HandleTypeDef structure that contains
* the configuration information for the specified PKA.
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID
* @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID
* @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID,
pPKA_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
if (HAL_PKA_STATE_READY == hpka->State)
{
switch (CallbackID)
{
case HAL_PKA_OPERATION_COMPLETE_CB_ID :
hpka->OperationCpltCallback = pCallback;
break;
case HAL_PKA_ERROR_CB_ID :
hpka->ErrorCallback = pCallback;
break;
case HAL_PKA_MSPINIT_CB_ID :
hpka->MspInitCallback = pCallback;
break;
case HAL_PKA_MSPDEINIT_CB_ID :
hpka->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_PKA_STATE_RESET == hpka->State)
{
switch (CallbackID)
{
case HAL_PKA_MSPINIT_CB_ID :
hpka->MspInitCallback = pCallback;
break;
case HAL_PKA_MSPDEINIT_CB_ID :
hpka->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
/**
* @brief Unregister a PKA Callback
* PKA callback is redirected to the weak predefined callback
* @param hpka Pointer to a PKA_HandleTypeDef structure that contains
* the configuration information for the specified PKA.
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID
* @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID
* @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
if (HAL_PKA_STATE_READY == hpka->State)
{
switch (CallbackID)
{
case HAL_PKA_OPERATION_COMPLETE_CB_ID :
hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */
break;
case HAL_PKA_ERROR_CB_ID :
hpka->ErrorCallback = HAL_PKA_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_PKA_MSPINIT_CB_ID :
hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */
break;
case HAL_PKA_MSPDEINIT_CB_ID :
hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_PKA_STATE_RESET == hpka->State)
{
switch (CallbackID)
{
case HAL_PKA_MSPINIT_CB_ID :
hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */
break;
case HAL_PKA_MSPDEINIT_CB_ID :
hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup PKA_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the PKA operations.
(#) There are two modes of operation:
(++) Blocking mode : The operation is performed in the polling mode.
These functions return when data operation is completed.
(++) No-Blocking mode : The operation is performed using Interrupts.
These functions return immediately.
The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error.
The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success.
To stop any operation in interrupt mode, use HAL_PKA_Abort().
(#) Blocking mode functions are :
(++) HAL_PKA_ModExp()
(++) HAL_PKA_ModExpFastMode()
(++) HAL_PKA_ModExpProtectMode()
(++) HAL_PKA_ModExp_GetResult();
(++) HAL_PKA_ECDSASign()
(++) HAL_PKA_ECDSASign_GetResult();
(++) HAL_PKA_ECDSAVerif()
(++) HAL_PKA_ECDSAVerif_IsValidSignature();
(++) HAL_PKA_RSACRTExp()
(++) HAL_PKA_RSACRTExp_GetResult();
(++) HAL_PKA_PointCheck()
(++) HAL_PKA_PointCheck_IsOnCurve();
(++) HAL_PKA_ECCMul()
(++) HAL_PKA_ECCMulFastMode()
(++) HAL_PKA_ECCMul_GetResult();
(++) HAL_PKA_ECCDoubleBaseLadder()
(++) HAL_PKA_ECCDoubleBaseLadder_GetResult();
(++) HAL_PKA_ECCProjective2Affine()
(++) HAL_PKA_ECCProjective2Affine_GetResult();
(++) HAL_PKA_ECCCompleteAddition()
(++) HAL_PKA_ECCCompleteAddition_GetResult();
(++) HAL_PKA_Add()
(++) HAL_PKA_Sub()
(++) HAL_PKA_Cmp()
(++) HAL_PKA_Mul()
(++) HAL_PKA_ModAdd()
(++) HAL_PKA_ModSub()
(++) HAL_PKA_ModInv()
(++) HAL_PKA_ModRed()
(++) HAL_PKA_MontgomeryMul()
(++) HAL_PKA_Arithmetic_GetResult(P);
(++) HAL_PKA_MontgomeryParam()
(++) HAL_PKA_MontgomeryParam_GetResult();
(#) No-Blocking mode functions with Interrupt are :
(++) HAL_PKA_ModExp_IT();
(++) HAL_PKA_ModExpFastMode_IT();
(++) HAL_PKA_ModExpProtectMode_IT()
(++) HAL_PKA_ModExp_GetResult();
(++) HAL_PKA_ECDSASign_IT();
(++) HAL_PKA_ECDSASign_GetResult();
(++) HAL_PKA_ECDSAVerif_IT();
(++) HAL_PKA_ECDSAVerif_IsValidSignature();
(++) HAL_PKA_RSACRTExp_IT();
(++) HAL_PKA_RSACRTExp_GetResult();
(++) HAL_PKA_PointCheck_IT();
(++) HAL_PKA_PointCheck_IsOnCurve();
(++) HAL_PKA_ECCMul_IT();
(++) HAL_PKA_ECCMulFastMode_IT();
(++) HAL_PKA_ECCMul_GetResult();
(++) HAL_PKA_ECCDoubleBaseLadder_IT()
(++) HAL_PKA_ECCDoubleBaseLadder_GetResult();
(++) HAL_PKA_ECCProjective2Affine_IT()
(++) HAL_PKA_ECCProjective2Affine_GetResult();
(++) HAL_PKA_ECCCompleteAddition_IT()
(++) HAL_PKA_ECCCompleteAddition_GetResult();
(++) HAL_PKA_Add_IT();
(++) HAL_PKA_Sub_IT();
(++) HAL_PKA_Cmp_IT();
(++) HAL_PKA_Mul_IT();
(++) HAL_PKA_ModAdd_IT();
(++) HAL_PKA_ModSub_IT();
(++) HAL_PKA_ModInv_IT();
(++) HAL_PKA_ModRed_IT();
(++) HAL_PKA_MontgomeryMul_IT();
(++) HAL_PKA_Arithmetic_GetResult();
(++) HAL_PKA_MontgomeryParam_IT();
(++) HAL_PKA_MontgomeryParam_GetResult();
(++) HAL_PKA_Abort();
@endverbatim
* @{
*/
/**
* @brief Modular exponentiation in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ModExp_Set(hpka, in);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout);
}
/**
* @brief Modular exponentiation in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ModExp_Set(hpka, in);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP);
}
/**
* @brief Modular exponentiation in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ModExpFastMode_Set(hpka, in);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout);
}
/**
* @brief Modular exponentiation in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ModExpFastMode_Set(hpka, in);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE);
}
/**
* @brief Modular exponentiation (protected) in blocking mode.
* Useful when a secret information is involved (RSA decryption)
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in,
uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ModExpProtectMode_Set(hpka, in);
return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout);
}
/**
* @brief Modular exponentiation (protected) in non-blocking mode with Interrupt.
* Useful when a secret information is involved (RSA decryption)
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ModExpProtectMode_Set(hpka, in);
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT);
}
/**
* @brief Retrieve operation result.
* @param hpka PKA handle
* @param pRes Output buffer
* @retval HAL status
*/
void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes)
{
uint32_t size;
/* Get output result size */
size = PKA_Result_GetSize(hpka, PKA_MODULAR_EXP_OUT_RESULT, 130UL);
/* Move the result to appropriate location (indicated in out parameter) */
PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size);
}
/**
* @brief Sign a message using elliptic curves over prime fields in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ECDSASign_Set(hpka, in);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout);
}
/**
* @brief Sign a message using elliptic curves over prime fields in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ECDSASign_Set(hpka, in);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE);
}
/**
* @brief Retrieve operation result.
* @param hpka PKA handle
* @param out Output information
* @param outExt Additional Output information (facultative)
*/
void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out,
PKA_ECDSASignOutExtParamTypeDef *outExt)
{
uint32_t size;
/* Get output result size */
size = PKA_Result_GetSize(hpka, PKA_ECDSA_SIGN_OUT_SIGNATURE_R, 20UL);
if (out != NULL)
{
PKA_Memcpy_u32_to_u8(out->RSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], size);
PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size);
}
/* If user requires the additional information */
if (outExt != NULL)
{
/* Move the result to appropriate location (indicated in outExt parameter) */
PKA_Memcpy_u32_to_u8(outExt->ptX, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X], size);
PKA_Memcpy_u32_to_u8(outExt->ptY, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y], size);
}
}
/**
* @brief Verify the validity of a signature using elliptic curves over prime fields in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ECDSAVerif_Set(hpka, in);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ECDSA_VERIFICATION, Timeout);
}
/**
* @brief Verify the validity of a signature using elliptic curves
* over prime fields in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ECDSAVerif_Set(hpka, in);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECDSA_VERIFICATION);
}
/**
* @brief Return the result of the ECDSA verification operation.
* @param hpka PKA handle
* @retval 1 if signature is verified, 0 in other case
*/
uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka)
{
return (hpka->Instance->RAM[PKA_ECDSA_VERIF_OUT_RESULT] == 0xD60DU) ? 1UL : 0UL;
}
/**
* @brief RSA CRT exponentiation in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_RSACRTExp_Set(hpka, in);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_RSA_CRT_EXP, Timeout);
}
/**
* @brief RSA CRT exponentiation in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_RSACRTExp_Set(hpka, in);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_RSA_CRT_EXP);
}
/**
* @brief Retrieve operation result.
* @param hpka PKA handle
* @param pRes Pointer to memory location to receive the result of the operation
* @retval HAL status
*/
void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes)
{
uint32_t size;
/* Move the result to appropriate location (indicated in out parameter) */
size = (hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] + 7UL) / 8UL;
PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_RSA_CRT_EXP_OUT_RESULT], size);
}
/**
* @brief Point on elliptic curve check in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_PointCheck_Set(hpka, in);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout);
}
/**
* @brief Point on elliptic curve check in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_PointCheck_Set(hpka, in);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK);
}
/**
* @brief Return the result of the point check operation.
* @param hpka PKA handle
* @retval 1 if point is on curve, 0 in other case
*/
uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka)
{
#define PKA_POINT_IS_ON_CURVE 0xD60DUL
/* Invert the value of the PKA RAM containing the result of the operation */
return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == PKA_POINT_IS_ON_CURVE) ? 1UL : 0UL;
}
/**
* @brief ECC scalar multiplication in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ECCMul_Set(hpka, in);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout);
}
/**
* @brief ECC scalar multiplication in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ECCMul_Set(hpka, in);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
}
/**
* @brief Retrieve operation result.
* @param hpka PKA handle
* @param out Output information
* @retval HAL status
*/
void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out)
{
uint32_t size;
/* Get output result size */
size = PKA_Result_GetSize(hpka, PKA_ECC_SCALAR_MUL_OUT_RESULT_X, 20UL);
/* If a destination buffer is provided */
if (out != NULL)
{
/* Move the result to appropriate location (indicated in out parameter) */
PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], size);
PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], size);
}
}
/**
* @brief Arithmetic addition in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ARITHMETIC_ADD, Timeout);
}
/**
* @brief Arithmetic addition in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_ADD);
}
/**
* @brief Arithmetic subtraction in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ARITHMETIC_SUB, Timeout);
}
/**
* @brief Arithmetic subtraction in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_SUB);
}
/**
* @brief Arithmetic multiplication in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_ARITHMETIC_MUL, Timeout);
}
/**
* @brief Arithmetic multiplication in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_MUL);
}
/**
* @brief Comparison in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_COMPARISON, Timeout);
}
/**
* @brief Comparison in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_COMPARISON);
}
/**
* @brief Modular addition in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_ADD, Timeout);
}
/**
* @brief Modular addition in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_ADD);
}
/**
* @brief Modular inversion in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ModInv_Set(hpka, in);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_INV, Timeout);
}
/**
* @brief Modular inversion in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ModInv_Set(hpka, in);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_INV);
}
/**
* @brief Modular subtraction in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_SUB, Timeout);
}
/**
* @brief Modular subtraction in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_SUB);
}
/**
* @brief Modular reduction in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ModRed_Set(hpka, in);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MODULAR_RED, Timeout);
}
/**
* @brief Modular reduction in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ModRed_Set(hpka, in);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_RED);
}
/**
* @brief Montgomery multiplication in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MONTGOMERY_MUL, Timeout);
}
/**
* @brief Montgomery multiplication in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_MUL);
}
/**
* @brief Retrieve operation result.
* @param hpka PKA handle
* @param pRes Pointer to memory location to receive the result of the operation
*/
void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes)
{
uint32_t mode = (hpka->Instance->CR & PKA_CR_MODE_Msk) >> PKA_CR_MODE_Pos;
uint32_t size = 0;
/* Move the result to appropriate location (indicated in pRes parameter) */
switch (mode)
{
case PKA_MODE_MONTGOMERY_PARAM:
case PKA_MODE_ARITHMETIC_SUB:
case PKA_MODE_MODULAR_ADD:
case PKA_MODE_MODULAR_RED:
case PKA_MODE_MODULAR_INV:
case PKA_MODE_MONTGOMERY_MUL:
size = hpka->Instance->RAM[2] / 32UL;
break;
case PKA_MODE_ARITHMETIC_ADD:
case PKA_MODE_MODULAR_SUB:
size = hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] / 32UL;
/* Manage the overflow of the addition */
if (hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT + size] != 0UL)
{
size += 1UL;
}
break;
case PKA_MODE_COMPARISON:
size = 1;
break;
case PKA_MODE_ARITHMETIC_MUL:
size = hpka->Instance->RAM[PKA_ARITHMETIC_MUL_NB_BITS] / 32UL * 2UL;
break;
default:
break;
}
if (pRes != NULL)
{
switch (mode)
{
case PKA_MODE_ARITHMETIC_SUB:
case PKA_MODE_MODULAR_ADD:
case PKA_MODE_MODULAR_RED:
case PKA_MODE_MODULAR_INV:
case PKA_MODE_MODULAR_SUB:
case PKA_MODE_MONTGOMERY_MUL:
case PKA_MODE_ARITHMETIC_ADD:
case PKA_MODE_COMPARISON:
case PKA_MODE_ARITHMETIC_MUL:
PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT], size);
break;
default:
break;
}
}
}
/**
* @brief Montgomery parameter computation in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1);
/* Start the operation */
return PKA_Process(hpka, PKA_MODE_MONTGOMERY_PARAM, Timeout);
}
/**
* @brief Montgomery parameter computation in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1);
/* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_PARAM);
}
/**
* @brief ECC double base ladder in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in,
uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ECCDoubleBaseLadder_Set(hpka, in);
return PKA_Process(hpka, PKA_MODE_DOUBLE_BASE_LADDER, Timeout);
}
/**
* @brief ECC double base ladder in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder_IT(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ECCDoubleBaseLadder_Set(hpka, in);
return PKA_Process_IT(hpka, PKA_MODE_DOUBLE_BASE_LADDER);
}
/**
* @brief ECC projective to affine in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in,
uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ECCProjective2Affine_Set(hpka, in);
return PKA_Process(hpka, PKA_MODE_ECC_PROJECTIVE_AFF, Timeout);
}
/**
* @brief ECC projective to affine in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine_IT(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ECCProjective2Affine_Set(hpka, in);
return PKA_Process_IT(hpka, PKA_MODE_ECC_PROJECTIVE_AFF);
}
/**
* @brief ECC complete addition in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in,
uint32_t Timeout)
{
/* Set input parameter in PKA RAM */
PKA_ECCCompleteAddition_Set(hpka, in);
return PKA_Process(hpka, PKA_MODE_ECC_COMPLETE_ADD, Timeout);
}
/**
* @brief ECC complete addition in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition_IT(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in)
{
/* Set input parameter in PKA RAM */
PKA_ECCCompleteAddition_Set(hpka, in);
return PKA_Process_IT(hpka, PKA_MODE_ECC_COMPLETE_ADD);
}
/**
* @brief Retrieve operation result.
* @param hpka PKA handle
* @param pRes pointer to buffer where the result will be copied
* @retval HAL status
*/
void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes)
{
uint32_t size;
/* Retrieve the size of the buffer from the PKA RAM */
size = (hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] + 31UL) / 32UL;
/* Move the result to appropriate location (indicated in out parameter) */
PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_OUT_PARAMETER], size);
}
/**
* @brief Abort any ongoing operation.
* @param hpka PKA handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka)
{
HAL_StatusTypeDef err = HAL_OK;
/* Clear EN bit */
/* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */
CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN);
SET_BIT(hpka->Instance->CR, PKA_CR_EN);
/* Reset any pending flag */
SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
/* Reset the error code */
hpka->ErrorCode = HAL_PKA_ERROR_NONE;
/* Reset the state */
hpka->State = HAL_PKA_STATE_READY;
return err;
}
/**
* @brief Reset the PKA RAM.
* @param hpka PKA handle
* @retval None
*/
void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka)
{
uint32_t index;
/* For each element in the PKA RAM */
for (index = 0; index < PKA_RAM_SIZE; index++)
{
/* Clear the content */
hpka->Instance->RAM[index] = 0UL;
}
}
/**
* @brief This function handles PKA event interrupt request.
* @param hpka PKA handle
* @retval None
*/
void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
{
uint32_t mode = PKA_GetMode(hpka);
FlagStatus addErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR);
FlagStatus ramErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR);
FlagStatus procEndFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_PROCEND);
FlagStatus operErrFlag = __HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR);
/* Address error interrupt occurred */
if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_ADDRERR) == SET) && (addErrFlag == SET))
{
hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR;
/* Clear ADDRERR flag */
__HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_ADDRERR);
}
/* RAM access error interrupt occurred */
if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_RAMERR) == SET) && (ramErrFlag == SET))
{
hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR;
/* Clear RAMERR flag */
__HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_RAMERR);
}
/* OPERATION access error interrupt occurred */
if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_FLAG_OPERR) == SET) && (operErrFlag == SET))
{
hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
/* Clear OPERR flag */
__HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_OPERR);
}
/* Check the operation success in case of ECDSA signature */
switch (mode)
{
case PKA_MODE_ECDSA_SIGNATURE :
/* If error output result is different from no error, operation need to be repeated */
if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != PKA_NO_ERROR)
{
hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
}
break;
case PKA_MODE_DOUBLE_BASE_LADDER :
/* If error output result is different from no error, operation need to be repeated */
if (hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_ERROR] != PKA_NO_ERROR)
{
hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
}
break;
case PKA_MODE_ECC_PROJECTIVE_AFF :
/* If error output result is different from no error, operation need to be repeated */
if (hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_ERROR] != PKA_NO_ERROR)
{
hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
}
break;
case PKA_MODE_ECC_MUL :
/* If error output result is different from no error, operation need to be repeated */
if (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR] != PKA_NO_ERROR)
{
hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
}
break;
case PKA_MODE_MODULAR_EXP_PROTECT :
/* If error output result is different from no error, operation need to be repeated */
if (hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_ERROR] != PKA_NO_ERROR)
{
hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
}
break;
default :
break;
}
/* Trigger the error callback if an error is present */
if (hpka->ErrorCode != HAL_PKA_ERROR_NONE)
{
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
hpka->ErrorCallback(hpka);
#else
HAL_PKA_ErrorCallback(hpka);
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
}
/* End Of Operation interrupt occurred */
if ((__HAL_PKA_GET_IT_SOURCE(hpka, PKA_IT_PROCEND) == SET) && (procEndFlag == SET))
{
/* Clear PROCEND flag */
__HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND);
/* Set the state to ready */
hpka->State = HAL_PKA_STATE_READY;
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
hpka->OperationCpltCallback(hpka);
#else
HAL_PKA_OperationCpltCallback(hpka);
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
}
}
/**
* @brief Process completed callback.
* @param hpka PKA handle
* @retval None
*/
__weak void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpka);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PKA_OperationCpltCallback could be implemented in the user file
*/
}
/**
* @brief Error callback.
* @param hpka PKA handle
* @retval None
*/
__weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpka);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PKA_ErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup PKA_Exported_Functions_Group3 Peripheral State and Error functions
* @brief Peripheral State and Error functions
*
@verbatim
===============================================================================
##### Peripheral State and Error functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Return the PKA handle state.
* @param hpka PKA handle
* @retval HAL status
*/
HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka)
{
/* Return PKA handle state */
return hpka->State;
}
/**
* @brief Return the PKA error code.
* @param hpka PKA handle
* @retval PKA error code
*/
uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka)
{
/* Return PKA handle error code */
return hpka->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup PKA_Private_Functions
* @{
*/
/**
* @brief Get PKA operating mode.
* @param hpka PKA handle
* @retval Return the current mode
*/
uint32_t PKA_GetMode(PKA_HandleTypeDef *hpka)
{
/* return the shifted PKA_CR_MODE value */
return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos);
}
/**
* @brief Wait for operation completion or timeout.
* @param hpka PKA handle
* @param Timeout Timeout duration in millisecond.
* @param Tickstart Tick start value
* @retval HAL status
*/
HAL_StatusTypeDef PKA_PollEndOfOperation(PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart)
{
/* Wait for the end of operation or timeout */
while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL)
{
/* Check if timeout is disabled (set to infinite wait) */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0UL))
{
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief Return a hal error code based on PKA error flags.
* @param hpka PKA handle
* @param mode PKA operating mode
* @retval error code
*/
uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode)
{
uint32_t err = HAL_PKA_ERROR_NONE;
/* Check RAMERR error */
if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR) == SET)
{
err |= HAL_PKA_ERROR_RAMERR;
}
/* Check ADDRERR error */
if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR) == SET)
{
err |= HAL_PKA_ERROR_ADDRERR;
}
/* Check OPEERR error */
if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR) == SET)
{
err |= HAL_PKA_ERROR_OPERATION;
}
/* Check the operation success in case of ECDSA signature */
if (mode == PKA_MODE_ECDSA_SIGNATURE)
{
#define EDCSA_SIGN_NOERROR PKA_NO_ERROR
/* If error output result is different from no error, ecsa sign operation need to be repeated */
if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != EDCSA_SIGN_NOERROR)
{
err |= HAL_PKA_ERROR_OPERATION;
}
}
/* Check the operation success in case of ECC double base ladder*/
if (mode == PKA_MODE_DOUBLE_BASE_LADDER)
{
/* If error output result is different from no error, PKA operation need to be repeated */
if (hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_ERROR] != PKA_NO_ERROR)
{
err |= HAL_PKA_ERROR_OPERATION;
}
}
/* Check the operation success in case of ECC projective to affine*/
if (mode == PKA_MODE_ECC_PROJECTIVE_AFF)
{
/* If error output result is different from no error, PKA operation need to be repeated */
if (hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_ERROR] != PKA_NO_ERROR)
{
err |= HAL_PKA_ERROR_OPERATION;
}
}
/* Check the operation success in case of ECC Fp scalar multiplication*/
if (mode == PKA_MODE_ECC_MUL)
{
/* If error output result is different from no error, PKA operation need to be repeated */
if (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR] != PKA_NO_ERROR)
{
err |= HAL_PKA_ERROR_OPERATION;
}
}
/* Check the operation success in case of protected modular exponentiation*/
if (mode == PKA_MODE_MODULAR_EXP_PROTECT)
{
/* If error output result is different from no error, PKA operation need to be repeated */
if (hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_ERROR] != PKA_NO_ERROR)
{
err |= HAL_PKA_ERROR_OPERATION;
}
}
return err;
}
/**
* @brief Get number of bits inside an array of u8.
* @param byteNumber Number of u8 inside the array
*/
uint32_t PKA_GetBitSize_u8(uint32_t byteNumber)
{
/* Convert from number of uint8_t in an array to the associated number of bits in this array */
return byteNumber * 8UL;
}
/**
* @brief Get optimal number of bits inside an array of u8.
* @param byteNumber Number of u8 inside the array
* @param msb Most significant uint8_t of the array
*/
uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb)
{
uint32_t position;
position = 32UL - __CLZ(msb);
return (((byteNumber - 1UL) * 8UL) + position);
}
/**
* @brief Get number of bits inside an array of u32.
* @param wordNumber Number of u32 inside the array
*/
uint32_t PKA_GetBitSize_u32(uint32_t wordNumber)
{
/* Convert from number of uint32_t in an array to the associated number of bits in this array */
return wordNumber * 32UL;
}
/**
* @brief Get number of uint8_t element in an array of bitSize bits.
* @param bitSize Number of bits in an array
*/
uint32_t PKA_GetArraySize_u8(uint32_t bitSize)
{
/* Manage the non aligned on uint8_t bitsize: */
/* 512 bits requires 64 uint8_t */
/* 521 bits requires 66 uint8_t */
return ((bitSize + 7UL) / 8UL);
}
/**
* @brief Copy uint32_t array to uint8_t array to fit PKA number representation.
* @param dst Pointer to destination
* @param src Pointer to source
* @param n Number of uint8_t to copy
* @retval dst
*/
void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n)
{
if (dst != NULL)
{
if (src != NULL)
{
uint32_t index_uint32_t = 0UL; /* This index is used outside of the loop */
for (; index_uint32_t < (n / 4UL); index_uint32_t++)
{
/* Avoid casting from uint8_t* to uint32_t* by copying 4 uint8_t in a row */
/* Apply __REV equivalent */
uint32_t index_uint8_t = n - 4UL - (index_uint32_t * 4UL);
dst[index_uint8_t + 3UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
dst[index_uint8_t + 2UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
dst[index_uint8_t + 1UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL);
dst[index_uint8_t + 0UL] = (uint8_t)((src[index_uint32_t] & 0xFF000000U) >> 24UL);
}
/* Manage the buffers not aligned on uint32_t */
if ((n % 4UL) == 1UL)
{
dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
}
else if ((n % 4UL) == 2UL)
{
dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
}
else if ((n % 4UL) == 3UL)
{
dst[2UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU));
dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL);
dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL);
}
else
{
/* The last element is already handle in the loop */
}
}
}
}
/**
* @brief Copy uint8_t array to uint32_t array to fit PKA number representation.
* @param dst Pointer to destination
* @param src Pointer to source
* @param n Number of uint8_t to copy (must be multiple of 4)
* @retval dst
*/
void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n)
{
if (dst != NULL)
{
if (src != NULL)
{
uint32_t index = 0UL; /* This index is used outside of the loop */
for (; index < (n / 4UL); index++)
{
/* Apply the equivalent of __REV from uint8_t to uint32_t */
dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
| ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \
| ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL) \
| ((uint32_t)src[(n - (index * 4UL) - 4UL)] << 24UL);
}
/* Manage the buffers not aligned on uint32_t */
if ((n % 4UL) == 1UL)
{
dst[index] = (uint32_t)src[(n - (index * 4UL) - 1UL)];
}
else if ((n % 4UL) == 2UL)
{
dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
| ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL);
}
else if ((n % 4UL) == 3UL)
{
dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \
| ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \
| ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL);
}
else
{
/* The last element is already handle in the loop */
}
}
}
}
/**
* @brief Copy uint32_t array to uint32_t array.
* @param dst Pointer to destination
* @param src Pointer to source
* @param n Number of u32 to be handled
* @retval dst
*/
void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n)
{
/* If a destination buffer is provided */
if (dst != NULL)
{
/* If a source buffer is provided */
if (src != NULL)
{
/* For each element in the array */
for (uint32_t index = 0UL; index < n; index++)
{
/* Copy the content */
dst[index] = src[index];
}
}
}
}
/**
* @brief Generic function to start a PKA operation in blocking mode.
* @param hpka PKA handle
* @param mode PKA operation
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout)
{
HAL_StatusTypeDef err = HAL_OK;
uint32_t tickstart;
if (hpka->State == HAL_PKA_STATE_READY)
{
/* Set the state to busy */
hpka->State = HAL_PKA_STATE_BUSY;
/* Clear any pending error */
hpka->ErrorCode = HAL_PKA_ERROR_NONE;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Set the mode and deactivate the interrupts */
MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE,
mode << PKA_CR_MODE_Pos);
/* Start the computation */
hpka->Instance->CR |= PKA_CR_START;
/* Wait for the end of operation or timeout */
if (PKA_PollEndOfOperation(hpka, Timeout, tickstart) != HAL_OK)
{
/* Abort any ongoing operation */
CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN);
hpka->ErrorCode |= HAL_PKA_ERROR_TIMEOUT;
/* Make ready for the next operation */
SET_BIT(hpka->Instance->CR, PKA_CR_EN);
}
/* Check error */
hpka->ErrorCode |= PKA_CheckError(hpka, mode);
/* Clear all flags */
hpka->Instance->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC);
/* Set the state to ready */
hpka->State = HAL_PKA_STATE_READY;
/* Manage the result based on encountered errors */
if (hpka->ErrorCode != HAL_PKA_ERROR_NONE)
{
err = HAL_ERROR;
}
}
else
{
err = HAL_ERROR;
}
return err;
}
/**
* @brief Generic function to start a PKA operation in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param mode PKA operation
* @retval HAL status
*/
HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode)
{
HAL_StatusTypeDef err = HAL_OK;
if (hpka->State == HAL_PKA_STATE_READY)
{
/* Set the state to busy */
hpka->State = HAL_PKA_STATE_BUSY;
/* Clear any pending error */
hpka->ErrorCode = HAL_PKA_ERROR_NONE;
/* Set the mode and activate interrupts */
MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE,
(mode << PKA_CR_MODE_Pos) | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE);
/* Start the computation */
hpka->Instance->CR |= PKA_CR_START;
}
else
{
err = HAL_ERROR;
}
return err;
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
{
/* Get the number of bit per operand */
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
/* Get the number of bit of the exponent */
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
/* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL));
/* Move the exponent to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL));
/* Move the modulus to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL));
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in)
{
/* Get the number of bit per operand */
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
/* Get the number of bit of the exponent */
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
/* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL));
/* Move the exponent to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL));
/* Move the modulus to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL));
/* Move the Montgomery parameter to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam,
in->OpSize / 4UL);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->OpSize / 4UL));
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in)
{
/* Get the number of bit per operand */
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize);
/* Get the number of bit of the exponent */
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize);
/* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + (in->OpSize / 4UL));
/* Move the exponent to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT], in->pExp, in->expSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + (in->expSize / 4UL));
/* Move the modulus to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_MODULUS], in->pMod, in->OpSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + (in->OpSize / 4UL));
/* Move Phi value to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI], in->pPhi, in->OpSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + (in->OpSize / 4UL));
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
{
/* Get the prime order n length */
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder));
/* Get the modulus p length */
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
/* Get the coefficient a sign */
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = in->coefSign;
/* Move the input parameters coefficient |a| to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], in->coef, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters coefficient B to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_B_COEFF], in->coefB, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], in->modulus, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters integer k to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_K], in->integer, in->primeOrderSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_K + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters base point G coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters base point G coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters hash of message z to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_HASH_E], in->hash, in->primeOrderSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters private key d to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], in->privateKey, in->primeOrderSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters prime order n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], in->primeOrder, in->primeOrderSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL));
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
{
/* Get the prime order n length */
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder));
/* Get the modulus p length */
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
/* Get the coefficient a sign */
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF_SIGN] = in->coefSign;
/* Move the input parameters coefficient |a| to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], in->coef, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], in->modulus, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters base point G coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters base point G coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX,
in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY,
in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters signature part r to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], in->RSign, in->primeOrderSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters signature part s to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], in->SSign, in->primeOrderSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters hash of message z to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_HASH_E], in->hash, in->primeOrderSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters curve prime order n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], in->primeOrder, in->primeOrderSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL));
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
{
/* Get the operand length M */
hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->size);
/* Move the input parameters operand dP to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DP_CRT], in->pOpDp, in->size / 2UL);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DP_CRT + (in->size / 8UL));
/* Move the input parameters operand dQ to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DQ_CRT], in->pOpDq, in->size / 2UL);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DQ_CRT + (in->size / 8UL));
/* Move the input parameters operand qinv to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_QINV_CRT], in->pOpQinv, in->size / 2UL);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_QINV_CRT + (in->size / 8UL));
/* Move the input parameters prime p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_P], in->pPrimeP, in->size / 2UL);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_P + (in->size / 8UL));
/* Move the input parameters prime q to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_Q], in->pPrimeQ, in->size / 2UL);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_Q + (in->size / 8UL));
/* Move the input parameters operand A to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_EXPONENT_BASE], in->popA, in->size);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_EXPONENT_BASE + (in->size / 4UL));
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
{
/* Get the modulus length */
hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
/* Get the coefficient a sign */
hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF_SIGN] = in->coefSign;
/* Move the input parameters coefficient |a| to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF], in->coefA, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters coefficient b to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_B_COEFF], in->coefB, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_GF], in->modulus, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters montgomery param R2 modulus N to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MONTGOMERY_PARAM], in->pMontgomeryParam,
(in->modulusSize / 4UL));
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MONTGOMERY_PARAM + ((in->modulusSize + 3UL) / 4UL));
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
{
/* Get the prime order n length */
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->scalarMulSize, *(in->primeOrder));
/* Get the modulus length */
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus));
/* Get the coefficient a sign */
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign;
/* Move the input parameters coefficient |a| to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters coefficient b to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + (in->modulusSize / 4UL));
/* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters scalar multiplier k to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters curve prime order N to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + (in->modulusSize / 4UL));
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
{
/* Get the number of bit per operand */
hpka->Instance->RAM[PKA_MODULAR_INV_NB_BITS] = PKA_GetBitSize_u32(in->size);
/* Move the input parameters operand A to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP1], in->pOp1, in->size);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP1 + in->size);
/* Move the input parameters modulus value n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP2_MOD], in->pMod, in->size * 4UL);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP2_MOD + in->size);
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
{
/* Get the number of bit per operand */
hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OP_LENGTH] = PKA_GetBitSize_u32(in->OpSize);
/* Get the number of bit per modulus */
hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MOD_LENGTH] = PKA_GetBitSize_u8(in->modSize);
/* Move the input parameters operand A to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OPERAND], in->pOp1, in->OpSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_OPERAND + in->OpSize);
/* Move the input parameters modulus value n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL));
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param size Size of the operand
* @param pOp1 Generic pointer to input data
*/
void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1)
{
uint32_t bytetoskip = 0UL;
uint32_t newSize;
if (pOp1 != NULL)
{
/* Count the number of zero bytes */
while ((bytetoskip < size) && (pOp1[bytetoskip] == 0UL))
{
bytetoskip++;
}
/* Get new size after skipping zero bytes */
newSize = size - bytetoskip;
/* Get the number of bit per operand */
hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(newSize, pOp1[bytetoskip]);
/* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS], pOp1, size);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MONTGOMERY_PARAM_IN_MODULUS + ((size + 3UL) / 4UL));
}
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ECCDoubleBaseLadder_Set(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in)
{
/* Get the prime order n length */
hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS] = PKA_GetBitSize_u8(in->primeOrderSize);
/* Get the modulus p length */
hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize);
/* Get the coefficient a sign */
hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN] = in->coefSign;
/* Move the input parameters coefficient |a| to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF], in->coefA, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_A_COEFF + (in->modulusSize / 4UL));
/* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_P], in->modulus, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_MOD_P + (in->modulusSize / 4UL));
/* Move the input parameters integer k to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER], in->integerK, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER + (in->modulusSize / 4UL));
/* Move the input parameters integer m to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER], in->integerM, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER + (in->modulusSize / 4UL));
/* Move the input parameters first point coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_X], in->basePointX1, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_X + (in->modulusSize / 4UL));
/* Move the input parameters first point coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y], in->basePointY1, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y + (in->modulusSize / 4UL));
/* Move the input parameters first point coordinate z to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z], in->basePointZ1, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z + (in->modulusSize / 4UL));
/* Move the input parameters second point coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_X], in->basePointX2, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_X + (in->modulusSize / 4UL));
/* Move the input parameters second point coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y], in->basePointY2, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y + (in->modulusSize / 4UL));
/* Move the input parameters second point coordinate z to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z], in->basePointZ2, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z + (in->modulusSize / 4UL));
}
/**
* @brief Retrieve operation result.
* @param hpka PKA handle
* @param out Output information
* @retval HAL status
*/
void HAL_PKA_ECCDoubleBaseLadder_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderOutTypeDef *out)
{
uint32_t size;
/* Move the result to appropriate location (indicated in out parameter) */
size = hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS] / 8UL;
if (out != NULL)
{
PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X], size);
PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y], size);
}
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in)
{
/* Get the modulus p length */
hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize);
/* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_P], in->modulus, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_MOD_P + (in->modulusSize / 4UL));
/* Move the input parameters point coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_X], in->basePointX, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_X + (in->modulusSize / 4UL));
/* Move the input parameters point coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y], in->basePointY, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y + (in->modulusSize / 4UL));
/* Move the input parameters point coordinate z to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z], in->basePointZ, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z + (in->modulusSize / 4UL));
/* Move the input parameters montgomery parameter R2 modulus n to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2], in->pMontgomeryParam,
(in->modulusSize / 4UL));
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 + (in->modulusSize / 4UL));
}
/**
* @brief Retrieve operation result.
* @param hpka PKA handle
* @param out Output information
* @retval HAL status
*/
void HAL_PKA_ECCProjective2Affine_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineOutTypeDef *out)
{
uint32_t size;
/* Move the result to appropriate location (indicated in out parameter) */
size = hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS] / 8UL;
if (out != NULL)
{
PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X], size);
PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y], size);
}
}
/**
* @brief Set input parameters.
* @param hpka PKA handle
* @param in Input information
*/
void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in)
{
/* Get the modulus p length */
hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize);
/* Get the coefficient a sign */
hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN] = in->coefSign;
/* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_P], in->modulus, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_MOD_P + (in->modulusSize / 4UL));
/* Move the input parameters coefA value to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_A_COEFF], in->coefA, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_A_COEFF + (in->modulusSize / 4UL));
/* Move the input parameters first point x value to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_X], in->basePointX1, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_X + (in->modulusSize / 4UL));
/* Move the input parameters first point y value to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_Y], in->basePointY1, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_Y + (in->modulusSize / 4UL));
/* Move the input parameters first point z value to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_Z], in->basePointZ1, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_Z + (in->modulusSize / 4UL));
/* Move the input parameters second point x value to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_X], in->basePointX2, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_X + (in->modulusSize / 4UL));
/* Move the input parameters second point y value to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_Y], in->basePointY2, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_Y + (in->modulusSize / 4UL));
/* Move the input parameters second point z value to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_Z], in->basePointZ2, in->modulusSize);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_Z + (in->modulusSize / 4UL));
}
/**
* @brief Retrieve operation result.
* @param hpka PKA handle
* @param out Output information
* @retval HAL status
*/
void HAL_PKA_ECCCompleteAddition_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionOutTypeDef *out)
{
uint32_t size;
/* Move the result to appropriate location (indicated in out parameter) */
size = (hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS] + 7UL) / 8UL;
if (out != NULL)
{
PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_X], size);
PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y], size);
PKA_Memcpy_u32_to_u8(out->ptZ, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z], size);
}
}
/**
* @brief Generic function to set input parameters.
* @param hpka PKA handle
* @param size Size of the operand
* @param pOp1 Generic pointer to input data
* @param pOp2 Generic pointer to input data
* @param pOp3 Generic pointer to input data
*/
void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2,
const uint8_t *pOp3)
{
/* Get the number of bit per operand */
hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] = PKA_GetBitSize_u32(size);
if (pOp1 != NULL)
{
/* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP1], pOp1, size);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP1 + size);
}
if (pOp2 != NULL)
{
/* Move the input parameters pOp2 to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP2], pOp2, size);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP2 + size);
}
if (pOp3 != NULL)
{
/* Move the input parameters pOp3 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP3], pOp3, size * 4UL);
__PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP3 + size);
}
}
/**
* @brief Handle PKA init Timeout.
* @param hpka PKA handle.
* @param Flag Specifies the PKA flag to check
* @param Status Flag status (SET or RESET)
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
while (__HAL_PKA_GET_FLAG(hpka, Flag) == Status)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
/* Set the state to ready */
hpka->State = HAL_PKA_STATE_READY;
/* Set the error code to timeout error */
hpka->ErrorCode = HAL_PKA_ERROR_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
/**
* @brief Get the size of output result.
* @param hpka PKA handle
* @param Startindex Specifies the start index of the result in the PKA RAM
* @param Maxsize Specifies the possible max size of the result in words
* @retval size
*/
uint32_t PKA_Result_GetSize(PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize)
{
uint32_t size;
uint32_t current_index = Maxsize - 1UL;
/* Determinate the last index of the result in the PKA RAM */
while ((hpka->Instance->RAM[Startindex + current_index] == 0UL) && (current_index != 0UL))
{
current_index--;
}
/* Get the size in bytes */
size = (current_index + 1UL) * 4UL;
return size;
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c
|
C
|
apache-2.0
| 104,137
|
/**
******************************************************************************
* @file stm32u5xx_hal_pssi.c
* @author MCD Application Team
* @brief PSSI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Parallel Synchronous Slave Interface (PSSI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The PSSI HAL driver can be used as follows:
(#) Declare a PSSI_HandleTypeDef handle structure, for example:
PSSI_HandleTypeDef hpssi;
(#) Initialize the PSSI low level resources by implementing the @ref HAL_PSSI_MspInit() API:
(##) Enable the PSSIx interface clock
(##) PSSI pins configuration
(+++) Enable the clock for the PSSI GPIOs
(+++) Configure PSSI pins as alternate function open-drain
(##) NVIC configuration if you need to use interrupt process
(+++) Configure the PSSIx interrupt priority
(+++) Enable the NVIC PSSI IRQ Channel
(##) DMA Configuration if you need to use DMA process
(+++) Declare DMA_HandleTypeDef handles structure for the transmit and receive
(+++) Enable the DMAx interface clock
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx and Rx
(+++) Associate the initialized DMA handle to the hpssi DMA Tx and Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
the DMA Tx and Rx
(#) Configure the Communication Bus Width, Control Signals, Input Polarity and Output Polarity
in the hpssi Init structure.
(#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware
(GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API.
(#) For PSSI IO operations, two operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
(+) Transmit an amount of data by byte in blocking mode using @ref HAL_PSSI_Transmit()
(+) Receive an amount of data by byte in blocking mode using @ref HAL_PSSI_Receive()
*** DMA mode IO operation ***
==============================
[..]
(+) Transmit an amount of data in non-blocking mode (DMA) using
@ref HAL_PSSI_Transmit_DMA()
(+) At transmission end of transfer, @ref HAL_PSSI_TxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_PSSI_TxCpltCallback()
(+) Receive an amount of data in non-blocking mode (DMA) using
@ref HAL_PSSI_Receive_DMA()
(+) At reception end of transfer, @ref HAL_PSSI_RxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_PSSI_RxCpltCallback()
(+) In case of transfer Error, @ref HAL_PSSI_ErrorCallback() function is executed and user can
add his own code by customization of function pointer @ref HAL_PSSI_ErrorCallback()
(+) Abort a PSSI process communication with Interrupt using @ref HAL_PSSI_Abort_IT()
(+) End of abort process, @ref HAL_PSSI_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_PSSI_AbortCpltCallback()
*** PSSI HAL driver macros list ***
==================================
[..]
Below the list of most used macros in PSSI HAL driver.
(+) @ref HAL_PSSI_ENABLE : Enable the PSSI peripheral
(+) @ref HAL_PSSI_DISABLE : Disable the PSSI peripheral
(+) @ref HAL_PSSI_GET_FLAG : Check whether the specified PSSI flag is set or not
(+) @ref HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag
(+) @ref HAL_PSSI_ENABLE_IT : Enable the specified PSSI interrupt
(+) @ref HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt
*** Callback registration ***
=============================================
Use Functions @ref HAL_PSSI_RegisterCallback() or @ref HAL_PSSI_RegisterAddrCallback()
to register an interrupt callback.
Function @ref HAL_PSSI_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : callback for transmission end of transfer.
(+) RxCpltCallback : callback for reception end of transfer.
(+) ErrorCallback : callback for error detection.
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_PSSI_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : callback for transmission end of transfer.
(+) RxCpltCallback : callback for reception end of transfer.
(+) ErrorCallback : callback for error detection.
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
By default, after the @ref HAL_PSSI_Init() and when the state is @ref HAL_PSSI_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_PSSI_TxCpltCallback(), @ref HAL_PSSI_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() only when
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
Callbacks can be registered/unregistered in @ref HAL_PSSI_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_PSSI_STATE_READY or @ref HAL_PSSI_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_PSSI_RegisterCallback() before calling @ref HAL_PSSI_DeInit()
or @ref HAL_PSSI_Init() function.
[..]
(@) You can refer to the PSSI HAL driver header file for more useful macros
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup PSSI PSSI
* @brief PSSI HAL module driver
* @{
*/
#ifdef HAL_PSSI_MODULE_ENABLED
#if defined(PSSI)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PSSI_Private_Define PSSI Private Define
* @{
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup PSSI_Private_Functions PSSI Private Functions
* @{
*/
/* Private functions to handle DMA transfer */
void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
void PSSI_DMAError(DMA_HandleTypeDef *hdma);
void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
/* Private functions to handle IT transfer */
static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
/* Private functions for PSSI transfer IRQ handler */
/* Private functions to handle flags during polling transfer */
static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PSSI_Exported_Functions PSSI Exported Functions
* @{
*/
/** @defgroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
deinitialize the PSSIx peripheral:
(+) User must implement HAL_PSSI_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
(+) Call the function HAL_PSSI_Init() to configure the selected device with
the selected configuration:
(++) Data Width
(++) Control Signals
(++) Input Clock polarity
(++) Output Clock polarity
(+) Call the function HAL_PSSI_DeInit() to restore the default configuration
of the selected PSSIx peripheral.
@endverbatim
* @{
*/
/**
* @brief Initializes the PSSI according to the specified parameters
* in the PSSI_InitTypeDef and initialize the associated handle.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi)
{
/* Check the PSSI handle allocation */
if (hpssi == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance));
assert_param(IS_PSSI_CONTROL_SIGNAL(hpssi->Init.ControlSignal));
assert_param(IS_PSSI_BUSWIDTH(hpssi->Init.BusWidth));
assert_param(IS_PSSI_CLOCK_POLARITY(hpssi->Init.ClockPolarity));
assert_param(IS_PSSI_DE_POLARITY(hpssi->Init.DataEnablePolarity));
assert_param(IS_PSSI_RDY_POLARITY(hpssi->Init.ReadyPolarity));
if (hpssi->State == HAL_PSSI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hpssi->Lock = HAL_UNLOCKED;
/* Init the PSSI Callback settings */
hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
hpssi->ErrorCallback = HAL_PSSI_ErrorCallback; /* Legacy weak ErrorCallback */
hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
if (hpssi->MspInitCallback == NULL)
{
hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hpssi->MspInitCallback(hpssi);
}
hpssi->State = HAL_PSSI_STATE_BUSY;
/* Disable the selected PSSI peripheral */
HAL_PSSI_DISABLE(hpssi);
/*---------------------------- PSSIx CR Configuration ----------------------*/
/* Configure PSSIx: Control Signal and Bus Width*/
MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DERDYCFG | PSSI_CR_EDM | PSSI_CR_DEPOL | PSSI_CR_RDYPOL,
hpssi->Init.ControlSignal | hpssi->Init.DataEnablePolarity |
hpssi->Init.ReadyPolarity | hpssi->Init.BusWidth);
hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
hpssi->State = HAL_PSSI_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitialize the PSSI peripheral.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi)
{
/* Check the PSSI handle allocation */
if (hpssi == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_PSSI_ALL_INSTANCE(hpssi->Instance));
hpssi->State = HAL_PSSI_STATE_BUSY;
/* Disable the PSSI Peripheral Clock */
HAL_PSSI_DISABLE(hpssi);
if (hpssi->MspDeInitCallback == NULL)
{
hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
hpssi->MspDeInitCallback(hpssi);
hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
hpssi->State = HAL_PSSI_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hpssi);
return HAL_OK;
}
/**
* @brief Initialize the PSSI MSP.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval None
*/
__weak void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpssi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PSSI_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the PSSI MSP.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval None
*/
__weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpssi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PSSI_MspDeInit can be implemented in the user file
*/
}
/**
* @brief Register a User PSSI Callback
* To be used instead of the weak predefined callback
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_PSSI_TX_COMPLETE_CB_ID Tx Transfer completed callback ID
* @arg @ref HAL_PSSI_RX_COMPLETE_CB_ID Rx Transfer completed callback ID
* @arg @ref HAL_PSSI_ERROR_CB_ID Error callback ID
* @arg @ref HAL_PSSI_ABORT_CB_ID Abort callback ID
* @arg @ref HAL_PSSI_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID,
pPSSI_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hpssi);
if (HAL_PSSI_STATE_READY == hpssi->State)
{
switch (CallbackID)
{
case HAL_PSSI_TX_COMPLETE_CB_ID :
hpssi->TxCpltCallback = pCallback;
break;
case HAL_PSSI_RX_COMPLETE_CB_ID :
hpssi->RxCpltCallback = pCallback;
break;
case HAL_PSSI_ERROR_CB_ID :
hpssi->ErrorCallback = pCallback;
break;
case HAL_PSSI_ABORT_CB_ID :
hpssi->AbortCpltCallback = pCallback;
break;
case HAL_PSSI_MSPINIT_CB_ID :
hpssi->MspInitCallback = pCallback;
break;
case HAL_PSSI_MSPDEINIT_CB_ID :
hpssi->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_PSSI_STATE_RESET == hpssi->State)
{
switch (CallbackID)
{
case HAL_PSSI_MSPINIT_CB_ID :
hpssi->MspInitCallback = pCallback;
break;
case HAL_PSSI_MSPDEINIT_CB_ID :
hpssi->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpssi);
return status;
}
/**
* @brief Unregister an PSSI Callback
* PSSI callback is redirected to the weak predefined callback
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_PSSI_TX_COMPLETE_CB_ID Tx Transfer completed callback ID
* @arg @ref HAL_PSSI_RX_COMPLETE_CB_ID Rx Transfer completed callback ID
* @arg @ref HAL_PSSI_ERROR_CB_ID Error callback ID
* @arg @ref HAL_PSSI_ABORT_CB_ID Abort callback ID
* @arg @ref HAL_PSSI_MSPINIT_CB_ID MspInit callback ID
* @arg @ref HAL_PSSI_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hpssi);
if (HAL_PSSI_STATE_READY == hpssi->State)
{
switch (CallbackID)
{
case HAL_PSSI_TX_COMPLETE_CB_ID :
hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_PSSI_RX_COMPLETE_CB_ID :
hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_PSSI_ERROR_CB_ID :
hpssi->ErrorCallback = HAL_PSSI_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_PSSI_ABORT_CB_ID :
hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_PSSI_MSPINIT_CB_ID :
hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */
break;
case HAL_PSSI_MSPDEINIT_CB_ID :
hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (HAL_PSSI_STATE_RESET == hpssi->State)
{
switch (CallbackID)
{
case HAL_PSSI_MSPINIT_CB_ID :
hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */
break;
case HAL_PSSI_MSPDEINIT_CB_ID :
hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
/* Update the error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hpssi);
return status;
}
/**
* @}
*/
/** @defgroup PSSI_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the PSSI data
transfers.
(#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode : The communication is performed using DMA.
These functions return the status of the transfer startup.
The end of the data processing will be indicated through the
dedicated the DMA IRQ .
(#) Blocking mode functions are :
(++) HAL_PSSI_Transmit()
(++) HAL_PSSI_Receive()
(#) No-Blocking mode functions with DMA are :
(++) HAL_PSSI_Transmit_DMA()
(++) HAL_PSSI_Receive_DMA()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_PSSI_TxCpltCallback()
(++) HAL_PSSI_RxCpltCallback()
(++) HAL_PSSI_ErrorCallback()
(++) HAL_PSSI_AbortCpltCallback()
@endverbatim
* @{
*/
/**
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent (in bytes)
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t transfer_size = Size;
if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) ||
((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U)))
{
hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
if (hpssi->State == HAL_PSSI_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hpssi);
hpssi->State = HAL_PSSI_STATE_BUSY;
hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
/* Disable the selected PSSI peripheral */
HAL_PSSI_DISABLE(hpssi);
/* Configure transfer parameters */
hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT |
((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL);
/* DMA Disable */
hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
/* Enable the selected PSSI peripheral */
HAL_PSSI_ENABLE(hpssi);
if (hpssi->Init.DataWidth == HAL_PSSI_8BITS)
{
uint8_t *pbuffer = pData;
while (transfer_size > 0U)
{
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Wait until Fifo is ready to transfer one byte flag is set */
if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK)
{
hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
/* Write data to DR */
*(__IO uint8_t *)(&hpssi->Instance->DR) = *(uint8_t *)pbuffer;
/* Increment Buffer pointer */
pbuffer++;
transfer_size--;
}
}
else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
{
uint16_t *pbuffer = (uint16_t *)pData;
__IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR);
while (transfer_size > 0U)
{
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Wait until Fifo is ready to transfer four bytes flag is set */
if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
{
hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
/* Write data to DR */
*dr = *pbuffer;
/* Increment Buffer pointer */
pbuffer++;
transfer_size -= 2U;
}
}
else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
{
uint32_t *pbuffer = (uint32_t *)pData;
while (transfer_size > 0U)
{
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Wait until Fifo is ready to transfer four bytes flag is set */
if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
{
hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
/* Write data to DR */
*(__IO uint32_t *)(&hpssi->Instance->DR) = *pbuffer;
/* Increment Buffer pointer */
pbuffer++;
transfer_size -= 4U;
}
}
else
{
hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
/* Check Errors Flags */
if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U)
{
HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS);
HAL_PSSI_DISABLE(hpssi);
hpssi->ErrorCode = HAL_PSSI_ERROR_UNDER_RUN;
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receives an amount of data in blocking mode.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received (in bytes)
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t transfer_size = Size;
if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) ||
((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U)))
{
hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
if (hpssi->State == HAL_PSSI_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hpssi);
hpssi->State = HAL_PSSI_STATE_BUSY;
hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
/* Disable the selected PSSI peripheral */
HAL_PSSI_DISABLE(hpssi);
/* Configure transfer parameters */
hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT |
((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL);
/* DMA Disable */
hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
/* Enable the selected PSSI peripheral */
HAL_PSSI_ENABLE(hpssi);
if (hpssi->Init.DataWidth == HAL_PSSI_8BITS)
{
uint8_t *pbuffer = pData;
while (transfer_size > 0U)
{
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Wait until Fifo is ready to receive one byte flag is set */
if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT1B, RESET, Timeout, tickstart) != HAL_OK)
{
hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
/* Read data from DR */
*pbuffer = *(__IO uint8_t *)(&hpssi->Instance->DR);
pbuffer++;
transfer_size--;
}
}
else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
{
uint16_t *pbuffer = (uint16_t *)pData;
__IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR);
while (transfer_size > 0U)
{
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Wait until Fifo is ready to receive four bytes flag is set */
if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
{
hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
/* Read data from DR */
*pbuffer = *dr;
pbuffer++;
transfer_size -= 2U;
}
}
else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
{
uint32_t *pbuffer = (uint32_t *)pData;
while (transfer_size > 0U)
{
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* Wait until Fifo is ready to receive four bytes flag is set */
if (PSSI_WaitOnStatusUntilTimeout(hpssi, PSSI_FLAG_RTT4B, RESET, Timeout, tickstart) != HAL_OK)
{
hpssi->ErrorCode = HAL_PSSI_ERROR_TIMEOUT;
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
/* Read data from DR */
*pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR);
pbuffer++;
transfer_size -= 4U;
}
}
else
{
hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
/* Check Errors Flags */
if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_RIS) != 0U)
{
HAL_PSSI_CLEAR_FLAG(hpssi, PSSI_FLAG_OVR_RIS);
hpssi->ErrorCode = HAL_PSSI_ERROR_OVER_RUN;
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Transmit an amount of data in non-blocking mode with DMA
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent (in bytes)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
{
HAL_StatusTypeDef dmaxferstatus;
if (hpssi->State == HAL_PSSI_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hpssi);
hpssi->State = HAL_PSSI_STATE_BUSY_TX;
hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
/* Disable the selected PSSI peripheral */
HAL_PSSI_DISABLE(hpssi);
/* Prepare transfer parameters */
hpssi->pBuffPtr = pData;
hpssi->XferCount = Size;
if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE)
{
hpssi->XferSize = PSSI_MAX_NBYTE_SIZE;
}
else
{
hpssi->XferSize = hpssi->XferCount;
}
if (hpssi->XferSize > 0U)
{
if (hpssi->hdmatx != NULL)
{
/* Configure BusWidth */
if (hpssi->hdmatx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE)
{
MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT |
((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
}
else
{
MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT |
((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
}
/* Set the PSSI DMA transfer complete callback */
hpssi->hdmatx->XferCpltCallback = PSSI_DMATransmitCplt;
/* Set the DMA error callback */
hpssi->hdmatx->XferErrorCallback = PSSI_DMAError;
/* Set the unused DMA callbacks to NULL */
hpssi->hdmatx->XferHalfCpltCallback = NULL;
hpssi->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA */
if ((hpssi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hpssi->hdmatx->LinkedListQueue != NULL)
{
/* Enable the DMA channel */
/* Set DMA data size */
hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hpssi->XferSize;
/* Set DMA source address */
hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
/* Set DMA destination address */
hpssi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] =
(uint32_t)&hpssi->Instance->DR;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hpssi->hdmatx);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmatx, (uint32_t)pData, (uint32_t)&hpssi->Instance->DR,
hpssi->XferSize);
}
}
else
{
/* Update PSSI state */
hpssi->State = HAL_PSSI_STATE_READY;
/* Update PSSI error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Update XferCount value */
hpssi->XferCount -= hpssi->XferSize;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Note : The PSSI interrupts must be enabled after unlocking current process
to avoid the risk of PSSI interrupt handle execution before current
process unlock */
/* Enable ERR interrupt */
HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
/* Enable DMA Request */
hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE;
/* Enable the selected PSSI peripheral */
HAL_PSSI_ENABLE(hpssi);
}
else
{
/* Update PSSI state */
hpssi->State = HAL_PSSI_STATE_READY;
/* Update PSSI error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Note : The PSSI interrupts must be enabled after unlocking current process
to avoid the risk of PSSI interrupt handle execution before current
process unlock */
/* Enable ERRinterrupt */
/* possible to enable all of these */
HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in non-blocking mode with DMA
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @param pData Pointer to data buffer
* @param Size Amount of data to be received (in bytes)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size)
{
HAL_StatusTypeDef dmaxferstatus;
if (hpssi->State == HAL_PSSI_STATE_READY)
{
/* Disable the selected PSSI peripheral */
HAL_PSSI_DISABLE(hpssi);
/* Process Locked */
__HAL_LOCK(hpssi);
hpssi->State = HAL_PSSI_STATE_BUSY_RX;
hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
/* Prepare transfer parameters */
hpssi->pBuffPtr = pData;
hpssi->XferCount = Size;
if (hpssi->XferCount > PSSI_MAX_NBYTE_SIZE)
{
hpssi->XferSize = PSSI_MAX_NBYTE_SIZE;
}
else
{
hpssi->XferSize = hpssi->XferCount;
}
if (hpssi->XferSize > 0U)
{
if (hpssi->hdmarx != NULL)
{
/* Configure BusWidth */
if (hpssi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)
{
MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE |
((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
}
else
{
MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth |
((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
}
/* Set the PSSI DMA transfer complete callback */
hpssi->hdmarx->XferCpltCallback = PSSI_DMAReceiveCplt;
/* Set the DMA error callback */
hpssi->hdmarx->XferErrorCallback = PSSI_DMAError;
/* Set the unused DMA callbacks to NULL */
hpssi->hdmarx->XferHalfCpltCallback = NULL;
hpssi->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA */
if ((hpssi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
{
if (hpssi->hdmarx->LinkedListQueue != NULL)
{
/* Enable the DMA channel */
/* Set DMA data size */
hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hpssi->XferSize;
/* Set DMA source address */
hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] =
(uint32_t)&hpssi->Instance->DR;
/* Set DMA destination address */
hpssi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
dmaxferstatus = HAL_DMAEx_List_Start_IT(hpssi->hdmarx);
}
else
{
/* Return error status */
return HAL_ERROR;
}
}
else
{
dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmarx, (uint32_t)&hpssi->Instance->DR, (uint32_t)pData,
hpssi->XferSize);
}
}
else
{
/* Update PSSI state */
hpssi->State = HAL_PSSI_STATE_READY;
/* Update PSSI error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
if (dmaxferstatus == HAL_OK)
{
/* Update XferCount value */
hpssi->XferCount -= hpssi->XferSize;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Note : The PSSI interrupts must be enabled after unlocking current process
to avoid the risk of PSSI interrupt handle execution before current
process unlock */
/* Enable ERR interrupt */
HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
/* Enable DMA Request */
hpssi->Instance->CR |= PSSI_CR_DMA_ENABLE;
/* Enable the selected PSSI peripheral */
HAL_PSSI_ENABLE(hpssi);
}
else
{
/* Update PSSI state */
hpssi->State = HAL_PSSI_STATE_READY;
/* Update PSSI error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_DMA;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Enable ERR,interrupt */
HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Abort a DMA process communication with Interrupt.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
{
/* Process Locked */
__HAL_LOCK(hpssi);
/* Disable Interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
/* Set State at HAL_PSSI_STATE_ABORT */
hpssi->State = HAL_PSSI_STATE_ABORT;
/* Abort DMA TX transfer if any */
if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
{
if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
{
hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
if (hpssi->hdmatx != NULL)
{
/* Set the PSSI DMA Abort callback :
will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
}
}
}
/* Abort DMA RX transfer if any */
else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
{
hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
if (hpssi->hdmarx != NULL)
{
/* Set the PSSI DMA Abort callback :
will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
{
/* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
}
}
}
else
{
/* Call the error callback */
hpssi->ErrorCallback(hpssi);
}
}
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Note : The PSSI interrupts must be enabled after unlocking current process
to avoid the risk of PSSI interrupt handle execution before current
process unlock */
HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/**
* @brief This function handles PSSI event interrupt request.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval None
*/
void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
{
/* Overrun/ Underrun Errors */
if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U)
{
/* Reset handle parameters */
hpssi->XferCount = 0U;
/* Disable all interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
/* Abort DMA TX transfer if any */
if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
{
if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
{
/* Set new error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_UNDER_RUN;
hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
if (hpssi->hdmatx != NULL)
{
/* Set the PSSI DMA Abort callback :
will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
}
}
}
/* Abort DMA RX transfer if any */
else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
{
/* Set new error code */
hpssi->ErrorCode |= HAL_PSSI_ERROR_OVER_RUN;
hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
if (hpssi->hdmarx != NULL)
{
/* Set the PSSI DMA Abort callback :
will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
{
/* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
}
}
}
else
{
/* Call the corresponding callback to inform upper layer of the error */
hpssi->ErrorCallback(hpssi);
}
}
/* If state is an abort treatment on going, don't change state */
if (hpssi->State == HAL_PSSI_STATE_ABORT)
{
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->AbortCpltCallback(hpssi);
}
else
{
/* Set HAL_PSSI_STATE_READY */
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->ErrorCallback(hpssi);
}
}
}
/**
* @brief Tx Transfer complete callback.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval None
*/
__weak void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpssi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PSSI_TxCpltCallback can be implemented in the user file
*/
}
/**
* @brief Rx Transfer complete callback.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval None
*/
__weak void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpssi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PSSI_RxCpltCallback can be implemented in the user file
*/
}
/**
* @brief PSSI error callback.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval None
*/
__weak void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpssi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PSSI_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief PSSI abort callback.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval None
*/
__weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpssi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PSSI_AbortCpltCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions
* @brief Peripheral State, Mode and Error functions
*
@verbatim
===============================================================================
##### Peripheral State, Mode and Error functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the PSSI handle state.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval HAL state
*/
HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi)
{
/* Return PSSI handle state */
return hpssi->State;
}
/**
* @brief Return the PSSI error code.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval PSSI Error Code
*/
uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi)
{
return hpssi->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup PSSI_Private_Functions
* @{
*/
/**
* @brief PSSI Errors process.
* @param hpssi PSSI handle.
* @param ErrorCode Error code to handle.
* @retval None
*/
static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
{
/* Reset handle parameters */
hpssi->XferCount = 0U;
/* Set new error code */
hpssi->ErrorCode |= ErrorCode;
/* Disable all interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
/* Abort DMA TX transfer if any */
if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
{
if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
{
hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
if (hpssi->hdmatx != NULL)
{
/* Set the PSSI DMA Abort callback :
will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
hpssi->hdmatx->XferAbortCallback = PSSI_DMAAbort;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hpssi->hdmatx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
}
}
}
/* Abort DMA RX transfer if any */
else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
{
hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
if (hpssi->hdmarx != NULL)
{
/* Set the PSSI DMA Abort callback :
will lead to call HAL_PSSI_ErrorCallback() at end of DMA abort procedure */
hpssi->hdmarx->XferAbortCallback = PSSI_DMAAbort;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hpssi->hdmarx) != HAL_OK)
{
/* Call Directly hpssi->hdma->XferAbortCallback function in case of error */
hpssi->hdmarx->XferAbortCallback(hpssi->hdmarx);
}
}
}
else
{
/*Nothing to do*/
}
}
/* If state is an abort treatment on going, don't change state */
if (hpssi->State == HAL_PSSI_STATE_ABORT)
{
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->AbortCpltCallback(hpssi);
}
else
{
/* Set HAL_PSSI_STATE_READY */
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->ErrorCallback(hpssi);
}
}
/**
* @brief DMA PSSI slave transmit process complete callback.
* @param hdma DMA handle
* @retval None
*/
void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmperror;
/* Disable Interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
/* Store current volatile hpssi->ErrorCode, misra rule */
tmperror = hpssi->ErrorCode;
/* Call the corresponding callback to inform upper layer of End of Transfer */
if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
PSSI_Error(hpssi, hpssi->ErrorCode);
}
/* hpssi->State == HAL_PSSI_STATE_BUSY_TX */
else
{
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->TxCpltCallback(hpssi);
}
}
/**
* @brief DMA PSSI master receive process complete callback.
* @param hdma DMA handle
* @retval None
*/
void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmperror;
/* Disable Interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
/* Store current volatile hpssi->ErrorCode, misra rule */
tmperror = hpssi->ErrorCode;
/* Call the corresponding callback to inform upper layer of End of Transfer */
if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
PSSI_Error(hpssi, hpssi->ErrorCode);
}
/* hpssi->State == HAL_PSSI_STATE_BUSY_RX */
else
{
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->RxCpltCallback(hpssi);
}
}
/**
* @brief DMA PSSI communication abort callback
* (To be called at end of DMA Abort procedure).
* @param hdma DMA handle.
* @retval None
*/
void PSSI_DMAAbort(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
/* Reset AbortCpltCallback */
hpssi->hdmatx->XferAbortCallback = NULL;
hpssi->hdmarx->XferAbortCallback = NULL;
/* Check if come from abort from user */
if (hpssi->State == HAL_PSSI_STATE_ABORT)
{
hpssi->State = HAL_PSSI_STATE_READY;
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->AbortCpltCallback(hpssi);
}
else
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->ErrorCallback(hpssi);
}
}
/**
* @brief This function handles PSSI Communication Timeout.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @param Flag Specifies the PSSI flag to check.
* @param Status The new Flag status (SET or RESET).
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart)
{
while ((HAL_PSSI_GET_STATUS(hpssi, Flag) & Flag) == (uint32_t)Status)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hpssi->ErrorCode |= HAL_PSSI_ERROR_TIMEOUT;
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
return HAL_ERROR;
}
}
}
return HAL_OK;
}
void PSSI_DMAError(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmperror;
/* Disable the selected PSSI peripheral */
HAL_PSSI_DISABLE(hpssi);
/* Disable Interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
/* Store current volatile hpssi->ErrorCode, misra rule */
tmperror = hpssi->ErrorCode;
/* Call the corresponding callback to inform upper layer of End of Transfer */
if ((hpssi->State == HAL_PSSI_STATE_ABORT) || (tmperror != HAL_PSSI_ERROR_NONE))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
PSSI_Error(hpssi, hpssi->ErrorCode);
}
else
{
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->ErrorCallback(hpssi);
}
}
/**
* @}
*/
#endif /* PSSI */
#endif /* HAL_PSSI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pssi.c
|
C
|
apache-2.0
| 57,272
|
/**
******************************************************************************
* @file stm32u5xx_hal_pwr.c
* @author MCD Application Team
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Initialization/De-Initialization Functions.
* + Peripheral Control Functions.
* + PWR Attributes Functions.
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### PWR peripheral overview #####
==============================================================================
[..]
(#) The Power control (PWR) provides an overview of the supply architecture
for the different power domains and of the supply configuration
controller.
(#) Domain architecture overview for the U5 devices:
(+) U5 devices have 2 power domains (CD and SRD).
The core domain (CD) contains a CPU (Cortex-M33), a Flash memory and
some peripherals dedicated for general purpose. The SRD domain
contains the system control and low-power peripherals.
(#) Every entity has low power mode as described below :
(#) The CPU low power modes are :
(+) CPU CRun.
(+) CPU CSleep.
(+) CPU CStop.
(#) The system low power modes are :
(+) Run.
(+) Stop 0.
(+) Stop 1.
(+) Stop 2.
(+) Stop 3.
(+) Standby.
(+) Shutdown.
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) After startup, power management peripheral is not active by default. Use
__HAL_RCC_PWR_CLK_ENABLE() macro to enable power interface.
(#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions
to enable/disable access to the backup domain (RCC Backup domain control
register RCC_BDCR, RTC registers, TAMP registers, backup registers and
backup SRAM).
(#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event
mode and voltage threshold) in order to set up the Programmed Voltage
Detector, then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD()
functions to start and stop the PVD detection.
(+) PVD level can be one of the following values :
(++) 2V0
(++) 2V2
(++) 2V4
(++) 2V5
(++) 2V6
(++) 2V8
(++) 2V9
(++) External input analog voltage PVD_IN (compared internally to
VREFINT)
(#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions
with the right parameter to configure the wake up pin polarity (Low or
High), the wake up pin selection and to enable and disable it.
(#) Call HAL_PWR_EnterSLEEPMode() function to enter the CPU in Sleep mode.
Wake-up from Sleep mode could be following to an event or an
interrupt according to low power mode intrinsic request called (__WFI()
or __WFE()).
(#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0
mode. Wake-up from Stop 0 mode could be following to an event or an
interrupt according to low power mode intrinsic request called (__WFI()
or __WFE()). (Regulator state on U5 devices is managed internally but
regulator parameter is kept for product compatibility).
(#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in
Standby mode. Wake-up from Standby mode can be following only by an
interrupt.
(#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to
enable and disable the Cortex-M33 re-entry in Sleep mode after an
interruption handling is over.
(#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions
to configure the Cortex-M33 to wake-up after any pending event / interrupt
even if it's disabled or has insufficient priority to cause exception
entry.
(#) Call HAL_PWR_PVD_IRQHandler() under PVD_AVD_IRQHandler() function to
handle the PWR PVD interrupt request.
(#) Call HAL_PWR_ConfigAttributes() function to configure PWR item secure and
privilege attributes and call HAL_PWR_GetConfigAttributes() function to
get the attribute configuration for the selected item.
*** PWR HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in PWR HAL driver.
(+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags.
(+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
#if defined (HAL_PWR_MODULE_ENABLED)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PWR_Private_Defines PWR Private Defines
* @{
*/
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVD trigger */
#define PVD_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVD trigger */
#define PVD_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVD threshold crossing */
#define PVD_MODE_EVT (0x08U) /*!< Mask for event yielded by PVD threshold crossing */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
* @brief Initialization and de-Initialization functions
*
@verbatim
===============================================================================
##### Initialization and De-Initialization Functions #####
===============================================================================
[..]
This section provides functions allowing to deinitialize power peripheral
and to manage backup domain access.
[..]
After system reset, the backup domain (RCC Backup domain control register
RCC_BDCR, RTC registers, TAMP registers, backup registers and backup SRAM)
is protected against possible unwanted write accesses.
The HAL_PWR_EnableBkUpAccess() function enables the access to the backup
domain.
The HAL_PWR_DisableBkUpAccess() function disables the access to the backup
domain.
@endverbatim
* @{
*/
/**
* @brief Deinitialize the HAL PWR peripheral registers to their default reset
* values.
* @note This functionality is not available in this product.
* The prototype is kept just to maintain compatibility with other
* products.
* @retval None.
*/
void HAL_PWR_DeInit(void)
{
}
/**
* @brief Enable access to the backup domain (RCC Backup domain control
* register RCC_BDCR, RTC registers, TAMP registers, backup registers
* and backup SRAM).
* @note After a system reset, the backup domain is protected against
* possible unwanted write accesses.
* @retval None.
*/
void HAL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
}
/**
* @brief Disable access to the backup domain (RCC Backup domain control
* register RCC_BDCR, RTC registers, TAMP registers, backup registers
* and backup SRAM).
* @retval None.
*/
void HAL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP);
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions
* @brief Low power modes configuration functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This section provides functions allowing to control power peripheral.
*** PVD configuration ***
=========================
[..]
(+) The PVD can be used to monitor the VDD power supply by comparing it
to a threshold selected by the PVDLS[2:0] bits in the PWR supply
voltage monitoring control register (PWR_SVMCR) and can be enabled by
setting the PVDE bit.
(+) A PVDO flag is available in the PWR supply voltage monitoring control
register (PWR_SVMCR) to indicate if VDD is higher or lower than the
PVD threshold. This event is internally connected to the EXTI line 16
and can generate an interrupt if enabled through the EXTI registers.
It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD can remain active in Stop 0, Stop 1, Stop 2 modes, and the PVM
interrupt can wake up from the Stop mode. The PVD is not functional in
Stop 3 mode.
(+) During Stop 1, Stop 2 and Stop 3 modes, it is possible to set the PVD
in ultra-low-power mode to further reduce the current consumption by
setting the ULPMEN bit in PWR_CR1 register.
*** Wake-up pin configuration ***
=================================
[..]
(+) Wake-up pin is used to wake up the system from Stop 3, Standby and
Shutdown mode.
The pin selection is configurable through the WUCR3 register to map
internal signal to wake up pin line.
The pin polarity is configurable through the WUCR2 register to be
active on rising or falling edges.
(+) There are up to 24 wake-up signals that can be mapped to up to 8
wake-up lines in the STM32U5 family.
*** Low Power modes configuration ***
=====================================
[..]
This section presents 3 principles low-power modes :
(+) Sleep mode : Cortex-M33 is stopped and all PWR domains are remaining
active (powered and clocked).
(+) Stop 0 mode : Cortex-M33 is stopped, clocks are stopped and the
regulator is running.
(+) Standby mode : All PWR domains enter DSTANDBY mode and the VCORE
supply regulator is powered off.
*** Sleep mode ***
==================
[..]
(+) Entry :
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode()
function.
(++) PWR_SLEEPENTRY_WFI: enter Sleep mode with WFI instruction.
(++) PWR_SLEEPENTRY_WFE: enter Sleep mode with WFE instruction.
-@@- The Regulator parameter is not used for the STM32U5 family and is
kept as parameter just to maintain compatibility with other families.
(+) Exit :
According to Sleep entry, any event when entry is __WFE() intrinsic
and any interrupt when entry is __WFI() intrinsic can wake up the
device from Sleep mode.
*** Stop 0 mode ***
===================
[..]
The Stop 0 mode is based on the Cortex-M33 Deepsleep mode combined with
the peripheral clock gating. The voltage regulator is configured in main
regulator mode. In Stop 0 mode, all clocks in the VCORE domain are stopped.
The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
MSIK for transferring data. All SRAMs and register contents are preserved,
but the SRAMs can be totally or partially switched off to further reduced
consumption.
The BOR is always available in Stop 0 mode.
(+) Entry:
The Stop mode is entered using the HAL_PWR_EnterSTOPMode() function
with :
(++) StopEntry:
(+++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction.
(+++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction.
-@@- The Regulator parameter is not used for the STM32U5 family and is
kept as parameter just to maintain compatibility with other families.
(+) Exit:
Any EXTI line configured in interrupt mode (the corresponding EXTI
interrupt vector must be enabled in the NVIC). The interrupt source
can be external interrupts or peripherals with wakeup capability.
Any peripheral interrupt occurring when the AHB/APB clocks are present
due to an autonomous peripheral clock request (the peripheral vector
must be enabled in the NVIC).
*** Standby mode ***
====================
[..]
The Standby mode is used to achieve the lowest power consumption with BOR.
The internal regulator is switched off so that the VCORE domain is powered
off.
The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and the HSE crystal
oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without
RTC).
The Brownout reset (BOR) always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software:
I/O with internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAMs and register contents are lost except
for registers and backup SRAM in the Backup domain and Standby circuitry.
Optionally, the full SRAM2 or 8 Kbytes or 56 Kbytes can be retained in
Standby mode, supplied by the low-power regulator (Standby with RAM2
retention mode).
The BORL (Brownout reset detector low) can be configured in ultra low
power mode to further reduce power consumption during Standby mode.
The device exits Standby mode upon an external reset (NRST pin), an IWDG
reset, WKUP pin event (configurable rising or falling edge), an RTC event
occurs (alarm, periodic wakeup, timestamp), or a tamper detection.
The system clock after wakeup is MSIS up to 4 MHz.
(++) Entry:
The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode()
function.
(++) Exit:
WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset,
BOR reset.
@endverbatim
* @{
*/
/**
* @brief Configure the voltage threshold detected by the Programmed Voltage
* Detector (PVD).
* @param pConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the
* PVD configuration information (PVDLevel and EventMode).
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *pConfigPVD)
{
/* Check the PVD parameter */
if (pConfigPVD == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(pConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(pConfigPVD->Mode));
/* Set PVDLS[2:0] bits according to PVDLevel value */
MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, pConfigPVD->PVDLevel);
/* Disable PVD Event/Interrupt */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/* Configure the PVD in interrupt mode */
if ((pConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT();
}
/* Configure the PVD in event mode */
if ((pConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
/* Configure the PVD in rising edge */
if ((pConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
/* Configure the PVD in falling edge */
if ((pConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
return HAL_OK;
}
/**
* @brief Enable the programmable voltage detector (PVD).
* @retval None.
*/
void HAL_PWR_EnablePVD(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
}
/**
* @brief Disable the programmable voltage detector (PVD).
* @retval None.
*/
void HAL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE);
}
/**
* @brief Enable the wake up line functionality.
* @note Wake up lines are used to wake up the system from Stop 3, Standby and
* Shutdown modes.
* @param WakeUpPin : Specifies which wake up line to enable. This parameter
* can be one of PWR_WakeUp_Pins_High_Polarity define
* group where every param select the wake up line, the
* wake up source with high polarity detection and the wake
* up selected I/O or can be one of
* PWR_WakeUp_Pins_Low_Polarity define group where every
* param select the wake up line, the wake up source with
* low polarity and the wake up selected I/O or can be one
* of PWR_WakeUp_Pins define group where every param select
* the wake up line, the wake up source with
* high polarity and the first wake up I/O.
* @retval None.
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin));
/* Specifies the wake up line polarity for the event detection (rising or falling edge) */
MODIFY_REG(PWR->WUCR2, (PWR_EWUP_MASK & WakeUpPin), (WakeUpPin >> PWR_WUP_POLARITY_SHIFT));
/* Specifies the wake up line I/O selection */
MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(PWR_EWUP_MASK & WakeUpPin) * 2U)),
(WakeUpPin >> PWR_WUP_SELECT_SIGNAL_SHIFT));
/* Enable wake-up line */
SET_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin));
}
/**
* @brief Disable the wake up line functionality.
* @param WakeUpPin : Specifies the wake up line to disable.
* This parameter can be a combination of all the following
* values :
* @arg @ref PWR_WAKEUP_PIN1
* @arg @ref PWR_WAKEUP_PIN2
* @arg @ref PWR_WAKEUP_PIN3
* @arg @ref PWR_WAKEUP_PIN4
* @arg @ref PWR_WAKEUP_PIN6
* @arg @ref PWR_WAKEUP_PIN5
* @arg @ref PWR_WAKEUP_PIN7
* @arg @ref PWR_WAKEUP_PIN8
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
{
/* Check the parameters */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin));
/* Disable wake-up pin */
CLEAR_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin));
}
/**
* @brief Enter the CPU in Sleep mode.
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
* @note CPU clock is off and all peripherals including Cortex-M33 core such
* as NVIC and SysTick can run and wake up the CPU when an interrupt
* or an event occurs.
* @param Regulator : Specifies the regulator state in Sleep mode.
* This parameter can be one of the following values :
* @arg @ref PWR_MAINREGULATOR_ON
* @arg @ref PWR_LOWPOWERREGULATOR_ON
* @note This parameter is not available in this product.
* The parameter is kept just to maintain compatibility with other
* products.
* @param SleepEntry : Specifies if Sleep mode is entered with WFI or WFE
* instruction.
* This parameter can be one of the following values :
* @arg @ref PWR_SLEEPENTRY_WFI enter Sleep mode with Wait
* For Interrupt request.
* @arg @ref PWR_SLEEPENTRY_WFE enter Sleep mode with Wait
* For Event request.
* @note When WFI entry is used, ticks interrupt must be disabled to avoid
* unexpected CPU wake up.
* @retval None.
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry)
{
UNUSED(Regulator);
/* Check the parameter */
assert_param(IS_PWR_SLEEP_ENTRY(SleepEntry));
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Sleep mode entry */
if (SleepEntry == PWR_SLEEPENTRY_WFI)
{
/* Wait For Interrupt Request */
__WFI();
}
else
{
/* Wait For Event Request */
__SEV();
__WFE();
__WFE();
}
}
/**
* @brief Enter the whole system to Stop 0 mode.
* @note In Stop 0 mode, the regulator remains in main regulator mode,
* allowing a very fast wakeup time but with much higher consumption
* comparing to other Stop modes.
* @note Stop 0 offers the largest number of active peripherals and wakeup
* sources, a smaller wakeup time but a higher consumption.
* Stop mode achieves the lowest power consumption while retaining
* the content of SRAM and registers. All clocks in the VCORE domain
* are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
* the HSE crystal oscillators are disabled. The LSE or LSI is still
* running.
* @note The system clock when exiting from Stop mode can be either MSIS up
* to 24 MHz or HSI16, depending on software configuration.
* @param Regulator : Specifies the regulator state in Stop mode.
* This parameter can be one of the following values :
* @arg @ref PWR_MAINREGULATOR_ON
* @arg @ref PWR_LOWPOWERREGULATOR_ON
* @note This parameter is not available in this product.
* The parameter is kept just to maintain compatibility with other
* products.
* @param StopEntry : Specifies if Stop mode is entered with WFI or WFE
* instruction.
* This parameter can be one of the following values :
* @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
* For Interrupt request.
* @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
* For Event request.
* @retval None.
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry)
{
UNUSED(Regulator);
/* Check the parameter */
assert_param(IS_PWR_STOP_ENTRY(StopEntry));
/* Select Stop 0 mode */
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, 0U);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Stop mode entry */
if (StopEntry == PWR_STOPENTRY_WFI)
{
/* Wait For Interrupt Request */
__WFI();
}
else
{
/* Wait For Event Request */
__SEV();
__WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Enter the whole system to Standby mode.
* @note The Standby mode is used to achieve the lowest power consumption
* with BOR. The internal regulator is switched off so that the VCORE
* domain is powered off. The PLL, the MSI (MSIS and MSIK) RC, the
* HSI16 RC and the HSE crystal oscillators are also switched off.
* @note After entering Standby mode, SRAMs and register contents are lost
* except for registers and backup SRAM in the Backup domain and
* Standby circuitry. Optionally, the full SRAM2 or 8 Kbytes or 56
* Kbytes can be retained in Standby mode, supplied by the low-power
* regulator (Standby with RAM2 retention mode) through
* HAL_PWREx_EnableSRAM2ContentStandbyRetention().
* @note The state of each I/O during Standby mode can be selected by
* software : I/O with internal pull-up through
* HAL_PWREx_EnableGPIOPullUp() and internal pull-down through
* HAL_PWREx_EnableGPIOPullDown().
* @retval None.
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
/* Select Standby mode */
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_2);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
__force_stores();
#endif /*( __CC_ARM)*/
/* Wait For Interrupt Request */
__WFI();
}
/**
* @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to
* thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
* processor re-enters Sleep mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run
* only on interruptions handling.
* @retval None.
*/
void HAL_PWR_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex-M33 System Control Register */
SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
/**
* @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to
* thread mode.
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the
* processor re-enters Sleep mode when an interruption handling is over.
* @retval None.
*/
void HAL_PWR_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex-M33 System Control Register */
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
}
/**
* @brief Enable CORTEX SEV-ON-PEND feature.
* @note Sets SEVONPEND bit of SCR register. When this bit is set, any
* pending event / interrupt even if it's disabled or has insufficient
* priority to cause exception entry wakes up the Cortex-M33.
* @retval None.
*/
void HAL_PWR_EnableSEVOnPend(void)
{
/* Set SEVONPEND bit of Cortex-M33 System Control Register */
SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
/**
* @brief Disable CORTEX SEVONPEND feature.
* @note Resets SEVONPEND bit of SCR register. When this bit is reset, only enabled
* pending event / interrupt to cause exception entry wakes up the Cortex-M33.
* @retval None.
*/
void HAL_PWR_DisableSEVOnPend(void)
{
/* Clear SEVONPEND bit of Cortex-M33 System Control Register */
CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
}
/**
* @brief This function handles the PWR PVD interrupt request.
* @note This API should be called under the PVD_AVD_IRQHandler().
* @retval None.
*/
void HAL_PWR_PVD_IRQHandler(void)
{
uint32_t rising_flag;
uint32_t falling_flag;
/* Get pending flags */
rising_flag = READ_REG(EXTI->RPR1);
falling_flag = READ_REG(EXTI->FPR1);
/* Check PWR EXTI flags for PVD */
if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PVD EXTI pending bit */
WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
}
}
/**
* @brief PWR PVD interrupt callback.
* @retval None.
*/
__weak void HAL_PWR_PVDCallback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PWR_PVDCallback can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group3 Attributes Management Functions
* @brief Attributes management functions
*
@verbatim
===============================================================================
##### PWR Attributes Functions #####
===============================================================================
[..]
When the TrustZone security is activated by the TZEN option bit in the
FLASH_OPTR register, some PWR register fields can be secured against
non-secure access.
The PWR TrustZone security allows the following features to be secured
through the PWR_SECCFGR register :
(++) Low-power mode.
(++) Wake-up (WKUP) pins.
(++) Voltage detection and monitoring.
(++) VBAT mode.
(++) I/Os pull-up/pull-down configuration.
Other PWR configuration bits are secure when :
(++) The system clock selection is secure in RCC: the voltage scaling
(VOS) configuration and the regulator booster (BOOSTEN) are secure.
(++) A GPIO is configured as secure: its corresponding bit for pull-up /
pull-down configuration in Standby mode is secure.
(++) The UCPD1 is secure in the GTZC: the PWR_UCPDR register is secure.
A non-secure access to a secure-protected register bit is denied :
(++) The secured bits are not written (WI) with a non-secure write access.
(++) The secured bits are read as 0 (RAZ) with a non-secure read access.
[..]
When the TrustZone security is disabled (TZEN = 0), PWR_SECCFGR is RAZ/WI
and all other registers are non-secure.
[..]
By default, after a reset, all PWR registers can be read or written with
both privileged and unprivileged accesses, except PWR_PRIVCFGR that can be
written with privileged access only. PWR_PRIVCFGR can be read by secure
and non secure, privileged and unprivileged accesses.
The SPRIV bit in PWR_PRIVCFGR can be written with secure privileged access
only. This bit configures the privileged access of all PWR secure
functions (defined by PWR_SECCFGR, GTZC, RCC or GPIO).
When the SPRIV bit is set in PWR_PRIVCFGR:
(++) The PWR secure bits can be written only with privileged access,
including PWR_SECCFGR.
(++) The PWR secure bits can be read only with privileged access except
PWR_SECCFGR and PWR_PRIVCFGR that can be read by privileged or
unprivileged access.
(++) An unprivileged access to a privileged PWR bit or register is
discarded : the bits are read as zero and the write to these bits is
ignored (RAZ/WI).
The NSPRIV bit of PWR_PRIVCFGR can be written with privileged access only,
secure or non-secure. This bit configures the privileged access of all PWR
securable functions that are configured as non-secure (defined by
PWR_SECCFGR, GTZC, RCC or GPIO).
When the NSPRIV bit is set in PWR_PRIVCFGR :
(++) The PWR securable bits that are configured as non-secure, can be
written only with privileged access.
(++) The PWR securable bits that are configured as non-secure, can be read
only with privileged access except PWR_PRIVCFGR that can be read by
privileged or unprivileged accesses.
(++) The VOSRDY and BOOSTRDY bits in PWR_VOSR, PWR_SR, PWR_SVMSR, PWR_BDSR
and PWR_WUSR, can be read with privileged or unprivileged accesses.
(++) An unprivileged access to a privileged PWR bit or register is
discarded : the bits are read as zero and the write to these bits is
ignored (RAZ/WI).
@endverbatim
* @{
*/
/**
* @brief Configure the PWR item attributes.
* @note Available attributes are security and privilege protection.
* @note Security attribute can only be set only by secure access.
* @note Privilege attribute for secure items can be managed only by a secure
* privileged access.
* @note Privilege attribute for nsecure items can be managed by a secure
* privileged access or by a nsecure privileged access.
* @param Item : Specifies the item(s) to set attributes on.
* This parameter can be a combination of @ref PWR_Items.
* @param Attributes : Specifies the available attribute(s).
* This parameter can be one of @ref PWR_Attributes.
* @retval None.
*/
void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes)
{
/* Check the parameters */
assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
assert_param(IS_PWR_ATTRIBUTES(Attributes));
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Secure item management (TZEN = 1) */
if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK)
{
/* Privilege item management */
if ((Attributes & PWR_SEC_PRIV) == PWR_SEC_PRIV)
{
SET_BIT(PWR->SECCFGR, Item);
SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
}
else
{
SET_BIT(PWR->SECCFGR, Item);
CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV);
}
}
/* NSecure item management */
else
{
/* Privilege item management */
if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV)
{
CLEAR_BIT(PWR->SECCFGR, Item);
SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
}
else
{
CLEAR_BIT(PWR->SECCFGR, Item);
CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
}
}
#else
/* Prevent unused argument(s) compilation warning */
UNUSED(Item);
/* NSecure item management (TZEN = 0) */
if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK)
{
/* Privilege item management */
if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV)
{
SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
}
else
{
CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV);
}
}
#endif /* __ARM_FEATURE_CMSE */
}
/**
* @brief Get attribute(s) of a PWR item.
* @param Item : Specifies the item(s) to get attributes of.
* This parameter can be one of @ref PWR_Items.
* @param pAttributes : Pointer to return attribute(s).
* Returned value could be one of @ref PWR_Attributes.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
{
uint32_t attributes;
/* Check attribute pointer */
if (pAttributes == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Check item security */
if ((PWR->SECCFGR & Item) == Item)
{
/* Get Secure privileges attribute */
attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_SPRIV) == 0U) ? PWR_SEC_NPRIV : PWR_SEC_PRIV;
}
else
{
/* Get Non-Secure privileges attribute */
attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV;
}
#else
/* Get Non-Secure privileges attribute */
attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV;
#endif /* __ARM_FEATURE_CMSE */
/* return value */
*pAttributes = attributes;
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined (HAL_PWR_MODULE_ENABLED) */
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c
|
C
|
apache-2.0
| 35,777
|
/**
******************************************************************************
* @file stm32u5xx_hal_pwr_ex.c
* @author MCD Application Team
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller extension peripheral :
* + Power Supply Control Functions
* + Low Power Control Functions
* + Voltage Monitoring Functions
* + Memories Retention Functions
* + I/O Pull-Up Pull-Down Configuration Functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Call HAL_PWREx_ControlVoltageScaling() and HAL_PWREx_GetVoltageRange() to
set / get the voltage scaling range.
(+) Voltage scaling can be one of the following values :
(++) voltage output scale 1 : 1V2
=> Used when system clock frequency is up to 160 MHz
(++) voltage output scale 2 : 1V1
=> Used when system clock frequency is up to 100 MHz
(++) voltage output scale 3 : 1V0
=> Used when system clock frequency is up to 50 MHz
(++) voltage output scale 4 : 0V9
=> Used when system clock frequency is up to 24 MHz
(#) Call HAL_PWREx_EnableFastSoftStart() and HAL_PWREx_DisableFastSoftStart()
to enable / disable the fast software startup for the current regulator.
(#) Call HAL_PWREx_EnterSTOP1Mode() function to enter the whole system to
Stop 1 mode. Wake-up from Stop 1 mode could be following to an event or
an interrupt according to low power mode intrinsic request called
(__WFI() or __WFE()). (Regulator state on U5 devices is managed
internally but regulator parameter is kept for product compatibility).
(#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the whole system to
Stop 2 mode. Wake-up from Stop 2 mode could be following to an event or
an interrupt according to low power mode intrinsic request called
(__WFI() or __WFE()). (Regulator state on U5 devices is managed
internally but regulator parameter is kept for product compatibility).
(#) Call HAL_PWREx_EnterSTOP3Mode() function to enter the whole system to
Stop 3 mode. Wake-up from Stop 3 mode could be following to an event or
an interrupt according to low power mode intrinsic request called
(__WFI() or __WFE()). (Regulator state on U5 devices is managed
internally but regulator parameter is kept for product compatibility).
(#) Call HAL_PWREx_EnterSHUTDOWNMode() function to enter the whole system in
Shutdown mode. Wake-up from Shutdown mode can be following to an external
reset (NRST pin), a WKUP pin event (configurable rising or falling edge),
or an RTC event occurs (alarm, periodic wakeup, timestamp), or a tamper
detection.
(#) Call HAL_PWREx_ConfigSRDDomain() to force in Run mode or to enter in Stop
mode Smart Run Domain when the system enters Stop mode (Stop 0/1/2).
(#) Call HAL_PWREx_EnableUltraLowPowerMode() and
HAL_PWREx_DisableUltraLowPowerMode() to enable / disable the BOR ultra
low power mode.
(#) Call HAL_PWREx_S3WU_IRQHandler() function to handle the PWR Stop 3 wake
up interrupt request.
(#) Call HAL_PWREx_EnableBatteryCharging() and
HAL_PWREx_DisableBatteryCharging() to enable / disable the battery
charging capability when VDD alimentation is available.
(#) Call HAL_PWREx_EnableVddUSB(), HAL_PWREx_EnableVddIO2() and
HAL_PWREx_EnableVddA() to enable respectively VDDUSB, VDDIO2 and VDDA
electrical and logical isolation.
It is recommended to disable VDDUSB, VDDIO2 and VDDA electrical and
logical isolation through HAL_PWREx_DisableVddUSB(),
HAL_PWREx_DisableVddIO2() and HAL_PWREx_DisableVddA().
(#) Call HAL_PWREx_ConfigPVM() after setting parameters to be configured
(event mode and PVD type) in order to set up the Peripheral Voltage
Monitor, then use HAL_PWREx_EnableUVM(), HAL_PWREx_EnableIO2VM(),
HAL_PWREx_EnableAVM1() and HAL_PWREx_EnableAVM2() functions to start the
PVM VDDx monitoring and use HAL_PWREx_DisableUVM(),
HAL_PWREx_DisableIO2VM(), HAL_PWREx_DisableAVM1() and
HAL_PWREx_DisableAVM2() to stop the PVM VDDx monitoring.
(+) PVM monitored voltages are :
(++) VDDUSB versus 1V2
(++) VDDIO2 versus 0V9
(++) VDDA versus 1V6
(++) VDDA versus 1V8
(#) Call HAL_PWREx_EnableUSBHSTranceiverSupply() and
HAL_PWREx_DisableUSBHSTranceiverSupply() to enable / disable the internal
USB HS transceiver supply.
(+) This feature is available only for STM32U59xxx and STM32U5Axxx devices.
(#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() to
enable / disable the VBAT and temperature monitoring.
(#) Call HAL_PWREx_EnableUCPDStandbyMode() and
HAL_PWREx_DisableUCPDStandbyMode() to enable / disable the UCPD
configuration memorization in Standby mode.
(#) Call HAL_PWREx_EnableUCPDDeadBattery() and
HAL_PWREx_DisableUCPDDeadBattery() to enable / disable the dead battery
behavior.
(#) Call HAL_PWREx_PVD_PVM_IRQHandler() function to handle the PWR PVD and
PVM interrupt request.
(#) Call HAL_PWREx_EnableSRAM2ContentStandbyRetention() and
HAL_PWREx_DisableSRAM2ContentStandbyRetention() to
enable / disable the SRAM2 content retention in Stop 3 and Standby low
power modes.
(#) Call HAL_PWREx_EnableRAMsContentStopRetention() and
HAL_PWREx_DisableRAMsContentStopRetention() to
enable / disable the RAMs content retention in Stop mode (Stop 0/1/2/3).
(+) Retained RAM can be one of the following RAMs :
(++) SRAM1
(++) SRAM2
(++) SRAM3
(++) SRAM4
(++) ICACHE
(++) DMA2DRAM
(++) PKA32RAM
(++) DCACHE1
(++) FMAC
(++) FDCAN
(++) USB
(++) DCACHE2 (available only for STM32U599xx and STM32U5A9xx devices)
(++) LTDC (available only for STM32U599xx and STM32U5A9xx devices)
(++) GFXMMU (available only for STM32U599xx and STM32U5A9xx devices)
(++) DSI (available only for STM32U599xx and STM32U5A9xx devices)
(#) Call HAL_PWREx_EnableRAMsContentRunRetention() and
HAL_PWREx_DisableRAMsContentRunRetention() to
enable / disable the RAMs content retention in Run mode.
(+) Retained RAM can be one of the following RAMs :
(++) SRAM1
(++) SRAM2
(++) SRAM3
(++) SRAM4
(++) SRAM5 (available only for STM32U59xxx and STM32U5Axxx devices)
(#) Call HAL_PWREx_EnableFlashFastWakeUp() and
HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory
fast wakeup from Stop mode (Stop 0/1).
(#) Call HAL_PWREx_EnableSRAM4FastWakeUp() and
HAL_PWREx_DisableSRAM4FastWakeUp() to enable / disable the SRAM4 memory
fast wakeup from Stop mode (Stop 0/1/2).
(#) Call HAL_PWREx_EnableBkupRAMRetention() and
HAL_PWREx_DisableBkupRAMRetention() to enable / disable the Backup RAM
content retention in Standby, Shutdown and VBAT modes.
(#) Call HAL_PWREx_EnablePullUpPullDownConfig() and
HAL_PWREx_DisablePullUpPullDownConfig() to I/O enable / disable pull-up
and pull-down configuration.
(#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to
apply respectively pull-up and pull-down to selected I/O.
Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to
disable applied respectively pull-up and pull-down to selected I/O.
@endverbatim
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup PWREx PWREx
* @brief PWR Extended HAL module driver
* @{
*/
#if defined (HAL_PWR_MODULE_ENABLED)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
* @{
*/
#if defined (PWR_PUCRJ_PU0)
/* PORTI pins mask */
#define PWR_PORTI_AVAILABLE_PINS (0xFFFFU)
/* PORTJ pins mask */
#define PWR_PORTJ_AVAILABLE_PINS (0x0FFFU)
#else
/* PORTI pins mask */
#define PWR_PORTI_AVAILABLE_PINS (0x00FFU)
#endif /* defined (PWR_PUCRJ_PU0) */
/* Time out value of flags setting */
#define PWR_FLAG_SETTING_DELAY (0x32U)
/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
* @{
*/
#define PVM_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVM trigger */
#define PVM_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVM trigger */
#define PVM_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVM threshold crossing */
#define PVM_MODE_EVT (0x08U) /*!< Mask for event yielded by PVM threshold crossing */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
* @{
*/
/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
* @brief Power supply control functions
*
@verbatim
===============================================================================
##### Power supply control functions #####
===============================================================================
[..]
This section provides functions allowing to control power supply.
[..]
(+) The STM32U5 Series devices embed two regulators : one LDO (linear
voltage regulator) and one SMPS (step down converter) in parallel to
provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3
and SRAM4 and embedded Flash memory.
(+) The SMPS allows the power consumption to be reduced but some
peripherals can be perturbed by the noise generated by the SMPS,
requiring the application to switch to LDO when running this
peripheral in order to reach the best performances.
(+) The LDO and the SMPS regulators have two modes: Main regulator mode
(used when performance is needed), and Low-power regulator mode. LDO
or SMPS can be used in all voltage scaling ranges, and in all Stop
modes.
(+) After reset, the regulator is the LDO, in Range 4. Switching to SMPS
provides lower consumption in particular at high VDD voltage. It is
possible to switch from LDO to SMPS, or from SMPS to LDO on the fly in
any range, by configuring the REGSEL bit. It is recommended to switch
first to SMPS before changing the voltage range.
(+) When exiting the Stop or Standby modes, the regulator is the same than
when entering low power modes. The voltage range is the Range 4.
(+) Both regulators can provide four different voltages (voltage scaling)
and can operate in Stop modes.
Voltage scaling ranges can be one of the following values :
(++) voltage output scale 1 : 1V2
=> Used when system clock frequency is up to 160 MHz
(++) voltage output scale 2 : 1V1
=> Used when system clock frequency is up to 100 MHz
(++) voltage output scale 3 : 1V0
=> Used when system clock frequency is up to 50 MHz
(++) voltage output scale 4 : 0V9
=> Used when system clock frequency is up to 24 MHz
@endverbatim
* @{
*/
/**
* @brief Configure the main internal regulator output voltage to achieve
* a tradeoff between performance and power consumption.
* @param VoltageScaling : Specifies the regulator output voltage scale.
* This parameter can be one of the following values :
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1.
* Provides a typical output voltage at 1.2 V.
* Used when system clock frequency is up to 160 MHz.
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2.
* Provides a typical output voltage at 1.1 V.
* Used when system clock frequency is up to 100 MHz.
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3.
* Provides a typical output voltage at 1.0 V.
* Used when system clock frequency is up to 50 MHz.
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4.
* Provides a typical output voltage at 0.9 V.
* Used when system clock frequency is up to 24 MHz.
* @note Before moving to voltage scaling 2, it is mandatory to ensure that
* the system frequency is between 50 MHz and 100 MHz.
* @note Before moving to voltage scaling 3, it is mandatory to ensure that
* the system frequency is between 24 MHz and 50 MHz.
* @note Before moving to voltage scaling 4, it is mandatory to ensure that
* the system frequency is below 24 MHz.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
uint32_t timeout;
uint32_t vos_old;
/* Check the parameter */
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
/* Get the current voltage scale applied */
vos_old = READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS);
/* No change, nothing to do */
if (vos_old == VoltageScaling)
{
return HAL_OK;
}
/* Check voltage scaling level */
/*
* The Embedded power distribution (EPOD) must be enabled before switching to
* voltage scale 1 / 2 from voltage scale lower.
*/
if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3)
{
MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), (VoltageScaling | PWR_VOSR_BOOSTEN));
}
else
{
MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), VoltageScaling);
}
/* Wait until VOSRDY is raised */
timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U))
{
timeout--;
}
/* Check time out */
if (timeout != 0U)
{
/* Wait until ACTVOSRDY is raised */
timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U))
{
timeout--;
}
}
/* Check time out */
if (timeout == 0U)
{
return HAL_TIMEOUT;
}
return HAL_OK;
}
/**
* @brief Return Voltage Scaling Range.
* @retval Applied voltage scaling value.
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
return (PWR->SVMSR & PWR_SVMSR_ACTVOS);
}
/**
* @brief Configure the system Power Supply.
* @param SupplySource : Specifies the Power Supply source to set after a
* system startup.
* This parameter can be one of the following values :
* @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power Domains.
* @arg PWR_SMPS_SUPPLY : The SMPS regulator supplies the Vcore Power Domains.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
{
uint32_t timeout;
/* Check the parameter */
assert_param(IS_PWR_SUPPLY(SupplySource));
/* Set maximum time out */
timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U;
/* Configure the LDO as system regulator supply */
if (SupplySource == PWR_LDO_SUPPLY)
{
/* Set the power supply configuration */
CLEAR_BIT(PWR->CR3, PWR_CR3_REGSEL);
/* Wait until system switch on new regulator */
while (HAL_IS_BIT_SET(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
{
timeout--;
}
}
/* Configure the SMPS as system regulator supply */
else
{
/* Set the power supply configuration */
SET_BIT(PWR->CR3, PWR_CR3_REGSEL);
/* Wait until system switch on new regulator */
while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U))
{
timeout--;
}
}
/* Check time out */
if (timeout == 0U)
{
return HAL_TIMEOUT;
}
return HAL_OK;
}
/**
* @brief Get the power supply configuration.
* @retval The supply configured.
*/
uint32_t HAL_PWREx_GetSupplyConfig(void)
{
return (PWR->SVMSR & PWR_SVMSR_REGS);
}
/**
* @brief Enable fast soft start for the current regulator.
* @retval None.
*/
void HAL_PWREx_EnableFastSoftStart(void)
{
SET_BIT(PWR->CR3, PWR_CR3_FSTEN);
}
/**
* @brief Disable fast soft start for the current regulator.
* @retval None.
*/
void HAL_PWREx_DisableFastSoftStart(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN);
}
/**
* @}
*/
/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
* @brief Low power control functions
*
@verbatim
===============================================================================
##### Low power control functions #####
===============================================================================
[..]
This section provides functions allowing to control low power modes.
*** Low Power modes configuration ***
=====================================
[..]
This section presents 4 principles low power modes :
(+) Stop 1 mode : Cortex-M33 is stopped, clocks are stopped and the
regulator is in low power mode. Several peripheral can
operate in this mode.
(+) Stop 2 mode : Cortex-M33 is stopped, clocks are stopped and the
regulator is in low power mode. Only autonomous
peripherals can operate in this mode.
(+) Stop 3 mode : Cortex-M33 is stopped, clocks are stopped and the
regulator is in low power mode. No peripheral can
operate in this mode. Only RAMs content is preserved.
(+) Shutdown mode : All PWR domains enter Shutdown mode and the VCORE
supply regulator is powered off. The SRAMs and
register contents are lost except for registers in the
Backup domain.
*** Stop 1 mode ***
===================
[..]
The Stop 1 mode is based on the Cortex-M33 Deepsleep mode combined with
the peripheral clock gating. The voltage regulator is configured in low
power mode. In Stop 1 mode, all clocks in the VCORE domain are stopped.
The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
MSIK for transferring data. All SRAMs and register contents are preserved,
but the SRAMs can be totally or partially switched off to further reduced
consumption.
The BOR is always available in Stop 1 mode.
(+) Entry:
The Stop 1 mode is entered by using the HAL_PWREx_EnterSTOP1Mode()
function.
(++) PWR_STOPENTRY_WFI: enter Stop 1 mode with WFI instruction.
(++) PWR_STOPENTRY_WFE: enter Stop 1 mode with WFE instruction.
(+) Exit:
Any EXTI line configured in interrupt mode (the corresponding EXTI
interrupt vector must be enabled in the NVIC). The interrupt source
can be external interrupts or peripherals with wakeup capability.
Any peripheral interrupt occurring when the AHB/APB clocks are present
due to an autonomous peripheral clock request (the peripheral vector
must be enabled in the NVIC)
Any EXTI line configured in event mode.
*** Stop 2 mode ***
===================
[..]
The Stop 2 mode is based on the Cortex-M33 Deepsleep mode combined with
peripheral clock gating. In Stop 2 mode, all clocks in the VCORE domain
are stopped.
The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or
MSIK for transferring data. All SRAMs and register contents are preserved,
but the SRAMs can be totally or partially switched off to further reduce
consumption.
The BOR is always available in Stop 2 mode.
(+) Entry:
The Stop 2 mode is entered by using the HAL_PWREx_EnterSTOP2Mode()
function.
(++) PWR_STOPENTRY_WFI: enter Stop 2 mode with WFI instruction.
(++) PWR_STOPENTRY_WFE: enter Stop 2 mode with WFE instruction.
(+) Exit:
Any EXTI line configured in interrupt mode (the corresponding EXTI
interrupt vector must be enabled in the NVIC). The interrupt source
can be external interrupts or peripherals with wakeup capability.
Any peripheral interrupt occurring when the AHB/APB clocks are present
due to an autonomous peripheral clock request (the peripheral vector
must be enabled in the NVIC)
Any EXTI line configured in event mode.
*** Stop 3 mode ***
===================
[..]
The Stop 3 mode is based on the Cortex-M33 Deepsleep mode combined with
peripheral clock gating. In Stop 3 mode, all clocks in the VCORE domain
are stopped.
The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled.
All SRAMs and register contents are preserved, but the SRAMs can be
totally or partially switched off to further reduce consumption.
The BOR is always available in Stop 3 mode.
(+) Entry:
The Stop 3 mode is entered by using the HAL_PWREx_EnterSTOP3Mode()
function.
(++) PWR_STOPENTRY_WFI: enter Stop 3 mode with WFI instruction.
(++) PWR_STOPENTRY_WFE: enter Stop 3 mode with WFE instruction.
(+) Exit:
WKUPx pin edge, RTC or TAMP event, external Reset in NRST pin, IWDG
Reset, BOR reset.
*** Shutdown mode ***
====================
[..]
The lowest power consumption is reached in Shutdown mode. It is based on
the Deepsleep mode with the voltage regulator disabled. The VCORE domain
is consequently powered off.
The PLL, HSI16, MSIS, MSIK and HSE oscillators are also switched off.
The SRAMs and register contents are lost except for registers in the
Backup domain.
The BOR is not available in Shutdown mode.
No power voltage monitoring is possible in this mode, therefore the switch
to Backup domain is not supported.
(+) Entry:
The Shutdown mode is entered by using the HAL_PWREx_EnterSHUTDOWNMode()
function.
(+) Exit:
WKUPx pin edge, RTC/TAMP event, external Reset in NRST pin.
@endverbatim
* @{
*/
/**
* @brief Enter the whole system to Stop 1 mode.
* @note Stop 1 offers the largest number of active peripherals and wakeup
* sources, a smaller wakeup time but a higher consumption.
* @note Stop mode achieves the lowest power consumption while retaining
* the content of SRAM and registers. All clocks in the VCORE domain
* are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
* the HSE crystal oscillators are disabled. The LSE or LSI is still
* running.
* @note The system clock when exiting from Stop mode can be either MSIS up
* to 24 MHz or HSI16, depending on software configuration.
* @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
* instruction.
* This parameter can be one of the following values :
* @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
* For Interrupt request.
* @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
* For Event request.
* @retval None.
*/
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Stop 1 mode */
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_0);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Stop mode entry */
if (STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Enter the whole system to Stop 2 mode.
* @note In Stop 2 mode, all clocks in the VCORE domain are stopped. The PLL,
* MSIS, MSIK, HSI16 and HSE oscillators are disabled.
* @note Stop mode achieves the lowest power consumption while retaining
* the content of SRAM and registers. All clocks in the VCORE domain
* are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
* the HSE crystal oscillators are disabled. The LSE or LSI is still
* running.
* @note The system clock when exiting from Stop mode can be either MSIS up
* to 24 MHz or HSI16, depending on software configuration.
* @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
* instruction.
* This parameter can be one of the following values :
* @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
* For Interrupt request.
* @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
* For Event request.
* @retval None.
*/
void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Stop 2 mode */
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_1);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Stop mode entry */
if (STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Enter the whole system to Stop 3 mode.
* @note Stop 3 is the lowest power mode with full retention, but the
* functional peripherals and sources of wakeup are reduced to the same
* ones than in Standby mode.
* @note Stop mode achieves the lowest power consumption while retaining
* the content of SRAM and registers. All clocks in the VCORE domain
* are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and
* the HSE crystal oscillators are disabled. The LSE or LSI is still
* running.
* @note The system clock when exiting from Stop mode can be either MSIS up
* to 24 MHz or HSI16, depending on software configuration.
* @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE
* instruction.
* This parameter can be one of the following values :
* @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait
* For Interrupt request.
* @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait
* For Event request.
* @retval None.
*/
void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry)
{
/* Check the parameter */
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Set Stop mode 3 */
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1));
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Stop mode entry */
if (STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Enter the whole system to Shutdown mode.
* @note Shutdown mode allows the lowest power consumption. The internal
* regulator is switched off so that the VCORE domain is powered off.
* The PLL, the HSI16, the MSI (MSIS and MSIK), the LSI and the HSE
* oscillators are also switched off.
* @note The SRAMs and register contents are lost except for registers in the
* Backup domain. The BOR is not available in Shutdown mode. No power
* voltage monitoring is possible in this mode, therefore the switch to
* Backup domain is not supported.
* @retval None.
*/
void HAL_PWREx_EnterSHUTDOWNMode(void)
{
/* Set Shutdown mode */
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_2));
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* This option is used to ensure that store operations are completed */
#if defined (__CC_ARM)
__force_stores();
#endif /* (__CC_ARM)*/
/* Request Wait For Interrupt */
__WFI();
}
/**
* @brief Configure the SRD domain when the System in Stop 0/1/2 mode.
* @param SRDState : Specifies the SRD state.
* This parameter can be one of the following values :
* @arg PWR_SRD_DOMAIN_STOP : SRD in Stop mode when system
* goes to Stop 0/1/2 mode
* @arg PWR_SRD_DOMAIN_RUN : SRD in Run mode when system
* goes to Stop 0/1/2 mode
* @retval None.
*/
void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState)
{
/* Check the parameter */
assert_param(IS_PWR_SRD_STATE(SRDState));
/* Config the SRD domain */
MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDState);
}
/**
* @brief Enable BOR ultra-low power mode.
* @note BOR operating can be in discontinuous (ultra-low power) mode in
* Stop 1, Stop 2, Stop 3 and Standby modes and when the regulator is
* in Range 4 (Run, Sleep or Stop 0 mode).
* @retval None.
*/
void HAL_PWREx_EnableUltraLowPowerMode(void)
{
SET_BIT(PWR->CR1, PWR_CR1_ULPMEN);
}
/**
* @brief Disable BOR ultra-low power mode.
* @retval None.
*/
void HAL_PWREx_DisableUltraLowPowerMode(void)
{
CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN);
}
/**
* @brief This function handles the PWR Wake up from Stop 3 interrupt request.
* @note This API should be called under the PWR_S3WU_IRQHandler().
* @param WakeUpPin : Specifies the wakeup pin interrupt to be handled.
* This parameter can be a combination of @ref PWR_WakeUp_Pins.
* @retval None.
*/
void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin)
{
/* Check PWR wake up line 1 */
if ((WakeUpPin & PWR_WAKEUP_PIN1) != 0U)
{
if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) != 0U)
{
/* Clear PWR wake up flag line 1 */
SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1);
/* PWR S3WU interrupt user callback */
HAL_PWREx_S3WUCallback(WakeUpPin);
}
}
/* Check PWR wake up line 2 */
if ((WakeUpPin & PWR_WAKEUP_PIN2) != 0U)
{
if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) != 0U)
{
/* Clear PWR wake up flag line 2 */
SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2);
/* PWR S3WU interrupt user callback */
HAL_PWREx_S3WUCallback(WakeUpPin);
}
}
/* Check PWR wake up line 3 */
if ((WakeUpPin & PWR_WAKEUP_PIN3) != 0U)
{
if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) != 0U)
{
/* Clear PWR wake up flag line 3 */
SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3);
/* PWR S3WU interrupt user callback */
HAL_PWREx_S3WUCallback(WakeUpPin);
}
}
/* Check PWR wake up line 4 */
if ((WakeUpPin & PWR_WAKEUP_PIN4) != 0U)
{
if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) != 0U)
{
/* Clear PWR wake up flag line 4 */
SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4);
/* PWR S3WU interrupt user callback */
HAL_PWREx_S3WUCallback(WakeUpPin);
}
}
/* Check PWR wake up line 5 */
if ((WakeUpPin & PWR_WAKEUP_PIN5) != 0U)
{
if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) != 0U)
{
/* Clear PWR wake up flag line 5 */
SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5);
/* PWR S3WU interrupt user callback */
HAL_PWREx_S3WUCallback(WakeUpPin);
}
}
/* Check PWR wake up line 6 */
if ((WakeUpPin & PWR_WAKEUP_PIN6) != 0U)
{
if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) != 0U)
{
/* Clear PWR wake up flag line 6 */
SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6);
/* PWR S3WU interrupt user callback */
HAL_PWREx_S3WUCallback(WakeUpPin);
}
}
/* Check PWR wake up line 7 */
if ((WakeUpPin & PWR_WAKEUP_PIN7) != 0U)
{
if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) != 0U)
{
/* Clear PWR wake up flag line 7 */
SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7);
/* PWR S3WU interrupt user callback */
HAL_PWREx_S3WUCallback(WakeUpPin);
}
}
/* Check PWR wake up line 8 */
if ((WakeUpPin & PWR_WAKEUP_PIN8) != 0U)
{
if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) != 0U)
{
/* Clear PWR wake up flag line 8 */
SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8);
/* PWR S3WU interrupt user callback */
HAL_PWREx_S3WUCallback(WakeUpPin);
}
}
}
/**
* @brief PWR S3WU interrupt callback.
* @param WakeUpPin : Specifies the wakeup pin interrupt to be handled.
* This parameter can be a combination of @ref PWR_WakeUp_Pins.
* @retval None.
*/
__weak void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(WakeUpPin);
/* NOTE : This function should not be modified; when the callback is needed,
HAL_PWREx_S3WU_IRQHandler() API can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions
* @brief Voltage monitoring functions
*
@verbatim
===============================================================================
##### Voltage Monitoring Functions #####
===============================================================================
[..]
This section provides functions allowing voltage monitoring.
*** PVM configuration ***
=========================
[..]
(+) The supplies (VDDA, VDDIO2 and VDDUSB) can be independent from VDD and
can be monitored with four peripheral voltage monitoring (PVM):
(++) The UVM monitors the USB supply VDDUSB. VDDUSBRDY indicates if
the VDDUSB independent power supply is higher or lower than the
VUVM threshold.
(++) The IO2VM monitors the PG[15:2] supply VDDIO2. VDDIO2RDY
indicates if the VDDIO2 independent power supply is higher or
lower than the VIO2VM threshold.
(++) The AVM1 monitors the analog supply VDDA. VDDA1RDY indicates if
the VDDA independent power supply is higher or lower than the
VAVM1 threshold.
(++) The AVM2 monitors the analog supply VDDA. VDDA2RDY indicates if
the VDDA independent power supply is higher or lower than the
VAVM2 threshold.
(+) Each PVM output is connected to an EXTI line and can generate an
interrupt if enabled through the EXTI registers. The PVMx output
interrupt is generated when the independent power supply drops below
the PVM threshold and/or when it rises above the PVM threshold,
depending on EXTI line rising/falling edge configuration.
(+) Each PVM can remain active in Stop 0, Stop 1, Stop 2 modes, and the
PVM interrupt can wake up from the Stop mode. The PVM is not
functional in Stop 3 mode.
*** VBAT charging ***
=====================
[..]
When VDD is present, it is possible to charge the external battery on VBAT
through an internal resistance.
The VBAT charging is done either through a 5 kOhm resistor or through a 1.5
kOhm resistor depending on the VBRS bit value in the PWR_BDCR2 register.
The battery charging is enabled by setting VBE bit in the PWR_BDCR2
register. It is automatically disabled in VBAT mode.
*** Backup domain monitoring ***
================================
[..]
When the Backup domain voltage and temperature monitoring is enabled
(MONEN = 1 in the PWR_BDCR1 register), the Backup domain voltage and the
temperature are monitored.
If the Backup domain voltage monitoring internal tamper is enabled in the
TAMP peripheral (ITAMP1E = 1 in the TAMP_CR1 register), a tamper event is
generated when the Backup domain voltage is above the functional range.
In case the Backup domain voltage is below the functional range,
a Brownout reset is generated, erasing all device including Backup domain.
*** Backup domain battery ***
=============================
[..]
(+) To retain the content of the backup registers and supply the RTC
function when VDD is turned off, the VBAT pin can be connected to an
optional backup voltage supplied by a battery or by another source.
The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to
PC15 I/Os, allowing the RTC to operate even when the main power supply
is turned off. The backup SRAM is optionally powered by VBAT pin when
the BREN bit is set in the PWR Backup domain control register 1
(PWR_BDCR1).
The switch to the VBAT supply is controlled by the power down reset
embedded in the Reset block.
(+) After exiting reset, the USB Type-C (dead battery) behavior is enabled,
which may have a pull-down effect on CC1 and CC2 pins. It is
recommended to disable it in all cases, either to stop this pull-down
or to handover control to the UCPD (the UCPD must be initialized
before doing the disable).
@endverbatim
* @{
*/
/**
* @brief Configure the voltage monitor threshold detected by the Peripheral
* voltage monitoring (PVM).
* @param pConfigPVM : Pointer to a PWR_PVMTypeDef structure that contains the
* PVM configuration information (PVMType and EventMode).
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM)
{
/* Check the PVM parameter */
if (pConfigPVM == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_PWR_PVM_TYPE(pConfigPVM->PVMType));
assert_param(IS_PWR_PVM_MODE(pConfigPVM->Mode));
/* Check the peripheral voltage monitor type */
switch (pConfigPVM->PVMType)
{
case PWR_UVM: /* Independent USB voltage monitor */
/* Disable EXTI UVM event and interrupt */
__HAL_PWR_UVM_EXTI_DISABLE_EVENT();
__HAL_PWR_UVM_EXTI_DISABLE_IT();
__HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE();
__HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE();
/* Configure the UVM in interrupt mode */
if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
{
__HAL_PWR_UVM_EXTI_ENABLE_IT();
}
/* Configure the UVM in event mode */
if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
{
__HAL_PWR_UVM_EXTI_ENABLE_EVENT();
}
/* Configure the UVM in rising edge */
if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
{
__HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE();
}
/* Configure the UVM in falling edge */
if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
{
__HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE();
}
break;
case PWR_IO2VM: /* Independent I/Os voltage monitor */
/* Disable EXTI IO2VM event and interrupt */
__HAL_PWR_IO2VM_EXTI_DISABLE_EVENT();
__HAL_PWR_IO2VM_EXTI_DISABLE_IT();
__HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE();
__HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE();
/* Configure the IO2VM in interrupt mode */
if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
{
__HAL_PWR_IO2VM_EXTI_ENABLE_IT();
}
/* Configure the IO2VM in event mode */
if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
{
__HAL_PWR_IO2VM_EXTI_ENABLE_EVENT();
}
/* Configure the IO2VM in rising edge */
if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
{
__HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE();
}
/* Configure the IO2VM in falling edge */
if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
{
__HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE();
}
break;
case PWR_AVM1: /* VDDA Independent analog supply voltage monitor 1 (1.6V threshold) */
/* Disable EXTI AVM1 event and interrupt */
__HAL_PWR_AVM1_EXTI_DISABLE_EVENT();
__HAL_PWR_AVM1_EXTI_DISABLE_IT();
__HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE();
__HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE();
/* Configure the AVM1 in interrupt mode */
if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
{
__HAL_PWR_AVM1_EXTI_ENABLE_IT();
}
/* Configure the AVM1 in event mode */
if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
{
__HAL_PWR_AVM1_EXTI_ENABLE_EVENT();
}
/* Configure the AVM1 in rising edge */
if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
{
__HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE();
}
/* Configure the AVM1 in falling edge */
if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
{
__HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE();
}
break;
case PWR_AVM2: /* VDDA Independent analog supply voltage monitor 2 (1.8V threshold) */
/* Disable EXTI AVM2 event and interrupt */
__HAL_PWR_AVM2_EXTI_DISABLE_EVENT();
__HAL_PWR_AVM2_EXTI_DISABLE_IT();
__HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE();
__HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE();
/* Configure the AVM2 in interrupt mode */
if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
{
__HAL_PWR_AVM2_EXTI_ENABLE_IT();
}
/* Configure the AVM2 in event mode */
if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
{
__HAL_PWR_AVM2_EXTI_ENABLE_EVENT();
}
/* Configure the AVM2 in rising edge */
if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
{
__HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE();
}
/* Configure the AVM2 in falling edge */
if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
{
__HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE();
}
break;
default: /* No valid voltage monitor selected */
return HAL_ERROR;
break;
}
return HAL_OK;
}
/**
* @brief Enable VDDUSB supply.
* @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply
* is present for consumption saving.
* @retval None.
*/
void HAL_PWREx_EnableVddUSB(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_USV);
}
/**
* @brief Disable VDDUSB supply.
* @retval None.
*/
void HAL_PWREx_DisableVddUSB(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV);
}
/**
* @brief Enable VDDIO2 supply.
* @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply
* is present for consumption saving.
* @retval None.
*/
void HAL_PWREx_EnableVddIO2(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
}
/**
* @brief Disable VDDIO2 supply.
* @retval None.
*/
void HAL_PWREx_DisableVddIO2(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV);
}
/**
* @brief Enable VDDA supply.
* @note Remove VDDA electrical and logical isolation, once VDDA supply is
* present for consumption saving.
* @retval None.
*/
void HAL_PWREx_EnableVddA(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
}
/**
* @brief Disable VDDA supply.
* @retval None.
*/
void HAL_PWREx_DisableVddA(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV);
}
/**
* @brief Enable the UVM Voltage Monitoring : VDDUSB versus 1.2 V.
* @retval None.
*/
void HAL_PWREx_EnableUVM(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
}
/**
* @brief Disable the UVM Voltage Monitoring : VDDUSB versus 1.2 V.
* @retval None.
*/
void HAL_PWREx_DisableUVM(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN);
}
/**
* @brief Enable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V.
* @retval None.
*/
void HAL_PWREx_EnableIO2VM(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
}
/**
* @brief Disable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V.
* @retval None.
*/
void HAL_PWREx_DisableIO2VM(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN);
}
/**
* @brief Enable the AVM1 Voltage Monitoring : VDDA versus 1.6 V.
* @retval None.
*/
void HAL_PWREx_EnableAVM1(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
}
/**
* @brief Disable the AVM1 Voltage Monitoring : VDDA versus 1.6 V.
* @retval None.
*/
void HAL_PWREx_DisableAVM1(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN);
}
/**
* @brief Enable the AVM2 Voltage Monitoring : VDDA versus 1.8 V.
* @retval None.
*/
void HAL_PWREx_EnableAVM2(void)
{
SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
}
/**
* @brief Disable the AVM2 Voltage Monitoring : VDDA versus 1.8 V.
* @retval None.
*/
void HAL_PWREx_DisableAVM2(void)
{
CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN);
}
/**
* @brief Enable the VBAT and temperature monitoring.
* @retval None.
*/
void HAL_PWREx_EnableMonitoring(void)
{
SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
}
/**
* @brief Disable the VBAT and temperature monitoring.
* @retval None.
*/
void HAL_PWREx_DisableMonitoring(void)
{
CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN);
}
#if defined (PWR_VOSR_USBPWREN)
/**
* @brief Enable the internal USB HS transceiver supply.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void)
{
uint32_t vos;
/* Get the system applied voltage scaling range */
vos = HAL_PWREx_GetVoltageRange();
/* Check the system applied voltage scaling range */
if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2))
{
SET_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN));
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Disable the internal USB HS transceiver supply.
* @retval HAL status.
*/
void HAL_PWREx_DisableUSBHSTranceiverSupply(void)
{
CLEAR_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN));
}
#endif /* defined (PWR_VOSR_USBPWREN) */
/**
* @brief Enable UCPD configuration memorization in Standby mode.
* @retval None.
*/
void HAL_PWREx_EnableUCPDStandbyMode(void)
{
SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
}
/**
* @brief Disable UCPD configuration memorization in Standby mode.
* @note This function must be called on exiting the Standby mode and before
* any UCPD configuration update.
* @retval None.
*/
void HAL_PWREx_DisableUCPDStandbyMode(void)
{
CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY);
}
/**
* @brief Enable dead battery behavior.
* @note After exiting reset, the USB Type-C (dead battery) behavior is
* enabled, which may have a pull-down effect on CC1 and CC2 pins.
* It is recommended to disable it in all cases, either to stop this
* pull-down or to handover control to the UCPD (the UCPD must be
* initialized before doing the disable).
* @retval None.
*/
void HAL_PWREx_EnableUCPDDeadBattery(void)
{
CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
}
/**
* @brief Disable dead battery behavior.
* @note After exiting reset, the USB Type-C (dead battery) behavior is
* enabled, which may have a pull-down effect on CC1 and CC2 pins.
* It is recommended to disable it in all cases, either to stop this
* pull-down or to handover control to the UCPD (the UCPD must be
* initialized before doing the disable).
* @retval None.
*/
void HAL_PWREx_DisableUCPDDeadBattery(void)
{
SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
}
/**
* @brief Enable the Battery charging.
* @note When VDD is present, charge the external battery through an internal
* resistor.
* @param ResistorValue : Specifies the charging resistor.
* This parameter can be one of the following values :
* @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
* @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
* @retval None.
*/
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)
{
/* Check the parameter */
assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue));
/* Specify the charging resistor */
MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, ResistorValue);
/* Enable the Battery charging */
SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
}
/**
* @brief Disable the Battery charging.
* @retval None.
*/
void HAL_PWREx_DisableBatteryCharging(void)
{
CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE);
}
/**
* @brief This function handles the PWR PVD/PVM interrupt request.
* @note This API should be called under the PVD_PVM_IRQHandler().
* @retval None.
*/
void HAL_PWREx_PVD_PVM_IRQHandler(void)
{
uint32_t rising_flag;
uint32_t falling_flag;
/* Get pending flags */
rising_flag = READ_REG(EXTI->RPR1);
falling_flag = READ_REG(EXTI->FPR1);
/* Check PWR exti flags for PVD */
if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PVD exti pending bit */
WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
}
/* Check PWR exti flags for UVM */
if (((rising_flag | falling_flag) & PWR_EXTI_LINE_UVM) != 0U)
{
/* PWR UVM interrupt user callback */
HAL_PWREx_UVMCallback();
/* Clear UVM exti pending bit */
WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM);
WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM);
}
/* Check PWR exti flags for IO2VM */
if (((rising_flag | falling_flag) & PWR_EXTI_LINE_IO2VM) != 0U)
{
/* PWR IO2VM interrupt user callback */
HAL_PWREx_IO2VMCallback();
/* Clear IO2VM exti pending bit */
WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM);
WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM);
}
/* Check PWR exti flags for AVM1 */
if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM1) != 0U)
{
/* PWR AVM1 interrupt user callback */
HAL_PWREx_AVM1Callback();
/* Clear AVM1 exti pending bit */
WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1);
WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1);
}
/* Check PWR exti flags for AVM2 */
if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM2) != 0U)
{
/* PWR AVM2 interrupt user callback */
HAL_PWREx_AVM2Callback();
/* Clear AVM2 exti pending bit */
WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2);
WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2);
}
}
/**
* @brief PWR UVM interrupt callback.
* @retval None.
*/
__weak void HAL_PWREx_UVMCallback(void)
{
/* NOTE : This function should not be modified; when the callback is needed,
HAL_PWREx_UVMCallback() API can be implemented in the user file
*/
}
/**
* @brief PWR IO2VM interrupt callback.
* @retval None.
*/
__weak void HAL_PWREx_IO2VMCallback(void)
{
/* NOTE : This function should not be modified; when the callback is needed,
HAL_PWREx_IO2VMCallback() API can be implemented in the user file
*/
}
/**
* @brief PWR AVM1 interrupt callback.
* @retval None.
*/
__weak void HAL_PWREx_AVM1Callback(void)
{
/* NOTE : This function should not be modified; when the callback is needed,
HAL_PWREx_AVM1Callback() API can be implemented in the user file
*/
}
/**
* @brief PWR AVM2 interrupt callback.
* @retval None.
*/
__weak void HAL_PWREx_AVM2Callback(void)
{
/* NOTE : This function should not be modified; when the callback is needed,
HAL_PWREx_AVM2Callback() API can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions
* @brief Memories retention functions
*
@verbatim
===============================================================================
##### Memories Retention Functions #####
===============================================================================
[..]
Several STM32U5 devices RAMs are configurable to keep / lose RAMs content
during Stop mode (Stop 0/1/2/3).
(+) Retained content RAMs in Stop modes are :
(++) SRAM1
(++) SRAM2
(++) SRAM3
(++) SRAM4
(++) ICACHE
(++) DMA2DRAM
(++) PKA32RAM
(++) DCACHE
(++) FMAC
(++) FDCAN
(++) USB
[..]
Several STM32U5 devices RAMs are configurable to keep / lose RAMs content
during Run mode.
(+) Retained content RAMs in Run modes are :
(++) SRAM1
(++) SRAM2
(++) SRAM3
(++) SRAM4
[..]
SRAM2 is configurable to keep / lose its content in Stop 3 and Standby
modes. The SRAM2 retention feature granularity is at pages level.
[..]
BKPRAM is configurable to keep / lose its content in Standby, Shutdown and
VBAT modes.
@endverbatim
* @{
*/
/**
* @brief Enable SRAM2 page(s) content retention in Stop 3 and Standby mode.
* @note When RRSx bit is set, SRAM2 is powered by the low-power regulator in
* Stop 3 and Standby mode and its content is kept.
* @param SRAM2Pages : Specifies the SRAM2 pages.
* This parameter can be one of the following values :
* @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention.
* @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention.
* @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention.
* @retval None.
*/
void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
{
/* Check the parameters */
assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages));
/* Set RRSx bit(s) */
SET_BIT(PWR->CR1, SRAM2Pages);
}
/**
* @brief Disable SRAM2 page(s) content retention in Stop 3 and Standby mode.
* @note When RRSx bit is reset, SRAM2 is powered off in Stop 3 and Standby
* mode and its content is lost.
* @param SRAM2Pages : Specifies the SRAM2 pages.
* This parameter can be one of the following values :
* @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention.
* @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention.
* @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention.
* @retval None.
*/
void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages)
{
/* Check the parameters */
assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages));
/* Clear RRSx bit(s) */
CLEAR_BIT(PWR->CR1, SRAM2Pages);
}
/**
* @brief Enable RAM page(s) content retention in Stop mode (Stop 0, 1, 2, 3).
* @note When enabling content retention for a given RAM, memory kept powered
* in Stop mode. (Not optimized power consumption)
* @param RAMSelection: Specifies RAM page(s) to be retained in Stop mode.
* This parameter can be one or a combination of the same
* memory @ref PWREx_RAM_Contents_Stop_Retention.
* @retval None.
*/
void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection)
{
uint32_t dummy;
/* Check RAM ID */
switch (RAMSelection & SRAM_ID_MASK)
{
/* SRAM 1 Stop retention */
case SRAM1_ID:
{
/* Check the parameters */
assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID);
CLEAR_BIT(PWR->CR2, dummy);
#if defined (PWR_CR4_SRAM1PDS4)
/* Calculate pages mask */
dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U;
CLEAR_BIT(PWR->CR4, dummy);
#endif /* defined (PWR_CR4_SRAM1PDS4) */
break;
}
/* SRAM 2 Stop retention */
case SRAM2_ID:
{
/* Check the parameters */
assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos));
break;
}
/* SRAM 3 Stop retention */
case SRAM3_ID:
{
/* Check the parameters */
assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID);
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos));
#if defined (PWR_CR4_SRAM3PDS9)
/* Calculate pages mask */
dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U;
CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos));
#endif /* defined (PWR_CR4_SRAM3PDS9) */
break;
}
/* SRAM 4 Stop retention */
case SRAM4_ID:
{
/* Check the parameters */
assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos));
break;
}
/* ICACHE RAM Stop retention */
case ICACHERAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_ICRAMPDS_Pos);
break;
}
/* DCACHE1 RAM Stop retention */
case DCACHE1RAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_DC1RAMPDS_Pos);
break;
}
/* DMA2D RAM Stop retention */
case DMA2DRAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos));
break;
}
/* FMAC, FDCAN and USB RAM Stop retention */
case PERIPHRAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos));
break;
}
/* PKA32 RAM Stop retention */
case PKARAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos));
break;
}
#if defined (PWR_CR2_DC2RAMPDS)
/* DCACHE2 RAM Stop retention */
case DCACHE2RAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos));
break;
}
#endif /* defined (PWR_CR2_DC2RAMPDS) */
#if defined (PWR_CR2_GPRAMPDS)
/* LTDC and GFXMMU RAM Stop retention */
case GRAPHIPRAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos));
break;
}
#endif /* defined (PWR_CR2_GPRAMPDS) */
#if defined (PWR_CR2_DSIRAMPDS)
/* DSI RAM Stop retention */
case DSIRAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK;
CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos));
break;
}
#endif /* defined (PWR_CR2_DSIRAMPDS) */
#if defined (PWR_CR4_SRAM5PDS1)
/* SRAM 5 Stop retention */
case SRAM5_ID:
{
/* Check the parameters */
assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK);
CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos));
break;
}
#endif /* defined (PWR_CR4_SRAM5PDS1) */
default:
{
return;
break;
}
}
}
/**
* @brief Disable RAM page(s) content lost in Stop mode (Stop 0, 1, 2, 3).
* @note When disabling content lost for a given RAM, memory powered down
* in Stop mode. (Optimized power consumption)
* @param RAMSelection: Specifies RAM page(s) to be lost in Stop mode.
* This parameter can be one or a combination of the same
* memory @ref PWREx_RAM_Contents_Stop_Retention.
* @retval None.
*/
void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection)
{
uint32_t dummy;
/* Check RAM ID */
switch (RAMSelection & SRAM_ID_MASK)
{
/* SRAM 1 Stop retention */
case SRAM1_ID:
{
/* Check the parameters */
assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID);
SET_BIT(PWR->CR2, dummy);
#if defined (PWR_CR4_SRAM1PDS4)
/* Calculate pages mask */
dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U;
SET_BIT(PWR->CR4, dummy);
#endif /* defined (PWR_CR4_SRAM1PDS4) */
break;
}
/* SRAM 2 Stop retention */
case SRAM2_ID:
{
/* Check the parameters */
assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos));
break;
}
/* SRAM 3 Stop retention */
case SRAM3_ID:
{
/* Check the parameters */
assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID);
SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos));
#if defined (PWR_CR4_SRAM3PDS9)
/* Calculate pages mask */
dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID |
PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U;
SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos));
#endif /* defined (PWR_CR4_SRAM3PDS9) */
break;
}
/* SRAM 4 Stop retention */
case SRAM4_ID:
{
/* Check the parameters */
assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos));
break;
}
/* ICACHE RAM Stop retention */
case ICACHERAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_ICRAMPDS_Pos));
break;
}
/* DCACHE1 RAM Stop retention */
case DCACHE1RAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC1RAMPDS_Pos));
break;
}
/* DMA2D RAM Stop retention */
case DMA2DRAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos));
break;
}
/* FMAC, FDCAN and USB RAM Stop retention */
case PERIPHRAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos));
break;
}
/* PKA32 RAM Stop retention */
case PKARAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos));
break;
}
#if defined (PWR_CR2_DC2RAMPDS)
/* DCACHE2 RAM Stop retention */
case DCACHE2RAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos));
break;
}
#endif /* defined (PWR_CR2_DC2RAMPDS) */
#if defined (PWR_CR2_GPRAMPDS)
/* LTDC and GFXMMU RAM Stop retention */
case GRAPHIPRAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos));
break;
}
#endif /* defined (PWR_CR2_GPRAMPDS) */
#if defined (PWR_CR2_DSIRAMPDS)
/* DSI RAM Stop retention */
case DSIRAM_ID:
{
/* Check the parameters */
assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK;
SET_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos));
break;
}
#endif /* defined (PWR_CR2_DSIRAMPDS) */
#if defined (PWR_CR4_SRAM5PDS1)
/* SRAM 5 Stop retention */
case SRAM5_ID:
{
/* Check the parameters */
assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection));
/* Calculate pages mask */
dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK);
SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos));
break;
}
#endif /* defined (PWR_CR4_SRAM5PDS1) */
default:
{
return;
break;
}
}
}
/**
* @brief Enable RAMs full content retention in Run mode.
* @param RAMSelection : Specifies the SRAM content to be retained in Run mode.
* This parameter can be one or a combination of the following values :
* @arg PWR_SRAM1_FULL_RUN : SRAM1 full content retention.
* @arg PWR_SRAM2_FULL_RUN : SRAM2 full content retention.
* @arg PWR_SRAM3_FULL_RUN : SRAM3 full content retention.
* @arg PWR_SRAM4_FULL_RUN : SRAM4 full content retention.
* @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for
* STM32U59xxx and STM32U5Axxx devices).
* @retval None.
*/
void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection)
{
/* Check the parameters */
assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection));
/* Enable RAM retention in Run mode */
CLEAR_BIT(PWR->CR1, RAMSelection);
}
/**
* @brief Disable RAMs full content retention in Run mode.
* @param RAMSelection : Specifies the SRAM content to be lost in Run mode.
* This parameter can be one or a combination of the following values :
* @arg PWR_SRAM1_FULL_RUN : SRAM1 full content lost.
* @arg PWR_SRAM2_FULL_RUN : SRAM2 full content lost.
* @arg PWR_SRAM3_FULL_RUN : SRAM3 full content lost.
* @arg PWR_SRAM4_FULL_RUN : SRAM4 full content lost.
* @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for
* STM32U59xxx and STM32U5Axxx devices).
* @retval None.
*/
void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection)
{
/* Check the parameters */
assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection));
/* Disable RAM retention in Run mode */
SET_BIT(PWR->CR1, RAMSelection);
}
/**
* @brief Enable the Backup RAM retention in Standby, Shutdown and VBAT modes.
* @note If BREN is reset, the backup RAM can still be used in Run, Sleep and
* Stop modes. However, its content is lost in Standby, Shutdown and
* VBAT modes.
* @note This bit can be enabled only when LDO regulator is selected as
* source supply.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void)
{
/*
Backup RAM retention in Standby, Shutdown and VBAT should be enabled
when the Vcore is alimented by the LDO regulator
*/
if (HAL_PWREx_GetSupplyConfig() == PWR_LDO_SUPPLY)
{
SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
}
/* SMPS regulator selected */
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Disable the Backup RAM retention in Standby, Shutdown and VBAT modes.
* @note If BREN is reset, the backup RAM can still be used in Run, Sleep and
* Stop modes. However, its content is lost in Standby, Shutdown and
* VBAT modes. This bit can be writte
* @retval None.
*/
void HAL_PWREx_DisableBkupRAMRetention(void)
{
CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN);
}
/**
* @brief Enable the flash memory fast wakeup from Stop 0 and Stop 1 modes.
* @note This feature is used to obtain the best trade-off between low-power
* consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
* When this feature is enabled, the Flash memory remains in normal
* mode in Stop 0 and Stop 1 modes, which offers a faster startup time
* with higher consumption.
* @retval None.
*/
void HAL_PWREx_EnableFlashFastWakeUp(void)
{
SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
}
/**
* @brief Disable the Flash Power Down in Stop mode.
* @note This feature is used to obtain the best trade-off between low-power
* consumption and wakeup time when exiting the Stop 0 or Stop 1 modes.
* When this feature is disabled, the Flash memory enters low-power
* mode in Stop 0 and Stop 1 modes, which causes a slower startup time
* with lower consumption.
* @retval None.
*/
void HAL_PWREx_DisableFlashFastWakeUp(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU);
}
/**
* @brief Enable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes.
* @note This bit is used to obtain the best trade-off between low-power consumption
* and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting
* Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time
* to SRAM4 during Stop modes.
* @retval None.
*/
void HAL_PWREx_EnableSRAM4FastWakeUp(void)
{
SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
}
/**
* @brief Disable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes.
* @note This bit is used to obtain the best trade-off between low-power consumption
* and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting
* Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time
* to SRAM4 during Stop modes.
* @retval None.
*/
void HAL_PWREx_DisableSRAM4FastWakeUp(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU);
}
/**
* @}
*/
/** @defgroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions
* @brief I/O pull-up / pull-down configuration functions
*
@verbatim
===============================================================================
##### Voltage monitoring Functions #####
===============================================================================
[..]
In Standby and Shutdown mode, pull up and pull down can be configured to
maintain an I/O in the selected state. If the APC bit in the PWR_APCR
register is set, the I/Os can be configured either with a pull-up through
PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I,J), or with a pull-down through
PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I,J)), or can be kept in analog state
if none of the PWR_PUCRx or PWR_PDCRx register is set.
(+) Port J is available only for STM32U59xxx and STM32U5Axxx devices.
[..]
The pull-down configuration has highest priority over pull-up
configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same
I/O.
This configuration is lost when exiting the Shutdown but not from Standby
mode.
@endverbatim
* @{
*/
/**
* @brief Enable pull-up and pull-down configuration.
* @note When APC bit is set, the I/O pull-up and pull-down configurations
* defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby
* and Shutdown modes.
* @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the
* corresponding PDy bit of PWR_PDCRx register is also set (pull-down
* configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and
* HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict
* when setting PUy or PDy bit.
* @retval None.
*/
void HAL_PWREx_EnablePullUpPullDownConfig(void)
{
SET_BIT(PWR->APCR, PWR_APCR_APC);
}
/**
* @brief Disable pull-up and pull-down configuration.
* @note When APC bit is cleared, the I/O pull-up and pull-down configurations
* defined in PWR_PUCRx and PWR_PDCRx registers are not applied in
* Standby and Shutdown modes.
* @retval None.
*/
void HAL_PWREx_DisablePullUpPullDownConfig(void)
{
CLEAR_BIT(PWR->APCR, PWR_APCR_APC);
}
/**
* @brief Enable GPIO pull-up state in Standby and Shutdown modes.
* @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O
* in pull-up state in Standby and Shutdown modes.
* @note This state is effective in Standby and Shutdown modes only if APC
* bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
* @note The configuration is lost when exiting the Shutdown mode due to the
* power-on reset, maintained when exiting the Standby mode.
* @note To avoid any conflict at Standby and Shutdown modes exits, the
* corresponding PDy bit of PWR_PDCRx register is cleared unless it is
* reserved.
* @note Even if a PUy bit to set is reserved, the other PUy bits entered as
* input parameter at the same time are set.
* @param GPIO_Port : Specify the IO port.
* This parameter can be a value of
* @ref PWREx_GPIO_Port.
* @param GPIO_Pin : Specify the I/O pins numbers.
* This parameter can be a value of
* @ref PWREx_GPIO_Pin_Mask.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
/* Check GPIO port */
switch (GPIO_Port)
{
case PWR_GPIO_A: /* Apply Pull Up to GPIO port A */
SET_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
break;
case PWR_GPIO_B: /* Apply Pull Up to GPIO port B */
SET_BIT(PWR->PUCRB, GPIO_Pin);
CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
break;
case PWR_GPIO_C: /* Apply Pull Up to GPIO port C */
SET_BIT(PWR->PUCRC, GPIO_Pin);
CLEAR_BIT(PWR->PDCRC, GPIO_Pin);
break;
case PWR_GPIO_D: /* Apply Pull Up to GPIO port D */
SET_BIT(PWR->PUCRD, GPIO_Pin);
CLEAR_BIT(PWR->PDCRD, GPIO_Pin);
break;
case PWR_GPIO_E: /* Apply Pull Up to GPIO port E */
SET_BIT(PWR->PUCRE, GPIO_Pin);
CLEAR_BIT(PWR->PDCRE, GPIO_Pin);
break;
case PWR_GPIO_F: /* Apply Pull Up to GPIO port F */
SET_BIT(PWR->PUCRF, GPIO_Pin);
CLEAR_BIT(PWR->PDCRF, GPIO_Pin);
break;
case PWR_GPIO_G: /* Apply Pull Up to GPIO port G */
SET_BIT(PWR->PUCRG, GPIO_Pin);
CLEAR_BIT(PWR->PDCRG, GPIO_Pin);
break;
case PWR_GPIO_H: /* Apply Pull Up to GPIO port H */
SET_BIT(PWR->PUCRH, GPIO_Pin);
CLEAR_BIT(PWR->PDCRH, GPIO_Pin);
break;
case PWR_GPIO_I: /* Apply Pull Up to GPIO port I */
SET_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
break;
#if defined (PWR_PUCRJ_PU0)
case PWR_GPIO_J: /* Apply Pull Up to GPIO port J */
SET_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
break;
#endif /* defined (PWR_PUCRJ_PU0) */
default:
return HAL_ERROR;
break;
}
return HAL_OK;
}
/**
* @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
* @note Reset the relevant PUy bits of PWR_PUCRx register used to configure
* the I/O in pull-up state in Standby and Shutdown modes.
* @note Even if a PUy bit to reset is reserved, the other PUy bits entered as
* input parameter at the same time are reset.
* @param GPIO_Port : Specify the IO port.
* This parameter can be a value of
* @ref PWREx_GPIO_Port.
* @param GPIO_Pin : Specify the I/O pins numbers.
* This parameter can be a value of
* @ref PWREx_GPIO_Pin_Mask.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
/* Check GPIO port */
switch (GPIO_Port)
{
case PWR_GPIO_A: /* Disable Pull Up for GPIO port A */
CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
break;
case PWR_GPIO_B: /* Disable Pull Up for GPIO port B */
CLEAR_BIT(PWR->PUCRB, GPIO_Pin);
break;
case PWR_GPIO_C: /* Disable Pull Up for GPIO port C */
CLEAR_BIT(PWR->PUCRC, GPIO_Pin);
break;
case PWR_GPIO_D: /* Disable Pull Up for GPIO port D */
CLEAR_BIT(PWR->PUCRD, GPIO_Pin);
break;
case PWR_GPIO_E: /* Disable Pull Up for GPIO port E */
CLEAR_BIT(PWR->PUCRE, GPIO_Pin);
break;
case PWR_GPIO_F: /* Disable Pull Up for GPIO port F */
CLEAR_BIT(PWR->PUCRF, GPIO_Pin);
break;
case PWR_GPIO_G: /* Disable Pull Up for GPIO port G */
CLEAR_BIT(PWR->PUCRG, GPIO_Pin);
break;
case PWR_GPIO_H: /* Disable Pull Up for GPIO port H */
CLEAR_BIT(PWR->PUCRH, GPIO_Pin);
break;
case PWR_GPIO_I: /* Disable Pull Up for GPIO port I */
CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
break;
#if defined (PWR_PUCRJ_PU0)
case PWR_GPIO_J: /* Disable Pull Up for GPIO port J */
CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
break;
#endif /* defined (PWR_PUCRJ_PU0) */
default:
return HAL_ERROR;
break;
}
return HAL_OK;
}
/**
* @brief Enable GPIO pull-down state in Standby and Shutdown modes.
* @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O
* in pull-down state in Standby and Shutdown modes.
* @note This state is effective in Standby and Shutdown modes only if APC bit
* is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
* @note The configuration is lost when exiting the Shutdown mode due to the
* power-on reset, maintained when exiting the Standby mode.
* @note To avoid any conflict at Standby and Shutdown modes exits, the
* corresponding PUy bit of PWR_PUCRx register is cleared unless it is
* reserved.
* @note Even if a PDy bit to set is reserved, the other PDy bits entered as
* input parameter at the same time are set.
* @param GPIO_Port : Specify the IO port.
* This parameter can be a value of
* @ref PWREx_GPIO_Port.
* @param GPIO_Pin : Specify the I/O pins numbers.
* This parameter can be a value of
* @ref PWREx_GPIO_Pin_Mask.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
/* Check GPIO port */
switch (GPIO_Port)
{
case PWR_GPIO_A: /* Apply Pull Down to GPIO port A */
SET_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14))));
break;
case PWR_GPIO_B: /* Apply Pull Down to GPIO port B */
SET_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
CLEAR_BIT(PWR->PUCRB, GPIO_Pin);
break;
case PWR_GPIO_C: /* Apply Pull Down to GPIO port C */
SET_BIT(PWR->PDCRC, GPIO_Pin);
CLEAR_BIT(PWR->PUCRC, GPIO_Pin);
break;
case PWR_GPIO_D: /* Apply Pull Down to GPIO port D */
SET_BIT(PWR->PDCRD, GPIO_Pin);
CLEAR_BIT(PWR->PUCRD, GPIO_Pin);
break;
case PWR_GPIO_E: /* Apply Pull Down to GPIO port E */
SET_BIT(PWR->PDCRE, GPIO_Pin);
CLEAR_BIT(PWR->PUCRE, GPIO_Pin);
break;
case PWR_GPIO_F: /* Apply Pull Down to GPIO port F */
SET_BIT(PWR->PDCRF, GPIO_Pin);
CLEAR_BIT(PWR->PUCRF, GPIO_Pin);
break;
case PWR_GPIO_G: /* Apply Pull Down to GPIO port G */
SET_BIT(PWR->PDCRG, GPIO_Pin);
CLEAR_BIT(PWR->PUCRG, GPIO_Pin);
break;
case PWR_GPIO_H: /* Apply Pull Down to GPIO port H */
SET_BIT(PWR->PDCRH, GPIO_Pin);
CLEAR_BIT(PWR->PUCRH, GPIO_Pin);
break;
case PWR_GPIO_I: /* Apply Pull Down to GPIO port I */
SET_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
break;
#if defined (PWR_PUCRJ_PU0)
case PWR_GPIO_J: /* Apply Pull Down to GPIO port J */
SET_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
break;
#endif /* defined (PWR_PUCRJ_PU0) */
default:
return HAL_ERROR;
break;
}
return HAL_OK;
}
/**
* @brief Disable GPIO pull-down state in Standby and Shutdown modes.
* @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
* in pull-down state in Standby and Shutdown modes.
* @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
* parameter at the same time are reset.
* @param GPIO_Port : Specify the IO port.
* This parameter can be a value of
* @ref PWREx_GPIO_Port.
* @param GPIO_Pin : Specify the I/O pins numbers.
* This parameter can be a value of
* @ref PWREx_GPIO_Pin_Mask.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_PWR_GPIO_PORT(GPIO_Port));
assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin));
/* Check GPIO port */
switch (GPIO_Port)
{
case PWR_GPIO_A: /* Disable Pull Down for GPIO port A */
CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15))));
break;
case PWR_GPIO_B: /* Disable Pull Down for GPIO port B */
CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4))));
break;
case PWR_GPIO_C: /* Disable Pull Down for GPIO port C */
CLEAR_BIT(PWR->PDCRC, GPIO_Pin);
break;
case PWR_GPIO_D: /* Disable Pull Down for GPIO port D */
CLEAR_BIT(PWR->PDCRD, GPIO_Pin);
break;
case PWR_GPIO_E: /* Disable Pull Down for GPIO port E */
CLEAR_BIT(PWR->PDCRE, GPIO_Pin);
break;
case PWR_GPIO_F: /* Disable Pull Down for GPIO port F */
CLEAR_BIT(PWR->PDCRF, GPIO_Pin);
break;
case PWR_GPIO_G: /* Disable Pull Down for GPIO port G */
CLEAR_BIT(PWR->PDCRG, GPIO_Pin);
break;
case PWR_GPIO_H: /* Disable Pull Down for GPIO port H */
CLEAR_BIT(PWR->PDCRH, GPIO_Pin);
break;
case PWR_GPIO_I: /* Disable Pull Down for GPIO port I */
CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS));
break;
#if defined (PWR_PUCRJ_PU0)
case PWR_GPIO_J: /* Disable Pull Down for GPIO port J */
CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS));
break;
#endif /* defined (PWR_PUCRJ_PU0) */
default:
return HAL_ERROR;
break;
}
return HAL_OK;
}
/**
* @}
*/
#endif /* defined (HAL_PWR_MODULE_ENABLED) */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c
|
C
|
apache-2.0
| 88,892
|
/**
******************************************************************************
* @file stm32u5xx_hal_ramcfg.c
* @author MCD Application Team
* @brief RAMCFG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the RAMs configuration controller peripheral:
* + RAMCFG Initialization and De-initialization Functions.
* + RAMCFG ECC Operation Functions.
* + RAMCFG Configure Wait State Functions.
* + RAMCFG Write Protection Functions.
* + RAMCFG Erase Operation Functions.
* + RAMCFG Handle Interrupt and Callbacks Functions.
* + RAMCFG State and Error Functions.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### RAMCFG Peripheral features #####
==============================================================================
[..]
(+) Each SRAM is managed by a RAMCFG instance.
(+) Each SRAM can be erased independently through its RAMCFG instance.
(+) The wait state value for each SRAM can be configured independently
through its RAMCFG instance.
(+) SRAM2 is divided to 64 pages with 1 kB granularity. Each page can be
write protected independently through its RAMCFG instance.
(+) SRAM2, SRAM3 and BKPRAM support ECC correction feature. This mechanism
adopts the Single Error Correction Double Error Detection (SECDED)
algorithm. This feature provides the following information:
(++) Single error address.
(++) Double error address.
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Call HAL_RAMCFG_Init() to initialize the RAMCFG peripheral before using
any feature. Call HAL_RAMCFG_DeInit() to de-initialize the RAMCFG when
using this peripheral is no more needed or a hardware issue has occurred.
*** ECC feature ***
===================
[..]
(+) Call HAL_RAMCFG_StartECC() and HAL_RAMCFG_StopECC() to enable and
disable ECC hardware process.
(+) Call HAL_RAMCFG_EnableNotification() and HAL_RAMCFG_DisableNotification()
to enable and disable ECC interrupts. Interrupts can be :
(++) Single error interrupt.
(++) Double error interrupt.
(++) Double error interrupt redirected to Non masKable
interrupt (NMI).
(+) Call HAL_RAMCFG_GetSingleErrorAddress() to get the address of the
last fail RAM word detected (only for single error) and
call HAL_RAMCFG_GetDoubleErrorAddress() to get the address of the
last fail RAM word detected (only for double error).
(+) Call HAL_RAMCFG_IsECCErrorDetected() to check if an ECC single/double
error was detected. This API is used in silent mode (No ECC interrupt
is enabled).
*** Wait State feature ***
==========================
[..]
(+) Call HAL_RAMCFG_ConfigWaitState() to configure the wait state value
for a given SRAM according to the HCLK frequency and voltage range
scaling.
(+) Call HAL_RAMCFG_GetWaitState() to get the current configured wait
state value.
*** Write protection feature ***
================================
[..]
(+) Call HAL_RAMCFG_EnableWriteProtection() to enable the write
protection for the given SRAM2 page(s).
(+) There is no API to disable write protection as this feature can
be disabled only by a global peripheral reset or system reset.
(+) Any write access to a write protected area of SRAM2 causes a
HardFault interrupt.
*** Erase feature ***
=====================
[..]
(+) Call HAL_RAMCFG_Erase() to launch a hardware erase for the given
SRAM.
(+) The erase value is equal to 0 when launching erase hardware through
RAMCFG.
(+) SRAM2 write protected pages are erased when performing an erase
through RAMCFG.
*** RAMCFG HAL driver macros list ***
=====================================
[..]
Below the list of used macros in RAMCFG HAL driver.
(+) __HAL_RAMCFG_ENABLE_IT : Enable the specified RAMCFG interrupts.
(+) __HAL_RAMCFG_DISABLE_IT : Disable the specified RAMCFG interrupts.
(+) __HAL_RAMCFG_GET_FLAG : Get the RAMCFG pending flags.
(+) __HAL_RAMCFG_CLEAR_FLAG : Clear the RAMCFG pending flags.
(+) __HAL_RAMCFG_GET_IT_SOURCE : Check whether the specified RAMCFG
interrupt source is enabled or not.
@endverbatim
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32u5xx_hal.h"
/** @addtogroup STM32U5xx_HAL_Driver
* @{
*/
/** @defgroup RAMCFG RAMCFG
* @brief RAMCFG HAL module driver
* @{
*/
#ifdef HAL_RAMCFG_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup RAMCFG_Private_Constants
* @{
*/
#define RAMCFG_TIMEOUT_VALUE 50000U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RAMCFG_Exported_Functions
* @{
*/
/** @addtogroup RAMCFG_Exported_Functions_Group1
*
@verbatim
===============================================================================
##### Initialization and de-initialization Functions #####
===============================================================================
[..]
This section provides functions allowing to initialize and de-initialize the
RAMCFG instance.
[..]
The HAL_RAMCFG_Init() function follows the RAMCFG instance configuration
procedures as described in the reference manual.
The HAL_RAMCFG_DeInit() function allows to deinitialize the RAMCFG instance.
@endverbatim
* @{
*/
/**
* @brief Initialize the RAMCFG by clearing flags and disabling interrupts.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
* the configuration information for the specified RAMCFG
* instance.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg)
{
/* Check the RAMCFG peripheral handle */
if (hramcfg == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
/* Update RAMCFG peripheral state */
hramcfg->State = HAL_RAMCFG_STATE_BUSY;
#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
/* Check if a valid MSP API was registered */
if (hramcfg->MspInitCallback == NULL)
{
/* Init the low level hardware */
hramcfg->MspInitCallback = HAL_RAMCFG_MspInit;
}
/* Init the low level hardware */
hramcfg->MspInitCallback(hramcfg);
#else
HAL_RAMCFG_MspInit(hramcfg);
#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
/* Unlock the SRAM ECC enable bit and disable the ECC feature */
WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY1);
WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY2);
hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
/* Disable all RAMCFG interrupts */
__HAL_RAMCFG_DISABLE_IT(hramcfg, RAMCFG_IT_ALL);
/* Clear RAMCFG monitor flags */
__HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAGS_ALL);
/* Initialise the RAMCFG error code */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE;
/* Initialize the RAMCFG state */
hramcfg->State = HAL_RAMCFG_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitialize the RAMCFG peripheral.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
* the configuration information for the specified RAMCFG
* instance.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_DeInit(RAMCFG_HandleTypeDef *hramcfg)
{
/* Check the RAMCFG peripheral handle */
if (hramcfg == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
/* Unlock the SRAM ECC enable bit and disable the ECC feature */
WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY1);
WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY2);
hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
/* Disable all RAMCFG interrupts */
__HAL_RAMCFG_DISABLE_IT(hramcfg, RAMCFG_IT_ALL);
/* Clear RAMCFG monitor flags */
__HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAGS_ALL);
#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
/* Check if a valid MSP API was registered */
if (hramcfg->MspDeInitCallback != NULL)
{
/* Init the low level hardware */
hramcfg->MspDeInitCallback(hramcfg);
}
/* Clean callbacks */
hramcfg->DetectSingleErrorCallback = NULL;
hramcfg->DetectDoubleErrorCallback = NULL;
#else
HAL_RAMCFG_MspDeInit(hramcfg);
#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
/* Reset the RAMCFG error code */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE;
/* Reset the RAMCFG state */
hramcfg->State = HAL_RAMCFG_STATE_RESET;
return HAL_OK;
}
/**
* @brief Initialize the RAMCFG MSP.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
* the configuration information for the specified RAMCFG.
* @retval None.
*/
__weak void HAL_RAMCFG_MspInit(RAMCFG_HandleTypeDef *hramcfg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hramcfg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_RAMCFG_MspInit can be implemented in the user file */
}
/**
* @brief DeInitialize the RAMCFG MSP.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
* the configuration information for the specified RAMCFG.
* @retval None.
*/
__weak void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hramcfg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_RAMCFG_MspDeInit can be implemented in the user file */
}
/**
* @}
*/
/** @addtogroup RAMCFG_Exported_Functions_Group2
*
@verbatim
===============================================================================
##### ECC Operations Functions #####
===============================================================================
[..]
This section provides functions allowing to manage ECC feature provided by
the RAMCFG peripheral.
[..]
The HAL_RAMCFG_StartECC() function allows enabling and starting the ECC
mechanism for the selected RAMCFG instance.
The HAL_RAMCFG_StopECC() function allows disabling and stopping the ECC
mechanism for the selected RAMCFG instance.
The HAL_RAMCFG_EnableNotification() function allows enabling interrupts
for single ECC error, double ECC error and NMI error.
The HAL_RAMCFG_DisableNotification() function allows disabling interrupts
for single ECC error, double ECC error. When NMI interrupt is enabled it
can only be disabled by a global peripheral reset or by a system reset.
The HAL_RAMCFG_IsECCErrorDetected() function allows to check if an ECC error
has occurred.
The HAL_RAMCFG_GetSingleErrorAddress() function allows to get the address of
the last single ECC error detected.
The HAL_RAMCFG_GetDoubleErrorAddress() function allows to get the address of
the last double ECC error detected.
@endverbatim
* @{
*/
/**
* @brief Start ECC mechanism for the given SRAM.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
* the configuration information for the specified RAMCFG
* instance.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_StartECC(RAMCFG_HandleTypeDef *hramcfg)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
/* Check RAMCFG state */
if (hramcfg->State == HAL_RAMCFG_STATE_READY)
{
/* Update RAMCFG peripheral state */
hramcfg->State = HAL_RAMCFG_STATE_BUSY;
/* Check if ECC mechanism is active */
if ((hramcfg->Instance->CR & RAMCFG_CR_ECCE) != RAMCFG_CR_ECCE)
{
/* Start the SRAM ECC mechanism and latching the error address */
hramcfg->Instance->CR |= (RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
/* Update the RAMCFG state */
hramcfg->State = HAL_RAMCFG_STATE_READY;
}
}
else
{
/* Update the RAMCFG error code and return error */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Stop ECC mechanism for the given SRAM.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
* the configuration information for the specified RAMCFG
* instance.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_StopECC(RAMCFG_HandleTypeDef *hramcfg)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
/* Check RAMCFG state */
if (hramcfg->State == HAL_RAMCFG_STATE_READY)
{
/* Update RAMCFG peripheral state */
hramcfg->State = HAL_RAMCFG_STATE_BUSY;
/* Check if ECC mechanism is active */
if ((hramcfg->Instance->CR & RAMCFG_CR_ECCE) == RAMCFG_CR_ECCE)
{
/* Unlock the SRAM ECC bit */
WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY1);
WRITE_REG(hramcfg->Instance->ECCKEY, RAMCFG_ECC_KEY2);
/* Start the SRAM ECC mechanism and latching the error address */
hramcfg->Instance->CR &= ~(RAMCFG_CR_ECCE | RAMCFG_CR_ALE);
/* Update the RAMCFG state */
hramcfg->State = HAL_RAMCFG_STATE_READY;
}
}
else
{
/* Update the RAMCFG error code and return error */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Enable the RAMCFG error interrupts.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @param Notifications : Select the notification to be enabled.
* This parameter can be any value of @ref
* RAMCFG_Interrupt group.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_EnableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
assert_param(IS_RAMCFG_INTERRUPT(Notifications));
/* Check RAMCFG state */
if (hramcfg->State == HAL_RAMCFG_STATE_READY)
{
/* Update RAMCFG peripheral state */
hramcfg->State = HAL_RAMCFG_STATE_BUSY;
/* Enable RAMCFG interrupts */
__HAL_RAMCFG_ENABLE_IT(hramcfg, Notifications);
/* Update the RAMCFG state */
hramcfg->State = HAL_RAMCFG_STATE_READY;
}
else
{
/* Update the RAMCFG error code and return error */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Disable the RAMCFG error interrupts.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @param Notifications : Select the notification to be disabled.
* This parameter can be :
* RAMCFG_IT_SINGLEERR : Single Error Interrupt.
* RAMCFG_IT_DOUBLEERR : Double Error Interrupt.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_DisableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
assert_param(IS_RAMCFG_INTERRUPT(Notifications));
/* Check RAMCFG state */
if (hramcfg->State == HAL_RAMCFG_STATE_READY)
{
/* Update RAMCFG peripheral state */
hramcfg->State = HAL_RAMCFG_STATE_BUSY;
/* Disable RAMCFG interrupts */
__HAL_RAMCFG_DISABLE_IT(hramcfg, Notifications);
/* Update the RAMCFG state */
hramcfg->State = HAL_RAMCFG_STATE_READY;
}
else
{
/* Update the RAMCFG error code and return error */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Check if an ECC single error has occurred.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @retval State of bit (1 or 0).
*/
uint32_t HAL_RAMCFG_IsECCSingleErrorDetected(RAMCFG_HandleTypeDef *hramcfg)
{
/* Check the parameters */
assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
/* Return the state of SEDC flag */
return ((READ_BIT(hramcfg->Instance->ISR, RAMCFG_FLAG_SINGLEERR) == (RAMCFG_FLAG_SINGLEERR)) ? 1UL : 0UL);
}
/**
* @brief Check if an ECC double error was occurred.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @retval State of bit (1 or 0).
*/
uint32_t HAL_RAMCFG_IsECCDoubleErrorDetected(RAMCFG_HandleTypeDef *hramcfg)
{
/* Check the parameters */
assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
/* Return the state of SEDC flag */
return ((READ_BIT(hramcfg->Instance->ISR, RAMCFG_FLAG_DOUBLEERR) == (RAMCFG_FLAG_DOUBLEERR)) ? 1UL : 0UL);
}
/**
* @brief Get the RAMCFG single error address.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @retval Single error address offset.
*/
uint32_t HAL_RAMCFG_GetSingleErrorAddress(RAMCFG_HandleTypeDef *hramcfg)
{
/* Check the parameters */
assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
return hramcfg->Instance->SEAR;
}
/**
* @brief Get the RAMCFG double error address.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @retval Double error address offset.
*/
uint32_t HAL_RAMCFG_GetDoubleErrorAddress(RAMCFG_HandleTypeDef *hramcfg)
{
/* Check the parameters */
assert_param(IS_RAMCFG_ECC_INSTANCE(hramcfg->Instance));
return hramcfg->Instance->DEAR;
}
/**
* @}
*/
/** @addtogroup RAMCFG_Exported_Functions_Group3
*
@verbatim
===============================================================================
##### Wait State Functions #####
===============================================================================
[..]
This section provides functions allowing to get and configure the wait state
value .
[..]
The HAL_RAMCFG_ConfigWaitState() function allows configuring the wait state
value.
The HAL_RAMCFG_GetWaitState() function allows getting the current wait state
value.
@endverbatim
* @{
*/
/**
* @brief Configure the wait state value for the given SRAM.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @param WaitState : Select the value of wait state to be configured.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_ConfigWaitState(RAMCFG_HandleTypeDef *hramcfg, uint32_t WaitState)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
assert_param(IS_RAMCFG_WAITSTATE(WaitState));
/* Check RAMCFG state */
if (hramcfg->State == HAL_RAMCFG_STATE_READY)
{
/* Update RAMCFG peripheral state */
hramcfg->State = HAL_RAMCFG_STATE_BUSY;
/* Set the SRAM wait state */
hramcfg->Instance->CR = WaitState;
/* Update RAMCFG peripheral state */
hramcfg->State = HAL_RAMCFG_STATE_READY;
}
else
{
/* Update the RAMCFG error code and return error */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @brief Get the current wait state value for the given SRAM.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @retval Wait state value.
*/
uint32_t HAL_RAMCFG_GetWaitState(RAMCFG_HandleTypeDef *hramcfg)
{
/* Check the parameters */
assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
/* Return the configured wait state number */
return (hramcfg->Instance->CR & RAMCFG_CR_WSC);
}
/**
* @}
*/
/** @addtogroup RAMCFG_Exported_Functions_Group4
*
@verbatim
===============================================================================
##### Write Protection Functions #####
===============================================================================
[..]
This section provides functions to enable write protection feature for
the page(s) of SRAM2.
[..]
The HAL_RAMCFG_EnableWriteProtection() function allows the user to enable the write
protection for the page(s) of SRAM2.
The HAL_RAMCFG_GetWaitState() function allows get the current wait state
value. Disabling SRAM2 page(s) protection is performed only by a glabal
peripheral reset or a by a system reset.
@endverbatim
* @{
*/
/**
* @brief Enable write protection for the given page(s).
* Write protection feature can be disabled only by system reset.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @param StartPage : Select the start page number.
* @param NbPage : Number of page to be protected.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg, uint32_t StartPage, uint32_t NbPage)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t page_mask_0 = 0U;
uint32_t page_mask_1 = 0U;
/* Check the parameters */
assert_param(IS_RAMCFG_WP_INSTANCE(hramcfg->Instance));
assert_param(IS_RAMCFG_WRITEPROTECTION_PAGE(StartPage + NbPage));
/* Check RAMCFG state */
if (hramcfg->State == HAL_RAMCFG_STATE_READY)
{
/* Update RAMCFG peripheral state */
hramcfg->State = HAL_RAMCFG_STATE_BUSY;
/* Repeat for page number to be protected */
for (uint32_t count = 0U; count < NbPage; count++)
{
if ((StartPage + count) < 32U)
{
page_mask_0 |= (1UL << (StartPage + count));
}
else
{
page_mask_1 |= (1UL << ((StartPage + count) - 32U));
}
}
/* Apply mask to protect pages */
SET_BIT(hramcfg->Instance->WPR1, page_mask_0);
SET_BIT(hramcfg->Instance->WPR2, page_mask_1);
/* Update the RAMCFG state */
hramcfg->State = HAL_RAMCFG_STATE_READY;
}
else
{
/* Update the RAMCFG error code and return error */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
status = HAL_ERROR;
}
return status;
}
/**
* @}
*/
/** @addtogroup RAMCFG_Exported_Functions_Group5
*
@verbatim
===============================================================================
##### Erase Operation Functions #####
===============================================================================
[..]
This section provides functions allowing a hardware erase for the given SRAM.
[..]
The HAL_RAMCFG_Erase() function allows a hardware mass erase for the given
SRAM. The erase value for all SRAMs is 0.
@endverbatim
* @{
*/
/**
* @brief Launch a Mass Erase for the given SRAM.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg)
{
uint32_t timeout = RAMCFG_TIMEOUT_VALUE;
uint32_t tickstart = HAL_GetTick();
/* Check the parameters */
assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
/* Check RAMCFG state */
if (hramcfg->State == HAL_RAMCFG_STATE_READY)
{
/* Update RAMCFG peripheral state */
hramcfg->State = HAL_RAMCFG_STATE_BUSY;
/* Unlock the RAMCFG erase bit */
WRITE_REG(hramcfg->Instance->ERKEYR, RAMCFG_ERASE_KEY1);
WRITE_REG(hramcfg->Instance->ERKEYR, RAMCFG_ERASE_KEY2);
/* Start the SRAM erase operation */
hramcfg->Instance->CR |= RAMCFG_CR_SRAMER;
/*
Wait for the SRAM hardware erase operation to complete by polling on
SRAMBUSY flag to be reset.
*/
while (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_SRAMBUSY) != 0U)
{
if (timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > timeout) || (timeout == 0U))
{
/* Update the RAMCFG error code */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_TIMEOUT;
/* Update the RAMCFG state and return error status */
hramcfg->State = HAL_RAMCFG_STATE_ERROR;
return HAL_ERROR;
}
}
}
}
else
{
/* Update the error code and return error status */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY;
return HAL_ERROR;
}
/* Update the RAMCFG state */
hramcfg->State = HAL_RAMCFG_STATE_READY;
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup RAMCFG_Exported_Functions_Group6
*
@verbatim
===============================================================================
##### Handle Interrupt and Callbacks Functions #####
===============================================================================
[..]
This section provides functions to handle RAMCFG interrupts and
Register / UnRegister the different callbacks.
[..]
The HAL_RAMCFG_IRQHandler() function allows the user to handle the active RAMCFG
interrupt request.
The HAL_RAMCFG_RegisterCallback() function allows the user to register the selected
RAMCFG callbacks.
The HAL_RAMCFG_UnRegisterCallback() function allows the user to unregister the
selected RAMCFG callbacks.
@endverbatim
* @{
*/
/**
* @brief Handles RAMCFG interrupt request.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @retval None.
*/
void HAL_RAMCFG_IRQHandler(RAMCFG_HandleTypeDef *hramcfg)
{
/* Single Error Interrupt Management ****************************************/
if (__HAL_RAMCFG_GET_IT_SOURCE(hramcfg, RAMCFG_IT_SINGLEERR) != 0U)
{
if (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_SINGLEERR) != 0U)
{
/* Clear active flags */
__HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAG_SINGLEERR);
#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
/* Check if a valid single error callback is registered */
if (hramcfg->DetectSingleErrorCallback != NULL)
{
/* Single error detection callback */
hramcfg->DetectSingleErrorCallback(hramcfg);
}
#else
HAL_RAMCFG_DetectSingleErrorCallback(hramcfg);
#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
}
}
/* Double Error Interrupt Management ****************************************/
if (__HAL_RAMCFG_GET_IT_SOURCE(hramcfg, RAMCFG_IT_DOUBLEERR) != 0U)
{
if (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_DOUBLEERR) != 0U)
{
/* Clear active flags */
__HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAG_DOUBLEERR);
#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
/* Check if a valid double error callback is registered */
if (hramcfg->DetectDoubleErrorCallback != NULL)
{
/* Double error detection callback */
hramcfg->DetectDoubleErrorCallback(hramcfg);
}
#else
HAL_RAMCFG_DetectDoubleErrorCallback(hramcfg);
#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
}
}
}
/**
* @brief RAMCFG single error detection callback.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
* the configuration information for the specified RAMCFG.
* @retval None.
*/
__weak void HAL_RAMCFG_DetectSingleErrorCallback(RAMCFG_HandleTypeDef *hramcfg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hramcfg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_RAMCFG_DetectSingleErrorCallback can be implemented in
the user file. */
}
/**
* @brief RAMCFG double error detection callback.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains
* the configuration information for the specified RAMCFG.
* @retval None.
*/
__weak void HAL_RAMCFG_DetectDoubleErrorCallback(RAMCFG_HandleTypeDef *hramcfg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hramcfg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_RAMCFG_DetectDoubleErrorCallback can be implemented in
the user file. */
}
#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1)
/**
* @brief Register RAMCFG callbacks.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @param CallbackID : User Callback identifier a HAL_MDMA_CallbackIDTypeDef
* ENUM as parameter.
* @param pCallback : Pointer to private callback function.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg,
HAL_RAMCFG_CallbackIDTypeDef CallbackID,
void (* pCallback)(RAMCFG_HandleTypeDef *_hramcfg))
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code and return error */
hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
/* Check RAMCFG state */
if (hramcfg->State == HAL_RAMCFG_STATE_READY)
{
switch (CallbackID)
{
case HAL_RAMCFG_SE_DETECT_CB_ID:
/* Register single error callback */
hramcfg->DetectSingleErrorCallback = pCallback;
break;
case HAL_RAMCFG_DE_DETECT_CB_ID:
/* Register single error callback */
hramcfg->DetectDoubleErrorCallback = pCallback;
break;
case HAL_RAMCFG_MSPINIT_CB_ID :
/* Register msp init callback */
hramcfg->MspInitCallback = pCallback;
break;
case HAL_RAMCFG_MSPDEINIT_CB_ID :
/* Register msp de-init callback */
hramcfg->MspDeInitCallback = pCallback;
break;
default:
/* Update the error code and return error */
hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else if (hramcfg->State == HAL_RAMCFG_STATE_RESET)
{
switch (CallbackID)
{
case HAL_RAMCFG_MSPINIT_CB_ID :
/* Register msp init callback */
hramcfg->MspInitCallback = pCallback;
break;
case HAL_RAMCFG_MSPDEINIT_CB_ID :
/* Register msp de-init callback */
hramcfg->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code and return error */
hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code and return error */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
return status;
}
/**
* @brief UnRegister RAMCFG callbacks.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @param CallbackID : User Callback identifier a HAL_MDMA_CallbackIDTypeDef
* ENUM as parameter.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, HAL_RAMCFG_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
/* Check RAMCFG state */
if (hramcfg->State == HAL_RAMCFG_STATE_READY)
{
switch (CallbackID)
{
case HAL_RAMCFG_SE_DETECT_CB_ID:
/* UnRegister single error callback */
hramcfg->DetectSingleErrorCallback = NULL;
break;
case HAL_RAMCFG_DE_DETECT_CB_ID:
/* UnRegister double error callback */
hramcfg->DetectDoubleErrorCallback = NULL;
break;
case HAL_RAMCFG_MSPINIT_CB_ID :
/* UnRegister msp init callback */
hramcfg->MspInitCallback = NULL;
break;
case HAL_RAMCFG_MSPDEINIT_CB_ID :
/* UnRegister msp de-init callback */
hramcfg->MspDeInitCallback = NULL;
break;
case HAL_RAMCFG_ALL_CB_ID:
/* UnRegister all available callbacks */
hramcfg->DetectSingleErrorCallback = NULL;
hramcfg->DetectDoubleErrorCallback = NULL;
hramcfg->MspDeInitCallback = NULL;
hramcfg->MspInitCallback = NULL;
break;
default:
/* Return error status */
status = HAL_ERROR;
break;
}
}
else if (hramcfg->State == HAL_RAMCFG_STATE_RESET)
{
switch (CallbackID)
{
case HAL_RAMCFG_MSPINIT_CB_ID :
/* UnRegister msp init callback */
hramcfg->MspInitCallback = NULL;
break;
case HAL_RAMCFG_MSPDEINIT_CB_ID :
/* UnRegister msp de-init callback */
hramcfg->MspDeInitCallback = NULL;
break;
case HAL_RAMCFG_ALL_CB_ID:
/* UnRegister all available callbacks */
hramcfg->MspDeInitCallback = NULL;
hramcfg->MspInitCallback = NULL;
break;
default :
/* Update the error code */
hramcfg->ErrorCode |= HAL_RAMCFG_ERROR_INVALID_CALLBACK;
/* Update return status */
status = HAL_ERROR;
break;
}
}
else
{
/* Update the error code and return error */
hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK;
status = HAL_ERROR;
}
return status;
}
/**
* @}
*/
#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */
/** @addtogroup RAMCFG_Exported_Functions_Group7
*
@verbatim
===============================================================================
##### State and Error Functions #####
===============================================================================
[..]
This section provides functions to check and get the RAMCFG state
and the error code .
[..]
The HAL_RAMCFG_GetState() function allows the user to get the RAMCFG peripheral
state.
The HAL_RAMCFG_GetError() function allows the user to get the RAMCFG peripheral error
code.
@endverbatim
* @{
*/
/**
* @brief Get the RAMCFG peripheral state.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @retval RAMCFG state.
*/
HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(RAMCFG_HandleTypeDef *hramcfg)
{
/* Check the parameters */
assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
/* Return the RAMCFG state */
return hramcfg->State;
}
/**
* @brief Get the RAMCFG peripheral error code.
* @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that
* contains the configuration information for the
* specified RAMCFG instance.
* @retval RAMCFG error code.
*/
uint32_t HAL_RAMCFG_GetError(RAMCFG_HandleTypeDef *hramcfg)
{
/* Check the parameters */
assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance));
/* Return the RAMCFG error code */
return hramcfg->ErrorCode;
}
/**
* @}
*/
#endif /* HAL_RAMCFG_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/stm32u5/drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ramcfg.c
|
C
|
apache-2.0
| 38,288
|