code
stringlengths 1
1.05M
| repo_name
stringlengths 6
83
| path
stringlengths 3
242
| language
stringclasses 222
values | license
stringclasses 20
values | size
int64 1
1.05M
|
|---|---|---|---|---|---|
/**
******************************************************************************
* @file rtl8721d_ipc.h
* @author
* @version V1.0.0
* @date 2017-11-06
* @brief This file contains all the functions prototypes for the Internal Processor Communication(IPC)
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_IPC_H_
#define _RTL8721D_IPC_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup IPC
* @brief IPC driver modules
* @{
*/
/** @addtogroup IPC
* @verbatim
*****************************************************************************************
* Internal Processor Communication(IPC) Introduction
*****************************************************************************************
* -32 core-to-core interrupts.
* -16 hardware semephone.
* -CPU ID get.
*****************************************************************************************
* @endverbatim
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IPC_Exported_Functions IPC Exported Functions
* @{
*/
void IPC_INTConfig(IPC_TypeDef *IPCx, u8 IPC_ChNum, u32 NewState);
void IPC_IERSet(IPC_TypeDef *IPCx, u32 IPC_Chs);
u32 IPC_IERGet(IPC_TypeDef *IPCx);
void IPC_INTRequest(IPC_TypeDef *IPCx, u8 IPC_ChNum);
void IPC_INTClear(IPC_TypeDef *IPCx, u8 IPC_ChNum);
u32 IPC_INTGet(IPC_TypeDef *IPCx);
u32 IPC_CPUID(void);
u32 IPC_INTHandler(void *Data);
void IPC_INTUserHandler(u8 IPC_ChNum, VOID *IrqHandler, VOID *IrqData);
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IPC_Exported_Constants IPC Exported Constants
* @{
*/
/* Channel Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup IPC_Channel_Definitions IPC Channel Definitions
* @{
*****************************************************************************/
#define IPC_INT_CHAN_SHELL_SWITCH 0 /*!< KM0 <--> KM4 Switch shell */
#define IPC_INT_CHAN_WIFI_FW 1 /*!< KM0 <-- KM4 FW INFO*/
#define IPC_INT_CHAN_FLASHPG_REQ 2 /*!< KM0 <--> KM4 Flash Program REQUEST*/
#define IPC_INT_KM4_TICKLESS_INDICATION 3 /*!< KM0 <-- KM4 tickless indicate */
/** @} */
/**************************************************************************//**
* @defgroup IPC0_USER_BUF_Definitions LP IPC User IDX Definitions
* @{
*****************************************************************************/
#define IPC_USER_BUF_LOG_RP 7 /*!< logbuf write pointer */
#define IPC_USER_BUF_LOG_WP 8 /*!< logbuf read pointer */
/** @} */
/**************************************************************************//**
* @defgroup IPC_SEM_IDX_Definitions LP IPC SEM IDX Definitions
* @{
*****************************************************************************/
#define IPC_SEM_INDEX_LOG 0 /*!< KM0 <-- KM4 log print */
/** @} */
/**
* @}
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup IPC_Exported_Constants IPC Exported Types
* @{
*/
/* Other definations --------------------------------------------------------*/
typedef void (*IPC_IRQ_FUN)(VOID *Data, u32 IrqStatus, u32 ChanNum);
typedef enum
{
IPC_USER_POINT = 0,
IPC_USER_DATA = 1
} USER_MSG_TYP_DEF;
typedef struct _IPC_INIT_TABLE_ {
u32 USER_MSG_TYPE;
void (*func)(VOID *Data, u32 IrqStatus, u32 ChanNum);
VOID *IrqData;
}IPC_INIT_TABLE, *PIPC_INIT_TABLE;
extern const IPC_INIT_TABLE ipc_init_config[];
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_ipc.h
|
C
|
apache-2.0
| 4,117
|
/**
******************************************************************************
* @file rtl8721d_ipc_api.h
* @author
* @version V1.0.0
* @date 2018-06-11
* @brief This file contains all the functions prototypes for the IPC API function
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_IPC_API_H
#define _RTL8721D_IPC_API_H
void ipc_table_init(VOID);
void ipc_send_message(u8 IPC_ChNum, u32 Message);
u32 ipc_get_message(u8 IPC_ChNum);
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_ipc_api.h
|
C
|
apache-2.0
| 964
|
/**
******************************************************************************
* @file rtl8721d_ir.h
* @author
* @version V1.0.0
* @date 2017-09-18
* @brief This file contains all the functions prototypes for the IR firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_IR_H_
#define _RTL8721D_IR_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup IR
* @{
*/
/** @addtogroup IR
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* IR:
* - Base Address: IR_DEV
* - IPclk: SCLK, normally is 100MHz
* - carrier clock: 25k~500k
* - work mode: Half Duplex
* - SocPs: SleepMode not support
* - accuracy:3%
* - IRQ: IR_IRQ
* - GDMA support: not support
*
*****************************************************************************************
* PINMUX
*****************************************************************************************
*/
//1TODO: -to be define:derek
/*
*****************************************************************************************
* How to use IR TX
*****************************************************************************************
* To use the IR tx function, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
* RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
*
* 2. Configure the IR pinmux
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_IR)
*
* 3. Set parameters, change some parameter if needed
* void IR_StructInit(IR_InitTypeDef *IR_InitStruct)
*
* 4. Init hardware use step3 parameters.
* void IR_Init(IR_InitTypeDef *IR_InitStruct)
*
* 5. Enable IRQ using following function if needed
* IR_INTConfig(): IR IRQ Enable set
* InterruptRegister(): register the IR irq handler
*
* 6. Send TX data to FIFO
*
*****************************************************************************************
* How to use IR RX
*****************************************************************************************
* To use the IR rx function, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
* RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, ENABLE);
*
* 2. Configure the IR pinmux
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_IR)
*
* 3. Set parameters, change some parameter if needed
* void IR_StructInit(IR_InitTypeDef *IR_InitStruct)
*
* 4. Init hardware use step3 parameters.
* void IR_Init(IR_InitTypeDef *IR_InitStruct)
*
* 5. Enable IRQ using following function if needed
* IR_INTConfig(): IR IRQ Enable set
* InterruptRegister(): register the IR irq handler
*
* 6. Recieve Data from Rx fifo
* @endverbatim
*/
/*============================================================================*
* Types
*============================================================================*/
/** @defgroup IR_Exported_Types IR Exported Types
* @{
*/
/**
* @brief IR initialize parameters
*
* IR initialize parameters
*/
typedef struct
{
u32 IR_Clock; /*!< Specifies the IR IP core Input clock. */
u32 IR_Freq; /*!< Specifies the clock frequency. This parameter is IR carrier freqency whose unit is Hz.
This parameter can be a value of @ref IR_Frequency */
u32 IR_DutyCycle; /*!< Specifies the IR duty cycle. */
u32 IR_Mode; /*!< Specifies the IR mode.
This parameter can be a value of @ref IR_Mode */
u32 IR_TxIdleLevel; /*!< Specifies the IR output level in Tx mode
This parameter can be a value of @ref IR_Idle_Status */
u32 IR_TxInverse; /*!< Specifies inverse FIFO data or not in TX mode
This parameter can be a value of @ref IR_TX_Data_LEVEL */
u32 IR_TxFIFOThrLevel; /*!< Specifies TX FIFO interrupt threshold in TX mode. When TX FIFO depth <= threshold value, trigger interrupt.
This parameter can be a value of @ref IR_Tx_Threshold */
u32 IR_TxCOMP_CLK; /*!< Specifies TX compensation clk. This CLK used when @ref IR_Tx_DATA_TYPE = IR_TX_CLK_Self_Def.*/
u32 IR_RxStartMode; /*!< Specifies Start mode in RX mode
This parameter can be a value of @ref IR_Rx_Start_Mode */
u32 IR_RxFIFOThrLevel; /*!< Specifies RX FIFO interrupt threshold in RX mode. when RX FIFO depth > threshold value, trigger interrupt.
This parameter can be a value of @ref IR_Rx_Threshold */
u32 IR_RxFIFOFullCtrl; /*!< Specifies data discard mode in RX mode when RX FIFO is full and receiving new data
This parameter can be a value of @ref IR_RX_FIFO_DISCARD_SETTING */
u32 IR_RxTriggerMode; /*!< Specifies trigger in RX mode
This parameter can be a value of @ref IR_RX_Trigger_Mode */
u32 IR_RxFilterTime; /*!< Specifies filter time in RX mode
This parameter can be a value of @ref IR_RX_Filter_Time */
u32 IR_RxCntThrType; /*!< Specifies counter level type when trigger IR_INT_RX_CNT_THR interrupt in RX mode
This parameter can be a value of @ref IR_RX_COUNTER_THRESHOLD_TYPE */
u32 IR_RxCntThr; /*!< Specifies counter threshold value when trigger IR_INT_RX_CNT_THR interrupt in RX mode */
} IR_InitTypeDef, *PIR_InitTypeDef;
/** End of group IR_Exported_Types
* @}
*/
/*============================================================================*
* Constants
*============================================================================*/
/** @defgroup IR_Exported_Constants IR Exported Constants
* @{
*/
/** @defgroup IR_Peripheral_definitions
* @{
*/
#define IS_IR_ALL_PERIPH(PERIPH) ((PERIPH) == IR_DEV)
/**
* @}
*/
/** @defgroup IR_Frequency IR Frequency
* @{
*/
#define IS_IR_FREQUENCY(F) (((F) >= 5000) && ((F) <= 500000))
/**
* @}
*/
/** @defgroup IR_TRXFIFO
* @{
*/
#define IR_TX_FIFO_SIZE 32
#define IR_RX_FIFO_SIZE 32
/**
* @}
*/
/** @defgroup IR_Mode IR Mode
* @{
*/
#define IR_MODE_TX (0x00000000U << 31)
#define IR_MODE_RX (0x00000001U << 31)
#define IR_MODE(MODE) ((MODE) & (0x00000001 << 31))
#define IS_IR_MODE(MODE) (((MODE) == IR_MODE_TX) || ((MODE) == IR_MODE_RX))
/**
* @}
*/
/** @defgroup IR_TX_Data_LEVEL IR TX Data Level
* @{
*/
#define IR_TX_DATA_NORMAL (0x00000000 << 14)
#define IR_TX_DATA_INVERSE (0x00000001 << 14)
#define IR_TX_DATA_CARRIER_NORMAL (0x00000000 << 13)
#define IR_TX_DATA_CARRIER_INVERSE (0x00000001 << 13)
#define IR_TX_DATA_LEVEL_MASK (IR_TX_DATA_INVERSE|IR_TX_DATA_CARRIER_INVERSE)
#define IS_IR_TX_DATA_TYPE(TYPE) (((TYPE) & (~IR_TX_DATA_LEVEL_MASK)) == 0)
/** End of group IR_TX_Data_LEVEL
* @}
*/
/** @defgroup IR_Tx_Threshold IR TX Threshold
* @{
*/
#define IR_TX_FIFO_THRESHOLD(THD) ((THD) << 8)
#define IS_IR_TX_FIFO_THRESHOLD(THD) ((THD) <= IR_TX_FIFO_SIZE)
#define IR_TX_FIFO_THRESHOLD_MASK ((0x0000001f) << 8)
/** End of group IR_Tx_Threshold
* @}
*/
/** @defgroup IR_Idle_Status IR Idle Status
* @{
*/
#define IR_IDLE_OUTPUT_LOW (0x00000000 << 6)
#define IR_IDLE_OUTPUT_HIGH (0x00000001 << 6)
#define IS_IR_IDLE_STATUS(LEVEL) (((LEVEL) == IR_IDLE_OUTPUT_HIGH) || \
((LEVEL) == IR_IDLE_OUTPUT_LOW))
/** End of group IR_Idle_Status
* @}
*/
/** @defgroup IR_Rx_Start_Ctrl
* @{
*/
#define IR_RX_AUTO_MODE (0x00000001 << 27)
#define IR_RX_MANUAL_MODE (0x00000000 << 27)
#define IS_RX_START_MODE(MODE) (((MODE) == IR_RX_AUTO_MODE) || \
((MODE) == IR_RX_MANUAL_MODE))
#define IS_RX_RX_TRIGGER_EDGE(EDGE) (((EDGE) == IR_RX_FALL_EDGE) || \
((EDGE) == IR_RX_RISING_EDGE) || \
((EDGE) == IR_RX_DOUBLE_EDGE))
/** End of group IR_Rx_Start_Ctrl
* @}
*/
/** @defgroup IR_RX_Filter_Time
* @{
*/
#define IR_RX_FILTER_TIME_20NS (0x00000000 << 21)
#define IR_RX_FILTER_TIME_30NS (0x00000001 << 21)
#define IR_RX_FILTER_TIME_40NS (0x00000002 << 21)
#define IR_RX_FILTER_TIME_50NS (0x00000003 << 21)
#define IR_RX_FILTER_TIME_60NS (0x00000004 << 21)
#define IR_RX_FILTER_TIME_70NS (0x00000005 << 21)
#define IR_RX_FILTER_TIME_80NS (0x00000006 << 21)
#define IR_RX_FILTER_TIME_90NS (0x00000007 << 21)
#define IS_IR_RX_FILTER_TIME_CTRL(CTRL) (((CTRL) == IR_RX_FILTER_TIME_20NS) || \
((CTRL) == IR_RX_FILTER_TIME_30NS) || \
((CTRL) == IR_RX_FILTER_TIME_40NS) || \
((CTRL) == IR_RX_FILTER_TIME_50NS) || \
((CTRL) == IR_RX_FILTER_TIME_60NS) || \
((CTRL) == IR_RX_FILTER_TIME_70NS) || \
((CTRL) == IR_RX_FILTER_TIME_80NS) || \
((CTRL) == IR_RX_FILTER_TIME_90NS))
/** End of group IR_RX_Filter_Time
* @}
*/
/** @defgroup IR_RX_FIFO_DISCARD_SETTING
* @{
*/
#define IR_RX_FIFO_FULL_DISCARD_NEWEST (0x00000001 << 13)
#define IR_RX_FIFO_FULL_DISCARD_OLDEST (0x00000000 << 13)
#define IS_IR_RX_FIFO_FULL_DISCARD_CTRL(CTRL) (((CTRL) == IR_RX_FIFO_FULL_DISCARD_NEWEST) || \
((CTRL) == IR_RX_FIFO_FULL_DISCARD_OLDEST))
/** End of group IR_RX_FIFO_DISCARD_SETTING
* @}
*/
/** @defgroup IR_Rx_Threshold IR RX Threshold
* @{
*/
#define IR_RX_FIFO_THRESHOLD(THD) ((THD) <<8)
#define IS_IR_RX_FIFO_THRESHOLD(THD) ((THD) <= IR_RX_FIFO_SIZE)
#define IR_RX_FIFO_THRESHOLD_MASK ((0x0000001f) << 8)
/** End of group IR_Rx_Threshold
* @}
*/
/** @defgroup IR_INT_EN
* @{
*/
#define IS_TX_INT_MASK(MASK) (((MASK) & (~IR_TX_INT_ALL_MASK)) == 0)
#define IS_TX_INT(MASK) (((MASK) & (~IR_TX_INT_ALL_EN)) == 0)
#define IS_TX_INT_CLR(MASK) (((MASK) & (~IR_TX_INT_ALL_CLR)) == 0)
#define IS_RX_INT_MASK(MASK) (((MASK) & (~IR_RX_INT_ALL_MASK)) == 0)
#define IS_RX_INT(MASK) (((MASK) & (~IR_RX_INT_ALL_EN)) == 0)
#define IS_RX_INT_CLR(MASK) (((MASK) & (~IR_RX_INT_ALL_CLR)) == 0)
/** End of group IR_Rx_INT_EN
* @}
*/
/** @defgroup IR_RX_COUNTER_THRESHOLD
* @{
*/
#define IR_RX_COUNT_LOW_LEVEL (0x00000000U << 31)
#define IR_RX_COUNT_HIGH_LEVEL (0x00000001U << 31)
#define IS_IR_RX_COUNT_LEVEL_CTRL(CTRL) (((CTRL) == IR_RX_COUNT_LOW_LEVEL) || \
((CTRL) == IR_RX_COUNT_HIGH_LEVEL))
#define IS_IR_RX_COUNTER_THRESHOLD(THD) ((THD) <= 0x7fffffff)
/** End of group IR_RX_COUNTER_THRESHOLD
* @}
*/
/** End of group IR_Exported_Constants
* @}
*/
/*============================================================================*
* Functions
*============================================================================*/
/** @defgroup IR_Exported_Functions IR Exported Functions
* @{
*/
void IR_DeInit(void);
void IR_Init(IR_TypeDef *IRx, IR_InitTypeDef *IR_InitStruct);
void IR_StructInit(IR_InitTypeDef *IR_InitStruct);
void IR_Cmd(IR_TypeDef *IRx, u32 mode, u32 NewState);
void IR_SetRxCounterThreshold(IR_TypeDef *IRx, u32 IR_RxCntThrType, u32 IR_RxCntThr);
void IR_SendBuf(IR_TypeDef *IRx, u32 *pBuf, u32 len, u32 IsLastPacket);
void IR_ReceiveBuf(IR_TypeDef *IRx, u32 *pBuf, u32 len);
void IR_INTConfig(IR_TypeDef *IRx, u32 IR_INT, u32 newState);
void IR_MaskINTConfig(IR_TypeDef *IRx, u32 IR_INT, u32 newState);
u32 IR_GetINTStatus(IR_TypeDef *IRx);
u32 IR_GetIMR(IR_TypeDef *IRx);
u32 IR_FSMRunning(IR_TypeDef *IRx);
void IR_ClearINTPendingBit(IR_TypeDef *IRx, u32 IR_CLEAR_INT);
void IR_SetTxThreshold(IR_TypeDef *IRx, uint8_t thd);
void IR_SetRxThreshold(IR_TypeDef *IRx, uint8_t thd);
u32 IR_GetTxFIFOFreeLen(IR_TypeDef *IRx);
u32 IR_GetRxDataLen(IR_TypeDef *IRx);
void IR_SendData(IR_TypeDef *IRx, u32 data);
void IR_StartManualRxTrigger(IR_TypeDef *IRx);
u32 IR_ReceiveData(IR_TypeDef *IRx);
void IR_ClearTxFIFO(IR_TypeDef *IRx);
void IR_ClearRxFIFO(IR_TypeDef *IRx);
/** @} */ /* End of group IR_Exported_Functions */
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup IR_Register_Definitions IR Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup IR_CLK_DIV
* @{
*****************************************************************************/
#define IR_CLOCK_DIV ((u32)0x0000003F) /*BIT[11:0], IR CLOCK DIV*/
/** @} */
/**************************************************************************//**
* @defgroup IR_TX_CONFIG
* @{
*****************************************************************************/
#define IR_MODE_SEL ((u32)0x00000001 << 31) /*BIT[31], IR Work mode*/
#define IR_TX_START ((u32)0x00000001 << 30) /*BIT[30], IR TX FSM start*/
#define IR_TX_DUTY_NUM ((u32)0x0000003F << 16) /*BIT[27:16], IR TX DUTY NUM*/
#define IR_TX_OUTPUT_INVERSE ((u32)0x00000001 << 14) /*BIT[14], IR Inverse active output*/
#define IR_TX_DE_INVERSE ((u32)0x00000001 << 13) /*BIT[13], IR Inverse FIFO define*/
#define IR_TX_FIFO_LEVEL_TH ((u32)0x0000000F << 8) /*BIT[12:8], IR TX FIFO interrupt threshold*/
#define IR_TX_IDEL_STATE ((u32)0x00000001 << 6) /*BIT[6], IR TX output State in idle*/
#define IR_TX_FIFO_OVER_INT_MASK ((u32)0x00000001 << 5) /*BIT[5], IR TX FIFO overflow Interrupt mask*/
#define IR_TX_FIFO_OVER_INT_EN ((u32)0x00000001 << 4) /*BIT[4], IR TX FIFO overflow Interrupt enable*/
#define IR_TX_FIFO_LEVEL_INT_MASK ((u32)0x00000001 << 3) /*BIT[3], IR TX FIFO Level Interrupt mask*/
#define IR_TX_FIFO_EMPTY_INT_MASK ((u32)0x00000001 << 2) /*BIT[2], IR TX FIFO Empty Interrupt mask*/
#define IR_TX_FIFO_LEVEL_INT_EN ((u32)0x00000001 << 1) /*BIT[1], IR TX FIFO Level Interrupt enable*/
#define IR_TX_FIFO_EMPTY_INT_EN ((u32)0x00000001 << 0) /*BIT[0], IR TX FIFO Empty Interrupt enable*/
#define IR_TX_INT_ALL_MASK ((u32)0x0000002C)
#define IR_TX_INT_ALL_EN ((u32)0x00000013)
/** @} */
/**************************************************************************//**
* @defgroup IR_TX_SR
* @{
*****************************************************************************/
#define IR_TX_FIFO_EMPTY_STATUS ((u32)0x00000001 << 15) /*BIT[15], IR TX_FIFO_EMPTY status*/
#define IR_TX_FIFO_FULL_STATUS ((u32)0x00000001 << 14) /*BIT[14], IR TX_FIFO_FULL status*/
#define IR_TX_FIFO_LEVEL ((u32)0x0000003f << 8) /*BIT[13:8], IR TX FIFO DATA number*/
#define IR_TX_FSM_STATUS ((u32)0x00000001 << 4) /*BIT[4], IR TX FSM status*/
#define IR_TX_FIFO_OVER_INT_STATUS ((u32)0x00000001 << 2) /*BIT[2], IR TX FIFO overflow Interrupt status*/
#define IR_TX_FIFO_LEVEL_INT_STATUS ((u32)0x00000001 << 1) /*BIT[1], IR TX FIFO Level Interrupt stauts*/
#define IR_TX_FIFO_EMPTY_INT_STATUS ((u32)0x00000001 << 0) /*BIT[0], IR TX FIFO Empty Interrupt status*/
/** @} */
/**************************************************************************//**
* @defgroup IR_TX_COMPE_DIV
* @{
*****************************************************************************/
#define IR_TX_COMPESATION_DIV ((u32)0x0000003F) /*BIT[11:0], IR COMP CLOCK DIV*/
/** @} */
/**************************************************************************//**
* @defgroup IR_TX_INT_CLR
* @{
*****************************************************************************/
#define IR_TX_FIFO_OVER_INT_CLR ((u32)0x00000001 << 3) /*BIT[3], IR TX FIFO overflow Interrupt clear*/
#define IR_TX_FIFO_LEVEL_INT_CLR ((u32)0x00000001 << 2) /*BIT[2], IR TX FIFO Level Interrupt clear*/
#define IR_TX_FIFO_EMPTY_INT_CLR ((u32)0x00000001 << 1) /*BIT[1], IR TX FIFO Empty Interrupt clear*/
#define IR_TX_FIFO_CLR ((u32)0x00000001 << 0) /*BIT[0], IR TX FIFO clear*/
#define IR_TX_INT_ALL_CLR ((u32)0x0000000E)
/** @} */
/**************************************************************************//**
* @defgroup IR_TX_FIFO
* @{
*****************************************************************************/
#define IR_TX_DATA_CARRIER_MASK ((u32)0x00000001 << 31) /*BIT[31], IR TX DATA Carrier*/
#define IR_TX_DATA_END_MASK ((u32)0x00000001 << 30) /*BIT[30], IR TX End Flag*/
#define IR_TX_CLK_NORMAL ((u32)0x00000000 << 28) /*BIT[29:28], IR TX DATA cycle unit = 1*carrier cycle*/
#define IR_TX_CLK_1P5 ((u32)0x00000001 << 28) /*BIT[29:28], IR TX DATA cycle unit = 1.5*carrier cycle*/
#define IR_TX_CLK_1P25 ((u32)0x00000002 << 28) /*BIT[29:28], IR TX DATA cycle unit = 1.25*carrier cycle*/
#define IR_TX_CLK_COMP ((u32)0x00000003 << 28) /*BIT[29:28], IR TX DATA cycle unit = 1*compensation cycle*/
#define IR_TX_DATA_TIME ((u32)0x0FFFFFFF << 0) /*BIT[27:0], IR TX FIFO overflow Interrupt clear*/
/** @} */
/**************************************************************************//**
* @defgroup IR_RX_CONFIG
* @{
*****************************************************************************/
#define IR_RX_START ((u32)0x00000001 << 28) /*BIT[28], IR RX FSM start*/
#define IR_RX_START_MODE ((u32)0x00000001 << 27) /*BIT[27], IR RX start mode*/
#define IR_RX_MANUAL_START ((u32)0x00000001 << 26) /*BIT[26], IR RX manual start trigger*/
#define IR_RX_FALL_EDGE ((u32)0x00000000 << 24) /*BIT[25:24], IR RX auto start trigger edge*/
#define IR_RX_RISING_EDGE ((u32)0x00000001 << 24) /*BIT[25:24], IR RX auto start trigger edge*/
#define IR_RX_DOUBLE_EDGE ((u32)0x00000002 << 24) /*BIT[25:24], IR RX auto start trigger edge*/
#define IR_RX_FILTER_STAGETX ((u32)0x00000002 << 21) /*BIT[23:21], IR RX filter*/
#define IR_RX_FIFO_ERROR_INT_MASK ((u32)0x00000001 << 19) /*BIT[19], IR RX FIFO read underflow Interrupt mask*/
#define IR_RX_CNT_THR_INT_MASK ((u32)0x00000001 << 18) /*BIT[18], IR RX CNT threshold Interrupt mask*/
#define IR_RX_FIFO_OF_INT_MASK ((u32)0x00000001 << 17) /*BIT[17], IR RX FIFO overflow Interrupt mask*/
#define IR_RX_CNT_OF_INT_MASK ((u32)0x00000001 << 16) /*BIT[16], IR RX CNT overflow Interrupt mask*/
#define IR_RX_FIFO_LEVEL_INT_MASK ((u32)0x00000001 << 15) /*BIT[15], IR RX FIFO threshold Interrupt mask*/
#define IR_RX_FIFO_FULL_INT_MASK ((u32)0x00000001 << 14) /*BIT[14], IR RX FIFO FULL Interrupt mask*/
#define IR_RX_INT_ALL_MASK ((u32)0x0000003F << 14)
#define IR_RX_FIFO_DISCARD_SET ((u32)0x00000001 << 13) /*BIT[13], IR RX FIFO discard set*/
#define IR_RX_FIFO_LEVEL_TH ((u32)0x0000000F << 8) /*BIT[12:8], IR TX FIFO interrupt threshold*/
#define IR_RX_FIFO_ERROR_INT_EN ((u32)0x00000001 << 5) /*BIT[5], IR RX FIFO read underflow Interrupt enable*/
#define IR_RX_CNT_THR_INT_EN ((u32)0x00000001 << 4) /*BIT[4], IR RX CNT threshold Interrupt enable*/
#define IR_RX_FIFO_OF_INT_EN ((u32)0x00000001 << 3) /*BIT[3], IR RX FIFO overflow Interrupt enable*/
#define IR_RX_CNT_OF_INT_EN ((u32)0x00000001 << 2) /*BIT[2], IR RX CNT overflow Interrupt enable*/
#define IR_RX_FIFO_LEVEL_INT_EN ((u32)0x00000001 << 1) /*BIT[1], IR RX FIFO threshold Interrupt enable*/
#define IR_RX_FIFO_FULL_INT_EN ((u32)0x00000001 << 0) /*BIT[0], IR RX FIFO FULL Interrupt enable*/
#define IR_RX_INT_ALL_EN ((u32)0x0000003F)
/** @} */
/**************************************************************************//**
* @defgroup IR_RX_SR
* @{
*****************************************************************************/
#define IR_RX_FIFO_EMPTY_STATUS ((u32)0x00000001 << 17) /*BIT[17], IR RX FIFO Empty status*/
#define IR_RX_FIFO_LEVEL ((u32)0x0000003f << 8) /*BIT[13:8], IR RX FIFO Level status*/
#define IR_RX_FSM_STATUS ((u32)0x00000001 << 7) /*BIT[7], IR RX FSM status*/
#define IR_RX_FIFO_ERROR_INT_STATUS ((u32)0x00000001 << 5) /*BIT[5], IR RX FIFO read underflow Interrupt status*/
#define IR_RX_CNT_THR_INT_STATUS ((u32)0x00000001 << 4) /*BIT[4], IR RX CNT threshold Interrupt status*/
#define IR_RX_FIFO_OF_INT_STATUS ((u32)0x00000001 << 3) /*BIT[3], IR_RX FIFO overflow Interrupt status*/
#define IR_RX_CNT_OF_INT_STATUS ((u32)0x00000001 << 2) /*BIT[2], IR_RX CNT overflow Interrupt status*/
#define IR_RX_FIFO_LEVEL_INT_STATUS ((u32)0x00000001 << 1) /*BIT[1], IR_RX FIFO threshold Interrupt status*/
#define IR_RX_FIFO_FULL_INT_STATUS ((u32)0x00000001 << 0) /*BIT[0], IR RX FIFO FULL Interrupt status*/
/** @} */
/**************************************************************************//**
* @defgroup IR_RX_INT_CLR
* @{
*****************************************************************************/
#define IR_RX_FIFO_CLR ((u32)0x00000001 << 8) /*BIT[8], IR TX FIFO clear*/
#define IR_RX_FIFO_ERROR_INT_CLR ((u32)0x00000001 << 5) /*BIT[5], IR RX FIFO read underflow Interrupt clear*/
#define IR_RX_CNT_THR_INT_CLR ((u32)0x00000001 << 4) /*BIT[4], IR RX CNT threshold Interrupt clear*/
#define IR_RX_FIFO_OF_INT_CLR ((u32)0x00000001 << 3) /*BIT[3], IR_RX FIFO overflow Interrupt clear*/
#define IR_RX_CNT_OF_INT_CLR ((u32)0x00000001 << 2) /*BIT[2], IR_RX CNT overflow Interrupt clear*/
#define IR_RX_FIFO_LEVEL_INT_CLR ((u32)0x00000001 << 1) /*BIT[1], IR_RX FIFO threshold Interrupt clear*/
#define IR_RX_FIFO_FULL_INT_CLR ((u32)0x00000001 << 0) /*BIT[0], IR RX FIFO FULL Interrupt clear*/
#define IR_RX_INT_ALL_CLR ((u32)0x0000003F)
/** @} */
/**************************************************************************//**
* @defgroup IR_RX_CNT_INT_SEL
* @{
*****************************************************************************/
#define IR_RX_COUNT_LEVEL ((u32)0x00000001 << 31) /*BIT[31], IR RX CNT LEVEL*/
#define IR_RX_COUNTER_THRESHOLD ((u32)0x7FFFFFFF) /*BIT[30:0], IR RX CYCLE*/
/** @} */
/**************************************************************************//**
* @defgroup IR_RX_FIFO
* @{
*****************************************************************************/
#define IR_RX_LEVEL ((u32)0x00000001 << 31) /*BIT[31], IR RX LEVEL*/
#define IR_RX_COUNTER ((u32)0x7FFFFFFF) /*BIT[30:0], IR RX CYCLE*/
/** @} */
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
/** @} */ /* End of group IR */
/** @} */ /* End of group AmebaD_Periph_Driver */
#endif /* _RTL8721D_IR_H_ */
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_ir.h
|
C
|
apache-2.0
| 23,013
|
/**
******************************************************************************
* @file rtl8721d_keyscan.h
* @author
* @version V1.0.0
* @date 2017-10-16
* @brief This file contains all the functions prototypes for the keyscan.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_KEYSCAN_H_
#define _RTL8721D_KEYSCAN_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @addtogroup KeyScan KeyScan
* @{
*/
/** @addtogroup KeyScan
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* KEYSCAN:
* - Base Address: KEYSCAN_DEV
* - Sclk: 32K/10Mhz
* - Keypad Array: Up to 6*6 (36), multi-key detect
* - Scan Clock: Configurable, up to 10Mhz
* - Work Mode: Event Trigger Mode and Regular Scan Mode
* - Debounce Timer: Configurable
* - SocPs: Sleep Mode (clock gating & power gating)
* - IRQ: KeyScan_IRQ
*
*****************************************************************************************
* How to use Normal KeyScan
*****************************************************************************************
* To use the normal KeyScan mode, the following steps are mandatory:
*
* 1. Enable KeyScan peripheral clock
*
* 2. configure the KeyScan pinmux.
*
* 3. Program Scan clock, Work Mode, Columns and Rows select, Dobounce Timer, Threshold
* KeyScan_StructInit(KeyScan_InitTypeDef* KeyScan_InitStruct)
*
* 4. Init Hardware use step3 parameters:
* KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KeyScan_InitTypeDef* KeyScan_InitStruct)
*
* 5. Enable the NVIC and the corresponding interrupt using following function if you need
* to use interrupt mode.
* KeyScan_INTConfig(): KeyScan IRQ Enable set
* KeyScan_INTMask(): KeyScan IRQ mask set
* InterruptRegister(): register the keyscan irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 6. Enable KeyScan module using KeyScan_Cmd().
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types --------------------------------------------------------*/
/** @defgroup KeyScan_Exported_Types KeyScan Exported Types
* @{
*/
/**
* @brief KeyScan Init structure definition
*/
typedef struct {
u32 KS_ClkDiv; /*!< Specifies Keyscan clock divider. Scan_clk = Bus clock/(KS_ClkDiv+1).
This parameter must be set to a value in the 0x0-0xfff range. */
u32 KS_WorkMode; /*!< Specifies Keyscan work mode.
This parameter can be a value of @ref KeyScan_Work_Mode_definitions */
u32 KS_RowSel; /*!< Specifies which row(s) is used.
This parameter must be set to a value in the 0x1-0xff range. */
u32 KS_ColSel; /*!< Specifies which column(s) is used.
This parameter must be set to a value in the 0x1-0xff range. */
u32 KS_DebounceCnt; /*!< Specifies Keyscan Debounce Timer. Debounce Timer = (KS_DebounceCnt +1)* Scan_clk.
This parameter must be set to a value in the 0x0-0xfff range. */
u32 KS_IntervalCnt; /*!< Specifies Keyscan Scan Interval Timer. Interval Timer = (KS_IntervalCnt +1)* Scan_clk.
This parameter must be set to a value in the 0x0-0xfff range. */
u32 KS_ReleaseCnt; /*!< Specifies Keyscan All Release Timer. Release Timer = (KS_ReleaseCnt+1) * Scan_clk.
This parameter must be set to a value in the 0x0-0xfff range. */
u32 KS_LimitLevel; /*!< Specifies the max allowable key number be pressed at a time
This parameter can be a value of @ref KeyScan_FIFO_LimitLevel_Control */
u32 KS_ThreholdLevel; /*!< Specifies Keyscan FIFO threshold to trigger KS_FIFO_FULL
This parameter can be a value of @ref KeyScan_FIFO_ThreholdLevel_Control */
u32 KS_OverCtrl; /*!< Specifies Keyscan FIFO over control.
This parameter can be a value of @ref KeyScan_FIFO_Overflow_Control */
}KeyScan_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup KeyScan_Exported_Constants KeyScan Exported Constants
* @{
*/
/** @defgroup KeyScan_Peripheral_definitions
* @{
*/
#define IS_KEYSCAN_ALL_PERIPH(PERIPH) ((PERIPH) == KEYSCAN_DEV)
/**
* @}
*/
/** @defgroup KeyScan_Work_Mode_definitions
* @{
*/
#define KS_REGULAR_SCAN_MODE ((u32)0x00000000 << 3)
#define KS_EVENT_TRIGGER_MODE ((u32)0x00000001 << 3)
#define IS_KS_WORK_MODE(MODE) (((MODE) == KS_REGULAR_SCAN_MODE) || \
((MODE) == KS_EVENT_TRIGGER_MODE))
/**
* @}
*/
/** @defgroup KeyScan_FIFO_Overflow_Control
* @{
*/
#define KS_FIFO_OVER_CTRL_DIS_NEW ((u32)0x00000000 << 1)
#define KS_FIFO_OVER_CTRL_DIS_LAST ((u32)0x00000001 << 1)
#define IS_KS_FIFO_OVER_CTRL(CTRL) (((CTRL) == KS_FIFO_OVER_CTRL_DIS_NEW) || \
((CTRL) == KS_FIFO_OVER_CTRL_DIS_LAST))
/**
* @}
*/
/** @defgroup KeyScan_FIFO_LimitLevel_Control
* @{
*/
#define IS_KS_FIFO_LIMIT_LEVEL(DATA_NUM) ((DATA_NUM) <= 6)
/**
* @}
*/
/** @defgroup KeyScan_FIFO_ThreholdLevel_Control
* @{
*/
#define IS_KS_FIFO_TH_LEVEL(DATA_NUM) (((DATA_NUM) > 0) && ((DATA_NUM) < 16))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup KeyScan_Exported_Functions KeyScan Exported Functions
* @{
*/
/** @defgroup KeyScan_Exported_Normal_Functions KeyScan Exported Normal Functions
* @{
*/
_LONG_CALL_ void KeyScan_StructInit(KeyScan_InitTypeDef* KeyScan_InitStruct);
_LONG_CALL_ void KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KeyScan_InitTypeDef* KeyScan_InitStruct);
_LONG_CALL_ void KeyScan_INTConfig(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT, u8 newState);
_LONG_CALL_ void KeyScan_ClearINT(KEYSCAN_TypeDef *KeyScan, u32 KeyScan_IT);
_LONG_CALL_ u32 KeyScan_GetRawINT(KEYSCAN_TypeDef *KeyScan);
_LONG_CALL_ u32 KeyScan_GetINT(KEYSCAN_TypeDef *KeyScan);
_LONG_CALL_ u8 KeyScan_GetDataNum(KEYSCAN_TypeDef *KeyScan);
_LONG_CALL_ void KeyScan_ClearFIFOData(KEYSCAN_TypeDef *KeyScan);
_LONG_CALL_ BOOL KeyScan_GetFIFOState(KEYSCAN_TypeDef *KeyScan, u32 KeyScan_Flag);
_LONG_CALL_ void KeyScan_Read(KEYSCAN_TypeDef *KeyScan, u32 *outBuf, u8 count);
_LONG_CALL_ void KeyScan_Cmd(KEYSCAN_TypeDef *KeyScan, u8 NewState);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup KeyScan_Register_Definitions KeyScan Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup KS_CLK_DIV
* @{
*****************************************************************************/
#define BIT_KS_CLK_DIV ((u32)0x00000fff) /*Bit[11:0], bits for clock division*/
/** @} */
/**************************************************************************//**
* @defgroup KS_TIM_CFG0
* @{
*****************************************************************************/
#define BIT_KS_POST_GUARD_TIMER ((u32)0x0000000f << 24) /*Bit[27:24], bits for post guard timer set*/
#define BIT_KS_PRE_GUARD_TIMER ((u32)0x0000000f << 16) /*Bit[19:16], bits for pre guard timer set*/
#define BIT_KS_DEB_TIMER ((u32)0x00000fff) /*Bit[11:0], bits for debounce timer set*/
/** @} */
/**************************************************************************//**
* @defgroup KS_TIM_CFG1
* @{
*****************************************************************************/
#define BIT_KS_INTERVAL_TIMER ((u32)0x00000fff << 16) /*Bit[27:16], bits for interval timer set*/
#define BIT_KS_RELEASE_TIMER ((u32)0x00000fff) /*Bit[11:0], bits for all release timer set*/
/** @} */
/**************************************************************************//**
* @defgroup KS_CTRL
* @{
*****************************************************************************/
#define BIT_KS_WORK_MODE ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan work mode select*/
#define BIT_KS_BUSY_STATUS ((u32)0x00000001 << 1) /*Bit[1], bit for FSM busy status*/
#define BIT_KS_RUN_ENABLE ((u32)0x00000001) /*Bit[0], bit for enable internal key scan scan clock*/
/** @} */
/**************************************************************************//**
* @defgroup KS_FIFO_CFG
* @{
*****************************************************************************/
#define BIT_KS_FIFO_LIMIT_LEVEL ((u32)0x0000000f << 24) /*Bit[27:24], bits for fifo limit level set*/
#define BIT_KS_FIFO_THREHOLD_LEVEL ((u32)0x0000000f << 16) /*Bit[19:16], bits for fifo threshold set*/
#define BIT_KS_FIFO_OV_CTRL ((u32)0x00000001 << 1) /*Bit[1], bit for fifo overflow control*/
#define BIT_KS_FIFO_CLR ((u32)0x00000001) /*Bit[0], bit for fifo data clear*/
/** @} */
/**************************************************************************//**
* @defgroup KS_COL_CFG
* @{
*****************************************************************************/
#define BIT_KS_COLUMN_SEL ((u32)0x000000ff) /*Bit[7:0], bits for key column select*/
/** @} */
/**************************************************************************//**
* @defgroup KS_ROW_CFG
* @{
*****************************************************************************/
#define BIT_KS_ROW_SEL ((u32)0x000000ff) /*Bit[7:0], bits for key row select*/
/** @} */
/**************************************************************************//**
* @defgroup KS_DATA_NUM
* @{
*****************************************************************************/
#define BIT_KS_FIFO_FULL ((u32)0x00000001 << 17) /*Bit[17], bit for fifo full flag*/
#define BIT_KS_FIFO_EMPTY ((u32)0x00000001 << 16) /*Bit[16], bit for fifo empty flag*/
#define BIT_KS_FIFO_DATA_LEVEL ((u32)0x0000001f) /*Bit[4:0], bits for fifo data level*/
/** @} */
/**************************************************************************//**
* @defgroup KS_DATA
* @{
*****************************************************************************/
#define BIT_KS_PRESS_EVENT ((u32)0x00000001 << 8) /*Bit[8], bit for key press event*/
#define BIT_KS_RELEASE_EVENT ((u32)0x00000000 << 8) /*Bit[8], bit for key release event*/
#define BIT_KS_EVENT_FLAG ((u32)0x0000000f << 8) /*Bit[11:8], bits for keyscan event*/
#define BIT_KS_ROW_INDEX ((u32)0x0000000f << 4) /*Bit[7:4], bits for key row index*/
#define BIT_KS_COL_INDEX ((u32)0x0000000f) /*Bit[3:0], bits for key column index*/
#define BIT_KS_DATA ((u32)0x00000fff) /*Bit[11:8], bits for keyscan data*/
/** @} */
/**************************************************************************//**
* @defgroup KS_IMR
* @{
*****************************************************************************/
#define BIT_KS_SCAN_EVENT_INT_MSK ((u32)0x00000001 << 6) /*Bit[6], bit for key event interrupt mask*/
#define BIT_KS_FIFO_LIMIT_INT_MSK ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit interrupt mask*/
#define BIT_KS_FIFO_OVERFLOW_INT_MSK ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow interrupt mask*/
#define BIT_KS_FIFO_FULL_INT_MSK ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan fifo full interrupt mask*/
#define BIT_KS_SCAN_FINISH_INT_MSK ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish interrupt mask*/
#define BIT_KS_FIFO_NOTEMPTY_INT_MSK ((u32)0x00000001 << 1) /*Bit[1], bit for keyscan fifo not empty interrupt mask*/
#define BIT_KS_ALL_RELEASE_INT_MSK ((u32)0x00000001) /*Bit[0], bit for keyscan all release interrupt mask*/
#define BIT_KS_ALL_INT_MSK ((u32)0x0000007f)
/** @} */
/**************************************************************************//**
* @defgroup KS_ICR
* @{
*****************************************************************************/
#define BIT_KS_FIFO_LIMIT_INT_CLR ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit interrupt clear*/
#define BIT_KS_FIFO_OVERFLOW_INT_CLR ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow interrupt clear*/
#define BIT_KS_SCAN_FINISH_INT_CLR ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish interrupt clear*/
#define BIT_KS_ALL_RELEASE_INT_CLR ((u32)0x00000001) /*Bit[0], bit for keyscan all release interrupt clear*/
#define BIT_KS_ALL_INT_CLR ((u32)0x0000007f)
/** @} */
/**************************************************************************//**
* @defgroup KS_ISR
* @{
*****************************************************************************/
#define BIT_KS_SCAN_EVENT_INT_STATUS ((u32)0x00000001 << 6) /*Bit[6], bit for key event interrupt status*/
#define BIT_KS_FIFO_LIMIT_INT_STATUS ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit interrupt status*/
#define BIT_KS_FIFO_OVERFLOW_INT_STATUS ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow interrupt status*/
#define BIT_KS_FIFO_FULL_INT_STATUS ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan fifo full interrupt status*/
#define BIT_KS_SCAN_FINISH_INT_STATUS ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish interrupt status*/
#define BIT_KS_FIFO_NOTEMPTY_INT_STATUS ((u32)0x00000001 << 1) /*Bit[1], bit for keyscan fifo not empty interrupt status*/
#define BIT_KS_ALL_RELEASE_INT_STATUS ((u32)0x00000001) /*Bit[0], bit for keyscan all release interrupt status*/
/** @} */
/**************************************************************************//**
* @defgroup KS_ISR_RAW
* @{
*****************************************************************************/
#define BIT_KS_SCAN_EVENT_RAW_INT_STATUS ((u32)0x00000001 << 6) /*Bit[6], bit for key event raw interrupt status*/
#define BIT_KS_FIFO_LIMIT_RAW_INT_STATUS ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit raw interrupt status*/
#define BIT_KS_FIFO_OVERFLOW_RAW_INT_STATUS ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow raw interrupt status*/
#define BIT_KS_FIFO_FULL_RAW_INT_STATUS ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan fifo full raw interrupt status*/
#define BIT_KS_SCAN_FINISH_RAW_INT_STATUS ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish raw interrupt status*/
#define BIT_KS_FIFO_NOTEMPTY_RAW_INT_STATUS ((u32)0x00000001 << 1) /*Bit[1], bit for keyscan fifo not empty raw interrupt status*/
#define BIT_KS_ALL_RELEASE_RAW_INT_STATUS ((u32)0x00000001) /*Bit[0], bit for keyscan all release raw interrupt status*/
/** @} */
/**************************************************************************//**
* @defgroup KS_DUMMY
* @{
*****************************************************************************/
#define BIT_DUMMY_H ((u32)0x00000001 << 8) /*Bit[15:8], bit for Dummy_h*/
#define BIT_DUMMY_L ((u32)0x00000001 << 2) /*Bit[7:2], bit for Dummy_l*/
#define BIT_KS_DISCHARGE ((u32)0x00000001 << 1) /*Bit[1], bit for discharge the column spurious capacitance,1 for enable discharge*/
#define BIT_KS_INTERVAL_POLARITY ((u32)0x00000001) /*Bit[0], bit for configure the column polarity in debounce and interval phase,1 for drive low*/
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#endif
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_keyscan.h
|
C
|
apache-2.0
| 15,950
|
/**
******************************************************************************
* @file rtl8721d_lcdc.h
* @author
* @version V1.0.0
* @date 2017-08-07
* @brief This file contains all the functions prototypes for the LCDC firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_LCDC_H_
#define _RTL8721D_LCDC_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup LCDC
* @{
*/
/** @addtogroup LCDC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* LCDC:
* - Base Address: LCDC (0x40070000)
* - Support RGB565 data format
* - SYS_CLK: 100MHz
* - Support 8-bit /16-bit MCU i8080 parallel interface
* Support resolution of 8-/16-bit mode can be (1024x1024) for still picture display
* Support resolution of 8-bit mode can be (645x645) for animate display when refresh rate is 30F/S
* Support resolution of 16-bit mode can be (912x912) for animate display when refresh rate is 30F/S
* - MCU I/F mode supports:
* IO mode
* Trigger DMA mode
* MCU VSYNC mode
* MCU TE mode
* - Support 6-/16-bit RGB parallel Interface
* Support resolution of 6-bit mode is less than (527x527) for animate display when refresh rate is 60F/S
* Support resolution of 16-bit mode is less than (912x912) for animate display when refresh rate is 60F/S
* - RGB I/F mode supports:
* DE mode
* HV mode
* -Support LED dot matrix display interface like 04/08/12/75
* -LED I/F mode supports:
* single channel and single color mode
* single channel and two colors mode
* single channel and three colors mode
* two channel and single color mode
* two channel and two colors mode
* two channel and three colors mode
*
*****************************************************************************************
* How to use IO mode in LCDC MCU I/F mode
*****************************************************************************************
* To use the LCDC MCU I/F IO mode, the following steps are mandatory.
*
* 1. Enable LCDC peripheral clock.
*
* 2. Configure the LCDC pinmux.
*
* 3. Use the following function to set default parameters. Change other parameters if needed, such as 8 bit
* or 16 bit parallel interface, data/write/read/cs/rs pulse active level, write/read pulse width etc.
* LCDC_MCUStructInit(LCDC_MCUInitTypeDef* LCDC_MCUInitStruct);
*
* 4. Initialize the hardware use step3 parameters.
* LCDC_MCUInit(LCDC_TypeDef* LCDCx, LCDC_MCUInitTypeDef* LCDC_MCUInitStruct);
*
* 5. Enable the LCDC using the function LCDC_Cmd().
*
* 6. Send command to LCM using the function LCDC_MCUIOWriteCmd() to initialize the LCD module.
*
* 7. write/read data to/from LCM using the function LCDC_MCUIOWriteData() and LCDC_MCUIOReadData()
* and send command to LCM to drive LCD displaying.
*
*****************************************************************************************
* How to use trigger DMA mode in LCDC MCU I/F mode
*****************************************************************************************
* To use the LCDC MCU I/F trigger DMA mode, the following steps are mandatory.
*
* 1. Enable LCDC peripheral clock.
*
* 2. Configure the LCDC pinmux.
*
* 3. Configure LCDC working in MCU IO mode, send commands and parameters to LCM to initialize LCD.
*
* 4. Configure the LCDC_MCUInitStruct parameter corresponding to trigger DMA mode; change other parameters if needed.
* LCDC_MCUStructInit(LCDC_MCUInitTypeDef* LCDC_MCUInitStruct);
* LCDC_MCUInitStruct->LCDC_MCUMode = LCDC_MCU_DMA_MODE;
* LCDC_MCUInitStruct->LCDC_MCUDMAMode = LCDC_TRIGGER_DMA_MODE;
*
* 5. Configure the LCDC_MCUInitStruct parameter corresponding to plane size.
*
* 6. Initialize the hardware use step4,5 parameters.
* LCDC_MCUInit(LCDC_TypeDef* LCDCx, LCDC_MCUInitTypeDef* LCDC_MCUInitStruct)
*
* 7. Configure the LCDC DMA parameters using the function LCDC_DMAModeConfig(), malloc image buffer and arrange
* image base address using the function LCDC_DMAImageBaseAddrConfig().
*
* 8. Enable LCDC interrupt if needed using the function LCDC_INTConfig().
*
* 9. Enable the LCDC using the function LCDC_Cmd().
*
* 10. Trigger one frame transfer using the function LCDC_MCUDMATrigger() and update the image buffer to change
* the display effect.
*
*****************************************************************************************
* How to use VSYNC mode in LCDC MCU I/F mode
*****************************************************************************************
* To use the LCDC MCU I/F VSYNC mode, the following steps are mandatory.
*
* 1. Enable LCDC peripheral clock.
*
* 2. Configure the LCDC pinmux.
*
* 3. Configure LCDC working in MCU IO mode, send commands and parameters to LCM to let LCD working in VSYNC mode.
*
* 4. Configure the LCDC_MCUInitStruct parameter corresponding to VSYNC mode; change other parameters if needed, such as
* VSYNC pulse active level, VSYNC pulse width, VSYNC idle period.
* LCDC_MCUStructInit(LCDC_MCUInitTypeDef* LCDC_MCUInitStruct);
* LCDC_MCUInitStruct->LCDC_MCUMode = LCDC_MCU_DMA_MODE;
* LCDC_MCUInitStruct->LCDC_MCUDMAMode = LCDC_AUTO_DMA_MODE;
* LCDC_MCUInitStruct->LCDC_MCUSyncMode = LCDC_MCU_SYNC_WITH_VSYNC;
*
* 5. Configure the LCDC_MCUInitStruct parameter corresponding to plane size.
*
* 6. Initialize the hardware use step4,5 parameters.
* LCDC_MCUInit(LCDC_TypeDef* LCDCx, LCDC_MCUInitTypeDef* LCDC_MCUInitStruct)
*
* 7. Configure the LCDC DMA parameters using the function LCDC_DMAModeConfig(), malloc image buffer and arrange
* image base address using the function LCDC_DMAImageBaseAddrConfig().
*
* 8. Enable the specified LCDC interrupt if needed using the function LCDC_INTConfig().
*
* 9. Enable the LCDC using the function LCDC_Cmd().
*
* 10. The LCDC can transfer image data to LCM automatically synchronized with the VSYNC signal and you can update the
* image buffer to change the display effect.
*
*****************************************************************************************
* How to use TE mode in LCDC MCU I/F mode
*****************************************************************************************
* To use the LCDC MCU I/F TE mode, the following steps are mandatory.
*
* 1. Enable LCDC peripheral clock.
*
* 2. Configure the LCDC pinmux.
*
* 3. Configure LCDC working in MCU IO mode, send commands and parameters to LCM to let LCD working in TE mode.
*
* 4. Configure the LCDC_MCUInitStruct parameter corresponding to VSYNC mode; change other parameters if needed, such as
* VSYNC pulse active level, VSYNC pulse width, VSYNC idle period etc.
* LCDC_MCUStructInit(LCDC_MCUInitTypeDef* LCDC_MCUInitStruct);
* LCDC_MCUInitStruct->LCDC_MCUMode = LCDC_MCU_DMA_MODE;
* LCDC_MCUInitStruct->LCDC_MCUDMAMode = LCDC_AUTO_DMA_MODE;
* LCDC_MCUInitStruct->LCDC_MCUSyncMode = LCDC_MCU_SYNC_WITH_TE;
*
* 5. Configure the LCDC_MCUInitStruct parameter corresponding to plane size.
*
* 6. Initialize the hardware use step 4,5 parameters.
* LCDC_MCUInit(LCDC_TypeDef* LCDCx, LCDC_MCUInitTypeDef* LCDC_MCUInitStruct)
*
* 7. Configure the LCDC DMA parameters using the function LCDC_DMAModeConfig(), malloc image buffer and arrange
* image base address using the function LCDC_DMAImageBaseAddrConfig().
*
* 8. Enable the specified LCDC interrupt if needed using the function LCDC_INTConfig().
*
* 9. Enable the LCDC using the function LCDC_Cmd().
*
* 10. The LCDC can transfer image data to LCM automatically synchronized with the TE signal from LCM and you can update the
* image buffer to change the display effect.
*
*****************************************************************************************
* How to use DE mode in LCDC RGB I/F mode
*****************************************************************************************
* To use the LCDC RGB I/F DE mode, the following steps are mandatory.
*
* 1. Enable LCDC peripheral clock.
*
* 2. Configure the LCDC pinmux.
*
* 3. Configure LCM parameters through SPI or other interfaces if needed.
*
* 4. Configure the LCDC_RGBInitStruct parameter corresponding to DE mode; change other parameters if needed, such as
* data pulse polarity, ENABLE signal active level, VSYNC pulse active level, HSYNC pulse active level, dot clock active edge,
* VFP, VBP, VSW, HBP, HFP, HSW, refresh frequency etc.
* LCDC_RGBStructInit(LCDC_RGBInitTypeDef * LCDC_RGBInitStruct);
* LCDC_RGBInitStruct->LCDC_RGBSyncMode = LCDC_RGB_DE_MODE;
*
* 5. Configure the LCDC_RGBInitStruct parameter corresponding to plane size.
*
* 6. Initialize the hardware use step 4,5 parameters.
* LCDC_RGBInit(LCDC_TypeDef* LCDCx, LCDC_RGBInitTypeDef* LCDC_RGBInitStruct)
*
* 7. Configure the LCDC DMA parameters: set burst size using the function LCDC_DMAModeConfig(),
* set DMA FIFO under flow mode and error data using the functions LCDC_DMAUnderFlowModeConfig() and
* LCDC_DMAUnderFlowModeConfig(), malloc image buffer and arrange image base address using the function
* LCDC_DMAImageBaseAddrConfig().
*
* 8. Enable the specified LCDC interrupt if needed using the functions LCDC_INTConfig() and LCDC_LineINTPosConfig().
*
* 9. Enable the LCDC using the function LCDC_Cmd().
*
* 10. The LCDC can transfer image data to LCM automatically according to the refresh frequency and you can update the
* image buffer to change the display effect.
*
*****************************************************************************************
* How to use HV mode in LCDC RGB I/F mode
*****************************************************************************************
* To use the LCDC RGB I/F HV mode, the following steps are mandatory.
*
* 1. Enable LCDC peripheral clock.
*
* 2. Configure the LCDC pinmux.
*
* 3. Configure LCM parameters through SPI or other interfaces if needed.
*
* 4. Configure the LCDC_RGBInitStruct parameter corresponding to DE mode; change other parameters if needed, such as
* data pulse polarity, VSYNC pulse active level, HSYNC pulse active level, dot clock active edge,
* VFP, VBP, VSW, HBP, HFP, HSW, 6 bit parallel I/F or 16 bit parallel I/F mode, refresh frequency.
* LCDC_RGBStructInit(LCDC_RGBInitTypeDef * LCDC_RGBInitStruct);
*
* 5. Configure the LCDC_RGBInitStruct parameter corresponding to plane size.
*
* 6. Initialize the hardware use step 4,5 parameters.
* LCDC_RGBInit(LCDC_TypeDef* LCDCx, LCDC_RGBInitTypeDef* LCDC_RGBInitStruct)
*
* 7. Configure the LCDC DMA parameters: set burst size using the function LCDC_DMAModeConfig(),
* set DMA FIFO under flow mode and error data using the functions LCDC_DMAUnderFlowModeConfig() and
* LCDC_DMAUnderFlowModeConfig(), malloc image buffer and arrange image base address using the function
* LCDC_DMAImageBaseAddrConfig().
*
* 8. Enable the specified LCDC interrupt if needed using the functions LCDC_INTConfig() and LCDC_LineINTPosConfig().
*
* 9. Enable the LCDC using the function LCDC_Cmd().
*
* 10. The LCDC can transfer image data to LCM automatically according to the refresh frequency and you can update the
* image buffer to change the display effect.
*
*****************************************************************************************
* How to use LCDC LED I/F mode
*****************************************************************************************
* To use the LCDC LED I/F mode, the following steps are mandatory.
*
* 1. Enable LCDC peripheral clock.
*
* 2. Configure the LCDC pinmux.
*
* 3. Configure the LCDC_LEDInitStruct parameter corresponding to LED I/F mode; change other parameters if needed, such as
* color channel, color numbers, timing(latch start time, latch pulse width, OE active width), refresh frequency.
* LCDC_LEDStructInit(LCDC_LEDInitTypeDef * LCDC_LEDInitStruct)
*
* 4. Configure the LCDC_LEDInitStruct parameter corresponding to plane size.
*
* 5. Initialize the hardware use step 3, 4 parameters.
* LCDC_LEDInit(LCDC_TypeDef* LCDCx, LCDC_LEDInitTypeDef* LCDC_LEDInitStruct)
*
* 6. Configure the LCDC DMA parameters: set burst size using the function LCDC_DMAModeConfig(), malloc image buffer
* and arrange image base address using the function LCDC_DMAImageBaseAddrConfig().
*
* 7. Enable the specified LCDC interrupt if needed using the functions LCDC_INTConfig() and LCDC_LineINTPosConfig().
*
* 8. Enable the LCDC using the function LCDC_Cmd().
*
* 9. The LCDC can transfer image data to LED array board automatically according to the refresh frequency and you can update the
* image buffer to change the display effect.
*
*****************************************************************************************
* @endverbatim
*/
/*===================================================================================================*/
#define LCDC_SYS_CLK (100000000)
/*===================================================================================================*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup LCDC_Exported_Types LCDC Exported Types
* @{
*/
/**
* @brief LCDC MCU I/F Mode Initialization structure definition
*/
typedef struct
{
u32 LCDC_MCUIfMode; /*!< Specifies the LCDC MCU Interface Mode.
This parameter can be a value of @ref LCDC_MCU_IF_MODE_define. */
u32 LCDC_MCUMode; /*!< Specifies the LCDC MCU Mode.
This parameter can be a value of @ref LCDC_MCU_MODE_define. */
u32 LCDC_MCUDMAMode; /*!< Specifies the LCDC MCU DMA Mode.
This parameter can be a value of @ref LCDC_DMA_MODE_define. */
u32 LCDC_MCUImgHeight; /*!< Specifies the height of the LCDC PlANE SIZE.
This parameter can be a number between 0x000 and 0xfff. */
u32 LCDC_MCUImgWidth; /*!< Specifies the width of the LCDC PlANE SIZE.
This parameter can be a number between 0x000 and 0xfff. */
u32 LCDC_MCUSyncMode; /*!< Specifies the LCDC MCU synchronize mode.
This parameter can be a value of @ref LCDC_MCU_SYNC_MODE_define. */
u32 LCDC_MCUVsyncPulPlrty; /*!< Specifies the LCDC MCU vsync pulse polarity.
This parameter can be a value of @ref LCDC_MCU_VSYNC_PUL_POLARITY_define. */
u32 LCDC_MCUTEPulPlrty; /*!< Specifies the LCDC MCU TE pulse polarity.
This parameter can be a value of @ref LCDC_MCU_TE_PUL_POLARITY_define.*/
u32 LCDC_MCUTEDelay; /*!< Specifies the LCDC MCU TE delay interval, This interval is from
detected TE signal to starting frame transfer. For more details of this value,
refer to the TEDELAY field in register LCDC_MCU_CFG in the LCDC Specification.
This parameter can be a number between 5 and 65539. Unit: WR pulse width. */
u32 LCDC_MCUDataPulPlrty; /*!< Specifies the LCDC MCU data pulse polarity.
This parameter can be a value of @ref LCDC_MCU_DATA_PUL_POLARITY_define. */
u32 LCDC_MCURdPulPlrty; /*!< Specifies the LCDC MCU read pulse polarity.
This parameter can be a value of @ref LCDC_MCU_READ_PUL_POLARITY_define. */
u32 LCDC_MCUWrPulPlrty; /*!< Specifies the LCDC MCU write pulse polarity.
This parameter can be a value of @ref LCDC_MCU_WRITE_PUL_POLARITY_define. */
u32 LCDC_MCURsPulPlrty; /*!< Specifies the LCDC MCU RS pulse polarity.
This parameter can be a value of @ref LCDC_MCU_RS_PUL_POLARITY_define. */
u32 LCDC_MCUCsPulPlrty; /*!< Specifies the LCDC MCU CS pulse polarity.
This parameter can be a value of @ref LCDC_MCU_CS_PUL_POLARITY_define. */
u32 LCDC_MCUVsyncIdlePrd; /*!< Specifies the LCDC MCU VSYNC idle polarity. Unit: Write Pulse width.
This parameter can be a number between 0x0005 and (0x100000-0x5). */
u32 LCDC_MCUVsyncSigWidth; /*!< Specifies the LCDC MCU VSYNC signal width. Unit: Write Pulse width.
This parameter can be a number between 0x01 and 0x100. */
u32 LCDC_MCURdInacvWidth; /*!< Specifies the LCDC MCU Read Inactive pulse width. Unit: SYS_Clk.
This parameter can be a number between 0x01 and 0x800. */
u32 LCDC_MCURdAcvWidth; /*!< Specifies the LCDC MCU Read active pulse width. Unit: SYS_Clk.
This parameter can be a number between 0x01 and 0x800. */
u32 LCDC_MCUWrPulWidth; /*!< Specifies the LCDC MCU write active pulse width. Unit: SYS_Clk.
This parameter can be a even number between 0x02 and (0x400). */
u32 LCDC_MCUIOTimeOutClkNum; /*!< Specifies the LCDC MCU IO write/read timeout clock number. Unit: write clock.
This parameter can be a even number between 0x0 and 0xFFFF. */
} LCDC_MCUInitTypeDef;
/**
* @brief LCDC RGB I/F Mode Initialization structure definition
*
*/
typedef struct
{
u32 LCDC_RGBIfMode; /*!< Specifies the LCDC RGB Interface Mode.
This parameter can be a value of @ref LCDC_RGB_IF_MODE_define */
u32 LCDC_RGBImgHeight; /*!< Specifies the height of the LCDC PlANE SIZE.
This parameter can be a number between 0x000 and 0xfff. */
u32 LCDC_RGBImgWidth; /*!< Specifies the width of the LCDC PlANE SIZE.
This parameter can be a number between 0x000 and 0xfff. */
u32 LCDC_RGBRefreshFreq; /*!< Specifies the RGB frame refresh frequency.
This parameter can be a number between 0x000 and 0xfff.*/
u32 LCDC_RGBSyncMode; /*!< Specifies the RGB frame synchronize Mode.
This parameter can be a value of @ref LCDC_RGB_SYNC_MODE_define */
u32 LCDC_RGBDatPulPlrty; /*!< Specifies the RGB data pulse polariy.
This parameter can be a value of @ref LCDC_RGB_DATA_PUL_POLARITY_define */
u32 LCDC_RGBEnPulPlrty; /*!< Specifies the RGB ENABLE pulse polariy.
This parameter can be a value of @ref LCDC_RGB_ENABLE_PUL_POLARITY_define */
u32 LCDC_RGBHsPulPlrty; /*!< Specifies the RGB HSYNC pulse polariy.
This parameter can be a value of @ref LCDC_RGB_HSYNC_PUL_POLARITY_define */
u32 LCDC_RGBVsPulPlrty; /*!< Specifies the RGB VSYNC pulse polariy.
This parameter can be a value of @ref LCDC_RGB_VSYNC_PUL_POLARITY_define */
u32 LCDC_RGBDclkActvEdge; /*!< Specifies the RGB DCLK active edge.
This parameter can be a value of @ref LCDC_RGB_DCLK_ACTIVE_EDGE_define */
u32 LCDC_RGBVFP; /*!< Specifies the front porch line number.
This parameter can be a number between 0x1 and 0x10. Unit: line*/
u32 LCDC_RGBVBP; /*!< Specifies the back porch line number.
This parameter can be a number between 0x1 and 0x10. Unit: line*/
u32 LCDC_RGBVSW; /*!< Specifies the vertical signal width.
This parameter can be a number between 0x1 and 0x10. Unit: line*/
u32 LCDC_RGBHFP; /*!< Specifies the Horizontal front porch Unit: DCLK.
This parameter can be a number between 0x01 and 0x100. Unit: DCLK*/
u32 LCDC_RGBHBP; /*!< Specifies the Horizontal back porch Unit: DCLK.
This parameter can be a number between 0x01 and 0x100. Unit: DCLK*/
u32 LCDC_RGBHSW; /*!< Specifies the Horizontal sync signal width.
This parameter can be a number between 0x01 and 0x100. Unit: DCLK*/
} LCDC_RGBInitTypeDef;
/**
* @brief LCDC LED I/F Mode Initialization structure definition
*
*/
typedef struct
{
u32 LCDC_LEDIfMode; /*!< Specifies the LCDC LED Interface Mode.
This parameter can be a value of @ref LCDC_LED_IF_MODE_define */
u32 LCDC_LEDImgHeight; /*!< Specifies the height of the LED PlANE SIZE.
This parameter can be a number between 0x000 and 0xfff. */
u32 LCDC_LEDImgWidth; /*!< Specifies the width of the LED PlANE SIZE.
This parameter can be a number between 0x000 and 0xfff. */
u32 LCDC_LEDRefreshFreq; /*!< Specifies the LED frame refresh frequency.
This parameter can be a number between 0x000 and 0xfff.*/
u32 LCDC_LEDColorChnl; /*!< Specifies the LED I/F color channel.
This parameter can be a value of @ref LCDC_LED_COLOR_CHANNEL_define */
u32 LCDC_LEDColorNum; /*!< Specifies the LED I/F color number.
This parameter can be a value of @ref LCDC_LED_COLOR_NUMBER_define */
u32 LCDC_LEDClkPlrty; /*!< Specifies the LED I/F DCLK polarity.
This parameter can be a value of @ref LCDC_LED_DCLK_POLARITY_define */
u32 LCDC_LEDOePlrty; /*!< Specifies the LED I/F OE pulse polarity.
This parameter can be a value of @ref LCDC_LED_OE_POLARITY_define */
u32 LCDC_LEDLatPlrty; /*!< Specifies the LED I/F Latch polarity.
This parameter can be a value of @ref LCDC_LED_LATCH_POLARITY_define */
u32 LCDC_LEDDatPlrty; /*!< Specifies the LED I/F Data polarity.
This parameter can be a value of @ref LCDC_LED_Data_POLARITY_define */
u32 LCDC_LEDOEActw; /*!< Specifies the LED I/F OE Active Width Time.
This parameter can be a number between 0x001 and 0x1000. Unit: DCLK */
u32 LCDC_LEDLatchWidth; /*!< Specifies the LED I/F LAT Width Time.
This parameter can be a number between 0x01 and 0x100. Unit: DCLK */
u32 LCDC_LEDFrmIdlePd; /*!< Specifies the LED I/F Frame dile period.
This parameter can be a number between 0x001 and 0x1000. Unit: DCLK */
u32 LCDC_LEDLineIdlePd; /*!< Specifies the LED I/F Line idle period.
This parameter can be a number between 0x01 and 0x100. Unit: DCLK */
}LCDC_LEDInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LCDC_Exported_Constants LCDC Exported Constants
* @{
*/
/** @defgroup LCDC_MCU_IF_MODE_define
* @{
*/
#define LCDC_MCU_IF_8_BIT ((u32)0x00000000)
#define LCDC_MCU_IF_16_BIT ((u32)0x00010000)
#define IS_LCDC_MCU_IF_MODE(MODE) (((MODE) == LCDC_MCU_IF_8_BIT) || \
((MODE) == LCDC_MCU_IF_16_BIT))
/**
* @}
*/
/** @defgroup LCDC_MCU_MODE_define
* @{
*/
#define LCDC_MCU_DMA_MODE ((u32)0x00000000)
#define LCDC_MCU_IO_MODE ((u32)0x00000800)
#define IS_LCDC_MCU_MODE(MODE) (((MODE) == LCDC_MCU_IO_MODE) || \
((MODE) == LCDC_MCU_DMA_MODE))
/**
* @}
*/
/** @defgroup LCDC_DMA_MODE_define
* @{
*/
#define LCDC_AUTO_DMA_MODE ((u32)0x00000000)
#define LCDC_TRIGGER_DMA_MODE ((u32)0x00000001)
#define IS_LCDC_DMA_MODE(MODE) (((MODE) == LCDC_AUTO_DMA_MODE) || \
((MODE) == LCDC_TRIGGER_DMA_MODE))
/**
* @}
*/
/** @defgroup LCDC_MCU_SYNC_MODE_define
* @{
*/
#define LCDC_MCU_SYNC_WITH_INTERNAL_CLK ((u32)0x00000000)
#define LCDC_MCU_SYNC_WITH_VSYNC ((u32)0x00000200)
#define LCDC_MCU_SYNC_WITH_TE ((u32)0x00000400)
#define IS_LCDC_MCU_SYNC_MODE(MODE) (((MODE) == LCDC_MCU_SYNC_WITH_INTERNAL_CLK) || \
((MODE) == LCDC_MCU_SYNC_WITH_VSYNC) || \
((MODE) == LCDC_MCU_SYNC_WITH_TE))
/**
* @}
*/
/** @defgroup LCDC_MCU_VSYNC_PUL_POLARITY_define
* @{
*/
#define LCDC_MCU_VSYNC_PUL_LOW_LEV_ACTIVE ((u32)0x00000000)
#define LCDC_MCU_VSYNC_PUL_HIGH_LEV_ACTIVE ((u32)0x00000040)
#define IS_LCDC_MCU_VSYNC_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_MCU_VSYNC_PUL_LOW_LEV_ACTIVE) || \
((POLARITY) == LCDC_MCU_VSYNC_PUL_HIGH_LEV_ACTIVE))
/**
* @}
*/
/** @defgroup LCDC_MCU_TE_PUL_POLARITY_define
* @{
*/
#define LCDC_MCU_TE_PUL_LOW_LEV_ACTIVE ((u32)0x00000000)
#define LCDC_MCU_TE_PUL_HIGH_LEV_ACTIVE ((u32)0x00000020)
#define IS_LCDC_MCU_TE_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_MCU_TE_PUL_LOW_LEV_ACTIVE) || \
((POLARITY) == LCDC_MCU_TE_PUL_HIGH_LEV_ACTIVE))
/**
* @}
*/
/** @defgroup LCDC_MCU_DATA_PUL_POLARITY_define
* @{
*/
#define LCDC_MCU_DAT_PUL_NORMAL ((u32)0x00000000)
#define LCDC_MCU_DAT_PUL_INVERT ((u32)0x00000010)
#define IS_LCDC_MCU_DAT_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_MCU_DAT_PUL_NORMAL) || \
((POLARITY) == LCDC_MCU_DAT_PUL_INVERT))
/**
* @}
*/
/** @defgroup LCDC_MCU_READ_PUL_POLARITY_define
* @{
*/
#define LCDC_MCU_RD_PUL_RISING_EDGE_FETCH ((u32)0x00000000)
#define LCDC_MCU_RD_PUL_FALLING_EDGE_FETCH ((u32)0x00000008)
#define IS_LCDC_MCU_RD_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_MCU_RD_PUL_RISING_EDGE_FETCH) || \
((POLARITY) == LCDC_MCU_RD_PUL_FALLING_EDGE_FETCH))
/**
* @}
*/
/** @defgroup LCDC_MCU_WRITE_PUL_POLARITY_define
* @{
*/
#define LCDC_MCU_WR_PUL_RISING_EDGE_FETCH ((u32)0x00000000)
#define LCDC_MCU_WR_PUL_FALLING_EDGE_FETCH ((u32)0x00000004)
#define IS_LCDC_MCU_WR_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_MCU_WR_PUL_RISING_EDGE_FETCH) || \
((POLARITY) == LCDC_MCU_WR_PUL_FALLING_EDGE_FETCH))
/**
* @}
*/
/** @defgroup LCDC_MCU_RS_PUL_POLARITY_define
* @{
*/
#define LCDC_MCU_RS_PUL_LOW_LEV_CMD_ADDR ((u32)0x00000000)
#define LCDC_MCU_RS_PUL_HIGH_LEV_CMD_ADDR ((u32)0x00000002)
#define IS_LCDC_MCU_RS_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_MCU_RS_PUL_LOW_LEV_CMD_ADDR) || \
((POLARITY) == LCDC_MCU_RS_PUL_HIGH_LEV_CMD_ADDR))
/**
* @}
*/
/** @defgroup LCDC_MCU_CS_PUL_POLARITY_define
* @{
*/
#define LCDC_MCU_CS_PUL_LOW_LEV_ACTIVE ((u32)0x00000000)
#define LCDC_MCU_CS_PUL_HIGH_LEV_ACTIVE ((u32)0x00000001)
#define IS_LCDC_MCU_CS_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_MCU_CS_PUL_LOW_LEV_ACTIVE) || \
((POLARITY) == LCDC_MCU_CS_PUL_HIGH_LEV_ACTIVE))
/**
* @}
*/
/** @defgroup LCDC_RGB_IF_MODE_define
* @{
*/
#define LCDC_RGB_IF_6_BIT ((u32)0x00080000)
#define LCDC_RGB_IF_16_BIT ((u32)0x00090000)
#define IS_LCDC_RGB_IF_MODE(MODE) (((MODE) == LCDC_RGB_IF_6_BIT) || \
((MODE) == LCDC_RGB_IF_16_BIT))
/**
* @}
*/
/** @defgroup LCDC_RGB_SYNC_MODE_define
* @{
*/
#define LCDC_RGB_DE_MODE ((u32)0x00000000)
#define LCDC_RGB_HV_MODE ((u32)0x02000000)
#define IS_LCDC_RGB_SYNC_MODE(MODE) (((MODE) == LCDC_RGB_DE_MODE) || \
((MODE) == LCDC_RGB_HV_MODE))
/**
* @}
*/
/** @defgroup LCDC_RGB_DATA_PUL_POLARITY_define
* @{
*/
#define LCDC_RGB_DAT_PUL_NORMAL ((u32)0x00000000)
#define LCDC_RGB_DAT_PUL_INVERT ((u32)0x00100000)
#define IS_LCDC_RGB_DAT_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_RGB_DAT_PUL_NORMAL) || \
((POLARITY) == LCDC_RGB_DAT_PUL_INVERT))
/**
* @}
*/
/** @defgroup LCDC_RGB_ENABLE_PUL_POLARITY_define
* @{
*/
#define LCDC_RGB_EN_PUL_LOW_LEV_ACTIVE ((u32)0x00000000)
#define LCDC_RGB_EN_PUL_HIGH_LEV_ACTIVE ((u32)0x00080000)
#define IS_LCDC_RGB_EN_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_RGB_EN_PUL_LOW_LEV_ACTIVE) || \
((POLARITY) == LCDC_RGB_EN_PUL_HIGH_LEV_ACTIVE))
/**
* @}
*/
/** @defgroup LCDC_RGB_HSYNC_PUL_POLARITY_define
* @{
*/
#define LCDC_RGB_HS_PUL_LOW_LEV_SYNC ((u32)0x00000000)
#define LCDC_RGB_HS_PUL_HIGH_LEV_SYNC ((u32)0x00040000)
#define IS_LCDC_RGB_HS_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_RGB_HS_PUL_LOW_LEV_SYNC) || \
((POLARITY) == LCDC_RGB_HS_PUL_HIGH_LEV_SYNC))
/**
* @}
*/
/** @defgroup LCDC_RGB_VSYNC_PUL_POLARITY_define
* @{
*/
#define LCDC_RGB_VS_PUL_LOW_LEV_SYNC ((u32)0x00000000)
#define LCDC_RGB_VS_PUL_HIGH_LEV_SYNC ((u32)0x00020000)
#define IS_LCDC_RGB_VS_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_RGB_VS_PUL_LOW_LEV_SYNC) || \
((POLARITY) == LCDC_RGB_VS_PUL_HIGH_LEV_SYNC))
/**
* @}
*/
/** @defgroup LCDC_RGB_DCLK_ACTIVE_EDGE_define
* @{
*/
#define LCDC_RGB_DCLK_RISING_EDGE_FETCH ((u32)0x00000000)
#define LCDC_RGB_DCLK_FALLING_EDGE_FETCH ((u32)0x00010000)
#define IS_LCDC_RGB_DCLK_EDGE(EDGE) (((EDGE) == LCDC_RGB_DCLK_RISING_EDGE_FETCH) || \
((EDGE) == LCDC_RGB_DCLK_FALLING_EDGE_FETCH))
/**
* @}
*/
/** @defgroup LCDC_LED_IF_MODE_define
* @{
*/
#define LCDC_LED_IF ((u32)0x000f0000)
#define IS_LCDC_LED_IF_MODE(MODE) (((MODE) == LCDC_LED_IF))
/**
* @}
*/
/** @defgroup LCDC_LED_COLOR_CHANNEL_define
* @{
*/
#define LCDC_LED_ONE_CHANNEL ((u32)0x00000000)
#define LCDC_LED_TWO_CHANNEL ((u32)0x00000004)
#define IS_LCDC_LED_CHANNEL(CHANNEL) (((CHANNEL) == LCDC_LED_ONE_CHANNEL) || \
((CHANNEL) == LCDC_LED_TWO_CHANNEL))
/**
* @}
*/
/** @defgroup LCDC_LED_COLOR_NUMBER_define
* @{
*/
#define LCDC_LED_ONE_COLOR ((u32)0x00000000)
#define LCDC_LED_TWO_COLOR ((u32)0x00000001)
#define LCDC_LED_THREE_COLOR ((u32)0x00000002)
#define IS_LCDC_LED_COLOR_NUM(NUM) (((NUM) == LCDC_LED_ONE_COLOR) || \
((NUM) == LCDC_LED_TWO_COLOR) || \
((NUM) == LCDC_LED_THREE_COLOR))
/**
* @}
*/
/** @defgroup LCDC_LED_DCLK_POLARITY_define
* @{
*/
#define LCDC_LED_DCLK_RISING_EDGE_FETCH ((u32)0x00000000)
#define LCDC_LED_DCLK_FALLING_EDGE_FETCH ((u32)0x00000010)
#define IS_LCDC_LED_DCLK_EDGE(EDGE) (((EDGE) == LCDC_LED_DCLK_RISING_EDGE_FETCH) || \
((EDGE) == LCDC_LED_DCLK_FALLING_EDGE_FETCH))
/**
* @}
*/
/** @defgroup LCDC_LED_LATCH_POLARITY_define
* @{
*/
#define LCDC_LED_LACTH_RISING_EDGE_FETCH ((u32)0x00000000)
#define LCDC_LED_LATCH_FALLING_EDGE_FETCH ((u32)0x00000020)
#define IS_LCDC_LED_LATCH_EDGE(EDGE) (((EDGE) == LCDC_LED_LACTH_RISING_EDGE_FETCH) || \
((EDGE) == LCDC_LED_LATCH_FALLING_EDGE_FETCH))
/**
* @}
*/
/** @defgroup LCDC_LED_OE_POLARITY_define
* @{
*/
#define LCDC_LED_OE_LOW_LEV_ACTIVE ((u32)0x00000000)
#define LCDC_LED_OE_HIGH_LEV_ACTIVE ((u32)0x00000040)
#define IS_LCDC_LED_OE_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_LED_OE_LOW_LEV_ACTIVE) || \
((POLARITY) == LCDC_LED_OE_HIGH_LEV_ACTIVE))
/**
* @}
*/
/** @defgroup LCDC_LED_DATA_POLARITY_define
* @{
*/
#define LCDC_LED_DAT_PUL_NORMAL ((u32)0x00000000)
#define LCDC_LED_DAT_PUL_INVERT ((u32)0x00000080)
#define IS_LCDC_LED_DAT_PUL_POLARITY(POLARITY) (((POLARITY) == LCDC_LED_DAT_PUL_NORMAL) || \
((POLARITY) == LCDC_LED_DAT_PUL_INVERT))
/**
* @}
*/
/** @defgroup LCDC_DMA_UNDERFLOW_MODE_define
* @{
*/
#define LCDC_DMAUNFW_OUTPUT_LASTDATA ((u32)0x00000000)
#define LCDC_DMAUNFW_OUTPUT_ERRORDATA ((u32)0x02000000)
#define IS_LCDC_DMA_DMA_UNDERFLOW_MODE(MODE) (((MODE) == LCDC_DMAUNFW_OUTPUT_LASTDATA) || \
((MODE) == LCDC_DMAUNFW_OUTPUT_ERRORDATA))
/**
* @}
*/
/** @defgroup LCDC_INTERRUPTS_define
* @{
*/
#define LCDC_IT_FRM_START ((u32)0x00000020)
#define LCDC_IT_IO_TIMEOUT ((u32)0x00000010)
#define LCDC_IT_LINE ((u32)0x00000008)
#define LCDC_IT_FRDN ((u32)0x00000004)
#define LCDC_IT_DMAUNDFW ((u32)0x00000001)
#define IS_LCDC_CONFIG_IT(IT) (((IT) == LCDC_IT_DMAUNDFW) || \
((IT) == LCDC_IT_FRDN) || \
((IT) == LCDC_IT_LINE)|| \
((IT) == LCDC_IT_IO_TIMEOUT)|| \
((IT) == LCDC_IT_FRM_START))
#define IS_LCDC_CLEAR_IT(IT) ((((IT) & (u32)0xFFFFFFC2) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup LCDC_type_define
* @{
*/
#define IS_LCDC_ALL_PERIPH(PERIPH) (PERIPH == LCDC)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LCDC_Exported_Functions LCDC Exported Functions
* @{
*/
/** @defgroup LCDC_MCU_Interface_functions
* @{
*/
_LONG_CALL_ void LCDC_MCUStructInit(LCDC_MCUInitTypeDef* LCDC_MCUInitStruct);
_LONG_CALL_ void LCDC_MCUInit(LCDC_TypeDef* LCDCx, LCDC_MCUInitTypeDef* LCDC_MCUInitStruct);
_LONG_CALL_ void LCDC_MCUDMATrigger(LCDC_TypeDef* LCDCx);
_LONG_CALL_ u32 LCDC_MCUGetRunStatus(LCDC_TypeDef* LCDCx);
_LONG_CALL_ void LCDC_MCUIOWriteData(LCDC_TypeDef* LCDCx, u16 Data);
_LONG_CALL_ u16 LCDC_MCUIOReadData(LCDC_TypeDef* LCDCx);
_LONG_CALL_ void LCDC_MCUIOWriteCmd(LCDC_TypeDef* LCDCx, u16 Cmd);
/**
* @}
*/
/** @defgroup LCDC_RGB_Interface_functions
* @{
*/
_LONG_CALL_ void LCDC_RGBStructInit(LCDC_RGBInitTypeDef * LCDC_RGBInitStruct);
_LONG_CALL_ void LCDC_RGBInit(LCDC_TypeDef* LCDCx, LCDC_RGBInitTypeDef* LCDC_RGBInitStruct);
_LONG_CALL_ void LCDC_RGBGetSyncStatus(LCDC_TypeDef* LCDCx, u32 * pHSStatus, u32 * pVSStatus);
/**
* @}
*/
/** @defgroup LCDC_LED_Interface_functions
* @{
*/
_LONG_CALL_ void LCDC_LEDStructInit(LCDC_LEDInitTypeDef * LCDC_LEDInitStruct);
_LONG_CALL_ void LCDC_LEDInit(LCDC_TypeDef* LCDCx, LCDC_LEDInitTypeDef* LCDC_LEDInitStruct);
_LONG_CALL_ void LCDC_LEDSetOEWidth(LCDC_TypeDef* LCDCx, u32 OEActvWidth);
/**
* @}
*/
/** @defgroup LCDC_DMA_Configure_functions
* @{
*/
_LONG_CALL_ void LCDC_DMAModeConfig(LCDC_TypeDef* LCDCx, u32 BurstSize);
_LONG_CALL_ void LCDC_DMAUnderFlowConfig(LCDC_TypeDef* LCDCx, u32 DmaUnFlwMode, u32 ErrorData);
_LONG_CALL_ void LCDC_DMAImageBaseAddrConfig(LCDC_TypeDef* LCDCx, u32 ImgBaseAddr);
/**
* @}
*/
/** @defgroup LCDC_Interrupt_functions
* @{
*/
_LONG_CALL_ void LCDC_INTConfig(LCDC_TypeDef* LCDCx, u32 LCDC_IT, u32 NewState);
_LONG_CALL_ void LCDC_LineINTPosConfig(LCDC_TypeDef* LCDCx, u32 LineNum);
_LONG_CALL_ u32 LCDC_GetINTStatus(LCDC_TypeDef* LCDCx);
_LONG_CALL_ u32 LCDC_GetRawINTStatus(LCDC_TypeDef* LCDCx);
_LONG_CALL_ void LCDC_ClearAllINT(LCDC_TypeDef* LCDCx);
_LONG_CALL_ void LCDC_ClearINT(LCDC_TypeDef* LCDCx, u32 LCDC_IT);
_LONG_CALL_ void LCDC_GetCurPosStatus(LCDC_TypeDef* LCDCx, u32* pCurPosX, u32* pCurPosY);
_LONG_CALL_ void LCDC_GetDmaUnINTCnt(LCDC_TypeDef* LCDCx, u32* DmaUnIntCnt);
/**
* @}
*/
/** @defgroup LCDC_global_functions
* @{
*/
_LONG_CALL_ void LCDC_Cmd(LCDC_TypeDef* LCDCx, u32 NewState);
_LONG_CALL_ void LCDC_InsDisable(LCDC_TypeDef* LCDCx);
_LONG_CALL_ void LCDC_DeInit(LCDC_TypeDef* LCDCx);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup LCDC_Register_Definitions LCDC Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup LCDC_CTRL
* @{
*****************************************************************************/
#define LCDC_CTRL_LCDCEN ((u32)0x00000001) /*BIT[0], Enable LCDC*/
#define LCDC_CTRL_LCDCDIS ((u32)0x00000001<<1) /*BIT[1], Disable LCDC*/
#define LCDC_CTRL_LCDCINSDIS ((u32)0x00000001<<2) /*BIT[2], Disable LCDC instantly*/
#define LCDC_CTRL_IF_MODE ((u32)0x000F0000) /*LCDC_CTRL[19:16], bit field for LCDC Interface Mode*/
#define LCDC_CTRL_8_BIT_MCU ((u32)0x00000000) /*LCDC_CTRL[19:16]=0000B, 8 bit MCU I/F*/
#define LCDC_CTRL_16_BIT_MCU ((u32)0x00010000) /*LCDC_CTRL[19:16]=0001B, 16 bit MCU I/F*/
#define LCDC_CTRL_6_BIT_RGB ((u32)0x00080000) /*LCDC_CTRL[19:16]=1000B, 6 bit RGB I/F*/
#define LCDC_CTRL_16_BIT_RGB ((u32)0x00090000) /*LCDC_CTRL[19:16]=1001B, 16 bit RGB I/F*/
#define LCDC_CTRL_LED_IF ((u32)0x000F0000) /*LCDC_CTRL[19:16]=1111B, LED I/F*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_PLANE_SIZE
* @{
*****************************************************************************/
#define LCDC_PLANE_SIZE_IMG_HEIGHT ((u32)0x0FFF0000) /*Bit[27:16], bits for image height setting*/
#define LCDC_PLANE_SIZE_IMG_WIDTH ((u32)0x00000FFF) /*Bit[11:0], bits for image width setting*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_UNDFLW_CFG
* @{
*****************************************************************************/
#define LCDC_UNDFLW_CFG_UNDMODE ((u32)0x00000001<<25) /*Bit[25], output mode when DMA FIFO under flow happens*/
#define LCDC_UNDFLW_CFG_ERROUTDATA ((u32)0x0000FFFF) /*Bit[15:0], bits for DMA under flow error data field*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_DMA_MODE_CFG
* @{
*****************************************************************************/
#define LCDC_DMA_MODE_CFG_TRIGGER_MODE ((u32)0x00000001) /*Bit[0], trigger mode or auto mode selection*/
#define LCDC_DMA_MODE_CFG_TRIGGER_ONE_TIME ((u32)0x00000001<<1) /*Bit[1], trigger DMA to transfer one frame*/
#define LCDC_DMA_MODE_CFG_RDOTST ((u32)0x00000007<<2) /*Bit[4:2], bits for DMA burst size configuration*/
#define LCDC_DMA_MODE_CFG_DMAINTV ((u32)0xFFFFFF00) /*Bit[31:8], The interval cycle count between two DMA requests.
Unit: bus clock cycle.( for debug)*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_CLK_DIV
* @{
*****************************************************************************/
#define LCDC_CLK_DIV_DCLKDIV ((u32)0x0000FFFF) /*Bit[15:0], bits for DCLK clock divider*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_IRQ_EN
* @{
*****************************************************************************/
#define LCDC_IRQ_EN_DMAUNINTEN ((u32)0x00000001) /*Bit[0], DMA FIFO underflow interrupt enable*/
#define LCDC_IRQ_EN_LCDFRDINTEN ((u32)0x00000001<<2) /*Bit[2], LCD/LED refresh done interrupt enable*/
#define LCDC_IRQ_EN_LCDLINEINTEN ((u32)0x00000001<<3) /*Bit[3], LCD/LED line interrupt enable*/
#define LCDC_IRQ_EN_IOTIMEOUTEN ((u32)0x00000001<<4) /*Bit[4], IO write/read timeout interrupt enable*/
#define LCDC_IRQ_EN_FRMSTARTEN ((u32)0x00000001<<5) /*Bit[5], Frame start interrupt enable*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_IRQ_STATUS
* @{
*****************************************************************************/
#define LCDC_IRQ_STATUS_DMAUNINTS ((u32)0x00000001) /*Bit[0], DMA FIFO underflow interrupt status,Write 1 clear*/
#define LCDC_IRQ_STATUS_LCDFRDINTS ((u32)0x00000001<<2) /*Bit[2], LCD refresh frame done interrupt status,Write 1 clear*/
#define LCDC_IRQ_STATUS_LINEINTS ((u32)0x00000001<<3) /*Bit[3], Line Interrupt status,Write 1 clear*/
#define LCDC_IRQ_STATUS_IOTIMEOUTINTS ((u32)0x00000001<<4) /*Bit[4], IO write/read timeout Interrupt status,Write 1 clear*/
#define LCDC_IRQ_STATUS_FRMSTARTINTS ((u32)0x00000001<<5) /*Bit[5], Frame start Interrupt status,Write 1 clear*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_IRQ_RAW
* @{
*****************************************************************************/
#define LCDC_IRQ_RAW_DMAUNINTRS ((u32)0x00000001) /*Bit[0], DMA FIFO underflow interrupt raw status*/
#define LCDC_IRQ_RAW_LCDFRDINTS ((u32)0x00000001<<2) /*Bit[2], LCD refresh frame done interrupt raw status*/
#define LCDC_IRQ_RAW_LINEINTS ((u32)0x00000001<<3) /*Bit[3], Line Interrupt raw status*/
#define LCDC_IRQ_RAW_IOTIMEOUTINTS ((u32)0x00000001<<4) /*Bit[4], IO write/read timeout Interrupt raw status*/
#define LCDC_IRQ_RAW_FRMSTARTINTS ((u32)0x00000001<<5) /*Bit[5], frame start Interrupt raw status*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_LINE_INT_POS
* @{
*****************************************************************************/
#define LCDC_LINE_INTPOS ((u32)0x00000FFF) /*Bit[11:0], Bits for Line Interrupt Position*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_CUR_POS_STATUS
* @{
*****************************************************************************/
#define LCDC_CUR_POS_STS_X ((u32)0x00000FFF) /*BIT[11:0], current X position*/
#define LCDC_CUR_POS_STS_Y ((u32)0x00000FFF<<16) /*BIT[27:16], current Y position*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_STATUS
* @{
*****************************************************************************/
#define LCDC_STATUS_DMAUNINTCNT ((u32)0x0000FFFF) /*Bit[15:0], DMA FIFO underflow interrupt count*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_RGB_CFG
* @{
*****************************************************************************/
#define LCDC_RGB_CFG_DCLKPL ((u32)0x00000001<<16) /*Bit[16], The polarity of the DCLK active edge*/
#define LCDC_RGB_CFG_VSPL ((u32)0x00000001<<17) /*Bit[17], The VSYNC pulse polarity*/
#define LCDC_RGB_CFG_HSPL ((u32)0x00000001<<18) /*Bit[18], The HSYNC pulse polarity*/
#define LCDC_RGB_CFG_ENPL ((u32)0x00000001<<19) /*Bit[19], The ENABLE pulse polarity*/
#define LCDC_RGB_CFG_DATPL ((u32)0x00000001<<20) /*Bit[20], The Data pulse polarity*/
#define LCDC_RGB_CFG_RGBIFUPDATE ((u32)0x00000001<<24) /*Bit[24], Force HW updates RGB I/F parameters
after current LCD refresh frame done. CPU writes 1
to force HW updating parameters. After updating,
HW cleared this bit.(ex. DMA Address update should
take care of this bit)*/
#define LCDC_RGB_CFG_RGB_SYNC_MODE ((u32)0x000000003<<25) /*Bit[26:25], bit field for RGB sync mode*/
#define LCDC_RGB_CFG_RGB_DE_MODE ((u32)0x000000000) /*Bit[26:25] = 00B, DE mode,frame synchronized with ENABLE signal*/
#define LCDC_RGB_CFG_RGB_HV_MODE ((u32)0x000000001<<25) /*Bit[26:25] = 01B, HV mode,frame synchronized with sync signal*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_RGB_VSYNC_CFG
* @{
*****************************************************************************/
#define LCDC_RGB_VSYNC_CFG_VSW ((u32)0x0000000F) /*Bit[3:0], Vertical sync signal width*/
#define LCDC_RGB_VSYNC_CFG_VBP ((u32)0x0000000F<<8) /*Bit[11:8], Back porch line number*/
#define LCDC_RGB_VSYNC_CFG_VFP ((u32)0x0000000F<<16) /*Bit[19:16], Front porch line number*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_RGB_HSYNC_CFG
* @{
*****************************************************************************/
#define LCDC_RGB_HSYNC_CFG_HSW ((u32)0x000000FF) /*Bit[7:0], Horizontal sync signal width*/
#define LCDC_RGB_HSYNC_CFG_HBP ((u32)0x000000FF<<8) /*Bit[15:8], Horizontal back porch*/
#define LCDC_RGB_HSYNC_CFG_HFP ((u32)0x000000FF<<16) /*Bit[23:16], Horizontal front porch*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_RGB_SYNC_STATUS
* @{
*****************************************************************************/
#define LCDC_RGB_SYNC_STATUS_VSSTATUS ((u32)0x00000003) /*Bit[1:0], bit field for VSYNC Status*/
#define LCDC_RGB_SYNC_STATUS_VSYNC ((u32)0x00000000) /*Bit[1:0]=00B HSYNC*/
#define LCDC_RGB_SYNC_STATUS_VFP ((u32)0x00000001) /*Bit[1:0]=01B, HFP*/
#define LCDC_RGB_SYNC_STATUS_VACTIVE ((u32)0x00000002) /*Bit[1:0]=10B, ACTIVE*/
#define LCDC_RGB_SYNC_STATUS_VBP ((u32)0x00000003) /*Bit[1:0]=11B, HBP*/
#define LCDC_RGB_SYNC_STATUS_HSSTATUS ((u32)0x00000003<<2) /*Bit[3:2], bit field for HSYNC Status*/
#define LCDC_RGB_SYNC_STATUS_HSYNC ((u32)0x00000000<<2) /*Bit[3:2]=00B HSYNC*/
#define LCDC_RGB_SYNC_STATUS_HFP ((u32)0x00000001<<2) /*Bit[3:2]=01B, HFP*/
#define LCDC_RGB_SYNC_STATUS_HACTIVE ((u32)0x00000002<<2) /*Bit[3:2]=10B, ACTIVE*/
#define LCDC_RGB_SYNC_STATUS_HBP ((u32)0x00000003<<2) /*Bit[3:2]=11B, HBP*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_MCU_CFG
* @{
*****************************************************************************/
#define LCDC_MCU_CFG_CSPL ((u32)0x00000001) /*Bit[0], CS pulse polarity*/
#define LCDC_MCU_CFG_RSPL ((u32)0x00000001<<1) /*Bit[1], RS pulse polarity*/
#define LCDC_MCU_CFG_WRPL ((u32)0x00000001<<2) /*Bit[2], WR pulse polarity*/
#define LCDC_MCU_CFG_RDPL ((u32)0x00000001<<3) /*Bit[3], RD pulse polarity*/
#define LCDC_MCU_CFG_DATAPL ((u32)0x00000001<<4) /*Bit[4], DATA pulse polarity*/
#define LCDC_MCU_CFG_TEPL ((u32)0x00000001<<5) /*Bit[5], TE pulse polarity*/
#define LCDC_MCU_CFG_MCUSYPL ((u32)0x00000001<<6) /*Bit[6], MCU VSYNC pulse polarity*/
#define LCDC_MCU_CFG_MCUIFUPDATE ((u32)0x00000001<<8) /*Bit[8], Force HW updates MCU I/F Timing
shadow register at specific timing*/
#define LCDC_MCU_CFG_MCUSYNCMODE ((u32)0x00000003<<9) /*Bit[10:9], bit field for MCU SYNC mode setting*/
#define LCDC_MCU_CFG_SYNC_INTERNAL_CLK ((u32)0x00000000<<9) /*Bit[10:9]=00B, synchronized with the internal clock*/
#define LCDC_MCU_CFG_SYNC_VSYNC_INPUT ((u32)0x00000001<<9) /*Bit[10:9]=01B, synchronized with the VSYNC INPUT*/
#define LCDC_MCU_CFG_SYNC_TE ((u32)0x00000002<<9) /*Bit[10:9]=10B, synchronized with the TE*/
#define LCDC_MCU_CFG_IOMODE_EN ((u32)0x00000001<<11) /*Bit[11], MCU I/F mode enable*/
#define LCDC_MCU_CFG_IOMODE_RUN ((u32)0x00000001<<12) /*Bit[12], MCU I/F mode run*/
#define LCDC_MCU_CFG_IOMODE_TEDELAY ((u32)0x0000FFFF<<16) /*Bit[31:16], TE delay interval -5*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_MCU_VSYNC_CFG
* @{
*****************************************************************************/
#define LCDC_MCU_VSYNC_CFG_MCUVSW ((u32)0x000000FF) /*Bit[7:0], VSYNC signal widdth - 1*/
#define LCDC_MCU_VSYNC_CFG_MCUVSPD ((u32)0x0000FFFF<<12) /*Bit[31:12], VSYNC idle period*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_MCU_TIMING_CFG
* @{
*****************************************************************************/
#define LCDC_MCU_TIMING_CFG_WRPULW ((u32)0x000003FF) /*Bit[9:0], write pulse width */
#define LCDC_MCU_TIMING_CFG_RDACTW ((u32)0x000007FF<<10) /*Bit[20:10], RD active pulse width -1*/
#define LCDC_MCU_TIMING_CFG_RDINACTW ((u32)0x000007FF<<21) /*Bit[31:21], RD inactive pulse width -1*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_MCU_IO_DATA
* @{
*****************************************************************************/
#define LCDC_MCU_IO_WR_CMD_FG ((u32)0x80000000) /*Bit[31], bit field for writing command control*/
#define LCDC_MCU_IO_WR_DAT_FG ((u32)0x7FFFFFFF) /*For writing data mask*/
#define LCDC_MCU_IO_RW_DATA ((u32)0x0000FFFF) /*Bit[15:0], bit field for write/read data*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_MCU_IO_TO_CFG
* @{
*****************************************************************************/
#define LCDC_MCU_IO_TIMEOUT_CLK_NUM ((u32)0x0000FFFF) /*Bit[15:0], bit field for write/read timeout clock number, unit: write clock*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_LED_CFG
* @{
*****************************************************************************/
#define LCDC_LED_CFG_COLORNUM ((u32)0x00000003) /*Bit[1:0], bit field for Color number in frame buffer*/
#define LCDC_LED_CFG_ONECOLOR ((u32)0x00000000) /*Bit[1:0]=00B, one color*/
#define LCDC_LED_CFG_TWOCOLOR ((u32)0x00000001) /*Bit[1:0]=01B, two color*/
#define LCDC_LED_CFG_THREECOLOR ((u32)0x00000002) /*Bit[1:0]=10B, three color*/
#define LCDC_LED_CFG_COLORCHAN ((u32)0x00000001<<2) /*Bit[2], color channel*/
#define LCDC_LED_CFG_LEDIFUPDATE ((u32)0x00000001<<3) /*Bit[3], Force HW updates LED I/F parameters after current LED refresh frame done.*/
#define LCDC_LED_CFG_CLKPL ((u32)0x00000001<<4) /*Bit[4], The polarity of the DCLK active edge*/
#define LCDC_LED_CFG_LATPL ((u32)0x00000001<<5) /*Bit[5], The polarity of the LATCH active edge.*/
#define LCDC_LED_CFG_OEPL ((u32)0x00000001<<6) /*Bit[6], The OE pulse polarity.*/
#define LCDC_LED_CFG_DATPL ((u32)0x00000001<<7) /*Bit[7], The Data pulse polarity..*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_LED_TIMING
* @{
*****************************************************************************/
#define LCDC_LED_TIMING_LATW ((u32)0x000000FF) /*Bit[7:0], bit field for LAT Width Time - 1. Unit: dotclock*/
#define LCDC_LED_TIMING_OEACTW ((u32)0x0000FFFF<<8) /*Bit[23:8], bit field for OE Active Width Time - 1. Unit: dotclock*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_LED_IDLE
* @{
*****************************************************************************/
#define LCDC_LED_TIMING_LINEIDLE ((u32)0x000000FF) /*Bit[7:0], bit field for line idle Width Time - 1. Unit: dotclock*/
#define LCDC_LED_TIMING_FRMIDLEPD ((u32)0x00000FFF<<20) /*Bit[31:20], bit field for frame idle period interval - 1. Unit: dotclock*/
/** @} */
/**************************************************************************//**
* @defgroup LCDC_IMG_BASE_ADDR
* @{
*****************************************************************************/
#define LCDC_IMG_BASE_ADDR_MASK ((u32)0xFFFFFFFF) /*Bit[31:0], Image DMA source address.*/
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_lcdc.h
|
C
|
apache-2.0
| 53,587
|
/**
******************************************************************************
* @file rtl8721d_loguart.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for UART LOG firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _8710B_DIAG_H_
#define _8710B_DIAG_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup DIAG
* @brief DIAG driver modules
* @{
*/
/** @addtogroup DIAG
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* -Control API for LOGUART.
* -These API is used by system, user should not use these API if not needed.
* -LOGUART is UART2.
*
*****************************************************************************************
* pinmux
*****************************************************************************************
* -S0: GPIOA_16/17: QFN48, QFN68, QFN48-MCM.
* -S1: GPIOA_29/30: QFN32.
* -EFUSE 0x19[6]: 0: S1 PA29 & PA30, 1: S0 PA16 & PA17.
*
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DIAG_Exported_Constants DIAG Exported Constants
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DIAG_Exported_Functions DIAG Exported Functions
* @{
*/
_LONG_CALL_ void LOGUART_DiagInit(BOOL InitConsol);
_LONG_CALL_ void LOGUART_PutChar(u8 c);
_LONG_CALL_ u8 LOGUART_GetChar(BOOL PullMode);
_LONG_CALL_ u8 LOGUART_Readable(void);
_LONG_CALL_ u32 LOGUART_GetIMR(void);
_LONG_CALL_ void LOGUART_SetIMR (u32 SetValue);
_LONG_CALL_ void LOGUART_WaitBusy(void);
_LONG_CALL_ void LOGUART_SetBaud_FromFlash(void);
#define DiagPutChar LOGUART_PutChar
#define DiagGetChar LOGUART_GetChar
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
#endif //_8710B_DIAG_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_loguart.h
|
C
|
apache-2.0
| 2,688
|
/**
******************************************************************************
* @file rtl8721d_ota.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the OTA functions.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_OTA_H_
#define _RTL8721D_OTA_H_
/** @addtogroup AmebaD_Platform
* @{
*/
#define SERVER_LOCAL 1
#define SERVER_CLOUD 2
#define SERVER_TYPE SERVER_LOCAL /*configure OTA demo type*/
#define MAX_IMG_NUM 2
#define HTTP_OTA_UPDATE
#define HTTPS_OTA_UPDATE
#if (defined HTTP_OTA_UPDATE) || (defined HTTPS_OTA_UPDATE)
#define HEADER_BAK_LEN 32
typedef struct {
u32 status_code;
u32 header_len;
u8 *body;
u32 body_len;
u8 *header_bak;
u32 parse_status;
} http_response_result_t;
#endif
/** @defgroup OTA
* @brief OTA driver modules
* @{
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup OTA_Exported_Types OTA Exported Types
* @{
*/
/**
* @brief OTA firmware file header structure definition
*/
typedef struct
{
u32 FwVer; /*!< Specifies the OTA firmware verision.
This parameter is in first Dword in the firmware file. */
u32 HdrNum;/*!< Specifies the OTA firmware header number.
This parameter indicates how many headers in firmware file. */
}update_file_hdr;
/**
* @brief OTA firmware file image header structure definition
*/
typedef struct
{
u8 ImgId[4]; /*!< Specifies the OTA image ID.
This parameter is used to identify the OTA header needed. */
u32 ImgHdrLen; /*!< Specifies the OTA image header length.
This parameter indicates the Image Header Length. */
u32 Checksum; /*!< Specifies the OTA image checksum.
This parameter is used to judge whether the image received is correct. */
u32 ImgLen; /*!< Specifies the OTA image length. */
u32 Offset; /*!< Specifies the the location in the total firmware file. */
u32 FlashAddr; /*!< Specifies the flash offset address of the corresponding image. */
}update_file_img_hdr;
/**
* @brief OTA firmware file download information structure definition
*/
typedef struct
{
u32 ImgId; /*!< Specifies the Image ID.*/
u32 FlashAddr; /*!< Specifies the Flash Address.
This parameter is used to write the Image to the flash. */
u32 ImgOffset; /*!< Specifies the Image location in Firmware header.
This parameter indicates the Image location in firmware file. */
u32 ImageLen; /*!< Specifies the OTA image length. */
}update_dw_info;
/**
* @brief OTA target image header structure definition
*/
typedef struct
{
update_file_hdr FileHdr; /*!< Specifies the firmware file header. */
update_file_img_hdr FileImgHdr[MAX_IMG_NUM]; /*!< Specifies the target OTA image firmware file header. */
u8 Sign[MAX_IMG_NUM][9]; /*!< Specifies the signature of target image. */
u8 ValidImgCnt; /*!< Specifies valid image number in file. */
}update_ota_target_hdr;
/* Exported constants --------------------------------------------------------*/
/** @defgroup OTA_Exported_Constants OTA Exported Constants
* @{
*/
/** @defgroup OTA_system_parameter_definitions
* @{
*/
#define BACKUP_SECTOR (FLASH_RESERVED_DATA_BASE) /*back up system data offset address*/
#define LS_IMG2_OTA1_ADDR 0x08014000 /* KM0 OTA1 start address*/
#define LS_IMG2_OTA2_ADDR 0x08194000 /* KM0 OTA2 start address*/
#define BUF_SIZE 512 /*the size of the buffer used for receiving firmware data from server*/
#define OTA_IMAG 0 /*identify the OTA image*/
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup OTA_Exported_Functions OTA Exported Functions
* @{
*/
u32 OTA_Change(u32 OTAIdx);
void* ota_update_malloc(unsigned int size);
void ota_update_free(void *buf);
#if (SERVER_TYPE == SERVER_LOCAL)
void ota_platform_reset(void);
int ota_write_ota2_addr(uint32_t ota_addr);
u32 ota_get_cur_index(void);
int ota_readstream_user(u32 address, u32 len, u8 * data);
u32 recv_file_info_from_server(u8 * Recvbuf, u32 len, int socket);
u32 recv_ota_file_hdr(u8 * Recvbuf, u32 * len, update_ota_target_hdr * pOtaTgtHdr, int socket);
u32 get_ota_tartget_header(u8* buf, u32 len, update_ota_target_hdr * pOtaTgtHdr, u8 target_idx);
void erase_ota_target_flash(u32 addr, u32 len);
u32 download_new_fw_from_server(int socket, update_ota_target_hdr * pOtaTgtHdr, u8 targetIdx);
u32 verify_ota_checksum(update_ota_target_hdr * pOtaTgtHdr);
u32 change_ota_signature(update_ota_target_hdr * pOtaTgtHdr, u32 ota_target_index);
#endif
#if (defined HTTP_OTA_UPDATE) || (defined HTTPS_OTA_UPDATE)
int parser_url( char *url, char *host, u16 *port, char *resource);
int parse_http_response(unsigned char *response, unsigned int response_len, http_response_result_t *result);
#ifdef HTTP_OTA_UPDATE
int update_ota_http_connect_server(int server_socket, char *host, int port);
u32 recv_ota_file_hdr_http(u8 * Recvbuf, u32 writelen, u32 * len, update_ota_target_hdr * pOtaTgtHdr, int socket);
int http_read_socket( int socket, u8 *recevie_buf, int buf_len );
u32 download_new_fw_from_server_http(u8* first_buf, unsigned int firstbuf_len, int socket, update_ota_target_hdr * pOtaTgtHdr, u8 targetIdx);
int http_update_ota(char *host, int port, char *resource);
#endif
#ifdef HTTPS_OTA_UPDATE
#if !defined(MBEDTLS_CONFIG_FILE)
#include <mbedtls/config.h>
#else
#include MBEDTLS_CONFIG_FILE
#endif
#include <mbedtls/platform.h>
#include <mbedtls/net_sockets.h>
#include <mbedtls/ssl.h>
u32 recv_ota_file_hdr_https(u8 * Recvbuf, u32 writelen, u32 * len, update_ota_target_hdr * pOtaTgtHdr, mbedtls_ssl_context * ssl);
int https_read_socket(mbedtls_ssl_context * ssl, u8 * recevie_buf, int buf_len);
u32 download_new_fw_from_server_https(u8 * first_buf, unsigned int firstbuf_len, mbedtls_ssl_context * ssl, update_ota_target_hdr * pOtaTgtHdr, u8 targetIdx);
int https_update_ota(char *host, int port, char *resource);
#endif
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif //_RTL8721D_OTA_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_ota.h
|
C
|
apache-2.0
| 6,711
|
/**
******************************************************************************
* @file rtl8721d_otf.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the flash run time decrypt firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_RSIP_H_
#define _RTL8721D_RSIP_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup PROTECTION
* @brief PROTECTION driver modules
* @{
*/
/** @addtogroup PROTECTION
* @verbatim
*****************************************************************************************
* RSIP(OTF) Introduction
*****************************************************************************************
* -used for flash firmware protection, and flash firmware will be encrypted use AES.
* -16B KEY shoud be written to EFUSE OTP KEY area use EFUSE_OTF_KEY.
* -Enable should be write to EFUSE 0x19[5].
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PROTECTION_Exported_Functions OTF Exported Functions
* @{
*/
_LONG_CALL_ void RSIP_Cmd(u32 NewStatus);
_LONG_CALL_ void RSIP_OTF_init(u8* IV);
_LONG_CALL_ void RSIP_OTF_Cmd(u32 NewStatus);
_LONG_CALL_ void RSIP_OTF_Mask(u32 MaskIdx, u32 Addr, u32 Len, u32 NewStatus);
_LONG_CALL_ u32 RSIP_KEY_Request(u32 KeyTypeBit);
_LONG_CALL_ void RSIP_MMU_Config(u32 MMUIdx, u32 AddrStart, u32 AddrEnd, u32 IsMinus, u32 AddrOffset);
_LONG_CALL_ void RSIP_MMU_Cmd(u32 MMUIdx, u32 NewStatus);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup RSIP_Register_Definitions OTF Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup OTF_DEC
* @{
*****************************************************************************/
#define REG_SYS_OTF_DEC_CTRL 0x02D8
#define REG_SYS_OTF_DEC_ADDR_MASK0 0x02DC
#define REG_SYS_OTF_DEC_ADDR_MASK1 0x02E4
#define REG_SYS_OTF_DEC_ADDR_MASK2 0x02E8
#define REG_SYS_OTF_DEC_ADDR_MASK3 0x02EC
#define REG_SYS_OTF_DEC_IV_EXT 0x02F0
/** @} */
/**************************************************************************//**
* @defgroup REG_OTF_DEC_CTRL
* @{
*****************************************************************************/
#define OTF_FEN_OTFDEC ((u32)0x00000001) /*!<function enable of OTF decoder */
#define OTF_DEC_IV_BYTE_SWAP ((u32)0x00000002) /*!<Big/little endian conversion for input OTF IV */
#define OTF_DEC_KEY_BYTE_SWAP ((u32)0x00000004) /*!<Big/little endian conversion for input OTF KEY*/
#define OTF_DEC_CIPHER_BYTE_SWAP ((u32)0x00000008) /*!Big/little endian conversion for calculated cipher*/
/** @} */
/**************************************************************************//**
* @defgroup OTF_MASK_ENTRYx_CTRL
* @{
*****************************************************************************/
#define OTF_DEC_BIT_MASK_EN ((u32)0x00000001) /*!<Decoder mask enable for address~address+length */
#define OTF_DEC_BIT_MASK_SIZE ((u32)0x000000FF) /*!<Address range for decoder mask, unit is 4KB */
#define OTF_DEC_BIT_SHIFT_SIZE 8
#define IS_OTF_MASK_SIZE(SIZE) ((((SIZE) & ~OTF_DEC_BIT_MASK_SIZE) == 0x00) && (((SIZE) & OTF_DEC_BIT_MASK_SIZE) != 0x00))
/** @} */
/**************************************************************************//**
* @defgroup MMU_ENTRYx_CTRL
* @{
*****************************************************************************/
#define MMU_BIT_ENTRY_VALID ((u32)0x00000001) /*!< MMU entry_x valid */
#define MMU_BIT_ENTRY_OFFSET_MINUS ((u32)0x00000002) /*!< MMU_ENTRYx_OFFSET flag, 0 Plus, 1 Minus. */
/** @} */
/**************************************************************************//**
* @defgroup RDP_ERROR_STATUS
* @{
*****************************************************************************/
#define RDP_SYSTEMBIN_WRONG ((u32)0x00000001) /*!<system.bin not load to flash */
#define RDP_RDPBIN_WRONG ((u32)0x00000002) /*!<rdp.bin not load to flash */
#define RDP_KEY_REQUEST_TIMEOUT ((u32)0x00000003) /*!<Key request timeout */
#define RDP_NOT_ENABLE ((u32)0x00000004) /*!<RDP not enable in efuse */
#define RDP_CHECKSUM_ERROR ((u32)0x00000005) /*!<Check sum error */
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
#define KEY_REQ_POLL_TIMES 0xFF
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_otf.h
|
C
|
apache-2.0
| 5,368
|
/**
******************************************************************************
* @file rtl8721d_pinmap.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of pin control:
* - pinmux
* - active pad pull up & pull down
* - sleep pad pull up & pull down
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_PINMAP_H_
#define _RTL8710B_PINMAP_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup PIN
* @brief PIN driver modules
* @{
*/
/** @defgroup PINMAP
* @brief PINMAP driver modules
* @{
*/
/** @addtogroup PINMAP
* @verbatim
*****************************************************************************************
* PINMAP
*****************************************************************************************
* you can use pinmap to config pinmux instead of Pinmux_Config function
* you can use pinmap to config GPIO pull high/low status for power save when enter power save mode
*****************************************************************************************
* How To Use
*****************************************************************************************
* -1) ENABLE MACRO: CONFIG_PINMAP_ENABLE
* -2) Set all pins function in pmap_func based on your board
* -3) Bootloader will call pinmap_init, then all pinmux will be set based on pmap_func
* -4) pinmap_sleep will be called when enter sleep mode, all GPIO will pull high or low based on pmap_func
* -5) pinmap_wake will be called when wake from sleep mode, all GPIO will back to active mode
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PINMAP_Exported_Types PINMAP Exported Types
* @{
*/
/**
* @brief PINMAP Init structure definition
*/
typedef struct
{
u32 PinName; /*!< Specifies the pin name, This parameter can be a value of @ref PINMUX_Pin_Name_definitions */
u32 FuncPuPd;/*!< Specifies the pin function PU/PD, This parameter can be a value of @ref GPIO_Pull_parameter_definitions */
u32 SleepPuPd;/*!< Specifies the pin sleep PU/PD, This parameter can be a value of @ref GPIO_Pull_parameter_definitions */
u32 DSleepPuPd;/*!< Specifies the pin deep sleep PU/PD, This parameter can be a value of @ref GPIO_Pull_parameter_definitions */
u32 LowPowerPin;/*!< Specifies if it is a low power pin or touch pin, if so, this pin will keep state in DSLP state */
} PMAP_TypeDef;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PINMAP_Exported_Functions PINMAP Exported Functions
* @{
*/
void pinmap_init(void);
void pinmap_sleep(void);
void pinmap_deepsleep(void);
void pinmap_wake(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
#define GPIO_PuPd_KEEP 0xFF /* keep pupd unchanged */
#endif //_RTL8710B_PINMAP_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_pinmap.h
|
C
|
apache-2.0
| 3,644
|
/**
******************************************************************************
* @file rtl8721d_pinmux.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the pinmux firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _HAL_8721D_PINMUX_
#define _HAL_8721D_PINMUX_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup PIN
* @brief PIN driver modules
* @{
*/
/** @defgroup PINMUX
* @brief PINMUX modules
* @{
*/
/** @addtogroup PINMUX
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* -Every GPIO pin can be set to some function based on pinmux spec.
* -Every GPIO pin can set internal pull-up, pull-down based on pinmux spec.
*
*====================================================================
* pad control Spec.
*====================================================================
* -[31:16] reserved
* -[15] pad shut down enable
* -[14] H3L1 for SDIO pad, other pad reserved
* -[13] pull resistor selection
* -[12] schmitt trigger enable
* -[11:10] pad driving strength
* -[9] pull down resistor enable
* -[8] pull up resistor enable
* -[7:5] reserved for function id extend
* -[4:0] function id
*
*****************************************************************************************
* How to use Pinmux
*****************************************************************************************
* 1. Set the Internal pad function type for each pin using the follwoing function:
* Pinmux_Config(u8 PinName, u32 PinFunc)
*
* 2. Set the Internal pad pull type for each pin using the follwoing function:
* PAD_PullCtrl(u8 PinName, u8 PullType)
*
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PINMUX_Exported_Constants PINMUX Exported Constants
* @{
*/
/** @defgroup PINMUX_Pin_Name_definitions
* @note: Pin_Name = (((port)<<5)|(pin))
* @{
*/
#define _PA_0 (0x00) //0x400
#define _PA_1 (0x01) //0x404
#define _PA_2 (0x02) //0x408
#define _PA_3 (0x03) //0x40C
#define _PA_4 (0x04) //0x410
#define _PA_5 (0x05) //0x414
#define _PA_6 (0x06) //0x418
#define _PA_7 (0x07) //0x41C
#define _PA_8 (0x08) //0x420
#define _PA_9 (0x09) //0x424
#define _PA_10 (0x0A) //0x428
#define _PA_11 (0x0B) //0x42C
#define _PA_12 (0x0C) //0x430
#define _PA_13 (0x0D) //0x434
#define _PA_14 (0x0E) //0x438
#define _PA_15 (0x0F) //0x43C
#define _PA_16 (0x10) //0x440
#define _PA_17 (0x11) //0x444
#define _PA_18 (0x12) //0x448
#define _PA_19 (0x13) //0x44C
#define _PA_20 (0x14) //0x450
#define _PA_21 (0x15) //0x454
#define _PA_22 (0x16) //0x458
#define _PA_23 (0x17) //0x45C
#define _PA_24 (0x18) //0x460
#define _PA_25 (0x19) //0x464
#define _PA_26 (0x1A) //0x468
#define _PA_27 (0x1B) //0x46C
#define _PA_28 (0x1C) //0x470
#define _PA_29 (0x1D) //0x474
#define _PA_30 (0x1E) //0x478
#define _PA_31 (0x1F) //0x47C
#define _PB_0 (0x20) //0x480
#define _PB_1 (0x21) //0x484
#define _PB_2 (0x22) //0x488
#define _PB_3 (0x23) //0x48C
#define _PB_4 (0x24) //0x490
#define _PB_5 (0x25) //0x494
#define _PB_6 (0x26) //0x498
#define _PB_7 (0x27) //0x49C
#define _PB_8 (0x28) //0x4A0
#define _PB_9 (0x29) //0x4A4
#define _PB_10 (0x2A) //0x4A8
#define _PB_11 (0x2B) //0x4AC
#define _PB_12 (0x2C) //0x4B0
#define _PB_13 (0x2D) //0x4B4
#define _PB_14 (0x2E) //0x4B8
#define _PB_15 (0x2F) //0x4Bc
#define _PB_16 (0x30) //0x4C0
#define _PB_17 (0x31) //0x4C4
#define _PB_18 (0x32) //0x4C8
#define _PB_19 (0x33) //0x4CC
#define _PB_20 (0x34) //0x4D0
#define _PB_21 (0x35) //0x4D4
#define _PB_22 (0x36) //0x4D8
#define _PB_23 (0x37) //0x4DC
#define _PB_24 (0x38) //0x4E0
#define _PB_25 (0x39) //0x4E4
#define _PB_26 (0x3A) //0x4E8
#define _PB_27 (0x3B) //0x4EC
#define _PB_28 (0x3C) //0x4F0
#define _PB_29 (0x3D) //0x4F4
#define _PB_30 (0x3E) //0x4F8
#define _PB_31 (0x3F) //0x4FC
#define _PNC (0xFFFFFFFF)
/**
* @}
*/
/** @defgroup PINMUX_Port_And_Pin_definitions
* @{
*/
#define PORT_NUM(pin) ((pin>>5) & 0x03)
#define PIN_NUM(pin) (pin & 0x1f)
/**
* @}
*/
/** @defgroup PINMUX_PAD_Control_definitions
* @{
*/
#define PAD_BIT_SHUT_DWON BIT(15)
#define PAD_BIT_SDIO_H3L1 BIT(14)
#define PAD_BIT_PULL_RESISTOR_SEL BIT(13)
#define PAD_BIT_SCHMITT_TRIGGER_EN BIT(12)
#define PAD_BIT_PULL_RESISTOR_SMALL BIT(11) /* for PAD C/F/G */
#define PAD_BIT_SHIFT_DRIVING_STRENGTH 10
#define PAD_BIT_MASK_DRIVING_STRENGTH 0x03
#define PAD_BIT_PULL_DOWN_RESISTOR_EN BIT(9)
#define PAD_BIT_PULL_UP_RESISTOR_EN BIT(8)
#define PAD_BIT_SHIFT_FUNCTION_ID 0
#define PAD_BIT_MASK_FUNCTION_ID 0x1F
/**
* @}
*/
/** @defgroup GPIO_Pull_Resistor_definitions
* @{
*/
#define GPIO_Resistor_LARGE 0x00 /*!< GPIO Resistor LARGE */
#define GPIO_Resistor_SMALL 0x01 /*!< GPIO Resistor SMALL */
/**
* @}
*/
/** @defgroup PINMUX_Function_definitions
* @{
*/
#define PINMUX_FUNCTION_GPIO (0)
#define PINMUX_FUNCTION_UART (1)
#define PINMUX_FUNCTION_UART_RTSCTS (2)
#define PINMUX_FUNCTION_LOGUART (2)
#define PINMUX_FUNCTION_SPIM (3)
#define PINMUX_FUNCTION_SPIS (3)
#define PINMUX_FUNCTION_RTC (4)
#define PINMUX_FUNCTION_TIMINPUT (4)
#define PINMUX_FUNCTION_EXT32K (28)
#define PINMUX_FUNCTION_RTCOUT (28)
#define PINMUX_FUNCTION_TIMINPUT_HS (22)
#define PINMUX_FUNCTION_IR (5)
#define PINMUX_FUNCTION_SPIF (6)
#define PINMUX_FUNCTION_I2C (7)
#define PINMUX_FUNCTION_SDIOD (8)
#define PINMUX_FUNCTION_SDIOH (8)
#define PINMUX_FUNCTION_PWM (9)
#define PINMUX_FUNCTION_PWM_HS (9)
#define PINMUX_FUNCTION_PWM_LP (10)
#define PINMUX_FUNCTION_SWD (11)
#define PINMUX_FUNCTION_I2S (12)
#define PINMUX_FUNCTION_DMIC (12)
#define PINMUX_FUNCTION_KEYSCAN_ROW (29)
#define PINMUX_FUNCTION_KEYSCAN_COL (30)
#define PINMUX_FUNCTION_LCD (13)
#define PINMUX_FUNCTION_USB (14)
#define PINMUX_FUNCTION_QDEC (15)
#define PINMUX_FUNCTION_SGPIO (16)
#define PINMUX_FUNCTION_RFE (18)
#define PINMUX_FUNCTION_BTCOEX (19)
#define PINMUX_FUNCTION_WIFIFW (20)
#define PINMUX_FUNCTION_EXT_PCM (20)
#define PINMUX_FUNCTION_BB_PIN (21)
#define PINMUX_FUNCTION_SIC (22)
#define PINMUX_FUNCTION_WAKEUP (31)
#define PINMUX_FUNCTION_DBGPORT (23)
#define PINMUX_FUNCTION_BBDBG (25)
/**
* @}
*/
/** @defgroup PINMUX_Peripheral_Location_definitions
* @note just used by function PINMUX_Ctrl
* @{
*/
#define PINMUX_S0 (0)
#define PINMUX_S1 (1)
#define PINMUX_S2 (2)
#define PINMUX_S3 (3)
/**
* @}
*/
/** @defgroup PINMUX_PAD_DrvStrength_definitions
* @{
*/
#define PAD_DRV_STRENGTH_0 (0x00000000 << 9)
#define PAD_DRV_STRENGTH_1 (0x00000001 << 9)
#define PAD_DRV_STRENGTH_2 (0x00000002 << 9)
#define PAD_DRV_STRENGTH_3 (0x00000003 << 9)
#define PAD_DRV_STRENGTH_4 (0x00000004 << 9)
#define PAD_DRV_STRENGTH_5 (0x00000005 << 9)
#define PAD_DRV_STRENGTH_6 (0x00000006 << 9)
#define PAD_DRV_STRENGTH_7 (0x00000007 << 9)
/**
* @}
*/
/**
* @}
*/
/** @defgroup PINMUX_Exported_Functions PINMUX Exported Functions
* @{
*/
_LONG_CALL_ void PAD_CMD(u8 PinName, u8 NewStatus);
_LONG_CALL_ void PAD_DrvStrength(u8 PinName, u32 DrvStrength);
_LONG_CALL_ void PAD_PullCtrl(u8 PinName, u8 PullType);
_LONG_CALL_ void Pinmux_Config(u8 PinName, u32 PinFunc);
_LONG_CALL_ u32 Pinmux_ConfigGet(u8 PinName);
_LONG_CALL_ void Pinmux_UartLogCtrl(u32 PinLocation, BOOL Operation);
_LONG_CALL_ void Pinmux_SpicCtrl(u32 PinLocation, BOOL Operation);
/**
* @brief Set the Internal pad Resistor type.
* @param PinName : value of @ref PINMUX_Pin_Name_definitions.
* @param PullType : the pull type for the pin.This parameter can be one of the following values:
* @arg GPIO_Resistor_LARGE
* @arg GPIO_Resistor_SMALL
* @retval None
* @note Just for PAD C/F/G:
* @note PA[12]/PA[13]/PA[14]/PA[15]/PA[16]/PA[17]/PA[18]/PA[19]/PA[20]/PA[21]/PA[25]/PA[26] 4.7K/50K
* @note PA[29]/PA[30]/PA[31] 4.7K/10K
*/
static inline void PAD_ResistorCtrl(u8 PinName, u8 RType)
{
u32 Temp = 0;
/* get PADCTR */
Temp = PINMUX->PADCTR[PinName];
/* set resistor small */
Temp |= PAD_BIT_PULL_RESISTOR_SMALL; /* by default is small */
/* set large if needed */
if (RType == GPIO_Resistor_LARGE) {
Temp &= ~PAD_BIT_PULL_RESISTOR_SMALL;
}
/* set PADCTR register */
PINMUX->PADCTR[PinName] = Temp;
}
/**
* @brief Turn off pinmux SWD function.
* @retval None
*/
static inline void Pinmux_Swdoff(void)
{
u32 Temp = 0;
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_SWD_PMUX_EN);
Temp &= (~BIT_LSYS_SWD_PMUX_EN);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SWD_PMUX_EN, Temp);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
#define FLASH_S0_CS_GPIO _PB_18
#define FLASH_S1_CS_GPIO _PB_16
#endif //_HAL_8721D_PINMUX_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_pinmux.h
|
C
|
apache-2.0
| 9,755
|
/**
******************************************************************************
* @file rtl8721d_pmc.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of the soc power management circut:
* - wakeup timer
* - wakeup pin
* - sleep option
* - sleep mode
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_PMC_H_
#define _RTL8721D_PMC_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup PMC
* @brief PMC driver modules
* @{
*/
/** @addtogroup PMC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* we support following soc power save functions:
* - sleep clock gating
* - sleep power gating
* - deep standby
* - deep sleep
*
*****************************************************************************************
* sleep power gating
*****************************************************************************************
* following functions can be used when power gating:
* -UART0/UART1
* -TIM4/TIM5
* -RTC
* -WIFI
* -SDIO
* -USB
* -I2C0/I2C1
* -ADC
* -GPIO
* -REGU timer
* -normal wakepin
* -ANA timer
* following functions will be closed when power gating:
* -UART2 LOGUART
* -TIM0-TIM3
* -SPIC flash
*
*****************************************************************************************
* deep standby
*****************************************************************************************
* following functions can be used when deep standby:
* -RTC
* -REGU timer
* -normal wakepin
* -ANA timer
*
*****************************************************************************************
* deep sleep
*****************************************************************************************
* following functions can be used when deep standby:
* -REGU timer
* -REGU wakepin
*
*****************************************************************************************
* wakepin (A18/A5/A22/A23: mux normal wakepin and REGU wakepin)
*****************************************************************************************
* normal wakepin:
* -SLP_CG
* -SLP_PG
* -STDBY
* REGU wakepin:
* -just used in DSLP (1.2V closed)
* -just support high acive, so this pin should pull low on your board
*
*****************************************************************************************
*****************************************************************************************
* SLP & SNZ power option
*****************************************************************************************
* BIT_SYSON_PMOPT_SLP_EN_SWR & BIT_SYSON_PMOPT_SNZ_EN_SWR
* -we have two 1.2V LDO
* -BIG LDO: SWR mode or LDO mode (can config )
* -LITTLE LDO: a little 1.2v LDO
* -BIT_SYSON_PMOPT_SLP_EN_SWR
* -ENABLE/DISABLE BIG LDO when SLP
* BIT_SYSON_PMOPT_SNZ_EN_SWR
* -ENABLE/DISABLE BIG LDO when SNZ, WIFI & ADC need open BIG LDO when SNZ
*
* BIT_SYSON_PMOPT_SLP_EN_PWM & BIT_SYSON_PMOPT_SNZ_EN_PWM
* -BIT_SYSON_PMOPT_SLP_EN_PWM
* -ENABLE/DISABLE LDO heavy loading current mode when SLP
* -BIT_SYSON_PMOPT_SNZ_EN_PWM
* -ENABLE/DISABLE heavy loading current mode when SNZ, WIFI & ADC need heavy loading when SNZ
*
* BIT_SYSON_PMOPT_SLP_XTAL_EN & BIT_SYSON_PMOPT_SNZ_XTAL_EN
* -WIFI and SOC both need XTAL when work,
* -but WIFI have individual option to control XTAL, so BIT_SYSON_PMOPT_SNZ_XTAL_EN not needed
*
* BIT_SYSON_PMOPT_SLP_SYSPLL_EN & BIT_SYSON_PMOPT_SNZ_SYSPLL_EN
* -WIFI and SOC both have individual PLL, here is SOC 500M PLL
* -So BIT_SYSON_PMOPT_SNZ_SYSPLL_EN not needed
*
* BIT_SYSON_SNFEVT_WIFI_MSK = 1 & BIT_SYSON_BYPASS_SNZ_SLP = 1
* - after OS suspend, platform will enter SNZ and close CPU, then platform enter sleep mode when WIFI 32K
* - BIT_SYSON_PMOPT_SNZ_EN_SOC should never open, or CPU will not close when platform will enter SNZ
*
* BIT_SYSON_SNFEVT_WIFI_MSK = 1 & BIT_SYSON_BYPASS_SNZ_SLP = 0 (not use this config)
* - after OS suspend, platform will enter sleep mode & close CPU after WIFI 32K
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PMC_Exported_Constants PMC Exported Constants
* @{
*/
/** @defgroup SOCPS_PS_Wakeup_Pin_definitions
* @{
*/
#define WAKUP_0 ((u32)0x00000000)/*!< see aon_wakepin */
#define WAKUP_1 ((u32)0x00000001)/*!< see aon_wakepin */
#define WAKUP_2 ((u32)0x00000002)/*!< see aon_wakepin */
#define WAKUP_3 ((u32)0x00000003)/*!< see aon_wakepin */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
typedef struct
{
u32 km0_config_wifi_enable;
u32 km0_enable_key_touch;
u32 km0_tickles_debug; /* open km0 tickles log, it will encrease power consumption */
u32 km0_osc2m_close; /* just uart and normal ADC(2M/12=166K) use it, captouch ADC use 131K */
u32 km0_pg_enable;
u32 km0_rtc_calibration;
u32 km0_audio_pad_enable;
/* debug */
u32 km0_fw_idle_time;
u32 km0_clk_down_time;
u32 km0_rf_off_time;
u32 km0_gating_time;
u32 km0_rf_on_time;
u32 km0_wake_time;
u32 km0_dur1;
} PSCFG_TypeDef;
typedef struct
{
u32 wifi_app_ctrl_tdma; /* Enable APP Control TDMA */
u32 wifi_ultra_low_power; /* Enable WIFI low power RX */
u32 km4_cache_enable; /* km4 cache enable, carefull about SRAM data sync when use DMA */
u32 km0_dslp_force_reinit; /* km0 reinit all when wake from DLPS */
} WIFICFG_TypeDef;
extern PSCFG_TypeDef ps_config;
extern WIFICFG_TypeDef wifi_config;
void SOCPS_SetWakeEventAON(u32 Option, u32 NewStatus);
void SOCPS_SleepCG_RAM(VOID);
void SOCPS_SWR_PFMForce(u32 NewStatus);
int SOCPS_WakeEvent(void);
#endif //_RTL8721D_PMC_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_pmc.h
|
C
|
apache-2.0
| 6,598
|
/**
******************************************************************************
* @file rtl8721d_psram.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the PSRAM firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_PSRAM_H
#define _RTL8710B_PSRAM_H
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup PSRAM
* @brief PSRAM driver modules
* @{
*/
/** @addtogroup PSRAM
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* PSRAM_Controller is used to communicate with PSRAM
* PSRAM:
* - IPclk: 50Mhz
* - Memory Size: 32M bits
* - Address Mapping: 0x0200_0000 ~ 0x0240_0000
* - Access: direct access or dpin mode
* - IRQ: PSRAMC_IRQ
* - GDMA: Support
*
*****************************************************************************************
* How to use PSRAM_Controller to direct access PSRAM memory
*****************************************************************************************
* To direct access PSRAM memory, the following steps are mandatory:
*
* 1. Program read/write Latency, access mode, refresh_rate
* PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 2. Init Hardware use step1 parameters:
* PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 3. Calibration the best rwds delay line:
* PSRAM_calibration()
*
* 4. Access PSRAM memory normally
*
*****************************************************************************************
* How to use PSRAM_Controller to access PSRAM by Dpin mode
*****************************************************************************************
* To access PSRAM by Dpin mode, the following steps are mandatory:
*
* 1. Program read/write Latency, access mode, refresh_rate
* PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 2. Init Hardware use step1 parameters:
* PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 3. Calibration the best rwds delay line:
* PSRAM_calibration()
*
* 4. Generate PSRAM command address value for dpin mode
* PSRAM_CTRL_CA_Gen()
*
* 5. Access PSRAM memory/registers by dpin mode
* PSRAM_CTRL_DPin_Mem():Access PSRAM memory
* PSRAM_CTRL_DPin_Reg():Access PSRAM register
*
* @note: Cache should be disable during DPIN mode
*
*****************************************************************************************
* How to use PSRAM_Controller to access PSRAM by DMA mode
*****************************************************************************************
* To access PSRAM by DMA mode, the following steps are mandatory:
*
* 1. Program read/write Latency, access mode, refresh_rate
* PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 2. Init Hardware use step1 parameters:
* PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct)
*
* 3. Calibration the best rwds delay line:
* PSRAM_calibration()
*
* 4. Alloc a free channel for PSRAM GDMA and register GDMA IRQ callback function and data
* GDMA_ChnlAlloc()
*
* 5. GDMA related configurations(source address/destination address/block size etc.)
* GDMA_StructInit():Fills GDMA_InitStruct member with its default value
* GDMA_Init():Init GDMA
* GDMA_BurstEnable():Enable GDMA Burst Transmission
*
* 6. Active the PSRAM DMA Request using the function GDMA_Cmd()
*
* @note: The Maximum Msize of Channel0 is different from other Channels
* Maximum Msize of Channel0 is 256
* Maximum Msize of Channel1 ~ Channel5 is 8
*
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PSRAM_Exported_Types PSRAM Exported Types
* @{
*/
/**
* @brief PSRAM Init structure definition
*/
typedef struct {
u8 PCTL_dfi_cs_wr_dly; /*!< Specifies the latency contrast between PHY write data path latency
and PHY command path latency.
This parameter must be set to a value in the 0-15 range */
u8 PCTL_dfi_cs_rd_dly; /*!< Specifies the latency contrast between PHY read data enable path
latency and PHY command path latency .
This parameter must be set to a value in the 0-15 range */
u8 PCTL_tphy_wrdata; /*!< Specifies the delay latency from DFI write command to DFI write data.
This parameter is proposed to set PCTL_wl+2 */
u8 PCTL_fix_tphy_lat; /*!< Specifies thePSRAM_LPC_CTRL uses TPHY_WRDATA or TPHY_RDDATA only .
This parameter can be a value of @ref PSRAM_TPHY_LAT_definitions */
u8 PCTL_tphy_rddata; /*!< Specifies the delay latency from DFI read command to DFI read data.
This parameter is proposed to set PCTL_rl+3 */
u8 PCTL_dfi_path_dly; /*!< Specifies which TPHY_WRATA/TPHY_RDDATA cycle to sample DFI latency.
This parameter is proposed to set PCTL_wl */
u8 PCTL_wl; /*!< Specifies the PSRAM write latency .
This parameter must be set to a value in the 3-6 range */
u8 PCTL_rl; /*!< Specifies the PSRAM read latency.
This parameter must be set to a value in the 3-6 range */
u32 PCTL_tcph_ps; /*!< Specifies the PSRAM CE# pin HIGH cycles between subsequent command.
This parameter unit is ps */
u32 PCTL_tpu_ps; /*!< Specifies the time between access PSRAM and RESET# pin high.
This parameter unit is ps */
u32 PCTL_tcem_ps; /*!< Specifies the maximum average Refresh commands delay cycles.
This parameter unit is ps */
u32 PCTL_clk_ps; /*!< Specifies the PSRAM clock cycle.
This parameter unit is ps */
u8 PCTL_mr0_burst_len; /*!< Specifies the PSRAM burst length.
This parameter can be a value of @ref PSRAM_BURST_LENGTH_definitions */
u8 PCTL_mr0_burst_type; /*!< Specifies the PSRAM wrapped burst type.
This parameter can be a value of @ref PSRAM_BURST_TYPE_definitions */
u8 PCTL_mr0_lat_mode; /*!< Specifies the PSRAM whether fix latency.
This parameter can be a value of @ref PSRAM_LATENCY_MODE_definitions */
u8 PCTL_mr0_init_lat; /*!< Specifies the PSRAM initial latency.
This parameter can be a value of @ref PSRAM_INIT_LATENCY_definitions */
u8 PCTL_mr0_drv_strength; /*!< Specifies the PSRAM drive strength.
This parameter can be a value of @ref PSRAM_DRV_STRENGTH_definitions */
u8 PCTL_mr0_dpd_en; /*!< Specifies the PSRAM whether enter deep power pown.
This parameter can be a value of @ref PSRAM_DPD_definitions */
u8 PCTL_mr1_pasr; /*!< Specifies the PSRAM partial array self refresh.
This parameter can be a value of @ref PSRAM_PASR_definitions */
u8 PCTL_mr1_half_slp; /*!< Specifies the PSRAM half sleep mode set.
This parameter can be a value of @ref PSRAM_HALF_SLP_definitions */
u8 PCTL_mr1_refresh_rate; /*!< Specifies the PSRAM refresh rate.
This parameter can be a value of @ref PSRAM_REFRESH_RATE_definitions */
} PCTL_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PSRAM_Exported_Constants PSRAM Exported Constants
* @{
*/
/** @defgroup PSRAM_Peripheral_definitions
* @{
*/
#define IS_PSRAM_ALL_PERIPH(PERIPH) ((PERIPH) == PSRAM_DEV)
/**
* @}
*/
/** @defgroup PSRAM_TPHY_LAT_definitions
* @{
*/
#define PSRAM_FIX_TPHY_LATENCY 1
#define PSRAM_UNSET_TPHY_LATENCY 0
/**
* @}
*/
/** @defgroup PSRAM_BURST_LENGTH_definitions
* @{
*/
#define PSRAM_BURST_LENGTH_128B 0
#define PSRAM_BURST_LENGTH_64B 1
#define PSRAM_BURST_LENGTH_16B 2
#define PSRAM_BURST_LENGTH_32B 3
/**
* @}
*/
/** @defgroup PSRAM_BURST_TYPE_definitions
* @{
*/
#define PSRAM_BURST_VENDOR_TYPE 0
#define PSRAM_BURST_LEGACY_TYPE 1
/**
* @}
*/
/** @defgroup PSRAM_LATENCY_MODE_definitions
* @{
*/
#define PSRAM_2TIMES_LATENCY_FIXED 1
#define PSRAM_VARIABLE_LATENCY 0
/**
* @}
*/
/** @defgroup PSRAM_INIT_LATENCY_definitions
* @{
*/
#define PSRAM_INIT_LATENCY_5CLK 0
#define PSRAM_INIT_LATENCY_6CLK 1
#define PSRAM_INIT_LATENCY_3CLK 0xe
#define PSRAM_INIT_LATENCY_4CLK 0xf
/**
* @}
*/
/** @defgroup PSRAM_DRV_STRENGTH_definitions
* @{
*/
#define PSRAM_DRV_STRENGTH_50OHMS 0
#define PSRAM_DRV_STRENGTH_35OHMS 1
#define PSRAM_DRV_STRENGTH_100OHMS 2
#define PSRAM_DRV_STRENGTH_200OHMS 3
/**
* @}
*/
/** @defgroup PSRAM_DPD_definitions
* @{
*/
#define PSRAM_DPD_MODE 0
#define PSRAM_NORMAL_MODE 1
/**
* @}
*/
/** @defgroup PSRAM_PASR_definitions
* @{
*/
#define PSRAM_PASR_FULL_ARRAY 0
#define PSRAM_PASR_BOT_HALF_ARRAY 1
#define PSRAM_PASR_BOT_QUARTER_ARRAY 2
#define PSRAM_PASR_BOT_EIGHTH_ARRAY 3
#define PSRAM_PASR_NONE 4
#define PSRAM_PASR_TOP_HALF_ARRAY 5
#define PSRAM_PASR_TOP_QUARTER_ARRAY 6
#define PSRAM_PASR_TOP_EIGHTH_ARRAY 7
/**
* @}
*/
/** @defgroup PSRAM_HALF_SLP_definitions
* @{
*/
#define PSRAM_HALF_SLP_DIS 0
#define PSRAM_HALF_SLP_EN 1
/**
* @}
*/
/** @defgroup PSRAM_REFRESH_RATE_definitions
* @{
*/
#define PSRAM_REFRESH_RATE_FAST 0
#define PSRAM_REFRESH_RATE_NORMAL 1
/**
* @}
*/
/** @defgroup PSRAM_BURST_TYPE_definitions
* @{
*/
#define PSRAM_WRAPPED_TYPE 0
#define PSRAM_LINEAR_TYPE 1
#define IS_PSRAM_BURST_TYPE(TYPE) (((TYPE) == PSRAM_WRAPPED_TYPE) || \
((TYPE) == PSRAM_LINEAR_TYPE))
/**
* @}
*/
/** @defgroup PSRAM_ADDR_SPACE_definitions
* @{
*/
#define PSRAM_MEM_SPACE 0
#define PSRAM_REG_SPACE 1
#define IS_PSRAM_ADDR_SPACE(MODE) (((MODE) == PSRAM_MEM_SPACE) || \
((MODE) == PSRAM_REG_SPACE))
/**
* @}
*/
/** @defgroup PSRAM_WR_TRANSACTION_definitions
* @{
*/
#define PSRAM_WRITE_TRANSACTION 0
#define PSRAM_READ_TRANSACTION 1
#define IS_PSRAM_WR_TRANSACTION(MODE) (((MODE) == PSRAM_WRITE_TRANSACTION) || \
((MODE) == PSRAM_READ_TRANSACTION))
/**
* @}
*/
/** @defgroup PSRAM_DPIN_WR_MODE_definitions
* @{
*/
#define PSRAM_DPIN_READ_MODE 0 << 17
#define PSRAM_DPIN_WRITE_MODE 1 << 17
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PSRAM_Exported_Functions PSRAM Exported Functions
* @{
*/
_LONG_CALL_ void PSRAM_CTRL_StructInit(PCTL_InitTypeDef *PCTL_InitStruct);
_LONG_CALL_ void PSRAM_CTRL_Init(PCTL_InitTypeDef *PCTL_InitStruct);
_LONG_CALL_ void PSRAM_CTRL_CA_Gen(u8* PSRAM_CA, u32 StartAddr, u8 BurstType, u8 AddSpace, u8 RW);
_LONG_CALL_ void PSRAM_CTRL_DPin_Mem(u8* PSRAM_CA, u32* PSRAM_data, u32 PSRAM_byteen, u8 RW);
_LONG_CALL_ void PSRAM_CTRL_DPin_Reg(u8* PSRAM_CA, u32* PSRAM_data, u8 RW);
_LONG_CALL_ u32 PSRAM_PHY_REG_Read(u8 offset);
_LONG_CALL_ void PSRAM_PHY_REG_Write(u8 offset, u32 reg_val);
_LONG_CALL_ BOOL PSRAM_calibration(VOID);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/** @defgroup PSRAM_Register_Definitions PSRAM Register Definitions
* @{
*/
/**************************************************************************//**
* @defgroup PSRAM_CCR
* @{
*****************************************************************************/
/******************** Bits definition for CCR register *******************/
#define BIT_PSRAM_CR_UPDATE ((u32)0x00000001 << 31) /*Bit[31],bit for update the internal timing/control registers or Quick INIT done*/
#define BIT_PSRAM_FLUSH_FIFO ((u32)0x00000001 << 8) /*Bit[8],bit for flush all FIFO in PSRAM_LPC_CTRL*/
#define BIT_PSRAM_DPIN ((u32)0x00000001 << 3) /*Bit[3],bit for start to set PSRAM command function*/
#define BIT_PSRAM_INIT ((u32)0x00000001) /*Bit[0],bit for start to issue PSRAM initialization sequence*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_DCR
* @{
*****************************************************************************/
/******************** Bits definition for DCR register *******************/
#define BIT_PSRAM_AADMUX ((u32)0x00000001 << 20) /*Bit[20], bit for indicate the target PSRAM is AADMUX type or ADMUX or mormal type*/
#define BIT_PSRAM_PAGE_SIZE ((u32)0x0000000f << 16) /*Bit[19:16], bits for indicate the target PSRAM page size*/
#define BIT_PSRAM_SUSPEND_EN ((u32)0x00000001 << 9) /*Bit[9], bit for indicate PSRAM_CTRL support SUSPEND command*/
#define BIT_PSRAM_CLK_EN ((u32)0x00000001 << 8) /*Bit[8], bit for indicate PSRAM at asynchronous mode clock enable*/
#define BIT_PSRAM_CRE_EN ((u32)0x00000001 << 7) /*Bit[7], bit for indicate access PSRAM register mode*/
#define BIT_PSRAM_DFI_RATE ((u32)0x00000007 << 4) /*Bit[6:4], bits for set DFI ratio*/
#define BIT_PSRAM_DDR_MODE ((u32)0x00000001 << 3) /*Bit[3], bit for indicate the PSRAM work at DDR mode or SDR mode*/
#define BIT_PSRAM_ASYNC_MODE ((u32)0x00000001 << 2) /*Bit[2], bit for indicate the PSRAM work at asynchronous mode or synchronous mode*/
#define BIT_PSRAM_DQ ((u32)0x00000003) /*Bit[1:0], bits for set the PSRAM architecture*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_IOCR0
* @{
*****************************************************************************/
/******************** Bits definition for IOCR0 register *******************/
#define BIT_PSRAM_DFI_PATH_DLY_MASK ((u32)0x0000001f << 25) /*Bit[29:25], bits for select which TPHY_WRATA/TPHY_RDDATA cycle to sample dfi_latency_en*/
#define BIT_PSRAM_DFI_PATH_DLY_SHIFT 25
#define BIT_PSRAM_TPHY_RDDATA_EN_MASK ((u32)0x0000001f << 20) /*Bit[24:20], bits for setting the delay latency from DFI read command to dfi_rddata_en signal*/
#define BIT_PSRAM_TPHY_RDDATA_EN_SHIFT 20
#define BIT_PSRAM_FIX_TPHY_LAT_MASK ((u32)0x00000001 << 19) /*Bit[19], bit for PSRAM_LPC_CTRL uses TPHY_WRDATA or TPHY_RDDATA only*/
#define BIT_PSRAM_FIX_TPHY_LAT_SHIFT 19
#define BIT_PSRAM_TPHY_WRDATA_MASK ((u32)0x0000001f << 12) /*Bit[16:12], bits for setting the delay latency from DFI write command to DFI write data*/
#define BIT_PSRAM_TPHY_WRDATA_SHIFT 12
#define BIT_PSRAM_RD_PIPE_MASK ((u32)0x0000000f << 8) /*Bit[11:8], bits for SDR mode read data delay setting*/
#define BIT_PSRAM_RD_PIPE_SHIFT 8
#define BIT_PSRAM_DFI_CS_RD_DLY_MASK ((u32)0x0000000f << 4) /*Bit[7:4], bits for setting the latency contrast between PHY write data path latency and
PHY command path latency*/
#define BIT_PSRAM_DFI_CS_RD_DLY_SHIFT 4
#define BIT_PSRAM_DFI_CS_WR_DLY_MASK ((u32)0x0000000f) /*Bit[3:0], bits for setting the latency contrast between PHY read data enable path latency
and PHY command path latency*/
#define BIT_PSRAM_DFI_CS_WR_DLY_SHIFT 0
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_CSR
* @{
*****************************************************************************/
/******************** Bits definition for CSR register *******************/
#define BIT_PSRAM_DPIN_MODE ((u32)0x00000003 << 17) /*Bit[18:17], bit for DPIN mode decode*/
#define BIT_PSRAM_MEM_IDLE ((u32)0x00000001 << 8) /*Bit[8], bit for disable memory access state*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_DRR
* @{
*****************************************************************************/
/******************** Bits definition for DRR register *******************/
#define BIT_PSRAM_PU_TIME_MASK ((u32)0x0000007f << 15) /*Bit[21:15], bits for If non-defined CR_INTI_RMBIT configuration*/
#define BIT_PSRAM_PU_TIME_SHIFT 15
#define BIT_PSRAM_CEM_TIME_MASK ((u32)0x000007ff << 4) /*Bit[14:4], bits for Maximum average Refresh commands delay cycles*/
#define BIT_PSRAM_CEM_TIME_SHIFT 4
#define BIT_PSRAM_CPH_TIME_MASK ((u32)0x0000000f) /*Bit[3:0], bits for PSRAM CE# pin HIGH cycles between subsequent command*/
#define BIT_PSRAM_CPH_TIME_SHIFT 0
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_CMD_DPIN_NDGE
* @{
*****************************************************************************/
/******************** Bits definition for CMD_DPIN_NDGE register *******************/
#define BIT_PSRAM_DPIN_ADDR_NDGE ((u32)0x00ffffff) /*Bit[23:0], bits for PSRAM command address value in DPIN function at negative edge*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_CMD_DPIN
* @{
*****************************************************************************/
/******************** Bits definition for CMD_DPIN register *******************/
#define BIT_PSRAM_DPIN_ADDR_POSI ((u32)0x00ffffff) /*Bit[23:0], bits for PSRAM command address value in DPIN function at positive edge*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_CR_TDPIN
* @{
*****************************************************************************/
/******************** Bits definition for CR_TDPIN register *******************/
#define BIT_PSRAM_DFI_RESET_N ((u32)0x00000001) /*Bit[0], bit for set the PSRAM TDPIN register value*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_MR_INFO
* @{
*****************************************************************************/
/******************** Bits definition for MR_INFO register *******************/
#define BIT_PSRAM_RL_LATENCY_MASK ((u32)0x0000001f << 5) /*Bit[9:5], bits for indicate PSRAM read latency counter*/
#define BIT_PSRAM_RL_LATENCY_SHIFT 5
#define BIT_PSRAM_WL_LATENCY_MASK ((u32)0x0000001f) /*Bit[4:0], bits for indicate PSRAM write latency counter*/
#define BIT_PSRAM_WL_LATENCY_SHIFT 0
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_MR0
* @{
*****************************************************************************/
/******************** Bits definition for MR0 register *******************/
#define BIT_PSRAM_MR0_MASK ((u32)0x0000ffff) /*Bit[15:0], bits for setting the value to PSRAM CR0 register in initialization flow*/
#define BIT_PSRAM_MR0_BURST_DPD_MODE_MASK ((u32)0x00000001)
#define BIT_PSRAM_MR0_BURST_DPD_MODE_SHIFT 15
#define BIT_PSRAM_MR0_BURST_DRV_STRENGTH_MASK ((u32)0x00000007)
#define BIT_PSRAM_MR0_BURST_DRV_STRENGTH_SHIFT 12
#define BIT_PSRAM_MR0_BURST_RSVD_MASK ((u32)0x0000000f)
#define BIT_PSRAM_MR0_BURST_RSVD_SHIFT 8
#define BIT_PSRAM_MR0_BURST_INIT_LAT_MASK ((u32)0x0000000f)
#define BIT_PSRAM_MR0_BURST_INIT_LAT_SHIFT 4
#define BIT_PSRAM_MR0_BURST_LAT_MODE_MASK ((u32)0x00000001)
#define BIT_PSRAM_MR0_BURST_LAT_MODE_SHIFT 3
#define BIT_PSRAM_MR0_BURST_TYPE_MASK ((u32)0x00000001)
#define BIT_PSRAM_MR0_BURST_TYPE_SHIFT 2
#define BIT_PSRAM_MR0_BURST_LENGTH_MASK ((u32)0x00000003)
#define BIT_PSRAM_MR0_BURST_LENGTH_SHIFT 0
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_MR1
* @{
*****************************************************************************/
/******************** Bits definition for MR1 register *******************/
#define BIT_PSRAM_MR1_MASK ((u32)0x0000ffff) /*Bit[15:0], bits for setting the value to PSRAM CR1 register in initialization flow*/
#define BIT_PSRAM_MR1_REFRESH_RATE_MASK ((u32)0x00000001)
#define BIT_PSRAM_MR1_REFRESH_RATE_SHIFT 6
#define BIT_PSRAM_MR1_HALF_SLP_MODE_MASK ((u32)0x00000001)
#define BIT_PSRAM_MR1_HALF_SLP_MODE_SHIFT 5
#define BIT_PSRAM_MR1_PASR_MASK ((u32)0x00000007)
#define BIT_PSRAM_MR1_PASR_SHIFT 0
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_DPDRI
* @{
*****************************************************************************/
/******************** Bits definition for DPDRI register *******************/
#define BIT_PSRAM_DPIN_DATA_INDEX ((u32)0x0000000f) /*Bit[3:0], bits for indicate select which DPIN DATA register .*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_DPDR
* @{
*****************************************************************************/
/******************** Bits definition for DPDR register *******************/
#define BIT_PSRAM_DPIN_DATA ((u32)0xffffffff) /*Bit[31:0], bits for indicate the data which will be written to PSRAM or the data
read from PSRAM.*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_PCTL_SVN_ID
* @{
*****************************************************************************/
/******************** Bits definition for PCTL_SVN_ID register *******************/
#define BIT_PSRAM_CTRL_GIT_CNT ((u32)0x0000ffff << 16) /*Bit[31:16], bits for indicate the Git counter of the released RTL code.*/
#define BIT_PSRAM_CTRL_RELEASE_DATE ((u32)0x0000ffff) /*Bit[15:0], bits for indicate the IP release date for the particular project.*/
/** @} */
/**************************************************************************//**
* @defgroup PSRAM_PCTL_IDR
* @{
*****************************************************************************/
/******************** Bits definition for PCTL_IDR register *******************/
#define BIT_PSRAM_CTRL_CR_VER ((u32)0x0000ffff << 16) /*Bit[31:16], bits for control register version number.*/
#define BIT_PSRAM_CTRL_CR_PCTL_DEF ((u32)0x0000ffff) /*Bit[15:0], bits for user definition or support PSRAM type.*/
/** @} */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************** Bits definition for REG_PSRAM_CAL_CTRL register *******************/
#define BIT_PSRAM_CFG_CAL_INTR ((u32)0x00000001 << 16) /*Bit[16], bit for Interrupt flag raised by calibration.*/
#define BIT_PSRAM_CFG_CAL_INTR_MASK ((u32)0x00000001 << 8) /*Bit[8], bit for Calibration fail interrupt mask.*/
#define BIT_PSRAM_CFG_CAL_THD_MASK ((u32)0x0000000f) /*Bit[7:4], bits for Error check threshold value , used as a filter*/
#define BIT_PSRAM_CFG_CAL_THD_SHIFT 4
#define BIT_PSRAM_CFG_CAL_EN ((u32)0x00000001) /*Bit[0], bit for Hardware auto calibration enable.*/
/******************** Bits definition for REG_PSRAM_CAL_PARA register *******************/
#define BIT_PSRAM_CFG_CAL_JMIN_MASK ((u32)0x00000007) /*Bit[26:24], bits for Minimum J.*/
#define BIT_PSRAM_CFG_CAL_JMIN_SHIFT 24
#define BIT_PSRAM_CFG_CAL_JMAX_MASK ((u32)0x0000000f) /*Bit[19:16], bits for Maximum J.*/
#define BIT_PSRAM_CFG_CAL_JMAX_SHIFT 16
#define BIT_PSRAM_CFG_CAL_J_MASK ((u32)0x0000000f) /*Bit[11:8], bits for Initial value J calibrated by software.*/
#define BIT_PSRAM_CFG_CAL_J_SHIFT 8
#define BIT_PSRAM_CFG_CAL_N_MASK ((u32)0x0000001f) /*Bit[4:0], bits for Initial value N calibrated by software.*/
#define BIT_PSRAM_CFG_CAL_N_SHIFT 0
/******************** Bits definition for REG_PSRAM_CAL_STATUS register *******************/
#define BIT_PSRAM_CFG_CAL_CUR_ST_MASK ((u32)0x0000001f) /*Bit[28:24], bits for Calibration current state.*/
#define BIT_PSRAM_CFG_CAL_CUR_ST_SHIFT 24
#define BIT_PSRAM_CFG_CAL_PDST_MASK ((u32)0x00000007) /*Bit[18:16], bits for Calibration check result for last read burst.*/
#define BIT_PSRAM_CFG_CAL_PDST_SHIFT 16
#define BIT_PSRAM_CFG_CAL_CUR_J_MASK ((u32)0x0000000f) /*Bit[11:8], bits for Current value J read from hardware.*/
#define BIT_PSRAM_CFG_CAL_CUR_J_SHIFT 8
#define BIT_PSRAM_CFG_CAL_CUR_N_MASK ((u32)0x0000001f) /*Bit[4:0], bits for Current value N read from hardware.*/
#define BIT_PSRAM_CFG_CAL_CUR_N_SHIFT 0
/******************** Bits definition for REG_PSRAM_CMD_ADDR_INFO_L register *******************/
#define BIT_PSRAM_CMD_ADDR_INFO_L_MASK ((u32)0xffffffff) /*Bit[31:0], bits for Command/Address information[31:0].*/
/******************** Bits definition for REG_PSRAM_CMD_ADDR_INFO_H register *******************/
#define BIT_PSRAM_CMD_ADDR_INFO_H_MASK ((u32)0x0000ffff) /*Bit[15:0], bits for Command/Address information[47:32].*/
/******************** Bits definition for REG_PSRAM_BYTE_CNT_INFO register *******************/
#define BIT_PSRAM_WBYTE_ACCU_MASK ((u32)0x000000ff) /*Bit[31:24], bits for length of write data given by psram controller, will be cleared at the end of this Transaction.*/
#define BIT_PSRAM_WBYTE_ACCU_SHIFT 24
#define BIT_PSRAM_WBYTE_CNT_MASK ((u32)0x000000ff) /*Bit[23:16], bits for length of data written to psram controller, will be cleared at the end of this Transaction.*/
#define BIT_PSRAM_WBYTE_CNT_SHIFT 16
#define BIT_PSRAM_RBYTE_ACCU_MASK ((u32)0x000000ff) /*Bit[15:8], bits for length of read data given by psram controller, will be cleared at the beginning of next Transaction.*/
#define BIT_PSRAM_RBYTE_ACCU_SHIFT 8
#define BIT_PSRAM_RBYTE_CNT_MASK ((u32)0x000000ff) /*Bit[7:0], bits for length of data read from psram controller, will be cleared at the beginning of next Transaction.*/
#define BIT_PSRAM_RBYTE_CNT_SHIFT 0
/******************** Bits definition for REG_PSRAM_TIME_OUT_CTRL register *******************/
#define BIT_PSRAM_TIME_OUT_INTR ((u32)0x00000001 << 31) /*Bit[31], bit for read transaction time out interrupt flag.*/
#define BIT_PSRAM_TIME_OUT_INTR_MASK ((u32)0x00000001 << 23) /*Bit[23], bit for read transaction time out interrupt mask.*/
#define BIT_PSRAM_TIME_OUT_THOLD_MASK ((u32)0x000000ff) /*Bit[7:0], bits for read transaction time out threshold.*/
#define BIT_PSRAM_TIME_OUT_THOLD_SHIFT 0
/******************** Bits definition for REG_PSRAM_DBG_SEL register *******************/
#define BIT_PSRAM_PSRAM_PHY_DBG_SEL_MASK ((u32)0xff) /*Bit[7:0], bits for psram phy debug select signal.*/
#define BIT_PSRAM_PSRAM_PHY_DBG_SEL_SHIFT 0
/******************** Bits definition for REG_PSRAM_DBG_INFO register *******************/
#define BIT_PSRAM_PSRAM_PHY_DBG_MASK ((u32)0xffffffff) /*Bit[31:0], bits for psram phy debug signals.*/
#define BIT_PSRAM_PSRAM_PHY_DBG_SHIFT 0
/******************** PSRAM PHY register *******************/
#define REG_PSRAM_CAL_CTRL 0x000 /*!< PSRAM PHY Calibration control register */
#define REG_PSRAM_CAL_PARA 0x004 /*!< PSRAM PHY Calibration parameter register*/
#define REG_PSRAM_CAL_STATUS 0x008 /*!< PSRAM PHY Calibration status register*/
#define REG_PSRAM_CMD_ADDR_INFO_L 0x010 /*!< PSRAM Command/address information register[31:0]*/
#define REG_PSRAM_CMD_ADDR_INFO_H 0x014 /*!< PSRAM Command/address information register[48:32]*/
#define REG_PSRAM_BYTE_CNT_INFO 0x018 /*!< PSRAM Byte Counts register*/
#define REG_PSRAM_TIME_OUT_CTRL 0x01C /*!< PSRAM Timeout Control register*/
#define REG_PSRAM_DBG_SEL 0x0F0 /*!< PSRAM Debug select register*/
#define REG_PSRAM_DBG_INFO 0x0F8 /*!< PSRAM Debug information register*/
/* Other definations --------------------------------------------------------*/
typedef struct
{
u32 psram_dev_enable; /*enable psram*/
u32 psram_dev_cal_enable; /*enable psram calibration function*/
u32 psram_dev_retention; /*enable psram retention when km4 enter low power mode*/
u32 psram_heap_start_address; /*config psram heap start address*/
u32 psram_heap_size; /*config psram heap size*/
} PSRAMCFG_TypeDef;
extern PSRAMCFG_TypeDef psram_dev_config;
#endif //_RTL8710B_PSRAM_H
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_psram.h
|
C
|
apache-2.0
| 28,272
|
/**
******************************************************************************
* @file rtl8721d_qdec.h
* @author
* @version V1.0.0
* @date 2017-10-16
* @brief This file contains all the functions prototypes for the QDecoder.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_QDEC_H_
#define _RTL8721D_QDEC_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @addtogroup QDecoder QDecoder
* @{
*/
/** @addtogroup QDecoder
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* QDEC:
* - Base Address: QDEC_DEV
* - Sclk: 32K/2Mhz
* - HW input : PHA, PHB, IDX
* - Sample Clock: Configurable, up to 2Mhz
* - Debounce Timer: Configurable
* - IRQ: QDECODER_IRQ_LP
*
*****************************************************************************************
* How to use Normal QDecoder
*****************************************************************************************
* To use the normal QDecoder mode, the following steps are mandatory:
*
* 1. configure the QDec pinmux
*
* 2. Init Qdec
* QDEC_StructInit(QDEC_InitTypeDef *QDEC_InitStruct)
* QDEC_Init(QDEC_TypeDef *QDec, QDEC_InitTypeDef *QDEC_InitStruct)
*
* 3. Reset sub-function if need,eg:
* QDEC_RstPC(QDEC_TypeDef *QDec)
* QDEC_RstRC(QDEC_TypeDef *QDec)
* QDEC_RsALL(QDEC_TypeDef *QDec)
*
* 4. Set Interrupt trigger condition as needed
*
* 5. enable velocity function as needed
*
* 6. Polling status or Get stauts according to the interrupt.
*
*****************************************************************************************
* How to enable velocity function
*****************************************************************************************
* To enable the velocity function, the following steps are mandatory:
*
* 1. Init VcMod and VTmr
* QDEC_SetVcMod(QDEC_TypeDef *QDec, u32 mode)
* QDEC_SetVTmr(QDEC_TypeDef *QDec, u32 duration)
*
* 2. Reset velocity status if need.
* QDEC_VtRst(QDEC_TypeDef *QDec)
*
* 3. Configure interrupt if needed
*
* 4. enable velocity function
* QDEC_VT_Cmd(QDEC_TypeDef *QDec, u32 NewState)
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types --------------------------------------------------------*/
/** @defgroup QDecoder_Exported_Types QDecoder Exported Types
* @{
*/
/**
* @brief QDecoder Init structure definition
*/
typedef struct {
u32 QD_SysClk; /*!< Specifies QDec Bus clock .
This parameter can be a value of @ref QDecoder_Bus_Clock_definitions */
u32 QD_SmpClk; /*!< Specifies Qdec sample clock.
This parameter must be set to a value in the (1/32 ~ 1) * QD_SysClk range. */
u32 QD_DebounceTmr; /*!< Specifies glitch width under QD_DebounceTmr * Tsysclk will be filtered.
This parameter must be set to a value in the 0x1-0x7ff range. */
u32 QD_Rc_Mod; /*!< Specifies rotation counter calc mode.
This parameter can be a value of @ref QDecoder_RC_mode_definition */
u32 QD_Cnt_Sc; /*!< Specifies position counter calc mode.
This parameter can be a value of @ref QDecoder_Cnt_Sc_definition */
u32 QD_MPC; /*!< Specifies max position counter value
This parameter must be set to a value in the 0x0-0xffff range. */
u32 QD_IdxMod; /*!< Specifies Qdecoder index signal work mode.
This parameter can be a value of @ref QDecoder_IDX_Mode_definition */
u32 QD_PC_Rst_Mod; /*!< Specifies Qdecoder position counter reset mode.
This parameter can be a value of @ref QDecoder_PC_Reset_Mode_definition*/
u32 QD_PC_Rst_Phase; /*!< Specifies Qdecoder position counter reset phase.
This parameter can be a value of @ref QDecoder_PC_Reset_PHASE_definition*/
u32 QD_VTmr; /*!< Specifies velocity measure timer in ms, .
This parameter can be a value of in the 0x0-0xffffff*Tsysclk range */
u32 QD_VCMod; /*!< Specifies velocity counter mode .
This parameter can be a value of @ref QDecoder_VC_Work_Mode_definitions */
}QDEC_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup QDecoder_Exported_Constants Qdecoder Exported Constants
* @{
*/
/** @defgroup QDecoder_Peripheral_definitions
* @{
*/
#define IS_QDEC_ALL_PERIPH(PERIPH) ((PERIPH) == QDEC_DEV)
/**
* @}
*/
/** @defgroup QDecoder_Bus_Clock_definitions
* @{
*/
#define QD_SYS_CLK_32K ((u32)32768)
#define QD_SYS_CLK_2M ((u32)2000000)
#define IS_QD_SYS_CLK(CLK) (((CLK) == QD_SYS_CLK_32K) || \
((CLK) == QD_SYS_CLK_2M))
/**
* @}
*/
/** @defgroup QDecoder_Clock_selection
* @{
*/
#define QDEC_CLK_SEL_32K ((u32)0x00000001)
#define QDEC_CLK_SEL_2M ((u32)0x00000000)
/**
* @}
*/
/** @defgroup QDecoder_RC_mode_definition
* @{
*/
#define QD_RC_COUNT_IDX ((u32)0x00000000 << 28)
#define QD_RC_COUNT_OF ((u32)0x00000001 << 28)
#define IS_QD_RC_COUNT_MOD(MODE) (((MODE) == QD_RC_COUNT_IDX) || \
((MODE) == QD_RC_COUNT_OF))
/**
* @}
*/
/** @defgroup QDecoder_Cnt_Sc_definition
* @{
*/
#define QD_PC_1PHSAE_1COUNTER ((u32)0x00000000 << 13)
#define QD_PC_2PHSAE_1COUNTER ((u32)0x00000001 << 13)
#define IS_QD_PC_PHASE_COUTER(CNT) (((CNT) == QD_PC_2PHSAE_1COUNTER) || \
((CNT) == QD_PC_1PHSAE_1COUNTER))
/**
* @}
*/
/** @defgroup QDecoder_PC_Chang_Level_definition
* @{
*/
#define QD_PC_CHG_1COUNTER ((u32)0x00000000 << 3)
#define QD_PC_CHG_2COUNTER ((u32)0x00000001 << 3)
#define QD_PC_CHG_4COUNTER ((u32)0x00000002 << 3)
#define IS_QD_PC_CHG_COUTER(CNT) (((CNT) == QD_PC_CHG_1COUNTER) || \
((CNT) == QD_PC_CHG_2COUNTER) ||((CNT) == QD_PC_CHG_4COUNTER))
/**
* @}
*/
/** @defgroup QDecoder_IDX_Mode_definition
* @{
*/
#define QD_IDX_DISABLE ((u32)0x00000000 << 31)
#define QD_IDX_NORMAL (((u32)0x00000001 << 31) | ((u32)0x00000000 << 5))
#define QD_IDX_INVERSE (((u32)0x00000001 << 31) | ((u32)0x00000001 << 5))
#define IS_QD_IDX_MODE(MODE) (((MODE) == QD_IDX_DISABLE) || \
((MODE) == QD_IDX_NORMAL) || ((MODE) == QD_IDX_INVERSE))
/**
* @}
*/
/** @defgroup QDecoder_PC_Reset_PHASE_definition
* @{
*/
#define QD_PC_RST_AUTO_IDX ((u32)0x00000001 << 6)
#define QD_PC_RST_PHASE_00 ((u32)0x00000000 )
#define QD_PC_RST_PHASE_01 ((u32)0x00000001)
#define QD_PC_RST_PHASE_10 ((u32)0x00000002)
#define QD_PC_RST_PHASE_11 ((u32)0x00000003)
#define IS_QD_PC_RST_PHASE(PHASE) (((PHASE) == QD_PC_RST_AUTO_IDX) || \
((PHASE) <= 0x00000003))
/**
* @}
*/
/** @defgroup QDecoder_PC_Reset_Mode_definition
* @{
*/
#define QD_PC_RST_DISABLE ((u32)0x00000000 << 3)
#define QD_PC_RST_ONCE ((u32)0x00000001 << 3)
#define QD_PC_RST_ALWAYS ((u32)0x00000002 << 3)
#define IS_QD_PC_RST_MODE(MODE) (((MODE) == QD_PC_RST_DISABLE) || \
((MODE) == QD_PC_RST_ONCE) || ((MODE) == QD_PC_RST_ALWAYS))
/**
* @}
*/
/** @defgroup QDecoder_VC_Work_Mode_definitions
* @{
*/
#define QD_VC_MOD_ABS ((u32)0x00000000 << 9)
#define QD_VC_MOD_PC ((u32)0x00000001 << 9)
#define IS_QD_VC_MODE(MODE) (((MODE) == QD_VC_MOD_ABS) || \
((MODE) == QD_VC_MOD_PC))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup QDecoder_Exported_Functions QDecoder Exported Functions
* @{
*/
/** @defgroup QDecoder_Exported_Normal_Functions QDec Exported Normal Functions
* @{
*/
void QDEC_DeInit(void);
void QDEC_Init(QDEC_TypeDef *QDec, QDEC_InitTypeDef *QDEC_InitStruct);
void QDEC_StructInit(QDEC_InitTypeDef *QDEC_InitStruct);
void QDEC_Cmd(QDEC_TypeDef *QDec, u32 NewState);
void QDEC_RstPC(QDEC_TypeDef *QDec);
void QDEC_RstRC(QDEC_TypeDef *QDec);
void QDEC_RstALL(QDEC_TypeDef *QDec);
void QDEC_SetCntSC(QDEC_TypeDef *QDec, u32 cnt_sc);
void QDEC_SetPChg(QDEC_TypeDef *QDec, u32 Pchange);
void QDEC_SetPCC(QDEC_TypeDef *QDec, u32 CmpPC);
void QDEC_SetMPC(QDEC_TypeDef *QDec, u32 MaxPC);
void QDEC_SetRCC(QDEC_TypeDef *QDec, u32 CmpRC);
u32 QDEC_GetRC(QDEC_TypeDef *QDec);
u32 QDEC_GetPhase(QDEC_TypeDef *QDec);
u32 QDEC_GetDir(QDEC_TypeDef *QDec);
u32 QDEC_GetPC(QDEC_TypeDef *QDec);
void QDEC_Idx_Cmd(QDEC_TypeDef *QDec, u32 NewState);
void QDEC_SetRstMod(QDEC_TypeDef *QDec, u32 mode, u32 phase);
void QDEC_SetVTmr(QDEC_TypeDef *QDec, u32 duration);
void QDEC_SetVcMod(QDEC_TypeDef *QDec, u32 mode);
void QDEC_VT_Cmd(QDEC_TypeDef *QDec, u32 NewState);
void QDEC_VtRst(QDEC_TypeDef *QDec);
void QDEC_SetVcUpLmt(QDEC_TypeDef *QDec, u32 limt);
void QDEC_SetVcLowLmt(QDEC_TypeDef *QDec, u32 limt);
u32 QDEC_GetVT(QDEC_TypeDef *QDec);
u32 QDEC_GetVC(QDEC_TypeDef *QDec);
u32 QDEC_GetVCCAP(QDEC_TypeDef *QDec);
u32 QDEC_GetPCCAP(QDEC_TypeDef *QDec);
void QDEC_INTConfig(QDEC_TypeDef *QDec, u32 INT, u32 newState);
void QDEC_INTMask(QDEC_TypeDef *QDec, u32 mask, u32 newState);
void QDEC_ClearINT(QDEC_TypeDef *QDec, u32 INT);
u32 QDEC_GetRawINT(QDEC_TypeDef *QDec);
u32 QDEC_GetIMR(QDEC_TypeDef *QDec);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup QDecoder_Register_Definitions QDecoder Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup QDEC_CLK_CFG
* @{
*****************************************************************************/
#define QD_SMP_DIV ((u32)0x0001F000) /*Bit[16:12], Divider for input signal sampling clock*/
#define QD_DBN_TM ((u32)0x000007FF) /*Bit[10:0], Divider for De-bounce timer clock*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_CTRL
* @{
*****************************************************************************/
#define QD_AXIS_EN ((u32)0x00000001 << 31) /*Bit[31], Qdecoder enable control */
#define QD_PC_RST ((u32)0x00000001 << 30) /*Bit[30], Qdecoder position counter reset control*/
#define QD_RC_RST ((u32)0x00000001 << 29) /*Bit[29], Qdecoder rotation counter reset control*/
#define QD_RC_MOD ((u32)0x00000001 << 28) /*Bit[38], Qdecoder rotation mode*/
#define QD_ALL_RST ((u32)0x00000001 << 27) /*Bit[37], Qdecoder ALL reset control*/
#define QD_RC_CMP_INT_EN ((u32)0x00000001 << 24) /*Bit[24], Qdecoder rotation counter compare INT enable*/
#define QD_PC_ERR_INT_EN ((u32)0x00000001 << 23) /*Bit[23], Qdecoder position counter error INT enable*/
#define QD_IDX_PULSE_INT_EN ((u32)0x00000001 << 22) /*Bit[22], Qdecoder index pulse INT enable*/
#define QD_RC_UF_INT_EN ((u32)0x00000001 << 21) /*Bit[21], Qdecoder rotation counter underflow INT enable*/
#define QD_RC_OF_INT_EN ((u32)0x00000001 << 20) /*Bit[20], Qdecoder rotation counter overflow INT enable*/
#define QD_PC_CMP_INT_EN ((u32)0x00000001 << 19) /*Bit[19], Qdecoder position counter compare INT enable*/
#define QD_DR_CH_INT_EN ((u32)0x00000001 << 18) /*Bit[18], Qdecoder direction changed INT enable*/
#define QD_PC_CHG_INT_EN ((u32)0x00000001 << 17) /*Bit[17], Qdecoder position counter changged INT enable*/
#define QD_PC_OF_INT_EN ((u32)0x00000001 << 16) /*Bit[16], Qdecoder position counter overflow INT enable*/
#define QD_PC_UF_INT_EN ((u32)0x00000001 << 15) /*Bit[15], Qdecoder position counter underflow INT enable*/
#define QD_PHASE_ILL_INT_EN ((u32)0x00000001 << 14) /*Bit[14], Qdecoder phase changed illegal INT enable*/
#define QD_COUNTER_INT ((u32)0x01FFC000) /*Qdecoder counter related INT*/
#define QD_CNT_SC ((u32)0x00000001 << 13) /*Bit[13], Qdecoder number of phase state changed for the position accumulation counter*/
#define QD_DB_EN ((u32)0x00000001 << 12) /*Bit[12], Qdecoder de-bouncing enable*/
#define QD_PC_CHG_LEVEL ((u32)0x00000003 << 3) /*Bit[4:3], Qdecoder position changed interrupt trigger level*/
#define QD_MANUAL_INIT ((u32)0x00000001 << 2) /*Bit[2], Qdecoder manually initial disable*/
#define QD_INIT_PHASE ((u32)0x00000003) /*Bit[1:0], Qdecoder init pahse*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_MPC
* @{
*****************************************************************************/
#define QD_CMP_PC ((u32)0x0000FFFF << 16) /*Bit[31:16], Qdecoder position compare register*/
#define QD_MAX_PC ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder Max position counter register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_RC
* @{
*****************************************************************************/
#define QD_CMP_RC ((u32)0x00000FFF) /*Bit[11:0], Qdecoder rotation compare register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_PC
* @{
*****************************************************************************/
#define QD_RC ((u32)0x00000FFF << 20) /*Bit[31:20], Qdecoder current rotation counter*/
#define QD_PHASE_STATE ((u32)0x00000003 << 18) /*Bit[19:18], Qdecoder current phase state*/
#define QD_AL_STATUS ((u32)0x00000001 << 17) /*Bit[17], Qdecoder auto load status*/
#define QD_DIR_STATE ((u32)0x00000001 <<16) /*Bit[16], Qdecoder move direction*/
#define QD_PC ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder current position counter*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_ISC
* @{
*****************************************************************************/
#define QD_IDX_EN ((u32)0x00000001 << 31) /*Bit[31], Qdecoder index enable*/
#define QD_AUTO_IDX_EN ((u32)0x00000001 << 6) /*Bit[6], Qdecoder Auto-index enable*/
#define BIT_QD_IDX_INVERSE ((u32)0x00000001 << 5) /*Bit[5], Qdecoder index signal input inverse */
#define QD_POS_RST ((u32)0x00000003 << 3) /*Bit[4:3], Qdecoder position reset control*/
#define QD_POS_RST_PHASE ((u32)0x00000003) /*Bit[1:0], Qdecoder reset phase setting*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VCTRL
* @{
*****************************************************************************/
#define QD_VT_DIV ((u32)0x000000FF << 16) /*Bit[23:16], Qdecoder Velocity clock divider*/
#define QD_VMUC_MOD ((u32)0x00000001 << 9) /*Bit[9], Qdecoder Velocity counter increase mode*/
#define QD_VUPLMT_INT_EN ((u32)0x00000001 << 7) /*Bit[7], Qdecoder Velocity up limit interrupt enable */
#define QD_VLOWLMT_INT_EN ((u32)0x00000003 << 6) /*Bit[6], Qdecoder Velocity low limit interrupt enable*/
#define QD_VCCAP_INT_EN ((u32)0x00000001 << 4) /*Bit[4], Qdecoder Velocity counter capture interrupt enable */
#define QD_VELOCITY_INT ((u32)0x000000D0)
#define QD_VMUC_RST ((u32)0x00000001 << 2) /*Bit[2], Qdecoder Velocity reset*/
#define QD_VMUC_EN ((u32)0x00000001) /*Bit[0], Qdecoder Velocity enable*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VC
* @{
*****************************************************************************/
#define QD_VC ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder velocity accumulation counter*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VCCAP
* @{
*****************************************************************************/
#define QD_VCCAP ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder velocity accumulation counter capture register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_PCCAP
* @{
*****************************************************************************/
#define QD_PCCAP ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder position counter capture register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VTRLD
* @{
*****************************************************************************/
#define QD_VTRLD ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder velocity timer reload register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VT
* @{
*****************************************************************************/
#define QD_VT ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder velocity timer register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_VCOMP
* @{
*****************************************************************************/
#define QD_VUP_LMT ((u32)0x0000FFFF << 16) /*Bit[31:16], Qdecoder velocity counter up limit register*/
#define QD_VLOW_LMT ((u32)0x0000FFFF) /*Bit[15:0], Qdecoder velocity counter low limit register*/
/** @} */
/**************************************************************************//**
* @defgroup QDEC_IMR
* @{
*****************************************************************************/
#define QD_RC_COMP_INT_MASK ((u32)0x00000001 << 15) /*Bit[15], Qdecoder rotation counter compare INT mask*/
#define QD_VUPLMT_INT_MASK ((u32)0x00000001 << 13) /*Bit[13], Qdecoder Velocity up limit interrupt mask */
#define QD_VLOWLMT_INT_MASK ((u32)0x00000001 << 12) /*Bit[12], Qdecoder Velocity low limit interrupt mask*/
#define QD_VCCAP_INT_MASK ((u32)0x00000001 << 10) /*Bit[10], Qdecoder Velocity counter capture interrupt mask*/
#define QD_PC_ERR_INT_MASK ((u32)0x00000001 << 9) /*Bit[9], Qdecoder position counter error INT mask*/
#define QD_IDX_PULSE_INT_MASK ((u32)0x00000001 << 8) /*Bit[8], Qdecoder index pulse INT mask*/
#define QD_RC_UF_INT_MASK ((u32)0x00000001 << 7) /*Bit[7], Qdecoder rotation counter underflow INT mask*/
#define QD_RC_OF_INT_MASK ((u32)0x00000001 << 6) /*Bit[6], Qdecoder rotation counter overflow INT mask*/
#define QD_PC_CMP_INT_MASK ((u32)0x00000001 << 5) /*Bit[5], Qdecoder position counter compare INT mask*/
#define QD_DR_CH_INT_MASK ((u32)0x00000001 << 4) /*Bit[4], Qdecoder direction changed INT mask*/
#define QD_PHASE_ILL_INT_MASK ((u32)0x00000001 << 3) /*Bit[3], Qdecoder phase changed illegal INT mask*/
#define QD_PC_UF_INT_MASK ((u32)0x00000001 << 2) /*Bit[2], Qdecoder position counter underflow INT mask*/
#define QD_PC_OF_INT_MASK ((u32)0x00000001 << 1) /*Bit[1], Qdecoder position counter overflow INT mask*/
#define QD_PC_CHG_INT_MASK ((u32)0x00000001 << 0) /*Bit[0], Qdecoder position counter changed INT mask*/
#define QD_ALL_INT_MASK ((u32)0x0000B7FF)
/** @} */
/**************************************************************************//**
* @defgroup QDEC_ISR
* @{
*****************************************************************************/
#define QD_RC_COMP_INT_STATUS ((u32)0x00000001 << 15) /*Bit[15], Qdecoder rotation counter compare INT status*/
#define QD_VUPLMT_INT_STATUS ((u32)0x00000001 << 13) /*Bit[13], Qdecoder Velocity up limit interrupt status */
#define QD_VLOWLMT_INT_STATUS ((u32)0x00000001 << 12) /*Bit[12], Qdecoder Velocity low limit interrupt status*/
#define QD_VCCAP_INT_STATUS ((u32)0x00000001 << 10) /*Bit[10], Qdecoder Velocity counter capture interrupt status*/
#define QD_PC_ERR_INT_STATUS ((u32)0x00000001 << 9) /*Bit[9], Qdecoder position counter error INT status*/
#define QD_IDX_PULSE_INT_STATUS ((u32)0x00000001 << 8) /*Bit[8], Qdecoder index pulse INT status*/
#define QD_RC_UF_INT_STATUS ((u32)0x00000001 << 7) /*Bit[7], Qdecoder rotation counter underflow INT status*/
#define QD_RC_OF_INT_STATUS ((u32)0x00000001 << 6) /*Bit[6], Qdecoder rotation counter overflow INT status*/
#define QD_PC_CMP_INT_STATUS ((u32)0x00000001 << 5) /*Bit[5], Qdecoder position counter compare INT status*/
#define QD_DR_CH_INT_STATUS ((u32)0x00000001 << 4) /*Bit[4], Qdecoder direction changed INT status*/
#define QD_PHASE_ILL_INT_STATUS ((u32)0x00000001 << 3) /*Bit[3], Qdecoder phase changed illegal INT status*/
#define QD_PC_UF_INT_STATUS ((u32)0x00000001 << 2) /*Bit[2], Qdecoder position counter underflow INT status*/
#define QD_PC_OF_INT_STATUS ((u32)0x00000001 << 1) /*Bit[1], Qdecoder position counter overflow INT status*/
#define QD_PC_CHG_INT_STATUS ((u32)0x00000001 << 0) /*Bit[0], Qdecoder position counter changed INT status*/
#define QD_ALL_INT_STATUS ((u32)0x0000B7FF)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#endif
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_qdec.h
|
C
|
apache-2.0
| 21,783
|
/*
* rtl8721d_ram_libc.h
*
* Definitions for RTL library functions
*/
#ifndef _RTL8721D_RAM_LIBC_H_
#define _RTL8721D_RAM_LIBC_H_
#include <basic_types.h>
#include <diag.h>
#include <va_list.h>
extern int _rtl_vsprintf(char *buf, size_t size, const char *fmt, const int *dp);
extern int _rtl_printf(IN const char* fmt, ...);
extern int _rtl_sprintf(char* str, const char* fmt, ...);
extern int _rtl_snprintf(char* str, size_t size, const char* fmt, ...);
extern int _rtl_vsnprintf(char *buf, size_t size, const char *fmt, va_list ap);
extern int _rtl_sscanf(const char *buf, const char *fmt, ...);
#endif /* _RTL8721D_RAM_LIBC_H_ */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_ram_libc.h
|
C
|
apache-2.0
| 642
|
/**
******************************************************************************
* @file rtl8721d_rtc.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_RTC_H_
#define _RTL8721D_RTC_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup RTC
* @brief RTC driver modules
* @{
*/
/** @addtogroup RTC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* The real-time clock (RTC) is an independent BCD timer/counter.
* One 32-bit register contains the seconds, minutes, hours (12 or 24-hour format) expressed in binary coded decimal format (BCD).
* and days expressed in binary format.
* Daylight saving time compensation can also be performed.
* One programmable alarm contains seconds, minutes, hours and days with interrupt function,
* and can be triggered by any combination of the time fields.
* A digital calibration feature is available to compensate for some deviation.
* After backup domain reset, all RTC registers are protected against possible parasitic
* write accesses.
* Support a programmable register for RTC trigger SDM32K periodical calibration with active and power save mode.
* As long as the supply voltage remains in the operating range, the RTC never stops,
* regardless of the device status (Run mode, low power mode or under reset).
*
*****************************************************************************************
* How to use RTC
*****************************************************************************************
* To use the RTC, the following steps are mandatory:
*
* 1. Initialize the RTC Clock Source.
* RCC_PeriphClockSource_RTC()
*
* 2. Fill the variable RTC_InitStruct with default parameters, or set the desired parameters manually:
* RTC_StructInit(&RTC_InitStruct)
*
* 3. configure the RTC peripheral with the corresponding configurations contained in RTC_InitStruct:
* Call RTC_Init(&RTC_InitStruct)
*
* 4. Fill the variable RTC_TimeStruct with default parameters() (Time = 00d:00h:00min:00sec)
* RTC_TimeStructInit(&RTC_TimeStruct)
* setting the desired calendar time parameters manually.
*
* 5. Set calendar time:
* RTC_SetTime(RTC_Format_BIN, &RTC_TimeStruct).
*
* 6. If RTC_OUT output is needed, the pinmux configuration is as follows:
* Pinmux_Config(PinName, PINMUX_FUNCTION_RTCOUT)
*
*
*****************************************************************************************
* How to use Alarm
*****************************************************************************************
* To use the Alarm, the following steps are mandatory:
*
* 1. Configure the RTC as described in the first part of this driver.
*
* 2. Fill the variable RTC_AlarmStruct of type RTC_AlarmTypeDef with default parameters
* RTC_AlarmStructInit(&RTC_AlarmStruct)
* or setting the desired Alarm time parameters manually.
*
* 3. configure Alarm:
* RTC_SetAlarm(RTC_Format_BIN, &RTC_AlarmStruct)
*
* 4. Enable alarm and alarm interrupt.
* RTC_AlarmCmd(ENABLE)
*
* 5. Enable IRQ as follows:
* InterruptRegister(RTC_IntHandler, RTC_IRQ, NULL, 4);
* InterruptEn(RTC_IRQ, 4);
*
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
/**
* @brief RTC Init structure definition
*/
typedef struct {
u32 RTC_HourFormat; /*!< Specifies the RTC Hour Format.
This parameter can be a value of @ref RTC_Hour_Formats */
u32 RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a value of @ref RTC_Asynchronous_Predivider */
u32 RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be a value of @ref RTC_Synchronous_Predivider */
u32 RTC_DayThreshold; /*!< Specifies the RTC Day Threshold value.
This parameter must be a value of @ref RTC_Day_Threshold */
} RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
u16 RTC_Days; /*!< Day in binary format 9bits 0~0x1FF */
u8 RTC_Hours; /*!< Specifies the RTC Time Hour.
This parameter must be set to a value in the 1-12 range
if the RTC_HourFormat_12 is selected or 0-23 range if
the RTC_HourFormat_24 is selected. */
u8 RTC_Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be set to a value in the 0-59 range. */
u8 RTC_Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be set to a value in the 0-59 range. */
u8 RTC_H12_PMAM; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
}RTC_TimeTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
u32 RTC_AlarmMask; /*!< Specifies the RTC Alarm1 Masks(H:M:S).
This parameter can be a value of @ref RTC_AlarmMask1_Definitions */
u32 RTC_Alarm2Mask; /*!< Specifies the RTC Alarm2 Masks Day).
This parameter can be a value of @ref RTC_AlarmMask2_Definitions */
}RTC_AlarmTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
/** @defgroup RTC_Input_parameter_format_definitions
* @{
*/
#define RTC_Format_BIN ((u32)0x000000000)
#define RTC_Format_BCD ((u32)0x000000001)
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
/**
* @}
*/
/** @defgroup RTC_Hour_Formats
* @{
*/
#define RTC_HourFormat_24 ((u32)0x00000000)
#define RTC_HourFormat_12 ((u32)0x00000080)
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
((FORMAT) == RTC_HourFormat_24))
/**
* @}
*/
/** @defgroup RTC_Asynchronous_Predivider
* @{
*/
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FF)
/**
* @}
*/
/** @defgroup RTC_Synchronous_Predivider
* @{
*/
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FF)
/**
* @}
*/
/** @defgroup RTC_Day_Threshold
* @{
*/
#define RTC_DAYTHRES_MSK ((u32)0xFF800000)
#define IS_RTC_DAY_THRES(DAYS) ((DAYS) <= 0x1FF)
/**
* @}
*/
/** @defgroup RTC_Time_Definitions
* @{
*/
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
/**
* @}
*/
/** @defgroup RTC_AM_PM_Definitions
* @{
*/
#define RTC_H12_AM ((u8)0x00) //AM or 24-hour format
#define RTC_H12_PM ((u8)0x01) //PM
#define IS_RTC_H12_AMPM(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
/**
* @}
*/
/** @defgroup RTC_AlarmMask1_Definitions
* @{
*/
#define RTC_AlarmMask_None ((u32)0x00000000)
#define RTC_AlarmMask_Hours ((u32)0x00800000)
#define RTC_AlarmMask_Minutes ((u32)0x00008000)
#define RTC_AlarmMask_Seconds ((u32)0x00000080)
#define RTC_AlarmMask_All ((u32)0x00808080)
#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F) == 0)
/**
* @}
*/
/** @defgroup RTC_AlarmMask2_Definitions
* @{
*/
#define RTC_Alarm2Mask_None ((u32)0x00000000)
#define RTC_Alarm2Mask_Days ((u32)0x00000200)
#define IS_ALARM2_MASK(MASK) (((MASK) & ~RTC_Alarm2Mask_Days) == 0)
/**
* @}
*/
/** @defgroup RTC_Alarms_Definitions
* @{
*/
#define RTC_Alarm ((u32)0x00000100)
#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm)
#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & RTC_Alarm) != (u32)0)
/**
* @}
*/
/** @defgroup RTC_Alarms_Interrupt_Definitions
* @{
*/
#define RTC_Alarm_IntEn ((u32)0x00001000)
/**
* @}
*/
/** @defgroup RTC_DayLightSaving_Definitions
* @{
*/
#define RTC_DayLightSaving_SUB1H ((u32)0x00000002)
#define RTC_DayLightSaving_ADD1H ((u32)0x00000001)
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
((SAVE) == RTC_DayLightSaving_ADD1H))
#define RTC_StoreOperation_Reset ((u32)0x00000000)
#define RTC_StoreOperation_Set ((u32)0x00000004)
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
((OPERATION) == RTC_StoreOperation_Set))
/**
* @}
*/
/** @defgroup RTC_Output_selection_Definitions
* @{
*/
#define RTC_Output_Disable ((u32)0x00000000)
#define RTC_Output_Alarm ((u32)0x00000020) ////wakeup
#define RTC_Output_clkspre ((u32)0x00000040) ////1Hz
#define RTC_Output_clkapre ((u32)0x00000060) ////256Hz
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
((OUTPUT) == RTC_Output_Alarm) || \
((OUTPUT) == RTC_Output_clkspre) || \
((OUTPUT) == RTC_Output_clkapre))
/**
* @}
*/
/** @defgroup RTC_Smooth_Calibration_Definitions
* @{
*/
#define RTC_CalibPeriod_1MIN ((u32)0x00000000)
#define RTC_CalibPeriod_2MIN ((u32)0x00010000)
#define RTC_CalibPeriod_3MIN ((u32)0x00020000)
#define RTC_CalibPeriod_4MIN ((u32)0x00030000)
#define RTC_CalibPeriod_5MIN ((u32)0x00040000)
#define RTC_CalibPeriod_6MIN ((u32)0x00050000)
#define RTC_CalibPeriod_7MIN ((u32)0x00060000)
#define RTC_CalibPeriod_8MIN ((u32)0x00070000)
#define IS_RTC_CALIB_PERIOD(DCP) (((DCP) == RTC_CalibPeriod_1MIN) || \
((DCP) == RTC_CalibPeriod_2MIN) || \
((DCP) == RTC_CalibPeriod_3MIN) || \
((DCP) == RTC_CalibPeriod_4MIN) || \
((DCP) == RTC_CalibPeriod_5MIN) || \
((DCP) == RTC_CalibPeriod_6MIN) || \
((DCP) == RTC_CalibPeriod_7MIN) || \
((DCP) == RTC_CalibPeriod_8MIN))
#define RTC_Calib_Disable ((u32)0x00000000)
#define RTC_Calib_Enable ((u32)0x00008000)
#define IS_RTC_CALIB_ENABLE(DCE) (((DCE) == RTC_Calib_Disable) || \
((DCE) == RTC_Calib_Enable))
#define RTC_CalibSign_Positive ((u32)0x00000000)
#define RTC_CalibSign_Negative ((u32)0x00004000)
#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
((SIGN) == RTC_CalibSign_Negative))
#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) <= 0x7F)
/**
* @}
*/
/** @defgroup RTC_32K_Auto_Calibration_Definitions
* @{
*/
#define RTC_32K_AUTOCAL_DISABLE ((u32)0x00000000)
#define RTC_32K_AUTOCAL_MINUTES ((u32)0x00000001)
#define RTC_32K_AUTOCAL_HOURS ((u32)0x00000002)
#define RTC_32K_AUTOCAL_DAYS ((u32)0x00000003)
#define IS_RTC_32K_AUTOCAL_SIGN(SIGN) (((SIGN) == RTC_32K_AUTOCAL_DISABLE) || \
((SIGN) == RTC_32K_AUTOCAL_MINUTES) || \
((SIGN) == RTC_32K_AUTOCAL_HOURS) || \
((SIGN) == RTC_32K_AUTOCAL_DAYS))
/**
* @}
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
_LONG_CALL_ u32 RTC_BypassShadowCmd(u32 NewState);
_LONG_CALL_ void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
_LONG_CALL_ u32 RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
_LONG_CALL_ void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
_LONG_CALL_ u32 RTC_SetTime(u32 RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
_LONG_CALL_ void RTC_GetTime(u32 RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
_LONG_CALL_ void RTC_DayIntClear(void);
_LONG_CALL_ u32 RTC_DayIntCmd(u32 NewState);
_LONG_CALL_ u32 RTC_DayThresSet(u32 DayThres);
_LONG_CALL_ u32 RTC_DayThresGet(void);
_LONG_CALL_ u32 RTC_SetAlarm(u32 RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct);
_LONG_CALL_ void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
_LONG_CALL_ void RTC_GetAlarm(u32 RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct);
_LONG_CALL_ void RTC_AlarmCmd(u32 NewState);
_LONG_CALL_ void RTC_AlarmClear(void);
_LONG_CALL_ u32 RTC_DayLightSavingConfig(u32 RTC_DayLightSaving, u32 RTC_StoreOperation);
_LONG_CALL_ u32 RTC_GetStoreOperation(void);
_LONG_CALL_ u32 RTC_OutputConfig(u32 RTC_Output);
_LONG_CALL_ u32 RTC_SmoothCalibConfig(u32 CalibSign, u32 Value, u32 CalibPeriod, u32 Calib_Enable);
_LONG_CALL_ u32 RTC_32KAutoCalibConfig(u32 Cal_Period, u32 Unit_Sel);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup RTC_Register_Definitions RTC Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup RTC_TR
* @{
*****************************************************************************/
#define RTC_TR_DAY ((u32)0xFF800000)
#define RTC_TR_PM ((u32)0x00400000)
#define RTC_TR_HT ((u32)0x00300000)
#define RTC_TR_HU ((u32)0x000F0000)
#define RTC_TR_MNT ((u32)0x00007000)
#define RTC_TR_MNU ((u32)0x00000F00)
#define RTC_TR_ST ((u32)0x00000070)
#define RTC_TR_SU ((u32)0x0000000F)
/** @} */
/**************************************************************************//**
* @defgroup RTC_CR
* @{
*****************************************************************************/
#define RTC_CR_DOVTHIE ((u32)0x00010000)
#define RTC_CR_ALRAIE ((u32)0x00001000)
#define RTC_CR_ALRAE ((u32)0x00000100)
#define RTC_CR_FMT ((u32)0x00000080)
#define RTC_CR_OSEL ((u32)0x00000060)
#define RTC_CR_BYPSHAD ((u32)0x00000008)
#define RTC_CR_BCK ((u32)0x00000004)
#define RTC_CR_SUB1H ((u32)0x00000002)
#define RTC_CR_ADD1H ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup RTC_ISR
* @{
*****************************************************************************/
#define RTC_ISR_RECALPF ((u32)0x00010000)
#define RTC_ISR_DOVTHF ((u32)0x00008000)
#define RTC_ISR_ALRAF ((u32)0x00000100)
#define RTC_ISR_INIT ((u32)0x00000080)
#define RTC_ISR_INITF ((u32)0x00000040)
#define RTC_ISR_RSF ((u32)0x00000020)
#define RTC_ISR_INITS ((u32)0x00000010)
#define RTC_ISR_ALMWF ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup RTC_PRER
* @{
*****************************************************************************/
#define RTC_PRER_PREDIV_A ((u32)0x01FF0000)
#define RTC_PRER_PREDIV_S ((u32)0x000001FF)
/** @} */
/**************************************************************************//**
* @defgroup RTC_CALIBR
* @{
*****************************************************************************/
#define RTC_CALIBR_CALP ((u32)0x00070000)
#define RTC_CALIBR_DCE ((u32)0x00008000)
#define RTC_CALIBR_DCS ((u32)0x00004000)
#define RTC_CALIBR_DC ((u32)0x0000007F)
/** @} */
/**************************************************************************//**
* @defgroup RTC_ALRMAR
* @{
*****************************************************************************/
#define RTC_ALRMAR_MSK2 ((u32)0x00800000)
#define RTC_ALRMAR_PM ((u32)0x00400000)
#define RTC_ALRMAR_HT ((u32)0x00300000)
#define RTC_ALRMAR_HU ((u32)0x000F0000)
#define RTC_ALRMAR_MSK1 ((u32)0x00008000)
#define RTC_ALRMAR_MNT ((u32)0x00007000)
#define RTC_ALRMAR_MNU ((u32)0x00000F00)
#define RTC_ALRMAR_MSK0 ((u32)0x00000080)
#define RTC_ALRMAR_ST ((u32)0x00000070)
#define RTC_ALRMAR_SU ((u32)0x0000000F)
/** @} */
/**************************************************************************//**
* @defgroup RTC_ALRMBR
* @{
*****************************************************************************/
#define RTC_ALRMBR_MSK3 ((u32)0x00000200)
#define RTC_ALRMBR_DT ((u32)0x000001FF)
/** @} */
/**************************************************************************//**
* @defgroup RTC_WPR
* @{
*****************************************************************************/
#define RTC_WPR_KEY ((u32)0x000000FF)
/** @} */
/**************************************************************************//**
* @defgroup RTC_CLKACALR
* @{
*****************************************************************************/
#define RTC_32K_AUTOCAL_SEL ((u32)0x00000003)
#define RTC_AUTOCAL_THRES_MSK ((u32)0x000000FC)
#define IS_RTC_32K_AUTOCALIB_THRES(THRES) (THRES <= 0x3F)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Masks Definition */
#define RTC_TR_RESERVED_MASK ((u32)0xFFFF7F7F)
#define INITMODE_TIMEOUT ((u32) 0x00010000)
#define SYNCHRO_TIMEOUT ((u32) 0x00020000)
#define RECALPF_TIMEOUT ((u32) 0x00020000)
#define ALARMDIS_TIMEOUT ((u32) 0x00020000)
#endif //_RTL8721D_RTC_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_rtc.h
|
C
|
apache-2.0
| 17,771
|
/**
******************************************************************************
* @file rtl8721d_sdio.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_SDIO_H_
#define _RTL8710B_SDIO_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup SDIO
* @brief SDIO driver modules
* @{
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup SDIO_Exported_Types SDIO Exported Types
* @{
*/
/**
* @brief SDIO Init structure definition
*/
typedef struct {
/* TXBD */
u32 TXBD_BAR; /*!< Specifies TXBD base address */
u32 TXBD_RING_SIZE; /*!< Specifies TXBD ring size, This parameter must be set to a value in the 0-0xFFFF range. */
u32 TX_BUFFER_SIZE; /*!< Specifies TX buffer size, This parameter must be set to a value in the 0-0xFF range. */
/* RXBD */
u32 RXBD_BAR; /*!< Specifies RXBD base address */
u32 RXBD_RING_SIZE; /*!< Specifies RXBD ring size, This parameter must be set to a value in the 0-0xFFFF range. */
u32 RXBD_FREE_TH; /*!< the threshold of free RX BD count to trigger interrupt */
} SDIO_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDIO_Exported_Constants SDIO Exported Constants
* @{
*/
/** @defgroup SDIO_MP_CMD_definitions The SDIO MP CMD definations
* @{
*/
#define SDIO_MP_START 1
#define SDIO_MP_STOP 2
#define SDIO_MP_LOOPBACK 3
#define SDIO_MP_STATUS 4
#define SDIO_MP_READ_REG8 5
#define SDIO_MP_READ_REG16 6
#define SDIO_MP_READ_REG32 7
#define SDIO_MP_WRITE_REG8 8
#define SDIO_MP_WRITE_REG16 9
#define SDIO_MP_WRITE_REG32 10
#define SDIO_MP_WAKEUP 11 // wakeup the SDIO task manually, for debugging
#define SDIO_MP_DUMP 12 // start/stop to dump the SDIO status periodically
#define SDIO_MP_CTX 13 // setup continue TX test
#define SDIO_MP_CRX 14 // setup continue RX test
#define SDIO_MP_CRX_DA 15 // setup continue RX with dynamic allocate RX Buf test
#define SDIO_MP_CRX_STOP 16 // setup continue RX test
#define SDIO_MP_DBG_MSG 17 // Debug message On/Off
/**
* @}
*/
/** @defgroup SDIO_RPWM_definitions The SDIO RPWM definations
* @{
*/
#define RPWM2_ACT_BIT (0x00000001 << 0) // Active
#define RPWM2_SLEEP_BIT 0 // Sleep
#define RPWM2_DSTANDBY_BIT (0x00000001 << 1) // Deep Standby
#define RPWM2_PG_BIT 0 // Power Gated
#define RPWM2_FBOOT_BIT (0x00000001 << 2) // fast reboot
#define RPWM2_NBOOT_BIT 0 // normal reboot
#define RPWM2_WKPIN_0_BIT (0x00000001 << 3) // enable GPIO wakeup pin 0
#define RPWM2_WKPIN_1_BIT (0x00000001 << 4) // enable GPIO wakeup pin 1
#define RPWM2_WKPIN_2_BIT (0x00000001 << 5) // enable GPIO wakeup pin 2
#define RPWM2_WKPIN_3_BIT (0x00000001 << 6) // enable GPIO wakeup pin 3
#define RPWM2_WKPIN_0_LV_BIT (0x00000001 << 7) // GPIO wakeup pin 0 wakeup level
#define RPWM2_WKPIN_1_LV_BIT (0x00000001 << 8) // GPIO wakeup pin 1 wakeup level
#define RPWM2_WKPIN_2_LV_BIT (0x00000001 << 9) // GPIO wakeup pin 2 wakeup level
#define RPWM2_WKPIN_3_LV_BIT (0x00000001 << 10) // GPIO wakeup pin 3 wakeup level
#define RPWM2_CG_BIT (0x00000001 << 11) // Clock Gated
#define RPWM2_ACK_BIT (0x00000001 << 14) // Acknowledge
#define RPWM2_TOGGLE_BIT (0x00000001 << 15) // Toggle bit
/**
* @}
*/
/** @defgroup SDIO_CPWM2_definitions The SDIO CPWM2 definations
* @{
*/
#define CPWM2_ACT_BIT (0x00000001 << 0) // Active
#define CPWM2_DSTANDBY_BIT (0x00000001 << 1) // Deep Standby
#define CPWM2_FBOOT_BIT (0x00000001 << 2) // fast reboot
#define CPWM2_INIC_FW_RDY_BIT (0x00000001 << 3) // is the iNIC FW(1) or Boot FW(0)
#define CPWM2_TOGGLE_BIT (0x00000001 << 15) // Toggle bit
/**
* @}
*/
/** @defgroup SDIO_CPWM1_definitions The SDIO CPWM1 definations
* @{
*/
#define CPWM1_TOGGLE_BIT (0x00000001 << 7) // Toggle bit
/**
* @}
*/
/** @defgroup SDIO_EVENT_definitions The SDIO EVENT definations
* @{
*/
#define SDIO_EVENT_RX_PKT_RDY (0x00000001 << 1) // A new SDIO packet ready
#define SDIO_EVENT_DUMP (0x00000001 << 3) // SDIO status dump periodically Enable
#define SDIO_EVENT_EXIT (0x00000001 << 27) // Request to exit the SDIO task
#define SDIO_EVENT_MP_STOPPED (0x00000001 << 28) // The SDIO task is stopped
#define SDIO_EVENT_IRQ_STOPPED (0x00000001 << 29) // The SDIO task is stopped
#define SDIO_EVENT_TX_STOPPED (0x00000001 << 30) // The SDIO task is stopped
#define SDIO_EVENT_RX_STOPPED (0x00000001 << 31) // The SDIO task is stopped
/**
* @}
*/
/**
* @}
*/
/** @defgroup SDIO_Exported_Functions SDIO Exported Functions
* @{
*/
_LONG_CALL_ void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
_LONG_CALL_ void SDIO_Init(SDIO_InitTypeDef* SDIOInit_Struct);
_LONG_CALL_ void SDIO_INTClear(void);
_LONG_CALL_ VOID SDIO_INTConfig(u16 IntMask, u32 NewState);
_LONG_CALL_ u8 SDIO_RPWM1_Get(void);
_LONG_CALL_ u16 SDIO_RPWM2_Get(void);
_LONG_CALL_ void SDIO_CPWM1_Set(u8 Val);
_LONG_CALL_ void SDIO_CPWM2_Set(u16 Val, u32 Newstate);
_LONG_CALL_ u16 SDIO_RXBD_RPTR_Get(void);
_LONG_CALL_ void SDIO_RXBD_WPTR_Set(u16 Val);
_LONG_CALL_ u16 SDIO_TXBD_WPTR_Get(void);
_LONG_CALL_ void SDIO_TXBD_RPTR_Set(u16 Val);
_LONG_CALL_ void SDIO_DMA_Reset(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#define HAL_SDIO_READ32(addr) HAL_READ32(SDIO_DEVICE_REG_BASE, addr)
#define HAL_SDIO_WRITE32(addr, value) HAL_WRITE32(SDIO_DEVICE_REG_BASE, addr, value)
#define HAL_SDIO_READ16(addr) HAL_READ16(SDIO_DEVICE_REG_BASE, addr)
#define HAL_SDIO_WRITE16(addr, value) HAL_WRITE16(SDIO_DEVICE_REG_BASE, addr, value)
#define HAL_SDIO_READ8(addr) HAL_READ8(SDIO_DEVICE_REG_BASE, addr)
#define HAL_SDIO_WRITE8(addr, value) HAL_WRITE8(SDIO_DEVICE_REG_BASE, addr, value)
/* Registers Definitions --------------------------------------------------------*/
#define REG_SPDIO_TXBD_ADDR 0xA0 // 4 Bytes
#define REG_SPDIO_TXBD_SIZE 0xA4 // 4 Bytes
#define REG_SPDIO_TXBD_WPTR 0xA8 // 2 Bytes
#define REG_SPDIO_TXBD_RPTR 0xAC // 2 Bytes
#define REG_SPDIO_RXBD_ADDR 0xB0 // 4 Bytes
#define REG_SPDIO_RXBD_SIZE 0xB4 // 2 Bytes
#define REG_SPDIO_RXBD_C2H_WPTR 0xB6 // 2 Bytes
#define REG_SPDIO_RXBD_C2H_RPTR 0xB8 // 2 Bytes
#define REG_SPDIO_HCI_RX_REQ 0xBA // 1 Byte
#define REG_SPDIO_CPU_RST_DMA 0xBB // 1 Byte
#define REG_SPDIO_RX_REQ_ADDR 0xBC // 2 Bytes
#define REG_SPDIO_CPU_INT_MASK 0xC0 // 2 Bytes
#define REG_SPDIO_CPU_INT_STAS 0xC2 // 2 Bytes
#define REG_SPDIO_CCPWM 0xC4 // 1 Byts
#define REG_SPDIO_CPU_IND 0xC5 // 1 Byte
#define REG_SPDIO_CCPWM2 0xC6 // 2 Bytes
#define REG_SPDIO_CPU_H2C_MSG 0xC8 // 4 Bytes
#define REG_SPDIO_CPU_C2H_MSG 0xCC // 4 Bytes
#define REG_SPDIO_CRPWM 0xD0 // 1 Bytes
#define REG_SPDIO_CRPWM2 0xD2 // 2 Bytes
#define REG_SPDIO_AHB_DMA_CTRL 0xD4 // 4 Bytes
#define REG_SPDIO_RXBD_CNT 0xD8 // 4 Bytes
#define REG_SPDIO_TX_BUF_UNIT_SZ 0xD9 // 1 Bytes
#define REG_SPDIO_RX_BD_FREE_CNT 0xDA // 2 Bytes
#define REG_SPDIO_CPU_H2C_MSG_EXT 0xDC // 4 Bytes
#define REG_SPDIO_CPU_C2H_MSG_EXT 0xE0 // 4 Bytes
/******************** Bits definition for REG_SPDIO_CPU_RST_DMA register *******************/
#define BIT_CPU_RST_SDIO_DMA BIT(7)
/******************** Bits definition for REG_SPDIO_CPU_INT_MASK/REG_SPDIO_CPU_INT_STAS register *******************/
#define BIT_TXFIFO_H2C_OVF BIT(0)
#define BIT_H2C_BUS_RES_FAIL BIT(1)
#define BIT_H2C_DMA_OK BIT(2)
#define BIT_C2H_DMA_OK BIT(3)
#define BIT_H2C_MSG_INT BIT(4)
#define BIT_RPWM1_INT BIT(5)
#define BIT_RPWM2_INT BIT(6)
#define BIT_SDIO_RST_CMD_INT BIT(7)
#define BIT_RXBD_FLAG_ERR_INT BIT(8)
#define BIT_RX_BD_AVAI_INT BIT(9)
#define BIT_HOST_WAKE_CPU_INT BIT(10)
#define SDIO_INIT_INT_MASK (BIT_H2C_DMA_OK | BIT_C2H_DMA_OK | \
BIT_H2C_MSG_INT | BIT_RPWM1_INT | \
BIT_RPWM2_INT |BIT_H2C_BUS_RES_FAIL | \
BIT_RXBD_FLAG_ERR_INT)
/******************** Bits definition for REG_SPDIO_CPU_IND register *******************/
#define BIT_SYSTEM_TRX_RDY_IND BIT(0)
/******************** Bits definition for REG_SPDIO_HCI_RX_REQ register *******************/
#define BIT_HCI_RX_REQ BIT(0)
#endif /* #ifndef _RTL8710B_SDIO_H_ */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_sdio.h
|
C
|
apache-2.0
| 9,085
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8721D_SDIO_HOST_H_
#define _RTL8721D_SDIO_HOST_H_
#define SDIO_HOST_REG_BASE 0x40026000
#define HAL_SDIO_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
#define HAL_SDIO_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
#define HAL_SDIO_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
#define HAL_SDIO_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
#define HAL_SDIO_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
#define HAL_SDIO_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
/* =============== Register Offset Definition =============== */
#define REG_SDIO_HOST_SDMA_SYS_ADDR 0x00 // 4byte
#define REG_SDIO_HOST_BLK_SIZE 0x04 // 2byte
#define REG_SDIO_HOST_BLK_CNT 0x06 // 2byte
#define REG_SDIO_HOST_ARG 0x08 // 4byte
#define REG_SDIO_HOST_XFER_MODE 0x0C // 2byte
#define REG_SDIO_HOST_CMD 0x0E // 2byte
#define REG_SDIO_HOST_RSP0 0x10 // 4byte
#define REG_SDIO_HOST_RSP2 0x14 // 4byte
#define REG_SDIO_HOST_RSP4 0x18 // 4byte
#define REG_SDIO_HOST_RSP6 0x1C // 4byte
#define REG_SDIO_HOST_BUF_DATA_PORT 0x20 // 4byte
#define REG_SDIO_HOST_PRESENT_STATE 0x24 // 4byte
#define REG_SDIO_HOST_HOST_CTRL 0x28 // 1byte
#define REG_SDIO_HOST_PWR_CTRL 0x29 // 1byte
#define REG_SDIO_HOST_BLK_GAP_CTRL 0x2A // 1byte
#define REG_SDIO_HOST_WAKEUP_CTRL 0x2B // 1byte
#define REG_SDIO_HOST_CLK_CTRL 0x2C // 2byte
#define REG_SDIO_HOST_TIMEOUT_CTRL 0x2E // 1byte
#define REG_SDIO_HOST_SW_RESET 0x2F // 1byte
#define REG_SDIO_HOST_NORMAL_INT_STATUS 0x30 // 2byte
#define REG_SDIO_HOST_ERROR_INT_STATUS 0x32 // 2byte
#define REG_SDIO_HOST_NORMAL_INT_STATUS_EN 0x34 // 2byte
#define REG_SDIO_HOST_ERROR_INT_STATUS_EN 0x36 // 2byte
#define REG_SDIO_HOST_NORMAL_INT_SIG_EN 0x38 // 2byte
#define REG_SDIO_HOST_ERROR_INT_SIG_EN 0x3A // 2byte
#define REG_SDIO_HOST_CAPABILITIES 0x40 // 8byte
#define REG_SDIO_HOST_ADMA_SYS_ADDR 0x58 // 8byte
/* =============================================== */
/* Block Count Register (0x06) */
#define BLK_CNT_REG_MAX 0xFFFF // 65535 blocks
/* Transfer Mode Register (0x0C) */
#define XFER_MODE_DMA_EN BIT0
#define XFER_MODE_BLK_CNT_EN BIT1
#define XFER_MODE_AUTO_CMD12_EN BIT2
#define XFER_MODE_DATA_XFER_DIR BIT4
#define XFER_MODE_MULT_SINGLE_BLK BIT5
/* Present State Register (0x24) */
#define PRES_STATE_CMD_INHIBIT_CMD BIT0
#define PRES_STATE_CMD_INHIBIT_DAT BIT1
#define PRES_STATE_DAT_LINE_ACTIVE BIT2
#define PRES_STATE_CARD_INSERTED BIT16
#define PRES_STATE_DAT0_SIGNAL_LEVEL BIT20
/* Power Control Register (0x29) */
#define PWR_CTRL_SD_BUS_PWR BIT0
/* Clock Control Register (0x2C) */
#define CLK_CTRL_INTERAL_CLK_EN BIT0
#define CLK_CTRL_INTERAL_CLK_STABLE BIT1
#define CLK_CTRL_SD_CLK_EN BIT2
/* Software Reset Register (0x2F) */
#define SW_RESET_FOR_ALL BIT0
#define SW_RESET_FOR_CMD BIT1
#define SW_RESET_FOR_DAT BIT2
/* Normal Interrupt Status (0x30) */
#define NOR_INT_STAT_CMD_COMP BIT0
#define NOR_INT_STAT_XFER_COMP BIT1
#define NOR_INT_STAT_BLK_GAP_EVENT BIT2
#define NOR_INT_STAT_DMA_INT BIT3
#define NOR_INT_STAT_BUF_WR_RDY BIT4
#define NOR_INT_STAT_BUF_RD_RDY BIT5
#define NOR_INT_STAT_CARD_INSERT BIT6
#define NOR_INT_STAT_CARD_REMOVAL BIT7
#define NOR_INT_STAT_CARD_INT BIT8
#define NOR_INT_STAT_ERR_INT BIT15
/* Error Interrupt Status (0x32) */
#define ERR_INT_STAT_CMD_TIMEOUT BIT0
#define ERR_INT_STAT_CMD_CRC BIT1
#define ERR_INT_STAT_CMD_END_BIT BIT2
#define ERR_INT_STAT_CMD_IDX BIT3
#define ERR_INT_STAT_DATA_TIMEOUT BIT4
#define ERR_INT_STAT_DATA_CRC BIT5
#define ERR_INT_STAT_DATA_END_BIT BIT6
#define ERR_INT_STAT_CUR_LIMIT BIT7
#define ERR_INT_STAT_AUTO_CMD12 BIT8
#define ERR_INT_STAT_ADMA BIT9
/* Normal Interrupt Status Enable (0x34) */
#define NOR_INT_STAT_EN_CMD_COMP BIT0
#define NOR_INT_STAT_EN_XFER_COMP BIT1
#define NOR_INT_STAT_EN_BLK_GAP_EVENT BIT2
#define NOR_INT_STAT_EN_DMA_INT BIT3
#define NOR_INT_STAT_EN_BUF_WR_RDY BIT4
#define NOR_INT_STAT_EN_BUF_RD_RDY BIT5
#define NOR_INT_STAT_EN_CARD_INSERT BIT6
#define NOR_INT_STAT_EN_CARD_REMOVAL BIT7
#define NOR_INT_STAT_EN_CARD_INT BIT8
/* Error Interrupt Status Enable (0x36) */
#define ERR_INT_STAT_EN_CMD_TIMEOUT BIT0
#define ERR_INT_STAT_EN_CMD_CRC BIT1
#define ERR_INT_STAT_EN_CMD_END_BIT BIT2
#define ERR_INT_STAT_EN_CMD_IDX BIT3
#define ERR_INT_STAT_EN_DATA_TIMEOUT BIT4
#define ERR_INT_STAT_EN_DATA_CRC BIT5
#define ERR_INT_STAT_EN_DATA_END_BIT BIT6
#define ERR_INT_STAT_EN_CUR_LIMIT BIT7
#define ERR_INT_STAT_EN_AUTO_CMD BIT8
#define ERR_INT_STAT_EN_ADMA BIT9
/* Normal Interrupt Signal Enable (0x38) */
#define NOR_INT_SIG_EN_CMD_COMP BIT0
#define NOR_INT_SIG_EN_XFER_COMP BIT1
#define NOR_INT_SIG_EN_BLK_GAP_EVENT BIT2
#define NOR_INT_SIG_EN_DMA_INT BIT3
#define NOR_INT_SIG_EN_BUF_WR_RDY BIT4
#define NOR_INT_SIG_EN_BUF_RD_RDY BIT5
#define NOR_INT_SIG_EN_CARD_INSERT BIT6
#define NOR_INT_SIG_EN_CARD_REMOVAL BIT7
#define NOR_INT_SIG_EN_CARD_INT BIT8
/* Error Interrupt Signal Enable (0x3A) */
#define ERR_INT_SIG_EN_CMD_TIMEOUT BIT0
#define ERR_INT_SIG_EN_CMD_CRC BIT1
#define ERR_INT_SIG_EN_CMD_END_BIT BIT2
#define ERR_INT_SIG_EN_CMD_IDX BIT3
#define ERR_INT_SIG_EN_DATA_TIMEOUT BIT4
#define ERR_INT_SIG_EN_DATA_CRC BIT5
#define ERR_INT_SIG_EN_DATA_END_BIT BIT6
#define ERR_INT_SIG_EN_CUR_LIMIT BIT7
#define ERR_INT_SIG_EN_AUTO_CMD BIT8
#define ERR_INT_SIG_EN_ADMA BIT9
/* Capabilities Register (0x40) */
#define CAPA_TIMEOUT_CLK_UNIT BIT7
#define CAPA_ADMA2_SUPPORT BIT19
#define CAPA_HIGH_SPEED_SUPPORT BIT21
#define CAPA_VOLT_SUPPORT_33V BIT24
#define CAPA_VOLT_SUPPORT_30V BIT25
#define CAPA_VOLT_SUPPORT_18V BIT26
#define DATA_BLK_LEN 512
#define SCR_REG_LEN 8 // 64 bits
#define SWITCH_FN_STATUS_LEN 64 // 512 bits
#define SD_STATUS_LEN 64 // 512 bits
#define CSD_REG_LEN 16 // 128 bits
/* Switch Function (CMD6) Group */
#define SWITCH_FN_GRP1_DEFAULT BIT0
#define SWITCH_FN_GRP1_HIGH_SPEED BIT1
#define SWITCH_FN_GRP2_DEFAULT BIT0
#define SWITCH_FN_GRP2_FOR_EC BIT1
#define SWITCH_FN_GRP2_VENDOR_SPECIFIC BIT14
/* Operating Condition (ACMD41) */
#define ACMD41_POLL_INTERVAL 10000 // 10 ms
#define ACMD41_INIT_TIMEOUT 1000000 // 1 sec
/* Card Status (R1) */
#define R1_APP_CMD BIT5
#define R1_WP_VIOLATION BIT26
/* Error Interrupt Recovery */
#define HAL_SDH_RECOVERED 0x10
/* 0x0C */
typedef enum
{
WRITE_OP = 0,
READ_OP = 1
}DATA_OPERATION;
/* 0x0E */
typedef enum
{
CMD_GO_IDLE_STATE = 0,
CMD_ALL_SEND_CID = 2,
CMD_SEND_RELATIVE_ADDR = 3,
CMD_SET_DSR = 4,
CMD_SWITCH_FUNC = 6,
CMD_SELECT_DESELECT_CARD = 7,
CMD_SEND_IF_COND = 8,
CMD_SEND_CSD = 9,
CMD_SEND_CID = 10,
CMD_VOLTAGE_SWITCH = 11,
CMD_STOP_TRANSMISSION = 12,
CMD_SEND_STATUS = 13,
CMD_GO_INACTIVE_STATE = 15,
CMD_SET_BLOCKLEN = 16,
CMD_READ_SINGLE_BLOCK = 17,
CMD_READ_MULTIPLE_BLOCK = 18,
CMD_SET_BLOCK_COUNT = 23,
CMD_WRITE_BLOCK = 24,
CMD_WRITE_MULTIPLE_BLOCK = 25,
CMD_PROGRAM_CSD = 27,
CMD_ERASE_WR_BLK_START = 32,
CMD_ERASE_WR_BLK_END = 33,
CMD_ERASE = 38,
CMD_SD_SEND_OP_COND = 41,
CMD_LOCK_UNLOCK = 42,
CMD_SEND_SCR = 51,
CMD_APP_CMD = 55
}CMD_IDX;
typedef enum
{
NORMAL, // 00b
SUSPEND, // 01b
RESUME, // 10b
ABORT // 11b
}CMD_TYPE;
typedef enum
{
NO_DATA, // 00b
WITH_DATA // 01b
}DATA_PRESENT_SEL;
typedef enum
{
NO_RSP, // 00b
RSP_LEN_136, // 01b
RSP_LEN_48, // 10b
RSP_LEN_48_CHK_BUSY // 11b
}RSP_TYPE;
/* 0x28 */
typedef enum
{
SDMA, // 00b
RESERVED, // 01b
ADMA2_32BIT, // 10b
ADMA2_64BIT // 11b
}HOST_DMA_SELECT;
typedef enum
{
MODE_1_BIT = 0,
MODE_4_BIT = 1
}HOST_DATA_WIDTH;
/* 0x29 */
typedef enum
{
VOLT_33V = 7,// 111b
VOLT_30V = 6,// 110b
VOLT_18V = 5 // 101b
}HOST_SD_BUS_VOLT;
/* 0x2C */
typedef enum
{
BASE_CLK = 0x00,
BASE_CLK_DIVIDED_BY_2 = 0x01,
BASE_CLK_DIVIDED_BY_4 = 0x02,
BASE_CLK_DIVIDED_BY_8 = 0x04,
BASE_CLK_DIVIDED_BY_16 = 0x08,
BASE_CLK_DIVIDED_BY_32 = 0x10,
BASE_CLK_DIVIDED_BY_64 = 0x20,
BASE_CLK_DIVIDED_BY_128 = 0x40,
BASE_CLK_DIVIDED_BY_256 = 0x80
}SD_CLK_DIVISOR;
typedef enum
{
SD_CLK_162KHZ,
SD_CLK_325KHZ,
SD_CLK_650KHZ,
SD_CLK_1_3MHZ,
SD_CLK_2_6MHZ,
SD_CLK_5_2MHZ,
SD_CLK_10_4MHZ,
SD_CLK_20_8MHZ,
SD_CLK_41_6MHZ
}SD_CLK_FREQUENCY;
/* Card Status Register */
typedef enum
{
IDLE, // 0
READY, // 1
IDENTIFICATION, // 2
STAND_BY, // 3
TRANSFER, // 4
SENDING_DATA, // 5
RECEIVE_DATA, // 6
PROGRAMMING, // 7
DISCONNECT, // 8
UNKNOWN = 0xFF
}CURRENT_STATE;
/* OCR Register */
typedef enum
{
VDD_27_28 = BIT15,
VDD_28_29 = BIT16,
VDD_29_30 = BIT17,
VDD_30_31 = BIT18,
VDD_31_32 = BIT19,
VDD_32_33 = BIT20,
VDD_33_34 = BIT21,
VDD_34_35 = BIT22,
VDD_35_36 = BIT23,
CARD_CAPA_STATUS = BIT30,
CARD_PWR_UP_STATUS = BIT31
}OCR_VOLTAGE_PROFILE;
/* SCR Register */
typedef enum
{
SD_VER_10 = 0,
SD_VER_110 = 1,
SD_VER_200 = 2
}PHYSICAL_LAYER_SPEC_VER;
/* CSD Register */
typedef enum
{
CLEAR_WRITE_PROTECT = 0,
SET_WRITE_PROTECT = 1
}TEMPORARY_WRITE_PROTECT_STATUS;
/* Switch Function (CMD6) Status Data Structure Version */
typedef enum
{
BUSY_STATUS_UNDEFINED = 0, // bits [511:376] are defined
BUSY_STATUS_DEFINED = 1 // bits [511:272] are defined
}SWITCH_FN_STATUS_DATA_STRUCTURE_VER;
/* Switch Function (CMD6) Busy Status */
typedef enum
{
READY_STATUS = 0,
BUSY_STATUS = 1
}SWITCH_FN_BUSY_STATUS;
/* Switch Function (CMD6) Mode */
typedef enum
{
CHECK_FN = 0x0,
SWITCH_FN = 0x1
}SWITCH_FN_MODE;
/* Switch Function (CMD6) Group 1 */
typedef enum
{
FN1_DEFAULT = 0x0,
FN1_HIGH_SPEED = 0x1,
FN1_KEEP_CURRENT = 0xF
}SWITCH_FN_GROUP_1;
/* Switch Function (CMD6) Group 2 */
typedef enum
{
FN2_DEFAULT = 0x0,
FN2_FOR_EC = 0x1,
FN2_VENDOR_SPECIFIC = 0xE,
FN2_KEEP_CURRENT = 0xF
}SWITCH_FN_GROUP_2;
typedef enum
{
DESEL_CARD = 0,
SEL_CARD = 1
}CARD_SELECTION;
typedef enum
{
SDSC_ONLY = 0,
SDHC_SUPPORT = 1
}HOST_CAPACITY_SUPPORT;
typedef enum
{
BUS_1_BIT = 0,
BUS_4_BIT = 2
}DATA_BUS_WIDTH;
typedef struct _ADMA2_ATTRIB_
{
u16 Valid:1;
u16 End:1;
u16 Int:1;
u16 Rsvd1:1;
u16 Act1:1;
u16 Act2:1;
u16 Rsvd2:10;
}ADMA2_ATTRIB, *PADMA2_ATTRIB;
typedef struct _ADMA2_DESC_FMT_
{
ADMA2_ATTRIB Attrib1;
u16 Len1;
u32 Addr1;
/* Link to next descriptor (if needed) */
ADMA2_ATTRIB Attrib2;
u16 Len2;
u32 Addr2;
}ADMA2_DESC_FMT, *PADMA2_DESC_FMT;
/* 0x0E */
typedef struct _SDIO_HOST_CMD_FMT_
{
u16 RespType:2;
u16 Rsvd0:1;
u16 CmdCrcChkEn:1;
u16 CmdIdxChkEn:1;
u16 DataPresent:1;
u16 CmdType:2;
u16 CmdIdx:6;
u16 Rsvd1:2;
}SDIO_HOST_CMD_FMT, *PSDIO_HOST_CMD_FMT;
typedef struct _SDIO_HOST_CMD_
{
SDIO_HOST_CMD_FMT CmdFmt;
u32 Arg;
}SDIO_HOST_CMD, *PSDIO_HOST_CMD;
HAL_Status
HalSdioHostInitHostRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostInitCardRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostDeInitRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostEnableRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostDisableRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostIrqInitRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostReadBlocksDmaRtl8721d(
IN VOID *Data,
IN u64 ReadAddr,
IN u32 BlockCnt
);
HAL_Status
HalSdioHostWriteBlocksDmaRtl8721d(
IN VOID *Data,
IN u64 WriteAddr,
IN u32 BlockCnt
);
HAL_Status
HalSdioHostStopTransferRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostGetCardStatusRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostGetSdStatusRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostChangeSdClockRtl8721d(
IN VOID *Data,
IN u8 Frequency
);
HAL_Status
HalSdioHostEraseRtl8721d(
IN VOID *Data,
IN u64 StartAddr,
IN u64 EndAddr
);
HAL_Status
HalSdioHostGetWriteProtectRtl8721d(
IN VOID *Data
);
HAL_Status
HalSdioHostSetWriteProtectRtl8721d(
IN VOID *Data,
IN u8 Setting
);
#ifdef CONFIG_SDIO_HOST_VERIFY
#define HAL_MMC_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
#define HAL_MMC_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
#define HAL_MMC_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
/* RTL8721D Register */
// REG_SOC_HCI_COM_FUNC_EN (0x214)
#define SD_DEVICE_IP_ON_BLK BIT0
#define SD_DEVICE_IP_OFF_BLK BIT1
#define SD_HOST_IP_BLK BIT2
// REG_PESOC_HCI_CLK_CTRL0 (0x240)
#define SD_HOST_CLKEN_IN_CPU_RUN_MODE BIT2
// REG_HCI_PINMUX_CTRL (0x2A0)
#define SD_DEVICE_MODE_PINMUX_EN BIT0
#define SD_HOST_MODE_PINMUX_EN BIT1
// 0x40059000
#define SD_HOST_CARD_DETECT_CIRCUIT BIT10
/* SD Host Register */
#define REG_SDMA_SYS_ADDR_ARG 0x00 // 4byte
#define REG_BLOCK_SIZE 0x04 // 2byte
#define REG_BLOCK_COUNT 0x06 // 2byte
#define REG_ARGUMENT1 0x08 // 4byte
#define REG_TRANSFER_MODE 0x0C // 2byte
#define REG_COMMAND 0x0E // 2byte
#define REG_RESPONSE0 0x10 // 4byte
#define REG_RESPONSE2 0x14 // 4byte
#define REG_RESPONSE4 0x18 // 4byte
#define REG_RESPONSE6 0x1C // 4byte
#define REG_BUFFER_DATA_PORT 0x20 // 4byte
#define REG_PRESENT_STATE 0x24 // 4byte
#define REG_HOST_CONTROL1 0x28 // 1byte
#define REG_POWER_CONTROL 0x29 // 1byte
#define REG_BLOCK_GAP_CONTROL 0x2A // 1byte
#define REG_WAKEUP_CONTROL 0x2B // 1byte
#define REG_CLOCK_CONTROL 0x2C // 2byte
#define REG_TIMEOUT_CONTROL 0x2E // 1byte
#define REG_SW_RESET 0x2F // 1byte
#define REG_NORMAL_INT_STATUS 0x30 // 2byte
#define REG_ERROR_INT_STATUS 0x32 // 2byte
#define REG_NORMAL_INT_STATUS_ENABLE 0x34 // 2byte
#define REG_ERROR_INT_STATUS_ENABLE 0x36 // 2byte
#define REG_NORMAL_INT_SIGNAL_ENABLE 0x38 // 2byte
#define REG_ERROR_INT_SIGNAL_ENABLE 0x3A // 2byte
#define REG_CAPABILITIES 0x40 // 8byte
#define REG_ADMA_ADDRESS 0x58 // 8byte
// Transfer Mode (0x0C)
#define BIT_DMA_EN BIT0
#define BIT_BLK_CNT_EN BIT1
#define BIT_AUTO_CMD12_EN BIT2
#define BIT_AUTO_CMD23_EN BIT3
#define BIT_READ_TRANS BIT4
#define BIT_MULTI_BLK BIT5
// Present State (0x24)
#define BIT_CMD_INHIBIT_CMD BIT0
#define BIT_CMD_INHIBIT_DAT BIT1
#define BIT_CARD_INSERTED BIT16
#define BIT_WRITE_PROTECT_SWITCH_PIN BIT19
// Power Control (0x29)
#define BIT_POWER_33 0xE
#define BIT_POWER_30 0xC
#define BIT_POWER_18 0xA
// Clock Control (0x2C)
#define BIT_INTERNAL_CLK_EN BIT0
#define BIT_INTERNAL_CLK_STABLE BIT1
#define BIT_SD_CLK_EN BIT2
// Software Reset (0x2F)
#define BIT_SW_RESET_ALL BIT0
#define BIT_SW_RESET_CMD_LINE BIT1
#define BIT_SW_RESET_DAT_LINE BIT2
// Norma Interrupt Status (0x30)
#define BIT_COMMAND_COMPLETE BIT0
#define BIT_TRANSFER_COMPLETE BIT1
#define BIT_BLOCK_GAP_EVENT BIT2
#define BIT_DMA_INT BIT3
#define BIT_BUFFER_WRITE_RDY BIT4
#define BIT_BUFFER_READ_RDY BIT5
#define BIT_CARD_INSERTION BIT6
#define BIT_CARD_REMOVAL BIT7
#define BIT_CARD_INT BIT8
#define BIT_ERROR_INT BIT15
// Error Interrupt Status (0x32)
#define BIT_DATA_TIME_OUT_ERROR BIT4
#define BIT_DATA_CRC_ERROR BIT5
#define BIT_ADMA_ERROR BIT9
// Capabilities (0x40)
#define BIT_VDD_33 BIT24
#define BIT_VDD_30 BIT25
#define BIT_VDD_18 BIT26
#define ENABLE 1
#define DISABLE 0
#define ADMA_DESC_NUM 50
#define BUFFER_UNIT_SIZE 512
typedef enum _MMC_HOST_TEST_FUNC_ {
MMC_HOST_TEST_HW_INIT, // 0
MMC_HOST_TEST_CARD_INIT, // 1
MMC_HOST_TEST_SEND_CMD, // 2
MMC_HOST_TEST_DEBUG, // 3
MMC_HOST_TEST_SW_RESET, // 4
MMC_HOST_TEST_READ_SINGLE, // 5
MMC_HOST_TEST_WRITE_SINGLE, // 6
MMC_HOST_TEST_READ_MULTI, // 7
MMC_HOST_TEST_WRITE_MULTI, // 8
MMC_HOST_TEST_SINGLE_LONGRUN, // 9
MMC_HOST_TEST_MULTI_LONGRUN, // 10
MMC_HOST_TEST_CARD_DETECTION, // 11
MMC_HOST_TEST_WRITE_PROTECT, // 12
MMC_HOST_TEST_REGISTER_RW, // 13
SD_HOST_HAL_API_VERIFY = 20,
SD_HOST_ERASE_TEST = 21,
SD_HOST_WP_TEST = 22,
SD_HOST_MB_TEST = 23,
SD_HOST_ADMA_MAX_TEST = 24
}MMC_HOST_TEST_FUNC;
typedef enum _RESPONSE_TYPE_ {
No_Response, // 00b
Response_136, // 01b
Response_48, // 10b
Response_48_Busy // 11b
}RESPONSE_TYPE;
typedef enum _COMMAND_TYPE_ {
Normal, // 00b
Suspend, // 01b
Resume, // 10b
Abort // 11b
}COMMAND_TYPE;
typedef enum _DATA_PRESENT_ {
No_Data_Present, // 00b
Data_Present, // 01b
}DATA_PRESENT;
typedef enum _SUPPLY_VOLTAGE_ {
MMC_VDD_27_28 = BIT15,
MMC_VDD_28_29 = BIT16,
MMC_VDD_29_30 = BIT17,
MMC_VDD_30_31 = BIT18,
MMC_VDD_31_32 = BIT19,
MMC_VDD_32_33 = BIT20,
MMC_VDD_33_34 = BIT21,
MMC_VDD_34_35 = BIT22,
MMC_VDD_35_36 = BIT23,
}SUPPLY_VOLTAGE;
typedef enum _COMMAND_INDEX_ {
GO_IDLE_STATE = 0,
ALL_SEND_CID = 2,
SEND_RELATIVE_ADDR = 3,
SET_BUS_WIDTH = 6,
SELECT_CARD = 7,
SEND_IF_COND = 8,
SEND_CSD = 9,
STOP_TRANSMISSION = 12,
SEND_STATUS = 13,
READ_SINGLE_BLOCK = 17,
READ_MULTIPLE_BLOCK = 18,
WRITE_BLOCK = 24,
WRITE_MULTIPLE_BLOCK = 25,
SD_SEND_OP_COND = 41,
APP_CMD = 55,
}COMMAND_INDEX;
typedef enum _TRANSFER_CONFIG_ {
Read_Data = 0,
Write_Data = 1,
Single_Block = 0,
Multiple_Block = 1,
}TRANSFER_CONFIG;
typedef enum _ERROR_STATUS_ {
General_Error, // 0
CRC_Error, // 1
TIME_OUT_ERROR, // 2
CRC_Error_NeedCMD12, // 3
Transfer_OK // 4
}ERROR_STATUS;
typedef enum _CARD_CURRENT_STATE_ {
IDLE_STATE,
READY_STATE,
IDENT_STATE,
STBY_STATE,
TRAN_STATE,
DATA_STATE,
RCV_STATE,
PRG_STATE,
DIS_STATE,
UNKNOWN_STATE
}CARD_CURRENT_STATE;
typedef struct _COMMAND_FORMAT_
{
u16 Resp_Type:2;
u16 Rsvd0:1;
u16 CMD_CRC_Chk:1;
u16 CMD_Idx_Chk:1;
u16 Data_Present:1;
u16 CMD_Type:2;
u16 CMD_Idx:6;
u16 Rsvd1:2;
}COMMAND_FORMAT, *PCOMMAND_FPRMAT;
typedef struct _MMC_COMMAND
{
COMMAND_FORMAT Cmd_Format;
u32 Arg;
}MMC_COMMAND;
typedef struct _MMC_HOST_
{
u32 OCR_Avail;
u32 Resp[4];
u32 CID[4];
u32 RCA;
}MMC_HOST, *PMMC_HOST;
typedef struct _ADMA_ATTR_
{
u16 Valid:1;
u16 End:1;
u16 Int:1;
u16 Rsvd1:1;
u16 Act1:1;
u16 Act2:1;
u16 Rsvd2:10;
}ADMA_ATTR, *PADMA_ATTR;
// 24 bytes
typedef struct _ADMA_DESC_TABLE_
{
// 1st buffer desc
ADMA_ATTR Attribute1;
u16 Length1;
u32 Address1;
// 2nd buffer desc
ADMA_ATTR Attribute2;
u16 Length2;
u32 Address2;
// 3rd buffer desc
ADMA_ATTR Attribute3;
u16 Length3;
u32 Address3;
}ADMA_DESC_TABLE, *PADMA_DESC_TABLE;
// 1024 bytes
typedef struct _ADMA_BUFFER_
{
u8 Data1[512]; /* 1st buffer */
u8 Data2[512]; /* 2nd buffer */
}ADMA_BUFFER, *PADMA_BUFFER;
VOID
SdHostTestApp(
IN u8 *argv[]
);
#endif // end of "#ifdef CONFIG_SDIO_HOST_VERIFY"
#endif /* #ifndef _RTL8721D_SDIO_HOST_H_ */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_sdio_host.h
|
C
|
apache-2.0
| 19,445
|
/**
******************************************************************************
* @file rtl8721d_sdioh.h
* @author
* @version V1.0.0
* @date 2018-06-29
* @brief This file contains all the functions prototypes for the SDIOH firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_SDIO_HOST_H
#define _RTL8721D_SDIO_HOST_H
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup SDIOH
* @brief SDIOH driver modules
* @{
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Types SDIOH Exported Types
* @{
*/
/**
* @brief SDIOH init structure definition
*/
typedef struct {
u8 SDIOH_idle_level; /*!> Indicate the idle pin level mask. When operate in 1-Bit bus width, this value is 0x03.
When operate in 4-Bit bus width, this value is 0x1F. */
} SDIOH_InitTypeDef;
/**
* @brief SDIOH DMA control structure definition
*/
typedef struct {
u32 start_addr; /*!< Specify the DMA start address. Unit: 8 Bytes. */
u16 blk_cnt; /*!< Specify the DMA transfer length. Unit: 512 Bytes). */
u8 op; /*!< Specify the data move direction. Should be a value of @ref SDIOH_DMA_Operation. */
u8 type; /*!< Specify the transfer type. Shold be a value of @ref SDIOH_DMA_Transfer_Type. */
} SDIOH_DmaCtl;
/**
* @brief SDIOH command parameters structure definition
*/
typedef struct{
u32 arg; /*!< Specify the argument to be transfered with command. */
u8 idx; /*!< Specify the command to be transfered. */
u8 rsp_type; /*!< Specify the response type. Should be a value of @ref SDIOH_Card_Response_Classfication. */
u8 rsp_crc_chk; /*!< Specify CRC7 check enable or not. Should be ENABLE or DISABLE. */
u8 data_present; /*!< Specify which thers is data need to read after get response from card. Should be a value of
@ref SDIOH_Data_Present */
} SDIOH_CmdTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Constants SDIOH Exported Constants
* @{
*/
/** @defgroup SDIOH_Working_Mode
* @{
*/
#define SDIOH_NORMAL_WRITE 0
#define SDIOH_AUTO_WRITE3 1
#define SDIOH_AUTO_WRITE4 2
#define SDIOH_AUTO_READ3 5
#define SDIOH_AUTO_READ4 6
#define SDIOH_SEND_CMD_GET_RSP 8
#define SDIOH_AUTO_WRITE1 9
#define SDIOH_AUTO_WRITE2 10
#define SDIOH_NORMAL_READ 12
#define SDIOH_AUTO_READ1 13
#define SDIOH_AUTO_READ2 14
#define SDIOH_TUNING 15
/**
* @}
*/
/** @defgroup SDIOH_Card_Response_Type
* @{
*/
#define SDIOH_NO_RESP 0
#define SDIOH_RESP_R1 1
#define SDIOH_RESP_R2 2
#define SDIOH_RESP_R3 3
#define SDIOH_RESP_R6 4
#define SDIOH_RESP_R7 5
/**
* @}
*/
/** @defgroup SDIOH_Card_Response_Classification
* @{
*/
#define SDIOH_NO_RESP 0
#define SDIOH_RSP_6B 1
#define SDIOH_RSP_17B 2
/**
* @}
*/
/** @defgroup SDIOH_Data_Present
* @{
*/
#define SDIOH_NO_DATA 0
#define SDIOH_DATA_EXIST 1
/**
* @}
*/
/** @defgroup SDIOH_DMA_Transfer_Type
* @{
*/
#define SDIOH_DMA_NORMAL 0
#define SDIOH_DMA_64B 1
#define SDIOH_DMA_R2 2
/**
* @}
*/
/** @defgroup SDIOH_Mode_Definition
* @{
*/
#define SDIOH_SD20_MODE 0
#define SDIOH_DDR_MODE 1
#define SDIOH_SD30_MODE 2
/**
* @}
*/
/** @defgroup SDIOH_Bus_Width
* @{
*/
#define SDIOH_BUS_WIDTH_1BIT 0
#define SDIOH_BUS_WIDTH_4BIT 1
/**
* @}
*/
/** @defgroup SDIOH_DMA_Operation
* @{
*/
#define SDIOH_DMA_WRITE 0
#define SDIOH_DMA_READ 1
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Functions SDIOH Exported Functions
* @{
*/
/** @defgroup SDIO_HOST_Functions SDIO Host Functions
* @{
*/
_LONG_CALL_ u32 SDIOH_Busy(void);
_LONG_CALL_ u32 SDIOH_CheckTxError(u16 *status);
_LONG_CALL_ u32 SDIOH_WaitTxDone(u32 timeout_us);
_LONG_CALL_ u32 SDIOH_WaitDMADone(u32 timeout_us);
_LONG_CALL_ u32 SDIOH_GetISR(void);
_LONG_CALL_ void SDIOH_INTConfig(u8 SDIO_IT, u32 newState);
_LONG_CALL_ void SDIOH_INTClearPendingBit(u8 SDIO_IT);
_LONG_CALL_ u32 SDIOH_CheckBusState(u8 status, u32 timeout_us);
_LONG_CALL_ u8 SDIOH_GetBusWidth(void);
_LONG_CALL_ void SDIOH_SetBusWidth(u8 width);
_LONG_CALL_ void SDIOH_DMAConfig(SDIOH_DmaCtl *dma_ctl);
_LONG_CALL_ void SDIOH_DMAReset(void);
_LONG_CALL_ u32 SDIOH_SendCommand(SDIOH_CmdTypeDef *cmd_attrib, u32 timeout_us);
_LONG_CALL_ u8 SDIOH_GetResponse(u8 byte_index);
_LONG_CALL_ void SDIOH_SwitchSpeed(u8 clk_div, u8 mode);
_LONG_CALL_ u32 SDIOH_InitialModeCmd(u8 NewState, u8 Level);
_LONG_CALL_ u32 SDIOH_Init (u8 BusBitMode);
_LONG_CALL_ void SDIOH_DeInit (void);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup SDIOH_Register_Definitions SDIOH Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup SDIOH_SRAM_CRL
* @{
*****************************************************************************/
#define SDIOH_SHIFT_LX_BURST_SIZE 6
#define SDIOH_LX_BURST_SIZE_64B (0 << SDIOH_SHIFT_LX_BURST_SIZE)
#define SDIOH_SHIFT_MAP_SEL 5
#define SDIOH_MAP_SEL_DEC (1 << SDIOH_SHIFT_MAP_SEL)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_DMA_CRL1
* @{
*****************************************************************************/
#define SDIOH_MASK_DRAM_SA 0x0FFFFFFF
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_DMA_CRL2
* @{
*****************************************************************************/
#define SDIOH_MASK_DMA_LEN 0x0000FFFF
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_DMA_CRL3
* @{
*****************************************************************************/
#define SDIOH_DAT64_SEL BIT(5)
#define SDIOH_RSP17_SEL BIT(4)
#define SDIOH_SHIFT_DDR_WR 1
#define SDIOH_DMA_XFER BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_ISR
* @{
*****************************************************************************/
#define SDIOH_DMA_TRANSFER_DONE BIT(4)
#define SDIOH_CARD_ERROR BIT(2)
#define SDIOH_CARD_END BIT(1)
#define SDIOH_SD_ISR_ALL (0x16)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_ISREN
* @{
*****************************************************************************/
#define SDIOH_DMA_CTL_INT_EN BIT(4)
#define SDIOH_CARD_ERR_INT_EN BIT(2)
#define SDIOH_CARD_END_INT_EN BIT(1)
#define SDIOH_WRITE_DATA BIT(0)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CKGEN_CTL
* @{
*****************************************************************************/
#define SDIOH_SHIFT_SD30_SAMP_CLK_SRC 12
#define SDIOH_SHIFT_SD30_PUSH_CLK_SRC 8
#define SDIOH_SHIFT_CRC_CLK_SRC 4
#define SDIOH_SD30_SAMP_CLK_VP1 (2 << SDIOH_SHIFT_SD30_SAMP_CLK_SRC)
#define SDIOH_SD30_PUSH_CLK_VP0 (1 << SDIOH_SHIFT_SD30_PUSH_CLK_SRC)
#define SDIOH_CRC_CLK_SSC (0 << SDIOH_SHIFT_CRC_CLK_SRC)
#define SDIOH_MASK_CLKDIV (0x7)
#define SDIOH_CLK_DIV1 0
#define SDIOH_CLK_DIV2 1
#define SDIOH_CLK_DIV4 2
#define SDIOH_CLK_DIV8 3
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_STOP
* @{
*****************************************************************************/
#define SDIOH_TARGET_MODULE_SD BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_SELECT
* @{
*****************************************************************************/
#define SDIOH_CARD_SEL_SD_MODULE 0x2
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_EXIST
* @{
*****************************************************************************/
#define SDIOH_SD_WP BIT(5)
#define SDIOH_SD_EXIST BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_INT_EN
* @{
*****************************************************************************/
#define SDIOH_SDMMC_INT_EN BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_INT_PEND
* @{
*****************************************************************************/
#define SDIOH_SDMMC_INT_PEND BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_CARD_CLK_EN_CTL
* @{
*****************************************************************************/
#define SDIOH_SD_CARD_MOUDLE_EN BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_CONFIG1
* @{
*****************************************************************************/
#define SDIOH_INITIAL_MODE BIT(7)
#define SDIOH_CLK_DIV_BY_128 0
#define SDIOH_CLK_DIV_BY_256 BIT(6)
#define SDIOH_SD30_ASYNC_FIFO_RST_N BIT(4)
#define SDIOH_SHIFT_MODE_SEL 2
#define SDIOH_MASK_MODE_SEL 0xc
#define SDIOH_SHIFT_BUS_WIDTH 0
#define SDIOH_MASK_BUS_WIDTH 0x3
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_CONFIG2
* @{
*****************************************************************************/
#define SDIOH_CRC7_CAL_EN 0
#define SDIOH_CRC7_CAL_DIS BIT(7)
#define SDIOH_CRC16_CHK_EN 0
#define SDIOH_CRC16_CHK_DIS BIT(6)
#define SDIOH_WAIT_WR_CRCSTA_TO_EN 0
#define SDIOH_WAIT_WR_CRCSTA_TO_DIS BIT(5)
#define SDIOH_IGNORE_WR_CRC_ERR_EN 0
#define SDIOH_IGNORE_WR_CRC_ERR_DIS BIT(4)
#define SDIOH_WAIT_BUSY_END_DIS 0
#define SDIOH_WAIT_BUSY_END_EN BIT(3)
#define SDIOH_CRC7_CHK_EN 0
#define SDIOH_CRC7_CHK_DIS BIT(2)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_CONFIG3
* @{
*****************************************************************************/
#define SDIOH_STOP_STA_WAIT_BUSY_EN 0
#define SDIOH_STOP_STA_WAIT_BUSY_DIS BIT(7)
#define SDIOH_CMD_STA_WAIT_BUSY_EN 0
#define SDIOH_CMD_STA_WAIT_BUSY_DIS BIT(6)
#define SDIOH_DATA_PHA_WAIT_BUSY_EN BIT(5)
#define SDIOH_DATA_PHA_WAIT_BUSY_DIS 0
#define SDIOH_SD30_CLK_STOP_EN BIT(4)
#define SDIOH_SD30_CLK_STOP_DIS 0
#define SDIOH_SD20_CLK_STOP_EN BIT(3)
#define SDIOH_SD20_CLK_STOP_DIS 0
#define SDIOH_SD_CMD_RESP_CHK_EN BIT(2)
#define SDIOH_SD_CMD_RESP_CHK_DIS 0
#define SDIOH_ADDR_MODE_SECTOR 0
#define SDIOH_ADDR_MODE_BYTE BIT(1)
#define SDIOH_CMD_RESP_TO_EN BIT(0)
#define SDIOH_CMD_RESP_TO_DIS 0
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_STATUS1_2
* @{
*****************************************************************************/
#define SDIOH_SD_TUNNING_PAT_COMP_ERR BIT(0)
#define SDIOH_GET_WRCRC_STA_TO_ERR BIT(1)
#define SDIOH_MASK_WR_CRC_STA 0x1C
#define SDIOH_WR_CRC_ERR BIT(5)
#define SDIOH_CRC16_ERR BIT(6)
#define SDIOH_CRC7_ERR BIT(7)
#define SDIOH_SD_CMD_RSP_TO_ERR BIT(8)
#define SDIOH_SD_CMD_RSP_INVALID BIT(9)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_BLOCK_CNT_L
* @{
*****************************************************************************/
#define SDIOH_MASK_BLOCL_CNT_L 0xFF
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_BLOCK_CNT_H
* @{
*****************************************************************************/
#define SDIOH_MASK_BLOCL_CNT_H 0x7F
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_TRANSFER
* @{
*****************************************************************************/
#define SDIOH_START_TRANSFER BIT(7)
#define SDIOH_TRANSFER_END BIT(6)
#define SDIOH_SD_MODULE_FSM_IDLE BIT(5)
#define SDIOH_ERR_OCCUR BIT(4)
#define SDIOH_MASK_COM_CODE 0xF
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_CMD_STATE
* @{
*****************************************************************************/
#define SDIOH_CMD_FSM_IDLE BIT(7)
/** @} */
/**************************************************************************//**
* @defgroup SDIOH_SD_DATA_STATE
* @{
*****************************************************************************/
#define SDIOH_DATA_FSM_IDLE BIT(7)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
#undef SDIOH_SUPPORT_SD30
#define SDIOH_CMD_CPLT_TIMEOUT 5000 /* Max. timeout value when checking the flag of command complete, unit: us */
#define SDIOH_XFER_CPLT_TIMEOUT 1000000 /* Max. timeout value when checking the flag of transfer complete, unit: us */
#define SDIOH_READ_TIMEOUT 100000
#define SDIOH_WRITE_TIMEOUT 250000
#define SDIOH_ERASE_TIMEOUT 2000000//250000
#define HOST_COMMAND BIT(6) /* Transmission bit of register "SD_CMD0", indicating the direction of transmission (host = 1)*/
#define SDIOH_CMD_IDX_MASK 0x3F /* Command index mask of register "SD_CMD0" */
#define SDIOH_CMD8_VHS 0x1 /* Value of "VHS" field in CMD8, 2.7-3.6V */
#define SDIOH_CMD8_CHK_PATN 0xAA /* Value of "Check pattern" field in CMD8 */
#define SDIOH_OCR_VDD_WIN 0xFF8000 /* Value of "OCR" field in ACMD41, OCR bit[23:0] */
#define SDIOH_C6R2_BUF_LEN 64 /* Buffer for CMD6, R2, etc.*/
#define SDIOH_CSD_LEN 16
/* SDIOH_Card_Response_Byte_Index */
#define SDIO_RESP0 0
#define SDIO_RESP1 1
#define SDIO_RESP2 2
#define SDIO_RESP3 3
#define SDIO_RESP4 4
#define SDIO_RESP5 5
/* SDIOH_Signal_Level */
#define SDIOH_SIG_VOL_33 0
#define SDIOH_SIG_VOL_18 1
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_sdioh.h
|
C
|
apache-2.0
| 15,428
|
/**
******************************************************************************
* @file rtl8721_sgpio.h
* @author
* @version V1.0.0
* @date 2017-10-16
* @brief This file contains all the functions prototypes for the SGPIO firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_SGPIO_H_
#define _RTL8721D_SGPIO_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup SGPIO
* @brief SGPIO driver modules
* @{
*/
/** @addtogroup SGPIO
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* SGPIO:
* - SGPIO, which is 1-pin serial GPIO, combines standard GPIO and Timer fucntion.
* It can easily realize the conversion between serial data and parallel data.
* Capture functionality is also added to measure the input waveform.
* SGPIO used for security element.
* - Base Address: SGPIO_DEV(0x4801A000)
* - SGPIO clock: 2MHz
* - IRQ: SGPIO_IRQ_LP
* - basic function:
* - Timer mode:
* 16-bit RX and Multiple timer with 16-bit prescaler
* - Counter mode:
* Multiple counter can count RX trigger events
* - Capture mode:
* RX timer can be captured by capture events(RX trigger input or multiple match event)
* capture value can be transfeered to 0 or 1 by camparing the value
* - data communication:
* - RX receiving data:
* "implement the conversion from serial to parallel data by producing shift clock."
* extract the value on the data line at three RX match events
* set "0" or "1" input by capture compare event
* - TX output mode:
* "implement the conversion from parallel to serial data by producing shift clock."
* set external output level on three multiple match events and three RX match events
* send the "0" or "1" waveform by shifting the output value of a 32-bit FIFO.
* - support power saving mode
*
*****************************************************************************************
* How to use SGPIO RX match event
*****************************************************************************************
* To use the SGPIO RX match event to control RX or Multiple timer,
* the following steps are mandatory:
*
* 1. Configure the SGPIO pinmux and pull the SGPIO pin up.
* Pinmux_Congfig(PinName, PINMUX_FUNCTION_SGPIO)
* PAD_PullCtrl(PinName, GPIO_PuPd_UP)
*
* 2. Initialize RX timer as default,
* SGPIO_RX_StructInit(SGPIO_RXInitTypeDef * SGPIO_RXInitStruct)
* Select the RX Timer trigger mode.(set the pre-scale value if needed)
*
* 3. Initialize hardware using the value configured above.
* SGPIO_RX_Init(SGPIO_TypeDef *SGPIOx, SGPIO_RXInitTypeDef *SGPIO_RXInitStruct)
*
* 4. Configure the value of RXMRx match register using the function
* SGPIO_RXMRxConfig(SGPIOx, SGPIO_RXMRxVal, SGPIO_RXMRxCtl)
* to control RX timer stop/reset/shift_clk/interrupt, where x can be 0\1\2.
* SGPIO_RXMR0MULConfig(SGPIOx, SGPIO_RXMR0Val, SGPIO_RXMR0MULCtl)
* to control Multiple timer or counter to stop/reset.
*
* 5. Waiting for the input trigger to start RX timer.
*
* @note if using interrput, remember to initialize SGPIO interrupt information
* and enable SGPIO interrupt.
* InterruptEn(IRQn_Type IrqNum, Priority)
*
*****************************************************************************************
* How to use SGPIO Multiple match event
*****************************************************************************************
* To use the SGPIO multiple match event to control multiple or RX timer,
* the following steps are mandatory:
*
* 1. Configure the SGPIO pinmux and pull the SGPIO pin up.
* Pinmux_Congfig(PinName, PINMUX_FUNCTION_SGPIO)
* PAD_PullCtrl(PinName, GPIO_PuPd_UP)
*
* 2. Initialize multiple timer as default,
* SGPIO_MUL_StructInit(SGPIO_MULInitTypeDef * SGPIO_MULInitStruct)
* Select the Multiple Timer mode or Multiple counter mode.
*
* 3. Initialize hardware using the value configured above.
* SGPIO_MUL_Init(SGPIO_TypeDef *SGPIOx, SGPIO_MULInitTypeDef *SGPIO_MULInitStruct)
*
* 4. Configure the value of MULMRx match register using the function
* SGPIO_MULMR0MulConfig(SGPIOx, SGPIO_MULMR0Val0, SGPIO_MULMR0Val1, SGPIO_MULMR0Ctl)
* to control Multiple timer or counter stop/reset/shift_clk/interrupt.
* SGPIO_MULMR0RXConfig(SGPIOx, SGPIO_MULMR0Val0, SGPIO_MULMR0Val1, SGPIO_MULMR0RXCtl)
* to control RX timer stop/reset.
*
* 5. Enable Multiple timer/counter.
* SGPIO_MULTmr_Cmd(SGPIOx, ENABLE)
*
* @note if using interrput, remember to initialize SGPIO interrupt information
* and enable SGPIO interrupt.
* InterruptEn(IRQn_Type IrqNum, Priority)
*
*****************************************************************************************
* How to use SGPIO capture event
*****************************************************************************************
* To use the SGPIO capture event to capture RX timer, the following steps are mandatory.
*
* 1. Configure the SGPIO pinmux and pull the SGPIO pin up.
* Pinmux_Congfig(Pin_Num, PINMUX_FUNCTION_SGPIO)
* PAD_PullCtrl(PinName, GPIO_PuPd_UP)
*
* 2. Initialize the SGPIO interrupt infomation and enable it.
* InterruptRegister(IRQ_FUN IrqFun, IRQn_Type IrqNum, Data, Priority)
* InterruptEn(IRQn_Type IrqNum, Priority)
*
* 3. Initialize the RX timer and capture as default.
* SGPIO_RX_StructInit(SGPIO_RXInitTypeDef * SGPIO_RXInitStruct)
* SGPIO_CAP_StructInit(SGPIO_CAPInitTypeDef * SGPIO_CAPInitStruct)
*
* 4. Select the RX timer trigger edge and capture trigger edge.
* set RX timer pre-scale if needed.
*
* 5. Initialize hardware using the value configured above.
* SGPIO_RX_Init(SGPIO_TypeDef *SGPIOx, SGPIO_RXInitTypeDef *SGPIO_RXInitStruct)
* SGPIO_CAP_Init(SGPIO_TypeDef *SGPIOx, SGPIO_CAPInitTypeDef *SGPIO_CAPInitStruct)
*
* 6. Enable capture command.
* SGPIO_Cap_Cmd(SGPIOx, ENABLE)
*
* 7. Waiting for RX input.
*
*****************************************************************************************
* How to use SGPIO capture compare event
*****************************************************************************************
* To use the SGPIO capture compare event at multiple counter match event,
* the following steps are mandatory.
*
* 1. Configure the SGPIO pinmux and pull the SGPIO pin up.
* Pinmux_Congfig(Pin_Num, PINMUX_FUNCTION_SGPIO)
* PAD_PullCtrl(PinName, GPIO_PuPd_UP)
*
* 2. Initialize the SGPIO interrupt infomation and enable it.
* InterruptRegister(IRQ_FUN IrqFun, IRQn_Type IrqNum, Data, Priority)
* InterruptEn(IRQn_Type IrqNum, Priority)
*
* 3. Initialize the RX timer, capture and multiple timer as default.
* SGPIO_RX_StructInit(SGPIO_RXInitTypeDef * SGPIO_RXInitStruct)
* SGPIO_CAP_StructInit(SGPIO_CAPInitTypeDef * SGPIO_CAPInitStruct)
* SGPIO_MUL_StructInit(SGPIO_MULInitTypeDef * SGPIO_MULInitStruct)
*
* 4. Set Rx data source to capture compare.
* SGPIO_RXInitStruct.RxDataSrc_Sel = RX_DATA_SRC_CAP_CAMPARE;
* Set Capture source to multiple counter match event.
* SGPIO_CAPInitStruct.CapSrc_Sel = CAPSRC_MUL_COUNTER.
* set RX timer pre-scale if needed.(optional)
*
* 5. Select the RX trigger edge and capture trigger edge as well as mutiple counter edge.
*
* 6. Initialize hardware using the value configured above.
* SGPIO_RX_Init(SGPIO_TypeDef *SGPIOx, SGPIO_RXInitTypeDef *SGPIO_RXInitStruct)
* SGPIO_CAP_Init(SGPIO_TypeDef *SGPIOx, SGPIO_CAPInitTypeDef *SGPIO_CAPInitStruct)
* SGPIO_MUL_Init(SGPIO_TypeDef *SGPIOx, SGPIO_MULInitTypeDef *SGPIO_MULInitStruct)
*
* 7. Configure the Multiple match event.
* SGPIO_MULMR0MulConfig(SGPIOx, SGPIO_MULMR0Val0, SGPIO_MULMR0Val1, SGPIO_MULMR0Ctl)
*
* 8. Configure the capture compare value and output value.
* SGPIO_Cap_CompConfig(SGPIOx, CapComp_Val, CapComp_Mode)
*
* 9. Enable SGPIO capture event and multiple counter mode.
* SGPIO_Cap_Cmd(SGPIOx, ENABLE)
* SGPIO_MULTmr_Cmd(SGPIOx, ENABLE)
*
*****************************************************************************************
* How to use SGPIO output PWM
*****************************************************************************************
* To use the SGPIO output PWM, the following steps are mandatory.
*
* 1. Configure the SGPIO pinmux and pull the SGPIO pin up.
* Pinmux_Congfig(Pin_Num, PINMUX_FUNCTION_SGPIO)
* PAD_PullCtrl(PinName, GPIO_PuPd_UP)
*
* 2. Initialize the RX timer as default.
* SGPIO_RX_StructInit(SGPIO_RXInitTypeDef * SGPIO_RXInitStruct
* Set Rx trigger edge mode if needed.
*
* 3. Initialize hardware using the value configured above.
* SGPIO_RX_Init(SGPIO_TypeDef *SGPIOx, SGPIO_RXInitTypeDef *SGPIO_RXInitStruct)
*
* 4. Configure RX match event, whrer x can be 0\1\2.
* SGPIO_RXMRxConfig(SGPIOx, SGPIO_RXMRxVal, SGPIO_RXMRxCtl)
*
* 5. Configure the output level at RX match event.
* SGPIO_RXMRxTXConfig(SGPIOx, SGPIO_RXMR0TXCtl, SGPIO_RXMR1TXCtl, SGPIO_RXMR2TXCtl)
*
* 6. Waiting for the RX input trigger.
*
* @note if using interrput, remember to initialize SGPIO interrupt information
* and enable SGPIO interrupt.
* InterruptEn(IRQn_Type IrqNum, Priority)
*
*****************************************************************************************
* How to use SGPIO transfer multiple data
*****************************************************************************************
* To use the SGPIO transfer multiple data, the following steps are mandatory.
*
* 1. Configure the SGPIO pinmux and pull the SGPIO pin up.
* Pinmux_Congfig(Pin_Num, PINMUX_FUNCTION_SGPIO)
* PAD_PullCtrl(PinName, GPIO_PuPd_UP)
*
* 2. Initialize the SGPIO interrupt infomation and enable it.
* InterruptRegister(IRQ_FUN IrqFun, IRQn_Type IrqNum, Data, Priority)
* InterruptEn(IRQn_Type IrqNum, Priority)
*
* 3. Initialize the Multiple timer as default.
* SGPIO_MUL_StructInit(SGPIO_MULInitTypeDef * SGPIO_MULInitStruct)
* Set TX to bi-direction open-drain output.
* Configure the multiple positon register.
* select the multiple data direction if needed.
*
* 4. Initialize hardware using the value configured above.
* SGPIO_MUL_Init(SGPIO_TypeDef *SGPIOx, SGPIO_MULInitTypeDef *SGPIO_MULInitStruct)
*
* 5. Configure MUL match event with the four multiple match registers.
* SGPIO_MULMRxGP0ValConfig(SGPIOx, SGPIO_MULMR0GP0, SGPIO_MULMR1GP0, SGPIO_MULMR2GP0, SGPIO_MULMR3GP0)
* SGPIO_MULMRxGP1ValConfig(SGPIOx, SGPIO_MULMR0GP1, SGPIO_MULMR1GP1, SGPIO_MULMR2GP1, SGPIO_MULMR3GP1)
* SGPIO_MULMRxTXCtlConfig(SGPIOx, SGPIO_MULMR0TXCtl, SGPIO_MULMR1TXCtl, SGPIO_MULMR2TXCtl, SGPIO_MULMR3TXCtl)
*
* 6. Configure the multiple data value.
* SGPIO_SetTXData(SGPIOx, SGPIO_MulDataVal, SGPIO_MulDataDPVal)
*
* 7. Configure the MCNT interrupt event to set the waveform length.
* SGPIO_MULMCNTConfig(SGPIOx, SGPIO_MULMCNTVal, SGPIO_MULMCNTCtl)
*
* 8. Enable the multiple shift_clk, multiple data load and MCNT interrupt at least.
* SGPIO_INTConfig(SGPIOx, SGPIO_IT, ENABLE)
* SGPIO_MULMCNT_Cmd(SGPIOx, ENABLE)
*
* 9. Enable the multiple timer/counter.
* SGPIO_MULTmr_Cmd(SGPIOx, ENABLE)
*
* @note if using FIFO or DMA for data transfer, according to the related API.
* Configure FIFO register and GDMA transfer buffer, and enable the command related.
*
*****************************************************************************************
* How to SGPIO RX pattern match
*****************************************************************************************
* To use the SGPIO RX pattern match event at multiple counter match capture event,
* the following steps are mandatory.
*
* 1. Configure the SGPIO pinmux and pull the SGPIO pin up.
* Pinmux_Congfig(Pin_Num, PINMUX_FUNCTION_SGPIO)
* PAD_PullCtrl(PinName, GPIO_PuPd_UP)
*
* 2. Initialize the SGPIO interrupt infomation and enable it.
* InterruptRegister(IRQ_FUN IrqFun, IRQn_Type IrqNum, Data, Priority)
* InterruptEn(IRQn_Type IrqNum, Priority)
*
* 3. Initialize the RX timer, capture and multiple timer as default.
* SGPIO_RX_StructInit(SGPIO_RXInitTypeDef * SGPIO_RXInitStruct)
* SGPIO_CAP_StructInit(SGPIO_CAPInitTypeDef * SGPIO_CAPInitStruct)
* SGPIO_MUL_StructInit(SGPIO_MULInitTypeDef * SGPIO_MULInitStruct)
*
* 4. Set Rx data source to capture compare.
* SGPIO_RXInitStruct.RxDataSrc_Sel = RX_DATA_SRC_CAP_CAMPARE;
* Set Capture source to multiple counter match event.
* SGPIO_CAPInitStruct.CapSrc_Sel = CAPSRC_MUL_COUNTER.
* set RX timer pre-scale and RX positon register if needed.(optional)
*
* 5. Select the RX trigger edge and capture trigger edge as well as mutiple counter edge.
*
* 6. Initialize hardware using the value configured above.
* SGPIO_RX_Init(SGPIO_TypeDef *SGPIOx, SGPIO_RXInitTypeDef *SGPIO_RXInitStruct)
* SGPIO_CAP_Init(SGPIO_TypeDef *SGPIOx, SGPIO_CAPInitTypeDef *SGPIO_CAPInitStruct)
* SGPIO_MUL_Init(SGPIO_TypeDef *SGPIOx, SGPIO_MULInitTypeDef *SGPIO_MULInitStruct)
*
* 7. Configure the Multiple match event.
* SGPIO_MULMR0MulConfig(SGPIOx, SGPIO_MULMR0Val0, SGPIO_MULMR0Val1, SGPIO_MULMR0Ctl)
*
* 8. Configure the capture compare value and output value.
* SGPIO_Cap_CompConfig(SGPIOx, CapComp_Val, CapComp_Mode)
*
* 9. Configure RX match event to limit the sereaching time.
* SGPIO_RXMRxConfig(SGPIOx, SGPIO_RXMRxVal, SGPIO_RXMRxCtl)
* SGPIO_RXMR0MULConfig(SGPIOx, SGPIO_RXMR0Val, SGPIO_RXMR0MULCtl)
*
* 10. Configure the RX pattern match event, and enable this interrupt.
* SGPIO_RXPatternMatchConfig(SGPIOx, RXDATADP, RXDATAMask, ENABLE)
* SGPIO_INTConfig(SGPIOx, SGPIO_IT, ENABLE)
*
* 11. Enable SGPIO capture event and multiple counter mode.
* SGPIO_Cap_Cmd(SGPIOx, ENABLE)
* SGPIO_MULTmr_Cmd(SGPIOx, ENABLE)
*
*****************************************************************************************
* How to use SGPIO monitor at power saving mode.
*****************************************************************************************
* To use the SGPIO monitor mode, the following steps are mandatory.
*
* 1. Configure the SGPIO pinmux and pull the SGPIO pin up.
* Pinmux_Congfig(Pin_Num, PINMUX_FUNCTION_SGPIO)
* PAD_PullCtrl(PinName, GPIO_PuPd_UP)
*
* 2. Initialize the SGPIO interrupt infomation and enable it.
* InterruptRegister(IRQ_FUN IrqFun, IRQn_Type IrqNum, Data, Priority)
* InterruptEn(IRQn_Type IrqNum, Priority)
*
* 3. Initialize the RX timer, multiple timer as default.
* SGPIO_RX_StructInit(SGPIO_RXInitTypeDef * SGPIO_RXInitStruct)
* SGPIO_MUL_StructInit(SGPIO_MULInitTypeDef * SGPIO_MULInitStruct)
* Configure the RX input trigger edge and multiple timer mode.
* Configure the RX or Multiple pre-scale if needed.
*
* 4. Initialize hardware use the value configured above.
* SGPIO_RX_Init(SGPIO_TypeDef *SGPIOx, SGPIO_RXInitTypeDef *SGPIO_RXInitStruct)
* SGPIO_MUL_Init(SGPIO_TypeDef *SGPIOx, SGPIO_MULInitTypeDef *SGPIO_MULInitStr
*
* 5. Configure the RX match event as monitor action for example,and
* Configure the multiple match event as timeout to get into power saving mode.
* SGPIO_RXMRxConfig(SGPIOx, SGPIO_RXMRxVal, SGPIO_RXMRxCtl)
* SGPIO_MULMR0MULConfig(SGPIOx, SGPIO_MULMR0Val, SGPIO_MULMR0MULCtl)
*
* 6. Enable multiple timer/counter event.
*
* @note this is a example of monitor mode. the specific implementation can differ.
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SGPIO_Exported_Types SGPIO Exported Types
* @{
*/
/**
* @brief SGPIO RX Init structure definition
*/
typedef struct {
u32 RxTimerEdge_Sel; /*!< Specifies the trigger mode of RXTC.
This parameter can be a value of @ref RX_Timer_Trigger_Mode_definitions */
u32 RxDataSrc_Sel; /*!< Specifies the data source of RX.
This parameter can be a value of @ref RX_Data_Source_definitions */
u32 RxPRVal; /*!< Specifies the maximum value of RX Prescale Counter.
This parameter must be set to a value in the 0x0-0xffff range. */
u32 RxPRTC; /*!< Specifies the value of RX Prescale Counter.
This parameter must be set to a value in the 0x0-0xffff range. */
u32 RxTC; /*!< Specifies the value of RX Timer counter.
This parameter must be set to a value in the 0x0-0xffff range. */
u32 RxData; /*!< Specifies the value of RX Data.
This parameter must be set to a value in the 0x0-0xffffffff range. */
u32 RxData_DP; /*!< Specifies the value of RX Data Duplicate.
This parameter must be set to a value in the 0x0-0xffffffff range. */
u32 RxPosTC; /*!< Specifies the value of RX Position counter. RxPosTC counts down when generate a shift clock for RX Data Register
This parameter must be set to a value in the 0x0-0x1f range. */
u32 RxData_Dir; /*!< Specifies the direction of RX DATA.
This parameter can be a value of @ref RX_Data_Direction */
} SGPIO_RXInitTypeDef;
/**
* @brief SGPIO CAPTURE Init structure definition
*/
typedef struct {
u32 Cap_ValidEn; /*!< Specifies the valid match whether need to enable RXTMR_CEN.
This parameter can be a value of @ref Cap_RX_Valid_Control */
u32 Cap_RxTCStop_Ctrl; /*!< Specifies the RX stop control when capture trigger event happens.
This parameter can be a value of @ref Cap_RX_Stop_Control */
u32 Cap_RxTCRst_Ctrl; /*!< Specifies the RX reset control when capture trigger event happens.
This parameter can be a value of @ref Cap_RX_Reset_Control */
u32 CapSrc_Sel; /*!< Specifies the capture trigger source.
This parameter can be a value of @ref CapSrc_Sel_definitions */
u32 CapEdge_Sel; /*!< Specifies the rx input trigger mode when the CAPR is loaded with the value of RXTC
This parameter can be a value of @ref CapEdge_Sel_definitions */
u32 CapI_En; /*!< Specifies the interrupt enable control when capture load event happens.
This parameter can be a value of @ref Cap_Interrupt_Control */
} SGPIO_CAPInitTypeDef;
/**
* @brief SGPIO Multiple Init structure definition
*/
typedef struct {
u32 BiOut; /*!< Specifies the TX to bi-direction open-drain output. When disable output, bi-direction open-drain output is high.
This parameter can be a value of @ref MUL_BiOut_definitions */
u32 MulMode_Sel; /*!< Specifies the Increased mode of MULTC.
This parameter can be a value of @ref MUL_Mode_definitions */
u32 MulPRVal; /*!< Specifies the maximum value of Multiple Prescale Counter.
This parameter must be set to a value in the 0x0-0xffff range. */
u32 MulPRTC; /*!< Specifies the value of Multiple Prescale Counter.
This parameter must be set to a value in the 0x0-0xffff range. */
u32 MulTC; /*!< Specifies the value of Multiple Timer counter.
This parameter must be set to a value in the 0x0-0xffff range. */
u32 MulPosTC; /*!< Specifies the value of Multiple Position counter. MulPosTC counts down when generate a shift clock for Multiple Data Register
This parameter must be set to a value in the 0x0-0x1f range. */
u32 MulPosRST; /*!< Specifies the reload value of RxPosTC.
This parameter must be set to a value in the 0x0-0x1f range. */
u32 MulData_Dir; /*!< Specifies the direction of Multiple DATA.
This parameter can be a value of @ref MUL_Data_Direction */
} SGPIO_MULInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SGPIO_Exported_Constants SGPIO Exported Constants
* @{
*/
/** @defgroup SGPIO_Peripheral_definitions
* @{
*/
#define IS_SGPIO_ALL_PERIPH(PERIPH) ((PERIPH) == SGPIO_DEV)
/**
* @}
*/
/** @defgroup RX_Data_Source_definitions
* @{
*/
#define RX_DATA_SRC_EXTERNAL_INPUT ((u32)0x00000000 << 4)
#define RX_DATA_SRC_CAP_CAMPARE ((u32)0x00000001 << 4)
#define IS_RX_DATA_SRC(SOURCE) (((SOURCE) == RX_DATA_SRC_EXTERNAL_INPUT) || \
((SOURCE) == RX_DATA_SRC_CAP_CAMPARE))
/**
* @}
*/
/** @defgroup RX_Timer_Trigger_Mode_definitions
* @{
*/
#define RX_TIMER_NO_TRIGGER ((u32)0x00000000 << 8)
#define RX_TIMER_RISING_EDGE ((u32)0x00000001 << 8)
#define RX_TIMER_FALLING_EDGE ((u32)0x00000002 << 8)
#define RX_TIMER_BOTH_EDGE ((u32)0x00000003 << 8)
#define IS_RX_TIMER_TRIGGER_MODE(MODE) (((MODE) == RX_TIMER_NO_TRIGGER) || \
((MODE) == RX_TIMER_RISING_EDGE) || \
((MODE) == RX_TIMER_FALLING_EDGE) || \
((MODE) == RX_TIMER_BOTH_EDGE))
/**
* @}
*/
/** @defgroup RX_Data_Direction
* @{
*/
#define RX_DATA_DIR_MSB ((u32)0x00000000 << 7)
#define RX_DATA_DIR_LSB ((u32)0x00000001 << 7)
#define IS_RX_DATA_DIR(DIRECTION) (((DIRECTION) == RX_DATA_DIR_MSB) || \
((DIRECTION) == RX_DATA_DIR_LSB))
/**
* @}
*/
/** @defgroup RXMR0_Output_Control_Options
* @{
*/
#define RX_EMC0_NONE ((u32)0x00000000 << 6)
#define RX_EMC0_OUTPUT_LOW ((u32)0x00000001 << 6)
#define RX_EMC0_OUTPUT_HIGH ((u32)0x00000002 << 6)
#define RX_EMC0_OUTPUT_TOGGLE ((u32)0x00000003 << 6)
#define IS_RXMR0_OUTCTRL_OPTION(OPTION) (((OPTION) == RX_EMC0_NONE) || \
((OPTION) == RX_EMC0_OUTPUT_LOW) || \
((OPTION) == RX_EMC0_OUTPUT_HIGH) || \
((OPTION) == RX_EMC0_OUTPUT_TOGGLE))
/**
* @}
*/
/** @defgroup RXMR1_Output_Control_Options
* @{
*/
#define RX_EMC1_NONE ((u32)0x00000000 << 8)
#define RX_EMC1_OUTPUT_LOW ((u32)0x00000001 << 8)
#define RX_EMC1_OUTPUT_HIGH ((u32)0x00000002 << 8)
#define RX_EMC1_OUTPUT_TOGGLE ((u32)0x00000003 << 8)
#define IS_RXMR1_OUTCTRL_OPTION(OPTION) (((OPTION) == RX_EMC1_NONE) || \
((OPTION) == RX_EMC1_OUTPUT_LOW) || \
((OPTION) == RX_EMC1_OUTPUT_HIGH) || \
((OPTION) == RX_EMC1_OUTPUT_TOGGLE))
/**
* @}
*/
/** @defgroup RXMR2_Output_Control_Options
* @{
*/
#define RX_EMC2_NONE ((u32)0x00000000 << 10)
#define RX_EMC2_OUTPUT_LOW ((u32)0x00000001 << 10)
#define RX_EMC2_OUTPUT_HIGH ((u32)0x00000002 << 10)
#define RX_EMC2_OUTPUT_TOGGLE ((u32)0x00000003 << 10)
#define IS_RXMR2_OUTCTRL_OPTION(OPTION) (((OPTION) == RX_EMC2_NONE) || \
((OPTION) == RX_EMC2_OUTPUT_LOW) || \
((OPTION) == RX_EMC2_OUTPUT_HIGH) || \
((OPTION) == RX_EMC2_OUTPUT_TOGGLE))
/**
* @}
*/
/** @defgroup Cap_RX_Valid_Control
* @{
*/
#define CAP_RX_VALID_ENABLE ((u32)0x00000000 << 8) /*The valid match need to enable RXTMR_CEN*/
#define CAP_RX_VALID_DISABLE ((u32)0x00000001 << 8) /*The valid match don't need to enable RXTMR_CEN*/
#define IS_CAP_RX_VALID_OPTION(OPTION) (((OPTION) == CAP_RX_VALID_DISABLE) || \
((OPTION) == CAP_RX_VALID_ENABLE))
/**
* @}
*/
/** @defgroup Cap_RX_Stop_Control
* @{
*/
#define CAP_RX_STOP_DISABLE ((u32)0x00000000 << 6)
#define CAP_RX_STOP_ENABLE ((u32)0x00000001 << 6)
#define IS_CAP_RX_STOP_OPTION(OPTION) (((OPTION) == CAP_RX_STOP_DISABLE) || \
((OPTION) == CAP_RX_STOP_ENABLE))
/**
* @}
*/
/** @defgroup Cap_RX_Reset_Control
* @{
*/
#define CAP_RX_RESET_DISABLE ((u32)0x00000000 << 5)
#define CAP_RX_RESET_ENABLE ((u32)0x00000001 << 5)
#define IS_CAP_RX_RESET_OPTION(OPTION) (((OPTION) == CAP_RX_RESET_DISABLE) || \
((OPTION) == CAP_RX_RESET_ENABLE))
/**
* @}
*/
/** @defgroup Cap_CmpVal_Sel_definitions
* @{
*/
#define CAP_CMPVAL_SEL0 ((u32)0x00000000 << 7) /*RXDATA receives 0 when CAPR is bigger than CAP_CMPVAL*/
#define CAP_CMPVAL_SEL1 ((u32)0x00000001 << 7) /*RXDATA receives 1 when CAPR is bigger than CAP_CMPVAL*/
#define IS_CAP_CMPVAL_SEL_OPTION(OPTION) (((OPTION) == CAP_CMPVAL_SEL0) || \
((OPTION) == CAP_CMPVAL_SEL1))
/**
* @}
*/
/** @defgroup CapSrc_Sel_definitions
* @{
*/
#define CAPSRC_RX_INPUT ((u32)0x00000000 << 2)
#define CAPSRC_MUL_COUNTER ((u32)0x00000001 << 2)
#define IS_CAPSRC_SEL_OPTION(OPTION) (((OPTION) == CAPSRC_RX_INPUT) || \
((OPTION) == CAPSRC_MUL_COUNTER))
/**
* @}
*/
/** @defgroup CapEdge_Sel_definitions
* @{
*/
#define CAP_RX_FALLING_EDGE ((u32)0x00000001 << 3)
#define CAP_RX_RISING_EDGE ((u32)0x00000002 << 3)
#define IS_CAPEDGE_SEL_OPTION(OPTION) (((OPTION) == CAP_RX_FALLING_EDGE) || \
((OPTION) == CAP_RX_RISING_EDGE))
/**
* @}
*/
/** @defgroup Cap_Interrupt_Control
* @{
*/
#define CAP_INTR_DISABLE ((u32)0x00000000 << 1)
#define CAP_INTR_ENABLE ((u32)0x00000001 << 1)
#define IS_CAP_INTR_OPTION(OPTION) (((OPTION) == CAP_INTR_DISABLE) || \
((OPTION) == CAP_INTR_ENABLE))
/**
* @}
*/
/** @defgroup MUL_BiOut_definitions
* @{
*/
#define MUL_DISABLE_BIOUT ((u32)0x00000000 << 16)
#define MUL_ENABLE_BIOUT ((u32)0x00000001 << 16)
#define IS_MUL_BIOUT_MODE(MODE) (((MODE) == MUL_DISABLE_BIOUT) || \
((MODE) == MUL_ENABLE_BIOUT))
/**
* @}
*/
/** @defgroup MUL_Mode_definitions
* @{
*/
#define MUL_TIMER_MODE ((u32)0x00000000 << 8)
#define MUL_COUNTER_RISING_EDGE ((u32)0x00000001 << 8)
#define MUL_COUNTER_FALLING_EDGE ((u32)0x00000002 << 8)
#define MUL_COUNTER_BOTH_EDGE ((u32)0x00000003 << 8)
#define IS_MUL_MODE(MODE) (((MODE) == MUL_TIMER_MODE) || \
((MODE) == MUL_COUNTER_RISING_EDGE) || \
((MODE) == MUL_COUNTER_FALLING_EDGE) || \
((MODE) == MUL_COUNTER_BOTH_EDGE))
/**
* @}
*/
/** @defgroup MUL_Data_Direction
* @{
*/
#define MUL_DATA_DIR_LSB ((u32)0x00000000 << 8)
#define MUL_DATA_DIR_MSB ((u32)0x00000001 << 8)
#define IS_MUL_DATA_DIR(DIRECTION) (((DIRECTION) == MUL_DATA_DIR_MSB) || \
((DIRECTION) == MUL_DATA_DIR_LSB))
/**
* @}
*/
/** @defgroup MULMR1_Output_Control_Options
* @{
*/
#define MUL_EMC1_NONE ((u32)0x00000000)
#define MUL_EMC1_OUTPUT_LOW ((u32)0x00000001)
#define MUL_EMC1_OUTPUT_HIGH ((u32)0x00000002)
#define MUL_EMC1_OUTPUT_TOGGLE ((u32)0x00000003)
#define IS_MULMR1_OUTCTRL_OPTION(OPTION) (((OPTION) == MUL_EMC1_NONE) || \
((OPTION) == MUL_EMC1_OUTPUT_LOW) || \
((OPTION) == MUL_EMC1_OUTPUT_HIGH) || \
((OPTION) == MUL_EMC1_OUTPUT_TOGGLE))
/**
* @}
*/
/** @defgroup MULMR2_Output_Control_Options
* @{
*/
#define MUL_EMC2_NONE ((u32)0x00000000 << 2)
#define MUL_EMC2_OUTPUT_LOW ((u32)0x00000001 << 2)
#define MUL_EMC2_OUTPUT_HIGH ((u32)0x00000002 << 2)
#define MUL_EMC2_OUTPUT_TOGGLE ((u32)0x00000003 << 2)
#define IS_MULMR2_OUTCTRL_OPTION(OPTION) (((OPTION) == MUL_EMC2_NONE) || \
((OPTION) == MUL_EMC2_OUTPUT_LOW) || \
((OPTION) == MUL_EMC2_OUTPUT_HIGH) || \
((OPTION) == MUL_EMC2_OUTPUT_TOGGLE))
/**
* @}
*/
/** @defgroup MULMR3_Output_Control_Options
* @{
*/
#define MUL_EMC3_NONE ((u32)0x00000000 << 4)
#define MUL_EMC3_OUTPUT_LOW ((u32)0x00000001 << 4)
#define MUL_EMC3_OUTPUT_HIGH ((u32)0x00000002 << 4)
#define MUL_EMC3_OUTPUT_TOGGLE ((u32)0x00000003 << 4)
#define IS_MULMR3_OUTCTRL_OPTION(OPTION) (((OPTION) == MUL_EMC3_NONE) || \
((OPTION) == MUL_EMC3_OUTPUT_LOW) || \
((OPTION) == MUL_EMC3_OUTPUT_HIGH) || \
((OPTION) == MUL_EMC3_OUTPUT_TOGGLE))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SGPIO_Exported_Functions SGPIO Exported Functions
* @{
*/
void SGPIO_RX_StructInit(SGPIO_RXInitTypeDef* SGPIO_RXInitStruct);
void SGPIO_RX_Init(SGPIO_TypeDef *SGPIOx, SGPIO_RXInitTypeDef* SGPIO_RXInitStruct);
void SGPIO_RXMR0MULConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR0Val, u32 SGPIO_RXMR0MULCtl);
void SGPIO_RXPosConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_PosRstVal, u32 SGPIO_RXPOSCtl);
u32 SGPIO_GetRXData(SGPIO_TypeDef *SGPIOx);
void SGPIO_RXMR0Config(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR0Val, u32 SGPIO_RXMR0Ctl);
void SGPIO_RXMR1Config(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR1Val, u32 SGPIO_RXMR1Ctl);
void SGPIO_RXMR2Config(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR2Val, u32 SGPIO_RXMR2Ctl);
void SGPIO_RXMRxTXConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR0TXCtl, u32 SGPIO_RXMR1TXCtl, u32 SGPIO_RXMR2TXCtl);
void SGPIO_RXTmr_Reset(SGPIO_TypeDef *SGPIOx);
void SGPIO_RXTmr_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState);
void SGPIO_RXPatternMatchConfig(SGPIO_TypeDef *SGPIOx, u32 RXDATADP, u32 RXDATAMask, u8 NewState);
void SGPIO_MUL_StructInit(SGPIO_MULInitTypeDef* SGPIO_MULInitStruct);
void SGPIO_MUL_Init(SGPIO_TypeDef *SGPIOx, SGPIO_MULInitTypeDef* SGPIO_MULInitStruct);
void SGPIO_MULMR0MulConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0Val0, u32 SGPIO_MULMR0Val1, u32 SGPIO_MULMR0Ctl);
void SGPIO_MULMR0RXConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0Val0, u32 SGPIO_MULMR0Val1, u32 SGPIO_MULMR0RXCtl);
void SGPIO_MULMRxGP0ValConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0GP0, u32 SGPIO_MULMR1GP0, u32 SGPIO_MULMR2GP0, u32 SGPIO_MULMR3GP0);
void SGPIO_MULMRxGP1ValConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0GP1, u32 SGPIO_MULMR1GP1, u32 SGPIO_MULMR2GP1, u32 SGPIO_MULMR3GP1);
void SGPIO_MULMRxTXCtlConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0TXCtl, u32 SGPIO_MULMR1TXCtl, u32 SGPIO_MULMR2TXCtl, u32 SGPIO_MULMR3TXCtl);
void SGPIO_SetTXData(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MulDataVal, u32 SGPIO_MulDataDPVal);
void SGPIO_OutputConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_OutputCtl);
void SGPIO_MULTmr_Reset(SGPIO_TypeDef *SGPIOx);
void SGPIO_MULTmr_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState);
void SGPIO_MULMCNTConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMCNTVal, u32 SGPIO_MULMCNTCtl);
void SGPIO_MULMCNT_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState);
void SGPIO_CAP_StructInit(SGPIO_CAPInitTypeDef* SGPIO_CAPInitStruct);
void SGPIO_CAP_Init(SGPIO_TypeDef *SGPIOx, SGPIO_CAPInitTypeDef* SGPIO_CAPInitStruct);
u32 SGPIO_GetCapVal(SGPIO_TypeDef *SGPIOx);
void SGPIO_Cap_CompConfig(SGPIO_TypeDef *SGPIOx, u32 CapComp_Val, u32 CapComp_Mode);
void SGPIO_Cap_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState);
void SGPIO_INTConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_IT, u32 NewState);
void SGPIO_INTMask(SGPIO_TypeDef *SGPIOx, u32 SGPIO_IT, u32 NewState);
u32 SGPIO_GetRawINT(SGPIO_TypeDef *SGPIOx);
void SGPIO_ClearRawINT(SGPIO_TypeDef *SGPIOx, u32 SGPIO_IT);
void SGPIO_MULFIFO_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState);
void SGPIO_MULFIFO_Set(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULFIFOVal);
void SGPIO_MULDMA_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState);
BOOL SGPIO_MULGDMA_Init(SGPIO_TypeDef *SGPIOx, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u32 *pTxBuf, int TxCount);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup SGPIO_Register_Definitions SGPIO Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup SGPIO_RXTMR_CTRL
* @{
*****************************************************************************/
#define BIT_SGPIO_RXTMREDGE_SEL ((u32)0x00000003 << 8) /*Bit[9:8], bits for RXTC start condition set*/
#define BIT_SGPIO_RXTMR_CRST ((u32)0x00000001 << 1) /*Bit[1], bit for reset RXTC and RXPRTC*/
#define BIT_SGPIO_RXTMR_CEN ((u32)0x00000001) /*Bit[0], bit for enable RXTC and RXPRTC*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXPRVAL
* @{
*****************************************************************************/
#define BIT_SGPIO_RXPRVAL ((u32)0x0000ffff) /*Bit[15:0], bits for Maximum value of the RX Prescale Counter*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXPRTC
* @{
*****************************************************************************/
#define BIT_SGPIO_RXPRTC ((u32)0x0000ffff) /*Bit[15:0], bits for RX Prescale Counter value*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXTC
* @{
*****************************************************************************/
#define BIT_SGPIO_RXTC ((u32)0x0000ffff) /*Bit[15:0], bits for RX Timer Counter value*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXMC_CTRL
* @{
*****************************************************************************/
#define BIT_SGPIO_RX_POS_CTRL ((u32)0x0000c000) /*Bit[15:14], bits for RXTC control mask when RXPOSTC reaches 0*/
#define BIT_SGPIO_RX_POSSTOP_EN ((u32)0x00000001 << 15) /*Bit[15], bit for RXTC stop control when RXPOSTC reaches 0*/
#define BIT_SGPIO_RX_POSRST_EN ((u32)0x00000001 << 14) /*Bit[14], bit for RXTC reset control when RXPOSTC reaches 0*/
#define BIT_SGPIO_RX_MR0MUL_CTRL ((u32)0x00003000) /*Bit[13:12], bits for MULTC control mask when RXMR0 matches RXTC*/
#define BIT_SGPIO_RX_MR0MULSTOP_EN ((u32)0x00000001 << 13) /*Bit[13], bit for MULTC stop control when RXMR0 matches RXTC*/
#define BIT_SGPIO_RX_MR0MULRST_EN ((u32)0x00000001 << 12) /*Bit[12], bit for MULTC reset control when RXMR0 matches RXTC*/
#define BIT_SGPIO_RX_MR2_CTRL ((u32)0x00000f00) /*Bit[11:8], bits for RXTC control mask when RXMR2 matches RXTC*/
#define BIT_SGPIO_RX_MR2SCLK_EN ((u32)0x00000001 << 11) /*Bit[11], bit for shift clock control when RXMR2 matches RXTC*/
#define BIT_SGPIO_RX_MR2STOP_EN ((u32)0x00000001 << 10) /*Bit[10], bit for RXTC stop control when RXMR2 matches RXTC*/
#define BIT_SGPIO_RX_MR2RST_EN ((u32)0x00000001 << 9) /*Bit[9], bit for RXTC reset control when RXMR2 matches RXTC*/
#define BIT_SGPIO_RX_MR2_IE ((u32)0x00000001 << 8) /*Bit[8], bit for interrupt enable when RXMR2 matches RXTC*/
#define BIT_SGPIO_RX_MR1_CTRL ((u32)0x000000f0) /*Bit[7:4], bits for RXTC control mask when RXMR1 matches RXTC*/
#define BIT_SGPIO_RX_MR1SCLK_EN ((u32)0x00000001 << 7) /*Bit[7], bit for shift clock control when RXMR1 matches RXTC*/
#define BIT_SGPIO_RX_MR1STOP_EN ((u32)0x00000001 << 6) /*Bit[6], bit for RXTC stop control when RXMR1 matches RXTC*/
#define BIT_SGPIO_RX_MR1RST_EN ((u32)0x00000001 << 5) /*Bit[5], bit for RXTC reset control when RXMR1 matches RXTC*/
#define BIT_SGPIO_RX_MR1_IE ((u32)0x00000001 << 4) /*Bit[4], bit for interrupt enable when RXMR1 matches RXTC*/
#define BIT_SGPIO_RX_MR0_CTRL ((u32)0x0000000f) /*Bit[3:0], bits for RXTC control mask when RXMR0 matches RXTC*/
#define BIT_SGPIO_RX_MR0SCLK_EN ((u32)0x00000001 << 3) /*Bit[3], bit for shift clock control when RXMR0 matches RXTC*/
#define BIT_SGPIO_RX_MR0STOP_EN ((u32)0x00000001 << 2) /*Bit[2], bit for RXTC stop control when RXMR0 matches RXTC*/
#define BIT_SGPIO_RX_MR0RST_EN ((u32)0x00000001 << 1) /*Bit[1], bit for RXTC reset control when RXMR0 matches RXTC*/
#define BIT_SGPIO_RX_MR0_IE ((u32)0x00000001) /*Bit[0], bit for interrupt enable when RXMR0 matches RXTC*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXMR0
* @{
*****************************************************************************/
#define BIT_SGPIO_RXMR0 ((u32)0x0000ffff) /*Bit[15:0], bits for RX timer counter match register 0 set*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXMR1
* @{
*****************************************************************************/
#define BIT_SGPIO_RXMR1 ((u32)0x0000ffff) /*Bit[15:0], bits for RX timer counter match register 1 set*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXMR2
* @{
*****************************************************************************/
#define BIT_SGPIO_RXMR2 ((u32)0x0000ffff) /*Bit[15:0], bits for RX timer counter match register 2 set*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_CAP_CTRL
* @{
*****************************************************************************/
#define BIT_SGPIO_CAP_CMPVAL ((u32)0xffff0000) /*Bit[31:16], bits for capture compare value set*/
#define BIT_SGPIO_CAPVALID_EN ((u32)0x00000001 << 8) /*Bit[8], bit for whether valid match needs RXTMR_CEN is enabled*/
#define BIT_SGPIO_CAP_CMPVAL_SEL ((u32)0x00000001 << 7) /*Bit[7], bit for RXDATA receives value setwhen CAPR
is bigger than CAP_CMPVAL*/
#define BIT_SGPIO_CAP_RXTCSTOP_EN ((u32)0x00000001 << 6) /*Bit[6], bit for stop RXTC and clear RXTMR_CEN when
the capture trigger event happens*/
#define BIT_SGPIO_CAP_RXTCRST_EN ((u32)0x00000001 << 5) /*Bit[5], bit for reset RXTC when the capture trigger event happens*/
#define BIT_SGPIO_CAP_RXEDGE_SEL ((u32)0x00000003 << 3) /*Bit[4:3], bits for capture edge select mask*/
#define BIT_SGPIO_CAPSRC_SEL ((u32)0x00000001 << 2) /*Bit[2], bit for eelect the capture trigger source*/
#define BIT_SGPIO_CAP_IE ((u32)0x00000001 << 1) /*Bit[1], bit for interrupt enable when capture load event happens*/
#define BIT_SGPIO_CAP_EN ((u32)0x00000001) /*Bit[0], bit for ebalbe CAPR loaded with the value of RXTC*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_CAPR
* @{
*****************************************************************************/
#define BIT_SGPIO_CAPR ((u32)0x0000ffff) /*Bit[15:0], bits for RX timer counter capture value*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULTMR_CTRL
* @{
*****************************************************************************/
#define BIT_SGPIO_MULMODE_SEL ((u32)0x00000003 << 8) /*Bit[9:8], bits for MULTC work mode*/
#define BIT_SGPIO_MULTMR_CRST ((u32)0x00000001 << 1) /*Bit[1], bit for reset MULTC and MULPRTC*/
#define BIT_SGPIO_MULTMR_CEN ((u32)0x00000001) /*Bit[0], bit for enable MULTC and MULPRTC*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULPRVAL
* @{
*****************************************************************************/
#define BIT_SGPIO_MULPRVAL ((u32)0x0000ffff) /*Bit[15:0], bits for Maximum value of the Multiple Prescale Counter*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULPRTC
* @{
*****************************************************************************/
#define BIT_SGPIO_MULPRTC ((u32)0x0000ffff) /*Bit[15:0], bits for Multiple Prescale Counter value*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULTC
* @{
*****************************************************************************/
#define BIT_SGPIO_MULTC ((u32)0x0000ffff) /*Bit[15:0], bits for Multiple Timer Counter value*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULMC_CTRL
* @{
*****************************************************************************/
#define BIT_SGPIO_MUL_DMA_START ((u32)0x00000001 << 13) /*Bit[13], bit for trigger mutiple match FIFO load with data*/
#define BIT_SGPIO_MUL_DMA_EN ((u32)0x00000001 << 12) /*Bit[12], bit for DMA mode enable*/
#define BIT_SGPIO_MUL_FMODE_EN ((u32)0x00000001 << 11) /*Bit[11], bit for Multiple FIFO mode enable*/
#define BIT_SGPIO_MUL_MCNT_CTRL ((u32)0x00000700) /*Bit[10:8], bits for MULTC control mask when MUL_MCNT reaches zero*/
#define BIT_SGPIO_MUL_MCNTSTOP_EN ((u32)0x00000001 << 10) /*Bit[10], bit for MULTC stop control when MUL_MCNT reaches zero*/
#define BIT_SGPIO_MUL_MCNTRST_EN ((u32)0x00000001 << 9) /*Bit[9], bit for MULTC reset control when MUL_MCNT reaches zero*/
#define BIT_SGPIO_MUL_MCNT_IE ((u32)0x00000001 << 8) /*Bit[8], bit for interrupt enable when MUL_MCNT reaches zero*/
#define BIT_SGPIO_MUL_MR0MCNT_EN ((u32)0x00000001 << 7) /*Bit[7], bit for enable MUL_MCNT counts down when
MULMR0 matches MULTC*/
#define BIT_SGPIO_MUL_MR0CAPSRC_EN ((u32)0x00000001 << 6) /*Bit[6], bit for change the capture trigger source*/
#define BIT_SGPIO_MUL_MR0RX_CTRL ((u32)0x00000030) /*Bit[5:4], bits for RXTC control mask when MULMR0 matches MULTC*/
#define BIT_SGPIO_MUL_MR0RXSTOP_EN ((u32)0x00000001 << 5) /*Bit[5], bit for RXTC STOP control when MULMR0 matches MULTC*/
#define BIT_SGPIO_MUL_MR0RXRST_EN ((u32)0x00000001 << 4) /*Bit[4], bit for RXTC reset control when MULMR0 matches MULTC*/
#define BIT_SGPIO_MUL_MR0_CTRL ((u32)0x0000000f) /*Bit[3:0], bits for MULTC control mask when MULMR0 matches MULTC*/
#define BIT_SGPIO_MUL_MR0SCLK_EN ((u32)0x00000001 << 3) /*Bit[3], bit for shift clock control when MULMR0 matches MULTC*/
#define BIT_SGPIO_MUL_MR0STOP_EN ((u32)0x00000001 << 2) /*Bit[2], bit for MULTC STOP control when MULMR0 matches MULTC*/
#define BIT_SGPIO_MUL_MR0RST_EN ((u32)0x00000001 << 1) /*Bit[1], bit for MULTC reset control when MULMR0 matches MULTC*/
#define BIT_SGPIO_MUL_MR0_IE ((u32)0x00000001) /*Bit[0], bit for interrupt enable when MULMR0 matches MULTC*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULMR01GP0
* @{
*****************************************************************************/
#define BIT_SGPIO_MULMR1_GP0 ((u32)0xffff0000) /*Bit[31:16], bits for Multiple timer counter match register 1
when TXDATA[0] is 0*/
#define BIT_SGPIO_MULMR0_GP0 ((u32)0x0000ffff) /*Bit[15:0], bits for Multiple timer counter match register 0
when TXDATA[0] is 0*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULMR23GP0
* @{
*****************************************************************************/
#define BIT_SGPIO_MULMR3_GP0 ((u32)0xffff0000) /*Bit[31:16], bits for Multiple timer counter match register 3
when TXDATA[0] is 0*/
#define BIT_SGPIO_MULMR2_GP0 ((u32)0x0000ffff) /*Bit[15:0], bits for Multiple timer counter match register 2
when TXDATA[0] is 0*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULMR01GP1
* @{
*****************************************************************************/
#define BIT_SGPIO_MULMR1_GP1 ((u32)0xffff0000) /*Bit[31:16], bits for Multiple timer counter match register 1
when TXDATA[0] is 1*/
#define BIT_SGPIO_MULMR0_GP1 ((u32)0x0000ffff) /*Bit[15:0], bits for Multiple timer counter match register 0
when TXDATA[0] is 1*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULMR23GP1
* @{
*****************************************************************************/
#define BIT_SGPIO_MULMR3_GP1 ((u32)0xffff0000) /*Bit[31:16], bits for Multiple timer counter match register 3
when TXDATA[0] is 1*/
#define BIT_SGPIO_MULMR2_GP1 ((u32)0x0000ffff) /*Bit[15:0], bits for Multiple timer counter match register 2
when TXDATA[0] is 1*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MUL_MCNT
* @{
*****************************************************************************/
#define BIT_SGPIO_MUL_MCNT ((u32)0x000000ff) /*Bit[3:0], bits for mask of Multiple Match Counter Register*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULEMR
* @{
*****************************************************************************/
#define BIT_SGPIO_BIOUT ((u32)0x00000001 << 16) /*Bit[16], bit for send TX to bi-direction open-drain output*/
#define BIT_SGPIO_RXEMC_CTRL ((u32)0x00000fc0) /*Bit[11:6], bits for output control mask of RX match event*/
#define BIT_SGPIO_RXEMC2 ((u32)0x00000003 << 10) /*Bit[11:10], bits for output control mask of RXMR2 match event*/
#define BIT_SGPIO_RXEMC1 ((u32)0x00000003 << 8) /*Bit[9:8], bits for output control mask of RXMR1 match event*/
#define BIT_SGPIO_RXEMC0 ((u32)0x00000003 << 6) /*Bit[7:6], bits for output control mask of RXMR0 match event*/
#define BIT_SGPIO_MULEMC3 ((u32)0x00000003 << 4) /*Bit[5:4], bits for output control mask of MULMR3 match event*/
#define BIT_SGPIO_MULEMC2 ((u32)0x00000003 << 2) /*Bit[3:2], bits for output control mask of MULMR2 match event*/
#define BIT_SGPIO_MULEMC1 ((u32)0x00000003) /*Bit[1:0], bits for output control mask of MULMR1 match event*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_DATA_CTRL
* @{
*****************************************************************************/
#define BIT_SGPIO_TXDATA_DIR ((u32)0x00000001 << 8) /*Bit[8], bit for output direction set of the TXDATA*/
#define BIT_SGPIO_RXDATA_DIR ((u32)0x00000001 << 7) /*Bit[7], bit for output direction set of the RXDATA*/
#define BIT_SGPIO_PATTERN_MATCH_IE ((u32)0x00000001 << 6) /*Bit[6], bit for interrupt enable of pattern match*/
#define BIT_SGPIO_PATTERN_MATCH_MODE ((u32)0x00000001 << 5) /*Bit[5], bit for mode enable of pattern match*/
#define BIT_SGPIO_RXDATASRC_SEL ((u32)0x00000001 << 4) /*Bit[4], bit for select of RX data source*/
#define BIT_SGPIO_MULLOAD_IE ((u32)0x00000001 << 3) /*Bit[3], bit for interrupt enable when MULDATA_DP is loaded with MULDATA*/
#define BIT_SGPIO_RXLOAD_IE ((u32)0x00000001 << 2) /*Bit[2], bit for interrupt enable when RXDATA_DP is loaded with RXDATA*/
#define BIT_SGPIO_MULSFT_IE ((u32)0x00000001 << 1) /*Bit[1], bit for interrupt enable when have a shift clock for Multiple Data Register*/
#define BIT_SGPIO_RXSFT_IE ((u32)0x00000001) /*Bit[0], bit for interrupt enable when have a shift clock for RX Data Register*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXDATA
* @{
*****************************************************************************/
#define BIT_SGPIO_RXDATA ((u32)0xffffffff) /*Bit[31:0], bits for RX Data mask*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXDATA_DP
* @{
*****************************************************************************/
#define BIT_SGPIO_RXDATA_DP ((u32)0xffffffff) /*Bit[31:0], bits for RX Data Duplicate mask*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXPOSR
* @{
*****************************************************************************/
#define BIT_SGPIO_RXPOSRST ((u32)0x00001f00) /*Bit[12:8], bits for reload value mask of RXPOSTC after
RXPOSTC reaches 0x0*/
#define BIT_SGPIO_RXPOSTC ((u32)0x0000001f) /*Bit[4:0], bits for RX Position counter mask*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_RXDATAMASK
* @{
*****************************************************************************/
#define BIT_SGPIO_RXDATAMASK ((u32)0xffffffff) /*Bit[31:0], bits for mask of pattern match function mask*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULDATA
* @{
*****************************************************************************/
#define BIT_SGPIO_MULDATA ((u32)0xffffffff) /*Bit[31:0], bits for Multiple Data mask*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULDATA_DP
* @{
*****************************************************************************/
#define BIT_SGPIO_MULDATA_DP ((u32)0xffffffff) /*Bit[31:0], bits for Multiple Data Duplicate mask*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULPOSR
* @{
*****************************************************************************/
#define BIT_SGPIO_MULPOSRST ((u32)0x00001f00) /*Bit[12:8], bits for reload value mask of MULPOSTC after
MULPOSTC reaches 0x0*/
#define BIT_SGPIO_MULPOSTC ((u32)0x0000001f) /*Bit[4:0], bits for Multiple Position counter mask*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_MULFDATA
* @{
*****************************************************************************/
#define BIT_SGPIO_MULFDATA ((u32)0xffffffff) /*Bit[31:0], bits for match value mask for FIFO mode*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_ISR
* @{
*****************************************************************************/
#define BIT_SGPIO_MULMCNT_IS ((u32)0x00000001 << 10) /*Bit[10], bit for interrupt raw status when MUL_MCNT counts to zero*/
#define BIT_SGPIO_PATTERN_MATCH_IS ((u32)0x00000001 << 9) /*Bit[9], bit for interrupt raw status for matching pattern*/
#define BIT_SGPIO_MULLOAD_IS ((u32)0x00000001 << 8) /*Bit[8], bit for interrupt raw status for loading multiple data*/
#define BIT_SGPIO_RXLOAD_IS ((u32)0x00000001 << 7) /*Bit[7], bit for interrupt raw status for loading rx data*/
#define BIT_SGPIO_MULSFT_IS ((u32)0x00000001 << 6) /*Bit[6], bit for interrupt raw status for multiple shift clock*/
#define BIT_SGPIO_RXSFT_IS ((u32)0x00000001 << 5) /*Bit[5], bit for interrupt raw status for rx shift clock*/
#define BIT_SGPIO_CAPI_IS ((u32)0x00000001 << 4) /*Bit[4], bit for interrupt raw status for capture load event*/
#define BIT_SGPIO_MUL_MR0I_IS ((u32)0x00000001 << 3) /*Bit[3], bit for interrupt raw status for multiple MR0 match event*/
#define BIT_SGPIO_RX_MR2I_IS ((u32)0x00000001 << 2) /*Bit[2], bit for interrupt raw status for RX MR2 match event*/
#define BIT_SGPIO_RX_MR1I_IS ((u32)0x00000001 << 1) /*Bit[1], bit for interrupt raw status for RX MR1 match event*/
#define BIT_SGPIO_RX_MR0I_IS ((u32)0x00000001) /*Bit[0], bit for interrupt raw status for RX MR0 match event*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_GF
* @{
*****************************************************************************/
#define BIT_SGPIO_GF ((u32)0x000000ff) /*Bit[7:0], bits for set digital glitch filtering*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_OUTPUT
* @{
*****************************************************************************/
#define BIT_SGPIO_OUTPUT ((u32)0x00000001) /*Bit[0], bit for drive the state of output*/
#define BIT_SGPIO_OUTPUT_LOW ((u32)0x00000000) /*Bit[0], bit for drive the state low of output*/
#define BIT_SGPIO_OUTPUT_HIGH ((u32)0x00000001) /*Bit[0], bit for drive the state high of output*/
/** @} */
/**************************************************************************//**
* @defgroup SGPIO_IMR
* @{
*****************************************************************************/
#define BIT_SGPIO_INTR_MASK ((u32)0x00000fff) /*Bit[11:0], bits for all interrupt mask*/
#define BIT_SGPIO_MULMCNT_IM ((u32)0x00000001 << 10) /*Bit[10], bit for interrupt mask when MUL_MCNT counts to zero*/
#define BIT_SGPIO_PATTERN_MATCH_IM ((u32)0x00000001 << 9) /*Bit[9], bit for interrupt mask for matching pattern*/
#define BIT_SGPIO_MULLOAD_IM ((u32)0x00000001 << 8) /*Bit[8], bit for interrupt mask for loading multiple data*/
#define BIT_SGPIO_RXLOAD_IM ((u32)0x00000001 << 7) /*Bit[7], bit for interrupt mask for loading rx data*/
#define BIT_SGPIO_MULSFT_IM ((u32)0x00000001 << 6) /*Bit[6], bit for interrupt mask for multiple shift clock*/
#define BIT_SGPIO_RXSFT_IM ((u32)0x00000001 << 5) /*Bit[5], bit for interrupt mask for rx shift clock*/
#define BIT_SGPIO_CAPI_IM ((u32)0x00000001 << 4) /*Bit[4], bit for interrupt mask for capture load event*/
#define BIT_SGPIO_MUL_MR0I_IM ((u32)0x00000001 << 3) /*Bit[3], bit for interrupt mask for multiple MR0 match event*/
#define BIT_SGPIO_RX_MR2I_IM ((u32)0x00000001 << 2) /*Bit[2], bit for interrupt mask for RX MR2 match event*/
#define BIT_SGPIO_RX_MR1I_IM ((u32)0x00000001 << 1) /*Bit[1], bit for interrupt mask for RX MR1 match event*/
#define BIT_SGPIO_RX_MR0I_IM ((u32)0x00000001) /*Bit[0], bit for interrupt mask for RX MR0 match event*/
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
#endif //_RTL8721D_SGPIO_H_
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_sgpio.h
|
C
|
apache-2.0
| 54,067
|
#ifndef _RTL8721D_SIMULATION_H_
#define _RTL8721D_SIMULATION_H_
/* CPUID */
#define SIMULATION_KM0_CPUID 0
#define SIMULATION_KM4_CPUID 1
/* REG */
#define KM0_SIMULATION_STAGE_REG 0x144
#define KM4_SIMULATION_STAGE_REG 0x148
/* KM0 STAGE */
#define BIT_KM0_RUN_INTO_FLASH BIT(0) /* boot into flash */
#define BIT_KM0_IMG1_BSS_CLR BIT(1) /* img1 bss clear done */
#define BIT_KM0_FLASH_CLK_PLL_EN BIT(2) /* flash clk change from xtal to pll */
#define BIT_KM0_FLASH_QIO_EN BIT(3) /* flash Qaurd IO EN */
#define BIT_KM0_FLASH_CALI_START BIT(4) /* flash Calibration start */
#define BIT_KM0_FLASH_CALI_END BIT(5) /* flash Calibration end */
#define BIT_KM0_FUNCTIONS_EN BIT(6) /* Enable KM0 periperals clock & function ok */
#define BIT_KM0_SYSTIMER_EN BIT(7) /* Enable KM0 systimer ok */
#define BIT_KM0_KM4_FREERUN BIT(8) /* Let KM4 Free run into flash */
#define BIT_KM0_IMG2_VALID BIT(9) /* check image2 valid done */
#define BIT_KM0_IMG2_LOAD BIT(10) /* image2 load done */
#define BIT_KM0_TO_IMG2 BIT(11) /* image1 call image2 entry */
#define BIT_KM0_ENTER_IMG2 BIT(12) /* image2 enter */
#define BIT_KM0_IMG2_BSS_CLR BIT(13) /* image2 bss clear done */
#define BIT_KM0_OSC_CALI_START BIT(14) /* osc calibration start */
#define BIT_KM0_OSC_CALI_END BIT(15) /* osc calibration end */
#define BIT_KM0_RTC_INIT_DONE BIT(16) /* RC init done */
#define BIT_KM0_APP_ENTER BIT(17) /* app enter */
#define BIT_KM0_MAIN_ENTER BIT(18) /* main enter */
#define BIT_KM0_WIFIFW_INIT_START BIT(19) /* wififw init start */
#define BIT_KM0_WIFIFW_INIT_END BIT(20) /* wififw init end */
#define BIT_KM0_SIMULATION_START BIT(21) /* simulation start */
#define BIT_KM0_SIMULATION_END BIT(22) /* simulation end */
/* KM4 STAGE */
#define BIT_KM4_RUN_INTO_FLASH BIT(0)
#define BIT_KM4_IMG1_BSS_CLR BIT(1) /* img1 bss clear done */
#define BIT_KM4_IMG2_VALID BIT(2) /* check image2 valid done */
#define BIT_KM4_IMG2_LOAD BIT(3) /* image2 load done */
#define BIT_KM4_IMG3_LOAD_START BIT(4) /* img3 load start */
#define BIT_KM4_IMG3_LOAD_END BIT(5) /* img3 load end */
#define BIT_KM4_TZ_CFG_DONE BIT(6) /* trustzone config done */
#define BIT_KM4_TO_IMG2 BIT(7) /* image1 call image2 entry */
#define BIT_KM4_ENTER_IMG2 BIT(8) /* image2 enter */
#define BIT_KM4_IMG2_BSS_CLR BIT(9) /* image2 bss clear done */
#define BIT_KM4_ENTER_IMG3 BIT(10) /* image2 enter */
#define BIT_KM4_IMG3_BSS_CLR BIT(11) /* image2 bss clear done */
#define BIT_KM4_APP_ENTER BIT(12) /* app enter */
#define BIT_KM4_MAIN_ENTER BIT(13) /* main enter */
#define BIT_KM4_WIFI_INIT_START BIT(14) /* wififw init start */
#define BIT_KM4_WIFI_INIT_END BIT(15) /* wififw init end */
#define BIT_KM4_SIMULATION_START BIT(16) /* simulation start */
#define BIT_KM4_SIMULATION_END BIT(17) /* simulation end */
/* FUNCTION */
u32 simulation_stage_set(u32 cpuid, u32 sim_stage_bit);
#endif /* _RTL8721D_SIMULATION_H_ */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_simulation.h
|
C
|
apache-2.0
| 3,029
|
#ifndef _HAL_SOCPS_H_
#define _HAL_SOCPS_H_
typedef struct
{
u32 Module;
u32 Status;
} PWRCFG_TypeDef;
typedef struct
{
u32 Pinmux; /* PINMUX_S0/S1/S2 based on aon_wakepin */
u32 Status;
u32 Polarity; /* 1 is high, 0 is low */
} WAKEPIN_TypeDef;
typedef struct
{
u32 Module;
u32 Event;
u32 Status;
} HSWAKEEVENT_TypeDef;
extern u8 aon_wakepin[4][3];
extern PWRCFG_TypeDef sleep_wevent_config[];
extern PWRCFG_TypeDef sleep_aon_wevent_config[];
extern PWRCFG_TypeDef sleep_hsram_config[];
extern PWRCFG_TypeDef sleep_lsram_config[];
extern PWRCFG_TypeDef dsleep_lsram_config[];
extern WAKEPIN_TypeDef sleep_wakepin_config[];
extern PWRCFG_TypeDef km0_pwrmgt_config[];
extern PWRCFG_TypeDef dsleep_aon_wevent_config[];
extern HSWAKEEVENT_TypeDef hs_wakeevent_config[];
extern void SOCPS_InitSYSIRQ_HP(void);
extern void SOCPS_CPUReset(void);
extern void SOCPS_SleepPG(void);
extern void SOCPS_SleepCG(void);
extern void SOCPS_InitSYSIRQ(void);
extern void SOCPS_SleepInit(void);
extern void SOCPS_DsleepInit(void);
extern void SOCPS_SleepDeInit(void);
extern void SOCPS_DsleepWakeStatusSet(u32 DslpWake);
extern u32 SOCPS_DsleepWakeStatusGet(void);
extern void SOCPS_ClearWakeEvent_HP(void);
extern void SOCPS_SetWakeEvent_HP(u32 Option, u32 NewStatus);
extern void SOCPS_AONTimerCmd(u32 NewStatus);
extern int SOCPS_AONWakeReason(void);
extern void SOCPS_AONWakeClear(u32 BitMask);
extern void SOCPS_AONTimer(u32 SDuration);
extern void SOCPS_AONTSF(u32 EarlyBcnUs, u32 WakeIntvalUs);
extern VOID SOCPS_MMUReFill(VOID);
extern void SOCPS_SetWakeEvent(u32 Option, u32 NewStatus);
extern void SOCPS_SetWakeEventAON(u32 Option, u32 NewStatus);
extern void SOCPS_ClearWakePin(void);
extern void SOCPS_ClearWakeEvent(void);
extern void SOCPS_AudioLDO(u32 NewStatus);
extern void SOCPS_SWRLDO_Suspend(u32 new_status);
extern void SOCPS_OSC2M_Cmd(u32 new_status);
extern void SOCPS_SleepCG_RAM(void);
extern void SOCPS_SleepPG_RAM(void);
extern void SOCPS_DeepSleep_RAM(void);
extern int SOCPS_WakePinCheck(void);
#endif //_HAL_SOCPS_H_
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_soc_ps.h
|
C
|
apache-2.0
| 2,051
|
/**
******************************************************************************
* @file rtl8721d_ssi.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_SPI_H_
#define _RTL8710B_SPI_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup SPI
* @brief SPI driver modules
* @{
*/
/** @addtogroup SPI
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* SPI0:
* - Support Motorola SPI interface
* - Role: Master or Slave
* - Base Address: SPI0_DEV
* - Bus Clk: 100MHz
* - BaudRate: less than or equal to 50M
* - Transfer mode:Tx,Rx,TRx,EEPROM Read when configured as Master; TRx when configured as Slave
* - Data Frame Size: 4-16 bits supported
* - IRQ Number: SPI0_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI0_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI0_RX
*
* SPI1:
* - Support Motorola SPI interface
* - Role: Master
* - Base Address: SPI1_DEV
* - Bus Clk: 50MHz
* - BaudRate: less than or equal to 25M
* - Transfer mode:Tx,Rx,TRx,EEPROM Read
* - Data Frame Size: 4-16 bits supported
* - IRQ Number: SPI1_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI1_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI1_RX
*
*****************************************************************************************
* How to use Normal SPI
*****************************************************************************************
* To use the SPI in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the following functions:
* -RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE) for SPI0;
* -RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE) for SPI1;
*
* 2. Configure the SPIx pinmux:
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master;
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave;
*
* 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
* SSI_StructInit() and change some parameters if needed
*
* 4. Init Hardware use step3 parameters:
* SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct)
*
* 5. Enable the SPI:
* SSI_Cmd()
*
* 6. When using poll:
* -Using SSI_Writeable() function to make sure that the transmit FIFO is not full,
* then using SSI_WriteData() function to send data
*
* -Using SSI_Readable() function to make sure that the receive FIFO is not empty,
* then using SSI_ReadData() function to receive data
*
* 7. Enable the NVIC and the corresponding interrupt using following function if you need
* to use interrupt mode.
* -SSI_INTConfig(): SPI IRQ Mask set
* -InterruptRegister(): register the SPI irq handler
* -InterruptEn(): Enable the NVIC interrupt and set irq priority
*
*
* @note in SPI_Exported_Functions group, these functions below are about Interrupts
* and flags management:
* -SSI_GetIsr()
* -SSI_GetRawIsr()
* -SSI_INTConfig()
* -SSI_SetRxFifoLevel()
* -SSI_SetTxFifoLevel()
* -SSI_SetIsrClean()
*
*
*****************************************************************************************
* How to use SPI in DMA mode
*****************************************************************************************
* To use the SPI in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the following functions:
* -RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE) for SPI0;
* -RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE) for SPI1;
*
* 2. Configure the SPIx pinmux:
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master;
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave;
*
* 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
* SSI_StructInit() and change some parameters if needed
*
* 4. Init Hardware use step3 parameters:
* SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct)
*
* 5. Enable the SPI:
* SSI_Cmd()
*
* 6. GDMA related configurations(DMA burst size/source address/destination address/block size etc).
*
* 7. Active the SPI DMA TX/RX using SSI_SetDmaEnable() function.
*
* @note in SPI_Exported_Functions group, these functions below are about DMA:
* -SSI_SetDmaEnable()
* -SSI_SetDmaLevel()
*
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup SPI_Exported_Types SPI Exported Types
* @{
*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
u32 SPI_DmaRxDataLevel; /*!< Specifies the DMA receive data level.
The dma_rx_req is generated when the number of valid data entries in the
receive FIFO is equal to or above this field value+1,and RDMAE=1.
@note For Amebaz, the value range of this parameter should be 0 to 63,because
the depth of Rx FIFO is 64. */
u32 SPI_DmaTxDataLevel; /*!< Specifies the DMA transmit data level.
The dma_tx_req is generated when the number of valid data entries in the
transmit FIFO is equal to or below this field value,and TDMAE=1.
@note For Amebaz, the value range of this parameter should be 0 to 63,because
the depth of Rx FIFO is 64. */
u32 SPI_RxThresholdLevel; /*!< Specifies the receive FIFO threshold level.
This Parameter controls the level of entries(or above) at which the receive FIFO controller
triggers an interrupt.When the number of receive FIFO entries is greater than or equal to this
value +1,the receive FIFO full interrupt is triggered.
@note For Amebaz, the value range of this parameter should be 0 to 63,because the depth
of Rx FIFO is 64. */
u32 SPI_TxThresholdLevel; /*!< Specifies the transmit FIFO threshold level.
This Parameter controls the level of entries (or below) at which the transmit FIFO controller
triggers an interrupt.When the number of transmit FIFO entries is less than or equal to this
value,the transmit FIFO empty interrupt is triggered.
@note For Amebaz, the value range of this parameter should be 0 to 63,because of the depth
of Rx FIFO is 64. */
u32 SPI_SlaveSelectEnable; /*!< Set the slave select enable flag.
This Parameter controls which slave to be selected by master,each bit in SER register
corresponds to a slave select line(ss_x_n) from spi master.
@note The default vlaue of this parameter is 0,and one slave is selected.if more slaves to be selected,
you may use SW way to do this.And this parameter is used only when the device is master. */
u32 SPI_ClockDivider; /*!< Specifies the SPI Baud Rate.
The value of sclk_out equals to ssi_clk devides the value of this parameter
@note The LSB for this field is always set to 0 and is unaffected by a write operation,which ensures
an even value is held. */
u32 SPI_DataFrameNumber; /*!< Specifies the number of data frames master wants to receive .
When TMOD=10 or TMOD=11,Ctrl1 register uses this value to set the number of data frames to
be continuous received.
@note The value of this parameter should be set to the number of data frames that to be received
minus one.And this parameter is used only when the device is master. */
u32 SPI_DataFrameFormat; /*!< Selects which serial protocol transfers the data .
This parameter can be a value of @ref SPI_Frame_Format_definitions. */
u32 SPI_DataFrameSize; /*!< Selects the data frame length .
This parameter can be a value of @ref SPI_Data_Frame_Size_definitions.
@note Need to right-justify transmit data before writting into the transmit FIFO
The transmit logic ignores the upper unused bits when transmitting the data. */
u32 SPI_InterruptMask; /*!< Specifies which interrupt to be enable.
Each bit in this parameter corresponds to a specific interrupt.*/
u32 SPI_Role; /*!< Specifies the role of SPI device.
This parameter can be a value of @ref SPI_ROLE_definitions. . */
u32 SPI_SclkPhase; /*!< Specifies the serial clock phase.
When SPI_SclkPhase = 0, data are captured on the first edge of the serial clock. When SPI_SclkPhase = 1,
the serial clock starts toggling one cycle after the slave select line is activated, and data
are captured on the second edge of the serial clock.
This parameter can be a value of @ref SPI_SCPH_definitions.
@note Valid when the frame format(FRF) is set to Motorola SPI. */
u32 SPI_SclkPolarity; /*!< Specifies the serial clock polarity.
When SPI_SclkPolarity = 0, the serial clock remains low when idle. When SPI_SclkPolarity = 1,
the serial clock remains high when idle.
This parameter can be a value of @ref SPI_SCPOL_definitions.
@note Valid when the frame format(FRF) is set to Motorola SPI.*/
u32 SPI_TransferMode; /*!< Selects the mode of transfer for serial communication.
This parameter can be a value of @ref SPI_TMOD_definitions.
@note This transfer mode is only valid when the DW_apb_ssi is configured as a master device.*/
u32 SPI_MicrowireControlFrameSize; /*!< Selects the length of the control word for the Microwire frame format.
This parameter can be a value of @ref SPI_MW_Control_Frame_Size_definitions. */
u32 SPI_MicrowireDirection; /*!< Specifies of the data word when the Microwire serial protocol is used.
This parameter can be a value of @ref SPI_MW_Direction_definitions. */
u32 SPI_MicrowireHandshaking; /*!< Specifies Microwire Handshaking.
This parameter can be a value of @ref SPI_MW_Handshake_Enable_definitions. */
u32 SPI_MicrowireTransferMode; /*!< Specifies Microwire Transfer Mode.
This parameter can be a value of @ref SPI_MW_TMOD_definitions. */
}SSI_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
/** @defgroup SPI_TMOD_definitions
* @{
*/
#define TMOD_TR (0)
#define TMOD_TO (1)
#define TMOD_RO (2)
#define TMOD_EEPROM_R (3)
/**
* @}
*/
/** @defgroup SPI_SCPOL_definitions
* @{
*/
#define SCPOL_INACTIVE_IS_LOW (0)
#define SCPOL_INACTIVE_IS_HIGH (1)
/**
* @}
*/
/** @defgroup SPI_SCPH_definitions
* @{
*/
#define SCPH_TOGGLES_IN_MIDDLE (0)
#define SCPH_TOGGLES_AT_START (1)
/**
* @}
*/
/** @defgroup SPI_Data_Frame_Size_definitions
* @{
*/
#define DFS_4_BITS (3)
#define DFS_5_BITS (4)
#define DFS_6_BITS (5)
#define DFS_7_BITS (6)
#define DFS_8_BITS (7)
#define DFS_9_BITS (8)
#define DFS_10_BITS (9)
#define DFS_11_BITS (10)
#define DFS_12_BITS (11)
#define DFS_13_BITS (12)
#define DFS_14_BITS (13)
#define DFS_15_BITS (14)
#define DFS_16_BITS (15)
/**
* @}
*/
/** @defgroup SPI_SS_TOGGLE_PHASE_definitions
* @{
*/
#define SPI_SS_NOT_TOGGLE (0)
#define SPI_SS_TOGGLE (1)
/**
* @}
*/
/** @defgroup SPI_MW_Control_Frame_Size_definitions
* @{
*/
#define CFS_1_BIT (0)
#define CFS_2_BITS (1)
#define CFS_3_BITS (2)
#define CFS_4_BITS (3)
#define CFS_5_BITS (4)
#define CFS_6_BITS (5)
#define CFS_7_BITS (6)
#define CFS_8_BITS (7)
#define CFS_9_BITS (8)
#define CFS_10_BITS (9)
#define CFS_11_BITS (10)
#define CFS_12_BITS (11)
#define CFS_13_BITS (12)
#define CFS_14_BITS (13)
#define CFS_15_BITS (14)
#define CFS_16_BITS (15)
/**
* @}
*/
/** @defgroup SPI_ROLE_definitions
* @{
*/
#define SSI_SLAVE (0)
#define SSI_MASTER (1)
/**
* @}
*/
/** @defgroup SPI_Frame_Format_definitions
* @{
*/
#define FRF_MOTOROLA_SPI (0)
#define FRF_TI_SSP (1)
#define FRF_NS_MICROWIRE (2)
#define FRF_RSVD (3)
/**
* @}
*/
/** @defgroup SPI_DMA_Control_definitions
* @{
*/
#define SSI_NODMA (0)
#define SSI_RXDMA_ENABLE (1)
#define SSI_TXDMA_ENABLE (2)
#define SSI_TRDMA_ENABLE (3)
/**
* @}
*/
/** @defgroup SPI_MW_Handshake_Enable_definitions
* @{
*/
#define MW_HANDSHAKE_DISABLE (0)
#define MW_HANDSHAKE_ENABLE (1)
/**
* @}
*/
/** @defgroup SPI_MW_Direction_definitions
* @{
*/
#define MW_DIRECTION_SLAVE_TO_MASTER (0)
#define MW_DIRECTION_MASTER_TO_SLAVE (1)
/**
* @}
*/
/** @defgroup SPI_MW_TMOD_definitions
* @{
*/
#define MW_TMOD_NONSEQUENTIAL (0)
#define MW_TMOD_SEQUENTIAL (1)
/**
* @}
*/
/** @defgroup SPI_FIFO_depth_definitions
* @{
*/
#define SSI_TX_FIFO_DEPTH (64)
#define SSI_RX_FIFO_DEPTH (64)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
/** @defgroup SPI_Exported_Normal_Functions SPI Exported Normal Functions
* @{
*/
_LONG_CALL_ void SSI_Cmd(SPI_TypeDef *spi_dev, u32 NewStaus);
_LONG_CALL_ void SSI_SetSclkPolarity(SPI_TypeDef *spi_dev, u32 SclkPolarity);
_LONG_CALL_ void SSI_SetSclkPhase(SPI_TypeDef *spi_dev, u32 SclkPhase);
_LONG_CALL_ void SSI_WriteData(SPI_TypeDef *spi_dev, u32 value);
_LONG_CALL_ VOID SSI_INTConfig(SPI_TypeDef* spi_dev, u32 SSI_IT, u32 newState);
_LONG_CALL_ void SSI_SetRxFifoLevel(SPI_TypeDef *spi_dev, u32 RxThresholdLevel);
_LONG_CALL_ void SSI_SetTxFifoLevel(SPI_TypeDef *spi_dev, u32 TxThresholdLevel);
_LONG_CALL_ void SSI_SetSlaveEnable(SPI_TypeDef *spi_dev, u32 SlaveIndex);
_LONG_CALL_ u32 SSI_Busy(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_Writeable(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_Readable(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetRxCount(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetTxCount(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetStatus(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetIsr(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_ReadData(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_ReceiveData(SPI_TypeDef *spi_dev, void* RxData, u32 Length);
_LONG_CALL_ u32 SSI_SendData(SPI_TypeDef *spi_dev, void* TxData, u32 Length, u32 Role);
_LONG_CALL_ u32 SSI_GetRawIsr(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetSlaveEnable(SPI_TypeDef *spi_dev);
_LONG_CALL_ u32 SSI_GetDataFrameSize(SPI_TypeDef *spi_dev);
_LONG_CALL_ void SSI_SetSampleDelay(SPI_TypeDef *spi_dev, u32 SampleDelay);
_LONG_CALL_ void SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct);
_LONG_CALL_ void SSI_StructInit(SSI_InitTypeDef* SSI_InitStruct);
_LONG_CALL_ void SSI_SetDataFrameSize(SPI_TypeDef *spi_dev, u32 DataFrameSize);
_LONG_CALL_ void SSI_SetBaud(SPI_TypeDef *SPIx, u32 BaudRate, u32 IpClk);
_LONG_CALL_ void SSI_SetIsrClean(SPI_TypeDef *spi_dev, u32 InterruptStatus);
_LONG_CALL_ void SSI_SetReadLen(SPI_TypeDef *spi_dev, u32 DataFrameNumber);
/**
* @}
*/
/** @defgroup SPI_Exported_DMA_Functions SPI Exported DMA Functions
* @{
*/
_LONG_CALL_ BOOL SSI_TXGDMA_Init(u32 Index, PGDMA_InitTypeDef GDMA_InitStruct, void *CallbackData,
IRQ_FUN CallbackFunc, u8 *pTxData, u32 Length);
_LONG_CALL_ BOOL SSI_RXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData,
IRQ_FUN CallbackFunc, u8 *pRxData, u32 Length);
_LONG_CALL_ void SSI_SetDmaEnable(SPI_TypeDef *spi_dev, u32 newState, u32 Mask);
_LONG_CALL_ void SSI_SetDmaLevel(SPI_TypeDef *spi_dev, u32 TxLeve, u32 RxLevel);
_LONG_CALL_ void SSI_SetBaudDiv(SPI_TypeDef *spi_dev, u32 ClockDivider);
_LONG_CALL_ void SSI_SetRole(SPI_TypeDef *spi_dev, u32 role);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup SPI_Register_Definitions SPI Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup SPI_CTRLR0
* @{
*****************************************************************************/
#define BIT_CTRLR0_DFS ((u32)0x0000000F)
#define BIT_CTRLR0_FRF ((u32)0x00000003 << 4)
#define BIT_CTRLR0_SCPH ((u32)0x00000001 << 6)
#define BIT_CTRLR0_SCPOL ((u32)0x00000001 << 7)
#define BIT_CTRLR0_TMOD ((u32)0x00000003 << 8)
#define BIT_CTRLR0_SLV_OE ((u32)0x00000001 << 10)
#define BIT_CTRLR0_SRL ((u32)0x00000001 << 11)
#define BIT_CTRLR0_CFS ((u32)0x0000000F << 12)
#define BIT_CTRLR0_TXBYTESWP ((u32)0x00000001 << 21)
#define BIT_CTRLR0_TXBITSWP ((u32)0x00000001 << 22)
#define BIT_CTRLR0_RXBYTESWP ((u32)0x00000001 << 23)
#define BIT_CTRLR0_RXBITSWP ((u32)0x00000001 << 24)
#define BIT_CTRLR0_SSTOGGLE ((u32)0x00000001 << 31)
/** @} */
/**************************************************************************//**
* @defgroup SPI_CTRLR1
* @{
*****************************************************************************/
#define BIT_CTRLR1_NDF ((u32)0x0000FFFF)
/** @} */
/**************************************************************************//**
* @defgroup SPI_SSIENR
* @{
*****************************************************************************/
#define BIT_SSIENR_SSI_EN ((u32)0x00000001)
/** @} */
/**************************************************************************//**
* @defgroup SPI_MWCR
* @{
*****************************************************************************/
#define BIT_MWCR_MWMOD ((u32)0x00000001)
#define BIT_MWCR_MDD ((u32)0x00000001 << 1)
#define BIT_MWCR_MHS ((u32)0x00000001 << 2)
/** @} */
/**************************************************************************//**
* @defgroup SPI_SER
* @{
*****************************************************************************/
#define BIT_SER_SER ((u32)0x0000FFFF)
/** @} */
/**************************************************************************//**
* @defgroup SPI_BAUDR
* @{
*****************************************************************************/
#define BIT_BAUDR_SCKDV ((u32)0x0000FFFF)
/** @} */
/**************************************************************************//**
* @defgroup SPI_TXFLTR
* @{
*****************************************************************************/
#define BIT_TXFTLR_TFT ((u32)0x0000003F)//(TX_ABW-1):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_RXFLTR
* @{
*****************************************************************************/
#define BIT_RXFTLR_RFT ((u32)0x0000003F) // (RX_ABW-1):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_TXFLR
* @{
*****************************************************************************/
#define BIT_MASK_TXFLR_TXTFL ((u32)0x0000007F) // (TX_ABW):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_RXFLR
* @{
*****************************************************************************/
#define BIT_MASK_RXFLR_RXTFL ((u32)0x0000007F) // (RX_ABW):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_SR
* @{
*****************************************************************************/
#define BIT_SR_BUSY ((u32)0x00000001)
#define BIT_SR_TFNF ((u32)0x00000001 << 1)
#define BIT_SR_TFE ((u32)0x00000001 << 2)
#define BIT_SR_RFNE ((u32)0x00000001 << 3)
#define BIT_SR_RFF ((u32)0x00000001 << 4)
#define BIT_SR_TXE ((u32)0x00000001 << 5)
#define BIT_SR_DCOL ((u32)0x00000001 << 6)
/** @} */
/**************************************************************************//**
* @defgroup SPI_IMR
* @{
*****************************************************************************/
#define BIT_IMR_TXEIM ((u32)0x00000001)
#define BIT_IMR_TXOIM ((u32)0x00000001 << 1)
#define BIT_IMR_RXUIM ((u32)0x00000001 << 2)
#define BIT_IMR_RXOIM ((u32)0x00000001 << 3)
#define BIT_IMR_RXFIM ((u32)0x00000001 << 4)
#define BIT_IMR_MSTIM ((u32)0x00000001 << 5) /*Master only*/
#define BIT_IMR_FAEIM ((u32)0x00000001 << 5) /*Slave only*/
#define BIT_IMR_TXUIM ((u32)0x00000001 << 6) /*Slave only*/
#define BIT_IMR_SSRIM ((u32)0x00000001 << 7) /*Slave only*/
/** @} */
/**************************************************************************//**
* @defgroup SPI_ISR
* @{
*****************************************************************************/
#define BIT_ISR_TXEIS ((u32)0x00000001)
#define BIT_ISR_TXOIS ((u32)0x00000001 << 1)
#define BIT_ISR_RXUIS ((u32)0x00000001 << 2)
#define BIT_ISR_RXOIS ((u32)0x00000001 << 3)
#define BIT_ISR_RXFIS ((u32)0x00000001 << 4)
#define BIT_ISR_MSTIS ((u32)0x00000001 << 5) /*Master only*/
#define BIT_ISR_FAEIS ((u32)0x00000001 << 5) /*Slave only*/
#define BIT_ISR_TXUIS ((u32)0x00000001 << 6) /*Slave only*/
#define BIT_ISR_SSRIS ((u32)0x00000001 << 7) /*Slave only*/
/** @} */
/**************************************************************************//**
* @defgroup SPI_RISR
* @{
*****************************************************************************/
#define BIT_RISR_TXEIR ((u32)0x00000001)
#define BIT_RISR_TXOIR ((u32)0x00000001 << 1)
#define BIT_RISR_RXUIR ((u32)0x00000001 << 2)
#define BIT_RISR_RXOIR ((u32)0x00000001 << 3)
#define BIT_RISR_RXFIR ((u32)0x00000001 << 4)
#define BIT_RISR_MSTIR ((u32)0x00000001 << 5) /*Master only*/
#define BIT_RISR_FAEIS ((u32)0x00000001 << 5) /*Slave only*/
#define BIT_RISR_TXUIS ((u32)0x00000001 << 6) /*Slave only*/
#define BIT_RISR_SSRIS ((u32)0x00000001 << 7) /*Slave only*/
/** @} */
/**************************************************************************//**
* @defgroup SPI_DMACR
* @{
*****************************************************************************/
#define BIT_SHIFT_DMACR_RDMAE ((u32)0x00000001)
#define BIT_SHIFT_DMACR_TDMAE ((u32)0x00000001 << 1)
/** @} */
/**************************************************************************//**
* @defgroup SPI_DMATDLR
* @{
*****************************************************************************/
#define BIT_DMATDLR_DMATDL ((u32)0x0000003F) // (TX_ABW-1):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_DMARDLR
* @{
*****************************************************************************/
#define BIT_DMARDLR_DMARDL ((u32)0x0000003F )// (RX_ABW-1):0
/** @} */
/**************************************************************************//**
* @defgroup SPI_DR
* @{
*****************************************************************************/
#define BIT_DR_DR ((u32)0x0000FFFF)
/** @} */
/**************************************************************************//**
* @defgroup SPI_RX_SAMPLE_DELAY
* @{
*****************************************************************************/
#define BIT_RX_SAMPLE_DELAY ((u32)0x000000FF)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
typedef struct
{
SPI_TypeDef* SPIx;
u32 Tx_HandshakeInterface;
u32 Rx_HandshakeInterface;
IRQn_Type IrqNum;
} SPI_DevTable;
extern const SPI_DevTable SPI_DEV_TABLE[2];
#define SPI_SLAVE_TXERR_WORK_AROUND 1
#endif //_RTL8710B_SPI_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_ssi.h
|
C
|
apache-2.0
| 25,533
|
#ifndef __INC_RTL8721D_SYS_ON_BIT_H
#define __INC_RTL8721D_SYS_ON_BIT_H
//================= SYSON Register Address Definition =====================//
#define REG_SYS_NORESET_FF 0x0138
#endif //__INC_RTL8721D_SYS_ON_BIT_H
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_sys_on.h
|
C
|
apache-2.0
| 228
|
/**
******************************************************************************
* @file rtl8721d_syscfg.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for SYSCFG firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_SYSCFG_H_
#define _RTL8710B_SYSCFG_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup SYSCFG
* @brief SYSCFG driver modules
* @{
*/
/** @addtogroup SYSCFG
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* Used for system, user can not used it if not needed.
*
*****************************************************************************************
* REG_SYS_SYSTEM_CFG0 Introduction
*****************************************************************************************
*
* BIT[31] Trapped PKG_ENG_SEL value 0: normal package; 1: engineering mode
* BIT[30] CHIP_EN PIN input value
* BIT[27:24] BD info
* BIT[16] 1: Test chip; 0:MP
* BIT[11:8] Vendor ID
* BIT[7:4] Chip version
* BIT[3:0] Vendor ID defined in RF
*
*****************************************************************************************
* REG_LP_SYSTEM_CFG1 Introduction
*****************************************************************************************
*
* BIT[31:28] is BIT_SYSCFG_TRP_ICFG, value is load from following trap pin:
* ICFG[0]/ICFG[1]/ICFG[2]/ICFG[3] when trap pin TSET_MODE_SEL = 1
* BIT[27] is BIT_SYSCFG_TRP_BOOT_SEL
* 0: boot normal, 1: uart flash download
* value load from trap pin UART_DOWNLOAD_IMAGE
* BIT[25] is BIT_SYSCFG_TRP_SPSLDO_SEL, Trapped Selection for SPS
* 0: SWR mode; 1: LDO mode
* load from trap pin SPS_LDO_SEL
* BIT[8] BIT_SYS_XCLK_VLD Xtal Clock Stable, 1: Clock Stable
* BIT[0] BIT_SYSCFG_ALDN_STS 1: SYS CFG autoload done; 0; SYSCFG autoload not ready
*
*****************************************************************************************
* REG_LP_SYSTEM_CFG2 Introduction
*****************************************************************************************
*
* BIT[7:0] ROM Information
*
*
*****************************************************************************************
* trap pins
*****************************************************************************************
*
* GPIOA_0:
* TEST_MODE_SEL
* default PD
*
* GPIOA_3:
* SPS_LDO_SEL
* default PU, internal PU
* 0: SWR 1: LDO
* load to 0x1F4[25]
*
* GPIOA_30:
* UART_DOWNLOAD_IMAGE
* default PU
* load to 0x1F4[27]
*
*****************************************************************************************
* @endverbatim
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
/** @defgroup SYSCFG_Bounding_Option_definitions
* @{
*/
#define SYSCFG_BD_QFN32 ((u32)0x000000000)
#define SYSCFG_BD_QFN48_MCM_8MBFlash ((u32)0x000000001)
#define SYSCFG_BD_QFN48 ((u32)0x000000002)
#define SYSCFG_BD_QFN48_NEW ((u32)0x000000000)
#define SYSCFG_BD_QFN68 ((u32)0x000000007)
#define SYSCFG_BD_QFN68_NEW ((u32)0x000000005)
#define SYSCFG_BD_TFBGA_MCM_8761A ((u32)0x000000004)
/**
* @}
*/
/** @defgroup SYSCFG_CUT_Version_definitions
* @{
*/
#define SYSCFG_CUT_VERSION_A 0
#define SYSCFG_CUT_VERSION_B 1
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Functions SYSCFG Exported Functions
* @{
*/
_LONG_CALL_ u32 SYSCFG_GetChipInfo(void);
//_LONG_CALL_ u32 SYSCFG_CUTVersion(void);
_LONG_CALL_ u32 SYSCFG_TRP_LDOMode(void);
_LONG_CALL_ u32 SYSCFG_TRP_UARTImage(void);
_LONG_CALL_ u32 SYSCFG_TRP_ICFG(void);
_LONG_CALL_ u32 SYSCFG_ROMINFO_Get(void);
_LONG_CALL_ void SYSCFG_ROMINFO_Set(void);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
static inline u32
SYSCFG_CUTVersion(void)
{
u32 tmp = (HAL_READ32(0x48000000, 0x000C) >> 8) & 0xF; //get chip version from REG_AON_BOOT_REASON1
if(0 == tmp) {
return SYSCFG_CUT_VERSION_A; /*A-Cut*/
} else {
tmp = HAL_READ32(0x48000000, 0x03F0) & 0xF; //confirm chip version according to REG_LP_SYSTEM_CFG0
if(0 == tmp)
return SYSCFG_CUT_VERSION_B;
else
return tmp;
}
}
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other definations --------------------------------------------------------*/
/******************* Macro definition for TRP_ICFG ********************/
#define SYSCFG_TRP_ICFG_STOP_IN_ROMBOOT 2
#define SYSCFG_TRP_ICFG_FLASH_LOCATION 3 /* Ameba1 used, AmebaZ not use */
#endif //_RTL8710B_SYSCFG_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_syscfg.h
|
C
|
apache-2.0
| 5,494
|
/**************************************************************************//**
* @file system_ARMCM3.h
* @brief CMSIS Device System Header File for
* ARMCM3 Device Series
* @version V1.08
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef _SYSTEM_8195A_H
#define _SYSTEM_8195A_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
extern u32 SystemGetCpuClk(void);
extern void SystemSetCpuClk(u8 CpuClk);
/**
* @brief Generate random seed
* @param none
* @return value: random seed value
*/
u32 Gen_RandomSeed(VOID);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_8195A_H */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_system.h
|
C
|
apache-2.0
| 2,840
|
/**
******************************************************************************
* @file rtl8721d_tim.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the Timer firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_TIMER_H_
#define _RTL8721D_TIMER_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup Timer
* @brief Timer driver modules
* @{
*/
/** @addtogroup Timer
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* TIM0/TIM1/TIM2/TIM3: used as generic timers for time-base generation
* - Base Address: TIMM00/TIMM01/TIMM02/TIMM03/TIM0/TIM1/TIM2/TIM3
* - Clock Source: 32kHz
* - Resolution: 32bit
* - Count Mode: Upcounting
* - Interrupt Generation
* - Support Upcounting mode
* TIM4:
* - Base Address: TIMM04/TIM4
* - Channels: 1
* - Clock Source: XTAL, normally is 40MHz
* - Resolution: 16bit
* - Prescaler: 8bit
* - Count Mode: Upcounting
* - Input Pin: 1 input capture
* - Interrupt Generation
* - Support Upcounting mode/Statistic Pulse Width mode/Statistic Pulse Number mode
* TIM5:
* - Base Address: TIMM05/TIM5
* - Channels: 6(KM0)/18(KM4)
* - Clock Source: XTAL, normally is 40MHz
* - Resolution: 16bit
* - Prescaler: 8bit
* - Count Mode: Upcounting
* - Interrup Generation
* - Input Pin: 1 input capture
* - Ouput Pin: 6(KM0)/18(KM4) PWM out
* - Support Upcounting mode/Input capture mode/PWM mode/One Pulse mode
*
*****************************************************************************************
* Sys Timer
*****************************************************************************************
* - TIMM00 is used as systimer, so TIMM00 can not be used for other purpose
*
*****************************************************************************************
* Upcounting mode
*****************************************************************************************
* TIMM00~5/TIM0~5 support
* The counter counts from 0 to the auto-reload value (content of the TIMx_ARR register),
* then restarts from 0 and generates a counter overflow interrupt.
*
*****************************************************************************************
* Statistic Pulse Width mode
*****************************************************************************************
* Only TIMM04/TIM4 support
* TIMM04/TIM4 can statistic the width of active level of TRGI. When the TRGI is transferred from
* inactive level to active level, the counter is enabled automatically and counter starts
* from 0. When the TRGI is transferred from active level to inactive level , the counter
* is disabled automatically, the current counter value will be copied to CCR0 field of
* TIMx_CCR0, the CCxIF will be set and an interrupt can be sent if they are enabled.
*
*****************************************************************************************
* Statistic Pulse Number mode
*****************************************************************************************
* Only TIMM04/TIM4 support
* TIM4 can statistic the number of active edge of TRGI in the given period. When the
* counter overflow, the number will be copied to CCR0 field of TIMx_CCR0, the CCxIF will
* be set and an interrupt can be sent if they are enabled
*
*****************************************************************************************
* Input capture mode
*****************************************************************************************
* Only TIMM05/TIM5 supports
* In input capture mode, the CCRx field of TIMx_CCRx are used to latch the value of the
* counter after a transition detected by the TRGI signal. When a capture occurs, the
* corresponding CCXIF flag (TIMx_SR register) is set and an interrupt can be sent if they are enabled.
*
*****************************************************************************************
* PWM mode
*****************************************************************************************
* Only TIMM05/TIM5 supports
* Pulse Width Modulation mode allows you to generate a signal with a frequency determined
* by the value of the TIMx_ARR register and a duty cycle determined by the value of the
* CCRx field of TIMx_CCRx register.
* Period = (ARR + 1)*Tcnt, Duty cycle = CCRx*Tcnt/Period, where Tcnt = Txtal *(PSC+1).
*
*****************************************************************************************
* One Pulse mode
*****************************************************************************************
* Only TIM5 supports
* This mode allows the counter to be started in response to a stimulus and to generate
* a pulse with a programmable length after a programmable delay. Starting the counter can
* be controlled through the active edge of TRGI. Generating the waveform can be done in PWM
* mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR register. This makes
* the counter stop automatically at the next update event.
*
* NOTICE: you shoud pull up/down the pwm pin (PAD_PullCtrl) when you use one pulse mode based on polarity
*
*****************************************************************************************
* How to use Base Timer
*****************************************************************************************
* To use the Timer in Timing(Time base) mode, the following steps are mandatory:
*
* 1. Enable TIM clock :
* RCC_PeriphClockCmd(APBPeriph_GTIMER, APBPeriph_GTIMER_CLOCK, ENABLE)
*
* 2. Fill the TIM_InitStruct with default parameters using:
* RTIM_TimeBaseStructInit(&TIM_InitStruct)
* or setting the desired parameters manually.
*
* 3. Configure the Time Base unit with the corresponding configurations, register TimerIRQHandler
* and enable the NVIC if you need to generate the update interrupt.
* RTIM_TimeBaseInit(TIMx, &TIM_InitStruct, IrqNum, UserCB, UserCBData)
*
* 4. Enable the corresponding interrupt using :
* RTIM_INTConfig(TIMx, TIM_IT_Update, ENABLE)
*
* 5. Enable the TIM counter.
* RTIM_Cmd(TIMx, ENABLE)
*
* Note1: All other functions can be used separately to modify, if needed,
* a specific feature of the Timer.
*
*****************************************************************************************
* How to use Timer in Capture Compare Mode
*****************************************************************************************
* To use the Timer in CC mode, the following steps are mandatory:
*
* 1. Enable TIM clock :
* RCC_PeriphClockCmd(APBPeriph_GTIMER, APBPeriph_GTIMER_CLOCK, ENABLE)
*
* 2. Configure the TIM pinmux:
* Pinmux_Config(PinName, PinFunc)
*
* 3. Configure the Time base unit as described in the first part of this driver if needed,
* else the Timer will run with the default configuration:
* - Autoreload value = 0xFFFF
* - Prescaler value = 0x0000
*
* 4. Fill the TIM_CCInitStruct with the desired parameters including:
* - The TIM Output Compare mode: TIM_CCMode
* - TIM Output Compare Pulse value: TIM_OCMPulse
* - TIM Output Compare Polarity : TIM_CCPolarity
* - TIM Output Compare value update protection: TIM_OCProtection
*
* 5. Configure the desired channel with the corresponding configuration
* RTIM_CCxInit(TIMx, &TIM_CCInitStruct, TIM_Channel)
*
* 6. Enable corresponding TIM channel.
* RTIM_CCxCmd(TIMx, TIM_Channel, TIM_CCx_Enable)
*
* 7. Enable the TIM counter.
* RTIM_Cmd(TIMx, ENABLE)
*
* Note1: All other functions can be used separately to modify, if needed,
* a specific feature of the Timer.
*
* Note2: In case of PWM mode, the TIMx peripheral Preload register on CCRx(TIM_OCProtection)
* should be enabled.
*
* Note3: If the corresponding interrupt is needed, the user should:
* 1. Enable the NVIC to use the TIM interrupts.
* 2. Enable the corresponding interrupt using the function
* RTIM_ITConfig(TIMx, TIM_IT_CCx, ENABLE)
*
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIM_Exported_Types TIM Exported Types
* @{
*/
/**
* @brief TIM Basic Init structure definition
*/
typedef struct {
u32 TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between 0x00 and 0xFF, basic timer dont care */
u32 TIM_Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter is 16bits for TIM4-5, and 32bits for TIM0-TIM3
you can get it from SourceClock & TIM_Prescaler */
u32 TIM_UpdateEvent; /*!< Specifies whether or not to enable update event(UEV).
This parameter can be ENABLE or DISABLE. ENABLE means UEV Enable, DISABLE means UEV Disable*/
u32 TIM_UpdateSource; /*!< Specifies the update request source. This parameter can be
TIM_UpdateSource_Overflow or TIM_UpdateSource_Global.
TIM_UpdateSource_Overflow means counter overflow generates an update event(UEV).
TIM_UpdateSource_Global means both counter overflow and setting the UG bit can generate UEV.*/
u32 TIM_ARRProtection; /*!< DISABLE or ENABLE, when ENABLE: period will update when cnt = 0(counter overflow, an UEV happens),
or period will update immediatly */
u8 TIM_Idx; /*!< 0~5 */
} RTIM_TimeBaseInitTypeDef;
/**
* @brief TIM Output Compare Init structure definition
*/
typedef struct
{
u32 TIM_CCMode; /*!< Specifies the TIM5 mode. This parameter can be a value of TIM_CCMode_PWM or TIM_CCMode_Inputcapture */
u32 TIM_CCPolarity; /*!< Specifies the polarity. This parameter can be TIM_CCPolarity_High/TIM_CCPolarity_Low.
If CCx channel is configured as output:
TIM_CCPolarity_High means OCx active high.
TIM_CCPolarity_Low means OCx active low.
If CCx channel is configured as input:
TIM_CCPolarity_High means positive edge of TRGI is active for capture.
TIM_CCPolarity_Low means negative edge of TRGI is active for capture. */
u32 TIM_OCProtection; /*!< Output Compare value update protection. TIM_OCPreload_Enable/TIM_OCPreload_Disable.
TIM_OCPreload_Enable means duty cycle will update when UEV happens if write to CCRx field in TIMx_CCRX.
TIM_OCPreload_Disable means duty cycle will update immediately if write to CCRx field in TIMx_CCRX.*/
u32 TIM_OCPulse; /*!< Specifies the output pulse value to be loaded into the CCRx Register, which decides the duty cycle.
This parameter can be a number between 0x0000 and 0xFFFF */
u32 TIM_ICPulseMode; /*!< Specifies the TIM4 mode, TIM_CCMode_PulseWidth or TIM_CCMode_PulseNumber */
} TIM_CCInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIM_Exported_constants TIM Exported constants
* @{
*/
/** @defgroup TIM_Type_definitions
* @{
*/
#define IS_TIM_ALL_TIM(PERIPH) (((PERIPH) == TIM0) || \
((PERIPH) == TIM1) || \
((PERIPH) == TIM2) || \
((PERIPH) == TIM3) || \
((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIMM00) || \
((PERIPH) == TIMM01) || \
((PERIPH) == TIMM02) || \
((PERIPH) == TIMM03) || \
((PERIPH) == TIMM04) || \
((PERIPH) == TIMM05))
#define IS_TIM_ONE_PULSE_TIM(PERIPH) ((PERIPH) == TIM5 || (PERIPH) == TIMM05)
#define IS_TIM_CCM_TIM(PERIPH) (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIMM04) || \
((PERIPH) == TIMM05))
#define IS_TIM_PWM_TIM(PERIPH) ((PERIPH) == TIM5 || (PERIPH) == TIMM05)
#define IS_TIM_INPULSE_TIM(PERIPH) ((PERIPH) == TIM4 || (PERIPH) == TIMM04)
#define IS_TIM_40M_TIM(PERIPH) (((PERIPH) == TIM4) || \
((PERIPH) == TIM5) || \
((PERIPH) == TIMM04) || \
((PERIPH) == TIMM05))
/**
* @}
*/
/** @defgroup TIM_Channel_definitions
* @note TIMM0x: 0~5, TIMx: 0~17
* @{
*/
#define TIM_Channel_0 ((u16)0x0000)
#define TIM_Channel_1 ((u16)0x0001)
#define TIM_Channel_2 ((u16)0x0002)
#define TIM_Channel_3 ((u16)0x0003)
#define TIM_Channel_4 ((u16)0x0004)
#define TIM_Channel_5 ((u16)0x0005)
#define TIM_Channel_6 ((u16)0x0006)
#define TIM_Channel_7 ((u16)0x0007)
#define TIM_Channel_8 ((u16)0x0008)
#define TIM_Channel_9 ((u16)0x0009)
#define TIM_Channel_10 ((u16)0x000a)
#define TIM_Channel_11 ((u16)0x000b)
#define TIM_Channel_12 ((u16)0x000c)
#define TIM_Channel_13 ((u16)0x000d)
#define TIM_Channel_14 ((u16)0x000e)
#define TIM_Channel_15 ((u16)0x000f)
#define TIM_Channel_16 ((u16)0x0010)
#define TIM_Channel_17 ((u16)0x0011)
#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_0) || \
((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4) || \
((CHANNEL) == TIM_Channel_5) || \
((CHANNEL) == TIM_Channel_6) || \
((CHANNEL) == TIM_Channel_7) || \
((CHANNEL) == TIM_Channel_8) || \
((CHANNEL) == TIM_Channel_9) || \
((CHANNEL) == TIM_Channel_10) || \
((CHANNEL) == TIM_Channel_11) || \
((CHANNEL) == TIM_Channel_12) || \
((CHANNEL) == TIM_Channel_13) || \
((CHANNEL) == TIM_Channel_14) || \
((CHANNEL) == TIM_Channel_15) || \
((CHANNEL) == TIM_Channel_16) || \
((CHANNEL) == TIM_Channel_17))
/**
* @}
*/
/** @defgroup TIMx_Prescaler_definitons
* @{
*/
#define IS_TIM_PSC(VAL) (VAL <= 0xFF)
/**
* @}
*/
/** @defgroup TIMx_Control_Bit_definitions
* @{
*/
#define TIM_OPMode_ETP_positive ((u32)0x00000000)
#define TIM_OPMode_ETP_negative ((u32)0x00000100)
#define IS_TIM_OPM_ETP_MODE(MODE) (((MODE) == TIM_OPMode_ETP_positive) || \
((MODE) == TIM_OPMode_ETP_negative))
#define TIM_OPMode_Single ((u32)0x00000008)
#define TIM_OPMode_Repetitive ((u32)0x00000000) /* repeative is PWM mode */
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
((MODE) == TIM_OPMode_Repetitive))
#define TIM_UpdateSource_Global ((u32)0x00000000) /*!< Source of update is the counter overflow or the setting of UG bit. */
#define TIM_UpdateSource_Overflow ((u32)0x00000004) /*!< Source of update is counter overflow. */
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
((SOURCE) == TIM_UpdateSource_Overflow))
/**
* @}
*/
/** @defgroup TIMx_Interrupt_Enable_definitions
* @{
*/
#define TIM_IT_Update ((u32)0x00000001)
#define TIM_IT_CC0 ((u32)0x00000002)
#define TIM_IT_CC1 ((u32)0x00000004)
#define TIM_IT_CC2 ((u32)0x00000008)
#define TIM_IT_CC3 ((u32)0x00000010)
#define TIM_IT_CC4 ((u32)0x00000020)
#define TIM_IT_CC5 ((u32)0x00000040)
#define TIM_IT_CC6 ((u32)0x00000080)
#define TIM_IT_CC7 ((u32)0x00000100)
#define TIM_IT_CC8 ((u32)0x00000200)
#define TIM_IT_CC9 ((u32)0x00000400)
#define TIM_IT_CC10 ((u32)0x00000800)
#define TIM_IT_CC11 ((u32)0x00001000)
#define TIM_IT_CC12 ((u32)0x00002000)
#define TIM_IT_CC13 ((u32)0x00004000)
#define TIM_IT_CC14 ((u32)0x00008000)
#define TIM_IT_CC15 ((u32)0x00010000)
#define TIM_IT_CC16 ((u32)0x00020000)
#define TIM_IT_CC17 ((u32)0x00040000)
#define IS_TIM_IT(IT) ((((IT) & (u32)0xFFF80000) == 0x0000) && (((IT) & (u32)0x7FFFF) != 0x0000))
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC0) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_CC5) || \
((IT) == TIM_IT_CC6) || \
((IT) == TIM_IT_CC7) || \
((IT) == TIM_IT_CC8) || \
((IT) == TIM_IT_CC9) || \
((IT) == TIM_IT_CC10) || \
((IT) == TIM_IT_CC11) || \
((IT) == TIM_IT_CC12) || \
((IT) == TIM_IT_CC13) || \
((IT) == TIM_IT_CC14) || \
((IT) == TIM_IT_CC15) || \
((IT) == TIM_IT_CC16) || \
((IT) == TIM_IT_CC17))
/**
* @}
*/
/** @defgroup TIMx_PSC_Reload_Mode_definitons
* @{
*/
#define TIM_PSCReloadMode_Update ((u32)0x00000000)
#define TIM_PSCReloadMode_Immediate ((u32)0x00000001)
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
((RELOAD) == TIM_PSCReloadMode_Immediate))
/**
* @}
*/
/** @defgroup TIMx_Event_Generation_definitons
* @{
*/
#define TIM_EventSource_Update ((u32)0x00000001)
#define TIM_EventSource_CC0 ((u32)0x00000002)
#define TIM_EventSource_CC1 ((u32)0x00000004)
#define TIM_EventSource_CC2 ((u32)0x00000008)
#define TIM_EventSource_CC3 ((u32)0x00000010)
#define TIM_EventSource_CC4 ((u32)0x00000020)
#define TIM_EventSource_CC5 ((u32)0x00000040)
#define TIM_EventSource_CC6 ((u32)0x00000080)
#define TIM_EventSource_CC7 ((u32)0x00000100)
#define TIM_EventSource_CC8 ((u32)0x00000200)
#define TIM_EventSource_CC9 ((u32)0x00000400)
#define TIM_EventSource_CC10 ((u32)0x00000800)
#define TIM_EventSource_CC11 ((u32)0x00001000)
#define TIM_EventSource_CC12 ((u32)0x00002000)
#define TIM_EventSource_CC13 ((u32)0x00004000)
#define TIM_EventSource_CC14 ((u32)0x00008000)
#define TIM_EventSource_CC15 ((u32)0x00010000)
#define TIM_EventSource_CC16 ((u32)0x00020000)
#define TIM_EventSource_CC17 ((u32)0x00040000)
#define IS_LP_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF80) == 0x0000) && \
(((SOURCE) & 0x7F) != 0x0000))
#define IS_HP_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFF80000) == 0x0000) && \
(((SOURCE) & 0x7FFFF) != 0x0000))
/**
* @}
*/
/** @defgroup TIMx_Capture_Compare_definitions
* @{
*/
#define TIM_CCx_Enable ((u32)0x01000000)
#define TIM_CCx_Disable ((u32)0x00000000)
#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || ((CCX) == TIM_CCx_Disable))
#define TIM_OCPreload_Enable ((u32)0x02000000)
#define TIM_OCPreload_Disable ((u32)0x00000000)
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
((STATE) == TIM_OCPreload_Disable))
#define TIM_CCPolarity_High ((u32)0x00000000) /*!< if input is set : Positive edge of TRGI is active for capture */
#define TIM_CCPolarity_Low ((u32)0x04000000) /*!< if input is set : negative edge of TRGI is active for capture */
#define IS_TIM_CC_POLARITY(POLARITY) (((POLARITY) == TIM_CCPolarity_High) || \
((POLARITY) == TIM_CCPolarity_Low))
/* TIM5 PWM or Inputcapture mode */
#define TIM_CCMode_PWM ((u32)0x00000000)
#define TIM_CCMode_Inputcapture ((u32)0x08000000)
#define IS_TIM_CC_MODE(MODE) (((MODE) == TIM_CCMode_PWM) || \
((MODE) == TIM_CCMode_Inputcapture))
/* TIM4 pulse mode */
#define TIM_CCMode_PulseWidth ((u32)0x00000000)
#define TIM_CCMode_PulseNumber ((u32)0x10000000)
#define IS_TIM_CC_PULSEMODE(MODE) (((MODE) == TIM_CCMode_PulseWidth) || \
((MODE) == TIM_CCMode_PulseNumber))
#define TIM_CCMode_CCR ((u32)0x0000FFFF)
#define IS_TIM_CC_PULSEWIDTH(Compare) ((Compare) <= TIM_CCMode_CCR)
/**
* @}
*/
/**
* @}
*/
/** @defgroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
/** @defgroup TimeBase_Management_Functions TimeBase Management Functions
* @{
*/
_LONG_CALL_ void RTIM_TimeBaseStructInit(RTIM_TimeBaseInitTypeDef* TIM_InitStruct);
_LONG_CALL_ void RTIM_TimeBaseInit(RTIM_TypeDef* TIMx, RTIM_TimeBaseInitTypeDef* TIM_InitStruct, IRQn_Type IrqNum, IRQ_FUN UserCB, u32 UserCBData);
_LONG_CALL_ void RTIM_Cmd(RTIM_TypeDef* TIMx, u32 NewState);
_LONG_CALL_ void RTIM_DeInit(RTIM_TypeDef* TIMx);
_LONG_CALL_ u32 RTIM_GetCount(RTIM_TypeDef* TIMx);
_LONG_CALL_ void RTIM_UpdateDisableConfig(RTIM_TypeDef* TIMx, u32 NewState);
_LONG_CALL_ void RTIM_ARRPreloadConfig(RTIM_TypeDef* TIMx, u32 NewState);
_LONG_CALL_ void RTIM_UpdateRequestConfig(RTIM_TypeDef* TIMx, u32 TIM_UpdateSource);
_LONG_CALL_ void RTIM_PrescalerConfig(RTIM_TypeDef* TIMx, u32 Prescaler, u32 TIM_PSCReloadMode);
_LONG_CALL_ void RTIM_GenerateEvent(RTIM_TypeDef* TIMx, u32 TIM_EventSource);
_LONG_CALL_ void RTIM_ChangePeriod(RTIM_TypeDef* TIMx, u32 Autoreload);
_LONG_CALL_ void RTIM_ChangePeriodImmediate(RTIM_TypeDef* TIMx, u32 Autoreload);
_LONG_CALL_ void RTIM_Reset(RTIM_TypeDef* TIMx);
/**
* @}
*/
/** @defgroup Capture_Compare_Management_Functions Capture Compare Management Functions
* @{
*/
_LONG_CALL_ void RTIM_CCStructInit(TIM_CCInitTypeDef* TIM_CCInitStruct);
_LONG_CALL_ void RTIM_CCxInit(RTIM_TypeDef* TIMx, TIM_CCInitTypeDef* TIM_CCInitStruct, u16 TIM_Channel);
_LONG_CALL_ void RTIM_CCRxMode(RTIM_TypeDef* TIMx, u16 TIM_Channel, u32 TIM_CCMode);
_LONG_CALL_ void RTIM_CCRxSet(RTIM_TypeDef* TIMx, u32 Compare, u16 TIM_Channel);
_LONG_CALL_ u32 RTIM_CCRxGet(RTIM_TypeDef* TIMx, u16 TIM_Channel);
_LONG_CALL_ void RTIM_OCxPreloadConfig(RTIM_TypeDef* TIMx, u32 TIM_OCProtection, u16 TIM_Channel);
_LONG_CALL_ void RTIM_CCxPolarityConfig(RTIM_TypeDef* TIMx, u32 TIM_OCPolarity, u16 TIM_Channel);
_LONG_CALL_ void RTIM_CCxCmd(RTIM_TypeDef* TIMx, u16 TIM_Channel, u32 TIM_CCx);
_LONG_CALL_ void RTIM_SetOnePulseOutputMode(RTIM_TypeDef* TIMx, u32 TIM_OPMode, u32 TrigerPolarity);
/**
* @}
*/
/** @defgroup Interrupt_Management_Functions Interrupt Management Functions
* @{
*/
_LONG_CALL_ void RTIM_INTConfig(RTIM_TypeDef* TIMx, u32 TIM_IT, u32 NewState);
_LONG_CALL_ void RTIM_INTClear(RTIM_TypeDef* TIMx);
_LONG_CALL_ void RTIM_INTClearPendingBit(RTIM_TypeDef* TIMx, u16 TIM_IT);
_LONG_CALL_ u32 RTIM_GetFlagStatus(RTIM_TypeDef* TIMx, u32 TIM_FLAG);
_LONG_CALL_ u32 RTIM_GetINTStatus(RTIM_TypeDef* TIMx, u32 TIM_IT);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup TIM_Register_Definitions TIM Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup TIM_EN
* @{
*****************************************************************************/
#define TIM_CR_CNT_START ((u32)0x00000001) /*!<Counter start */
#define TIM_CR_CNT_STOP ((u32)0x00000002) /*!<Counter stop */
#define TIM_CR_CNT_RUN ((u32)0x00000100) /*!<Counter run status. polling bit */
#define TIM_CR_CNT_STS ((u32)0x00010000) /*!<Counter working status, polling bit */
/** @} */
/**************************************************************************//**
* @defgroup TIM_CR
* @{
*****************************************************************************/
#define TIM_CR_UDIS ((u32)0x00000002) /*!<Update disable */
#define TIM_CR_URS ((u32)0x00000004) /*!<Update request source */
#define TIM_CR_OPM ((u32)0x00000008) /*!<One pulse mode */
#define TIM_CR_ARPE ((u32)0x00000010) /*!<Auto-reload preload enable */
#define TIM_CR_ETP ((u32)0x00000100) /*!<External trigger polarity for one pulse mode (TRGI). */
/** @} */
/**************************************************************************//**
* @defgroup TIM_DIER
* @{
*****************************************************************************/
/* Interrupt EN */
#define TIM_DIER_UIE ((u32)0x00000001) /*!<Update interrupt enable */
#define TIM_DIER_CC0IE ((u32)0x00000002) /*!<Capture/Compare 0 interrupt enable */
#define TIM_DIER_CC1IE ((u32)0x00000004) /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE ((u32)0x00000008) /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE ((u32)0x00000010) /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE ((u32)0x00000020) /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_CC5IE ((u32)0x00000040) /*!<Capture/Compare 5 interrupt enable */
#define TIM_DIER_CC6IE ((u32)0x00000080) /*!<Capture/Compare 6 interrupt enable */
#define TIM_DIER_CC7IE ((u32)0x00000100) /*!<Capture/Compare 7 interrupt enable */
#define TIM_DIER_CC8IE ((u32)0x00000200) /*!<Capture/Compare 8 interrupt enable */
#define TIM_DIER_CC9IE ((u32)0x00000400) /*!<Capture/Compare 9 interrupt enable */
#define TIM_DIER_CC10IE ((u32)0x00000800) /*!<Capture/Compare 10 interrupt enable */
#define TIM_DIER_CC11IE ((u32)0x00001000) /*!<Capture/Compare 11 interrupt enable */
#define TIM_DIER_CC12IE ((u32)0x00002000) /*!<Capture/Compare 12 interrupt enable */
#define TIM_DIER_CC13IE ((u32)0x00004000) /*!<Capture/Compare 13 interrupt enable */
#define TIM_DIER_CC14IE ((u32)0x00008000) /*!<Capture/Compare 14 interrupt enable */
#define TIM_DIER_CC15IE ((u32)0x00010000) /*!<Capture/Compare 15 interrupt enable */
#define TIM_DIER_CC16IE ((u32)0x00020000) /*!<Capture/Compare 16 interrupt enable */
#define TIM_DIER_CC17IE ((u32)0x00040000) /*!<Capture/Compare 17 interrupt enable */
/** @} */
/**************************************************************************//**
* @defgroup TIM_SR
* @{
*****************************************************************************/
#define TIM_SR_UIF ((u32)0x00000001) /*!<Update interrupt Flag */
#define TIM_SR_CC0IF ((u32)0x00000002) /*!<Capture/Compare 0 interrupt Flag */
#define TIM_SR_CC1IF ((u32)0x00000004) /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF ((u32)0x00000008) /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF ((u32)0x00000010) /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF ((u32)0x00000020) /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_CC5IF ((u32)0x00000040) /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF ((u32)0x00000080) /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_CC7IF ((u32)0x00000100) /*!<Capture/Compare 7 interrupt Flag */
#define TIM_SR_CC8IF ((u32)0x00000200) /*!<Capture/Compare 8 interrupt Flag */
#define TIM_SR_CC9IF ((u32)0x00000400) /*!<Capture/Compare 9 interrupt Flag */
#define TIM_SR_CC10IF ((u32)0x00000800) /*!<Capture/Compare 10 interrupt Flag */
#define TIM_SR_CC11IF ((u32)0x00001000) /*!<Capture/Compare 11 interrupt Flag */
#define TIM_SR_CC12IF ((u32)0x00002000) /*!<Capture/Compare 12 interrupt Flag */
#define TIM_SR_CC13IF ((u32)0x00004000) /*!<Capture/Compare 13 interrupt Flag */
#define TIM_SR_CC14IF ((u32)0x00008000) /*!<Capture/Compare 14 interrupt Flag */
#define TIM_SR_CC15IF ((u32)0x00010000) /*!<Capture/Compare 15 interrupt Flag */
#define TIM_SR_CC16IF ((u32)0x00020000) /*!<Capture/Compare 16 interrupt Flag */
#define TIM_SR_CC17IF ((u32)0x00040000) /*!<Capture/Compare 17 interrupt Flag */
#define TIM_SR_UG_DONE ((u32)0x80000000) /*!<UG operation status for TIMx_EGR UG bit, polling bit */
/** @} */
/**************************************************************************//**
* @defgroup TIM_EGR
* @{
*****************************************************************************/
#define TIM_EGR_UG ((u32)0x00000001) /*!<Update Generation */
#define TIM_EGR_CC0G ((u32)0x00000002) /*!<Capture/Compare 0 Generation */
#define TIM_EGR_CC1G ((u32)0x00000004) /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G ((u32)0x00000008) /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G ((u32)0x00000010) /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G ((u32)0x00000020) /*!<Capture/Compare 4 Generation */
#define TIM_EGR_CC5G ((u32)0x00000040) /*!<Capture/Compare 5 Generation */
#define TIM_EGR_CC6G ((u32)0x00000080) /*!<Capture/Compare 6 Generation */
#define TIM_EGR_CC7G ((u32)0x00000100) /*!<Capture/Compare 7 Generation */
#define TIM_EGR_CC8G ((u32)0x00000200) /*!<Capture/Compare 8 Generation */
#define TIM_EGR_CC9G ((u32)0x00000400) /*!<Capture/Compare 9 Generation */
#define TIM_EGR_CC10G ((u32)0x00000800) /*!<Capture/Compare 10 Generation */
#define TIM_EGR_CC11G ((u32)0x00001000) /*!<Capture/Compare 11 Generation */
#define TIM_EGR_CC12G ((u32)0x00002000) /*!<Capture/Compare 12 Generation */
#define TIM_EGR_CC13G ((u32)0x00004000) /*!<Capture/Compare 13 Generation */
#define TIM_EGR_CC14G ((u32)0x00008000) /*!<Capture/Compare 14 Generation */
#define TIM_EGR_CC15G ((u32)0x00010000) /*!<Capture/Compare 15 Generation */
#define TIM_EGR_CC16G ((u32)0x00020000) /*!<Capture/Compare 16 Generation */
#define TIM_EGR_CC17G ((u32)0x00040000) /*!<Capture/Compare 17 Generation */
/** @} */
/**************************************************************************//**
* @defgroup TIM_CCMR
* @{
*****************************************************************************/
#define TIM_CCER_CCxE ((u32)0x01 << 24) /*!<Capture/Compare x input/output enable */
#define TIM_OCER_CCxPE ((u32)0x02 << 24) /*!<Output Compare x Preload enable */
#define TIM_CCER_CCxP ((u32)0x04 << 24) /*!<Capture/Compare x input/output Polarity */
#define TIM_CCER_CCxM ((u32)0x08 << 24) /*!<CCx working mode input or output mode */
#define TIM_ICER_CCxPULSE_MODE ((u32)0x10 << 24) /*!<CCx input pulse mode: width or num, just CC1 valid */
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
typedef struct
{
u32 PWM_CHANNEL;
u32 KM0_CHAN_STATUS;
u32 KM4_CHAN_STATUS;
} PWMCHANCFG_TypeDef;
extern PWMCHANCFG_TypeDef pwmchannel_config[];
extern int TIMx_irq[6];
extern int TIMx_irq_LP[6];
extern RTIM_TypeDef* TIMx[6];
extern RTIM_TypeDef* TIMx_LP[6];
extern u32 TIM_IT_CCx_LP[6];
extern u32 TIM_IT_CCx[18];
#define TIMER_TICK_US 31
#define TIMER_TICK_US_X4 (4*1000000/32000) //32k clock, 31.25us every timer_tick
#endif //_RTL8721D_TIMER_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_tim.h
|
C
|
apache-2.0
| 33,568
|
/**
******************************************************************************
* @file rtl8721d_trustzone.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the definations of trustzone.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _TRUSTZONE_H_
#define _TRUSTZONE_H_
typedef struct
{
u32 Start;
u32 End;
u32 NSC;
} TZ_CFG_TypeDef;
/*
* <q> Enable SAU
* <i> Value for SAU->CTRL register bit ENABLE
*/
#define SAU_INIT_CTRL_ENABLE 1
/*
* <o> When SAU is disabled
* <0=> All Memory is Secure
* <1=> All Memory is Non-Secure
* <i> Value for SAU->CTRL register bit ALLNS
* <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
*/
#define SAU_INIT_CTRL_ALLNS 0
#define SAU_ENTRYS_NUM 8
#define IDAU_ENTRYS_NUM 8
void BOOT_RAM_TZCfg(void);
/* The TT instruction takes a memory address and returns the configuration of the Memory Protection Unit (MPU) at that address.
The cmse_address_info_t is declared as following:
typedef union {
struct cmse_address_info {
unsigned mpu_region:8;
unsigned :8;
unsigned mpu_region_valid:1;
unsigned :1;
unsigned read_ok:1;
unsigned readwrite_ok:1;
unsigned :12;
} flags;
unsigned value;
} cmse_address_info_t;
When executed in the secure state the result of TT instruction is extended to return the SAU and IDAU configurations at the specific address.
The extended cmse_address_info_t is declared as following:
typedef union {
struct cmse_address_info {
unsigned mpu_region:8;
unsigned sau_region:8;
unsigned mpu_region_valid:1;
unsigned sau_region_valid:1;
unsigned read_ok:1;
unsigned readwrite_ok:1;
unsigned nonsecure_read_ok:1;
unsigned nonsecure_readwrite_ok:1;
unsigned secure:1;
unsigned idau_region_valid:1;
unsigned idau_region:8;
} flags;
unsigned value;
} cmse_address_info_t;
As a result, these extended bits are only valid when executing in Secure state, and are UNDEFINED if used from Non-secure state.
*/
__STATIC_INLINE u32 TrustZone_IsSecure(void)
{
#if defined (ARM_CORE_CM4)
cmse_address_info_t cmse_address_info = cmse_TT((void *)DiagPrintf);
return cmse_address_info.flags.secure;
#else
return 0;
#endif
}
#endif //_TRUSTZONE_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_trustzone.h
|
C
|
apache-2.0
| 2,815
|
/**
******************************************************************************
* @file rtl8721d_uart.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the UART firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_UART_H_
#define _RTL8710B_UART_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup UART
* @{
*/
/** @addtogroup UART
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* KM4 UART0:
* - Base Address: UART0_DEV
* - IPclk: XTAL, normally is 40MHz
* - BaudRate: 110~6000000
* - Low Power Rx: Support
* - SocPs: SleepMode (clock gating & power gating)
* - Boot From UART without Flash
* - IRQ: UART0_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART0_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART0_RX
*
* KM4 UART1_BT: The same as KM4 UART0 except following
* - Base Address: UART1_DEV
* - IRQ: UART1_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART1_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART1_RX
*
* KM0 LUART: The same as KM4 UART0 except following
* - Base Address: UART3_DEV
* - IRQ: UARTLP_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART3_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_UART3_RX
*
* KM0 LOG UART: Used as loguart
* - Base Address: UART2_DEV
* - IPclk: XTAL, normally is 40MHz
* - BaudRate: 110~6000000, default set 115200 for log
* - Low Power Rx: Support
* - Flash Program use LOGUART
* - IRQ: UART_LOG_IRQ
*
*****************************************************************************************
* Low Power Rx
*****************************************************************************************
* All UART support
* UART can receive data when soc enter power save mode
* baudrate: 110~115200
*
*****************************************************************************************
* How to use Normal Uart
*****************************************************************************************
* To use the normal uart mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power(it is enable default):
* RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
*
* 2. configure the UART pinmux
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
*
* 3. Set default parameters, change some parameter if needed
* UART_StructInit(UART_InitTypeDef* UART_InitStruct)
*
* 4. init hardware use step3 parameters.
* UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
*
* 5. Set Baud Rate.
* UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate)
*
* 6. Enable IRQ using following function if needed
* UART_INTConfig(): UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 7. Enable uart rx path:
* UART_RxCmd().
*
* @note in UART_Normal_functions group, these functions below are about Interrupts
* and flags management.
* UART_INTConfig()
* UART_IntStatus()
* UART_LineStatusGet()
*
*****************************************************************************************
* How to use uart in DMA mode
*****************************************************************************************
* To use the uart in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power(it is enable default):
* RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
*
* 2. configure the UART pinmux
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
*
* 3. Set default parameters, and change DMA mode open UART_InitStruct
* UART_StructInit(UART_InitTypeDef* UART_InitStruct)
*
* 4. init hardware use step3 parameters.
* UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
*
* 5. Set Baud Rate.
* UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate)
*
* 6. Enable uart rx path:
* UART_RxCmd().
*
* 7. Configure the uart DMA burst size:
* UART_TXDMAConfig()
* UART_RXDMAConfig().
*
* 8. Active the UART TX/RX DMA Request:
* UART_TXDMACmd()
* UART_RXDMACmd().
*
* 9. GDMA related configurations(source address/destination address/block size etc.).
* UART_TXGDMA_Init()
* UART_RXGDMA_Init()
*
*****************************************************************************************
* How to use uart in Low Power mode
*****************************************************************************************
* To use the uart in Low Power mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power(it is enable default):
* RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
*
* 2. configure the UART pinmux
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
*
* 3. Set default parameters, change some parameter if needed
* UART_StructInit(UART_InitTypeDef* UART_InitStruct)
*
* 4. init hardware use step3 parameters.
* UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
*
* 5. Set Baud Rate.
* UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate)
*
* 6. Enable IRQ using following function if needed
* UART_INTConfig(): UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 7. Configure monitor parameters:
* UART_MonitorParaConfig();
*
* 8. Enable monitor function if needed.
* UART_RxMonitorCmd()
*
* 9. Set lower power clock source
* RCC_PeriphClockSource_UART (UART_TypeDef* UARTx, u32 Source)
*
* 10. Set the low power RX Baud Rate
* UART_LPRxBaudSet(UART_TypeDef* UARTx, u32 BaudRate, u32 RxIPClockHz)
*
* 11. Enable uart rx path:
* UART_RxCmd().
*
* @note when uart work in low power rx mode, clock source can switch between
* XTAL and OSC. As for how and when to excute switching action,
* refer to related uart specifications for more details.
*
* @note Besides, if more details about the uart low power rx path contens is needed,
* please refer to uart specifications.
*
*****************************************************************************************
* How to use uart in IrDA mode
*****************************************************************************************
* To use the uart in IrDA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power(it is enable default):
* RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
*
* 2. configure the pinmux:
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
*
* 3. Disable rx path:
* UART_RxCmd().
*
* 4. Program the IrDA tx pulse width and location and IrDA rx pulse filter:
* UART_IrDAStructInit(IrDA_InitTypeDef * IrDA_InitStruct)
*
* 5. Init Hardware:
* UART_IrDAInit(UART_TypeDef* UARTx, IrDA_InitTypeDef * IrDA_InitStruct).
*
* 6. Enable the IrDA function:
* UART_IrDACmd().
*
* 7. According to the IrDA SIR protocol data format requrement, program Word Length,
* Stop Bit, Parity and DMA Mode(ENABLE/DISABLE):
* UART_StructInit(UART_InitTypeDef* UART_InitStruct)
* UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct)
*
* 8. Program the Baud Rate:
* UART_SetBaud().
*
* 9. Enable IRQ if needed:
* UART_INTConfig(): UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 10. Enable uart rx path:
* UART_RxCmd().
*
* @note AmebaD IrDA just support IrDA SIR protocol, setting baud rate is no more than
* 115200 bps.
*
* @note because IrDA transfers data using infrared carrier and for the property of the
* IrDA transceiver, IrDA just work in half duplex mode. For details, refer to the IrDA
* protocol specification.
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup UART_Exported_Types UART Exported Types
* @{
*/
/**
* @brief UART Init structure definition
*/
typedef struct
{
u32 DmaModeCtrl; /*!< Specifies the uart DMA mode state.
This parameter can be ENABLE or DISABLE. */
u32 WordLen; /*!< Specifies the UART word length.
This parameter can be a value of @ref UART_Word_length_define. */
u32 StopBit; /*!< Specifies the UART stop bit number.
This parameter can be a value of @ref UART_Stop_Bit_define. */
u32 Parity; /*!< Specifies the UART parity.
This parameter can be a value of @ref UART_Parity_Enable_define. */
u32 ParityType; /*!< Specifies the UART parity type.
This parameter can be a value of @ref UART_Parity_Type_define. */
u32 StickParity; /*!< Specifies the UART stick parity.
This parameter can be a value of @ref UART_Stick_Parity_Type_define. */
u32 FlowControl; /*!< Specifies the UART auto flow control.
This parameter can be ENABLE or DISABLE. */
u32 RxFifoTrigLevel; /*!< Specifies the UART rx fifo trigger level.
This parameter can be a value of @ref UART_RX_FIFO_TRIGGER_LEVEL_define. */
u32 RxErReportCtrl; /*!< Specifies the UART rx error report control.
This parameter can be a value of @ref UART_Rx_Err_Report_define. */
u32 RxTimeOutCnt; /*!< Specifies the UART rx time out counter.
This parameter can be a number between 0x00 and 0xffff.. */
} UART_InitTypeDef;
/**
* @brief UART IRDA Init structure definition
*
*/
typedef struct
{
u32 UART_IrDARxInv; /*!< Specifies the uart irda rx invert control.
This parameter can be ENABLE or DISABLE.
ENABLE: invert the irda input signal.
DISABLE: does't invert the irda input signal.
@note This parameter is only used in IrDA mode. */
u32 UART_IrDATxInv; /*!< Specifies the uart irda tx invert control.
This parameter can be ENABLE or DISABLE.
ENABLE: invert the irda output signal.
DISABLE: does't invert the irda output signal.
@note This parameter is only used in IrDA mode. */
u32 UART_UpperShift; /*!< Specifies the uart irda tx pulse right edge shift direction.
This parameter can be a value of @ref UART_IRDA_PULSE_SHIFT_define. */
u32 UART_UpperShiftVal; /*!< Specifies the uart irda tx pulse right edge shift value in the given direction.
This parameter can be a number between 0x0000 and 0x7fff. */
u32 UART_LowShift; /*!< Specifies the uart irda tx pulse left edge shift direction.
This parameter can be a value of @ref UART_IRDA_PULSE_SHIFT_define. */
u32 UART_LowShiftVal; /*!< Specifies the uart irda tx pulse left edge shift value in the given direction.
This parameter can be a number between 0x0000 and 0x7fff. */
u32 UART_RxFilterThres; /*!< Specifies the uart irda rx filter threshold.
This parameter can be a number between 0x0000 and 0x7fff
@note This parameter is only used in IrDA mode. */
u32 UART_RxFilterCmd; /*!< Specifies the uart irda rx filter control.
This parameter can be ENABLE or DISABLE.
ENABLE: uart IrDA rx filter is used.
DISABLE: uart IrDA rx filter is not used.
@note This parameter is only used in IrDA mode. */
}IrDA_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UART_Exported_Constants UART Exported Constants
* @{
*/
/** @defgroup UART_IRDA_PULSE_SHIFT_define
* @{
*/
#define UART_IRDA_PULSE_LEFT_SHIFT ((u32)0x00000000)
#define UART_IRDA_PULSE_RIGHT_SHIFT ((u32)0x00000001)
#define IS_IRDA_PUL_SHIFT(SHIFT) (((SHIFT) == UART_IRDA_PULSE_LEFT_SHIFT) || \
((SHIFT) == UART_IRDA_PULSE_RIGHT_SHIFT))
/**
* @}
*/
/** @defgroup UART_RX_FIFO_TRIGGER_LEVEL_define
* @{
*/
#define UART_RX_FIFOTRIG_LEVEL_1BYTES ((u32)0x00000000)
#define UART_RX_FIFOTRIG_LEVEL_4BYTES ((u32)0x00000040)
#define UART_RX_FIFOTRIG_LEVEL_8BYTES ((u32)0x00000080)
#define UART_RX_FIFOTRIG_LEVEL_14BYTES ((u32)0x000000c0)
#define IS_UART_RXFIFO_LEVEL(LEVEL) (((LEVEL) == UART_RX_FIFOTRIG_LEVEL_1BYTES) || \
((LEVEL) == UART_RX_FIFOTRIG_LEVEL_4BYTES) || \
((LEVEL) == UART_RX_FIFOTRIG_LEVEL_8BYTES) || \
((LEVEL) == UART_RX_FIFOTRIG_LEVEL_14BYTES))
/**
* @}
*/
/** @defgroup UART_Word_length_define
* @{
*/
#define RUART_WLS_7BITS ((u32)0x00000000)
#define RUART_WLS_8BITS ((u32)0x00000001)
#define IS_UART_WLS(VAL) (((VAL) == RUART_WLS_7BITS) || \
((VAL) == RUART_WLS_8BITS))
/**
* @}
*/
/** @defgroup UART_Stop_Bit_define
* @{
*/
#define RUART_STOP_BIT_1 ((u32)0x00000000)
#define RUART_STOP_BIT_2 ((u32)0x00000001)
#define IS_UART_STOP_BIT(VAL) (((VAL) == RUART_STOP_BIT_1) || \
((VAL) == RUART_STOP_BIT_2))
/**
* @}
*/
/** @defgroup UART_Parity_Enable_define
* @{
*/
#define RUART_PARITY_DISABLE ((u32)0x00000000)
#define RUART_PARITY_ENABLE ((u32)0x00000001)
#define IS_UART_PARITY_ENABLE(VAL) (((VAL) == RUART_PARITY_DISABLE) || \
((VAL) == RUART_PARITY_ENABLE))
/**
* @}
*/
/** @defgroup UART_Parity_Type_define
* @{
*/
#define RUART_ODD_PARITY ((u32)0x00000000)
#define RUART_EVEN_PARITY ((u32)0x00000001)
#define IS_UART_PARITY_TYPE(VAL) (((VAL) == RUART_ODD_PARITY) || \
((VAL) == RUART_EVEN_PARITY))
/**
* @}
*/
/** @defgroup UART_Stick_Parity_Type_define
* @{
*/
#define RUART_STICK_PARITY_DISABLE ((u32)0x00000000)
#define RUART_STICK_PARITY_ENABLE ((u32)0x00000001)
#define IS_UART_STICK_PARITY_ENABLE(VAL) (((VAL) == RUART_STICK_PARITY_DISABLE) || \
((VAL) == RUART_STICK_PARITY_ENABLE))
/**
* @}
*/
/** @defgroup UART_Interrupt_ID_define
* @{
*/
#define RUART_MODEM_STATUS ((u32)0x00000000)
#define RUART_TX_FIFO_EMPTY ((u32)0x00000001)
#define RUART_RECEIVER_DATA_AVAILABLE ((u32)0x00000002)
#define RUART_RECEIVE_LINE_STATUS ((u32)0x00000003)
#define RUART_LP_RX_MONITOR_DONE ((u32)0x00000004)
#define RUART_TIME_OUT_INDICATION ((u32)0x00000006)
/**
* @}
*/
/** @defgroup UART_RX_Clock_Source_define
* @{
*/
#define UART_RX_CLK_XTAL_40M ((u32)0x00000000)
#define UART_RX_CLK_OSC_LP ((u32)0x00000001)
#define UART_RX_CLK_XTAL_LP ((u32)0x00000002)
#define IS_UART_RX_CLK(CLK) (((CLK) == UART_RX_CLK_XTAL_40M) || \
((CLK) == UART_RX_CLK_XTAL_LP) || \
((CLK) == UART_RX_CLK_OSC_LP))
/**
* @}
*/
/** @defgroup UART_Rx_Err_Report_define
* @{
*/
#define UART_RX_EEROR_REPORT_DISABLE ((u32)0x00000000)
#define UART_RX_EEROR_REPORT_ENABLE ((u32)0x00000001)
#define IS_UART_RX_ERROR_REPORT(REPORT) (((REPORT) == UART_RX_EEROR_REPORT_DISABLE) || \
((REPORT) == UART_RX_EEROR_REPORT_ENABLE) )
/**
* @}
*/
/** @defgroup UART_Low_Power_Peripheral_define
* @{
*/
#define IS_LPUART_PERIPH(PERIPH) (((PERIPH) == UART0_DEV) || ((PERIPH) == UART2_DEV) || ((PERIPH) == UART3_DEV))
/**
* @}
*/
/** @defgroup UART_SoftWare_Status_define
* @{
*/
#define STATETX_DMA 1
#define STATETX_INT 2
#define STATETX_POLL 3
#define STATERX_DMA 1
#define STATERX_INT 2
#define STATERX_POLL 3
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
* @{
*/
/** @defgroup UART_Normal_functions
* @{
*/
_LONG_CALL_ void UART_DeInit(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
_LONG_CALL_ void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef *UART_InitStruct);
_LONG_CALL_ u32 UART_BaudParaGet(u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
_LONG_CALL_ void UART_BaudParaGetFull(u32 IPclk, u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
_LONG_CALL_ void UART_SetBaudExt(UART_TypeDef* UARTx, u32 Ovsr, u32 Ovsr_adj);
_LONG_CALL_ void UART_SetBaud(UART_TypeDef* UARTx, u32 BaudRate);
_LONG_CALL_ void UART_SetRxLevel(UART_TypeDef* UARTx, u32 FifoLv);
_LONG_CALL_ void UART_RxCmd(UART_TypeDef* UARTx, u32 NewState);
_LONG_CALL_ u32 UART_Writable(UART_TypeDef* UARTx);
_LONG_CALL_ u32 UART_Readable(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_CharPut(UART_TypeDef* UARTx, u8 TxData);
_LONG_CALL_ void UART_CharGet(UART_TypeDef* UARTx, u8 *pRxByte);
_LONG_CALL_ void UART_ReceiveData(UART_TypeDef* UARTx, u8* OutBuf, u32 Count);
_LONG_CALL_ void UART_SendData(UART_TypeDef* UARTx, u8* InBuf, u32 Count);
_LONG_CALL_ u32 UART_ReceiveDataTO(UART_TypeDef* UARTx, u8* OutBuf, u32 Count, u32 Times);
_LONG_CALL_ u32 UART_SendDataTO(UART_TypeDef* UARTx,u8* InBuf,u32 Count, u32 Times);
_LONG_CALL_ void UART_RxByteCntClear(UART_TypeDef* UARTx);
_LONG_CALL_ u32 UART_RxByteCntGet(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_BreakCtl(UART_TypeDef* UARTx, u32 NewState);
_LONG_CALL_ u32 UART_ClearRxFifo(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_ClearTxFifo(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_INTConfig(UART_TypeDef* UARTx, u32 UART_IT, u32 newState);
_LONG_CALL_ u32 UART_IntStatus(UART_TypeDef* UARTx);
_LONG_CALL_ u32 UART_ModemStatusGet(UART_TypeDef* UARTx);
_LONG_CALL_ u32 UART_LineStatusGet(UART_TypeDef* UARTx);
_LONG_CALL_ void UART_WaitBusy(UART_TypeDef* UARTx, u32 PollTimes);
/**
* @}
*/
/** @defgroup UART_DMA_functions
* @{
*/
_LONG_CALL_ void UART_TXDMAConfig(UART_TypeDef* UARTx, u32 TxDmaBurstSize);
_LONG_CALL_ void UART_RXDMAConfig(UART_TypeDef* UARTx, u32 RxDmaBurstSize);
_LONG_CALL_ void UART_TXDMACmd(UART_TypeDef* UARTx, u32 NewState);
_LONG_CALL_ void UART_RXDMACmd(UART_TypeDef* UARTx, u32 NewState);
_LONG_CALL_ BOOL UART_TXGDMA_Init(u8 UartIndex, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTxBuf, int TxCount);
_LONG_CALL_ BOOL UART_RXGDMA_Init(u8 UartIndex, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pRxBuf, int RxCount);
/**
* @}
*/
/** @defgroup UART_Low_Power_functions
* @{
*/
_LONG_CALL_ void UART_MonitorParaConfig(UART_TypeDef* UARTx, u32 BitNumThres, u32 OscPerbitUpdCtrl);
_LONG_CALL_ void UART_LPRxBaudSet(UART_TypeDef* UARTx, u32 BaudRate, u32 RxIPClockHz);
_LONG_CALL_ void UART_RxMonitorCmd(UART_TypeDef* UARTx, u32 NewState);
_LONG_CALL_ u32 UART_RxMonBaudCtrlRegGet(UART_TypeDef* UARTx);
_LONG_CALL_ u32 UART_RxMonitorSatusGet(UART_TypeDef* UARTx);
/**
* @}
*/
/** @defgroup UART_IRDA_functions
* @{
*/
_LONG_CALL_ void UART_IrDAStructInit(IrDA_InitTypeDef * IrDA_InitStruct);
_LONG_CALL_ void UART_IrDAInit(UART_TypeDef* UARTx, IrDA_InitTypeDef * IrDA_InitStruct);
_LONG_CALL_ void UART_IrDACmd(UART_TypeDef* UARTx, u32 NewState);
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup UART_Register_Definitions UART Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup UART_DLH_INTCR
* @{
*****************************************************************************/
#define RUART_IER_ERBI ((u32)0x00000001) /*BIT[0], Enable received data available interrupt (rx trigger)*/
#define RUART_IER_ETBEI ((u32)0x00000001<<1) /*BIT[1], Enable transmitter FIFO empty interrupt (tx fifo empty)*/
#define RUART_IER_ELSI ((u32)0x00000001<<2) /*BIT[2], Enable receiver line status interrupt (receiver line status)*/
#define RUART_IER_EDSSI ((u32)0x00000001<<3) /*BIT[3], Enable modem status interrupt (modem status transition)*/
#define RUART_IER_EDMI ((u32)0x00000001<<4) /*BIT[4], Enable low power rx monitor done interrupt (monitor done)*/
#define RUART_IER_ETOI ((u32)0x00000001<<5) /*BIT[5], Enable rx time out interrupt*/
/** @} */
/**************************************************************************//**
* @defgroup UART_INTID
* @{
*****************************************************************************/
#define RUART_IIR_INT_PEND ((u32)0x00000001) /*uart interrupt global status*/
#define RUART_IIR_INT_ID ((u32)0x00000007<<1) /*Uart Interrupt ID mask, register INTID[3:1]*/
/** @} */
/**************************************************************************//**
* @defgroup UART_FCR
* @{
*****************************************************************************/
#define RUART_FIFO_CTL_RX_ERR_RPT ((u32)0x00000001) /*BIT[0], 0x01, RX error report control bit*/
#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO ((u32)0x00000001<<1) /*BIT[1], 0x02, Write 1 clear*/
#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO ((u32)0x00000001<<2) /*BIT[2], 0x04, Write 1 clear*/
#define RUART_FIFO_CTL_REG_DMA_ENABLE ((u32)0x00000001<<3) /*BIT[3], 0x08, Uart DMA control bit*/
#define RUART_FIFO_CTL_REG_RX_TRG_LEV ((u32)0x00000003<<6) /*BIT[7:6], 0xc0, Uart rx trigger level field*/
/** @} */
/**************************************************************************//**
* @defgroup UART_MCR
* @{
*****************************************************************************/
#define RUART_MCL_FLOW_ENABLE ((u32)((0x00000001 << 5) | (0x00000001 << 1))) /*BIT[1],BIT[5],Uart auto flow control enable bit*/
/** @} */
/**************************************************************************//**
* @defgroup UART_LCR
* @{
*****************************************************************************/
#define BIT_UART_LCR_BREAK_CTRL ((u32)0x00000001<<6) /*BIT[6], Uart break control function enable bit*/
#define RUART_LINE_CTL_REG_DLAB_ENABLE ((u32)0x00000001<<7) /*BIT[7], 0x80*/
/** @} */
/**************************************************************************//**
* @defgroup UART_LSR
* @{
*****************************************************************************/
#define RUART_LINE_STATUS_REG_DR ((u32)0x00000001) /*BIT[0], Data ready indicator*/
#define RUART_LINE_STATUS_ERR_OVERRUN ((u32)0x00000001<<1) /*BIT[1], Over run*/
#define RUART_LINE_STATUS_ERR_PARITY ((u32)0x00000001<<2) /*BIT[2], Parity error*/
#define RUART_LINE_STATUS_ERR_FRAMING ((u32)0x00000001<<3) /*BIT[3], Framing error*/
#define RUART_LINE_STATUS_ERR_BREAK ((u32)0x00000001<<4) /*BIT[4], Break interrupt error*/
#define RUART_LINE_STATUS_REG_THRE ((u32)0x00000001<<5) /*BIT[5], 0x20, Transmit holding register empty interrupt enable*/
#define RUART_LINE_STATUS_REG_TEMT ((u32)0x00000001<<6) /*BIT[6], 0x40, Transmitter empty indicator(bit)*/
#define RUART_LINE_STATUS_ERR_RXFIFO ((u32)0x00000001<<7) /*BIT[7], RX FIFO error*/
#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN |RUART_LINE_STATUS_ERR_PARITY| \
RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
RUART_LINE_STATUS_ERR_RXFIFO) /*Line status error*/
/** @} */
/**************************************************************************//**
* @defgroup UART_SPR
* @{
*****************************************************************************/
#define RUART_SP_REG_RXBREAK_INT_STATUS ((u32)0x00000001<<7) /*BIT[7], 0x80, Write 1 clear*/
#define RUART_SP_REG_DBG_SEL ((u32)0x0000000F<<8) /*BIT[11:8], Debug port selection*/
#define RUART_SP_REG_XFACTOR_ADJ ((u32)0x000007FF<<16) /*BIT[26:16], ovsr_adj parameter field*/
/** @} */
/**************************************************************************//**
* @defgroup UART_STSR
* @{
*****************************************************************************/
//#define RUART_STS_REG_RESET_RCV ((u32)0x00000001<<3) /*BIT[3], 0x08, Reset uart receiver*/
#define RUART_STS_REG_XFACTOR ((u32)0x000FFFFF<<4) /*BIT[23:4]ovsr parameter field*/
/** @} */
/**************************************************************************//**
* @defgroup UART_MISCR
* @{
*****************************************************************************/
#define RUART_IRDA_ENABLE ((u32)0x00000001) /*BIT[0], Enable IrDA*/
#define RUART_IRDA_TX_INVERT ((u32)0x00000001 << 13) /*BIT[13], Enable IrDA tx invert*/
#define RUART_IRDA_RX_INVERT ((u32)0x00000001 << 14) /*BIT[14], Enable IrDA rx invert*/
#define RUART_TXDMA_BURSTSIZE_MASK ((u32)0x0000001F << 3) /*BIT[7:3], Uart tx DMA burst size mask.
This field value must be no more than 16.
Because tx fifo depth is 16 in UART IP hardware*/
#define RUART_RXDMA_BURSTSIZE_MASK ((u32)0x0000001F << 8) /*BIT[12:8], Uart rx DMA burst size mask.
This field value must be no more than 16.
Because rx fifo depth is 16 in uart IP hardware*/
#define RUART_TXDMA_ENABLE ((u32)0x00000001 << 1) /*BIT[1], Uart tx DMA enable bit*/
#define RUART_RXDMA_ENABLE ((u32)0x00000001 << 2) /*BIT[2], Uart rx DMA enable bit*/
#define RUART_RXDMA_OWNER ((u32)0x00000001 << 15) /*BIT[15], the DMA flow controller selection(UART or DMA)*/
#define RUART_RXDMA_DUMMY_DATA ((u32)0x000000FF << 16) /*BIT[23:16], dummy data when uart is the flow controller*/
#define RUART_RXDMA_DUMMY_FLAG ((u32)0x00000001 << 24) /*BIT[24], this bit is set when master read dummy data from UART RX FIFO, it can be cleared by software
by writing 1 to this bit*/
/** @} */
/**************************************************************************//**
* @defgroup UART_TXPLSR
* @{
*****************************************************************************/
#define RUART_IRDA_TX_PUL_LOW_BUND_VAL ((u32)0x00007FFF) /*BIT[14:0], IrDA tx pulse low bound edge shift value*/
#define RUART_IRDA_TX_PUL_LOW_BUND_SHIFT ((u32)0x00000001 << 15) /*BIT[15], IrDA tx pulse low bound edge shift direction*/
#define RUART_IRDA_TX_PUL_UP_BUND_VAL ((u32)0x00007FFF << 16) /*BIT[30:16], IrDA tx pulse upper bound edge shift value*/
#define RUART_IRDA_TX_PUL_UP_BUND_SHIFT ((u32)0x00000001 << 31) /*BIT[31], IrDA tx pulse upper bound edge shift direction*/
/** @} */
/**************************************************************************//**
* @defgroup UART_RXPLSR
* @{
*****************************************************************************/
#define RUART_IRDA_RX_FILTER_ENABLE ((u32)0x00000001) /*BIT[0], IrDA rx filter enable*/
#define RUART_IRDA_RX_FILTER_THRES ((u32)0x00007FFF << 1) /*BIT[15:1], IrDA rx filter threshold field*/
/** @} */
/**************************************************************************//**
* @defgroup UART_REG_RX_PATH_CTRL
* @{
*****************************************************************************/
#define RUART_REG_LP_RX_PATH_SELECT ((u32)0x00000001) /*BIT[0], 0x01, Select uart low power rx path*/
#define RUART_REG_LP_RX_PATH_RESET ((u32)0x00000001 << 2) /*BIT[2], 0x40, Reset uart low power rx path receiver*/
#define RUART_REG_RX_XFACTOR_ADJ ((u32)0x000007FF << 3) /*BIT[13:3], One factor of Baud rate calculation for rx path, similar with xfactor_adj */
#define RUART_REG_RX_TO_THRES ((u32)0x0000FFFF<<16) /*BIT[31:16], rx timeout threshold, unit is one bit period*/
/** @} */
/**************************************************************************//**
* @defgroup UART_REG_MON_BAUD_CTRL
* @{
*****************************************************************************/
#define RUART_LP_RX_MON_ENABLE ((u32)0x00000001) /*BIT[0], 0x01, Enable low power rx monitor function*/
#define RUART_LP_RX_BIT_NUM_THRES ((u32)0x000000FF << 1) /*BIT[8:1], Bit Number threshold of one monitor period*/
#define RUART_LP_RX_OSC_CYCNUM_PERBIT ((u32)0x000FFFFF << 9) /*BIT[28:9], Cycle number perbit for osc clock */
#define RUART_LP_RX_OSC_UPD_IN_XTAL ((u32)0x00000001 << 29) /*BIT[29], Control bit for osc monitor parameter update */
/** @} */
/**************************************************************************//**
* @defgroup UART_REG_MON_BAUD_STS
* @{
*****************************************************************************/
#define RUART_LP_RX_XTAL_CYCNUM_PERBIT ((u32)0x000FFFFF) /*BIT[19:0], Cycle number perbit for xtal clock */
#define RUART_LP_RX_MON_RDY ((u32)0x00000001 << 20) /*BIT[20], Monitor ready status*/
#define RUART_LP_RX_MON_TOTAL_BITS ((u32)0x0000000F << 21) /*BIT[28:21], Actualy monitor bit number */
/** @} */
/**************************************************************************//**
* @defgroup UART_REG_RX_BYTE_CNT
* @{
*****************************************************************************/
/******************** Bits definition for register *******************/
#define RUART_RX_READ_BYTE_CNTER ((u32)0x0000FFFF) /*BIT[15:0], Byte number of data read from rx fifo */
#define RUART_RX_BYTE_CNTER_CLEAR ((u32)0x00000001 << 16) /*BIT[16], Write 1 clear rx byte counter*/
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
typedef struct
{
u32 LOW_POWER_RX_ENABLE; /*Enable low power RX*/
} UARTCFG_TypeDef;
typedef struct
{
UART_TypeDef* UARTx;
u32 Tx_HandshakeInterface;
u32 Rx_HandshakeInterface;
IRQn_Type IrqNum;
} UART_DevTable;
extern UARTCFG_TypeDef uart_config[];
extern const UART_DevTable UART_DEV_TABLE[4];
extern u32 UART_StateTx[4];
extern u32 UART_StateRx[4];
#define MAX_UART_INDEX (4)
static inline void
UART_SetTxFlag(u32 UartIdx, u32 Flag)
{
UART_StateTx[UartIdx] = Flag;
}
static inline void
UART_SetRxFlag(u32 UartIdx, u32 Flag)
{
UART_StateRx[UartIdx] = Flag;
}
static inline u32
UART_GetTxFlag(u32 UartIdx)
{
return (UART_StateTx[UartIdx]);
}
static inline u32
UART_GetRxFlag(u32 UartIdx)
{
return (UART_StateRx[UartIdx]);
}
#endif
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_uart.h
|
C
|
apache-2.0
| 32,656
|
/**
******************************************************************************
* @file rtl8721d_usi_ssi.h
* @author
* @version V1.0.0
* @date 2017-11-27
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_USI_SSI_H_
#define _RTL8721D_USI_SSI_H_
#include "rtl8721d_usi.h"
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup USI-SPI
* @brief USI-SPI driver modules
* @{
*/
/** @addtogroup USI-SPI
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* USI-SPI:
* - Support Motorola SPI interface
* - Role: Master or Slave
* - Base Address: USI0_DEV
* - Bus Clk: 50MHz
* - BaudRate: less than or equal to 25M
* - Transfer mode: Tx,Rx,TRx when configured as Master; TRx when configured as Slave
* - Data Frame Size: 4-16 bits supported
* - IRQ Number: USI_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_RX
*
*****************************************************************************************
* How to use Normal USI SPI
*****************************************************************************************
* To use the SPI in normal mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the following functions:
* -RCC_PeriphClockCmd(APBPeriph_USI_REG, APBPeriph_USI_CLOCK, ENABLE);
*
* 2. Configure the SPIx pinmux:
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master;
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave;
*
* 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
* USI_SSI_StructInit() and change some parameters if needed
*
* 4. Init Hardware use step3 parameters:
* USI_SSI_Init(USI_TypeDef *usi_dev, USI_SSI_InitTypeDef *USI_SSI_InitStruct)
*
* 5. Enable the SPI:
* USI_SSI_Cmd()
*
* 6. When using poll:
* -Using USI_SSI_Writeable() function to make sure that the transmit FIFO is not full,
* then using USI_SSI_WriteData() function to send data
*
* -Using USI_SSI_Readable() function to make sure that the receive FIFO is not empty,
* then using USI_SSI_ReadData() function to receive data
*
* 7. Enable the NVIC and the corresponding interrupt using following function if you need
* to use interrupt mode.
* -USI_SSI_INTConfig(): SPI IRQ Mask set
* -InterruptRegister(): register the SPI irq handler
* -InterruptEn(): Enable the NVIC interrupt and set irq priority
*
*
* @note in SPI_Exported_Functions group, these functions below are about Interrupts
* and flags management:
* -USI_SSI_GetIsr()
* -USI_SSI_GetRawIsr()
* -USI_SSI_INTConfig()
* -USI_SSI_SetRxFifoLevel()
* -USI_SSI_SetTxFifoLevel()
* -USI_SSI_SetIsrClean()
*
*
*****************************************************************************************
* How to use USI SPI in DMA mode
*****************************************************************************************
* To use the USI SPI in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock using the following functions:
* -RCC_PeriphClockCmd(APBPeriph_USI_REG, APBPeriph_USI_CLOCK, ENABLE);
*
* 2. Configure the SPIx pinmux:
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master;
* -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave;
*
* 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
* USI_SSI_StructInit() and change some parameters if needed
*
* 4. Init Hardware use step3 parameters:
* USI_SSI_Init(USI_TypeDef *usi_dev, USI_SSI_InitTypeDef *USI_SSI_InitStruct)
*
* 5. Enable the SPI:
* USI_SSI_Cmd()
*
* 6. GDMA related configurations(DMA burst size/source address/destination address/block size etc).
*
* 7. Active the SPI DMA TX/RX using USI_SSI_SetDmaEnable() function.
*
* @note in SPI_Exported_Functions group, these functions below are about DMA:
* -USI_SSI_SetDmaEnable()
* -USI_SSI_SetDmaLevel()
*
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup USI_SPI_Exported_Types USI-SPI Exported Types
* @{
*/
/**
* @brief USI-SPI Init structure definition
*/
typedef struct
{
u32 USI_SPI_DmaRxDataLevel; /*!< Specifies the DMA receive data level.
The dma_rx_req is generated when the number of valid data entries in the
receive FIFO is equal to or above this field value+1,and rxdma_en =1.
@note For AmebaD, the value range of this parameter should be 0 to 63,because
the depth of Rx FIFO is 64. */
u32 USI_SPI_DmaTxDataLevel; /*!< Specifies the DMA transmit data level.
The dma_tx_req is generated when the number of valid data entries in the
transmit FIFO is equal to or below this field value,and txdma_en =1.
@note For AmebaD, the value range of this parameter should be 0 to 63,because
the depth of Rx FIFO is 64. */
u32 USI_SPI_RxThresholdLevel; /*!< Specifies the receive FIFO threshold level.
This Parameter controls the level of entries(or above) at which the receive FIFO controller
triggers an interrupt.When the number of receive FIFO entries is greater than or equal to this
value +1,the receive FIFO full interrupt is triggered.
@note For AmebaD, the value range of this parameter should be 0 to 63,because the depth
of Rx FIFO is 64. */
u32 USI_SPI_TxThresholdLevel; /*!< Specifies the transmit FIFO threshold level.
This Parameter controls the level of entries (or below) at which the transmit FIFO controller
triggers an interrupt.When the number of transmit FIFO entries is less than or equal to this
value,the transmit FIFO empty interrupt is triggered.
@note For AmebaD, the value range of this parameter should be 0 to 63,because of the depth
of Rx FIFO is 64. */
u32 USI_SPI_ClockDivider; /*!< Specifies the SPI Baud Rate.
The value of sclk_out equals to ssi_clk devides the value of this parameter
@note The LSB for this field is always set to 0 and is unaffected by a write operation,which ensures
an even value is held. */
u32 USI_SPI_DataFrameNumber; /*!< Specifies the number of data frames master wants to receive.
When TMOD=10, SPI uses this value to set the number of data frames to
be continuous received.
@note The value of this parameter should be set to the number of data frames that to be received
minus one.And this parameter is used only when the device is master. */
u32 USI_SPI_DataFrameSize; /*!< Selects the data frame length .
This parameter can be a value of @ref USI_SPI_Data_Frame_Size_definitions.
@note Need to right-justify transmit data before writting into the transmit FIFO
The transmit logic ignores the upper unused bits when transmitting the data. */
u32 USI_SPI_InterruptMask; /*!< Specifies which interrupt to enable.
Each bit in this parameter corresponds to a specific interrupt.*/
u32 USI_SPI_Role; /*!< Specifies the role of SPI device.
This parameter can be a value of @ref USI_SPI_ROLE_definitions. . */
u32 USI_SPI_SclkPhase; /*!< Specifies the serial clock phase.
When USI_SPI_SclkPhase = 0, data are captured on the first edge of the serial clock.
When USI_SPI_SclkPhase = 1, the serial clock starts toggling one cycle after the slave select line is activated,
and data are captured on the second edge of the serial clock.
This parameter can be a value of @ref USI_SPI_SCPH_definitions. */
u32 USI_SPI_SclkPolarity; /*!< Specifies the serial clock polarity.
When USI_SPI_SclkPolarity = 0, the serial clock remains low when idle.
When USI_SPI_SclkPolarity = 1, the serial clock remains high when idle.
This parameter can be a value of @ref USI_SPI_SCPOL_definitions. */
u32 USI_SPI_TransferMode; /*!< Selects the mode of transfer for serial communication.
This parameter can be a value of @ref USI_SPI_TMOD_definitions.
@note This transfer mode is only valid when the DW_apb_ssi is configured as a master device.*/
u32 USI_SPI_RxSampleDelay; /*!< Specifies the sample delay time of receive data input signal.The unit is spi_mst_clk.
@note This configuration is only valid when the DW_apb_ssi is configured as a master device.
For AmebaD, the value range of this parameter should be 0 to 0xFF */
u32 USI_SPI_SSTogglePhase; /*!< Specifies whether CS needs to toggle between transmissions when USI_SPI_SclkPhase = 0.
This parameter can be a value of @ref USI_SPI_SS_Toggle_Phase_definitions.
@note This configuration is only valid when the DW_apb_ssi is configured as a master device. */
}USI_SSI_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USI_SPI_Exported_Constants USI-SPI Exported Constants
* @{
*/
/** @defgroup USI_SPI_TMOD_definitions
* @{
*/
#define USI_SPI_TMOD_TR (0)
#define USI_SPI_TMOD_TO (1)
#define USI_SPI_TMOD_RO (2)
/**
* @}
*/
/** @defgroup USI_SPI_SCPOL_definitions
* @{
*/
#define USI_SPI_SCPOL_INACTIVE_IS_LOW (0)
#define USI_SPI_SCPOL_INACTIVE_IS_HIGH (1)
/**
* @}
*/
/** @defgroup USI_SPI_SCPH_definitions
* @{
*/
#define USI_SPI_SCPH_TOGGLES_IN_MIDDLE (0)
#define USI_SPI_SCPH_TOGGLES_AT_START (1)
/**
* @}
*/
/** @defgroup USI_SPI_SS_Toggle_Phase_definitions
* @{
*/
#define USI_SPI_SS_NOT_TOGGLE (0)
#define USI_SPI_SS_TOGGLE (1)
/**
* @}
*/
/** @defgroup USI_SPI_Data_Frame_Size_definitions
* @{
*/
#define USI_SPI_DFS_4_BITS (3)
#define USI_SPI_DFS_5_BITS (4)
#define USI_SPI_DFS_6_BITS (5)
#define USI_SPI_DFS_7_BITS (6)
#define USI_SPI_DFS_8_BITS (7)
#define USI_SPI_DFS_9_BITS (8)
#define USI_SPI_DFS_10_BITS (9)
#define USI_SPI_DFS_11_BITS (10)
#define USI_SPI_DFS_12_BITS (11)
#define USI_SPI_DFS_13_BITS (12)
#define USI_SPI_DFS_14_BITS (13)
#define USI_SPI_DFS_15_BITS (14)
#define USI_SPI_DFS_16_BITS (15)
/**
* @}
*/
/** @defgroup USI_SPI_ROLE_definitions
* @{
*/
#define USI_SPI_SLAVE (0)
#define USI_SPI_MASTER (1)
/**
* @}
*/
/** @defgroup USI_SPI_DMA_Control_definitions
* @{
*/
#define USI_SPI_NODMA (0)
#define USI_SPI_RXDMA_ENABLE (1)
#define USI_SPI_TXDMA_ENABLE (2)
#define USI_SPI_TRDMA_ENABLE (3)
/**
* @}
*/
/** @defgroup USI_SPI_FIFO_depth_definitions
* @{
*/
#define USI_SPI_TX_FIFO_DEPTH (64)
#define USI_SPI_RX_FIFO_DEPTH (64)
/**
* @}
*/
/** @defgroup USI_SPI_Interrupt_definitions
* @{
*/
#define USI_SPI_INTERRUPT_MASK (USI_TXFIFO_ALMOST_EMTY_INTR_EN | \
USI_TXFIFO_OVERFLOW_INTR_EN | \
USI_TXFIFO_UNDERFLOW_INTR_EN | \
USI_RXFIFO_ALMOST_FULL_INTR_EN | \
USI_RXFIFO_OVERFLOW_INTR_EN | \
USI_RXFIFO_UNDERFLOW_INTR_EN | \
USI_SPI_RX_DATA_FRM_ERR_INTER_EN)
#define USI_SPI_INTERRUPT_CLEAR_MASK (USI_TXFIFO_OVERFLOW_CLR | \
USI_TXFIFO_UNDERFLOW_CLR | \
USI_RXFIFO_OVERFLOW_CLR | \
USI_RXFIFO_UNDERFLOW_CLR | \
USI_SPI_RX_DATA_FRM_ERR_CLR)
/**
* @}
*/
/** @defgroup USI_TRX_Threshold_Level_definitions
* @{
*/
#define IS_USI_SPI_RxThresholdLevel(value) (value <= 63)
#define IS_USI_SPI_TxThresholdLevel(value) (value <= 63)
/**
* @}
*/
/** @defgroup USI_TRX_DMA_Level_definitions
* @{
*/
#define IS_USI_SPI_RxDMALevel(value) (value <= 63)
#define IS_USI_SPI_TxDMALevel(value) (value <= 63)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup USI_SPI_Exported_Functions USI-SPI Exported Functions
* @{
*/
/** @defgroup USI_SPI_Exported_Normal_Functions USI-SPI Exported Normal Functions
* @{
*/
_LONG_CALL_ void USI_SSI_StructInit(USI_SSI_InitTypeDef* USI_SSI_InitStruct);
_LONG_CALL_ void USI_SSI_Init(USI_TypeDef *usi_dev, USI_SSI_InitTypeDef *USI_SSI_InitStruct);
_LONG_CALL_ void USI_SSI_Cmd(USI_TypeDef *usi_dev, u32 NewStatus);
_LONG_CALL_ void USI_SSI_TRxPath_Cmd(USI_TypeDef *usi_dev, u32 path, u32 NewStatus);
_LONG_CALL_ u32 USI_SSI_GetTRxPath(USI_TypeDef *usi_dev);
_LONG_CALL_ void USI_SSI_INTConfig(USI_TypeDef* usi_dev, u32 USI_SSI_IT, u32 newState);
_LONG_CALL_ void USI_SSI_SetSclkPolarity(USI_TypeDef *usi_dev, u32 SclkPolarity);
_LONG_CALL_ void USI_SSI_SetSclkPhase(USI_TypeDef *usi_dev, u32 SclkPhase);
_LONG_CALL_ void USI_SSI_SetSSTogglePhase(USI_TypeDef *usi_dev, u32 TogglePhase);
_LONG_CALL_ void USI_SSI_SetDataFrameSize(USI_TypeDef *usi_dev, u32 DataFrameSize);
_LONG_CALL_ void USI_SSI_SetSampleDelay(USI_TypeDef *usi_dev, u32 SampleDelay);
_LONG_CALL_ void USI_SSI_SetReadLen(USI_TypeDef *usi_dev, u32 DataFrameNumber);
_LONG_CALL_ void USI_SSI_SetBaudDiv(USI_TypeDef *usi_dev, u32 ClockDivider);
_LONG_CALL_ void USI_SSI_SetBaud(USI_TypeDef *USIx, u32 BaudRate, u32 IpClk);
_LONG_CALL_ void USI_SSI_SetIsrClean(USI_TypeDef *usi_dev, u32 InterruptStatus);
_LONG_CALL_ void USI_SSI_WriteData(USI_TypeDef *usi_dev, u32 value);
_LONG_CALL_ void USI_SSI_SetRxFifoLevel(USI_TypeDef *usi_dev, u32 RxThresholdLevel);
_LONG_CALL_ void USI_SSI_SetTxFifoLevel(USI_TypeDef *usi_dev, u32 TxThresholdLevel);
_LONG_CALL_ u32 USI_SSI_Writeable(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_Writeable(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_ReadData(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_ReceiveData(USI_TypeDef *usi_dev, void* RxData, u32 Length);
_LONG_CALL_ u32 USI_SSI_SendData(USI_TypeDef *usi_dev, void* TxData, u32 Length, u32 Role);
_LONG_CALL_ u32 USI_SSI_GetRxCount(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetTxCount(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetTxFIFOStatus(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetRxFIFOStatus(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetTransStatus(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetDataFrameSize(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_Busy(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetIsr(USI_TypeDef *usi_dev);
_LONG_CALL_ u32 USI_SSI_GetRawIsr(USI_TypeDef *usi_dev);
/**
* @}
*/
/** @defgroup USI_SPI_Exported_DMA_Functions USI-SPI Exported DMA Functions
* @{
*/
_LONG_CALL_ BOOL USI_SSI_TXGDMA_Init(u32 Index, PGDMA_InitTypeDef GDMA_InitStruct, void *CallbackData,
IRQ_FUN CallbackFunc, u8 *pTxData, u32 Length);
_LONG_CALL_ BOOL USI_SSI_RXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData,
IRQ_FUN CallbackFunc, u8 *pRxData, u32 Length);
_LONG_CALL_ void USI_SSI_SetDmaEnable(USI_TypeDef *usi_dev, u32 newState, u32 Mask);
_LONG_CALL_ void USI_SSI_SetDmaLevel(USI_TypeDef *usi_dev, u32 TxLevel, u32 RxLevel);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
#endif //_RTL8721D_USI_SSI_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_usi_ssi.h
|
C
|
apache-2.0
| 16,725
|
/**
******************************************************************************
* @file rtl8721d_usi_uart.h
* @author
* @version V1.0.0
* @date 2017-09-26
* @brief This file contains all the functions prototypes for the USI firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_USI_UART_H_
#define _RTL8721D_USI_UART_H_
#include "rtl8721d_usi.h"
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup USI-UART
* @{
*/
/** @addtogroup USI-UART
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* USI0-UART:
* - Base Address: USI0_DEV
* - IPclk: XTAL, normally is 40MHz
* - BaudRate: 110~6000000
* - Low Power Rx: Support
* - Boot From UART without Flash
* - IRQ: USI_IRQ
* - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_TX
* - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_USI0_RX
*
*****************************************************************************************
* USI UART Low Power Rx
*****************************************************************************************
* USI0-UART support
* UART can receive data when soc enter power save mode
* baudrate: 110~500000
*
*****************************************************************************************
* How to use USI Normal Uart
*****************************************************************************************
* To use the normal uart mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
*
* 2. configure the USI UART pinmux
*
* 3. Set default parameters, change some parameter if needed
* USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct)
*
* 4. init hardware use step3 parameters.
* USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef *USI_UARTInitStruct)
*
* 5. Set Baud Rate.
* USI_UARTSetBaud(USI_TypeDef* USIx, u32 BaudRate)
*
* 6. Enable IRQ using following function if needed
* USI_UARTINTConfig(): USI UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 7. Enable uart rx path:
* USI_UARTRxCmd().
*
*****************************************************************************************
* How to use USI uart in DMA mode
*****************************************************************************************
* To use the uart in DMA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
*
* 2. configure the USI UART pinmux
*
* 3. Set default parameters, and change DMA mode open USI_UARTInitStruct
* USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct)
*
* 4. init hardware use step3 parameters.
* USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef *USI_UARTInitStruct)
*
* 5. Set Baud Rate.
* USI_UARTSetBaud(USI_TypeDef* USIx, u32 BaudRate)
*
* 6. Enable uart rx path:
* USI_UARTRxCmd().
*
* 7. Configure the uart DMA burst size:
* USI_UARTTXDMAConfig()
* USI_UARTRXDMAConfig().
*
* 8. Active the UART TX/RX DMA Request:
* USI_UARTTXDMACmd()
* USI_UARTRXDMACmd().
*
* 9. GDMA related configurations(source address/destination address/block size etc.).
* USI_UARTTXGDMA_Init()
* USI_UARTRXGDMA_Init()
*
*****************************************************************************************
* How to use USI uart in Low Power mode
*****************************************************************************************
* To use the uart in Low Power mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
*
* 2. configure the USI UART pinmux
*
* 3. Set default parameters, change some parameter if needed
* USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct)
*
* 4. init hardware use step3 parameters.
* USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef *USI_UARTInitStruct)
*
* 5. Set Baud Rate.
* USI_UARTSetBaud(USI_TypeDef* USIx, u32 BaudRate)
*
* 6. Enable IRQ using following function if needed
* USI_UARTINTConfig(): USI UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 6. Init Low power RX:
* USI_UARTLPRxStructInit(USI_LPUARTInitTypeDef* USI_LPUARTInitStruct)
* USI_UARTLPRxInit(USI_TypeDef* USIx, USI_LPUARTInitTypeDef *USI_LPUARTInitTypeDef)
*
* 7. Set the low power RX Baud Rate
* USI_UARTLPRxBaudSet(USI_TypeDef* USIx, u32 BaudRate, u32 RxIPClockHz)
*
* 8. Enable monitor function if needed.
* USI_UARTLPRxMonitorCmd()
*
* 9. Enable low power rx path:
* USI_UARTLPRxCmd().
*
* @note when uart work in low power rx mode, clock source can switch between
* XTAL and OSC. As for how and when to excute switching action,
* refer to related uart specifications for more details.
*
* @note Besides, if more details about the uart low power rx path contens is needed,
* please refer to uart specifications.
*
*****************************************************************************************
* How to use USI uart in IrDA mode
*****************************************************************************************
* To use the uart in IrDA mode, the following steps are mandatory:
*
* 1. Enable peripheral clock and power:
*
* 2. configure the pinmux:
*
* 3. Disable rx path:
* USI_UARTRxCmd().
*
* 4. Program the IrDA tx pulse width and location and IrDA rx pulse filter:
* USI_UARTIrDAStructInit(USI_UartIrDAInitTypeDef * IrDA_InitStruct)
*
* 5. Init Hardware:
* USI_UARTIrDAInit(USI_TypeDef* USIx, USI_UartIrDAInitTypeDef * IrDA_InitStruct).
*
* 6. Enable the IrDA function:
* USI_UARTIrDACmd().
*
* 7. According to the IrDA SIR protocol data format requrement, program Word Length,
* Stop Bit, Parity and DMA Mode(ENABLE/DISABLE):
* USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct)
* USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef *USI_UARTInitStruct)
*
* 8. Program the Baud Rate:
* USI_UARTSetBaud().
*
* 9. Enable IRQ if needed:
* USI_UARTINTConfig(): USI UART IRQ Mask set
* InterruptRegister(): register the uart irq handler
* InterruptEn(): Enable the NVIC interrupt
*
* 10. Enable uart rx path:
* USI_UARTRxCmd().
*
* @note AmebaD IrDA just support IrDA SIR protocol, setting baud rate is no more than
* 115200 bps.
*
* @note because IrDA transfers data using infrared carrier and for the property of the
* IrDA transceiver, IrDA just work in half duplex mode. For details, refer to the IrDA
* protocol specification.
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup USI_UART_Exported_Types USI-UART Exported Types
* @{
*/
/**
* @brief USI_UART Init structure definition
*/
typedef struct
{
u32 USI_UARTDmaModeCtrl; /*!< Specifies the uart DMA mode state.
This parameter can be ENABLE or DISABLE. */
u32 USI_UARTWordLen; /*!< Specifies the USI UART word length.
This parameter can be a value of @ref USI_UART_Word_length_define. */
u32 USI_UARTStopBit; /*!< Specifies the USI UART stop bit number.
This parameter can be a value of @ref USI_UART_Stop_Bit_define. */
u32 USI_UARTParity; /*!< Specifies the USI UART parity.
This parameter can be a value of @ref USI_UART_Parity_Enable_define. */
u32 USI_UARTParityType; /*!< Specifies the USI UART parity type.
This parameter can be a value of @ref USI_UART_Parity_Type_define. */
u32 USI_UARTStickParity; /*!< Specifies the USI UART stick parity.
This parameter can be a value of @ref USI_UART_Stick_Parity_Type_define. */
u32 USI_UARTFlowControl; /*!< Specifies the USI UART auto flow control.
This parameter can be ENABLE or DISABLE. */
u32 USI_UARTFlwCtrlRxHoldThd; /*!< Specifies the USI UART uart auto flow control rx hold threshold.
This parameter can be a value of 0 ~ 64. */
u32 USI_UARTRxFifoTrigLevel; /*!< Specifies the USI UART rx fifo trigger level.
This parameter can be a value of 0 ~ 64 . */
u32 USI_UARTTxFifoTrigLevel; /*!< Specifies the USI UART rx error report control.
This parameter can be a value of 0 ~ 64 . */
} USI_UARTInitTypeDef;
/**
* @brief USI UART Low Power Init structure definition
*/
typedef struct
{
u32 USI_LPUARTOscPerbitUpdCtrl; /*!< Specifies the OSC perbit update control when use xtal 8M.
This parameter can be ENABLE or DISABLE.
ENABLE: osc perbit updates with xtal perbit when use xtal 8M.
DISABLE: osc perbit does't update with xtal perbit when use xtal 8M.
@note This parameter is only used in low power rx path with xtal 8M.
@note osc perbit will update when use osc 8M, even if USI_LPUARTOscPerbitUpdCtrl is disable */
u32 USI_LPUARTBitNumThres; /*!< Specifies the bit number threshold of one monitor period.
This parameter is used to get the average clock cycles of one bit
and can be a number between 0x00 and 0x7f.
@note This parameter is only used in low power rx path. */
} USI_LPUARTInitTypeDef;
/**
* @brief USI UART IRDA Init structure definition
*/
typedef struct
{
u32 USI_UARTIrDARxInv; /*!< Specifies the uart irda rx invert control.
This parameter can be ENABLE or DISABLE.
ENABLE: invert the irda input signal.
DISABLE: does't invert the irda input signal.
@note This parameter is only used in IrDA mode. */
u32 USI_UARTIrDATxInv; /*!< Specifies the uart irda tx invert control.
This parameter can be ENABLE or DISABLE.
ENABLE: invert the irda output signal.
DISABLE: does't invert the irda output signal.
@note This parameter is only used in IrDA mode. */
u32 USI_UARTUpperShift; /*!< Specifies the USI uart irda tx pulse right edge shift direction.
This parameter can be a value of @ref USI_UART_IRDA_PULSE_SHIFT_define. */
u32 USI_UARTUpperShiftVal; /*!< Specifies the USI uart irda tx pulse right edge shift value in the given direction.
This parameter can be a number between 0x0000 and 0x7fff. */
u32 USI_UARTLowShift; /*!< Specifies the USI uart irda tx pulse left edge shift direction.
This parameter can be a value of @ref USI_UART_IRDA_PULSE_SHIFT_define. */
u32 USI_UARTLowShiftVal; /*!< Specifies the USI uart irda tx pulse left edge shift value in the given direction.
This parameter can be a number between 0x0000 and 0x7fff. */
u32 USI_UARTRxFilterThres; /*!< Specifies the USI uart irda rx filter threshold.
This parameter can be a number between 0x0000 and 0x7fff
@note This parameter is only used in IrDA mode. */
u32 USI_UARTRxFilterCmd; /*!< Specifies the USI uart irda rx filter control.
This parameter can be ENABLE or DISABLE.
ENABLE: USI uart IrDA rx filter is used.
DISABLE: USI uart IrDA rx filter is not used.
@note This parameter is only used in IrDA mode. */
}USI_UartIrDAInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USI_UART_Exported_Constants USI-UART Exported Constants
* @{
*/
/** @defgroup USI_UART_IRDA_PULSE_SHIFT_define
* @{
*/
#define USI_UART_IRDA_PULSE_LEFT_SHIFT ((u32)0x00000000)
#define USI_UART_IRDA_PULSE_RIGHT_SHIFT ((u32)0x00000001)
#define IS_USI_IRDA_PUL_SHIFT(SHIFT) (((SHIFT) == USI_UART_IRDA_PULSE_LEFT_SHIFT) || \
((SHIFT) == USI_UART_IRDA_PULSE_RIGHT_SHIFT))
/**
* @}
*/
/** @defgroup USI_UART_Word_length_define
* @{
*/
#define USI_RUART_WLS_7BITS ((u32)0x00000000)
#define USI_RUART_WLS_8BITS ((u32)0x00000001)
#define IS_USI_UART_WLS(VAL) (((VAL) == USI_RUART_WLS_7BITS) || \
((VAL) == USI_RUART_WLS_8BITS))
/**
* @}
*/
/** @defgroup USI_UART_Stop_Bit_define
* @{
*/
#define USI_RUART_STOP_BIT_1 ((u32)0x00000000)
#define USI_RUART_STOP_BIT_2 ((u32)0x00000002)
#define IS_USI_UART_STOP_BIT(VAL) (((VAL) == USI_RUART_STOP_BIT_1) || \
((VAL) == USI_RUART_STOP_BIT_2))
/**
* @}
*/
/** @defgroup USI_UART_Parity_Enable_define
* @{
*/
#define USI_RUART_PARITY_DISABLE ((u32)0x00000000)
#define USI_RUART_PARITY_ENABLE ((u32)0x00000010)
#define IS_USI_UART_PARITY_ENABLE(VAL) (((VAL) == USI_RUART_PARITY_DISABLE) || \
((VAL) == USI_RUART_PARITY_ENABLE))
/**
* @}
*/
/** @defgroup USI_UART_Parity_Type_define
* @{
*/
#define USI_RUART_ODD_PARITY ((u32)0x00000000)
#define USI_RUART_EVEN_PARITY ((u32)0x00000020)
#define IS_USI_UART_PARITY_TYPE(VAL) (((VAL) == USI_RUART_ODD_PARITY) || \
((VAL) == USI_RUART_EVEN_PARITY))
/**
* @}
*/
/** @defgroup USI_UART_Stick_Parity_Type_define
* @{
*/
#define USI_RUART_STICK_PARITY_DISABLE ((u32)0x00000000)
#define USI_RUART_STICK_PARITY_ENABLE ((u32)0x00000040)
#define IS_USI_UART_STICK_PARITY_ENABLE(VAL) (((VAL) == USI_RUART_STICK_PARITY_DISABLE) || \
((VAL) == USI_RUART_STICK_PARITY_ENABLE))
/**
* @}
*/
/** @defgroup USI_UART_Interrupt_ID_define
* @{
*/
/*TX FIFO (UART, I2C, SPI)*/
#define USI_TX_FIFO_ALMOST_EMPTY_INTER ((u32)0x00000001)
#define USI_TX_FIFO_OVERFLOW_INTER ((u32)0x00000002)
#define USI_TX_FIFO_UNDERFLOW_INTER ((u32)0x00000004) /*USI UART do not have this type interrupt*/
/*RX FIFO (UART, I2C, SPI)*/
#define USI_RX_FIFO_ALMOST_FULL_INTER ((u32)0x00000010)
#define USI_RX_FIFO_OVERFLOW_INTER ((u32)0x00000020)
#define USI_RX_FIFO_UNDERFLOW_INTER ((u32)0x00000040)
/*UART related interrupt*/
#define USI_UART_PARITY_ERROR_INTER ((u32)0x00000100)
#define USI_UART_STOP_ERROR_INTER ((u32)0x00000200)
#define USI_UART_BREAK_INTER ((u32)0x00000400)
#define USI_RX_FIFO_TIMEOUT_INTER ((u32)0x00000800)
#define USI_RX_BAUDMON_DONE_INTER ((u32)0x00001000)
#define USI_TX_CTS_CHANGE_INTER ((u32)0x00002000)
/*JUST FOR USI UART USE*/
#define IS_USI_UART_GET_IT(IT) (((IT) == USI_TX_FIFO_ALMOST_EMPTY_INTER) || \
((IT) == USI_TX_FIFO_OVERFLOW_INTER) || \
((IT) == USI_RX_FIFO_ALMOST_FULL_INTER)|| \
((IT) == USI_RX_FIFO_OVERFLOW_INTER)|| \
((IT) == USI_RX_FIFO_UNDERFLOW_INTER)|| \
((IT) == USI_UART_PARITY_ERROR_INTER)|| \
((IT) == USI_UART_STOP_ERROR_INTER)|| \
((IT) == USI_UART_BREAK_INTER)|| \
((IT) == USI_RX_FIFO_TIMEOUT_INTER)|| \
((IT) == USI_RX_BAUDMON_DONE_INTER)|| \
((IT) == USI_TX_CTS_CHANGE_INTER))
#define IS_USI_UART_IT(IT) ((((IT) & (u32)0xFFFFC08C) == 0x00) && ((IT) != 0x00))
#define IS_USI_UART_CLEAR_IT(IT) ((((IT) & (u32)0xFFFFC89D) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup USI_UART_Rx_DMA_mode_define
* @{
*/
#define USI_UART_RX_UART_IS_DMA_FLOW_CTRL ((u32)0x00000001)
#define USI_UART_RX_GDMA_IS_DMA_FLOW_CTRL ((u32)0x00000000)
#define IS_USI_UART_RX_DMA_MODE(MODE) (((MODE) == USI_UART_RX_UART_IS_DMA_FLOW_CTRL) || \
((MODE) == USI_UART_RX_GDMA_IS_DMA_FLOW_CTRL) )
/**
* @}
*/
/** @defgroup USI_Peripheral_define
* @{
*/
#define IS_ALL_USI_PERIPH(PERIPH) (((PERIPH) == USI0_DEV))
#define IS_ALL_USI_LP_PERIPH(PERIPH) (((PERIPH) == USI0_DEV))
/**
* @}
*/
/** @defgroup USI_UART_SoftWare_Status_define
* @{
*/
#define USI_UART_STATETX_DMA 1
#define USI_UART_STATETX_INT 2
#define USI_UART_STATETX_POLL 3
#define USI_UART_STATERX_DMA 1
#define USI_UART_STATERX_INT 2
#define USI_UART_STATERX_POLL 3
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup USI_UART_Exported_Functions USI-UART Exported Functions
* @{
*/
/** @defgroup USI_UART_Normal_functions
* @{
*/
_LONG_CALL_ void USI_UARTDeInit(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct);
_LONG_CALL_ void USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef* USI_UARTInitStruct);
_LONG_CALL_ u32 USI_UARTBaudParaGet(u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
_LONG_CALL_ void USI_UARTBaudParaGetFull(u32 IPclk, u32 baudrate, u32 *ovsr, u32 *ovsr_adj);
_LONG_CALL_ void USI_UARTSetBaudExt(USI_TypeDef* USIx, u32 Ovsr, u32 Ovsr_adj);
_LONG_CALL_ void USI_UARTSetBaud(USI_TypeDef* USIx, u32 BaudRate);
_LONG_CALL_ void USI_UARTSetRxLevel(USI_TypeDef* USIx, u32 FifoLv);
_LONG_CALL_ void USI_UARTRxCmd(USI_TypeDef* USIx, u32 NewState);
_LONG_CALL_ u32 USI_UARTWritable(USI_TypeDef* USIx);
_LONG_CALL_ u32 USI_UARTReadable(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTCharPut(USI_TypeDef* USIx, u8 TxData);
_LONG_CALL_ void USI_UARTCharGet(USI_TypeDef* USIx, u8 *pRxByte);
_LONG_CALL_ void USI_UARTReceiveData(USI_TypeDef* USIx, u8* OutBuf, u32 Count);
_LONG_CALL_ void USI_UARTSendData(USI_TypeDef* USIx, u8* InBuf, u32 Count);
_LONG_CALL_ u32 USI_UARTReceiveDataTO(USI_TypeDef* USIx, u8* OutBuf, u32 Count, u32 Times);
_LONG_CALL_ u32 USI_UARTSendDataTO(USI_TypeDef* USIx,u8* InBuf,u32 Count, u32 Times);
_LONG_CALL_ void USI_UARTRxByteCntClear(USI_TypeDef* USIx);
_LONG_CALL_ u32 USI_UARTRxByteCntGet(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTBreakCtl(USI_TypeDef* USIx, u32 NewState);
_LONG_CALL_ u32 USI_UARTClearRxFifo(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTClearTxFifo(USI_TypeDef* USIx);
_LONG_CALL_ u32 USI_UARTGetRxFifoValidCnt(USI_TypeDef* USIx);
_LONG_CALL_ u32 USI_UARTGetTxFifoEmptyCnt(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTINTConfig(USI_TypeDef* USIx, u32 UART_IT, u32 newState);
_LONG_CALL_ u32 USI_UARTIntStatus(USI_TypeDef* USIx);
_LONG_CALL_ u32 USI_UARTGetRawIntStatus(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTClearAllIntStatus(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTClearIntStatus(USI_TypeDef* USIx, u32 USIUART_IT);
_LONG_CALL_ void USI_UARTWaitBusy(USI_TypeDef* USIx, u32 PollTimes);
_LONG_CALL_ void USI_UARTRxTimeOutConfig(USI_TypeDef* USIx, u32 TimeOutCnt);
_LONG_CALL_ void USI_UARTRxDMAModeConfig(USI_TypeDef* USIx, u32 Mode);
_LONG_CALL_ void USI_UARTRxDMADummyDataConfig(USI_TypeDef* USIx, u8 Byte);
_LONG_CALL_ u32 USI_UARTGetRxDMADummyFlag(USI_TypeDef* USIx);
_LONG_CALL_ void USI_UARTRxClearDMADummyFlag(USI_TypeDef* USIx);
/**
* @}
*/
/** @defgroup USI_UART_DMA_functions
* @{
*/
_LONG_CALL_ void USI_UARTTXDMAConfig(USI_TypeDef* USIx, u32 TxDmaBurstSize);
_LONG_CALL_ void USI_UARTRXDMAConfig(USI_TypeDef* USIx, u32 RxDmaBurstSize);
_LONG_CALL_ void USI_UARTTXDMACmd(USI_TypeDef* USIx, u32 NewState);
_LONG_CALL_ void USI_UARTRXDMACmd(USI_TypeDef* USIx, u32 NewState);
_LONG_CALL_ BOOL USI_UARTTXGDMA_Init(u8 USIIndex, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTxBuf, int TxCount);
_LONG_CALL_ BOOL USI_UARTRXGDMA_Init(u8 USIIndex, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pRxBuf, int RxCount);
/**
* @}
*/
/** @defgroup USI_UART_Low_Power_functions
* @{
*/
_LONG_CALL_ void USI_UARTLPRxStructInit(USI_LPUARTInitTypeDef* USI_UARTInitStruct);
_LONG_CALL_ void USI_UARTLPRxInit(USI_TypeDef* USIx, USI_LPUARTInitTypeDef *USI_UARTInitStruct);
_LONG_CALL_ void USI_UARTLPRxBaudSet(USI_TypeDef* USIx, u32 BaudRate, u32 RxIPClockHz);
_LONG_CALL_ void USI_UART_LPRxMonitorCmd(USI_TypeDef* USIx, u32 NewState);
_LONG_CALL_ void USI_UARTLPRxpathSet(USI_TypeDef* USIx, u32 LPRxpath);
_LONG_CALL_ void USI_UARTLPRxIPClockSet(USI_TypeDef* USIx, u32 RxIPClock);
_LONG_CALL_ void USI_UARTLPRxCmd(USI_TypeDef* USIx, u32 NewState);
/**
* @}
*/
/** @defgroup USI_UART_IRDA_functions
* @{
*/
_LONG_CALL_ void USI_UARTIrDAStructInit(USI_UartIrDAInitTypeDef * IrDA_InitStruct);
_LONG_CALL_ void USI_UARTIrDAInit(USI_TypeDef* USIx, USI_UartIrDAInitTypeDef * IrDA_InitStruct);
_LONG_CALL_ void USI_UARTIrDACmd(USI_TypeDef* USIx, u32 NewState);
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
/*----------------USI UART definations---------------*/
typedef struct
{
u32 LOW_POWER_RX_ENABLE; /*Enable low power RX*/
} USI_UARTCFG_TypeDef;
extern USI_UARTCFG_TypeDef usi_uart_config[];
extern u32 USI_UART_StateTx[1];
extern u32 USI_UART_StateRx[1];
static inline void
USI_UART_SetTxFlag(u32 USIIdx, u32 Flag)
{
USI_UART_StateTx[USIIdx] = Flag;
}
static inline void
USI_UART_SetRxFlag(u32 USIIdx, u32 Flag)
{
USI_UART_StateRx[USIIdx] = Flag;
}
static inline u32
USI_UART_GetTxFlag(u32 USIIdx)
{
return (USI_UART_StateTx[USIIdx]);
}
static inline u32
USI_UART_GetRxFlag(u32 USIIdx)
{
return (USI_UART_StateRx[USIIdx]);
}
#endif
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_usi_uart.h
|
C
|
apache-2.0
| 23,615
|
/**
******************************************************************************
* @file rtl8721d_vector.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the IRQ firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8710B_VECTOR_TABLE_H_
#define _RTL8710B_VECTOR_TABLE_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup IRQ
* @brief IRQ modules
* @{
*/
/** @addtogroup IRQ
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* IRQ table, please refer to IRQ Exported Constants->IRQn_enum->IRQn
*
*****************************************************************************************
* how to use
*****************************************************************************************
* 1. register/unregister IRQ use: InterruptRegister/InterruptUnRegister
* 2. enable/disable IRQ use: InterruptEn/InterruptDis
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IRQ_Exported_Types IRQ Exported Types
* @{
*/
typedef s32 IRQn_Type;
typedef void (*HAL_VECTOR_FUN) (void);
typedef u32 (*IRQ_FUN)(void *Data);
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IRQ_Exported_Constants IRQ Exported Constants
* @{
*/
/** @defgroup IRQn_enum
* @{
*/
enum IRQn {
/****** Cortex-M4 Processor Exceptions Numbers ********/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** RTL8710B Specific Interrupt Numbers ************/
SYSTEM_ON_IRQ = 0, /*!< 0 SYS Interrupt for wakeup from power save */
WDG_IRQ = 1, /*!< 1 Watch dog global insterrupt */
RXI300_IRQ = 2, /*!< 2 RXI300 interrupt */
UART_LOG_IRQ = 3, /*!< 3 log uart intr */
GPIOA_IRQ = 4, /*!< 4 GPIOA portA global interrupt */
RTC_IRQ = 5, /*!< 5 rtc timer interrupt */
I2C0_IRQ = 6, /*!< 6 I2C0 global interrupt */
SPI_FLASH_IRQ = 7, /*!< 7 SPI Flash global interrupt */
GPIOB_IRQ = 8, /*!< 8 GPIOB portA global interrupt */
UARTLP_IRQ = 9, /*!< 9 UART0 global interrupt */
KEYSCAN_IRQ = 10, /*!< 10 KEYSCAN interrupt */
CTOUCH_IRQ = 11, /*!< 11 Cap-Touch interrupt */
BOR2_IRQ = 12, /*!< 12 BOR2 interrupt */
SGPIO_IRQ = 13, /*!< 13 SGPIO interrupt */
IPC_IRQ = 14, /*!< 14 IPC_KM0 interrupt */
ADC_IRQ = 15, /*!< 15 adc interrupt */
QDECODER_IRQ = 16, /*!< 16 Q-DECODER interrupt */
TIMER0_IRQ = 17, /*!< 17 Timer0 global interrupt */
TIMER1_IRQ = 18, /*!< 18 Timer1 global interrupt */
TIMER2_IRQ = 19, /*!< 19 Timer2 global interrupt */
TIMER3_IRQ = 20, /*!< 20 Timer3 global interrupt */
TIMER4_IRQ = 21, /*!< 21 Timer4 global interrupt */
TIMER5_IRQ = 22, /*!< 22 Timer5 global interrupt */
LCDC_IRQ = 23, /*!< 23 LCDC interrupt */
USB_OTG_IRQ = 24, /*!< 24 USOC interrupt */
SDIO_DEVICE_IRQ = 25, /*!< 25 SDIO device global interrupt */
SDIO_HOST_IRQ = 26, /*!< 26 SDIO host global interrupt */
CRYPTO_IRQ = 27, /*!< 27 IPsec global interrupt */
I2S0_PCM0_IRQ = 28, /*!< 28 I2S0 global interrupt */
PWR_DOWN_IRQ = 29, /*!< 29 power down enable interrupt */
ADC_COMP_IRQ = 30, /*!< 30 ADC compare interrupt */
WL_DMA_IRQ = 31, /*!< 31 Wlan Host global interrupt */
WL_PROTOCOL_IRQ = 32, /*!< 32 Wlan Firmware Wlan global interrupt */
PSRAMC_IRQ = 33, /*!< 33 PSRAM controller interrupt */
UART0_IRQ = 34, /*!< 34 UART0 global interrupt */
UART1_IRQ = 35, /*!< 35 UART1 BT UART global interrupt */
SPI0_IRQ = 36, /*!< 36 SPI0 global interrupt for communication spi */
SPI1_IRQ = 37, /*!< 37 SPI1 global interrupt for communication spi */
USI_IRQ = 38, /*!< 38 USI global interrupt */
IR_IRQ = 39, /*!< 39 IR global interrupt */
BT2WL_STS_IRQ = 40, /*!< 40 BT to WL Status Interrupt */
GDMA0_CHANNEL0_IRQ = 41, /*!< 41 GDMA0 channel 0 global interrupt */
GDMA0_CHANNEL1_IRQ = 42, /*!< 42 GDMA0 channel 1 global interrupt */
GDMA0_CHANNEL2_IRQ = 43, /*!< 43 GDMA0 channel 2 global interrupt */
GDMA0_CHANNEL3_IRQ = 44, /*!< 44 GDMA0 channel 3 global interrupt */
GDMA0_CHANNEL4_IRQ = 45, /*!< 45 GDMA0 channel 4 global interrupt */
GDMA0_CHANNEL5_IRQ = 46, /*!< 46 GDMA0 channel 5 global interrupt */
CRYPTO_IRQ_S = 50, /*!< 50 IPsec global interrupt */
RXI300_IRQ_S = 51, /*!< 51 RXI300 interrupt */
GDMA0_CHANNEL0_IRQ_S = 52, /*!< 52 GDMA0 channel 0 global interrupt */
GDMA0_CHANNEL1_IRQ_S = 53, /*!< 53 GDMA0 channel 1 global interrupt */
GDMA0_CHANNEL2_IRQ_S = 54, /*!< 54 GDMA0 channel 2 global interrupt */
GDMA0_CHANNEL3_IRQ_S = 55, /*!< 55 GDMA0 channel 3 global interrupt */
GDMA0_CHANNEL4_IRQ_S = 56, /*!< 56 GDMA0 channel 4 global interrupt */
GDMA0_CHANNEL5_IRQ_S = 57, /*!< 57 GDMA0 channel 5 global interrupt */
};
/**
* @}
*/
/** @defgroup LPIRQn_enum
* @{
*/
enum LPIRQn {
/****** Cortex-M4 Processor Exceptions Numbers ********/
NonMaskableInt_IRQn_LP = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn_LP = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn_LP = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn_LP = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn_LP = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn_LP = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn_LP = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn_LP = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn_LP = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** RTL8710B Specific Interrupt Numbers ************/
SYSTEM_ON_IRQ_LP = 0, /*!< 0 SYS Interrupt for wakeup from power save */
WDG_IRQ_LP = 1, /*!< 1 Watch dog global insterrupt */
RXI300_IRQ_LP = 2, /*!< 2 RXI300 interrupt */
UART_LOG_IRQ_LP = 3, /*!< 3 log uart intr */
GPIOA_IRQ_LP = 4, /*!< 4 GPIOA portA global interrupt */
RTC_IRQ_LP = 5, /*!< 5 rtc timer interrupt */
I2C0_IRQ_LP = 6, /*!< 6 I2C0 global interrupt */
SPI_FLASH_IRQ_LP = 7, /*!< 7 SPI Flash global interrupt */
GPIOB_IRQ_LP = 8, /*!< 8 GPIOB portA global interrupt */
UARTLP_IRQ_LP = 9, /*!< 9 UART0 global interrupt */
KEYSCAN_IRQ_LP = 10, /*!< 10 KEYSCAN interrupt */
CTOUCH_IRQ_LP = 11, /*!< 11 Cap-Touch interrupt */
BOR2_IRQ_LP = 12, /*!< 12 BOR2 interrupt */
SGPIO_IRQ_LP = 13, /*!< 13 SGPIO interrupt */
IPC_IRQ_LP = 14, /*!< 14 IPC_KM4 interrupt */
ADC_IRQ_LP = 15, /*!< 15 adc interrupt */
QDECODER_IRQ_LP = 16, /*!< 16 Q-DECODER interrupt */
TIMER0_IRQ_LP = 17, /*!< 17 Timer0 global interrupt */
TIMER1_IRQ_LP = 18, /*!< 18 Timer1 global interrupt */
TIMER2_IRQ_LP = 19, /*!< 19 Timer2 global interrupt */
TIMER3_IRQ_LP = 20, /*!< 20 Timer3 global interrupt */
TIMER4_IRQ_LP = 21, /*!< 21 Timer4 global interrupt */
TIMER5_IRQ_LP = 22, /*!< 22 Timer5 global interrupt */
GDMA0_CHANNEL0_IRQ_LP = 23, /*!< 23 GDMA channel 0 global interrupt */
GDMA0_CHANNEL1_IRQ_LP = 24, /*!< 24 GDMA channel 1 global interrupt */
GDMA0_CHANNEL2_IRQ_LP = 25, /*!< 25 GDMA channel 2 global interrupt */
WIFI_FISR_FESR = 26, /*!< 26 WIFI_FISR_FESR interrupt */
WIFI_FTSR_MAILBOX = 27, /*!< 27 WIFI_FTSR_MAILBOX interrupt */
GDMA0_CHANNEL3_IRQ_LP = 28, /*!< 28 GDMA channel 3 global interrupt */
PWR_DOWN_IRQ_LP = 29, /*!< 29 power down enable interrupt */
ADC_COMP_IRQ_LP = 30, /*!< 30 ADC compare interrupt */
KM4_WAKE_EVENT_IRQ_LP = 31, /*!< 31 KM4 peripherals wakeup CPU event interrupt */
};
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IRQ_Exported_Functions IRQ Exported Functions
* @{
*/
extern _LONG_CALL_ void irq_table_init(u32 StackP);
extern _LONG_CALL_ BOOL irq_register(IRQ_FUN IrqFun, IRQn_Type IrqNum, u32 Data, u32 Priority);
extern _LONG_CALL_ BOOL irq_unregister(IRQn_Type IrqNum);
extern _LONG_CALL_ void irq_enable(IRQn_Type IrqNum);
extern _LONG_CALL_ void irq_disable(IRQn_Type IrqNum);
#define InterruptRegister irq_register_check
#define InterruptUnRegister irq_unregister
#define InterruptEn(a,b) irq_enable(a)
#define InterruptDis(a) irq_disable(a)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Other Definitions --------------------------------------------------------*/
extern IRQ_FUN UserIrqFunTable[];
extern u32 UserIrqDataTable[];
extern HAL_VECTOR_FUN NewVectorTable[];
#if defined (ARM_CORE_CM4)
#define MAX_VECTOR_TABLE_NUM (64+16)
#define MAX_PERIPHERAL_IRQ_NUM 64
#define MAX_IRQ_PRIORITY_VALUE 7
#define IRQ_PRIORITY_SHIFT 1
#else
#define MAX_VECTOR_TABLE_NUM (16+32)
#define MAX_PERIPHERAL_IRQ_NUM 32
#define MAX_IRQ_PRIORITY_VALUE 3
#define IRQ_PRIORITY_SHIFT 2
#endif
#define MSP_RAM_LP 0x0008FFFC
#define VCT_RAM_LP 0x00080000
#define MSP_RAM_HP 0x1007EFFC
#define MSP_RAM_HP_NS 0x10004FFC
static inline BOOL irq_register_check(IRQ_FUN IrqFun, IRQn_Type IrqNum, u32 Data, u32 Priority) {
if(Priority > MAX_IRQ_PRIORITY_VALUE) {
Priority = MAX_IRQ_PRIORITY_VALUE;
}
Priority = (Priority << IRQ_PRIORITY_SHIFT);
return irq_register(IrqFun, IrqNum, Data, Priority);
}
#endif //_RTL8710B_VECTOR_TABLE_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_vector.h
|
C
|
apache-2.0
| 12,206
|
/**
******************************************************************************
* @file rtl8721d_wdg.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the WDG firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_WDG_H_
#define _RTL8721D_WDG_H_
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @defgroup WDG
* @brief WDG driver modules
* @{
*/
/** @addtogroup WDG
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* WDG:
* - Base Address: VENDOR_REG_BASE
* - Timer clk: SDM 32k
* - Generates MCU reset or WDG interrupt on expiry of a programmed time period,
* unless the program refreshes the watchdog
* - IRQ: WDG_IRQ
*
*****************************************************************************************
* WDG Register
*****************************************************************************************
* [31] R/W1C Wdt_to Watch dog timer timeout. 1 cycle pulse
* [30] R/W Wdt_mode 1: Reset system, 0: Interrupt CPU
* [29] R/W RSVD
* [28:25] R/W Cnt_limit 0: 0x001
* 1: 0x003
* 2: 0x007
* 3: 0x00F
* 4: 0x01F
* 5: 0x03F
* 6: 0x07F
* 7: 0x0FF
* 8: 0x1FF
* 9: 0x3FF
* 10: 0x7FF
* 11~15: 0xFFF
* [24] W Wdt_clear Write 1 to clear timer
* [23:17] R/W RSVD
* [16] R/W Wdt_en_byte Set 0x1 to enable watch dog timer
* [15:0] R/W BIT_VNDR_divfactor "Dividing factor.Watch dog timer is count with 32.768KHz/(divfactor+1).
* Minimum dividing factor is 1."
*
*****************************************************************************************
* How to use WGD
*****************************************************************************************
* To use WDG peripheral, the following steps are mandatory:
*
* 1. Get count ID and divisor factor according to WDG timeout period using
* WDG_Scalar(WDG_TEST_TIMEOUT, &CountProcess, &DivFacProcess);
*
* 2. Configure WDG with the corresponding configuration.
* WDG_Init(&WDG_InitStruct)
*
* 3. Activate the WDG peripheral:
WDG_Cmd(ENABLE).
*
* @note In interrupt mode, call WDG_IrqInit() function after WDG_Init()
*
* @note WDG_Refresh() function is used to clear timer, if call this function before timeout period,
* then MCU reset or WDG interrupt won't generate
*
*****************************************************************************************
* @endverbatim
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup WDG_Exported_Types WDG Exported Types
* @{
*/
/**
* @brief WDG Init structure definition
*/
typedef struct
{
u32 CountProcess; /*!< WDG parameter get from WDG_Scalar, Specifies count id of WDG
This parameter must be set to a value in the 0-11 range */
u32 DivFacProcess; /*!< WDG parameter get from WDG_Scalar, Specifies WDG timeout count divisor factor
This parameter must be set to a value in the 1-65535 range */
u32 RstAllPERI; /*!< WDG parameter, Specifies WDG reset all the PERIs in HS or not
This parameter must be set to a value of 0 or 1 */
} WDG_InitTypeDef;
/**
* @}
*/
/** @defgroup WDG_Exported_Functions WDG Exported Functions
* @{
*/
_LONG_CALL_ void WDG_Scalar(u32 Period, u32 *pCountProcess, u32 *pDivFacProcess);
_LONG_CALL_ void WDG_Init(WDG_InitTypeDef *WDG_InitStruct);
_LONG_CALL_ void WDG_IrqInit(void *handler, u32 Id);
_LONG_CALL_ void WDG_Cmd(u32 NewState);
_LONG_CALL_ void WDG_Refresh(void);
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/**************************************************************************//**
* @defgroup WDG_Register_Definitions WDG Register Definitions
* @{
*****************************************************************************/
/**************************************************************************//**
* @defgroup WDG_REG
* @{
*****************************************************************************/
#define WDG_BIT_ENABLE ((u32)0x00000001 << 16)
#define WDG_BIT_CLEAR ((u32)0x00000001 << 24)
#define WDG_BIT_RST_MODE ((u32)0x00000001 << 30)
#define WDG_BIT_ISR_CLEAR ((u32)0x00000001 << 31)
/** @} */
/** @} */
/**
* @}
*/
/**
* @}
*/
#endif //_RTL8721D_WDG_H_
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_wdg.h
|
C
|
apache-2.0
| 5,203
|
#ifndef __INC_RTL8711B_WL_ON_H
#define __INC_RTL8711B_WL_ON_H
/* this is a subset of hal_com_reg.h */
/* BIT_WL_PMC_OFFMAC 0x0020 */
#define BIT_WL_PMC_OFFMAC (0x00000001 << 1) /*!< Auto FSM to Turn On, include clock, isolation, power control for MAC only
(auto set by ICFG, and clear when Power Ready) */
#define BIT_WL_APMC_ONMAC (0x00000001 << 0) /*!< Auto FSM to Turn On, include clock, isolation, power control for MAC only */
/* REG_WL_RF_PSS 0x005c */
#define BIT_AFE_POWER_MODE_SEL (0x00000001 << 8) /*!< AFE power mode selection:1: LDO mode 0: Power-cut mode */
#define BIT_SEL_LDO_RF (0x00000001 << 2) /*!< Power source selection1: LDO mode (power source is 3.3V,VD33PAD); 0: Power Cut mode (Power source is 1.2V,VDTR). */
#define BIT_SEL_LDO_SYN (0x00000001 << 1) /*!< Power source selection1: LDO mode (power source is 3.3V,VD33SYN); 0: Power Cut mode (Power source is 1.2V,VDSYN). */
#define BIT_SEL_LDO_BUF (0x00000001 << 0) /*!< Power source selection1: LDO mode (power source is 3.3V,VD33SYN); 0: Power Cut mode (Power source is 1.2V,VDSYN). */
/* REG_USB_INDIRECT_CTRL 0x006c */
#define BIT_USB_HOST_INT_REQ (0x00000001 << 31) /*!< For USB doggle mode, USB Host write this bit to 1 will trigger interrupt to CM4. After CM4 finishes handling this interrupt , CM4 will clear this bit to 0 */
//#define BIT_USB_HOST_INT_TYPE (0x00000001 << 30) /*!< 0: read efuse, 1: write efuse, 2: host cmd */
#define BIT_USB_HOST_CMD (0x0000001F << 24) /*!< host cmd val */
/* REG_USB_SIE_IMR 0x0078 */
#define BIT_EFUSE_RD_MSK_CM4 (0x00000001 << 23) /*!< USB host indirect read efuse interrupt mask for cm4 */
#define BIT_USB_SUS_MSK_CM4 (0x00000001 << 22) /*!< USB suspend interrupt mask for cm4 */
#define BIT_USB_RES_MSK_CM4 (0x00000001 << 21) /*!< USB resume interrupt mask for cm4 */
#define BIT_SE0_RST_MSK_CM4 (0x00000001 << 20) /*!< SE0 reset interrupt mask for cm4 */
#define BIT_SIE_ACK_DONE_MSK_CM4 (0x00000001 << 19) /*!< SIE ACK done interrupt mask for cm4 */
#define BIT_SIE_NAK_DONE_MSK_CM4 (0x00000001 << 18) /*!< SIE NAK done interrupt mask for cm4 */
#define BIT_LPM_RSM_MSK_CM4 (0x00000001 << 17) /*!< SIE resume from LPM interrupt mask for cm4 */
#define BIT_LPM_ACT_MSK_CM4 (0x00000001 << 16) /*!< SIE enter LPM interrupt mask for cm4 */
#define BIT_EFUSE_RD_MSK_DW8051 (0x00000001 << 7) /*!< USB host indirect read efuse interrupt mask for dw8051 */
#define BIT_USB_SUS_MSK_DW8051 (0x00000001 << 6) /*!< USB suspend interrupt mask for dw8051 */
#define BIT_USB_RES_MSK_DW8051 (0x00000001 << 5) /*!< USB resume interrupt mask for dw8051 */
#define BIT_SE0_RST_MSK_DW8051 (0x00000001 << 4) /*!< SE0 reset interrupt mask for dw8051 */
#define BIT_SIE_ACK_DONE_MSK_DW8051 (0x00000001 << 3) /*!< SIE ACK done interrupt mask for dw8051 */
#define BIT_SIE_NAK_DONE_MSK_DW8051 (0x00000001 << 2) /*!< SIE NAK done interrupt mask for dw8051 */
#define BIT_LPM_RSM_MSK_DW8051 (0x00000001 << 1) /*!< SIE resume from LPM interrupt mask for dw8051 */
#define BIT_LPM_ACT_MSK_DW8051 (0x00000001 << 0) /*!< SIE enter LPM interrupt mask for dw8051 */
/* REG_USB_SIE_INT 0x007c */
#define BIT_USB_CMD_INT ((u32)(0x00000001 << 7)) /*!< USB host indirect read/write efuse or host cmd interrupt */
#define BIT_USB_SUS_INT ((u32)(0x00000001 << 6)) /*!< USB suspend interrupt */
#define BIT_USB_RES_INT ((u32)(0x00000001 << 5)) /*!< USB resume interrupt */
#define BIT_SE0_RST_INT ((u32)(0x00000001 << 4)) /*!< SE0 reset interrupt */
#define BIT_SIE_ACK_DONE_INT ((u32)(0x00000001 << 3)) /*!< SIE ACK done interrupt */
#define BIT_SIE_NAK_DONE_INT ((u32)(0x00000001 << 2)) /*!< SIE NAK done interrupt */
#define BIT_LPM_RSM_INT ((u32)(0x00000001 << 1)) /*!< SIE resume from LPM interrupt */
#define BIT_LPM_ACT_INT ((u32)(0x00000001 << 0)) /*!< IE enter LPM interrupt */
/* REG_USB_PWR_OPT 0x0088 */
#define BIT_CM4_WAKE_USB ((u32)(0x00000001 << 6)) /*!< R/W 0 cm4 wakeup usb device, 1: wakeup 0: not wakeup */
#define BIT_HOST_WAKE_DEV_EN ((u32)(0x00000001 << 5)) /*!< R/W 0 usb host wake device function enable, 1: Enable, 0:Disable */
#define BIT_HOST_WAKE_DEV ((u32)(0x00000001 << 4)) /*!< R/W 0 usb host wake device, 1: wake */
#define BIT_USB_LPS_BLOCK ((u32)(0x00000001 << 3)) /*!< R/W 0 Block USB RX for wlan is in LPS, 1: Block RX ; 0: Not block */
#define BIT_USB_LPM_NY ((u32)(0x00000001 << 2)) /*!< R/W 0 USB LPM Not Yet */
#define BIT_USB_SUS_DIS ((u32)(0x00000001 << 1)) /*!< R/W 0 Disable USB enter suspend, 1: Disable, 0: enable */
#define BIT_USB_LPMACT_EN ((u32)(0x00000001 << 0)) /*!< R/W 0 Enable USB enter LPM , 1: Enable, 0: Disable */
/* REG_SYS_CFG_8710B 0xF0 */
#define BIT_USB_DOGGLE_MODE ((u32)(0x00000001 << 1)) /*!< 1: enable usb host access wifi mac, this bit should set by host driver */
#define BIT_MCLK_VLD ((u32)(0x00000001 << 0)) /*!< 1: MAC clock ready flag */
#define REG_WL_PMC_CTRL 0x0020
#define REG_WL_RF_PSS 0x005C /*!< select RF power source: LDO:3.3V, PC: 1.2V*/
#define REG_SYS_CFG_8710B 0x00F0
#define REG_USB_INDIRECT_CTRL 0x006C
#define REG_USB_SIE_IMR 0x0078
#define REG_USB_SIE_INT 0x007c
#define REG_WL_PMC_ISR_8711B 0x0084
#define REG_USB_PWR_OPT 0x0088
#define REG_USB_HOST_RW_DATA 0x009C
#define REG_USB_HOST_RW_ADDR 0x00F8
#endif //__INC_RTL8711B_WL_ON_H
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721d_wl_on.h
|
C
|
apache-2.0
| 5,396
|
/**
******************************************************************************
* @file rtl8721dhp_rcc.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for peripheral reset and clock control driver.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_HP_RCC_H_
#define _RTL8721D_HP_RCC_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup RCC
* @brief RCC driver modules
* @{
*/
/** @defgroup HS_RCC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* - functions prototypes for peripheral reset and clock control driver.
*
*****************************************************************************************
*
*****************************************************************************************
* how to use
*****************************************************************************************
* use UART0 as example:
* RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
*
*****************************************************************************************
* @endverbatim
*/
/** @addtogroup HS_RCC
* @brief HS_RCC driver modules
* @{
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HS_RCC_CLK_Exported_Constants HS_RCC CLK Exported Constants
* @{
*/
#define SYS_CLK_CTRL1 0x03 //0x210
#define SYS_CLK_CTRL2 0x02
#define SYS_CLK_CTRL3 0x01
#define SYS_CLK_CTRL4 0x00
#define APBPeriph_CLOCK_NULL 0 //if you dont want to set any clock, you can use this
#define APBPeriph_PSRAM_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HSYS_PSRAM_CKE | BIT_SHIFT_HSYS_PSRAM_CKSL_100)
#define APBPeriph_AUDIOC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HSYS_AC_CK)
#define APBPeriph_VENDOR_REG_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_VNDR_CKE)
#define APBPeriph_USI_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_USI_CKE)
#define APBPeriph_IRDA_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_IRDA_CKE)
#define APBPeriph_IPC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_IPC_CKE)
#define APBPeriph_GTIMER_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_TIMER0_CKE)
#define APBPeriph_SPI1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_SPI1_CKE)
#define APBPeriph_SPI0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_SPI0_CKE)
#define APBPeriph_UART1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_UART1_CKE)
#define APBPeriph_UART0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_UART0_CKE)
#define APBPeriph_BT_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_BT_CKE)
#define APBPeriph_WL_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_WLAN_CKSL_AXIF | BIT_HSYS_WLAN_CKE_AXIF)
#define APBPeriph_GDMA0_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_GDMA0_CKE)
#define APBPeriph_LCDC_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_LCDC_CKE)
#define APBPeriph_I2S0_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_I2S0_CKE)
#define APBPeriph_SEC_ENG_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_IPSEC_CKE)
#define APBPeriph_LXBUS_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_LX1BUS_CKE)
#define APBPeriph_SPORT_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_SPORT_CKE)
#define APBPeriph_OTG_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_USBOTG_CKE)
#define APBPeriph_SDIOH_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_SDH_CKE_SCLK | BIT_HSYS_SDH_CKE_BCLK)
#define APBPeriph_SDIOD_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_SDD_CKE)
/**
* @}
*/
/** @defgroup AON_RCC_CLK_Exported_Constants Exported Constants
* @{
*/
#define APBPeriph_RTC_CLOCK (BIT_AON_RTC_CKE)
#define APBPeriph_CTOUCH_CLOCK (BIT_AON_CTOUCH_CKE)
#define APBPeriph_CK32KGEN_CLOCK (BIT_AON_CK32KGEN_CKE)
#define APBPeriph_KEYSCAN_CLOCK (BIT_AON_KEYSCAN_CKE)
#define APBPeriph_TSF_CLOCK (BIT_AON_TSF_CKE)
/**
* @}
*/
/** @defgroup HS_RCC_FUNC_Exported_Constants HS_RCC FUNC Exported Constants
* @{
*/
#define SYS_FUNC_EN1 0x03 //0x200
#define SYS_FUNC_EN2 0x02 //0x204
#define SYS_FUNC_EN3 0x01 //0x208
#define SYS_FUNC_EN4 0x00 //0x
#define APBPeriph_NULL 0 //if you dont want to set any function, you can use this
#define APBPeriph_PSRAM (SYS_FUNC_EN1 << 30 | BIT_HSYS_PSRAM_FEN)
#define APBPeriph_AUDIOC (SYS_FUNC_EN1 << 30 | BIT_HSYS_AC_FEN)
#define APBPeriph_VENDOR_REG (SYS_FUNC_EN1 << 30 | BIT_HS_VNDR_FEN)
#define APBPeriph_USI_REG (SYS_FUNC_EN1 << 30 | BIT_HS_USI_FEN)
#define APBPeriph_IRDA_REG (SYS_FUNC_EN1 << 30 | BIT_HS_IRDA_FEN)
#define APBPeriph_IPC (SYS_FUNC_EN1 << 30 | BIT_HS_IPC_FEN)
#define APBPeriph_GTIMER (SYS_FUNC_EN1 << 30 | BIT_HS_TIMER0_FEN)
#define APBPeriph_SPI1 (SYS_FUNC_EN1 << 30 | BIT_HS_SPI1_FEN)
#define APBPeriph_SPI0 (SYS_FUNC_EN1 << 30 | BIT_HS_SPI0_FEN)
#define APBPeriph_UART1 (SYS_FUNC_EN1 << 30 | BIT_HS_UART1_FEN_FUN | BIT_HS_UART1_FEN_GLB)
#define APBPeriph_UART0 (SYS_FUNC_EN1 << 30 | BIT_HS_UART0_FEN_FUN | BIT_HS_UART0_FEN_GLB)
#define APBPeriph_BT (SYS_FUNC_EN2 << 30 | BIT_HSYS_BT_FEN)
#define APBPeriph_WL (SYS_FUNC_EN2 << 30 | BIT_HSYS_WLAN_FEN_AXIF)
#define APBPeriph_GDMA0 (SYS_FUNC_EN2 << 30 | BIT_HSYS_GDMA0_FEN)
#define APBPeriph_LCDC (SYS_FUNC_EN2 << 30 | BIT_HSYS_LCDC_FEN)
#define APBPeriph_I2S0 (SYS_FUNC_EN2 << 30 | BIT_HSYS_I2S0_FEN)
#define APBPeriph_SECURITY_ENGINE (SYS_FUNC_EN2 << 30 | BIT_HSYS_IPSEC_FEN)
#define APBPeriph_LXBUS (SYS_FUNC_EN2 << 30 | BIT_HSYS_LX1BUS_FEN)
#define APBPeriph_SPORT (SYS_FUNC_EN3 << 30 | BIT_HSYS_SPORT_FEN)
#define APBPeriph_OTG (SYS_FUNC_EN3 << 30 | BIT_HSYS_USBOTG_FEN)
#define APBPeriph_SDIOH (SYS_FUNC_EN3 << 30 | BIT_HSYS_SDH_FEN_SCKGEN | BIT_HSYS_SDH_FEN)
#define APBPeriph_SDIOD (SYS_FUNC_EN3 << 30 | BIT_HSYS_SDD_FEN_OFF | BIT_HSYS_SDD_FEN_ON)
/**
* @}
*/
/** @defgroup AON_RCC_FUNC_Exported_Constants Exported Constants
* @{
*/
#define APBPeriph_RTC (BIT_AON_RTC_FEN)
#define APBPeriph_CTOUCH (BIT_AON_CTOUCH_FEN)
#define APBPeriph_CK32KGEN (BIT_AON_CK32KGEN_FEN)
#define APBPeriph_KEYSCAN (BIT_AON_KEYSCAN_FEN)
#define APBPeriph_TSF (BIT_AON_TSF_FEN)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HS_RCC_Exported_Functions HS_RCC Exported Functions
* @{
*/
_LONG_CALL_ void RCC_PeriphClockCmd(u32 APBPeriph, u32 APBPeriph_Clock, u8 NewState);
_LONG_CALL_ void RCC_WIFIClockCmd(u8 NewState);
_LONG_CALL_ void RCC_PeriphClockSource_RTC(u32 Xtal);
_LONG_CALL_ void RCC_PeriphClockSource_I2C(UNUSED_WARN_DIS u32 Idx, u32 Source);
_LONG_CALL_ void RCC_PeriphClockSource_QDEC(UNUSED_WARN_DIS u32 Idx, u32 Source);
_LONG_CALL_ void RCC_PeriphClockSource_UART (UART_TypeDef* UARTx, u32 Source);
/**
* @brief Enables or disables the AON APB peripheral clock and function
* @param APBPeriph: specifies the APB peripheral to gates its clock.
* this parameter can be one of @ref AON_RCC_FUNC_Exported_Constants
* @param APBPeriph_Clock: specifies the APB peripheral clock config.
* this parameter can be one of @ref AON_RCC_CLK_Exported_Constants
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
*/
__STATIC_INLINE void RCC_PeriphClockCmd_AON(u32 APBPeriph, u32 APBPeriph_Clock, u8 NewState)
{
u32 TempVal = 0;
//clock
if (APBPeriph_Clock != APBPeriph_CLOCK_NULL) {
if(NewState == ENABLE)
{
TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
TempVal |= APBPeriph_Clock;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
} else {
TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
TempVal &= ~APBPeriph_Clock;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
}
}
if (APBPeriph == APBPeriph_NULL)
return;
//function
if(NewState == ENABLE)
{
TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
TempVal |= APBPeriph;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
} else {
TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
TempVal &= ~APBPeriph;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
}
return;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/* Other definations --------------------------------------------------------*/
#endif /* _RTL8721D_HP_RCC_H_ */
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721dhp_rcc.h
|
C
|
apache-2.0
| 8,951
|
/**
******************************************************************************
* @file rtl8721dhp_sd.h
* @author
* @version V1.0.0
* @date 2018-06-29
* @brief This file contains all the functions prototypes for the SDIOH firmware
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_SDIO_SD_H
#define _RTL8721D_SDIO_SD_H
/** @addtogroup AmebaD_Periph_Driver
* @{
*/
/** @addtogroup SDIOH
* @brief SDIOH driver modules
* @{
*/
/** @addtogroup SDIOH
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* SDIOH:
* - Base Address: SDIOH_BASE
* - IP Clock: 100MHz
* - Support SD Spec. Version 2.0
* - High Voltage SD Memory Card
* – Operating voltage range: 2.7-3.6 V
* - Support 1/4-bit mode SD
* – Bus Speed Mode (using 4 parallel data lines)
* -Default Speed mode: 3.3V signaling, Frequency up to 25 MHz, up to 12.5 MB/sec
* -High Speed mode: 3.3V signaling, Frequency up to 50 MHz, up to 25 MB/sec
* - Support hardware CRC function for SD
*
*****************************************************************************************
* How to use SDIO Host Controller
*****************************************************************************************
* To use the SDIO Host Controller, the following steps are mandatory.
*
* 1. Insert SD card to card slot.
*
* 2. Call SD_Init() function to initialize SDIOH and SD card, in which the following operations are executed:
* (1) Enable SDIOH peripheral clock.
* (2) Configure the SDIOH pinmux.
* (3) Initialize SDIO Host to initial-mode and enable card interrupt.
* (4) If card insert is detected, card identification is started.
* (5) When card identification is successful, card enters into data transfer mode (Default Speed Mode).
* (6) Set SDIOH and card to 4-bit bus width or High Speed mode if needed according to configure parameters.
*
* 3. After initialization, users can call the following functions to read or write blocks.
* SD_RESULT SD_ReadBlocks(u32 sector,u8 *data,u32 count);
* SD_RESULT SD_WriteBlocks(u32 sector,const u8 *data,u32 count);
*
* Note that if users access SD card through FATFS, then the above steps don't need to be implemented manually.
* They are already porting to FATFS low-level driver, and users can call FATFS API directly.
* Details can be found in FATFS example.
*
*****************************************************************************************
* @endverbatim
*/
#define SD 0
#define EMMC 1
#define SDIO SD
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Constants SDIOH Exported Constants
* @{
*/
/** @defgroup SD_Command_Index
* @{
*/
typedef enum
{
SD_CMD_GoIdleSte = 0,
EMMC_CMD_SendOpCond = 1, // CMD only for EMMC
SD_CMD_AllSendCid = 2,
SD_CMD_SendRelAddr = 3,
SD_CMD_SetDsr = 4,
SD_CMD_SwitchFunc = 6,
SD_CMD_SetBusWidth = 6, // ACMD6
SD_CMD_SelDeselCard = 7,
SD_CMD_SendIfCond = 8, // CMD only for SD card
EMMC_CMD_SendExtCsd = 8, // CMD only for EMMC
SD_CMD_SendCsd = 9,
SD_CMD_SendCid = 10,
SD_CMD_VolSwitch = 11, // CMD only for SD card
SD_CMD_StopXsmission = 12,
SD_CMD_SendSts = 13,
SD_CMD_SetBlklen = 16,
SD_CMD_RdSingleBlk = 17,
SD_CMD_RdMulBlk = 18,
SD_CMD_SendTuningBlk = 19, // CMD only for SD card
SD_CMD_SendNumWrBlks = 22, // ACMD22
SD_CMD_SetBlkCnt = 23,
SD_CMD_SetWrBlkEraseCnt = 23, // ACMD23
SD_CMD_WrBlk = 24,
SD_CMD_WrMulBlk = 25,
SD_CMD_ProgCsd = 27,
SD_CMD_EraseBlkSt = 32, // CMD only for SD card
SD_CMD_EraseBlkEd = 33, // CMD only for SD card
EMMC_CMD_EraseAddrSt = 35, // CMD only for EMMC
EMMC_CMD_EraseAddrEd = 36, // CMD only for EMMC
SD_CMD_Erase = 38,
SD_CMD_SdSendOpCond = 41, // ACMD41 cmd only for SD card
SD_CMD_SendScr = 51, // ACMD51 cmd only for SD card
SD_CMD_AppCmd = 55 // CMD only for SD card
} SD_COMMAND;
/**
* @}
*/
/** @defgroup SD_Result
* @{
*/
typedef enum
{
SD_OK = 0,
SD_NODISK,
SD_INSERT,
SD_INITERR,
SD_PROTECTED,
SD_ERROR,
} SD_RESULT;
/**
* @}
*/
/** @defgroup SD_Card_States
* @{
*/
#define SD_CARD_READY 0x00000001
#define SD_CARD_IDENTIFICATION 0x00000002
#define SD_CARD_STANDBY 0x00000003
#define SD_CARD_TRANSFER 0x00000004
#define SD_CARD_SENDING 0x00000005
#define SD_CARD_RECEIVING 0x00000006
#define SD_CARD_PROGRAMMING 0x00000007
#define SD_CARD_DISCONNECTED 0x00000008
#define SD_CARD_ERROR 0x000000FF
/**
* @}
*/
/** @defgroup SD_Specification_Version SD_Specification_Version
* @{
*/
#define SD_SPEC_V101 0
#define SD_SPEC_V110 1
#define SD_SPEC_V200 2
#define SD_SPEC_V300 3
/**
* @}
*/
/** @defgroup SD_Access_Mode SD_Access_Mode
* @{
*/
#define SD_SPEED_DS 0 // 3.3V Function 0
#define SD_SPEED_HS 1 // 3.3V Function 1
#define SD_SPEED_SDR12 2 // 1.8V Function 0
#define SD_SPEED_SDR25 3 // 1.8V Function 1
#define SD_SPEED_SDR50 4 // 1.8V Function 2
#define SD_SPEED_SDR104 5 // 1.8V Function 3
#define SD_SPEED_DDR50 6 // 1.8V Function 4
#define SD_KEEP_CUR_SPEED 15
/**
* @}
*/
/**
* @}
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Types SDIOH Exported Types
* @{
*/
/**
* @brief SD card info structure definition
*/
typedef struct {
u8 csd[SDIOH_CSD_LEN]; /*!< Store the card-specific data(CSD) of the current SD card. */
u16 rca; /*!< Store the relative address(RCA) of the current SD card. */
u8 is_sdhc_sdxc; /*!< Specify the current card is SDSC or SDHC/SDXC. */
u8 sd_spec_ver; /*!< Specify the physical layer specification version of current
card, which would be a value of @ref SD_Specification_Version */
u32 capaticy; /*!< Specify the capacity of current card. Unit: KByte */
u32 read_bl_len; /*!< Specify max. read data block length of current card. Unit: byte */
u32 write_bl_len; /*!< Specify max. write data block length. Unit: byte */
u8 sig_level; /*!< Specify current signal level, 0: 3.3v, 1: 1.8v */
u8 bus_spd; /*!< Specify current bus speed, which would be a value of @ref SD_Access_Mode */
SD_RESULT sd_status; /*!< Specify current sd status, which would be a value of @ref SD_Result */
u8 dma_buf[SDIOH_C6R2_BUF_LEN] __attribute__((aligned(32))); /*!< DMA buffer, 32 byte-alignment */
} SD_CardInfo;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDIOH_Exported_Functions SDIOH Exported Functions
* @{
*/
/** @defgroup SD_Card_Functions SD Card Functions
* @{
*/
_LONG_CALL_ SD_RESULT SD_Init(void);
_LONG_CALL_ SD_RESULT SD_DeInit(void);
_LONG_CALL_ SD_RESULT SD_GetCapacity(u32* sector_count);
_LONG_CALL_ SD_RESULT SD_ReadBlocks(u32 sector,u8 *data,u32 count);
_LONG_CALL_ SD_RESULT SD_WriteBlocks(u32 sector,const u8 *data,u32 count);
_LONG_CALL_ SD_RESULT SD_Status(void);
_LONG_CALL_ SD_RESULT SD_GetEXTCSD(u8 *pbuf);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#define SD_BLOCK_SIZE 512 //Bytes
/* SDIO_RESP4 */
#define SD_APP_CMD BIT(5)
/* SDIO_RESP0 */
#define SD_ADDRESS_ERROR BIT(6)
#define SD_BLOCK_LEN_ERROR BIT(5)
#define SD_WP_VIOLATION BIT(2)
/* SDXC_Power_Control SDXC_Power_Control used in ACMD41*/
#define SD_POWER_SAVING 0
#define SD_MAX_PERFORM 1
/* SD_Switch_1.8v_Request used in ACMD41 */
#define SD_USE_CUR_VOL 0
#define SD_SWITCH_18V 1
/* SD_operation_mode used in CMD6 */
#define SD_CMD6_CHECK_MODE 0
#define SD_CMD6_SWITCH_MODE 1
/* SD_Capacity_Support in ACMD41 */
#define SD_SUPPORT_SDSC_ONLY 0
#define SD_SUPPORT_SDHC_SDXC 1
typedef struct {
u8 sdioh_bus_speed; /*!< Specify SDIO Host bus speed, should be SD_SPEED_DS or SD_SPEED_HS*/
u8 sdioh_bus_width; /*!< Specify SDIO Host bus width, should be a value of @ref SDIOH_Bus_Width */
u32 sdioh_cd_pin; /*!< Specify Card Detect pin, should be a value of _PB_25/_PA_6/_PNC */
u32 sdioh_wp_pin; /*!< Specify Write Protection pin, should be a value of _PB_25/_PA_6/_PNC */
} SDIOHCFG_TypeDef;
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721dhp_sd.h
|
C
|
apache-2.0
| 9,180
|
/**
******************************************************************************
* @file rtl8721dlp_km4.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for km0 control km4.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_LP_KM4_H_
#define _RTL8721D_LP_KM4_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup KM0_CTRL_KM4
* @brief KM0_CTRL_KM4 driver modules
* @{
*/
/** @addtogroup KM0_CTRL_KM4
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* - functions prototypes for for km0 control km4.
*
*****************************************************************************************
*
*****************************************************************************************
* how to use
*****************************************************************************************
*
*****************************************************************************************
* @endverbatim
*/
/* Exported Types --------------------------------------------------------*/
/** @defgroup km4_sleep_parameter km4 sleep parameter
* @{
*/
#ifndef CONFIG_BUILD_ROM
typedef struct
{
u8 dlps_enable;
u8 sleep_type;
u32 sleep_time;
} KM4SLEEP_ParamDef;
#endif
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup KM4_CTRL_Exported_Functions KM4_CTRL Exported Functions
* @{
*/
void km4_pm_init(void);
void km4_boot_on(void);
u32 km4_suspend(u32 type);
void km4_resume(void);
u32 km4_status_on(void);
void km4_set_wake_event(u32 wevt);
u32 km4_get_wake_event(void);
void km4_wake_event_update(void);
void km4_tickless_ipc_int(VOID *Data, u32 IrqStatus, u32 ChanNum);
void km4_flash_highspeed_resume(u32 Protection);
void km4_flash_highspeed_suspend(u32 Protection);
void km4_flash_highspeed_init(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/* Other definations --------------------------------------------------------*/
extern u8 km4_sleep_type;
extern u32 km4_sleep_timeout;
extern void flash_operation_config(void);
#endif /* _RTL8721D_LP_KM4_H_ */
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721dlp_km4.h
|
C
|
apache-2.0
| 2,962
|
/**
******************************************************************************
* @file rtl8721dlp_rcc.h
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for peripheral reset and clock control driver.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#ifndef _RTL8721D_LP_RCC_H_
#define _RTL8721D_LP_RCC_H_
/** @addtogroup AmebaD_Platform
* @{
*/
/** @defgroup RCC
* @brief RCC driver modules
* @{
*/
/** @defgroup LP_RCC
* @verbatim
*****************************************************************************************
* Introduction
*****************************************************************************************
* - functions prototypes for peripheral reset and clock control driver.
*
*****************************************************************************************
*
*****************************************************************************************
* how to use
*****************************************************************************************
* use UART0 as example:
* RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
*
*****************************************************************************************
* @endverbatim
*/
/** @addtogroup LP_RCC
* @brief LP_RCC driver modules
* @{
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LP_RCC_CLK_Exported_Constants LP_RCC CLK Exported Constants
* @{
*/
#define SYS_CLK_CTRL0 0x00 //0x210
#define SYS_CLK_CTRL1 0x01 //0x214
#define SYS_CLK_CTRL2 0x02 //0x004 AON
#define SYS_CLK_CTRL3 0x03 //TODO
#define APBPeriph_CLOCK_NULL 0 //if you dont want to set any clock, you can use this
#define APBPeriph_WLON_CLOCK (SYS_CLK_CTRL0 << 30 | BIT_LSYS_WLON_CKE)
#define APBPeriph_FLASH_CLOCK (SYS_CLK_CTRL0 << 30 | BIT_FLASH_CKE)
#define APBPeriph_GDMA0_CLOCK (SYS_CLK_CTRL0 << 30 | BIT_LSYS_GDMA0_CKE)
#define APBPeriph_EFUSE_CLOCK (SYS_CLK_CTRL0 << 30 | BIT_SYSON_CK_EELDR_EN)
#define APBPeriph_GPIO_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_GPIO0_CKE)
#define APBPeriph_QDEC0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_QDEC0_CKE)
#define APBPeriph_SGPIO_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_SPGIO0_CKE)
#define APBPeriph_I2C0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_I2C0_CKE)
#define APBPeriph_ADC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_ADC_CKE)
#define APBPeriph_UART1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_UART1_CKE)
#define APBPeriph_LOGUART_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_UART0_CKE)
#define APBPeriph_GTIMER_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_TIMER0_CKE)
#define APBPeriph_IPC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_LSYS_IPC_CKE)
#define APBPeriph_VENDOR_REG_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_VENDOR_CKE)
#define APBPeriph_RTC_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_AON_RTC_CKE)
#define APBPeriph_CTOUCH_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_AON_CTOUCH_CKE)
#define APBPeriph_CK32KGEN_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_AON_CK32KGEN_CKE)
#define APBPeriph_KEYSCAN_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_AON_KEYSCAN_CKE)
#define APBPeriph_TSF_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_AON_TSF_CKE)
/* Switch SPIC clock using RCC_PeriphClockSource_SPIC(), don't use the following macro. Because SPIC has RCC_PeriphClockCmd has bug. */
#define APBPeriph_FLASH_CLOCK_ANA4M (SYS_CLK_CTRL0 << 30 | BIT_FLASH_CKE | BIT_SHIFT_FLASH_CLK_ANA4M)
#define APBPeriph_FLASH_CLOCK_XTAL (SYS_CLK_CTRL0 << 30 | BIT_FLASH_CKE | BIT_SHIFT_FLASH_CLK_XTAL)
#define APBPeriph_FLASH_CLOCK_PLL (SYS_CLK_CTRL0 << 30 | BIT_FLASH_CKE | BIT_SHIFT_FLASH_CLK_PLL)
/**
* @}
*/
/** @defgroup LP_RCC_FUNC_Exported_Constants LP_RCC FUNC Exported Constants
* @{
*/
#define SYS_FUNC_EN0 0x03 //0x208
#define SYS_FUNC_EN1 0x02 //0x20C
#define SYS_FUNC_EN2 0x01 //0x004 AON
#define SYS_FUNC_EN3 0x00 //TODO
#define APBPeriph_NULL 0 //if you dont want to set any function, you can use this
#define APBPeriph_WLON (SYS_FUNC_EN0 << 30 | BIT_LSYS_WLON_FEN)
#define APBPeriph_FLASH (SYS_FUNC_EN0 << 30 | BIT_FLASH_FUN_EN)
#define APBPeriph_GDMA0 (SYS_FUNC_EN0 << 30 | BIT_LSYS_GDMA0_FEN)
#define APBPeriph_EFUSE (SYS_FUNC_EN0 << 30 | BIT_SYS_FEN_EELDR)
#define APBPeriph_GPIO (SYS_FUNC_EN1 << 30 | BIT_LSYS_GPIO0_FEN)
#define APBPeriph_QDEC0 (SYS_FUNC_EN1 << 30 | BIT_LSYS_QDEC0_FEN)
#define APBPeriph_SGPIO (SYS_FUNC_EN1 << 30 | BIT_LSYS_SPGIO0_FEN)
#define APBPeriph_I2C0 (SYS_FUNC_EN1 << 30 | BIT_LSYS_I2C0_FEN)
#define APBPeriph_ADC (SYS_FUNC_EN1 << 30 | BIT_LSYS_ADC_FEN)
#define APBPeriph_UART1 (SYS_FUNC_EN1 << 30 | BIT_LSYS_UART1_FEN_GLB | BIT_LSYS_UART1_FEN_FUN)
#define APBPeriph_LOGUART (SYS_FUNC_EN1 << 30 | BIT_LSYS_UART0_FEN_GLB | BIT_LSYS_UART0_FEN_FUN)
#define APBPeriph_GTIMER (SYS_FUNC_EN1 << 30 | BIT_LSYS_TIMER0_FEN)
#define APBPeriph_IPC (SYS_FUNC_EN1 << 30 | BIT_LSYS_IPC_FEN)
#define APBPeriph_VENDOR_REG (SYS_FUNC_EN1 << 30 | BIT_VENDOR_EN)
#define APBPeriph_RTC (SYS_FUNC_EN2 << 30 | BIT_AON_RTC_FEN)
#define APBPeriph_CTOUCH (SYS_FUNC_EN2 << 30 | BIT_AON_CTOUCH_FEN)
#define APBPeriph_CK32KGEN (SYS_FUNC_EN2 << 30 | BIT_AON_CK32KGEN_FEN)
#define APBPeriph_KEYSCAN (SYS_FUNC_EN2 << 30 | BIT_AON_KEYSCAN_FEN)
#define APBPeriph_TSF (SYS_FUNC_EN2 << 30 | BIT_AON_TSF_FEN)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LP_RCC_Exported_Functions LP_RCC Exported Functions
* @{
*/
_LONG_CALL_ void RCC_PeriphClockCmd(u32 APBPeriph, u32 APBPeriph_Clock, u8 NewState);
_LONG_CALL_ void RCC_PeriphClockSource_RTC(u32 Xtal);
_LONG_CALL_ void RCC_PeriphClockSource_I2C(UNUSED_WARN_DIS u32 Idx, u32 Source);
_LONG_CALL_ void RCC_PeriphClockSource_QDEC(UNUSED_WARN_DIS u32 Idx, u32 Source);
_LONG_CALL_ void RCC_PeriphClockSource_UART (UART_TypeDef* UARTx, u32 Source);
/**
* @brief Configure SPIC Clock.
* @param Source: This parameter can be one of the following values:
* @arg BIT_SHIFT_FLASH_CLK_ANA4M
* @arg BIT_SHIFT_FLASH_CLK_XTAL
* @arg BIT_SHIFT_FLASH_CLK_PLL
* @retval None
* @note Used to switch SPIC clock
*/
__STATIC_INLINE void RCC_PeriphClockSource_SPIC (u32 Source)
{
u32 Temp = 0;
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL0);
Temp &= ~ (BIT_MASK_FLASH_CLK_SEL << BIT_SHIFT_FLASH_CLK_SEL);
Temp |= Source;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL0, Temp);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Registers Definitions --------------------------------------------------------*/
/* Other definations --------------------------------------------------------*/
#endif /* _RTL8721D_LP_RCC_H_ */
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/rtl8721dlp_rcc.h
|
C
|
apache-2.0
| 7,352
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _SECTION_CONFIG_H_
#define _SECTION_CONFIG_H_
#include "basic_types.h"
#define RAM_VECTOR_TABLE1_SECTION \
SECTION(".ram_vector_table1")
#define RAM_VECTOR_TABLE2_SECTION \
SECTION(".ram_vector_table2")
#define RAM_VECTOR_TABLE3_SECTION \
SECTION(".ram_vector_table3")
//3 //3 Hal Section
#define HAL_ROM_TEXT_SECTION \
SECTION(".hal.rom.text")
#define HAL_ROM_ENTRY_NS_SECTION \
SECTION(".hal.rom.entryns.rodata")
#define SIM_ROM_DATA_SECTION \
SECTION(".sim.rom.rodata")
#define HAL_ROM_DATA_SECTION \
SECTION(".hal.rom.rodata")
#define HAL_ROM_BSS_SECTION \
SECTION(".hal.rom.bss")
#define HAL_ROM_BSS_SECTION_BANK \
SECTION(".hal.rom.bank.bss")
#define BOOT_RAM_TEXT_SECTION \
SECTION(".boot.ram.text")
#define BOOT_RAM_RODATA_SECTION \
SECTION(".boot.rodata")
#define BOOT_RAM_DATA_SECTION \
SECTION(".boot.ram.data")
#define BOOT_RAM_BSS_SECTION \
SECTION(".boot.ram.bss")
#define BOOT_RAM_END_BSS_SECTION \
SECTION(".boot.ram.end.bss")
//3 Shell
#if defined (ARM_CORE_CM0)
#define SHELL_ROM_TEXT_SECTION HAL_ROM_TEXT_SECTION
#define SHELL_ROM_BSS_SECTION HAL_ROM_BSS_SECTION
#define SHELL_ROM_DATA_SECTION HAL_ROM_DATA_SECTION
#else
#define SHELL_ROM_TEXT_SECTION
#define SHELL_ROM_BSS_SECTION
#define SHELL_ROM_DATA_SECTION
#endif
#define CMD_TABLE_DATA_SECTION \
SECTION(".cmd.table.data")
//3 Image 1 data
#define IMAGE1_ENTRY_SECTION \
SECTION(".image1.entry.data")
#define IMAGE1_VALID_PATTEN_SECTION \
SECTION(".image1.validate.rodata")
#define IMAGE1_DATA_SECTION \
SECTION(".image1.rodata")
#define IMAGE2_VALID_PATTEN_SECTION \
SECTION(".image2.validate.rodata")
//3 SRAM Config Section
#define SRAM_BD_DATA_SECTION \
SECTION(".bdsram.data")
#define SRAM_NOCACHE_DATA_SECTION \
SRAM_BD_DATA_SECTION
#define SRAM_BF_DATA_SECTION \
SECTION(".bfsram.data")
#define IMAGE2_ENTRY_SECTION \
SECTION(".image2.entry.data")
#define IMAGE2_RAM_TEXT_SECTION \
SECTION(".image2.ram.text")
#define SDRAM_DATA_SECTION
#if defined (ARM_CORE_CM4)
#define PSRAM_TEXT_SECTION SECTION(".psram.text")
#define PSRAM_DATA_SECTION SECTION(".psram.data")
#define PSRAM_RODATA_SECTION SECTION(".psram.rodata")
#define PSRAM_BSS_SECTION SECTION(".psram.bss")
#define PSRAM_HEAP_SECTION SECTION(".psram.heap")
#endif
//3 Wlan Section
#define WLAN_ROM_TEXT_SECTION
#define WLAN_ROM_DATA_SECTION
#define WLAN_RAM_MAP_SECTION
#undef CONFIG_WIFI_CRITICAL_CODE_SECTION
#define CONFIG_WIFI_CRITICAL_CODE_SECTION IMAGE2_RAM_TEXT_SECTION
#define CONFIG_FW_CRITICAL_CODE_SECTION //IMAGE2_RAM_TEXT_SECTION
//3 Apple Section
#define APPLE_ROM_TEXT_SECTION \
SECTION(".apple.rom.text")
#define APPLE_ROM_DATA_SECTION \
SECTION(".apple.rom.rodata")
//3 Libc Section
#define LIBC_ROM_TEXT_SECTION \
SECTION(".libc.rom.text")
#define LIBC_ROM_DATA_SECTION \
SECTION(".libc.rom.rodata")
#define LIBC_HEAP_SECTION \
SECTION(".heap.stdlib")
//3 SSL Section
#define SSL_ROM_TEXT_SECTION \
SECTION(".ssl.rom.text")
#define SSL_ROM_DATA_SECTION \
SECTION(".ssl.rom.rodata")
#define SSL_RAM_MAP_SECTION \
SECTION(".ssl_ram_map")
//OS Section
#define OS_ROM_TEXT_SECTION \
SECTION(".os.rom.text")
#define OS_ROM_DATA_SECTION \
SECTION(".os.rom.rodata")
//FLASH RUN CODE
#define FLASH_BOOT_TEXT_SECTION SECTION(".flashboot.text")
#define IMAGE2_CUSTOM_SIGNATURE SECTION(".img2_custom_signature") /* 32B: for OTA update */
//RDP (read protect area just text)
#define RDP_TEXT_SECTION SECTION(".rdp.ram.text")
#define RDP_DATA_SECTION SECTION(".rdp.ram.data")
#define RETENTION_TEXT_SECTION SECTION(".retention.ram.text")
#define RETENTION_DATA_SECTION SECTION(".retention.ram.data")
#define RETENTION_ENTRY_SECTION SECTION(".retention.entry.data")
/* rom map */
#define ROM_FUNCTION_MAP SECTION(".rommap.data")
//3 FW Section
#define FW_ROM_TEXT_SECTION \
SECTION(".FW.rom.text")
#define FW_ROM_DATA_SECTION \
SECTION(".FW.rom.rodata")
#define FW_ROM_BSS_SECTION \
SECTION(".FW.rom.bss")
#define FW_RAM_TEXT_SECTION \
SECTION(".FW.ram.text")
#define FW_RAM_DATA_SECTION \
SECTION(".FW.ram.rodata")
#define FW_RAM_BSS_SECTION \
SECTION(".FW.ram.bss")
/* image3 secure image */
#define IMAGE3_ENTRY_SECTION \
SECTION(".image3.nsc_entry.text")
/*USB_OTG define*/
#define OTG_ROM_TEXT_SECTION
#define START_OTG_RAM_FUN_SECTION
#define START_OTG_RAM_DATA_SECTION
#define OTG_ROM_DATA_SECTION
#endif //_SECTION_CONFIG_H_
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/section_config.h
|
C
|
apache-2.0
| 5,750
|
/**
******************************************************************************
* @file rtl8721d_adc.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* - Initialization and Configuration
* - Analog configuration
* - Mode configuration
* - Interrupts and flags management
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief Initializes the parameters in the ADC_InitStruct with default values.
* @param ADC_InitStruct: pointer to a ADC_InitTypeDef structure that contains
* the configuration information for the ADC peripheral.
* @retval None
*/
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
{
u8 i;
ADC_InitStruct->ADC_OpMode = ADC_SW_TRI_MODE;
ADC_InitStruct->ADC_ClkDiv = ADC_CLK_DIV_12;
ADC_InitStruct->ADC_RxThresholdLevel = 0;
ADC_InitStruct->ADC_DMAThresholdLevel = 7;
ADC_InitStruct->ADC_CvlistLen = ADC_CH_NUM - 1;
ADC_InitStruct->ADC_ChanInType = 0;
ADC_InitStruct->ADC_SpecialCh = 0xFF;
ADC_InitStruct->ADC_ChIDEn = DISABLE;
for(i = 0; i < ADC_InitStruct->ADC_CvlistLen + 1; i++)
ADC_InitStruct->ADC_Cvlist[i] = i;
}
/**
* @brief Initializes the ADC according to the specified parameters in ADC_InitStruct.
* @param ADC_InitStruct: pointer to a ADC_InitTypeDef structure that contains
* the configuration information for the ADC peripheral.
* @retval None
*/
void ADC_Init(ADC_InitTypeDef* ADC_InitStruct)
{
ADC_TypeDef *adc = ADC;
u32 value = 0;
u8 len, i;
assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_OpMode));
assert_param(IS_ADC_SAMPLE_CLK(ADC_InitStruct->ADC_ClkDiv));
assert_param(ADC_InitStruct->ADC_CvlistLen < 16);
/* Disable ADC, clear pending interrupt, clear FIFO */
ADC_Cmd(DISABLE);
adc->ADC_INTR_CTRL= 0;
ADC_INTClear();
ADC_ClearFIFO();
/* Set clock divider */
adc->ADC_CLK_DIV = (u32)ADC_InitStruct->ADC_ClkDiv & BIT_MASK_CLK_DIV;
/* Set adc configuration*/
value = adc->ADC_CONF & (~(BIT_MASK_CVLIST_LEN | BIT_MASK_OP_MODE));
value |= (ADC_InitStruct->ADC_OpMode << BIT_SHIFT_OP_MODE) | \
(ADC_InitStruct->ADC_CvlistLen << BIT_SHIFT_CVLIST_LEN);
adc->ADC_CONF = value;
/* Set channel input type */
adc->ADC_IN_TYPE = ADC_InitStruct->ADC_ChanInType;
/* Set channel switch list */
value = 0;
len = ((ADC_InitStruct->ADC_CvlistLen + 1) > 8) ? 8 : (ADC_InitStruct->ADC_CvlistLen + 1);
for(i = 0; i < len; i++) {
value |= (u32)(ADC_InitStruct->ADC_Cvlist[i] << BIT_SHIFT_CHSW0(i));
}
adc->ADC_CHSW_LIST[0] = value;
value = 0;
if((ADC_InitStruct->ADC_CvlistLen + 1) > 8) {
for(i = 8; i < (ADC_InitStruct->ADC_CvlistLen + 1); i++)
value |= (u32)(ADC_InitStruct->ADC_Cvlist[i] << BIT_SHIFT_CHSW1(i));
}
adc->ADC_CHSW_LIST[1] = value;
/* Set particular channel */
if(ADC_InitStruct->ADC_SpecialCh < ADC_CH_NUM) {
ADC_INTConfig(BIT_ADC_IT_CHCV_END_EN, ENABLE);
adc->ADC_IT_CHNO_CON = (u32)ADC_InitStruct->ADC_SpecialCh;
}
/* Set FIFO full level */
adc->ADC_FULL_LVL = (u32)ADC_InitStruct->ADC_RxThresholdLevel;
/* Set DMA level */
value = adc->ADC_DMA_CON & (~BIT_MASK_DMA_LVL);
value |= (ADC_InitStruct->ADC_DMAThresholdLevel << BIT_SHIFT_DMA_LVL);
adc->ADC_DMA_CON = value;
/* Set channel ID included in data or not */
if(ADC_InitStruct->ADC_ChIDEn)
adc->ADC_DELAY_CNT |= BIT_ADC_DAT_CHID;
}
/**
* @brief Enable or Disable the ADC peripheral.
* @param NewState: new state of the ADC peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ADC_Cmd(u32 NewState)
{
ADC_TypeDef *adc = ADC;
if(NewState != DISABLE)
adc->ADC_CONF |= BIT_ADC_ENABLE;
else {
adc->ADC_CONF &= ~BIT_ADC_ENABLE;
/* Need to clear FIFO, or there will be waste data in FIFO next time ADC is enable. Ameba-D A-cut bug */
ADC_ClearFIFO();
}
}
/**
* @brief ENABLE/DISABLE the ADC interrupt bits.
* @param ADC_IT: specifies the ADC interrupt to be setup.
* This parameter can be one or combinations of the following values:
* @arg BIT_ADC_IT_COMP_CH10_EN: ADC channel 10 compare interrupt
* @arg BIT_ADC_IT_COMP_CH9_EN: ADC channel 9 compare interrupt
* @arg BIT_ADC_IT_COMP_CH8_EN: ADC channel 8 compare interrupt
* @arg BIT_ADC_IT_COMP_CH7_EN: ADC channel 7 compare interrupt
* @arg BIT_ADC_IT_COMP_CH6_EN: ADC channel 6 compare interrupt
* @arg BIT_ADC_IT_COMP_CH5_EN: ADC channel 5 compare interrupt
* @arg BIT_ADC_IT_COMP_CH4_EN: ADC channel 4 compare interrupt
* @arg BIT_ADC_IT_COMP_CH3_EN: ADC channel 3 compare interrupt
* @arg BIT_ADC_IT_COMP_CH2_EN: ADC channel 2 compare interrupt
* @arg BIT_ADC_IT_COMP_CH1_EN: ADC channel 1 compare interrupt
* @arg BIT_ADC_IT_COMP_CH0_EN: ADC channel 0 compare interrupt
* @arg BIT_ADC_IT_ERR_EN: ADC error state interrupt
* @arg BIT_ADC_IT_DAT_OVW_EN: ADC data overwritten interrupt
* @arg BIT_ADC_IT_FIFO_EMPTY_EN: ADC FIFO empty interrupt
* @arg BIT_ADC_IT_FIFO_OVER_EN: ADC FIFO overflow interrupt
* @arg BIT_ADC_IT_FIFO_FULL_EN: ADC FIFO full interrupt
* @arg BIT_ADC_IT_CHCV_END_EN: ADC particular channel conversion done interrupt
* @arg BIT_ADC_IT_CV_END_EN: ADC conversion end interrupt
* @arg BIT_ADC_IT_CVLIST_END_EN: ADC conversion list end interrupt
* @param NewState: ENABLE/DISABLE.
* @retval None
*/
void ADC_INTConfig(u32 ADC_IT, u32 NewState)
{
ADC_TypeDef *adc = ADC;
if(NewState != DISABLE) {
adc->ADC_INTR_CTRL |= ADC_IT;
} else {
adc->ADC_INTR_CTRL &= ~ADC_IT;
}
}
/**
* @brief Clears all the ADC interrupt pending bits.
* @param None
* @retval None
* @note This function can also used to clear raw status.
*/
void ADC_INTClear(void)
{
ADC_TypeDef *adc = ADC;
/* Clear the all IT pending Bits */
adc->ADC_INTR_STS = BIT_ADC_IT_ALL_STS;
}
/**
* @brief Clears the ADC interrupt pending bits.
* @param ADC_IT: specifies the pending bit to clear.
* This parameter can be any combination of the following values:
* @arg BIT_ADC_IT_COMP_CH10_STS
* @arg BIT_ADC_IT_COMP_CH9_STS
* @arg BIT_ADC_IT_COMP_CH8_STS
* @arg BIT_ADC_IT_COMP_CH7_STS
* @arg BIT_ADC_IT_COMP_CH6_STS
* @arg BIT_ADC_IT_COMP_CH5_STS
* @arg BIT_ADC_IT_COMP_CH4_STS
* @arg BIT_ADC_IT_COMP_CH3_STS
* @arg BIT_ADC_IT_COMP_CH2_STS
* @arg BIT_ADC_IT_COMP_CH1_STS
* @arg BIT_ADC_IT_COMP_CH0_STS
* @arg BIT_ADC_IT_ERR_STS
* @arg BIT_ADC_IT_DAT_OVW_STS
* @arg BIT_ADC_IT_FIFO_EMPTY_STS
* @arg BIT_ADC_IT_FIFO_OVER_STS
* @arg BIT_ADC_IT_FIFO_FULL_STS
* @arg BIT_ADC_IT_CHCV_END_STS
* @arg BIT_ADC_IT_CV_END_STS
* @arg BIT_ADC_IT_CVLIST_END_STS
* @retval None
*/
void ADC_INTClearPendingBits(u32 ADC_IT)
{
ADC_TypeDef *adc = ADC;
adc->ADC_INTR_STS = ADC_IT;
}
/**
* @brief Get ADC interrupt status.
* @param None
* @retval Current Interrupt Status, each bit of this value represents one
* interrupt status which is as follows:
* @arg BIT_ADC_IT_COMP_CH10_STS
* @arg BIT_ADC_IT_COMP_CH9_STS
* @arg BIT_ADC_IT_COMP_CH8_STS
* @arg BIT_ADC_IT_COMP_CH7_STS
* @arg BIT_ADC_IT_COMP_CH6_STS
* @arg BIT_ADC_IT_COMP_CH5_STS
* @arg BIT_ADC_IT_COMP_CH4_STS
* @arg BIT_ADC_IT_COMP_CH3_STS
* @arg BIT_ADC_IT_COMP_CH2_STS
* @arg BIT_ADC_IT_COMP_CH1_STS
* @arg BIT_ADC_IT_COMP_CH0_STS
* @arg BIT_ADC_IT_ERR_STS
* @arg BIT_ADC_IT_DAT_OVW_STS
* @arg BIT_ADC_IT_FIFO_EMPTY_STS
* @arg BIT_ADC_IT_FIFO_OVER_STS
* @arg BIT_ADC_IT_FIFO_FULL_STS
* @arg BIT_ADC_IT_CHCV_END_STS
* @arg BIT_ADC_IT_CV_END_STS
* @arg BIT_ADC_IT_CVLIST_END_STS
*/
u32 ADC_GetISR(void)
{
ADC_TypeDef *adc = ADC;
return adc->ADC_INTR_STS;
}
/**
* @brief Get ADC raw interrupt status.
* @param None
* @retval Current Raw Interrupt Status, each bit of this value represents one
* raw interrupt status which is as follows:
* @arg BIT_ADC_IT_COMP_CH10_RAW_STS
* @arg BIT_ADC_IT_COMP_CH9_RAW_STS
* @arg BIT_ADC_IT_COMP_CH8_RAW_STS
* @arg BIT_ADC_IT_COMP_CH7_RAW_STS
* @arg BIT_ADC_IT_COMP_CH6_RAW_STS
* @arg BIT_ADC_IT_COMP_CH5_RAW_STS
* @arg BIT_ADC_IT_COMP_CH4_RAW_STS
* @arg BIT_ADC_IT_COMP_CH3_RAW_STS
* @arg BIT_ADC_IT_COMP_CH2_RAW_STS
* @arg BIT_ADC_IT_COMP_CH1_RAW_STS
* @arg BIT_ADC_IT_COMP_CH0_RAW_STS
* @arg BIT_ADC_IT_ERR_RAW_STS
* @arg BIT_ADC_IT_DAT_OVW_RAW_STS
* @arg BIT_ADC_IT_FIFO_EMPTY_RAW_STS
* @arg BIT_ADC_IT_FIFO_OVER_RAW_STS
* @arg BIT_ADC_IT_FIFO_FULL_RAW_STS
* @arg BIT_ADC_IT_CHCV_END_RAW_STS
* @arg BIT_ADC_IT_CV_END_RAW_STS
* @arg BIT_ADC_IT_CVLIST_END_RAW_STS
*/
u32 ADC_GetRawISR(void)
{
ADC_TypeDef *adc = ADC;
return adc->ADC_INTR_RAW_STS;
}
/**
* @brief Get the number of valid entries in ADC receive FIFO.
* @param None.
* @retval The number of valid entries in receive FIFO.
*/
u32 ADC_GetRxCount(void)
{
ADC_TypeDef *adc = ADC;
return adc->ADC_FLR & BIT_MASK_FLR;
}
/**
* @brief Get the last ADC used channel.
* @param None.
* @retval The last ADC used channel index.
*/
u32 ADC_GetLastChan(void)
{
ADC_TypeDef *adc = ADC;
return adc->ADC_LAST_CH;
}
/**
* @brief Get comparison result of ADC channel.
* @param ADC_Channel: The channel index
* @retval The comparison result of specified ADC channel.
*/
u32 ADC_GetCompStatus(u8 ADC_Channel)
{
ADC_TypeDef *adc = ADC;
u32 value = (adc->ADC_COMP_STS & BIT_MASK_COMP_STS_CH(ADC_Channel)) \
>> BIT_SHIFT_COMP_STS_CH(ADC_Channel);
return value;
}
/**
* @brief Set ADC channel threshold and criteria for comparison.
* @param ADC_channel: can be a value of @ref ADC_Chn_Selection as following:
* @arg ADC_CH0
* @arg ADC_CH1
* @arg ADC_CH2
* @arg ADC_CH3
* @arg ADC_CH4
* @arg ADC_CH5
* @arg ADC_CH6
* @arg ADC_CH7
* @arg ADC_CH8
* @arg ADC_CH9
* @arg ADC_CH10
* @param CompThresH: the higher threshold of channel for ADC automatic comparison
* @param CompThresH: the lower threshold of channel for ADC automatic comparison
* @param CompCtrl: This parameter can be a value of @ref ADC_Compare_Control_Definitions as following:
* @arg ADC_COMP_SMALLER_THAN_THL: less than the lower threshold
* @arg ADC_COMP_GREATER_THAN_THH: greater than the higher threshod
* @arg ADC_COMP_WITHIN_THL_AND_THH: between the lower and higher threshod
* @arg ADC_COMP_OUTSIDE_THL_AND_THH: out the range of the higher and lower threshod
* @retval None
*/
void ADC_SetComp(u8 ADC_channel, u16 CompThresH, u16 CompThresL, u8 CompCtrl)
{
ADC_TypeDef *adc = ADC;
u32 value;
assert_param(IS_ADC_CHN_SEL(ADC_channel));
assert_param(IS_ADC_VALID_COMP_TH(CompThresH));
assert_param(IS_ADC_VALID_COMP_TH(CompThresL));
assert_param(IS_ADC_COMP_CRITERIA(CompCtrl));
/* Set ADC channel threshold for comparison */
adc->ADC_COMP_TH_CH[ADC_channel] =
(u32)(CompThresH << BIT_SHIFT_COMP_TH_H) | (CompThresL << BIT_SHIFT_COMP_TH_L);
/* Set ADC channel comparison criteria */
value = adc->ADC_COMP_CTRL;
value &= ~ BIT_MASK_COMP_CTRL_CH(ADC_channel);
value |= (CompCtrl << BIT_SHIFT_COMP_CTRL_CH(ADC_channel));
adc->ADC_COMP_CTRL = value;
/* Enable comparison interrupt */
ADC_INTConfig(BIT_ADC_IT_COMP_CH_EN(ADC_channel), ENABLE);
}
/**
* @brief Reset the channel switch to default state.
* @param None
* @retval None
*/
void ADC_ResetCSwList(void)
{
ADC_TypeDef *adc = ADC;
adc->ADC_RST_LIST = BIT_ADC_RST_LIST;
adc->ADC_RST_LIST = 0;
}
/**
* @brief Detemine ADC FIFO is empty or not.
* @param None.
* @retval ADC FIFO is empty or not:
* - 0: Not Empty
* - 1: Empty
*/
u32 ADC_Readable(void)
{
u32 Status = ADC_GetStatus();
u32 Readable = (((Status & BIT_ADC_FIFO_EMPTY) == 0) ? 1 : 0);
return Readable;
}
/**
* @brief Read data from ADC receive FIFO .
* @param None
* @retval The conversion data.
*/
u16 ADC_Read(void)
{
u16 value = (u16)(ADC->ADC_DATA_GLOBAL & (BIT_MASK_DAT_GLOBAL | BIT_MASK_DAT_CHID));
return value;
}
/**
* @brief Continuous Read data in auto mode.
* @param pBuf: pointer to buffer to keep sample data
* @param len: the number of sample data to be read
* @retval None.
*/
void ADC_ReceiveBuf(u16 *pBuf, u32 len)
{
u32 i = 0;
ADC_AutoCSwCmd(ENABLE);
for(i = 0; i < len; i++){
while(ADC_Readable() == 0);
pBuf[i] = ADC_Read();
}
ADC_AutoCSwCmd(DISABLE);
}
/**
* @brief Clear ADC FIFO.
* @param None
* @retval None
*/
void ADC_ClearFIFO(void)
{
ADC->ADC_CLR_FIFO = 1;
ADC->ADC_CLR_FIFO = 0;
}
/**
* @brief Get ADC status.
* @param None
* @retval Current status,each bit of this value represents one status which is as follows:
*
* bit 2 : BIT_ADC_FIFO_EMPTY ADC FIFO Empty.
* - 0: FIFO in ADC is not empty
* - 1: FIFO in ADC is empty
*
* bit 1 : BIT_ADC_FIFO_FULL_REAL ADC FIFO real full flag.
* - 0: FIFO in ADC is not full real
* - 1: FIFO in ADC is full real
*
* bit 0 : BIT_ADC_BUSY_STS ADC busy Flag.
* - 0: The ADC is ready
* - 1: The ADC is busy
*/
u32 ADC_GetStatus(void)
{
ADC_TypeDef *adc = ADC;
return adc->ADC_BUSY_STS;
}
/**
* @brief Control the ADC module to do a conversion. Used as a start-convert event which is controlled by software.
* @param NewState: can be one of the following value:
* @arg ENABLE: Enable the analog module and analog mux. And then start a new channel conversion.
* @arg DISABLE: Disable the analog module and analog mux.
* @retval None.
* @note 1. Every time this bit is set to 1, ADC module would switch to a new channel and do one conversion.
* Every time a conversion is done, software MUST clear this bit manually.
* 2. Used in Sotfware Trigger Mode
*/
void ADC_SWTrigCmd(u32 NewState)
{
ADC_TypeDef *adc = ADC;
u8 div = adc->ADC_CLK_DIV;
u8 sync_time[4] = {12, 16, 32, 64};
if(NewState != DISABLE)
adc->ADC_SW_TRIG = BIT_ADC_SW_TRIG;
else
adc->ADC_SW_TRIG = 0;
/* Wait 2 clock to sync signal */
DelayUs(sync_time[div]);
}
/**
* @brief Controls the automatic channel switch enabled or disabled.
* @param NewState: can be one of the following value:
* @arg ENABLE: Enable the automatic channel switch.
* When setting this bit, an automatic channel switch starts from the first channel in the channel switch list.
* @arg DISABLE: Disable the automatic channel switch.
* If an automatic channel switch is in progess, writing 0 will terminate the automatic channel switch.
* @retval None.
* @note Used in Automatic Mode
*/
void ADC_AutoCSwCmd(u32 NewState)
{
ADC_TypeDef *adc = ADC;
u8 div = adc->ADC_CLK_DIV;
u8 sync_time[4] = {12, 16, 32, 64};
if(NewState != DISABLE)
adc->ADC_AUTO_CSW_CTRL = BIT_ADC_AUTO_CSW_EN;
else
adc->ADC_AUTO_CSW_CTRL = 0;
/* Wait 2 clock to sync signal */
DelayUs(sync_time[div]);
}
/**
* @brief Initialize the trigger timer when in ADC Timer-Trigger Mode.
* @param Tim_Idx: The timer index would be used to make ADC module do a conversion.
* @param PeriodMs: Indicate the period of trigger timer.
* @param NewState: can be one of the following value:
* @arg ENABLE: Enable the ADC timer trigger mode.
* @arg DISABLE: Disable the ADC timer trigger mode.
* @retval None.
* @note Used in Timer-Trigger Mode
*/
void ADC_TimerTrigCmd(u8 Tim_Idx, u32 PeriodMs, u32 NewState)
{
ADC_TypeDef *adc = ADC;
RTIM_TimeBaseInitTypeDef TIM_InitStruct;
assert_param(IS_ADC_VALID_TIM(Tim_Idx));
adc->ADC_EXT_TRIG_TIMER_SEL = Tim_Idx;
if(NewState != DISABLE) {
RTIM_TimeBaseStructInit(&TIM_InitStruct);
TIM_InitStruct.TIM_Idx = Tim_Idx;
TIM_InitStruct.TIM_Period = (PeriodMs *32768)/1000/2;//ms to tick
RTIM_TimeBaseInit(TIMx_LP[Tim_Idx], &TIM_InitStruct, TIMx_irq_LP[Tim_Idx], (IRQ_FUN)NULL, (u32)NULL);
RTIM_Cmd(TIMx_LP[Tim_Idx], ENABLE);
} else {
RTIM_Cmd(TIMx_LP[Tim_Idx], DISABLE);
}
}
/**
* @brief Enable or Disable DMA read mode.
* @param newState: ENABLE/DISABLE
* @retval None.
*/
void ADC_SetDmaEnable(u32 newState)
{
if (newState == DISABLE)
ADC->ADC_DMA_CON &= ~BIT_ADC_DMA_EN;
else
ADC->ADC_DMA_CON |= BIT_ADC_DMA_EN;
}
/**
* @brief Init and Enable ADC RX GDMA.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pDataBuf: Rx Buffer.
* @param DataLen: Rx Count.
* @retval TRUE/FLASE
*/
u32 ADC_RXGDMA_Init(
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8* pDataBuf,
u32 DataLen)
{
u8 GdmaChnl;
GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);
if (GdmaChnl == 0xFF) {
DBG_8195A("ADC_RXGDMA_Init GDMA busy \n");
return _FALSE;
}
/* ADC RX DMA */
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->MaxMuliBlock = 1;//MaxLlp;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_SrcMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstMsize = MsizeEight;
GDMA_InitStruct->GDMA_SrcInc = NoChange;
GDMA_InitStruct->GDMA_DstInc = IncType;
GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem;
GDMA_InitStruct->GDMA_SrcHandshakeInterface = GDMA_HANDSHAKE_INTERFACE_ADC_RX;
GDMA_InitStruct->GDMA_ReloadSrc = 1;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_BlockSize = DataLen;
GDMA_InitStruct->GDMA_SrcAddr = (u32)&(ADC->ADC_DATA_GLOBAL);
GDMA_InitStruct->GDMA_DstAddr = (u32)pDataBuf;
/* GDMA initialization */
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_adc.c
|
C
|
apache-2.0
| 19,454
|
/**
******************************************************************************
* @file rtl8721d_bor.c
* @author
* @version V1.0.0
* @date 2017-10-16
* @brief This file contains all the functions prototypes for the bor firmware
* library, including the following functionalities of bor controller:
* - mode set
* - threshold set
* - Debounce time set
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief Set BOR high and low threshold.
* @param Thres_Low: BOR low threshold.
* This parameter can be one of the following values:
* @arg BOR_TH_LOW0
* @arg BOR_TH_LOW1
* @arg BOR_TH_LOW2
* @arg BOR_TH_LOW3
* @arg BOR_TH_LOW4
* @arg BOR_TH_LOW5
* @arg BOR_TH_LOW6
* @arg BOR_TH_LOW7
* @param Thres_High: BOR high threshold.
* This parameter can be one of the following values:
* @arg BOR_TH_HIGH0
* @arg BOR_TH_HIGH1
* @arg BOR_TH_HIGH2
* @arg BOR_TH_HIGH3
* @arg BOR_TH_HIGH4
* @arg BOR_TH_HIGH5
* @arg BOR_TH_HIGH6
* @arg BOR_TH_HIGH7
* @note For chip to work normally, BOR_TH_LOW0 and BOR_TH_HIGH0 are not supported.
* @retval None
*/
VOID BOR_ThresholdSet(u32 Thres_Low, u32 Thres_High)
{
u32 temp=0;
assert_param(IS_BOR_TH_LOW(Thres_Low));
assert_param(IS_BOR_TH_HIGH(Thres_High));
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0);
temp &= (~((BIT_MASK_BOD_THRESHOLD_L << BIT_SHIFT_BOD_THRESHOLD_L) | \
(BIT_MASK_BOD_THRESHOLD_H << BIT_SHIFT_BOD_THRESHOLD_H)));
temp |= ((Thres_Low << BIT_SHIFT_BOD_THRESHOLD_L) | \
(Thres_High << BIT_SHIFT_BOD_THRESHOLD_H));
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0,temp);
}
/**
* @brief Set BOR interrupt mode debounce cycle.
* @param Option: BOR mode.
* This parameter can be one of the following values:
* @arg BOR_INTR: BOR interrupt mode
* @param Dbnc_Value: debounce cycle, in unit of ANA4M clock cycles.
* @retval None
*/
VOID BOR_DbncSet(u32 Option, u32 Dbnc_Value)
{
u32 temp=0;
if (BOR_INTR == Option) {
assert_param(IS_BOR_INTR_DBNC_THRES(Dbnc_Value));
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_BOD_DBNC_CTRL);
temp &= (~BIT_LSYS_MASK_BOD_DBNC_CYC);
temp |= (BIT_LSYS_BOD_DBNC_FEN | Dbnc_Value);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_BOD_DBNC_CTRL, temp);
}
}
/**
* @brief Clear BOR interrupt.
* @retval None
*/
VOID BOR_ClearINT(void)
{
u32 temp = 0;
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SLP_WAKE_EVENT_STATUS1);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SLP_WAKE_EVENT_STATUS1, temp);
}
/**
* @brief Enable BOR.
* @param Option: BOR mode.
* This parameter can be one of the following values:
* @arg BOR_RESET: BOR reset mode
* @arg BOR_INTR: BOR interrupt mode
* @param NewState: ENABLE or DISABLE.
* @retval None
*/
VOID BOR_ModeSet(u32 Option, u32 NewStatus)
{
u32 temp=0;
if (BOR_INTR == Option) {
if (NewStatus == DISABLE) {
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0);
temp &= ~BIT_POW_BOD_INTERRUPT;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0, temp);
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SLP_WAKE_EVENT_MSK1);
temp &= ~BIT_LP_BOD_MSK;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SLP_WAKE_EVENT_MSK1, temp);
} else {
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0);
temp |= BIT_POW_BOD_INTERRUPT;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0, temp);
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SLP_WAKE_EVENT_MSK1);
temp |= BIT_LP_BOD_MSK;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SLP_WAKE_EVENT_MSK1, temp);
}
} else {
if (NewStatus == DISABLE) {
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_BOOT_REASON1);
temp &= ~BIT_AON_BOD_RESET_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_BOOT_REASON1, temp);
} else {
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0);
temp |= BIT_POW_BOD_RESET;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0,temp);
DelayUs(200);
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_BOOT_REASON1);
temp |= BIT_AON_BOD_RESET_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_BOOT_REASON1, temp);
}
}
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_bor.c
|
C
|
apache-2.0
| 4,813
|
/**
******************************************************************************
* @file rtl8721dlp_captouch.c
* @author
* @version V1.0.0
* @date 2017-11-06
* @brief This file contains all the functions prototypes for the CapTouch function
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
#include "rtl8721d_captouch.h"
/**
* @brief Fills each CapTouch_InitStruct member with its default value.
* @param CapTouch_InitStruct: pointer to an CapTouch_InitTypeDef structure which will be initialized.
* @retval None
*/
void CapTouch_StructInit(CapTouch_InitTypeDef* CapTouch_InitStruct)
{
u8 i;
/* Load HAL initial data structure default value */
CapTouch_InitStruct->CT_DebounceEn = 1;
CapTouch_InitStruct->CT_SampleCnt = 6;
CapTouch_InitStruct->CT_ScanInterval = 60;
CapTouch_InitStruct->CT_ETCStep = 1;
CapTouch_InitStruct->CT_ETCFactor = 4;
CapTouch_InitStruct->CT_ETCScanInterval = 3;
for(i = 0; i < CT_CHANNEL_NUM; i++) {
CapTouch_InitStruct->CT_Channel[i].CT_CHEnable = DISABLE;
CapTouch_InitStruct->CT_Channel[i].CT_DiffThrehold = 0xf0;
CapTouch_InitStruct->CT_Channel[i].CT_MbiasCurrent = 0x11; //6uA
CapTouch_InitStruct->CT_Channel[i].CT_ETCNNoiseThr = 100;
CapTouch_InitStruct->CT_Channel[i].CT_ETCPNoiseThr = 100;
}
}
/**
* @brief Initializes the CapTouch peripheral according to the specified
* parameters in the CapTouch_InitStruct.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param CapTouch_InitStruct: pointer to a CapTouch_InitTypeDef structure that contains
* the configuration information for the specified CapTouch peripheral.
* @retval None
*/
void CapTouch_Init(CAPTOUCH_TypeDef *CapTouch, CapTouch_InitTypeDef* CapTouch_InitStruct)
{
u8 i;
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(CapTouch_InitStruct->CT_DebounceEn <= 1 );
assert_param(CapTouch_InitStruct->CT_SampleCnt<= 7 );
assert_param(CapTouch_InitStruct->CT_ScanInterval <= 0xFFF );
assert_param(CapTouch_InitStruct->CT_ETCStep <= 0xF );
assert_param(CapTouch_InitStruct->CT_ETCFactor <= 0xF );
assert_param(CapTouch_InitStruct->CT_ETCScanInterval <= 0x7F );
for(i = 0; i < CT_CHANNEL_NUM ;i++) {
assert_param(CapTouch_InitStruct->CT_Channel[i].CT_DiffThrehold <= 0xFFF );
assert_param(CapTouch_InitStruct->CT_Channel[i].CT_MbiasCurrent <= 0x3F );
//assert_param(CapTouch_InitStruct->CT_Channel[i].CT_ETCNNoiseThr <= 0xFF );
//assert_param(CapTouch_InitStruct->CT_Channel[i].CT_ETCPNoiseThr <= 0xFF );
}
/* Disable CTC, clear pending interrupt*/
CapTouch_Cmd(CapTouch, DISABLE);
CapTouch->CT_IER = 0;
CapTouch->CT_ICR_ALL = BIT_CT_ALL_INT_CLR;
/* Set control register*/
CapTouch->CT_CTRL = BIT_CT_BL_ENABLE | (CapTouch_InitStruct->CT_DebounceEn << 4);
CapTouch->CT_SP_CTRL = CapTouch_InitStruct->CT_SampleCnt << 16 | \
CapTouch_InitStruct->CT_ScanInterval;
CapTouch->CT_ETC_CTRL = CapTouch_InitStruct->CT_ETCStep << 12 | \
CapTouch_InitStruct->CT_ETCFactor << 8 | \
CapTouch_InitStruct->CT_ETCScanInterval << 1 | \
BIT_CT_ETC_ENABLE;
CapTouch->CT_MODE_CTRL = BIT_CT_AUTO_CHANNEL_ENABLE;
/* Configure each channel */
for(i = 0; i < CT_CHANNEL_NUM ;i++) {
if(CapTouch_InitStruct->CT_Channel[i].CT_CHEnable) {
CapTouch->CT_CH[i].CTRL = (CapTouch_InitStruct->CT_Channel[i].CT_DiffThrehold <<16) | BIT_CT_CHX_ENABLE;
CapTouch->CT_CH[i].MBIAS = CapTouch_InitStruct->CT_Channel[i].CT_MbiasCurrent;
CapTouch->CT_CH[i].ATHR = CapTouch_InitStruct->CT_Channel[i].CT_ETCNNoiseThr << 24 | \
CapTouch_InitStruct->CT_Channel[i].CT_ETCPNoiseThr << 16;
}
}
}
/**
* @brief Enables or disables the specified CapTouch peripheral.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param NewState: new state of the CapTouch peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CapTouch_Cmd(CAPTOUCH_TypeDef *CapTouch, u8 NewState)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
if (NewState != DISABLE) {
/* Enable the CapTouch peripheral and baseline */
CapTouch->CT_CTRL |= BIT_CT_ENABLE | BIT_CT_BL_ENABLE;
} else {
/* Disable the CapTouch peripheral */
CapTouch->CT_CTRL &= (~BIT_CT_ENABLE);
}
}
/**
* @brief Enables or disables the specified CapTouch interrupts.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param CapTouch_IT: specifies the CapTouch interrupt to be enabled or masked.
* This parameter can be one or combinations of the following values:
* @arg BIT_CT_OVER_N_NOISE_THRESHOLD_INT: CapTouch negetive noise overflow interrupt
* @arg BIT_CT_FIFO_OVERFLOW_INT: CapTouch FIFO overflow interrupt
* @arg BIT_CT_OVER_P_NOISE_THRESHOLD_INT:CapTouch positive noise overflow interrupt
* @arg CT_CHX_PRESS_INT(x): CapTouch channel(x) press interrupt, where x can be 0~3
* @arg CT_CHX_RELEASE_INT(x): CapTouch channel(x) release interrupt, where x can be 0~3
* @param NewState: new state of the specified CapTouch interrupts mask.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CapTouch_INTConfig(CAPTOUCH_TypeDef *CapTouch, uint32_t CapTouch_IT, u8 newState)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_INT_EN(CapTouch_IT));
if (newState == ENABLE) {
/* Enable CapTouch interrupts */
CapTouch->CT_IER |= CapTouch_IT;
} else {
/* Disable CapTouch interrupts */
CapTouch->CT_IER &= (~CapTouch_IT);
}
}
/**
* @brief Clears the specified CapTouch interrupt pending bit.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param CapTouch_IT: specifies the CapTouch interrupt to be cleared.
* This parameter can be one or combinations of the following values:
* @arg BIT_CT_N_NOISE_OVERFLOW_INT_CLR:CapTouch negetive noise overflow interrupt
* @arg BIT_CT_FIFO_OVERFLOW_INT_CLR: CapTouch FIFO overflow interrupt
* @arg BIT_CT_P_NOISE_OVERFLOW_INT_CLR:CapTouch positive noise overflow interrupt
* @arg CT_CHX_PRESS_INT(x): CapTouch channel(x) press interrupt, where x can be 0~3
* @arg CT_CHX_RELEASE_INT(x): CapTouch channel(x) release interrupt, where x can be 0~3
* @retval None
*/
void CapTouch_INTClearPendingBit(CAPTOUCH_TypeDef *CapTouch, u32 CapTouch_IT)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_INT_CLR(CapTouch_IT));
CapTouch->CT_ICR |= CapTouch_IT;
}
/**
* @brief Get CapTouch Raw Interrupt Status.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @retval raw interrupt status
*/
u32 CapTouch_GetRawISR(CAPTOUCH_TypeDef *CapTouch)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
return CapTouch->CT_ISR_RAW;
}
/**
* @brief Get CapTouch interrupt status.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @retval interrupt status
*/
u32 CapTouch_GetISR(CAPTOUCH_TypeDef *CapTouch)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
return CapTouch->CT_ISR;
}
/**
* @brief Get CapTouch channel enable status.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Channel: specified channel index, which can be 0~3
* @retval channel enable status.
*/
u32 CapTouch_GetChStatus(CAPTOUCH_TypeDef *CapTouch, u32 Channel)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_CHANNEL(Channel));
if (CapTouch->CT_CH[Channel].CTRL & BIT_CT_CHX_ENABLE)
return TRUE;
else
return FALSE;
}
/**
* @brief Enable or disable specified channel.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Channel: specified channel index, which can be 0~3
* @param NewState: new state of the specified channel.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CapTouch_ChCmd(CAPTOUCH_TypeDef *CapTouch, u8 Channel, u8 NewState)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_CHANNEL(Channel));
if (NewState != DISABLE) {
/* Enable the CapTouch crossponding channel */
CapTouch->CT_CH[Channel].CTRL |= BIT_CT_CHX_ENABLE;
} else {
/* Disable the CapTouch peripheral */
CapTouch->CT_CH[Channel].CTRL &= ~BIT_CT_CHX_ENABLE;
}
}
/**
* @brief Set CapTouch Scan interval.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Interval: scan interval in units of ms
* @retval None
*/
void CapTouch_SetScanInterval(CAPTOUCH_TypeDef *CapTouch, u32 Interval)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(Interval <= 4095);
CapTouch_Cmd(CapTouch, DISABLE);
TempVal = CapTouch->CT_SP_CTRL;
TempVal &= ~BIT_CT_SCAN_INTERVAL;
TempVal |= Interval;
CapTouch->CT_SP_CTRL = TempVal;
CapTouch_Cmd(CapTouch, ENABLE);
}
/**
* @brief Set Mbias current for specified channel.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Channel: specified channel index, which can be 0~3.
* @param Mbias: Mbias value, relate current = 0.25*Mbias.
* @retval None
*/
void CapTouch_SetChMbias(CAPTOUCH_TypeDef *CapTouch, u8 Channel, u8 Mbias)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_CHANNEL(Channel));
assert_param(Mbias < 64);
CapTouch_Cmd(CapTouch, DISABLE);
CapTouch->CT_CH[Channel].MBIAS =Mbias;
CapTouch_Cmd(CapTouch, ENABLE);
}
/**
* @brief Set relative touch threshold for related channel.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Channel: specified channel index, which can be 0~3
* @param Threshold: Related Threshold value.
* @retval None
*/
void CapTouch_SetChDiffThres(CAPTOUCH_TypeDef *CapTouch, u8 Channel, u32 Threshold)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_CHANNEL(Channel));
assert_param(Threshold < 4096);
CapTouch_Cmd(CapTouch, DISABLE);
TempVal = CapTouch->CT_CH[Channel].CTRL;
TempVal &= ~BIT_CT_CHX_TOUCH_THRES;
TempVal |= Threshold << 16;
CapTouch->CT_CH[Channel].CTRL = TempVal;
CapTouch_Cmd(CapTouch, ENABLE);
}
/**
* @brief Get relative threshold of touch judgement for specified channel.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Channel: specified channel index, which can be 0~3
* @retval Difference threshold of specified channel.
*/
u32 CapTouch_GetChDiffThres(CAPTOUCH_TypeDef *CapTouch, u8 Channel)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_CHANNEL(Channel));
return (CapTouch->CT_CH[Channel].CTRL & BIT_CT_CHX_TOUCH_THRES) >> 16;
}
/**
* @brief Get Absolute threshold of touch judgement for specified channel.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Channel: specified channel index, which can be 0~3
* @retval Difference threshold of specified channel.
*/
u32 CapTouch_GetChAbsThres(CAPTOUCH_TypeDef *CapTouch, u8 Channel)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_CHANNEL(Channel));
return CapTouch->CT_CH[Channel].ATHR & BIT_CT_CHX_TOUCH_ATHRES;
}
/**
* @brief Get positive or negative noise threshold for specified channel.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Channel: specified channel index, which can be 0~3
* @param type: can be P_NOISE_THRES or N_NOISE_THRES
* @retval Noise threshold of specified channel.
*/
u32 CapTouch_GetNoiseThres(CAPTOUCH_TypeDef *CapTouch, u8 Channel, u8 type)
{
u8 value;
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_CHANNEL(Channel));
if(type)
value = (CapTouch->CT_CH[Channel].ATHR & BIT_MASK_CHX_N_ENT) >> 24;
else
value = (CapTouch->CT_CH[Channel].ATHR & BIT_MASK_CHX_P_ENT) >> 16;
return value;
}
/**
* @brief Read Baseline data from specified channel.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Channel: specified channel index, which can be 0~3
* @retval Baseline data
*/
u32 CapTouch_GetChBaseline(CAPTOUCH_TypeDef *CapTouch, u8 Channel)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_CHANNEL(Channel));
return ((CapTouch->CT_CH[Channel].CTRL & BIT_CT_CHX_BASELINE) >> 4);
}
/**
* @brief Read average data from specified channel.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Channel: specified channel index, which can be 0~3
* @retval Average data
*/
u32 CapTouch_GetChAveData(CAPTOUCH_TypeDef *CapTouch, u8 Channel)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_CHANNEL(Channel));
return (CapTouch->CT_CH[Channel].DATA & BIT_CT_CHX_DATA);
}
/**
* @brief Enable or disable Debug mode.
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param NewState: new state of the Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CapTouch_DbgCmd(CAPTOUCH_TypeDef *CapTouch, u8 NewState)
{
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
if (NewState != DISABLE) {
/* Enable the CapTouch debug mode */
CapTouch->CT_MODE_CTRL |= BIT_CT_DBG_ENABLE;
} else {
/* Disable the CapTouch peripheral */
CapTouch->CT_MODE_CTRL |= BIT_CT_AUTO_CHANNEL_ENABLE;
CapTouch->CT_MODE_CTRL &= (~BIT_CT_DBG_ENABLE);
}
}
/**
* @brief select debug channel
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param Channel: specified channel index, which can be 0~3
* @retval none
*/
void CapTouch_DbgChannel(CAPTOUCH_TypeDef *CapTouch, u8 Channel)
{
u32 data;
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
assert_param(IS_CT_CHANNEL(Channel));
data = CapTouch->CT_MODE_CTRL;
data &= ~(BIT_CT_CHANNEL_SEL | BIT_CT_AUTO_CHANNEL_ENABLE);
data |= Channel << 5;
CapTouch->CT_MODE_CTRL = data;
}
/**
* @brief Get Raw data in debug mode
* @param CapTouch: which should be CAPTOUCH_DEV.
* @retval Raw data
*/
u32 CapTouch_DbgRawData(CAPTOUCH_TypeDef *CapTouch)
{
u32 loop = 0;
u32 data;
/* Check the parameters */
assert_param(IS_CAPTOUCH_ALL_PERIPH(CapTouch));
do {
data = CapTouch->CT_FIFO;
if(loop++ > 10000){
DBG_8195A("sample timeout \n" );
return 0xEAEA;
}
} while((data & BIT(31)) == 0);
return (data & 0x0FFF);
}
/**
* @brief Dump all registers
* @param CapTouch: which should be CAPTOUCH_DEV.
* @retval NA
*/
void CapTouch_DbgDumpReg(CAPTOUCH_TypeDef *CapTouch)
{
DBG_8195A("\n%08x: %08x (CT_CTRL)\n", &(CapTouch->CT_CTRL), CapTouch->CT_CTRL);
DBG_8195A("%08x: %08x (CT_SP_CTRL)\n", &(CapTouch->CT_SP_CTRL), CapTouch->CT_SP_CTRL);
DBG_8195A("%08x: %08x (CT_ETC_CTRL)\n", &(CapTouch->CT_ETC_CTRL), CapTouch->CT_ETC_CTRL);
DBG_8195A("%08x: %08x (CT_SNR)\n", &(CapTouch->CT_SNR), CapTouch->CT_SNR);
DBG_8195A("%08x: %08x (CT_MODE_CTRL)\n", &(CapTouch->CT_MODE_CTRL), CapTouch->CT_MODE_CTRL);
DBG_8195A("%08x: %08x (CT_FIFO_STATUS)\n", &(CapTouch->CT_FIFO_STATUS), CapTouch->CT_FIFO_STATUS);
DBG_8195A("%08x: %08x (CT_FIFO)\n", &(CapTouch->CT_FIFO), CapTouch->CT_FIFO);
DBG_8195A("%08x: %08x (CT_IER)\n", &(CapTouch->CT_IER), CapTouch->CT_IER);
DBG_8195A("%08x: %08x (CT_ISR)\n", &(CapTouch->CT_ISR), CapTouch->CT_ISR);
DBG_8195A("%08x: %08x (CT_ISR_RAW)\n", &(CapTouch->CT_ISR_RAW), CapTouch->CT_ISR_RAW);
DBG_8195A("%08x: %08x (CT_ICR_ALL)\n", &(CapTouch->CT_ICR_ALL), CapTouch->CT_ICR_ALL);
DBG_8195A("%08x: %08x (CT_ICR)\n", &(CapTouch->CT_ICR), CapTouch->CT_ICR);
DBG_8195A("%08x: %08x (CT_CH[0].CTRL)\n", &(CapTouch->CT_CH[0].CTRL), CapTouch->CT_CH[0].CTRL);
DBG_8195A("%08x: %08x (CT_CH[0].ATHR)\n", &(CapTouch->CT_CH[0].ATHR), CapTouch->CT_CH[0].ATHR);
DBG_8195A("%08x: %08x (CT_CH[0].MBIAS)\n", &(CapTouch->CT_CH[0].MBIAS), CapTouch->CT_CH[0].MBIAS);
DBG_8195A("%08x: %08x (CT_CH[0].DATA)\n", &(CapTouch->CT_CH[0].DATA), CapTouch->CT_CH[0].DATA);
DBG_8195A("%08x: %08x (CT_ADC_REG0X_LPAD)\n", &(CapTouch->CT_ADC_REG0X_LPAD), CapTouch->CT_ADC_REG0X_LPAD);
DBG_8195A("%08x: %08x (CT_ADC_REG1X_LPAD)\n", &(CapTouch->CT_ADC_REG1X_LPAD), CapTouch->CT_ADC_REG1X_LPAD);
DBG_8195A("%08x: %08x (CT_ADC_REG0X_LPSD)\n", &(CapTouch->CT_ADC_REG0X_LPSD), CapTouch->CT_ADC_REG0X_LPSD);
DBG_8195A("%08x: %08x (CT_ADC_TIME)\n", &(CapTouch->CT_ADC_TIME), CapTouch->CT_ADC_TIME);
}
/**
* @brief Dump all registers
* @param CapTouch: which should be CAPTOUCH_DEV.
* @param ch: specified channel index, which can be 0~3
* @retval NA
*/
void CapTouch_DbgDumpETC(CAPTOUCH_TypeDef *CapTouch, u32 ch)
{
/* To avoid gcc warnings */
( void ) CapTouch;
u32 DiffThres = 0;
u32 Baseline = 0;
u32 AveData = 0;
u32 NoiseThresP = 0;
u32 NoiseThresN = 0;
u32 AbsoThres = 0;
DiffThres = CapTouch_GetChDiffThres(CAPTOUCH_DEV, ch);
Baseline = CapTouch_GetChBaseline(CAPTOUCH_DEV, ch);
AveData = CapTouch_GetChAveData(CAPTOUCH_DEV, ch);
NoiseThresP = CapTouch_GetNoiseThres(CAPTOUCH_DEV, ch, P_NOISE_THRES);
NoiseThresN = CapTouch_GetNoiseThres(CAPTOUCH_DEV, ch, N_NOISE_THRES);
AbsoThres = CapTouch_GetChAbsThres(CAPTOUCH_DEV, ch);
DBG_8195A("\nCH[%d] ETC: ChDiffThres:%08x (%d) \n", ch, DiffThres, DiffThres);
DBG_8195A("CH[%d] ETC: Baseline:%08x (%d) \n", ch, Baseline, Baseline);
DBG_8195A("CH[%d] ETC: RawAveData:%08x (%d) Diff:%d \n", ch, AveData, AveData, AveData-Baseline);
DBG_8195A("CH[%d] ETC: NoiseThres P:%08x (%d) \n", ch, NoiseThresP, NoiseThresP);
DBG_8195A("CH[%d] ETC: NoiseThres N:%08x (%d) \n", ch, NoiseThresN, NoiseThresN);
DBG_8195A("CH[%d] ETC: AbsoThres:%08x (%d) \n", ch, AbsoThres, AbsoThres);
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_captouch.c
|
C
|
apache-2.0
| 18,278
|
/**
******************************************************************************
* @file rtl8721d_comparator.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of the Comparator peripheral:
* - Initialization and Configuration
* - Analog configuration
* - Mode configuration
* - Interrupts and flags management
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief Initializes the parameters in the CMP_InitStruct with default value.
* @param CMP_InitStruct: pointer to a CMP_InitTypeDef structure that contains
* the configuration information for the Comparator peripheral.
* @retval None
*/
void CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct)
{
u8 i;
for(i = 0; i < COMP_CH_NUM; i++) {
CMP_InitStruct->CMP_ChanCtrl[i].CMP_ChIndex = i;
CMP_InitStruct->CMP_ChanCtrl[i].CMP_Ref0 = 0; // Vref0 = 0.1*0=0v
CMP_InitStruct->CMP_ChanCtrl[i].CMP_Ref1 = 0x1F; // Vref1 = 0.1*31=3.1v
CMP_InitStruct->CMP_ChanCtrl[i].CMP_WakeType = COMP_WK_NONE;
CMP_InitStruct->CMP_ChanCtrl[i].CMP_WakeSysCtrl = COMP_WITHIN_REF0_AND_REF1;
CMP_InitStruct->CMP_ChanCtrl[i].CMP_WakeADCCtrl = COMP_WITHIN_REF0_AND_REF1;
}
}
/**
* @brief Initializes the Comparator according to the specified parameters in CMP_InitStruct.
* @param CMP_InitStruct: pointer to a CMP_InitTypeDef structure that contains
* the configuration for the Comparator peripheral.
* @retval None
*/
void CMP_Init(CMP_InitTypeDef* CMP_InitStruct)
{
u8 i, index;
u32 tmp, val_ch = 0;
CMP_TypeDef *comparator = COMPARATOR;
CMP_CHTypeDef *compChan = CMP_InitStruct->CMP_ChanCtrl;
CMP_Cmd(DISABLE);
tmp = comparator->COMP_INTR_CTRL;
for(i = 0; i < COMP_CH_NUM; i++) {
index = compChan[i].CMP_ChIndex;
val_ch |= (u32)(index << BIT_SHIFT_COMP_CHSW(i));
comparator->COMP_REF_CH[index] = (u32)((compChan[i].CMP_Ref0 << BIT_SHIFT_COMP_REF0) | \
(compChan[i].CMP_Ref1 << BIT_SHIFT_COMP_REF1));
if(compChan[i].CMP_WakeType & COMP_WK_ADC) {
tmp &= ~ BIT_MASK_COMP_WK_ADC_CTRL(index);
tmp |= (compChan[i].CMP_WakeADCCtrl << BIT_SHIFT_COMP_WK_ADC_CTRL(index)) | \
BIT_COMP_WK_ADC_EN(index);
}
if(compChan[i].CMP_WakeType & COMP_WK_SYS) {
tmp &= ~ BIT_MASK_COMP_WK_SYS_CTRL(index);
tmp |= (compChan[i].CMP_WakeSysCtrl << BIT_SHIFT_COMP_WK_SYS_CTRL(index)) | \
BIT_COMP_WK_SYS_EN(index);
}
}
comparator->COMP_INTR_CTRL = tmp;
comparator->COMP_CHSW_LIST = val_ch;
comparator->COMP_ANALOG |= BIT_SD_POSEDGE;
comparator->COMP_AUTO_SHUT = BIT_COMP_AUTO_SHUT;
}
/**
* @brief Enable or Disable the Comparator peripheral.
* @param NewState: new state of the Comparator peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CMP_Cmd(u32 NewState)
{
CMP_TypeDef *comparator = COMPARATOR;
if(NewState != DISABLE)
comparator->COMP_EN_TRIG |= BIT_COMP_ENABLE | BIT_COMP_EN_TRIG;
else
comparator->COMP_EN_TRIG &= ~(BIT_COMP_ENABLE | BIT_COMP_EN_TRIG);
}
/**
* @brief Indicate the Comparator is busy or not .
* @param None
* @retval busy status value:
* - 1: Busy
* - 0: Not Busy.
*/
u32 CMP_Busy(void)
{
CMP_TypeDef *comparator = COMPARATOR;
if(comparator->COMP_BUSY_STS & BIT_COMP_BUSY_STS)
return 1;
else
return 0;
}
/**
* @brief Get Comparator Wakeup ADC/SYS Status Register .
* @param None
* @retval Current Comparator Wakeup ADC/SYS Status Register
*/
u32 CMP_GetISR(void)
{
CMP_TypeDef *comparator = COMPARATOR;
return comparator->COMP_WK_STS;
}
/**
* @brief Clear pending bit in Comparator Wakeup ADC/SYS Status Register.
* @param Comparator Wakeup ADC/SYS Status Register
* @retval None
*/
void CMP_INTClearPendingBit(u32 Cmp_IT)
{
CMP_TypeDef *comparator = COMPARATOR;
comparator->COMP_WK_STS = Cmp_IT;
}
/**
* @brief Get the comparison result .
* @param channel : the Comparator channel index
* @retval The comparison result of specified channel index. The return value can be:
* -0: when Vin < Vref0
* -2: when Vin > Vref0 & Vin < Vref1
* -3: when Vin > Vref1
*/
u32 CMP_GetCompStatus(u8 channel)
{
CMP_TypeDef *comparator = COMPARATOR;
u32 value = (comparator->COMP_CH_STS & BIT_COMP_CH_STS(channel)) >> \
BIT_SHIFT_COMP_CH_STS(channel);
return value;
}
/**
* @brief Get the channel list index of the last used channel.
* @param None.
* @retval The channel list index of the last used channel. Not channel ID.
*/
u32 CMP_GetLastChan(void)
{
CMP_TypeDef *comparator = COMPARATOR;
return comparator->COMP_LAST_CH;
}
/**
* @brief Reset the channel switch to default state.
* @param None
* @retval None
*/
void CMP_ResetCSwList(void)
{
CMP_TypeDef *comparator = COMPARATOR;
comparator->COMP_RST_LIST = BIT_COMP_RST_LIST;
comparator->COMP_RST_LIST = 0;
}
/**
* @brief Controls the automatic channel swtich enabled or disabled in Comparator Automatic Mode.
* @param NewState: can be one of the following value:
* @arg ENABLE: Enable the automatic channel switch.
* When setting this bit, an automatic channel switch starts from the first channel in the channel switch list.
* @arg DISABLE: Disable the automatic channel switch.
* If an automatic channel switch is in progess, writing 0 will terminate the automatic channel switch.
* @retval None.
*/
void CMP_AutoCSwCmd(u32 NewState)
{
CMP_TypeDef *comparator = COMPARATOR;
if(NewState != DISABLE) {
comparator->COMP_AUTOSW_EN = BIT_COMP_AUTOSW_EN;
comparator->COMP_EN_TRIG |= BIT_COMP_EN_TRIG;
} else {
comparator->COMP_AUTOSW_EN = 0;
comparator->COMP_EN_TRIG &= ~BIT_COMP_EN_TRIG;
}
}
/**
* @brief Initialize the trigger timer when in Comparator Timer-Trigger Mode.
* @param Tim_Idx: The timer index would be used to make the Comparator module do a comparison.
* @param PeriodMs: Indicate the period of trigger timer.
* @param NewState: can be one of the following value:
* @arg ENABLE: Enable the Comparator timer trigger mode.
* @arg DISABLE: Disable the Comparator timer trigger mode.
* @retval None.
* @note Used in Comparator Timer-Trigger Mode
*/
void CMP_TimerTrigCmd(u8 Tim_Idx, u32 PeriodMs, u32 NewState)
{
CMP_TypeDef *comparator = COMPARATOR;
RTIM_TimeBaseInitTypeDef TIM_InitStruct;
comparator->COMP_EXT_TRIG_TIMER_SEL = Tim_Idx;
if(NewState != DISABLE) {
RTIM_TimeBaseStructInit(&TIM_InitStruct);
TIM_InitStruct.TIM_Idx = Tim_Idx;
TIM_InitStruct.TIM_Period = (PeriodMs *32768)/1000/2;//ms to tick
RTIM_TimeBaseInit(TIMx_LP[Tim_Idx], &TIM_InitStruct, TIMx_irq_LP[Tim_Idx], (IRQ_FUN)NULL, (u32)NULL);
RTIM_Cmd(TIMx_LP[Tim_Idx], ENABLE);
comparator->COMP_EXT_TRIG_CTRL = BIT_COMP_EXT_WK_TIMER;
} else {
RTIM_Cmd(TIMx_LP[Tim_Idx], DISABLE);
comparator->COMP_EXT_TRIG_CTRL = 0;
}
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_comparator.c
|
C
|
apache-2.0
| 7,438
|
/**
******************************************************************************
* @file rtl8721d_efuse.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions patch for EFUSE rom code.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_efuse.c
|
C
|
apache-2.0
| 777
|
/**
******************************************************************************
* @file rtl8721d_flash_ram.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the flash RAM functions.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
static u32 cpu_systick;
/**
* @brief This function is used to handle flash write ipc interrupt.
* @param Data: The pointer will be pass the IRQ handler
* @param IrqStatus: this specify the IPC_ISR.
* @param ChanNum: this specify the IPC channel number.
* @retval none
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_Write_IPC_Int(VOID *Data, u32 IrqStatus, u32 ChanNum)
{
/* To avoid gcc warnings */
( void ) Data;
( void ) IrqStatus;
( void ) ChanNum;
/*disable all interrupts first if primask is clear, or the CPU can't sleep*/
if(__get_PRIMASK() == 0) {
asm volatile ("cpsid i" : : : "memory");
//asm volatile ("cpsid f" : : : "memory");
asm volatile ("wfe");
asm volatile ("wfe");
asm volatile ("cpsie i" : : : "memory");
//asm volatile ("cpsie f" : : : "memory");
} else {
asm volatile ("wfe");
asm volatile ("wfe");
}
}
/**
* @brief This function is used to lock CPU when write or erase flash under XIP.
* @note
* - all interrupt include systick will be stopped.
* @retval none
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_Write_Lock(void)
{
u32 cpu_id = IPC_CPUID();
u32 lp_sleep_state;
asm volatile ("cpsid i" : : : "memory");
cpu_systick = SysTick->CTRL; //disable systick exception
SysTick->CTRL = 0;
//u32 hp_sleep_state;
/*IPC request to let the other CPU sleep*/
if (cpu_id == 1) {
ipc_send_message(IPC_INT_CHAN_FLASHPG_REQ, (uint32_t)NULL);
while(1) {
lp_sleep_state = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_KM0_CTRL); /*get KM0 sleep status*/
if(lp_sleep_state & BIT_KM0_SLEEPSYS) {
break;
}
}
} else {
#if defined (ARM_CORE_CM0)
u32 hp_sleep_state;
if(km4_status_on()) {
ipc_send_message(IPC_INT_CHAN_FLASHPG_REQ, (uint32_t)NULL);
while(1) {
hp_sleep_state = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLATFORM_PARA); /*get KM4 sleep status*/
if(hp_sleep_state & BIT_KM4_SLEEP_STATUS) {
break;
}
}
}
#endif
}
}
/**
* @brief This function is used to unlock CPU after write or erase flash under XIP.
* @note
* - all interrupt will be restored.
* @retval none
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_Write_Unlock(void)
{
u32 cpu_id = IPC_CPUID();
u32 lp_sleep_state;
//u32 hp_sleep_state;
/*send an event using "sev" instruction to let the other CPU wake up*/
asm volatile ("sev");
if (cpu_id == 1) {
while(1) {
lp_sleep_state = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_KM0_CTRL); /*get KM0 sleep status*/
if(!(lp_sleep_state & BIT_KM0_SLEEPSYS)) {
break;
}
}
} else {
#if defined (ARM_CORE_CM0)
u32 hp_sleep_state;
if(km4_status_on()) {
while(1) {
hp_sleep_state = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLATFORM_PARA); /*get KM4 sleep status*/
if(!(hp_sleep_state & BIT_KM4_SLEEP_STATUS)) {
break;
}
}
}
#endif
}
SysTick->CTRL = cpu_systick;//restore systick exception
asm volatile ("cpsie i" : : : "memory");
}
/**
* @brief This function is used to send Rx command to flash to get status register or flash id, and lock CPU when Rx
* @param cmd: command that need to be sent.
* @param read_len: the number of bytes that will be read by SPIC after sending cmd.
* @param read_data: pointer to a byte array which is used to save received data.
* @note This function is only used for rx status/flash id ,not used for read flash data.
* Only work in OneBitMode.
* @retval none
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_RxCmdXIP(u8 cmd, u32 read_len, u8* read_data)
{
FLASH_Write_Lock();
FLASH_RxCmd(cmd, read_len, read_data);
FLASH_Write_Unlock();
}
/**
* @brief FLASH_SetStatus used to set register status. FLASH_WriteEn & FLASH_WaitBusy, and lock CPU when set
* are included in this function to avoid hardfault when TxCmd in XIP
* @param Cmd: command to be sent
* @param Len: the number of bytes to be sent after Cmd
* @param Status: pointer to byte array to be sent
* @retval none
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_SetStatusXIP(u8 Cmd, u32 Len, u8* Status)
{
FLASH_Write_Lock();
FLASH_SetStatus(Cmd, Len, Status);
FLASH_Write_Unlock();
}
/**
* @brief FLASH_SetStatusBits set or clear status bits., used to set protect bit or quad enable bit, and lock CPU when set
* @param SetBits: 16bits valid, SetBits[7:0] is status1 & SetBits[15:8] is status2
* @param NewState: ENABLE/DISABLE
* @retval none
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_SetStatusBitsXIP(u32 SetBits, u32 NewState)
{
FLASH_Write_Lock();
FLASH_SetStatusBits(SetBits, NewState);
FLASH_Write_Unlock();
}
/**
* @brief This function is used to write data to flash in OneBitMode and User Mode, and lock CPU when write.
* @param StartAddr: Start address in flash from which SPIC writes.
* @param DataPhaseLen: the number of bytes that SPIC sends in Data Phase.
* @param pData: pointer to a byte array that is to be sent.
* @note
* - page program(256B) time typical is 0.7ms: BaudRate=2.9Mbps, so one bit mode is enough.
* - page program(12B) time typical is 20+2.5*11= 47.5us BaudRate = 2.02M bps, so program 12B once is enough.
* - for compatibility with amebaz, which has 16-byte TX FIFO is 16 byte and max len is 16-cmdlen = 12 byte
* @retval none
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_TxData12BXIP(u32 StartAddr, u8 DataPhaseLen, u8* pData)
{
FLASH_Write_Lock();
FLASH_TxData12B(StartAddr, DataPhaseLen, pData);
Cache_Flush();
FLASH_Write_Unlock();
}
/**
* @brief This function is used to erase flash, and lock CPU when erase.
* @param EraseType: can be one of the following parameters:
@arg EraseChip: Erase the whole chip.
@arg EraseBlock: Erase specified block(64KB)
@arg EraseSector: Erase specified sector(4KB)
* @param Address should 4 byte align.The block/sector which
* the address in will be erased.
* @retval none
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_EraseXIP(u32 EraseType, u32 Address)
{
FLASH_Write_Lock();
FLASH_Erase(EraseType, Address);
Cache_Flush();
FLASH_Write_Unlock();
}
/**
* @brief This function is used to erase some dwords, and keep other dwords unchanged in one sector.
* @param address: Start address in flash to be erased.
* @param dword_num: the number of dwords to be erased.
* @note
* - this function is just used for change some dwords in one sector.
* - this function will erase whole sector and then write back other dwords.
* - please dont use this function if not needed !!!!!!!!!!!!!!
* - FLASH_EraseXIP is recommended if need
* @retval none
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_EreaseDwordsXIP(u32 address, u32 dword_num)
{
u32 data[2];
u32 idx = 0;
u32 opt_sector = address & ~(0xFFF);
u32 erase_addr = address;
u32 erase_num = dword_num;
/* erase backup sector */
FLASH_EraseXIP(EraseSector, FLASH_RESERVED_DATA_BASE);
/* backup this sector */
for (idx = 0; idx < 0x1000; idx += 4) {
u32 read_addr = opt_sector + idx;
_memcpy(data, (const void *)(SPI_FLASH_BASE + read_addr), 4);
if (erase_num > 0) {
if (erase_addr == read_addr) {
data[0] = 0xFFFFFFFF;
erase_addr += 4;
erase_num--;
}
}
FLASH_TxData12BXIP((FLASH_RESERVED_DATA_BASE + idx), 4, (u8*)data);
}
/* erase this sector */
FLASH_EraseXIP(EraseSector, opt_sector);
/* write this sector with target data erased */
for (idx = 0; idx < 0x1000; idx += 8) {
_memcpy(data, (const void *)(SPI_FLASH_BASE + FLASH_RESERVED_DATA_BASE + idx), 8);
FLASH_TxData12BXIP((opt_sector + idx), 8, (u8*)data);
}
}
/**
* @brief This function is used to write data to flash in OneBitMode and User Mode, and lock CPU when write.
* @param StartAddr: Start address in flash from which SPIC writes.
* @param DataPhaseLen: the number of bytes that SPIC sends in Data Phase.
* @param pData: pointer to a byte array that is to be sent.
* @note
* - page program(256B) time typical is 0.7ms: BaudRate=2.9Mbps, so one bit mode is enough.
* - should use FLASH_SW_CS_Control to protect flash write
* @retval none
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_TxData256BXIP(u32 StartAddr, u32 DataPhaseLen, u8* pData)
{
FLASH_Write_Lock();
FLASH_TxData256B(StartAddr, DataPhaseLen, pData);
Cache_Flush();
FLASH_Write_Unlock();
}
/**
* @brief Read a stream of data from specified address
* @param obj: Flash object define in application software.
* @param address: Specifies the starting address to read from.
* @param len: Specifies the length of the data to read.
* @param data: Specified the address to save the readback data.
* @retval status: Success:1 or Failure: Others.
* @note auto mode is ok, because we have flash cache
*/
IMAGE2_RAM_TEXT_SECTION
int FLASH_ReadStream(u32 address, u32 len, u8 * data)
{
assert_param(data != NULL);
u32 offset_to_align;
u32 i;
u32 read_word;
u8 *ptr;
u8 *pbuf;
offset_to_align = address & 0x03;
pbuf = data;
if (offset_to_align != 0) {
/* the start address is not 4-bytes aligned */
read_word = HAL_READ32(SPI_FLASH_BASE, (address - offset_to_align));
ptr = (u8*)&read_word + offset_to_align;
offset_to_align = 4 - offset_to_align;
for (i=0;i<offset_to_align;i++) {
*pbuf = *(ptr+i);
pbuf++;
len--;
if (len == 0) {
break;
}
}
}
/* address = next 4-bytes aligned */
address = (((address-1) >> 2) + 1) << 2;
ptr = (u8*)&read_word;
if ((u32)pbuf & 0x03) {
while (len >= 4) {
read_word = HAL_READ32(SPI_FLASH_BASE, address);
for (i=0;i<4;i++) {
*pbuf = *(ptr+i);
pbuf++;
}
address += 4;
len -= 4;
}
} else {
while (len >= 4) {
*((u32 *)pbuf) = HAL_READ32(SPI_FLASH_BASE, address);
pbuf += 4;
address += 4;
len -= 4;
}
}
if (len > 0) {
read_word = HAL_READ32(SPI_FLASH_BASE, address);
for (i=0;i<len;i++) {
*pbuf = *(ptr+i);
pbuf++;
}
}
return 1;
}
/**
* @brief Write a stream of data to specified address
* @param address: Specifies the starting address to write to.
* @param len: Specifies the length of the data to write.
* @param data: Pointer to a byte array that is to be written.
* @retval status: Success:1 or Failure: Others.
*/
IMAGE2_RAM_TEXT_SECTION
int FLASH_WriteStream(u32 address, u32 len, u8 * data)
{
// Check address: 4byte aligned & page(256bytes) aligned
u32 page_begin = address & (~0xff);
u32 page_end = (address + len) & (~0xff);
u32 page_cnt = ((page_end - page_begin) >> 8) + 1;
u32 addr_begin = address;
u32 addr_end = (page_cnt == 1) ? (address + len) : (page_begin + 0x100);
u32 size = addr_end - addr_begin;
u8 *buffer = data;
u8 write_data[12];
u32 offset_to_align;
u32 read_word;
u32 i;
FLASH_Write_Lock();
while(page_cnt){
offset_to_align = addr_begin & 0x3;
if(offset_to_align != 0){
read_word = HAL_READ32(SPI_FLASH_BASE, addr_begin - offset_to_align);
for(i = offset_to_align;i < 4;i++){
read_word = (read_word & (~(0xff << (8*i)))) |( (*buffer) <<(8*i));
size--;
buffer++;
if(size == 0)
break;
}
FLASH_TxData12B(addr_begin - offset_to_align, 4, (u8*)&read_word);
}
addr_begin = (((addr_begin-1) >> 2) + 1) << 2;
for(;size >= 12 ;size -= 12){
_memcpy(write_data, buffer, 12);
FLASH_TxData12B(addr_begin, 12, write_data);
buffer += 12;
addr_begin += 12;
}
for(;size >= 4; size -=4){
_memcpy(write_data, buffer, 4);
FLASH_TxData12B(addr_begin, 4, write_data);
buffer += 4;
addr_begin += 4;
}
if(size > 0){
read_word = HAL_READ32(SPI_FLASH_BASE, addr_begin);
for( i = 0;i < size;i++){
read_word = (read_word & (~(0xff << (8*i)))) | ((*buffer) <<(8*i));
buffer++;
}
FLASH_TxData12B(addr_begin, 4, (u8*)&read_word);
}
page_cnt--;
addr_begin = addr_end;
addr_end = (page_cnt == 1) ? (address + len) : (((addr_begin>>8) + 1)<<8);
size = addr_end - addr_begin;
}
Cache_Flush();
FLASH_Write_Unlock();
return 1;
}
/**
* @brief Configure SPIC IP Clock.
* @param Source: This parameter can be one of the following values:
* @arg BIT_SHIFT_FLASH_CLK_XTAL
* @arg BIT_SHIFT_FLASH_CLK_PLL
* @param Protection: if disable interrupt when switch clock:
* @retval None
*/
IMAGE2_RAM_TEXT_SECTION
void FLASH_ClockSwitch(u32 Source, u32 Protection)
{
/* To avoid gcc warnings */
( void ) Source;
( void ) Protection;
#if defined (ARM_CORE_CM0)
//SPIC_TypeDef *spi_flash = SPIC;
u32 Temp = 0;
u32 timeout = 20;
if (Protection) {
asm volatile ("cpsid i" : : : "memory");
//asm volatile ("cpsid f" : : : "memory");
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
}
/* sequence should be followed strickly */
if (Source == BIT_SHIFT_FLASH_CLK_XTAL) {
/* 1. clock source switch to XTAL */
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL0);
Temp &= ~(BIT_MASK_FLASH_CLK_SEL << BIT_SHIFT_FLASH_CLK_SEL);
Temp |= Source;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL0, Temp);
DelayUs(10);
/* 2. close 400M & 400MPS */
Temp = HAL_READ32(PERI_ON_BASE, REG_LP_FLASH_CTRL);
Temp &= ~(BIT_FLASH_CK_PS_DIV_EN | BIT_FLASH_CK_DIV_EN); /* disable clock ps div & disable clock div*/
HAL_WRITE32(PERI_ON_BASE, REG_LP_FLASH_CTRL, Temp);
FLASH_CalibrationNewCmd(DISABLE);
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_PLL_SYS_PS_REG);
Temp &= ~BIT_EN_CK_400M;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_PLL_SYS_PS_REG, Temp);
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_PLL_SYS_PS_REG);
Temp &= ~BIT_POW_CKGEN_400M;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_PLL_SYS_PS_REG, Temp);
/* 3. SPIC Dummy to low speed dummy */
flash_init_para.FLASH_rd_sample_phase = SPIC_LOWSPEED_SAMPLE_PHASE;
FLASH_SetSpiMode(&flash_init_para, flash_init_para.FLASH_cur_bitmode);
} else if (Source == BIT_SHIFT_FLASH_CLK_PLL) {
/* 1. enable 400M & 400MPS */
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_PLL_SYS_PS_REG);
Temp |= BIT_POW_CKGEN_400M;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_PLL_SYS_PS_REG, Temp);
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_PLL_SYS_PS_REG);
Temp |= BIT_EN_CK_400M;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_PLL_SYS_PS_REG, Temp);
FLASH_CalibrationNewCmd(ENABLE);
Temp = HAL_READ32(PERI_ON_BASE, REG_LP_FLASH_CTRL);
Temp |= (BIT_FLASH_CK_PS_DIV_EN | BIT_FLASH_CK_DIV_EN); /* enable clock ps div & enable clock div*/
HAL_WRITE32(PERI_ON_BASE, REG_LP_FLASH_CTRL, Temp);
/* wait clock ready about 40us */
while (timeout > 0) {
timeout--;
Temp = HAL_READ32(PERI_ON_BASE, REG_LP_FLASH_CTRL);
if ((Temp & BIT_FLASH_PS_DIV_RDY) && (Temp & BIT_FLASH_DIV_RDY))
break;
}
/* 2. clock source switch */
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL0);
Temp &= ~(BIT_MASK_FLASH_CLK_SEL << BIT_SHIFT_FLASH_CLK_SEL);
Temp |= Source;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL0, Temp);
DelayUs(10);
/* 3. SPIC Dummy to high speed dummy */
flash_init_para.FLASH_rd_sample_phase = flash_init_para.FLASH_rd_sample_phase_cal;
FLASH_SetSpiMode(&flash_init_para, flash_init_para.FLASH_cur_bitmode);
}
if (Protection) {
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
asm volatile ("cpsie i" : : : "memory");
//asm volatile ("cpsie f" : : : "memory");
}
#endif
}
IMAGE2_RAM_TEXT_SECTION
void FLASH_Invalidate_Auto_Write(void)
{
/* Auto write related bits in valid command register are all set to 0,
just need to invalidate write single and write enable cmd in auto mode. */
SPIC_TypeDef *spi_flash = SPIC;
/* Disable SPI_FLASH User Mode */
spi_flash->ssienr = 0;
/* Invalidate write single and write enable cmd in auto mode */
spi_flash->wr_single = 0x0;
spi_flash->wr_enable = 0x0;
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_flash_ram.c
|
C
|
apache-2.0
| 17,026
|
/*
* Routines to access hardware
*
* Copyright (c) 2015 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "ameba_soc.h"
struct gdma_memcopy_s {
u32 ch_num;
volatile u32 dma_done;
GDMA_InitTypeDef GDMA_InitStruct;
};
struct gdma_memcopy_s gdma_memcpy;
//xSemaphoreHandle dma_memcpy_sema = NULL;
IMAGE2_RAM_TEXT_SECTION
static void memcpy_gdma_int(void *pData)
{
/* To avoid gcc warnings */
( void ) pData;
//portBASE_TYPE taskWoken = pdFALSE;
/* Clear Pending ISR */
GDMA_ClearINT(0, gdma_memcpy.ch_num);
GDMA_Cmd(0, gdma_memcpy.ch_num, DISABLE);
gdma_memcpy.dma_done = 1;
//xSemaphoreGiveFromISR(dma_memcpy_sema, &taskWoken);
//portEND_SWITCHING_ISR(taskWoken);
}
IMAGE2_RAM_TEXT_SECTION
void memcpy_gdma_init(void)
{
gdma_memcpy.dma_done = 1;
gdma_memcpy.ch_num = GDMA_ChnlAlloc(0, (IRQ_FUN)memcpy_gdma_int, (uint32_t)NULL, 10);
GDMA_StructInit(&(gdma_memcpy.GDMA_InitStruct));
gdma_memcpy.GDMA_InitStruct.GDMA_ChNum = gdma_memcpy.ch_num;
gdma_memcpy.GDMA_InitStruct.GDMA_Index = 0;
gdma_memcpy.GDMA_InitStruct.GDMA_IsrType = (TransferType|ErrType);
gdma_memcpy.GDMA_InitStruct.GDMA_SrcMsize = MsizeEight;
gdma_memcpy.GDMA_InitStruct.GDMA_DstMsize = MsizeEight;
//vSemaphoreCreateBinary(dma_memcpy_sema);
//xSemaphoreTake(dma_memcpy_sema, portMAX_DELAY);
}
IMAGE2_RAM_TEXT_SECTION
static inline u32 memcpy_use_cpu(void *dest, void *src, u32 size)
{
/* To avoid gcc warnings */
( void ) dest;
( void ) src;
if (size < 128) {
return TRUE;
}
if (gdma_memcpy.dma_done == 0) {
return TRUE;
}
return FALSE;
}
IMAGE2_RAM_TEXT_SECTION
int memcpy_gdma(void *dest, void *src, u32 size)
{
u32 size_4byte = size & ~(0x03);
u32 left = size & (0x03);
if (memcpy_use_cpu(dest, src, size) == TRUE) {
_memcpy(dest, src, size);
return 0;
}
gdma_memcpy.dma_done = 0;
if (((u32)(src)& 0x03) || ((u32)(dest)& 0x03)) {
gdma_memcpy.GDMA_InitStruct.GDMA_SrcDataWidth = TrWidthOneByte;
gdma_memcpy.GDMA_InitStruct.GDMA_DstDataWidth = TrWidthOneByte;
gdma_memcpy.GDMA_InitStruct.GDMA_BlockSize = size;
} else {
/* 4-bytes aligned, move 4 bytes each transfer */
gdma_memcpy.GDMA_InitStruct.GDMA_SrcDataWidth = TrWidthFourBytes;
gdma_memcpy.GDMA_InitStruct.GDMA_DstDataWidth = TrWidthFourBytes;
gdma_memcpy.GDMA_InitStruct.GDMA_BlockSize = size_4byte >> 2;
if (left != 0) {
char *dst0 = (char *) dest + size_4byte;
char *src0 = (char *) src + size_4byte;
while (left--){
*dst0++ = *src0++;
}
}
}
gdma_memcpy.GDMA_InitStruct.GDMA_SrcAddr = (u32)(src);
gdma_memcpy.GDMA_InitStruct.GDMA_DstAddr = (u32)(dest);
GDMA_Init(0, gdma_memcpy.ch_num, &(gdma_memcpy.GDMA_InitStruct));
GDMA_Cmd(0, gdma_memcpy.ch_num, ENABLE);
//xSemaphoreTake(dma_memcpy_sema, portMAX_DELAY);
while (gdma_memcpy.dma_done == 0);
return 0;
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_gdma_memcpy.c
|
C
|
apache-2.0
| 2,954
|
/**
******************************************************************************
* @file rtl8721d_i2c.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the I2C firmware
* library, including the following functionalities of theIntel-Integrated
* Circuit (I2C) peripheral:
* - Initialization
* - I2C Speed Setting
* - I2C Slave Address Updating
* - Receive/Send Data Interface
* - I2C Peripheral Control (disable/enable)
* - I2C SleepMode Control
* - Output pin Configuration
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable peripheral clock using the follwoing functions(it is enabled by default)
* RCC_PeriphClockCmd(APBPeriph_I2Cx, APBPeriph_I2Cx_CLOCK, ENABLE); for I2C0
*
* 2. Configure the I2C pinmux.
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2C)
*
* 3. Call I2C_Init(I2Cx, I2C_InitStruct) to configure the i2c with the corresponding configuration
*
* 4. Enable the NVIC and the corresponding interrupt using the function
* I2C_INTConfig() and register the i2c irq handler if you need to use interrupt mode.
*
* 5. When using the DMA mode
* - GDMA related configurations(source address/destination address/block size etc.)
* - Enable the DMA using the I2C_DMAControl() function
*
* 6. Enable i2c module using I2C_Cmd(I2Cx, NewState)
*
* @Note: All other functions can be used separately to modify, if needed,
* a specific feature of the I2C.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
const I2C_DevTable I2C_DEV_TABLE[1] = {
{I2C0_DEV, GDMA_HANDSHAKE_INTERFACE_I2C0_TX, GDMA_HANDSHAKE_INTERFACE_I2C0_RX, I2C0_IRQ_LP},
};
u32 I2C_SLAVEWRITE_PATCH;
u32 IC_FS_SCL_HCNT_TRIM;
u32 IC_FS_SCL_LCNT_TRIM;
/**
* @brief Fills each I2C_InitStruct member with its default value.
* @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
* @retval None
*/
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
{
/* Load HAL initial data structure default value */
I2C_InitStruct->I2CMaster = I2C_MASTER_MODE;
I2C_InitStruct->I2CAddrMod = I2C_ADDR_7BIT;
I2C_InitStruct->I2CSpdMod = I2C_SS_MODE;
I2C_InitStruct->I2CClk = 100;
I2C_InitStruct->I2CIPClk = 10000000;
I2C_InitStruct->I2CAckAddr = 0x11;
I2C_InitStruct->I2CSdaHd = 2;
I2C_InitStruct->I2CSlvSetup = 0x3;
I2C_InitStruct->I2CRXTL = 0x00;
I2C_InitStruct->I2CTXTL = 0x10;
I2C_InitStruct->I2CMstReSTR = DISABLE;
I2C_InitStruct->I2CMstGC = DISABLE;
I2C_InitStruct->I2CMstStartB = DISABLE;
I2C_InitStruct->I2CSlvNoAck = DISABLE;
I2C_InitStruct->I2CFilter = 0x101;
I2C_InitStruct->I2CTxDMARqLv = 0x09;
I2C_InitStruct->I2CRxDMARqLv = 0x03;
I2C_InitStruct->I2CAckAddr1 = 0x12;
}
/**
* @brief Initializes the I2Cx peripheral according to the specified
* parameters in the I2C_InitStruct.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that contains
* the configuration information for the specified I2C peripheral.
* @retval None
*/
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef* I2C_InitStruct)
{
u8 Specical;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_ADDR_MODE(I2C_InitStruct->I2CAddrMod));
assert_param(IS_I2C_SPEED_MODE(I2C_InitStruct->I2CSpdMod));
/* Disable the IC first */
I2Cx->IC_ENABLE &= ~BIT_CTRL_IC_ENABLE;
/* Master case*/
if (I2C_InitStruct->I2CMaster) {
/*RESTART MUST be set in these condition in Master mode.
But it might be NOT compatible in old slaves.*/
if ((I2C_InitStruct->I2CAddrMod == I2C_ADDR_10BIT) || (I2C_InitStruct->I2CSpdMod == I2C_HS_MODE) || (I2C_InitStruct->I2CMstStartB != 0))
I2C_InitStruct->I2CMstReSTR = ENABLE;
I2Cx->IC_CON = (BIT_CTRL_IC_CON_IC_SLAVE_DISABLE_1 |
BIT_CTRL_IC_CON_IC_SLAVE_DISABLE |
(I2C_InitStruct->I2CMstReSTR << 5) |
(I2C_InitStruct->I2CSpdMod << 1) |
(I2C_InitStruct->I2CMaster));
/* To set target addr.*/
Specical = 0;
if ((I2C_InitStruct->I2CMstGC != 0) || (I2C_InitStruct->I2CMstStartB != 0))
Specical = 1;
I2Cx->IC_TAR = ((I2C_InitStruct->I2CAddrMod << 12) |
(Specical << 11) |
(I2C_InitStruct->I2CMstStartB << 10) |
(I2C_InitStruct->I2CAckAddr & BIT_CTRL_IC_TAR));
/* To Set I2C clock*/
I2C_SetSpeed(I2Cx, I2C_InitStruct->I2CSpdMod, I2C_InitStruct->I2CClk, I2C_InitStruct->I2CIPClk);
} /*if (Master)*/
else {
I2Cx->IC_CON = ((I2C_InitStruct->I2CMaster << 7) |
(I2C_InitStruct->I2CMaster << 6) |
(I2C_InitStruct->I2CAddrMod << 3) |
(I2C_InitStruct->I2CSpdMod << 1) |
(I2C_InitStruct->I2CMaster));
/* To set slave0 addr. */
I2Cx->IC_SAR = (I2C_InitStruct->I2CAckAddr & BIT_CTRL_IC_SAR);
/* To set slave1 addr. */
I2Cx->IC_SAR1 = (I2C_InitStruct->I2CAckAddr1 & BIT_CTRL_IC_SAR1);
/* To set slave no ack */
I2Cx->IC_SLV_DATA_NACK_ONLY = I2C_InitStruct->I2CSlvNoAck;
/* Set ack general call. */
I2Cx->IC_ACK_GENERAL_CALL = (I2C_InitStruct->I2CSlvAckGC & BIT_CTRL_IC_ACK_GENERAL_CALL);
/* to set SDA setup time */
I2Cx->IC_SDA_SETUP = (I2C_InitStruct->I2CSlvSetup & BIT_CTRL_IC_SDA_SETUP);
}
/* To set SDA hold time */
I2Cx->IC_SDA_HOLD = (I2C_InitStruct->I2CSdaHd & BIT_CTRL_IC_SDA_HOLD);
/* To set TX_Empty Level */
I2Cx->IC_TX_TL = I2C_InitStruct->I2CTXTL;
/* To set RX_Full Level */
I2Cx->IC_RX_TL = I2C_InitStruct->I2CRXTL;
/* To set IC_FILTER */
I2Cx->IC_FILTER = I2C_InitStruct->I2CFilter;
/* To set TX/RX FIFO level */
I2Cx->IC_DMA_TDLR = I2C_InitStruct->I2CTxDMARqLv;
I2Cx->IC_DMA_RDLR = I2C_InitStruct->I2CRxDMARqLv;
/*I2C Clear all interrupts first*/
I2C_ClearAllINT(I2Cx);
/*I2C Disable all interrupts first*/
I2C_INTConfig(I2Cx, 0xFFFFFFFF, DISABLE);
}
/**
* @brief Master sets I2C Speed Mode.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param SpdMd: I2C Speed Mode.
* This parameter can be one of the following values:
* @arg I2C_SS_MODE:
* @arg I2C_FS_MODE:
* @arg I2C_HS_MODE:(not support in amebaD )
* @param I2Clk: I2C Bus Clock, unit is KHz.
* This parameter can be one of the following values:
* @arg 50:
* @arg 100:
* @arg 400:
* @arg 1000:
* @arg 3000:
* @param IPClk: I2C IP Clock, unit is Hz.
* @retval None
*/
void I2C_SetSpeed(I2C_TypeDef *I2Cx, u32 SpdMd, u32 I2Clk, u32 I2CIPClk)
{
u32 ICHLcnt;
u32 ICHtime;
u32 ICLtime;
u32 IPClkM = I2CIPClk /1000000;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
switch (SpdMd)
{
case I2C_SS_MODE:
{
ICHtime = ((1000000/I2Clk)*I2C_SS_MIN_SCL_HTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2Clk)*I2C_SS_MIN_SCL_LTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IPClkM)/1000;
I2Cx->IC_SS_SCL_HCNT = ICHLcnt + 1;
ICHLcnt = (ICLtime * IPClkM)/1000;
I2Cx->IC_SS_SCL_LCNT = ICHLcnt;
break;
}
case I2C_FS_MODE:
{
ICHtime = ((1000000/I2Clk)*I2C_FS_MIN_SCL_HTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2Clk)*I2C_FS_MIN_SCL_LTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IPClkM)/1000;
if (ICHLcnt > IC_FS_SCL_HCNT_TRIM)/*this part is according to the fine-tune result*/
ICHLcnt -= IC_FS_SCL_HCNT_TRIM;
I2Cx->IC_FS_SCL_HCNT = ICHLcnt + 1;
ICHLcnt = (ICLtime * IPClkM)/1000;
if (ICHLcnt > IC_FS_SCL_LCNT_TRIM)/*this part is according to the fine-tune result*/
ICHLcnt -= IC_FS_SCL_LCNT_TRIM;
I2Cx->IC_FS_SCL_LCNT = ICHLcnt;
break;
}
case I2C_HS_MODE:
{
/*set Fast mode count for Master code*/
ICHtime = ((1000000/I2Clk)*I2C_FS_MIN_SCL_HTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2Clk)*I2C_FS_MIN_SCL_LTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IPClkM)/1000;
I2Cx->IC_FS_SCL_HCNT = ICHLcnt + 1;
ICHLcnt = (ICLtime * IPClkM)/1000;
I2Cx->IC_FS_SCL_LCNT = ICHLcnt;
ICHtime = ((1000000/I2Clk)*I2C_HS_MIN_SCL_HTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
ICLtime = ((1000000/I2Clk)*I2C_HS_MIN_SCL_LTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
ICHLcnt = (ICHtime * IPClkM)/1000;
//if (ICHLcnt>8)/*this part is according to the fine-tune result*/
// ICHLcnt -= 3;
I2Cx->IC_HS_SCL_HCNT = ICHLcnt;
ICHLcnt = (ICLtime * IPClkM)/1000;
//if (ICHLcnt>6)/*this part is according to the fine-tune result*/
// ICHLcnt -= 6;
I2Cx->IC_HS_SCL_LCNT = ICHLcnt;
break;
}
default:
break;
}
}
/**
* @brief Master transmits the address byte to select the slave device.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param Address: specifies the slave address which will be transmitted
* @retval None.
*/
void I2C_SetSlaveAddress(I2C_TypeDef *I2Cx, u16 Address)
{
u32 tar = I2Cx->IC_TAR & ~(BIT_CTRL_IC_TAR);
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/*set target address to generate start signal*/
I2Cx->IC_TAR = (Address & BIT_CTRL_IC_TAR) | tar;
}
/**
* @brief Checks whether the specified I2C flag is set or not.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @param I2C_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg BIT_IC_STATUS_BUS_BUSY:
* @arg I2C_FLAG_SLV_ACTIVITY:
* @arg I2C_FLAG_MST_ACTIVITY:
* @arg I2C_FLAG_RFF:
* @arg I2C_FLAG_RFNE:
* @arg I2C_FLAG_TFE:
* @arg I2C_FLAG_TFNF:
* @arg I2C_FLAG_ACTIVITY:
* @retval The new state of I2C_FLAG:
* - 1: the specified I2C flag is set
* - 0: the specified I2C flag is not set
*/
u8 I2C_CheckFlagState(I2C_TypeDef *I2Cx, u32 I2C_FLAG)
{
u8 bit_status = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
if((I2Cx->IC_STATUS & I2C_FLAG) != 0)
{
/* I2C_FLAG is set */
bit_status = 1;
}
/* Return the I2C_FLAG status */
return bit_status;
}
/**
* @brief ENABLE/DISABLE the I2C's interrupt bits..
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @param I2C_IT: specifies the I2Cx interrupt sources to be enabled or disabled.
* This parameter can be one or combinations of the following values:
* @arg BIT_IC_INTR_MASK_M_DMA_I2C_DONE: I2C DMA Done Interrupt
* @arg BIT_IC_INTR_MASK_M_ADDR_2_MATCH: I2C slave1 Address Match Interrupt
* @arg BIT_IC_INTR_MASK_M_ADDR_1_MATCH: I2C slave0 Address Match Interrupt
* @arg BIT_IC_INTR_MASK_M_GEN_CALL: General Call Interrupt
* @arg BIT_IC_INTR_MASK_M_START_DET: Start or Restart Condition Interrupt
* @arg BIT_IC_INTR_MASK_M_STOP_DET: Stop Condition Interrupt
* @arg BIT_IC_INTR_MASK_M_ACTIVITY: I2C Activity Interrupt
* @arg BIT_IC_INTR_MASK_M_RX_DONE: Slave Transmitter RX Done Interrupt
* @arg BIT_IC_INTR_MASK_M_TX_ABRT: Transmit Abort Interrupt
* @arg BIT_IC_INTR_MASK_M_RD_REQ: Read Request Interrupt
* @arg BIT_IC_INTR_MASK_M_TX_EMPTY: Transmit FIFO Empty Interrupt
* @arg BIT_IC_INTR_MASK_M_TX_OVER: Transmit FIFO Over Interrupt
* @arg BIT_IC_INTR_MASK_M_RX_FULL: Receive FIFO Full Interrupt
* @arg BIT_IC_INTR_MASK_M_RX_OVER: Receive FIFO Over Interrupt
* @arg BIT_IC_INTR_MASK_M_RX_UNDER: Receive FIFO Under Interrupt
* @param NewState: specifies the state of the interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void I2C_INTConfig(I2C_TypeDef *I2Cx, u32 I2C_IT, u32 NewState)
{
u32 TempVal = I2Cx->IC_INTR_MASK;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
if (NewState == ENABLE) {
TempVal |= I2C_IT;
} else {
TempVal &= ~I2C_IT;
}
I2Cx->IC_INTR_MASK = TempVal;
}
/**
* @brief Clears the specified I2C interrupt pending bit.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param INTrBit: specifies the interrupt to be cleared.
* This parameter can be one of the following values:
* @arg BIT_IC_INTR_STAT_R_ADDR_2_MATCH: I2C slave1 Address Match Interrupt
* @arg BIT_IC_INTR_STAT_R_ADDR_1_MATCH: I2C slave0 Address Match Interrupt
* @arg BIT_IC_INTR_STAT_R_GEN_CALL: General Call Interrupt
* @arg BIT_IC_INTR_STAT_R_START_DET: Start or Restart Condition Interrupt
* @arg BIT_IC_INTR_STAT_R_STOP_DET: Stop Condition Interrupt
* @arg BIT_IC_INTR_STAT_R_ACTIVITY: I2C Activity Interrupt
* @arg BIT_IC_INTR_STAT_R_RX_DONE: Slave Transmitter RX Done Interrupt
* @arg BIT_IC_INTR_STAT_R_TX_ABRT: Transmit Abort Interrupt
* @arg BIT_IC_INTR_STAT_R_RD_REQ: Read Request Interrupt
* @arg BIT_IC_INTR_STAT_R_TX_EMPTY: Transmit FIFO Empty Interrupt
* @arg BIT_IC_INTR_STAT_R_TX_OVER: Transmit FIFO Over Interrupt
* @arg BIT_IC_INTR_STAT_R_RX_FULL: Receive FIFO Full Interrupt
* @arg BIT_IC_INTR_STAT_R_RX_OVER: Receive FIFO Over Interrupt
* @arg BIT_IC_INTR_STAT_R_RX_UNDER: Receive FIFO Under Interrupt
* @note BIT_IC_INTR_STAT_R_TX_EMPTY is automatically cleared by hardware when the buffer
* level goes above the I2CTXTL threshold.
* BIT_IC_INTR_STAT_R_RX_FULL is automatically cleared by hardware when the buffer
* level goes below the I2CRXTL threshold.
* @retval None
*/
void I2C_ClearINT(I2C_TypeDef *I2Cx, u32 INTrBit)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
switch (INTrBit) {
case BIT_IC_INTR_STAT_R_ADDR_2_MATCH:
I2Cx->IC_CLR_ADDR_MATCH;
break;
case BIT_IC_INTR_STAT_R_ADDR_1_MATCH:
I2Cx->IC_CLR_ADDR_MATCH;
break;
case BIT_IC_INTR_STAT_R_GEN_CALL:
I2Cx->IC_CLR_GEN_CALL;
break;
case BIT_IC_INTR_STAT_R_START_DET:
I2Cx->IC_CLR_START_DET;
break;
case BIT_IC_INTR_STAT_R_STOP_DET:
I2Cx->IC_CLR_STOP_DET;
break;
case BIT_IC_INTR_STAT_R_ACTIVITY:
I2Cx->IC_CLR_ACTIVITY;
break;
case BIT_IC_INTR_STAT_R_RX_DONE:
I2Cx->IC_CLR_RX_DONE;
break;
case BIT_IC_INTR_STAT_R_TX_ABRT:
I2Cx->IC_CLR_TX_ABRT;
break;
case BIT_IC_INTR_STAT_R_RD_REQ:
I2Cx->IC_CLR_RD_REQ;
break;
case BIT_IC_INTR_STAT_R_TX_OVER:
I2Cx->IC_CLR_TX_OVER;
break;
case BIT_IC_INTR_STAT_R_RX_OVER:
I2Cx->IC_CLR_RX_OVER;
break;
case BIT_IC_INTR_STAT_R_RX_UNDER:
I2Cx->IC_CLR_RX_UNDER;
break;
case BIT_IC_INTR_STAT_R_TX_EMPTY:
case BIT_IC_INTR_STAT_R_RX_FULL:
default:
break;
}
}
/**
* @brief Clears all of the I2C interrupt pending bit.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @retval None
*/
void I2C_ClearAllINT(I2C_TypeDef *I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
I2Cx->IC_CLR_INTR;
}
/**
* @brief Get I2C Raw Interrupt Status.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @retval raw interrupt status
*/
u32 I2C_GetRawINT(I2C_TypeDef *I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
return I2Cx->IC_RAW_INTR_STAT;
}
/**
* @brief Get I2C interrupt status.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @retval interrupt status
*/
u32 I2C_GetINT(I2C_TypeDef *I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
return I2Cx->IC_INTR_STAT;
}
/**
* @brief Master sends single byte through the I2Cx peripheral according to the set of the upper layer.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @param pBuf: point to the data that to be write.
* @param I2CCmd: specifies whether a read from FIFO or a write to FIFO is performed.
* @param I2CStop: specifies whether a STOP is issued after the byte is sent or received.
* @param I2CReSTR: specifies whether a RESTART is issued after the byte is sent or received.
* @retval None
*/
void I2C_MasterSendNullData(I2C_TypeDef *I2Cx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
I2Cx->IC_DATA_CMD = *(pBuf) |
(1 << 11) |
(I2CReSTR << 10) |
(I2CCmd << 8) |
(I2CStop << 9);
}
/**
* @brief Master sends single byte through the I2Cx peripheral according to the set of the upper layer.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @param pBuf: point to the data that to be write.
* @param I2CCmd: specifies whether a read from FIFO or a write to FIFO is performed.
* @param I2CStop: specifies whether a STOP is issued after the byte is sent or received.
* @param I2CReSTR: specifies whether a RESTART is issued after the byte is sent or received.
* @retval None
*/
void I2C_MasterSend(I2C_TypeDef *I2Cx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
I2Cx->IC_DATA_CMD = *(pBuf) |
(I2CReSTR << 10) |
(I2CCmd << 8) |
(I2CStop << 9);
}
/**
* @brief Slave sends single byte through the I2Cx peripheral after receiving read request of Master.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param Data: data to be transmitted.
* @param StopState: specifies whether a STOP is issued after the byte is sent.
* @retval None
*/
void I2C_SlaveSend(I2C_TypeDef *I2Cx, u8 Data)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
I2Cx->IC_DATA_CMD = Data;
}
/**
* @brief Returns the most recent received data by the I2Cx peripheral.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @retval The value of the received data.
*/
u8 I2C_ReceiveData(I2C_TypeDef *I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* Return the data in the DR register */
return (u8)I2Cx->IC_DATA_CMD;
}
/**
* @brief Send data with special length in master mode through the I2Cx peripheral.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param pBuf: point to the data to be transmitted.
* @param len: the length of data that to be transmitted.
* @retval None
*/
void I2C_MasterWrite(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* Write in the DR register the data to be sent */
for(cnt = 0; cnt < len; cnt++)
{
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFNF)) == 0);
if(cnt >= len - 1)
{
/*generate stop signal*/
I2Cx->IC_DATA_CMD = (*pBuf++) | (1 << 9);
}
else
{
I2Cx->IC_DATA_CMD = (*pBuf++);
}
}
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFE)) == 0);
}
/**
* @brief Send data with special length in master mode through the I2Cx peripheral.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @param pBuf: point to the data to be transmitted.
* @param len: the length of data that to be transmitted.
* @retval: The length of data that have been sent to tx fifo
*/
u8 I2C_MasterWriteBrk(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* Write in the DR register the data to be sent */
for(cnt = 0; cnt < len; cnt++)
{
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFNF)) == 0);
if(cnt >= len - 1)
{
/*generate stop signal*/
I2Cx->IC_DATA_CMD = (*pBuf++) | (1 << 9);
}
else
{
I2Cx->IC_DATA_CMD = (*pBuf++);
}
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFE)) == 0) {
if(I2C_GetRawINT(I2Cx) & BIT_IC_RAW_INTR_STAT_TX_ABRT) {
I2C_ClearAllINT(I2Cx);
return cnt;
}
}
}
return cnt;
}
/**
* @brief Read data with special length in master mode through the I2Cx peripheral under DW IP.
* @note Under DW IP, master must send two times read cmd:
* flow is:
* step 1: master request first data entry
* step 2: slave send first data entry
* step 3: master send seconed read cmd to ack first data and request second data
* step 4: slave send second data
* step 5: master rx full interrupt receive fisrt data and ack second data and request third data.
* loop step 4 and step 5.
* so last slave data have no ack, this is permitted by the spec.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @param pBuf: point to the buffer to hold the received data.
* @param len: the length of data that to be received.
* @retval None
*/
void I2C_MasterReadDW(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* read in the DR register the data to be received */
for(cnt = 0; cnt < len; cnt++)
{
if(cnt >= len - 1)
{
/* generate stop singal */
I2Cx->IC_DATA_CMD = 0x0003 << 8;
}
else
{
I2Cx->IC_DATA_CMD = 0x0001 << 8;
}
/* read data */
if(cnt > 0)
{
/* wait for I2C_FLAG_RFNE flag */
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_RFNE)) == 0);
*pBuf++ = (u8)I2Cx->IC_DATA_CMD;
}
}
/* recv last data and NACK */
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_RFNE)) == 0);
*pBuf++ = (u8)I2Cx->IC_DATA_CMD;
}
/**
* @brief Read data with special length in master mode through the I2Cx peripheral under in-house IP.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @param pBuf: point to the buffer to hold the received data.
* @param len: the length of data that to be received.
* @retval The length of data that have received from rx fifo.
*/
u8 I2C_MasterRead(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* read in the DR register the data to be received */
for(cnt = 0; cnt < len; cnt++)
{
if(cnt >= len - 1)
{
/* generate stop singal */
I2Cx->IC_DATA_CMD = 0x0003 << 8;
}
else
{
I2Cx->IC_DATA_CMD = 0x0001 << 8;
}
/* wait for I2C_FLAG_RFNE flag */
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_RFNE)) == 0) {
if(I2C_GetRawINT(I2Cx) & BIT_IC_RAW_INTR_STAT_TX_ABRT) {
I2C_ClearAllINT(I2Cx);
return cnt;
}
}
*pBuf++ = (u8)I2Cx->IC_DATA_CMD;
}
return cnt;
}
/**
* @brief Send data with special length in slave mode through the I2Cx peripheral.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param pBuf: point to the data to be transmitted.
* @param len: the length of data that to be transmitted.
* @retval None
*/
void I2C_SlaveWrite(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
for(cnt = 0; cnt < len; cnt++) {
/* Check I2C RD Request flag */
while((I2Cx->IC_RAW_INTR_STAT & BIT_IC_RAW_INTR_STAT_RD_REQ) == 0);
if (I2C_SLAVEWRITE_PATCH) {
I2Cx->IC_CLR_RD_REQ;
}
/* Check I2C TX FIFO status */
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFNF)) == 0);
I2Cx->IC_DATA_CMD = (*pBuf++);
}
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFE)) == 0);
}
/**
* @brief Read data with special length in slave mode through the I2Cx peripheral.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param pBuf: point to the buffer to hold the received data.
* @param len: the length of data that to be received.
* @retval None
*/
void I2C_SlaveRead(I2C_TypeDef *I2Cx, u8* pBuf, u8 len)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
for(cnt = 0; cnt < len; cnt++) {
/* Check I2C RX FIFO status */
while((I2C_CheckFlagState(I2Cx, (BIT_IC_STATUS_RFNE | BIT_IC_STATUS_RFF))) == 0);
*pBuf++ = (u8)I2Cx->IC_DATA_CMD;
}
}
/**
* @brief Sends data and read data in master mode through the I2Cx peripheral.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param pWriteBuf: Byte to be transmitted.
* @param Writelen: Byte number to be transmitted.
* @param pReadBuf: Byte to be received.
* @param Readlen: Byte number to be received.
* @retval None
*/
void I2C_MasterRepeatRead(I2C_TypeDef* I2Cx, u8* pWriteBuf, u8 Writelen, u8* pReadBuf, u8 Readlen)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* write in the DR register the data to be sent */
for(cnt = 0; cnt < Writelen; cnt++)
{
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFNF)) == 0);
if(cnt >= Writelen - 1)
{
/*generate restart signal*/
I2Cx->IC_DATA_CMD = (*pWriteBuf++) | (1 << 10);
}
else
{
I2Cx->IC_DATA_CMD = (*pWriteBuf++);
}
}
/*Wait I2C TX FIFO not full*/
while((I2C_CheckFlagState(I2Cx, BIT_IC_STATUS_TFNF)) == 0);
I2C_MasterRead(I2Cx, pReadBuf, Readlen);
}
/**
* @brief Enables or disables the specified I2C peripheral, this is one bit register.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @param NewState: new state of the I2Cx peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void I2C_Cmd(I2C_TypeDef *I2Cx, u8 NewState)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
if (NewState != DISABLE)
{
/* Enable the selected I2C peripheral */
I2Cx->IC_ENABLE |= BIT_CTRL_IC_ENABLE;
}
else
{
/* Disable the selected I2C peripheral */
I2Cx->IC_ENABLE &= ~BIT_CTRL_IC_ENABLE;
}
}
/**
* @brief Enable I2C Tx or Rx DMA.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param DmaCtrl: control Transmit DMA Enable or Receive DMA Enable
* This parameter can be one of the following values:
* @arg BIT_IC_DMA_CR_TDMAE:
* @arg BIT_IC_DMA_CR_RDMAE:
* @param NewState: the new state of the DMA function.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void I2C_DMAControl(I2C_TypeDef *I2Cx, u32 DmaCtrl, u8 NewState)
{
u32 I2CDMAEn = I2Cx->IC_DMA_CR;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
if (NewState == ENABLE)
I2CDMAEn |= DmaCtrl;
else
I2CDMAEn &= ~DmaCtrl;
I2Cx->IC_DMA_CR = I2CDMAEn;
}
/**
* @brief Initializes the I2Cx Control Register DMA mode.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param I2C_DmaCmd: Command to control the read or write operation and
* the action after the last data transferred.
* This parameter can be one or combinations of the following values:
* @arg BIT_IC_DMA_CMD_RESTART
* @arg BIT_IC_DMA_CMD_STOP
* @arg BIT_IC_DMA_CMD_RW
* @arg BIT_IC_DMA_CMD_ENABLE
* @param I2C_DmaBLen: length of data.
* This parameter must be set to a value in the 0-0xFFFF range.
* @retval None
*/
void I2C_DmaMode1Config(I2C_TypeDef *I2Cx, u32 I2C_DmaCmd, u32 I2C_DmaBLen)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_DMA_DATA_LEN(I2C_DmaBLen));
I2Cx->IC_DMA_MOD = I2C_DMA_REGISTER;
I2Cx->IC_DMA_DAT_LEN = I2C_DmaBLen;
I2Cx->IC_DMA_CMD = I2C_DmaCmd;
}
/**
* @brief Initializes the I2C Discripter DMA mode.
* @param I2Cx: where I2Cx can be I2C0_DEV .
* @param I2C_DmaCmd: set BIT[0] of IC_DMA_CMD to enable DMA mode.
* @param I2C_DmaBLen: length of data.
* This parameter must be set to a value in the 0-0xFF range.
* @retval None
*/
void I2C_DmaMode2Config(I2C_TypeDef *I2Cx, u32 I2C_DmaCmd, u32 I2C_DmaBLen)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_DMA_DATA_LEN(I2C_DmaBLen));
I2Cx->IC_DMA_MOD = I2C_DMA_DESCRIPTOR;
I2Cx->IC_DMA_CMD = I2C_DmaCmd;
}
/**
* @brief Init and Enable I2C TX GDMA.
* @param Index: 0 .
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pTxBuf: Tx Buffer.
* @param TxCount: Tx Count.
* @retval TRUE/FLASE
* @note can not support legacy DMA mode
*/
BOOL I2C_TXGDMA_Init(
u8 Index,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pTxBuf,
int TxCount
)
{
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);
if (GdmaChnl == 0xFF) {
/* No Available DMA channel */
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_InitStruct->GDMA_DIR = TTFCMemToPeri;
GDMA_InitStruct->GDMA_DstHandshakeInterface = I2C_DEV_TABLE[Index].Tx_HandshakeInterface;
GDMA_InitStruct->GDMA_DstAddr = (u32)&I2C_DEV_TABLE[Index].I2Cx->IC_DATA_CMD;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_DstInc = NoChange;
GDMA_InitStruct->GDMA_SrcInc = IncType;
if (((TxCount & 0x03)==0) && (((u32)(pTxBuf) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeOne;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_BlockSize = TxCount >> 2;
} else {
/* move 1 byte each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_BlockSize = TxCount;
}
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
GDMA_InitStruct->GDMA_SrcAddr = (u32)(pTxBuf);
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Init and Enable I2C RX GDMA.
* @param I2C Index: 0.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pRxBuf: Rx Buffer.
* @param RxCount: Rx Count.
* @retval TRUE/FLASE
* @note support Master or Slave RXDMA
*/
BOOL I2C_RXGDMA_Init(
u8 Index,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pRxBuf,
int RxCount
)
{
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);
if (GdmaChnl == 0xFF) {
/* No Available DMA channel */
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem;
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->GDMA_SrcHandshakeInterface = I2C_DEV_TABLE[Index].Rx_HandshakeInterface;
GDMA_InitStruct->GDMA_SrcAddr = (u32)&I2C_DEV_TABLE[Index].I2Cx->IC_DATA_CMD;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_DstInc = IncType;
GDMA_InitStruct->GDMA_SrcInc = NoChange;
if (((u32)(pRxBuf) & 0x03)==0) {
/* 4-bytes aligned, move 4 bytes each DMA transaction */
GDMA_InitStruct->GDMA_DstMsize = MsizeOne;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
} else {
/* move 1 byte each DMA transaction */
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
}
GDMA_InitStruct->GDMA_BlockSize = RxCount;
GDMA_InitStruct->GDMA_DstAddr = (u32)(pRxBuf);
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
/* multi block close */
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Clock-gated I2C clock domain for address matching interrupts wake up.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @param NewState: the new state of the Rx Path.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void I2C_Sleep_Cmd(I2C_TypeDef *I2Cx, u32 NewStatus)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
if (NewStatus != DISABLE) {
I2C_INTConfig(I2Cx, BIT_IC_INTR_MASK_M_ADDR_1_MATCH|BIT_IC_INTR_MASK_M_ADDR_2_MATCH, ENABLE);
I2Cx->IC_SLEEP |= BIT_IC_SLEEP_CLOCK_CONTROL;
} else {
I2C_INTConfig(I2Cx, BIT_IC_INTR_MASK_M_ADDR_1_MATCH|BIT_IC_INTR_MASK_M_ADDR_2_MATCH, DISABLE);
I2Cx->IC_SLEEP &= ~BIT_IC_SLEEP_CLOCK_CONTROL;
}
}
/**
* @brief Wake up clock domain of Clock-gated I2C after address matching interrupts.
* @param I2Cx: where I2Cx can be I2C0_DEV.
* @retval None
*/
void I2C_WakeUp(I2C_TypeDef *I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
I2C_ClearINT(I2Cx, BIT_IC_INTR_STAT_R_ADDR_2_MATCH);
I2C_ClearINT(I2Cx, BIT_IC_INTR_STAT_R_ADDR_1_MATCH);
I2C_Sleep_Cmd(I2Cx, DISABLE);
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_i2c.c
|
C
|
apache-2.0
| 33,860
|
/**
******************************************************************************
* @file rtl8721d_ipc_api.c
* @author
* @version V1.0.0
* @date 2018-06-11
* @brief This file contains all the API for the IPC function
* library.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief init ipc channel according to ipc_init_config[].
* @retval None
*/
void ipc_table_init(VOID)
{
u32 i;
for (i = 0;;) {
/* Check if search to end */
if (ipc_init_config[i].USER_MSG_TYPE == 0xFFFFFFFF) {
break;
}
if((ipc_init_config[i].func != NULL) || (ipc_init_config[i].IrqData != NULL)) {
IPC_INTUserHandler(i, (void*)ipc_init_config[i].func, ipc_init_config[i].IrqData);
}
i++;
}
}
/**
* @brief exchange messages between KM0 and KM4.
* @param IPC_ChNum: the IPC channel number.
* @param Message: pointer to the message to be exchanged,and should not stored in stack.
* @retval None
*/
void ipc_send_message(u8 IPC_ChNum, u32 Message)
{
u32 CpuId = IPC_CPUID();
IPC_TypeDef *IPC_DEV;
if(CpuId == 1)
IPC_DEV = IPCM4_DEV;
else if(CpuId == 0)
IPC_DEV = IPCM0_DEV;
if(IPC_USER_POINT == ipc_init_config[IPC_ChNum].USER_MSG_TYPE) {
/*message is shared between two cpu ,so it can't store in stack
* assume stack down growth, and 0x100 is an estimated value
*/
//alios todo
//assert_param((Message > (u32)(vTaskStackAddr() + vTaskStackSize()*4)) || (Message < (u32)vTaskStackAddr()));
}
IPC_DEV->IPCx_USR[IPC_ChNum] = (u32)Message;
IPC_INTRequest(IPC_DEV, IPC_ChNum);
}
/**
* @brief get ipc message.
* @param IPC_ChNum: the IPC channel number.
* @retval : pointer to the message to be exchanged.
* @note for data massage, corresponding data cache should be invalidate before access.
*/
u32 ipc_get_message(u8 IPC_ChNum)
{
u32 CpuId = IPC_CPUID();
IPC_TypeDef *IPC_DEV;
/*KM4 read mesaage for km0*/
if(CpuId == 1)
IPC_DEV = IPCM0_DEV;
else if(CpuId == 0)
IPC_DEV = IPCM4_DEV;
return IPC_DEV->IPCx_USR[IPC_ChNum];
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_ipc_api.c
|
C
|
apache-2.0
| 2,519
|
/**
******************************************************************************
* @file rtl8721dhp_ir.c
* @author
* @version V1.0.0
* @date 2017-09-17
* @brief This file contains all the functions prototypes for the IR firmware
* library, including the following functionalities of the Universal Asynchronous
* Receiver/Transmitter peripheral:
* -Initialization
* -IR Control (disable/enable)
* -Receive/Send Data Interface
* -Interrupts and flags management
* -Threshold setting interface
* -Clear TX/RX FIFO
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief Deinitializes the IR peripheral registers to their default values.
* @param None.
* @retval None
*/
void IR_DeInit(void)
{
//1TODO:
// RCC_PeriphClockCmd(APBPeriph_IR, APBPeriph_IR_CLOCK, DISABLE);
}
/**
* @brief Initializes the IR peripheral according to the specified
* parameters in the IR_InitStruct
* @param IR_InitStruct: pointer to a IR_InitTypeDef structure that
* contains the configuration information for the specified IR peripheral
* @retval None
*/
void IR_Init(IR_TypeDef *IRx, IR_InitTypeDef *IR_InitStruct)
{
/* Check the parameters */
assert_param(IS_IR_ALL_PERIPH(IRx));
assert_param(IS_IR_MODE(IR_InitStruct->IR_Mode));
/* Configure IR clock divider. Formula: IR_CLK = IO_CLK/(1+IR_CLK_DIV) */
IRx->IR_CLK_DIV = (IR_InitStruct->IR_Clock) / (IR_InitStruct->IR_Freq) - 1;
IRx->IR_TX_COMPE_DIV = (IR_InitStruct->IR_Clock) / (IR_InitStruct->IR_TxCOMP_CLK) - 1;
if (IR_InitStruct->IR_Mode == IR_MODE_TX) {
/* Check the parameters in TX mode */
assert_param(IS_IR_FREQUENCY(IR_InitStruct->IR_Freq));
assert_param(IS_IR_IDLE_STATUS(IR_InitStruct->IR_TxIdleLevel));
assert_param(IS_IR_TX_DATA_TYPE(IR_InitStruct->IR_TxInverse));
assert_param(IS_IR_TX_FIFO_THRESHOLD(IR_InitStruct->IR_TxFIFOThrLevel));
/* Configure TX mode parameters and disable all TX interrupt */
IRx->IR_TX_CONFIG = (IR_InitStruct->IR_Mode) | \
(IR_InitStruct->IR_TxIdleLevel) | \
(IR_InitStruct->IR_TxInverse) | \
(IR_TX_FIFO_THRESHOLD(IR_InitStruct->IR_TxFIFOThrLevel)) | \
(((IRx->IR_CLK_DIV + 1) / (IR_InitStruct->IR_DutyCycle)) << 16);
/* Clear all TX interrupt and TX FIFO */
IRx->IR_TX_INT_CLR = IR_TX_INT_ALL_CLR | IR_TX_FIFO_CLR;
} else {
/* Check the parameters in RX mode */
assert_param(IS_RX_START_MODE(IR_InitStruct->IR_RxStartMode));
assert_param(IS_IR_RX_FIFO_THRESHOLD(IR_InitStruct->IR_RxFIFOThrLevel));
assert_param(IS_IR_RX_FIFO_FULL_DISCARD_CTRL(IR_InitStruct->IR_RxFIFOFullCtrl));
assert_param(IS_RX_RX_TRIGGER_EDGE(IR_InitStruct->IR_RxTriggerMode));
assert_param(IS_IR_RX_FILTER_TIME_CTRL(IR_InitStruct->IR_RxFilterTime));
assert_param(IS_IR_RX_COUNT_LEVEL_CTRL(IR_InitStruct->IR_RxCntThrType));
assert_param(IS_IR_RX_COUNTER_THRESHOLD(IR_InitStruct->IR_RxCntThr));
/* Enable RX mode */
IRx->IR_TX_CONFIG |= (IR_InitStruct->IR_Mode);
/* Configure RX mode parameters and disable all RX interrupt */
IRx->IR_RX_CONFIG = (IR_InitStruct->IR_RxStartMode) | \
(IR_InitStruct->IR_RxTriggerMode) | \
(IR_InitStruct->IR_RxFilterTime) | \
(IR_RX_FIFO_THRESHOLD(IR_InitStruct->IR_RxFIFOThrLevel));
/* Configure IR RX counter threshold parameters */
IRx->IR_RX_CNT_INT_SEL = (IR_InitStruct->IR_RxCntThrType) | (IR_InitStruct->IR_RxCntThr);
/* Clear all RX interrupt and RX FIFO */
IRx->IR_RX_INT_CLR = IR_RX_INT_ALL_CLR | IR_RX_FIFO_CLR;
}
}
/**
* @brief Fills each IR_InitStruct member with its default value.
* @param IR_InitStruct: pointer to an IR_InitTypeDef structure which will be initialized.
* @retval None
*/
void IR_StructInit(IR_InitTypeDef *IR_InitStruct)
{
IR_InitStruct->IR_Clock = 100000000; /*100M*/
IR_InitStruct->IR_Freq = 38000;
IR_InitStruct->IR_DutyCycle = 3;
IR_InitStruct->IR_Mode = IR_MODE_TX;
IR_InitStruct->IR_TxIdleLevel = IR_IDLE_OUTPUT_LOW;
IR_InitStruct->IR_TxInverse = IR_TX_DATA_NORMAL | IR_TX_DATA_CARRIER_NORMAL;
IR_InitStruct->IR_TxFIFOThrLevel = 0;
IR_InitStruct->IR_TxCOMP_CLK = 1000000; /*1M*/
IR_InitStruct->IR_RxStartMode = IR_RX_AUTO_MODE;
IR_InitStruct->IR_RxFIFOThrLevel = 0;
IR_InitStruct->IR_RxFIFOFullCtrl = IR_RX_FIFO_FULL_DISCARD_NEWEST;
IR_InitStruct->IR_RxTriggerMode = IR_RX_DOUBLE_EDGE;
IR_InitStruct->IR_RxFilterTime = IR_RX_FILTER_TIME_50NS;
IR_InitStruct->IR_RxCntThrType = IR_RX_COUNT_LOW_LEVEL;
IR_InitStruct->IR_RxCntThr = 0x23a; /* This value can be 0 to 0x7fffffff */
}
/**
* @brief Enable or disable the selected IR mode.
* @param mode: selected IR operation mode.
* This parameter can be the following values:
* @arg IR_MODE_TX: Transmission mode.
* @arg IR_MODE_RX: Receiving mode.
* @param NewState: new state of the operation mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void IR_Cmd(IR_TypeDef *IRx, u32 mode, u32 NewState)
{
/* Check the parameters */
assert_param(IS_IR_ALL_PERIPH(IRx));
assert_param(IS_IR_MODE(mode));
if (NewState == ENABLE) {
if (mode == IR_MODE_TX)
IRx->IR_TX_CONFIG |= IR_TX_START;
else
IRx->IR_RX_CONFIG |= IR_RX_START;
} else if (NewState == DISABLE) {
if (mode == IR_MODE_TX)
IRx->IR_TX_CONFIG &= ~IR_TX_START;
else
IRx->IR_RX_CONFIG &= ~IR_RX_START;
}
}
/**
* @brief Configure counter threshold value in receiving mode.You can use it to stop receiving IR data.
* @param IR_RxCntThrType:
* This parameter can be the following values:
* @arg IR_RX_Count_Low_Level: Low level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
* @arg IR_RX_Count_High_Level: High level counter value >= IR_RxCntThr, trigger IR_INT_RX_CNT_THR interrupt.
* @param IR_RxCntThr: Configure IR Rx counter threshold value which can be 0 to 0x7fffffffUL.
* @retval None
*/
void IR_SetRxCounterThreshold(IR_TypeDef *IRx, u32 IR_RxCntThrType, u32 IR_RxCntThr)
{
/* Check the parameters */
assert_param(IS_IR_ALL_PERIPH(IRx));
assert_param(IS_IR_RX_COUNT_LEVEL_CTRL(IR_RxCntThrType));
assert_param(IS_IR_RX_COUNTER_THRESHOLD(IR_RxCntThr));
/* Configure IR RX counter threshold parameters */
IRx->IR_RX_CNT_INT_SEL = (IR_RxCntThrType) | (IR_RxCntThr);
}
/**
* @brief Send data.
* @param buf: data buffer to send.
* @param length: buffer length.
* @param IsLastPacket:
* This parameter can be the following values:
* @arg ENABLE: The last data in IR packet and there is no continous data.In other words, An infrared data transmission is completed.
* @arg DISABLE: There is data to be transmitted continuously.
* @retval None
*/
void IR_SendBuf(IR_TypeDef *IRx, u32 *pBuf, u32 len, u32 IsLastPacket)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
if (len == 0)
return;
while (--len)
IRx->IR_TX_FIFO = *pBuf++;
/* If send the last IR packet, SET the following bit */
if (IsLastPacket == _TRUE)
IRx->IR_TX_FIFO = *pBuf |IR_TX_DATA_END_MASK;
else
IRx->IR_TX_FIFO = *pBuf;
}
/**
* @brief Read data From RX FIFO.
* @param buf: buffer address to receive data.
* @param length: read data length.
* @retval None
*/
void IR_ReceiveBuf(IR_TypeDef *IRx, u32 *pBuf, u32 len)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
while (len--)
*pBuf++ = IRx->IR_RX_FIFO;
}
/**
* @brief Enables or disables the specified IR interrupts.
* @param IR_INT: specifies the IR interrupts sources to be enabled or disabled.
* This parameter can be the following values:
* @arg IR_TX_FIFO_EMPTY_INT_EN: TX FIFO empty interrupt.
* @arg IR_TX_FIFO_LEVEL_INT_EN: TX FIFO threshold interrupt.
* @arg IR_TX_FIFO_OVER_INT_EN: TX FIFO overflow interrupt.
* @arg IR_RX_FIFO_FULL_INT_EN: RX FIFO full interrupt.
* @arg IR_RX_FIFO_LEVEL_INT_EN: RX FIFO threshold interrupt.
* @arg IR_RX_CNT_OF_INT_EN: RX counter overflow interrupt.
* @arg IR_RX_FIFO_OF_INT_EN: RX FIFO overflow interrupt.
* @arg IR_RX_CNT_THR_INT_EN: RX counter threshold interrupt.
* @arg IR_RX_FIFO_ERROR_INT_EN: RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
* @param NewState: new state of the specified IR interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void IR_INTConfig(IR_TypeDef *IRx, u32 IR_INT, u32 newState)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
if (IR_MODE(IRx->IR_TX_CONFIG) == IR_MODE_RX) {
assert_param(IS_RX_INT(IR_INT));
if (newState == ENABLE)
IRx->IR_RX_CONFIG |= IR_INT;
else
IRx->IR_RX_CONFIG &= ~IR_INT;
} else {
assert_param(IS_TX_INT(IR_INT));
if (newState == ENABLE)
IRx->IR_TX_CONFIG |=IR_INT;
else
IRx->IR_TX_CONFIG &= ~IR_INT;
}
}
/**
* @brief Mask or unmask the specified IR interrupts.
* @param IR_INT: specifies the IR interrupts sources to be mask or unmask.
* This parameter can be the following values:
* @arg IR_TX_FIFO_EMPTY_INT_MASK: TX FIFO empty interrupt mask.
* @arg IR_TX_FIFO_LEVEL_INT_MASK: TX FIFO threshold interrupt mask.
* @arg IR_TX_FIFO_OVER_INT_MASK: TX FIFO overflow interrupt mask.
* @arg IR_RX_FIFO_FULL_INT_Msk: RX FIFO full interrupt mask.
* @arg IR_RX_FIFO_LEVEL_INT_Msk: RX FIFO threshold interrupt mask.
* @arg IR_RX_CNT_OF_INT_Msk: RX counter overflow interrupt mask.
* @arg IR_RX_FIFO_OF_INT_Msk: RX FIFO overflow interrupt mask.
* @arg IR_RX_CNT_THR_INT_Msk: RX counter threshold interrupt mask.
* @arg IR_RX_FIFO_ERROR_INT_Msk: RX FIFO error read interrupt mask. Trigger when RX FIFO empty and read RX FIFO.
* @param NewState: new state of the specified IR interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void IR_MaskINTConfig(IR_TypeDef *IRx, u32 IR_INT, u32 newState)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
if (IR_MODE(IRx->IR_TX_CONFIG) == IR_MODE_RX) {
assert_param(IS_RX_INT_MASK(IR_INT));
if (newState == ENABLE)
IRx->IR_RX_CONFIG |= IR_INT;
else
IRx->IR_RX_CONFIG &= ~IR_INT;
} else {
assert_param(IS_TX_INT_MASK(IR_INT));
if (newState == ENABLE)
IRx->IR_TX_CONFIG |= IR_INT;
else
IRx->IR_TX_CONFIG &= ~IR_INT;
}
}
/**
* @brief Get the specified IR interrupt status.
* @retval The new state of IR_INT (SET or RESET).
*/
u32 IR_GetINTStatus(IR_TypeDef *IRx)
{
u32 status;
assert_param(IS_IR_ALL_PERIPH(IRx));
if (IR_MODE(IRx->IR_TX_CONFIG) == IR_MODE_RX)
status = (IRx->IR_RX_SR);
else
status = (IRx->IR_TX_SR);
/* Return the IR_INT status */
return status;
}
/**
* @brief Get the specified IR interrupt mask status.
* @retval The new mask state of IR_INT (SET or RESET).
*/
u32 IR_GetIMR(IR_TypeDef *IRx)
{
u32 mask;
assert_param(IS_IR_ALL_PERIPH(IRx));
if (IR_MODE(IRx->IR_TX_CONFIG) == IR_MODE_RX)
mask = IRx->IR_RX_CONFIG & IR_RX_INT_ALL_MASK;
else
mask = IRx->IR_TX_CONFIG & IR_TX_INT_ALL_MASK;
/* Return the IR_INT mask status */
return mask;
}
/**
* @brief Get the specified IR FSM status.
* @retval The new state of FSM (IDLE or RUN).
* @TRUE:RUN, FALSE:IDLE.
*/
u32 IR_FSMRunning(IR_TypeDef *IRx)
{
u32 status = FALSE;
assert_param(IS_IR_ALL_PERIPH(IRx));
if (IR_MODE(IRx->IR_TX_CONFIG) == IR_MODE_RX) {
if((IRx->IR_RX_SR) & IR_RX_FSM_STATUS)
status = TRUE;
} else {
if((IRx->IR_TX_SR) & IR_TX_FSM_STATUS)
status = TRUE;
}
return status;
}
/**
* @brief Clears the IR interrupt pending bits.
* @param IR_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg IR_TX_FIFO_EMPTY_INT_CLR: Clear TX FIFO empty interrupt.
* @arg IR_TX_FIFO_LEVEL_INT_CLR: Clear TX FIFO threshold interrupt.
* @arg IR_TX_FIFO_OVER_INT_CLR: Clear TX FIFO overflow interrupt.
* @arg IR_RX_FIFO_FULL_INT_CLR: Clear RX FIFO full interrupt.
* @arg IR_RX_FIFO_LEVEL_INT_CLR: Clear RX FIFO threshold interrupt.
* @arg IR_RX_CNT_OF_INT_CLR: Clear RX counter overflow interrupt.
* @arg IR_RX_FIFO_OF_INT_CLR: Clear RX FIFO overflow interrupt.
* @arg IR_RX_CNT_THR_INT_CLR: Clear RX counter threshold interrupt.
* @arg IR_RX_FIFO_ERROR_INT_CLR: Clear RX FIFO error read interrupt. Trigger when RX FIFO empty and read RX FIFO.
* @retval None
*/
void IR_ClearINTPendingBit(IR_TypeDef *IRx, u32 IR_CLEAR_INT)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
if (IR_MODE(IRx->IR_TX_CONFIG) == IR_MODE_RX) {
assert_param(IS_RX_INT_CLR(IR_CLEAR_INT));
IRx->IR_RX_INT_CLR |= IR_CLEAR_INT;
} else {
assert_param(IS_TX_INT_CLR(IR_CLEAR_INT));
IRx->IR_TX_INT_CLR |= IR_CLEAR_INT;
}
}
/**
* @brief set tx threshold.when TX FIFO depth <= threshold value, trigger interrupt
* @param thd: tx threshold.
* @retval None
*/
void IR_SetTxThreshold(IR_TypeDef *IRx, uint8_t thd)
{
u32 Tx_config;
assert_param(IS_IR_ALL_PERIPH(IRx));
assert_param(IS_IR_RX_FIFO_THRESHOLD(thd));
Tx_config = IRx->IR_TX_CONFIG;
Tx_config &= ~IR_TX_FIFO_THRESHOLD_MASK;
Tx_config |= IR_TX_FIFO_THRESHOLD(thd);
IRx->IR_TX_CONFIG = Tx_config;
}
/**
* @brief set rx threshold.when RX FIFO depth > threshold value, trigger interrupt
* @param thd: rx threshold.
* @retval None
*/
void IR_SetRxThreshold(IR_TypeDef *IRx, uint8_t thd)
{
u32 Rx_config;
assert_param(IS_IR_ALL_PERIPH(IRx));
assert_param(IS_IR_RX_FIFO_THRESHOLD(thd));
Rx_config = IRx->IR_RX_CONFIG;
Rx_config &= ~IR_RX_FIFO_THRESHOLD_MASK;
Rx_config |= IR_RX_FIFO_THRESHOLD(thd);
IRx->IR_RX_CONFIG = Rx_config;
}
/**
* @brief Get free size of TX FIFO .
* @param None
* @retval the free size of TX FIFO
*/
u32 IR_GetTxFIFOFreeLen(IR_TypeDef *IRx)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
return (IR_TX_FIFO_SIZE - ((IRx->IR_TX_SR & (IR_TX_FIFO_LEVEL)) >> 8)); //IR_TX_FIFO_SIZE - TX FIFO offset
}
/**
* @brief Get data size in RX FIFO.
* @param None
* @retval current data size in RX FIFO.
*/
u32 IR_GetRxDataLen(IR_TypeDef *IRx)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
return ((((IRx->IR_RX_SR) & IR_RX_FIFO_LEVEL) >> 8));
}
/**
* @brief Send one data.
* @param data: send data.
* @retval None
*/
void IR_SendData(IR_TypeDef *IRx, u32 data)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
IRx->IR_TX_FIFO = data;
}
/**
* @brief Start trigger only in manual receive mode.
* @param None.
* @retval None
*/
void IR_StartManualRxTrigger(IR_TypeDef *IRx)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
/* Start Rx manual mode */
IRx->IR_RX_CONFIG |= IR_RX_MANUAL_START;
}
/**
* @brief Read one data.
* @param none
* @retval data which read from RX FIFO.
*/
u32 IR_ReceiveData(IR_TypeDef *IRx)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
return IRx->IR_RX_FIFO;
}
/**
* @brief Clear IR TX FIFO.
* @param none
* @retval None
*/
void IR_ClearTxFIFO(IR_TypeDef *IRx)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
IRx->IR_TX_INT_CLR = IR_TX_FIFO_CLR;
}
/**
* @brief Clear IR RX FIFO.
* @param none
* @retval None
*/
void IR_ClearRxFIFO(IR_TypeDef *IRx)
{
assert_param(IS_IR_ALL_PERIPH(IRx));
IRx->IR_RX_INT_CLR = IR_RX_FIFO_CLR;
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_ir.c
|
C
|
apache-2.0
| 15,591
|
/**
******************************************************************************
* @file rtl8721dlp_keyscan.c
* @author
* @version V1.0.0
* @date 2017-10-16
* @brief This file contains all the functions prototypes for the keyscan firmware
* library, including the following functionalities of keyscan controller:
* - Initialization
* - get key press/release status and index
* - Keyscan sleep mode control
* - Interrupts and flags management
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
#include "rtl8721d_keyscan.h"
/**
* @brief Fills each KeyScan_InitStruct member with its default value.
* @param KeyScan_InitStruct: pointer to an KeyScan_InitTypeDef structure which will be initialized.
* @retval None
*/
void KeyScan_StructInit(KeyScan_InitTypeDef* KeyScan_InitStruct)
{
/* Load HAL initial data structure default value */
KeyScan_InitStruct->KS_ClkDiv = 49;
KeyScan_InitStruct->KS_ColSel = 0x03;
KeyScan_InitStruct->KS_RowSel = 0x03;
KeyScan_InitStruct->KS_WorkMode = KS_REGULAR_SCAN_MODE;
KeyScan_InitStruct->KS_DebounceCnt = 0x3e7;
KeyScan_InitStruct->KS_IntervalCnt = 0x7cf;
KeyScan_InitStruct->KS_ReleaseCnt = 0x3e7;
KeyScan_InitStruct->KS_ThreholdLevel = 8;
KeyScan_InitStruct->KS_LimitLevel = 2;
KeyScan_InitStruct->KS_OverCtrl = KS_FIFO_OVER_CTRL_DIS_NEW;
}
/**
* @brief Initializes the KeyScan peripheral according to the specified
* parameters in the KeyScan_InitStruct.
* @param KeyScan: selected KeyScan peripheral.
* @param KeyScan_InitStruct: pointer to a KeyScan_InitTypeDef structure that contains
* the configuration information for the specified KeyScan peripheral.
* @retval None
*/
void KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KeyScan_InitTypeDef* KeyScan_InitStruct)
{
/* Check the parameters */
assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
assert_param(KeyScan_InitStruct->KS_ClkDiv <= 0xfff);
assert_param((KeyScan_InitStruct->KS_ColSel >= 0x1) && (KeyScan_InitStruct->KS_ColSel <= 0xff));
assert_param((KeyScan_InitStruct->KS_RowSel >= 0x1) && (KeyScan_InitStruct->KS_RowSel <= 0xff));
assert_param(KeyScan_InitStruct->KS_DebounceCnt <= 0xfff);
assert_param(KeyScan_InitStruct->KS_IntervalCnt <= 0xfff);
assert_param(KeyScan_InitStruct->KS_ReleaseCnt <= 0xfff);
assert_param(IS_KS_WORK_MODE(KeyScan_InitStruct->KS_WorkMode));
assert_param(IS_KS_FIFO_OVER_CTRL(KeyScan_InitStruct->KS_OverCtrl));
assert_param(IS_KS_FIFO_LIMIT_LEVEL(KeyScan_InitStruct->KS_LimitLevel));
assert_param(IS_KS_FIFO_TH_LEVEL(KeyScan_InitStruct->KS_ThreholdLevel));
/* Disable the IC first */
KeyScan->KS_CTRL &= (~BIT_KS_RUN_ENABLE);
/* Mask all keyscan interrupt */
KeyScan->KS_IMR &= (~BIT_KS_ALL_INT_MSK);
/* clock divider config */
KeyScan->KS_CLK_DIV &= (~BIT_KS_CLK_DIV);
KeyScan->KS_CLK_DIV |= KeyScan_InitStruct->KS_ClkDiv;
/* Config scan mode*/
KeyScan->KS_CTRL &= (~BIT_KS_WORK_MODE);
KeyScan->KS_CTRL |= KeyScan_InitStruct->KS_WorkMode;
KeyScan->KS_FIFO_CFG = (KeyScan_InitStruct->KS_OverCtrl) | (KeyScan_InitStruct->KS_ThreholdLevel << 16) |\
(KeyScan_InitStruct->KS_LimitLevel << 24);
/* time count config */
KeyScan->KS_TIM_CFG0 &= (~BIT_KS_DEB_TIMER);
KeyScan->KS_TIM_CFG0 |= KeyScan_InitStruct->KS_DebounceCnt;
KeyScan->KS_TIM_CFG1 = (KeyScan_InitStruct->KS_IntervalCnt << 16) | KeyScan_InitStruct->KS_ReleaseCnt;
/* Set col map, config which col to work */
KeyScan->KS_COL_CFG = KeyScan_InitStruct->KS_ColSel;
/* Set row map, config which row to work */
KeyScan->KS_ROW_CFG = KeyScan_InitStruct->KS_RowSel;
/* clear all interrupt status and status flag */
KeyScan->KS_ICR |= BIT_KS_ALL_INT_CLR;
return;
}
/**
* @brief Enables or disables the specified KeyScan interrupts mask.
* @param KeyScan: selected KeyScan peripheral.
* @param KeyScan_IT: specifies the KeyScan interrupt sources to be enabled or masked.
* This parameter can be one or combinations of the following values:
* @arg BIT_KS_SCAN_EVENT_INT_MSK: Mask Scan event interrupt status
* @arg BIT_KS_FIFO_LIMIT_INT_MSK: Mask FIFO limit interrupt status
* @arg BIT_KS_FIFO_OVERFLOW_INT_MSK: Mask FIFO overflow interrupt
* @arg BIT_KS_FIFO_FULL_INT_MSK: Mask FIFO full interrupt
* @arg BIT_KS_SCAN_FINISH_INT_MSK: Mask scan finish interrupt
* @arg BIT_KS_FIFO_NOTEMPTY_INT_MSK: Mask FIFO nonempty interrupt
* @arg BIT_KS_ALL_RELEASE_INT_MSK: Mask All Release interrupt
* @param NewState: new state of the specified KeyScan interrupts mask.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void KeyScan_INTConfig(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT, u8 newState)
{
/* Check the parameters */
assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
if (newState == ENABLE) {
/* Enable KeyScan interrupts */
KeyScan->KS_IMR |= KeyScan_IT;
} else {
/* Disable KeyScan interrupts */
KeyScan->KS_IMR &= (~KeyScan_IT);
}
}
/**
* @brief Clears the specified KeyScan interrupt pending bit.
* @param KeyScan: selected KeyScan peripheral.
* @param KeyScan_IT: specifies the KeyScan interrupt to be cleared.
* This parameter can be one or combinations of the following values:
* @arg BIT_KS_FIFO_LIMIT_INT_STATUS: FIFO limit interrupt status
* @arg BIT_KS_FIFO_OVERFLOW_INT_STATUS: FIFO overflow interrupt status
* @arg BIT_KS_SCAN_FINISH_INT_STATUS: Scan finish interrupt status
* @arg BIT_KS_ALL_RELEASE_INT_STATUS: All Release interrupt status
* @note BIT_KS_SCAN_EVENT_INT_STATUS is automatically cleared by hardware when the data is read.
* BIT_KS_FIFO_FULL_INT_STATUS is automatically cleared by hardware when the buffer level
* goes below the BIT_KS_FIFO_THREHOLD_LEVEL threshold.
* BIT_KS_FIFO_NOTEMPTY_INT_STATUS is automatically cleared by hardware when the FIFO is empty.
* @retval None
*/
void KeyScan_ClearINT(KEYSCAN_TypeDef *KeyScan, u32 KeyScan_IT)
{
/* Check the parameters */
assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
KeyScan->KS_ICR |= KeyScan_IT;
}
/**
* @brief Get KeyScan Raw Interrupt Status.
* @param KeyScan: selected KeyScan peripheral.
* @retval raw interrupt status
*/
u32 KeyScan_GetRawINT(KEYSCAN_TypeDef *KeyScan)
{
/* Check the parameters */
assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
return KeyScan->KS_ISR_RAW;
}
/**
* @brief Get KeyScan interrupt status.
* @param KeyScan: selected KeyScan peripheral.
* @retval interrupt status
*/
u32 KeyScan_GetINT(KEYSCAN_TypeDef *KeyScan)
{
/* Check the parameters */
assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
return KeyScan->KS_ISR;
}
/**
* @brief Get data number of keyscan FIFO.
* @param KeyScan: selected KeyScan peripheral.
* @retval data number of keyscan FIFO
*/
u8 KeyScan_GetDataNum(KEYSCAN_TypeDef *KeyScan)
{
/* Check the parameters */
assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
return (KeyScan->KS_DATA_NUM & BIT_KS_FIFO_DATA_LEVEL);
}
/**
* @brief Clears the FIFO data.
* @param KeyScan: selected KeyScan peripheral.
* @retval None
*/
void KeyScan_ClearFIFOData(KEYSCAN_TypeDef *KeyScan)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
TempVal = KeyScan->KS_FIFO_CFG;
KeyScan->KS_FIFO_CFG = (TempVal | BIT_KS_FIFO_CLR);
}
/**
* @brief Get status of keyscan FIFO.
* @param KeyScan: selected KeyScan peripheral.
* @param KeyScan_Flag: specifies the flag to check.
* This parameter can be one of the following values:
* @arg BIT_KS_FIFO_FULL
* @arg BIT_KS_FIFO_EMPTY
* @retval the new statue of the specified flag.
* This parameter can be: _TRUE or _FALSE.
*/
BOOL KeyScan_GetFIFOState(KEYSCAN_TypeDef *KeyScan, u32 KeyScan_Flag)
{
/* Check the parameters */
assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
if ((KeyScan->KS_DATA_NUM & KeyScan_Flag) != 0) {
return _TRUE;
} else {
return _FALSE;
}
}
/**
* @brief Read data from keyscan FIFO.
* @param KeyScan: selected KeyScan peripheral.
* @param *outBuf: buffer to save data read from KeyScan FIFO.
* @param count: number of data to be read.
* @retval None
*/
void KeyScan_Read(KEYSCAN_TypeDef *KeyScan, u32 *outBuf, u8 count)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
for (TempVal = 0; TempVal < count; TempVal++) {
*outBuf++ = KeyScan->KS_DATA_ENTRY;
}
return;
}
/**
* @brief Enables or disables the specified KeyScan peripheral.
* @param KeyScan: selected KeyScan peripheral.
* @param NewState: new state of the KeyScan peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void KeyScan_Cmd(KEYSCAN_TypeDef *KeyScan, u8 NewState)
{
/* Check the parameters */
assert_param(IS_KEYSCAN_ALL_PERIPH(KeyScan));
if (NewState != DISABLE) {
/* Enable the KeyScan peripheral */
KeyScan->KS_CTRL |= BIT_KS_RUN_ENABLE;
} else {
/* Disable the KeyScan peripheral */
KeyScan->KS_CTRL &= (~BIT_KS_RUN_ENABLE);
}
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_keyscan.c
|
C
|
apache-2.0
| 9,634
|
/**
******************************************************************************
* @file rtl8721d_pll.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of the NCO clock:
* - NCO32k
* - NCO8M
* - EXT32k Disable/Enable
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief PLL divider set
* @param div: Division
*/
void PLL_Div(u32 div)
{
u32 Tmp;
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PERI_CLK_CTRL3);
Tmp &= ~(BIT_MASK_HSYS_I2S_CLKDIV << BIT_SHIFT_HSYS_I2S_CLKDIV);
Tmp |= ((u32)div) << BIT_SHIFT_HSYS_I2S_CLKDIV;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PERI_CLK_CTRL3, Tmp);
}
/**
* @brief I2S or PCM PLL select
* @param sel: PLL select
*/
void PLL_Sel(u32 sel)
{
u32 Tmp;
if ((sel == PLL_PCM) ||(sel == PLL_I2S)){
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PERI_CLK_CTRL3);
Tmp &= ~(BIT_MASK_HSYS_AC_SPORT_CKSL << BIT_SHIFT_HSYS_AC_SPORT_CKSL);
Tmp |= ((u32)sel) << BIT_SHIFT_HSYS_AC_SPORT_CKSL;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PERI_CLK_CTRL3, Tmp);
}
else{
}
}
/**
* @brief I2S PLL control register set.
* @param new_state: DISABLE/ENABLE
*/
void PLL_I2S_Set(u32 new_state)
{
u32 Tmp;
if (ENABLE == new_state){
//enable 98.304M PLL
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0);
Tmp |= BIT_SYS_AMACRO_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
Tmp |= (BIT_LP_PLL_BG_I_EN |BIT_LP_PLL_BG_EN);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, Tmp);
DelayUs(2);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
Tmp |= BIT_LP_PLL_MBIAS_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
Tmp |= BIT_PLL_I2S_POWCUT_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
DelayUs(400);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_XTAL_CTRL1);
Tmp &= ~BIT_XTAL_AAC_GM_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_XTAL_CTRL1, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
Tmp |= (BIT_PLL_I2S_DIV_EN | BIT_PLL_I2S_EN);
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PWR_ISO_CTRL);
Tmp &= ~BIT_HSYS_ISO_AUXPLL_I2S;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PWR_ISO_CTRL, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1);
Tmp |= BIT_PLL_I2S_POW_SDM_FCODE;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1, Tmp);
while ((HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_TEST) & BIT_PLL_I2S_RDY) != BIT_PLL_I2S_RDY) ;
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
Tmp |= BIT_PLL_I2S_CLK_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
Tmp |= BIT_PLL_I2S_DIV2_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
}
else{
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
Tmp &= ~(BIT_PLL_I2S_CLK_EN|BIT_PLL_I2S_DIV2_EN|BIT_PLL_I2S_EN|BIT_PLL_I2S_DIV_EN|BIT_PLL_I2S_DIV_EN);
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
}
}
/**
* @brief PCM PLL control register set.
* @param new_state: DISABLE/ENABLE
*/
void PLL_PCM_Set(u32 new_state)
{
u32 Tmp;
if (ENABLE == new_state){
//enable 45.1584M PLL
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0);
Tmp |= BIT_SYS_AMACRO_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
Tmp |= (BIT_LP_PLL_BG_I_EN |BIT_LP_PLL_BG_EN);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, Tmp);
DelayUs(2);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0);
Tmp |= BIT_LP_PLL_MBIAS_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
Tmp |= BIT_PLL_PCM_POWCUT_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
DelayUs(400);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_XTAL_CTRL1);
Tmp &= ~BIT_XTAL_AAC_GM_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_XTAL_CTRL1, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
Tmp |= (BIT_PLL_PCM_DIV_EN | BIT_PLL_PCM_EN);
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PWR_ISO_CTRL);
Tmp &= ~BIT_HSYS_ISO_AUXPLL_PCM;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PWR_ISO_CTRL, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1);
Tmp |= BIT_PLL_PCM_POW_SDM_FCODE;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1, Tmp);
while ((HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_TEST) & BIT_PLL_PCM_RDY) != BIT_PLL_PCM_RDY) ;
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
Tmp |= BIT_PLL_PCM_CLK_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
Tmp |= BIT_PLL_PCM_DIV2_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
}
else{
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
Tmp &= ~(BIT_PLL_PCM_CLK_EN|BIT_PLL_PCM_DIV2_EN|BIT_PLL_PCM_EN|BIT_PLL_PCM_DIV_EN|BIT_PLL_PCM_DIV_EN);
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
}
}
/**
* @brief I2S PLL output adjust by ppm.
* @param ppm: ~0.75ppm per FOF step
* @param action: slower or faster or reset
* This parameter can be one of the following values:
* @arg PLL_AUTO: reset to auto 98.304M
* @arg PLL_FASTER: pll clock faster than 98.304M
* @arg PLL_SLOWER: pll clock slower than 98.304M
*/
void PLL_I2S_ClkTune(u32 ppm, u32 action)
{
u32 Tmp;
u32 FOF_new;
assert_param(ppm<=100);
if (action == PLL_AUTO){
//switch to auto mode
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
Tmp |= BIT2;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
return;
}
//switch to manual mode
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0);
Tmp &= ~BIT2;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL0, Tmp);
//set div.N
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1);
Tmp &= ~(BIT_PLL_MASK_I2S_DIVN_SDM<<BIT_PLL_SHIFT_I2S_DIVN_SDM);
Tmp |= (u32)0x11<<BIT_PLL_SHIFT_I2S_DIVN_SDM;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1, Tmp);
//adjust fo.N, fo.f
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL3);
if (action == PLL_FASTER){
FOF_new = 0x92a+ppm*4/3;
}
else if (action == PLL_SLOWER){
FOF_new = 0x92a-ppm*4/3;
}
else{
FOF_new = 0x92a;
}
Tmp &= ~((BIT_PLL_MASK_I2S_SDM_FON<<BIT_PLL_SHIFT_I2S_SDM_FON)|(BIT_PLL_MASK_I2S_SDM_FOF<<BIT_PLL_SHIFT_I2S_SDM_FOF));
Tmp |= (u32)FOF_new<<BIT_PLL_SHIFT_I2S_SDM_FOF;
Tmp |= (u32)0x5<<BIT_PLL_SHIFT_I2S_SDM_FON;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL3, Tmp);
//reset BIT_PLL_I2S_TRIG_RREQ_EN
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1);
Tmp |= BIT_PLL_I2S_TRIG_RREQ_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1);
Tmp &= ~BIT_PLL_I2S_TRIG_RREQ_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_I2S_CTRL1, Tmp);
}
/**
* @brief PCM PLL output adjust by ppm.
* @param ppm: ~5/6*ppm per FOF step
* @param action: slower or faster or reset
* This parameter can be one of the following values:
* @arg PLL_AUTO: reset to auto 45.1584M
* @arg PLL_FASTER: pll clock faster than 45.1584M
* @arg PLL_SLOWER: pll clock slower than 45.1584M
*/
void PLL_PCM_ClkTune(u32 ppm, u32 action)
{
u32 Tmp;
u32 FOF_new;
assert_param(ppm<=100);
if (action == PLL_AUTO){
//switch to auto mode
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
Tmp |= BIT2;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
return;
}
//switch to manual mode
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0);
Tmp &= ~BIT2;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL0, Tmp);
//set div.N
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1);
Tmp &= ~(BIT_PLL_MASK_PCM_DIVN_SDM<<BIT_PLL_SHIFT_PCM_DIVN_SDM);
Tmp |= (u32)0x10<<BIT_PLL_SHIFT_PCM_DIVN_SDM;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1, Tmp);
//adjust fo.N, fo.f
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL3);
if (action == PLL_FASTER){
FOF_new = 0x1038+ppm*6/5;
}
else if (action == PLL_SLOWER){
FOF_new = 0x1038-ppm*6/5;
}
else{
FOF_new = 0x1038;
}
Tmp &= ~((BIT_PLL_MASK_PCM_SDM_FON<<BIT_PLL_SHIFT_PCM_SDM_FON)|(BIT_PLL_MASK_PCM_SDM_FOF<<BIT_PLL_SHIFT_PCM_SDM_FOF));
Tmp |= (u32)FOF_new<<BIT_PLL_SHIFT_PCM_SDM_FOF;
Tmp |= (u32)0x0<<BIT_PLL_SHIFT_PCM_SDM_FON;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL3, Tmp);
//reset BIT_PLL_PCM_TRIG_RREQ_EN
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1);
Tmp |= BIT_PLL_PCM_TRIG_RREQ_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1, Tmp);
Tmp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1);
Tmp &= ~BIT_PLL_PCM_TRIG_RREQ_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_PLL_PCM_CTRL1, Tmp);
}
/**
* @brief PLL control register2 set.
* @param BitMask: set bit
* @param NewState: DISABLE/ENABLE
*/
void PLL2_Set(u32 BitMask, u32 NewState)
{
/* To avoid gcc warnings */
( void ) BitMask;
( void ) NewState;
#ifdef AMEBAD_TODO
DBG_8195A("%s Please check this function \n", __func__);
#endif
}
/**
* @brief PLL control register3 set.
* @param BitMask: set bit
* @param NewState: DISABLE/ENABLE
*/
void PLL3_Set(u32 BitMask, u32 NewState)
{
/* To avoid gcc warnings */
( void ) BitMask;
( void ) NewState;
#ifdef AMEBAD_TODO
DBG_8195A("%s Please check this function \n", __func__);
#endif
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_pll.c
|
C
|
apache-2.0
| 10,558
|
/**
******************************************************************************
* @file rtl8721dlp_qdec.c
* @author
* @version V1.0.0
* @date 2017-10-17
* @brief This file contains all the functions prototypes for the QDec firmware
* library, including the following functionalities of the Qdecoder
* -Initialization
* -QDec Control (disable/enable):
* -QDec Reset
* -Get status Interface
* -Interrupts and trigger condition management
* -QDec speed meausure
* -QDec speed limit Interrupts
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. configure the QDec pinmux.
*
* 2. Init Qdec.
*
* 3. Reset sub-function if needed.
*
* 4. Set Interrupt trigger condition as needed.
*
* 5. enable sub-function as needed.
*
* 6. Polling status or Get stauts according to the interrupt.
*
*
* @endverbatim
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief Deinitializes the QDEC peripheral registers .
* @param None.
* @retval None
*/
void QDEC_DeInit(void)
{
RCC_PeriphClockCmd(APBPeriph_QDEC0, APBPeriph_QDEC0_CLOCK, DISABLE);
}
/**
* @brief Initializes the QDEC peripheral according to the specified.
* @param QDEC_InitStruct: pointer to a QDEC_InitTypeDef structure that
* contains the configuration information for the specified QDEC peripheral.
* @retval None.
*/
void QDEC_Init(QDEC_TypeDef *QDec, QDEC_InitTypeDef *QDEC_InitStruct)
{
u32 VTmr_rld;
u8 VTmr_Div = 0;
/* Check the parameters */
assert_param(IS_QD_SYS_CLK(QDEC_InitStruct->QD_SysClk));
assert_param(QDEC_InitStruct->QD_SmpClk <= QDEC_InitStruct->QD_SysClk);
assert_param(QDEC_InitStruct->QD_SmpClk >= (QDEC_InitStruct->QD_SysClk >> 5));
assert_param(QDEC_InitStruct->QD_DebounceTmr <= 0x7ff);
assert_param(IS_QD_RC_COUNT_MOD(QDEC_InitStruct->QD_Rc_Mod));
assert_param(IS_QD_PC_PHASE_COUTER(QDEC_InitStruct->QD_Cnt_Sc));
assert_param(QDEC_InitStruct->QD_MPC <= 0xFFFF);
assert_param(IS_QD_IDX_MODE(QDEC_InitStruct->QD_IdxMod));
assert_param(IS_QD_PC_RST_MODE(QDEC_InitStruct->QD_PC_Rst_Mod));
assert_param(IS_QD_PC_RST_PHASE(QDEC_InitStruct->QD_PC_Rst_Phase));
assert_param(IS_QD_VC_MODE(QDEC_InitStruct->QD_VCMod));
/*to avoid overflow*/
/*VTmr_rld =VTmr /(1000/SysClk) = VTmr*SysClk/1000 = Vtmr *(sysclk/1024)*/
VTmr_rld = QDEC_InitStruct->QD_VTmr * (QDEC_InitStruct->QD_SysClk/1000);
assert_param(VTmr_rld <= 0xFFFFFF);
while((VTmr_rld / (1+VTmr_Div)) > 0xFFFF){
VTmr_Div++;
}
VTmr_rld /= (VTmr_Div+1);
RCC_PeriphClockCmd(APBPeriph_QDEC0, APBPeriph_QDEC0_CLOCK, DISABLE);
if(QDEC_InitStruct->QD_SysClk == QD_SYS_CLK_2M){
RCC_PeriphClockSource_QDEC(0, QDEC_CLK_SEL_2M);
}
else{
RCC_PeriphClockSource_QDEC(0, QDEC_CLK_SEL_32K);
}
RCC_PeriphClockCmd(APBPeriph_QDEC0, APBPeriph_QDEC0_CLOCK, ENABLE);
QDec->QDEC_CLK_CFG = (((QDEC_InitStruct->QD_SysClk /QDEC_InitStruct->QD_SmpClk)-1) << 12) |\
(QDEC_InitStruct->QD_DebounceTmr);
QDec->QDEC_CTRL = QDEC_InitStruct->QD_Rc_Mod |QDEC_InitStruct->QD_Cnt_Sc | \
(QDEC_InitStruct->QD_DebounceTmr ? QD_DB_EN:0);
QDec->QDEC_MPC = QDEC_InitStruct ->QD_MPC;
QDec->QDEC_ISC = QDEC_InitStruct->QD_IdxMod | QDEC_InitStruct->QD_PC_Rst_Mod | \
QDEC_InitStruct->QD_PC_Rst_Phase;
QDec->QDEC_VCTRL = ((VTmr_Div) << 16) | QDEC_InitStruct->QD_VCMod;
QDec->QDEC_VTRLD = VTmr_rld;
}
/**
* @brief Fills each QDEC_InitStruct member with its default value.
* @param QDEC_InitStruct: pointer to an QDEC_InitTypeDef structure which will be initialized.
* @retval None.
*/
void QDEC_StructInit(QDEC_InitTypeDef *QDEC_InitStruct)
{
QDEC_InitStruct->QD_SysClk = QD_SYS_CLK_32K;
QDEC_InitStruct->QD_SmpClk = 10000;
QDEC_InitStruct->QD_DebounceTmr = 1;
QDEC_InitStruct->QD_Rc_Mod = QD_RC_COUNT_OF;
QDEC_InitStruct->QD_Cnt_Sc = QD_PC_1PHSAE_1COUNTER;
QDEC_InitStruct->QD_MPC = 0xFFFF;
QDEC_InitStruct->QD_IdxMod = QD_IDX_DISABLE;
QDEC_InitStruct->QD_PC_Rst_Mod = QD_PC_RST_DISABLE;
QDEC_InitStruct->QD_PC_Rst_Phase = QD_PC_RST_PHASE_00;
QDEC_InitStruct->QD_VTmr = 1000;
QDEC_InitStruct->QD_VCMod = QD_VC_MOD_ABS;
}
/**
* @brief Enable or disable the QDec.
* @param QDec: selected Qdec peripheral.
* @param NewState: new state of the QDec.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void QDEC_Cmd(QDEC_TypeDef *QDec, u32 NewState)
{
u8 trycnt =200;
u32 Cur_status = 0;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
if (NewState == ENABLE){
QDec->QDEC_CTRL &= ~QD_MANUAL_INIT;
QDec->QDEC_CTRL |= QD_AXIS_EN;
//auto init should check until auto load done
do{
Cur_status = QDec->QDEC_PC;
if(Cur_status & QD_AL_STATUS)
break;
}while(trycnt--);
} else if (NewState == DISABLE) {
QDec->QDEC_CTRL &= ~QD_AXIS_EN;
}
}
/**
* @brief Reset QDec position counter .
* @param QDec: selected Qdec peripheral.
* @retval None.
*/
void QDEC_RstPC(QDEC_TypeDef *QDec)
{
u32 reg_ctrl;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
reg_ctrl = QDec->QDEC_CTRL;
/*disable compare interrupt to avoid error trigger */
QDec->QDEC_CTRL &= ~(QD_AXIS_EN | QD_PC_CMP_INT_EN);
QDec->QDEC_CTRL |= QD_PC_RST;
QDec->QDEC_CTRL &= ~QD_PC_RST;
QDec->QDEC_CTRL = reg_ctrl;
}
/**
* @brief Reset QDec rotation counter .
* @param QDec: selected Qdec peripheral.
* @retval None.
*/
void QDEC_RstRC(QDEC_TypeDef *QDec)
{
u32 reg_ctrl;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
reg_ctrl = QDec->QDEC_CTRL;
QDec->QDEC_CTRL &= ~(QD_AXIS_EN | QD_RC_CMP_INT_EN);
QDec->QDEC_CTRL |= QD_RC_RST;
QDec->QDEC_CTRL &= ~QD_RC_RST;
QDec->QDEC_CTRL = reg_ctrl;
}
/**
* @brief Reset QDec state machine and all other functions .
* @param QDec: selected Qdec peripheral.
* @retval None.
*/
void QDEC_RstALL(QDEC_TypeDef *QDec)
{
u32 reg_ctrl;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
reg_ctrl = QDec->QDEC_CTRL;
QDec->QDEC_CTRL &= ~QD_AXIS_EN;
QDec->QDEC_CTRL |= QD_ALL_RST;
QDec->QDEC_CTRL &= ~QD_ALL_RST;
QDec->QDEC_CTRL = reg_ctrl;
}
/**
* @brief Configure the number of phase state changed for the position accumulation counter.
* @param QDec: selected Qdec peripheral.
* @param cnt_sc:This parameter can be one of the following values:
* @arg QD_PC_1PHSAE_1COUNTER: position counter change one when Qdecoder change one pahse.
* @arg QD_PC_2PHSAE_1COUNTER: position counter change one when Qdecoder change two pahse.
* @retval None.
*/
void QDEC_SetCntSC(QDEC_TypeDef *QDec, u32 cnt_sc)
{
u32 reg_ctrl;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param(IS_QD_PC_PHASE_COUTER(cnt_sc));
reg_ctrl = QDec->QDEC_CTRL;
reg_ctrl &= ~QD_CNT_SC;
reg_ctrl |= cnt_sc;
QDec->QDEC_CTRL = reg_ctrl;
}
/**
* @brief Set Qdecoder position counter change interrupt trigger valure .
* @param QDec: selected Qdec peripheral.
* @param Pchange:This parameter can be one of the following values:
* @arg QD_PC_CHG_1COUNTER: position counter change +/-1 will trigger interrupt.
* @arg QD_PC_CHG_2COUNTER: position counter change +/-2 will trigger interrupt.
* @arg QD_PC_CHG_4COUNTER: position counter change +/-4 will trigger interrupt.
* @retval None.
*/
void QDEC_SetPChg(QDEC_TypeDef *QDec, u32 Pchange)
{
u32 reg_ctrl;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param(IS_QD_PC_CHG_COUTER(Pchange));
reg_ctrl = QDec->QDEC_CTRL;
/*Jerry_dong suggest because hw do not Exaggerate clock domain*/
QDec->QDEC_CTRL &= ~(QD_AXIS_EN | QD_PC_CHG_INT_EN);
reg_ctrl &= ~QD_PC_CHG_LEVEL;
reg_ctrl |= Pchange;
QDec->QDEC_CTRL = reg_ctrl;
}
/**
* @brief Set Qdecoder position counter compare value.
* @param QDec: selected Qdec peripheral.
* @param CmpPC: compare position counter value.
* @retval None.
*/
void QDEC_SetPCC(QDEC_TypeDef *QDec, u32 CmpPC)
{
u32 reg_mpc;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param(CmpPC <= 0xffff);
reg_mpc = QDec->QDEC_MPC;
reg_mpc &= ~QD_CMP_PC;
reg_mpc |= (CmpPC << 16);
QDec->QDEC_MPC = reg_mpc;
}
/**
* @brief Set Qdecoder max position counter.
* @param QDec: selected Qdec peripheral.
* @param MaxPC: compare rotation counter value.
* @retval None.
*/
void QDEC_SetMPC(QDEC_TypeDef *QDec, u32 MaxPC)
{
u32 reg_mpc;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param(MaxPC <= 0xffff);
reg_mpc = QDec->QDEC_MPC;
reg_mpc &= ~QD_MAX_PC;
reg_mpc |= MaxPC;
QDec->QDEC_MPC = reg_mpc;
}
/**
* @brief Set Qdecoder rotation counter compare value.
* @param QDec: selected Qdec peripheral.
* @param CmpRC: compare rotation counter value.
* @retval None.
*/
void QDEC_SetRCC(QDEC_TypeDef *QDec, u32 CmpRC)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param(CmpRC <= 0xfff);
QDec->QDEC_RC = CmpRC;
}
/**
* @brief Get Qdecoder rotation counter.
* @param QDec: selected Qdec peripheral.
* @retval Qdecoder current rotation counter.
*/
u32 QDEC_GetRC(QDEC_TypeDef *QDec)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
return (((QDec->QDEC_PC) & QD_RC) >> 20);
}
/**
* @brief Get Qdecoder phase status.
* @param QDec: selected Qdec peripheral.
* @retval current phase status of PHA&PHB.
*/
u32 QDEC_GetPhase(QDEC_TypeDef *QDec)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
return (((QDec->QDEC_PC) & QD_PHASE_STATE) >> 18);
}
/**
* @brief Get Qdecoder movement direction.
* @param QDec: selected Qdec peripheral.
* @retval movement direction: 0 for decrease, 1 for increase.
*/
u32 QDEC_GetDir(QDEC_TypeDef *QDec)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
return (((QDec->QDEC_PC) & QD_DIR_STATE) >> 16);
}
/**
* @brief Get Qdecoder position counter.
* @param QDec: selected Qdec peripheral.
* @retval Qdecoder current position counter.
*/
u32 QDEC_GetPC(QDEC_TypeDef *QDec)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
return ((QDec->QDEC_PC) & QD_PC);
}
/**
* @brief Enables or disables the index pulse detection.
* @param QDec: selected Qdec peripheral.
* @param NewState: new state of the Qdecoder index detection.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void QDEC_Idx_Cmd(QDEC_TypeDef *QDec, u32 NewState)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
if (NewState == ENABLE)
QDec->QDEC_ISC |= QD_IDX_EN;
else if (NewState == DISABLE)
QDec->QDEC_ISC &= ~QD_IDX_EN;
}
/**
* @brief QDec set position counter reset mode.
* @param QDec: selected Qdec peripheral.
* @param mode: reset function work mode,This parameter can be:
* QD_PC_RST_DISABLE: disable reset function.
* QD_PC_RST_ONCE : only reset on the 1st index pluse .
* QD_PC_RST_ALWAYS : always reset on the index pluse.
* @param phase: reset phase,This parameter can be:
* QD_PC_RST_AUTO_IDX: reset on the idx pluse edge.
* QD_PC_RST_PHASE_00: reset on phase 00 during index pluse.
* QD_PC_RST_PHASE_01: reset on phase 01 during index pluse.
* QD_PC_RST_PHASE_10: reset on phase 10 during index pluse.
* QD_PC_RST_PHASE_11: reset on phase 11 during index pluse.
* @retval None.
*/
void QDEC_SetRstMod(QDEC_TypeDef *QDec, u32 mode, u32 phase)
{
u32 reg_isc;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param(IS_QD_PC_RST_MODE(mode));
assert_param(IS_QD_PC_RST_PHASE(phase));
reg_isc = QDec->QDEC_ISC;
reg_isc &= ~0x0000005B;
reg_isc |= mode;
reg_isc |= phase;
QDec->QDEC_ISC = reg_isc;
}
/**
* @brief Set velocity Timer duration.
* @param QDec: selected Qdec peripheral.
* @param duration: duration of one velocity measure unit.
* after the duration VC will be captured to VCCAP.
* @retval None.
*/
void QDEC_SetVTmr(QDEC_TypeDef *QDec, u32 duration)
{
u32 vt_div = 0;
u32 Temp = 0;
u32 vt_rld,sysclk;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL1);
if (Temp &= BIT_LSYS_QDEC0_CKSL32K) {
sysclk = QD_SYS_CLK_32K;
} else {
sysclk = QD_SYS_CLK_2M;
}
/*to avoid overflow*/
/*VTmr_rld =VTmr /(1000/SysClk) = VTmr*SysClk/1000 = Vtmr *(sysclk/1024)*/
vt_rld = duration *(sysclk/1000);
assert_param(vt_rld <= 0xFFFFFF);
while((vt_rld / (1+vt_div)) > 0xFFFF){
vt_div++;
}
vt_rld /= (vt_div+1);
QDec->QDEC_VCTRL &= ~QD_VT_DIV;
QDec->QDEC_VCTRL |= vt_div << 16;
QDec->QDEC_VTRLD = vt_rld;
}
/**
* @brief Set velocity counter mode.
* @param QDec: selected Qdec peripheral.
* @param mode: This parameter can be one of the following values:
* @arg QD_VC_MOD_ABS: velocity conter use absolute value of position counter.
* @arg QD_VC_MOD_PC: velocity counter use same vaule of position counter.
* @retval None.
*/
void QDEC_SetVcMod(QDEC_TypeDef *QDec, u32 mode)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param(IS_QD_VC_MODE(mode));
QDec->QDEC_VCTRL &= ~QD_VMUC_MOD;
QDec->QDEC_VCTRL |= mode;
}
/**
* @brief Enables or disables the specified Qdecoder velocity function.
* @param QDec: selected Qdec peripheral.
* @param NewState: new state of the Qdecoder velocity function.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void QDEC_VT_Cmd(QDEC_TypeDef *QDec, u32 NewState)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
if (NewState == ENABLE)
QDec->QDEC_VCTRL |= QD_VMUC_EN;
else if (NewState == DISABLE)
QDec->QDEC_VCTRL &= ~QD_VMUC_EN;
}
/**
* @brief Reset velocity timer and.
* @param QDec: selected Qdec peripheral.
* @retval None.
*/
void QDEC_VtRst(QDEC_TypeDef *QDec)
{
u32 reg_vctrl;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
reg_vctrl = QDec->QDEC_VCTRL;
QDec->QDEC_VCTRL &= ~QD_VMUC_EN;
/*hw clock issue ,may can not sample VMUC Disable*/
DelayUs(500);
QDec->QDEC_VCTRL |= QD_VMUC_RST;
QDec->QDEC_VCTRL &= ~QD_VMUC_RST;
QDec->QDEC_VCTRL = reg_vctrl;
}
/**
* @brief Set Qdec velocity counter up limit value.
* @param QDec: selected Qdec peripheral.
* @param limt: the limited value to be setting.
* @retval None.
*/
void QDEC_SetVcUpLmt(QDEC_TypeDef *QDec, u32 limt)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param(limt <= 0xffff);
QDec->QDEC_VCOMP &= ~QD_VUP_LMT;
QDec->QDEC_VCOMP |= limt << 16;
}
/**
* @brief Set Qdec velocity counter low limit value.
* @param QDec: selected Qdec peripheral.
* @param limt: the limited value to be setting.
* @retval None.
*/
void QDEC_SetVcLowLmt(QDEC_TypeDef *QDec, u32 limt)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param(limt <= 0xffff);
QDec->QDEC_VCOMP &= ~QD_VLOW_LMT;
QDec->QDEC_VCOMP |= limt;
}
/**
* @brief Get Qdec velocity Timer value.
* @param QDec: selected Qdec peripheral.
* @retval velocity timerr value.
*/
u32 QDEC_GetVT(QDEC_TypeDef *QDec)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
return QDec->QDEC_VT;
}
/**
* @brief Get Qdec velocity counter value.
* @param QDec: selected Qdec peripheral.
* @retval velocity counter value.
*/
u32 QDEC_GetVC(QDEC_TypeDef *QDec)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
return QDec->QDEC_VC;
}
/**
* @brief Get Qdec velocity counter capture value.
* @param QDec: selected Qdec peripheral.
* @retval velocity counter capture value.
*/
u32 QDEC_GetVCCAP(QDEC_TypeDef *QDec)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
return QDec->QDEC_VCCAP;
}
/**
* @brief Get Qdec position counter capture value.
* @param QDec: selected Qdec peripheral.
* @retval positon counter capture value.
*/
u32 QDEC_GetPCCAP(QDEC_TypeDef *QDec)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
return QDec->QDEC_PCCAP;
}
/**
* @brief Enables or disables the specified QDec interrupts.
* @param QDec: selected Qdec peripheral.
* @param INT: specifies the QDec interrupts sources to be enabled or disabled.
* This parameter can be the following values:
* @arg QD_RC_CMP_INT_EN: Qdecoder rotation counter compare INT enable.
* @arg QD_VUPLMT_INT_EN: Qdecoder Velocity up limit interrupt enable.
* @arg QD_VLOWLMT_INT_EN: Qdecoder Velocity low limit interrupt enable.
* @arg QD_VCCAP_INT_EN: Qdecoder Velocity counter capture interrupt enable.
* @arg QD_PC_ERR_INT_EN: Qdecoder position counter error INT enable.
* @arg QD_IDX_PULSE_INT_EN: Qdecoder index pulse INT enable.
* @arg QD_RC_UF_INT_EN: Qdecoder rotation counter underflow INT enable.
* @arg QD_RC_OF_INT_EN: Qdecoder rotation counter overflow INT enable.
* @arg QD_PC_CMP_INT_EN: Qdecoder position counter compare INT enable.
* @arg QD_DR_CH_INT_EN: Qdecoder direction changed INT enable.
* @arg QD_PHASE_ILL_INT_EN: Qdecoder phase changed illegal INT enable.
* @arg QD_PC_UF_INT_EN: Qdecoder position counter underflow INT enable.
* @arg QD_PC_OF_INT_EN: Qdecoder position counter overflow INT enable.
* @arg QD_PC_CHG_INT_EN: Qdecoder position counter changed INT enable.
* @param NewState: new state of the specified QDecinterrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void QDEC_INTConfig(QDEC_TypeDef *QDec, u32 INT, u32 newState)
{
u32 velocity_int,counter_int;
assert_param(IS_QDEC_ALL_PERIPH(QDec));
counter_int = INT & QD_COUNTER_INT;
velocity_int = INT & QD_VELOCITY_INT;
if (newState == ENABLE) {
QDec->QDEC_CTRL |= counter_int;
QDec->QDEC_VCTRL |= velocity_int;
}else if (newState == DISABLE) {
QDec->QDEC_CTRL &= ~counter_int;
QDec->QDEC_VCTRL &= ~velocity_int;
}
}
/**
* @brief Mask or unmask the specified QDec interrupts.
* @param QDec: selected Qdec peripheral.
* @param mask: specifies the Qdec interrupts sources to be mask or unmask.
* This parameter can be one or combinations of the following values:
* @arg QD_RC_COMP_INT_MASK: Qdecoder rotation counter compare INT mask.
* @arg QD_VUPLMT_INT_MASK: Qdecoder Velocity up limit interrupt mask.
* @arg QD_VLOWLMT_INT_MASK: Qdecoder Velocity low limit interrupt mask.
* @arg QD_VCCAP_INT_MASK: Qdecoder Velocity counter capture interrupt mask.
* @arg QD_PC_ERR_INT_MASK: Qdecoder position counter error INT mask.
* @arg QD_IDX_PULSE_INT_MASK: Qdecoder index pulse INT mask.
* @arg QD_RC_UF_INT_MASK: Qdecoder rotation counter underflow INT mask.
* @arg QD_RC_OF_INT_MASK: Qdecoder rotation counter overflow INT mask.
* @arg QD_PC_CMP_INT_MASK: Qdecoder position counter compare INT mask.
* @arg QD_DR_CH_INT_MASK: Qdecoder direction changed INT mask.
* @arg QD_PHASE_ILL_INT_MASK: Qdecoder phase changed illegal INT mask.
* @arg QD_PC_UF_INT_MASK: Qdecoder position counter underflow INT mask.
* @arg QD_PC_OF_INT_MASK: Qdecoder position counter overflow INT mask.
* @arg QD_PC_CHG_INT_MASK: Qdecoder position counter changed INT mask.
* @param NewState: new state of the specified QDec interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void QDEC_INTMask(QDEC_TypeDef *QDec, u32 mask, u32 newState)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param((mask & (~QD_ALL_INT_MASK)) == 0);
if (newState == ENABLE)
QDec->QDEC_IMR |= mask;
else if (newState == DISABLE)
QDec->QDEC_IMR &= ~mask;
}
/**
* @brief Clear the specified QDec interrupts.
* @param QDec: selected Qdec peripheral.
* @param INT: specifies the Qdec interrupts sources to be clear.
* This parameter can be one or combinations of the following values:
* @arg QD_RC_COMP_INT_STATUS: Qdecoder rotation counter compare INT status.
* @arg QD_VUPLMT_INT_STATUS: Qdecoder Velocity up limit interrupt status.
* @arg QD_VLOWLMT_INT_STATUS: Qdecoder Velocity low limit interrupt status.
* @arg QD_VCCAP_INT_STATUS: Qdecoder Velocity counter capture interrupt status.
* @arg QD_PC_ERR_INT_STATUS: Qdecoder position counter error INT status.
* @arg QD_IDX_PULSE_INT_STATUS: Qdecoder index pulse INT status.
* @arg QD_RC_UF_INT_STATUS: Qdecoder rotation counter underflow INT status.
* @arg QD_RC_OF_INT_STATUS: Qdecoder rotation counter overflow INT status.
* @arg QD_PC_CMP_INT_STATUS: Qdecoder position counter compare INT status.
* @arg QD_DR_CH_INT_STATUS: Qdecoder direction changed INT status.
* @arg QD_PHASE_ILL_INT_STATUS: Qdecoder phase changed illegal INT status.
* @arg QD_PC_UF_INT_STATUS: Qdecoder position counter underflow INT status.
* @arg QD_PC_OF_INT_STATUS: Qdecoder position counter overflow INT status.
* @arg QD_PC_CHG_INT_STATUS: Qdecoder position counter changed INT status.
* @retval None
*/
void QDEC_ClearINT(QDEC_TypeDef *QDec, u32 INT)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
assert_param((INT & (~QD_ALL_INT_STATUS)) == 0);
QDec->QDEC_ISR |= INT;
}
/**
* @brief Get the specified QDec interrupt status.
* @param QDec: selected Qdec peripheral.
* @retval The new state of IR_INT (SET or RESET).
*/
u32 QDEC_GetRawINT(QDEC_TypeDef *QDec)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
return QDec->QDEC_ISR;
}
/**
* @brief Get the specified QDec interrupt mask status.
* @param QDec: selected Qdec peripheral.
* @retval The mask state of IR_INT (SET or RESET).
*/
u32 QDEC_GetIMR(QDEC_TypeDef *QDec)
{
assert_param(IS_QDEC_ALL_PERIPH(QDec));
return QDec->QDEC_IMR;
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor Corporation *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_qdec.c
|
C
|
apache-2.0
| 22,093
|
/*
* Routines to access rom software library.
*
* Copyright (c) 2019 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "diag.h"
#include "strproc.h"
#include <stdarg.h>
typedef union _va_int_ {
va_list ap;
const int *dp;
} va_int,*pva_int;
int _rtl_vsprintf(char *buf, size_t size, const char *fmt, const int *dp)
{
char *p, *s, *buf_end = NULL;
if(buf == NULL)
return 0;
s = buf;
buf_end = size? (buf + size):(char*)~0;
for(; *fmt != '\0'; ++fmt) {
if(*fmt != '%') {
*s++ = *fmt;
if(s >= buf_end) {
goto Exit;
}
continue;
}
if(*++fmt == 's') {
for(p = (char *)*dp++; *p != '\0'; p++) {
*s++ = *p;
if(s >= buf_end) {
goto Exit;
}
}
}
else { /* Length of item is bounded */
char tmp[20], *q = tmp;
int alt = 0;
int shift = 0;// = 12;
const long *lpforchk = (const long *)dp;
if((*lpforchk) < 0x10) {
shift = 0;
}
else if(((*lpforchk) >= 0x10) && ((*lpforchk) < 0x100)) {
shift = 4;
}
else if(((*lpforchk) >= 0x100) && ((*lpforchk) < 0x1000)) {
shift = 8;
}
else if(((*lpforchk) >= 0x1000) && ((*lpforchk) < 0x10000)) {
shift = 12;
}
else if(((*lpforchk) >= 0x10000) && ((*lpforchk) < 0x100000)) {
shift = 16;
}
else if(((*lpforchk) >= 0x100000) && ((*lpforchk) < 0x1000000)) {
shift = 20;
}
else if(((*lpforchk) >= 0x1000000) && ((*lpforchk) < 0x10000000)) {
shift = 24;
}
else if((*lpforchk) >= 0x10000000) {
shift = 28;
}
else {
shift = 28;
}
if((*fmt >= '0') && (*fmt <= '9'))
{
int width;
unsigned char fch = *fmt;
for(width=0; (fch>='0') && (fch<='9'); fch=*++fmt)
{ width = width * 10 + fch - '0';
}
shift=(width-1)*4;
}
/*
* Before each format q points to tmp buffer
* After each format q points past end of item
*/
if((*fmt == 'x')||(*fmt == 'X') || (*fmt == 'p') || (*fmt == 'P')) {
/* With x86 gcc, sizeof(long) == sizeof(int) */
const long *lp = (const long *)dp;
long h = *lp++;
int hex_count = 0;
unsigned long h_back = h;
int ncase = (*fmt & 0x20);
dp = (const int *)lp;
if((*fmt == 'p') || (*fmt == 'P'))
alt=1;
if(alt) {
*q++ = '0';
*q++ = 'X' | ncase;
}
while(h_back) {
hex_count += (h_back & 0xF) ? 1 : 0;
h_back = h_back >> 4;
}
if(shift < (hex_count - 1)*4)
shift = (hex_count - 1)*4;
for(; shift >= 0; shift -= 4)
*q++ = "0123456789ABCDEF"[(h >> shift) & 0xF] | ncase;
}
else if(*fmt == 'd') {
int i = *dp++;
char *r;
int digit_space = 0;
if(i < 0) {
*q++ = '-';
i = -i;
digit_space++;
}
p = q; /* save beginning of digits */
do {
*q++ = '0' + (i % 10);
i /= 10;
digit_space++;
} while(i);
for(; shift >= 0; shift -= 4) {
if(digit_space-- > 0) {
; //do nothing
} else {
*q++ = '0';
}
}
/* reverse digits, stop in middle */
r = q; /* don't alter q */
while(--r > p) {
i = *r;
*r = *p;
*p++ = i;
}
}
else if(*fmt == 'c')
*q++ = *dp++;
else {
if(*fmt != '%')
DiagPrintf("%s: format not support!\n", __func__);
*q++ = *fmt;
}
/* now output the saved string */
for(p = tmp; p < q; ++p) {
*s++ = *p;
if(s >= buf_end) {
goto Exit;
}
}
}
}
Exit:
if(buf)
*s = '\0';
return (s - buf);
}
int _rtl_vsnprintf(char *buf, size_t size, const char *fmt, va_list ap)
{
int ret;
va_int m;
m.ap = ap;
ret = _rtl_vsprintf(buf, size, fmt, m.dp);
return ret;
}
int _rtl_snprintf(char* str, size_t size, const char* fmt, ...)
{
int ret;
ret = _rtl_vsprintf(str, size, fmt, ((const int *)&fmt)+1);
return ret;
}
int _rtl_sprintf(char* str, const char* fmt, ...)
{
const char* fmt1;
fmt1 = fmt;
for(; *fmt1 != '\0'; ++fmt1) {
if(*fmt1 != '%')
continue;
else
fmt1 ++;
while(isdigit(*fmt1)){
fmt1 ++;
}
if((*fmt1 == 's') || (*fmt1 == 'x') || (*fmt1 == 'X') || (*fmt1 == 'p') || (*fmt1 == 'P') || (*fmt1 == 'd') || (*fmt1 == 'c') || (*fmt1 == '%'))
continue;
else {
DiagPrintf("%s: format not support!\n", __func__);
break;
}
}
if (ConfigDebugClose == 1)
return 0;
return DiagVSprintf((char*)str, fmt, ((const int *)&fmt)+1);
}
int _rtl_printf(const char* fmt, ...)
{
u32 ret;
const char* fmt1;
log_buffer_t *buf = NULL;
fmt1 = fmt;
for(; *fmt1 != '\0'; ++fmt1) {
if(*fmt1 == '"') {
do {
fmt1 ++;
} while(*fmt1 != '"');
fmt1 ++;
}
if(*fmt1 != '%')
continue;
else
fmt1 ++;
while(isdigit(*fmt1)){
fmt1 ++;
}
if((*fmt1 == 's') || (*fmt1 == 'x') || (*fmt1 == 'X') || (*fmt1 == 'p') || (*fmt1 == 'P') || (*fmt1 == 'd') || (*fmt1 == 'c') || (*fmt1 == '%'))
continue;
else {
DiagPrintf("%s: format not support!\n", __func__);
break;
}
}
if (ConfigDebugClose == 1)
return 0;
if (ConfigDebugBuffer == 1 && ConfigDebugBufferGet != NULL) {
buf = (log_buffer_t *)ConfigDebugBufferGet(fmt);
}
if (buf != NULL) {
return DiagVSprintf(buf->buffer, fmt, ((const int *)&fmt)+1);
} else {
ret = DiagVSprintf(NULL, fmt, ((const int *)&fmt)+1);
return ret;
}
}
/*
* Fast implementation of tolower() for internal usage. Do not use in your
* code.
*/
static inline char _tolower(const char c)
{
return c | 0x20;
}
int _rtl_sscanf(const char *buf, const char *fmt, ...)
{
int ret;
char nxt_fmt = -1;
va_list args;
const char* fmt1;
fmt1 = fmt;
for(; *fmt1 != '\0'; ++fmt1) {
if(*fmt1 != '%')
continue;
else
fmt1 ++;
if(*fmt1 == '*')
continue;
while(isdigit(*fmt1)){
fmt1 ++;
}
if(*fmt1 == 'h' || _tolower(*fmt1) == 'l' || _tolower(*fmt1) == 'z') {
nxt_fmt = *fmt1++;
if(nxt_fmt == *fmt1) {
if((nxt_fmt == 'h') || (nxt_fmt == 'l'))
fmt1++;
}
}
if(!*fmt1) {
break;
}
if(*fmt1 == 'n')
continue;
if((*fmt1 == 'c') || (*fmt1 == 's') || (*fmt1 == 'o') || (*fmt1 == 'x') || (*fmt1 == 'X') || (*fmt1 == 'i') || (*fmt1 == 'd') || (*fmt1 == 'u') || (*fmt1 == '%'))
continue;
else {
DiagPrintf("%s: format not support!\n", __func__);
break;
}
}
va_start (args, fmt);
ret = _vsscanf(buf, fmt, args);
va_end (args);
return ret;
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_ram_libc.c
|
C
|
apache-2.0
| 6,443
|
/**
******************************************************************************
* @file rtl8721d_rtc.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
* - Initialization
* - Calendar (Time and Date) configuration
* - Alarms configuration
* - WakeUp Timer configuration
* - Daylight Saving configuration
* - Output pin Configuration
* - Smooth digital Calibration configuration
* - TimeStamp configuration
* - Interrupts and flags management
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief Converts a 2 digit decimal to BCD format.
* @param Value: Byte to be converted.
* @retval Converted byte
*/
u8 RTC_ByteToBcd2(u8 Value)
{
u8 bcdhigh = 0;
while (Value >= 10) {
bcdhigh++;
Value -= 10;
}
return ((u8)(bcdhigh << 4) | Value);
}
/**
* @brief Convert from 2 digit BCD to Binary.
* @param Value: BCD value to be converted.
* @retval Converted word
*/
u8 RTC_Bcd2ToByte(u8 Value)
{
u8 tmp = 0;
tmp = (u8)(((Value & 0xF0) >> 0x4) * 10);
return ((u8)(tmp + (Value & 0x0F)));
}
/**
* @brief Enters the RTC Initialization mode.
* @note the time, date and prescaler registers can be updated in init mode.
* @param None
* @retval status value:
* - 1: RTC is in Init mode
* - 0: RTC is not in Init mode
*/
u32 RTC_EnterInitMode(void)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 counter = 0x00;
u32 status = 0;
u32 initstatus = 0x00;
/* Check if the Initialization mode is set */
if ((RTC->ISR & RTC_ISR_INITF) == 0) {
/* Set the Initialization mode */
RTC->ISR |= (u32)RTC_ISR_INIT;
/* Wait till RTC is in INIT state and if Time out is reached exit */
do {
/* check Calendar registers update is allowed */
initstatus = RTC->ISR & RTC_ISR_INITF;
counter++;
} while((counter != INITMODE_TIMEOUT) && (initstatus == 0x00));
if (RTC->ISR & RTC_ISR_INITF) {
status = 1;
} else {
status = 0;
}
} else {
status = 1;
}
return (status);
}
/**
* @brief Exits the RTC Initialization mode.
* @note When the initialization sequence is complete, the calendar restarts
* counting after 4 RTCCLK cycles.
* @param None
* @retval None
* @about 3 RTC clock
*/
void RTC_ExitInitMode(void)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
/* Exit Initialization mode */
RTC->ISR &= ~RTC_ISR_INIT;
}
/**
* @brief Waits until the RTC Time register (RTC_TR) is
* synchronized with RTC APB clock.
* @note To read the calendar through the shadow registers after Calendar
* initialization, calendar update or after wakeup from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
* correctly copied into the RTC_TR shadow registers.
* @param None
* @retval status value:
* - 1: RTC registers are synchronised
* - 0: RTC registers are not synchronised
* @about 2 RTC clock
*/
u32 RTC_WaitForSynchro(void)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 counter = 0;
u32 status = 0;
u32 synchrostatus = 0x00;
/* we can not poll RTC_ISR_RSF when RTC_CR_BYPSHAD */
if (RTC->CR & RTC_CR_BYPSHAD) {
return 1;
}
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* write 1 to Clear RSF flag */
RTC->ISR |= RTC_ISR_RSF;
/* Wait the registers to be synchronised */
do {
synchrostatus = RTC->ISR & RTC_ISR_RSF; /* 6bus cycle one time */
counter++;
} while ((counter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
if (RTC->ISR & RTC_ISR_RSF) {
status = 1;
} else {
status = 0;
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
return (status);
}
/**
* @brief Enables or Disables the Bypass Shadow feature.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @param NewState: new state of the Bypass Shadow feature.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
u32 RTC_BypassShadowCmd(u32 NewState)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 status;
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Set Initialization mode */
if (RTC_EnterInitMode()) {
if (NewState != DISABLE) {
/* Set the BYPSHAD bit */
RTC->CR |= RTC_CR_BYPSHAD;
} else {
/* Reset the BYPSHAD bit */
RTC->CR &= ~RTC_CR_BYPSHAD;
}
/* Exit Initialization mode */
RTC_ExitInitMode();
if (RTC_WaitForSynchro()) {
status = 1;
} else {
status = 0;
}
} else {
status = 0;
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
return status;
}
/**
* @brief Fills each RTC_InitStruct member with its default value.
* @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be
* initialized.
* @retval None
*/
void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
{
/* Initialize the RTC_HourFormat member */
RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
/* Initialize the RTC_AsynchPrediv member */
RTC_InitStruct->RTC_AsynchPrediv = (u32)0x7F; /* 32768 /128 = 256Hz */
/* Initialize the RTC_SynchPrediv member */
RTC_InitStruct->RTC_SynchPrediv = (u32)0xFF; /* 256 /256 = 1Hz*/
/*Initialize the RTC_Day_Threshold member*/
RTC_InitStruct->RTC_DayThreshold = 365;
}
/**
* @brief Initializes the RTC registers according to the specified parameters
* in RTC_InitStruct.
* @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains
* the configuration information for the RTC peripheral.
* @note The RTC Prescaler register is write protected and can be written in
* initialization mode only.
* @retval status value:
* - 1: RTC registers are initialized
* - 0: RTC registers are not initialized
*/
u32 RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 Temp = 0;
u32 status = 0;
/* Check the parameters */
assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
assert_param(IS_RTC_DAY_THRES(RTC_InitStruct->RTC_DayThreshold));
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Set Initialization mode */
if (RTC_EnterInitMode()) {
/* Configure the RTC PRER to provide 1Hz to the Calendar */
Temp = (RTC_InitStruct->RTC_SynchPrediv) | (RTC_InitStruct->RTC_AsynchPrediv << 16);
RTC->PRER = Temp;
/* Set RTC CR FMT Bit */
Temp = RTC->CR;
Temp &= ((u32)~(RTC_CR_FMT | RTC_DAYTHRES_MSK | RTC_CR_DOVTHIE));
Temp |= ((u32)((RTC_InitStruct->RTC_HourFormat) | (RTC_InitStruct->RTC_DayThreshold<<23)));
/* Reset the BYPSHAD bit, get counter from shadow registger */
Temp &= ~RTC_CR_BYPSHAD;
RTC->CR = Temp;
/* Exit Initialization mode */
RTC_ExitInitMode();
if (RTC_WaitForSynchro()) {
status = 1;
} else {
status = 0;
}
} else {
status = 0;
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
return status;
}
/**
* @brief Fills each RTC_TimeStruct member with its default value
* (Time = 00d:00h:00min:00sec).
* @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be
* initialized.
* @retval None
*/
void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
{
/* Time = 00h:00min:00sec */
RTC_TimeStruct->RTC_H12_PMAM = RTC_H12_AM;
RTC_TimeStruct->RTC_Hours = 0;
RTC_TimeStruct->RTC_Minutes = 0;
RTC_TimeStruct->RTC_Seconds = 0;
RTC_TimeStruct->RTC_Days = 0;
}
/**
* @brief Set the RTC current time.
* @param RTC_Format: specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_Format_BIN: Binary data format
* @arg RTC_Format_BCD: BCD data format
* @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains
* the time configuration information for the RTC.
* @retval status value:
* - 1: RTC Time register is configured
* - 0: RTC Time register is not configured
*/
u32 RTC_SetTime(u32 RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 tmpreg = 0;
u32 status = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(RTC_Format));
if (RTC_Format == RTC_Format_BIN) {
if ((RTC->CR & RTC_CR_FMT) != RTC_HourFormat_24) {
assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
assert_param(IS_RTC_H12_AMPM(RTC_TimeStruct->RTC_H12_PMAM));
} else {
RTC_TimeStruct->RTC_H12_PMAM = 0x00;
assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
}
assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
} else {
if ((RTC->CR & RTC_CR_FMT) != RTC_HourFormat_24) {
tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
assert_param(IS_RTC_HOUR12(tmpreg));
assert_param(IS_RTC_H12_AMPM(RTC_TimeStruct->RTC_H12_PMAM));
} else {
RTC_TimeStruct->RTC_H12_PMAM = 0x00;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
}
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
}
/* Check the input parameters format */
if (RTC_Format != RTC_Format_BIN) {
tmpreg = (((u32)(RTC_TimeStruct->RTC_Hours) << 16) | \
((u32)(RTC_TimeStruct->RTC_Minutes) << 8) | \
((u32)RTC_TimeStruct->RTC_Seconds) | \
((u32)(RTC_TimeStruct->RTC_H12_PMAM) << 22));
} else {
tmpreg = (u32)(((u32)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
((u32)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
((u32)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
(((u32)RTC_TimeStruct->RTC_H12_PMAM) << 22));
}
/* set Days */
tmpreg |= (u32)(RTC_TimeStruct->RTC_Days) << 23;
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Set Initialization mode */
if (RTC_EnterInitMode()) {
/* Set the RTC_TR register */
RTC->TR = (u32)(tmpreg & RTC_TR_RESERVED_MASK);
/* Exit Initialization mode */
RTC_ExitInitMode();
if (RTC_WaitForSynchro()) {
status = 1;
} else {
status = 0;
}
} else {
status = 0;
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
return status;
}
/**
* @brief Get the RTC current Time.
* @param RTC_Format: specifies the format of the returned parameters.
* This parameter can be one of the following values:
* @arg RTC_Format_BIN: Binary data format
* @arg RTC_Format_BCD: BCD data format
* @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will
* contain the returned current time configuration.
* @retval None
*/
void RTC_GetTime(u32 RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(RTC_Format));
/* Get the RTC_TR register */
tmpreg = (u32)(RTC->TR & RTC_TR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
RTC_TimeStruct->RTC_Hours = (u8)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
RTC_TimeStruct->RTC_Minutes = (u8)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
RTC_TimeStruct->RTC_Seconds = (u8)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
RTC_TimeStruct->RTC_H12_PMAM = (u8)((tmpreg & (RTC_TR_PM)) >> 22);
RTC_TimeStruct->RTC_Days = (u16)((tmpreg & RTC_TR_DAY) >> 23);
/* Check the input parameters format */
if (RTC_Format == RTC_Format_BIN) {
/* Convert the structure parameters to Binary format */
RTC_TimeStruct->RTC_Hours = (u8)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
RTC_TimeStruct->RTC_Minutes = (u8)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
RTC_TimeStruct->RTC_Seconds = (u8)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
}
}
/**
* @brief clear day over threshold pending interrupt.
* @retval None
*/
void RTC_DayIntClear(void)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 isr = RTC->ISR;
u32 counter = 0;
/*not clear alarm flag*/
isr &= ~RTC_ISR_ALRAF;
isr |= RTC_ISR_DOVTHF;
RTC->ISR = isr;
while (1) {
/* check Alarm flag clear success*/
if ((RTC->ISR & RTC_ISR_DOVTHF) == 0)
break;
if (counter >= ALARMDIS_TIMEOUT)
break;
counter++;
}
/*delay one 32.768k clock cycle for actual interrupt signal clear*/
DelayUs(36);
}
/**
* @brief Enables or disables the RTC day over threshold interrupt.
* @param NewState: new state of the RTC day over threshold interrupt.
* This parameter can be: ENABLE or DISABLE.
*/
u32 RTC_DayIntCmd(u32 NewState)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 status = 0;
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Set Initialization mode */
if (RTC_EnterInitMode()) {
/* clear isr, or set will fail */
RTC_DayIntClear();
/* Configure the day over threshold interrupt state */
if (NewState != DISABLE) {
/*enable day over threshold interrupt*/
RTC->CR |= (u32)(RTC_CR_DOVTHIE);
} else {
RTC->CR &= (u32)~(RTC_CR_DOVTHIE);
}
/* Exit Initialization mode */
RTC_ExitInitMode();
if (RTC_WaitForSynchro()) {
status = 1;
} else {
status = 0;
}
} else {
status = 0;
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
return status;
}
/**
* @brief Set the RTC day threshold.
* @param DayThres: specifies the day threshold to be configured.
* This parameter can be a value of @ref RTC_Day_Threshold.
* @retval status value:
* - 1: RTC day threshold is configured
* - 0: RTC day threshold is not configured
*/
u32 RTC_DayThresSet(u32 DayThres)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 temp = RTC->CR;
u32 status;
assert_param(IS_RTC_DAY_THRES(DayThres));
temp &= ~RTC_DAYTHRES_MSK;
temp |= (u32)((DayThres) << 23);
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Set Initialization mode */
if (RTC_EnterInitMode()) {
/*Set the RTC_CR register*/
RTC->CR = temp;
/* Exit Initialization mode */
RTC_ExitInitMode();
if (RTC_WaitForSynchro()) {
status = 1;
} else {
status = 0;
}
} else {
status = 0;
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
return status;
}
/**
* @brief Get the RTC day threshold value in RTC_CR register.
* @retval RTC day threshold value
*/
u32 RTC_DayThresGet(void)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
return ((RTC->CR & RTC_DAYTHRES_MSK) >>23);
}
/**
* @brief Set the specified RTC Alarm.
* @note The Alarm register can only be written when the corresponding Alarm
* is disabled (Use the RTC_AlarmCmd(DISABLE)).
* @param RTC_Format: specifies the format of the returned parameters.
* This parameter can be one of the following values:
* @arg RTC_Format_BIN: Binary data format
* @arg RTC_Format_BCD: BCD data format
* @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that
* contains the alarm configuration parameters.
* @retval status value:
* - 1: RTC Time Alarm is configured
* - 0: RTC Time Alarm is not configured
*/
u32 RTC_SetAlarm(u32 RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 tmpreg = 0;
u32 counter = 0;
u32 status = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(RTC_Format));
assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
assert_param(IS_ALARM2_MASK(RTC_AlarmStruct->RTC_Alarm2Mask));
if (RTC_Format == RTC_Format_BIN) {
if ((RTC->CR & RTC_CR_FMT) != RTC_HourFormat_24) {
assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
assert_param(IS_RTC_H12_AMPM(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12_PMAM));
} else {
RTC_AlarmStruct->RTC_AlarmTime.RTC_H12_PMAM = 0x00;
assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
}
assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
} else {
if ((RTC->CR & RTC_CR_FMT) != RTC_HourFormat_24) {
tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
assert_param(IS_RTC_HOUR12(tmpreg));
assert_param(IS_RTC_H12_AMPM(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12_PMAM));
} else {
RTC_AlarmStruct->RTC_AlarmTime.RTC_H12_PMAM = 0x00;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
}
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
}
/* Check the input parameters format */
if (RTC_Format != RTC_Format_BIN) {
tmpreg = (((u32)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
((u32)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
((u32)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
((u32)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12_PMAM) << 22) | \
((u32)RTC_AlarmStruct->RTC_AlarmMask));
} else {
tmpreg = (((u32)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
((u32)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
((u32)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
((u32)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12_PMAM) << 22) | \
((u32)RTC_AlarmStruct->RTC_AlarmMask));
}
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Disable Alarm */
RTC->CR &= ~RTC_Alarm;
while (1) {
/* check Alarm update allowed */
if (RTC->ISR & RTC_ISR_ALMWF)
break;
if (counter >= ALARMDIS_TIMEOUT)
break;
counter++;
}
/* clear isr, or set wll fail */
RTC->ISR |= RTC_ISR_ALRAF;
if (RTC->ISR & RTC_ISR_ALMWF) {
/* Configure the Alarm1 register H:M:S */
RTC->ALMR1L = (u32)tmpreg;
/* Configure the Alarm2 register D */
RTC->ALMR1H = ((u32)RTC_AlarmStruct->RTC_AlarmTime.RTC_Days) | ((u32)RTC_AlarmStruct->RTC_Alarm2Mask);
status = 1;
} else {
status = 0;
}
/* Enable Alarm after this function */
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
return status;
}
/**
* @brief Fills each RTC_AlarmStruct member with its default value
* (Time = 00d:00h:00mn:20sec / Date = 1st day of the month/Mask =
* all fields are masked except Alarm Seconds field).
* @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
* will be initialized.
* @retval None
*/
void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
{
/* Alarm Time Settings : Time = 00h:00mn:00sec */
RTC_AlarmStruct->RTC_AlarmTime.RTC_H12_PMAM = RTC_H12_AM;
RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 20;
RTC_AlarmStruct->RTC_AlarmTime.RTC_Days = 0;
/* Alarm Masks Settings : Mask = all fields are not masked */
RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_Hours | RTC_AlarmMask_Minutes;
/* Alarm2 Mask: Day */
RTC_AlarmStruct->RTC_Alarm2Mask = RTC_Alarm2Mask_Days;
}
/**
* @brief Get the RTC Alarm value and masks.
* @param RTC_Format: specifies the format of the output parameters.
* This parameter can be one of the following values:
* @arg RTC_Format_BIN: Binary data format
* @arg RTC_Format_BCD: BCD data format
* @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will
* contains the output alarm configuration values.
* @retval None
*/
void RTC_GetAlarm(u32 RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 tmpreg = 0;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(RTC_Format));
/* Get the RTC_ALRMxR register */
tmpreg = (u32)(RTC->ALMR1L);
/* Fill the structure with the read parameters */
RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (u8)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (u8)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (u8)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
RTC_AlarmStruct->RTC_AlarmTime.RTC_H12_PMAM = (u8)((tmpreg & RTC_ALRMAR_PM) >> 22);
RTC_AlarmStruct->RTC_AlarmMask = (u32)(tmpreg & RTC_AlarmMask_All);
if (RTC_Format == RTC_Format_BIN) {
RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes);
RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds);
}
/* Get Days */
RTC_AlarmStruct->RTC_AlarmTime.RTC_Days = (u16)((RTC->ALMR1H) & RTC_ALRMBR_DT);
RTC_AlarmStruct->RTC_Alarm2Mask = (u32)((RTC->ALMR1H) & RTC_ALRMBR_MSK3);
}
/**
* @brief Enables or disables the specified RTC Alarm.
* @param NewState: new state of the specified alarm.
* This parameter can be: ENABLE or DISABLE.
*/
void RTC_AlarmCmd(u32 NewState)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 counter = 0;
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Configure the Alarm state */
if (NewState != DISABLE) {
RTC->ISR |= RTC_ISR_ALRAF;
RTC->CR |= (u32)(RTC_Alarm | RTC_Alarm_IntEn);
/* we should wait shadow reigster sync ok */
RTC_WaitForSynchro();
} else {
/* clear isr, or set will fail */
RTC->ISR |= RTC_ISR_ALRAF;
/* Disable the Alarm in RTC_CR register */
RTC->CR &= (u32)~(RTC_Alarm | RTC_Alarm_IntEn);
/* wait alarm disable */
while (1) {
/* check Alarm update allowed */
if (RTC->ISR & RTC_ISR_ALMWF)
break;
if (counter >= ALARMDIS_TIMEOUT)
break;
counter++;
}
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
}
/**
* @brief clear alarm pending interrupt.
* @retval None
*/
void RTC_AlarmClear(void)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 isr = RTC->ISR;
u32 counter = 0;
/*not clear day over thres flag*/
isr &= ~RTC_ISR_DOVTHF;
isr |= RTC_ISR_ALRAF;
RTC->ISR = isr;
while (1) {
/* check Alarm flag clear success*/
if ((RTC->ISR & RTC_ISR_ALRAF) == 0)
break;
if (counter >= ALARMDIS_TIMEOUT)
break;
counter++;
}
/*delay one 32.768k clock cycle for actual interrupt signal clear*/
DelayUs(36);
}
/**
* @brief Adds or substract one hour from the current time.
* @param RTC_DayLightSaving: the value of hour adjustment.
* This parameter can be one of the following values:
* @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
* @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
* @param RTC_StoreOperation: Specifies the value to be written in the BCK bit
* in CR register to store the operation.
* This parameter can be one of the following values:
* @arg RTC_StoreOperation_Reset: BCK Bit Reset
* @arg RTC_StoreOperation_Set: BCK Bit Set
* @retval None
*/
u32 RTC_DayLightSavingConfig(u32 RTC_DayLightSaving, u32 RTC_StoreOperation)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 CRTmp = RTC->CR;
u32 status = 0;
/* Check the parameters */
assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Clear the bits to be configured */
CRTmp &= (u32)~(RTC_CR_BCK);
/* Configure the RTC_CR register */
CRTmp |= (u32)(RTC_DayLightSaving | RTC_StoreOperation);
/* Set Initialization mode */
if (RTC_EnterInitMode()) {
/* write CR */
RTC->CR = CRTmp;
/* Exit Initialization mode */
RTC_ExitInitMode();
if (RTC_WaitForSynchro()) {
status = 1;
} else {
status = 0;
}
} else {
status = 0;
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
//RTC_WaitForSynchro();
return status;
}
/**
* @brief Returns the RTC Day Light Saving stored operation.
* @retval RTC Day Light Saving stored operation.
* - RTC_StoreOperation_Reset
* - RTC_StoreOperation_Set
*/
u32 RTC_GetStoreOperation(void)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
return (RTC->CR & RTC_CR_BCK);
}
/**
* @brief Configures the RTC output.
* @param RTC_Output: Specifies which signal will be routed to the RTC output.
* This parameter can be one of the following values:
* @arg RTC_Output_Disable: No output selected
* @arg RTC_Output_Alarm: signal of Alarm mapped to output
* @arg RTC_Output_clkspre: signal of clkspre mapped to output
* @arg RTC_Output_clkapre: signal of clkapre mapped to output
* @retval None
*/
u32 RTC_OutputConfig(u32 RTC_Output)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 CRTmp = RTC->CR;
u32 status;
/* Check the parameters */
assert_param(IS_RTC_OUTPUT(RTC_Output));
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Clear the bits to be configured */
CRTmp &= (u32)~(RTC_CR_OSEL);
/* Configure the output selection and polarity */
CRTmp |= (u32)(RTC_Output);
/* Set Initialization mode */
if (RTC_EnterInitMode()) {
/* write CR */
RTC->CR = CRTmp;
/* Exit Initialization mode */
RTC_ExitInitMode();
if (RTC_WaitForSynchro()) {
status = 1;
} else {
status = 0;
}
} else {
status = 0;
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
return status;
}
/**
* @brief Configures the Coarse calibration parameters.
* @param CalibSign: CalibSign specifies the sign of the coarse calibration value.
* This parameter can be one of the following values:
* @arg RTC_CalibSign_Positive: The value sign is positive
* @arg RTC_CalibSign_Negative: The value sign is negative
* @param Value: value of coarse calibration expressed in ppm (coded on 7 bits).
* @param CalibPeriod: Calibration period, Compensate DC clkapre cycles every (CALP+1) minutes (coded on 3 bits).
* This parameter can be one of the following values:
* @arg RTC_CalibPeriod_1MIN
* @arg RTC_CalibPeriod_2MIN
* @arg RTC_CalibPeriod_3MIN
* @arg RTC_CalibPeriod_4MIN
* @arg RTC_CalibPeriod_5MIN
* @arg RTC_CalibPeriod_6MIN
* @arg RTC_CalibPeriod_7MIN
* @arg RTC_CalibPeriod_8MIN
* @param Calib_Enable: RTC_Calib_Disable or RTC_Calib_Enable .
* @retval status value:
* - 1: RTC Coarse calibration are initialized
* - 0: RTC Coarse calibration are not initialized
*/
u32 RTC_SmoothCalibConfig(u32 CalibSign, u32 Value, u32 CalibPeriod, u32 Calib_Enable)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 counter = 0;
u32 status = 0;
u32 temp = 0;
/* Check the parameters */
assert_param(IS_RTC_CALIB_SIGN(CalibSign));
assert_param(IS_RTC_CALIB_VALUE(Value));
assert_param(IS_RTC_CALIB_PERIOD(CalibPeriod));
assert_param(IS_RTC_CALIB_ENABLE(Calib_Enable));
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* check if a calibration is pending*/
/* wait until the Calibration is completed*/
while (1) {
temp = RTC->ISR;
if ((temp & RTC_ISR_RECALPF) == 0)
break;
if (counter >= RECALPF_TIMEOUT)
break;
counter++;
}
/* check if the calibration pending is completed or if there is no calibration operation at all*/
if ((RTC->ISR & RTC_ISR_RECALPF) == 0) {
if (Calib_Enable == RTC_Calib_Disable) {
RTC->CALIBR &= ~RTC_Calib_Enable;
} else {
RTC->CALIBR = (u32)(Value | CalibSign | Calib_Enable | CalibPeriod);
}
status = 1;
} else {
status = 0;
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
return status;
}
/**
* @brief Configures the 32K auto calibration parameters.
* @param Cal_Period: value of auto calibration period (coded on 6 bits), unit is based on Unit_Sel.
* @param Unit_Sel: Autocal_sel specifies the sign of the auto calibration.
* This parameter can be one of the following values:
* @arg RTC_32K_AUTOCAL_DISABLE: The auto calibration counter is disable
* @arg RTC_32K_AUTOCAL_MINUTES: The auto calibration counter update per minute
* @arg RTC_32K_AUTOCAL_HOURS: The auto calibration counter update per hour
* @arg RTC_32K_AUTOCAL_DAYS: The auto calibration counter update per day
* @retval status value:
* - 1: RTC 32K auto calibration are configured ok
* - 0: RTC 32K auto calibration are configured fail
* @note:
* - RTC ACAL_CNT[5:0] will be cleared by hardware
*/
u32 RTC_32KAutoCalibConfig(u32 Cal_Period, u32 Unit_Sel)
{
RTC_TypeDef* RTC = ((RTC_TypeDef *) RTC_BASE);
u32 clkacalr = 0;
u32 status;
/* Check the parameters */
assert_param(IS_RTC_32K_AUTOCALIB_THRES(Cal_Period));
assert_param(IS_RTC_32K_AUTOCAL_SIGN(Unit_Sel));
if (Unit_Sel != RTC_32K_AUTOCAL_DISABLE)
assert_param((Cal_Period) > 0);
clkacalr |= (u32)(((Cal_Period)<< 2) | Unit_Sel);
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
/* Set Initialization mode */
if (RTC_EnterInitMode()) {
/*Write CLKACALR */
RTC->CLKACALR = clkacalr;
/* Exit Initialization mode */
RTC_ExitInitMode();
/*Wait shadow reigster sync ok, then ACAL_CNT[5:0] will be cleared by hardware */
if (RTC_WaitForSynchro()) {
status = 1;
} else {
status = 0;
}
} else {
status = 0;
}
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
return status;
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_rtc.c
|
C
|
apache-2.0
| 31,207
|
/**
******************************************************************************
* @file rtl8721dlp_sgpio.c
* @author
* @version V1.0.0
* @date 2017-10-16
* @brief This file provides firmware rom patch functions to manage clk
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
#include "rtl8721d_sgpio.h"
/**
* @brief Fills each SGPIO_RXInitStruct member with its default value.
* @param SGPIO_RXInitStruct: pointer to an SGPIO_RXInitTypeDef structure which will be initialized.
* @retval None
*/
void SGPIO_RX_StructInit(SGPIO_RXInitTypeDef* SGPIO_RXInitStruct)
{
/* Load HAL initial data structure default value */
SGPIO_RXInitStruct->RxDataSrc_Sel = RX_DATA_SRC_EXTERNAL_INPUT;
SGPIO_RXInitStruct->RxTimerEdge_Sel = RX_TIMER_RISING_EDGE;
SGPIO_RXInitStruct->RxPRVal = (2-1);
SGPIO_RXInitStruct->RxPRTC = 0x0;
SGPIO_RXInitStruct->RxTC = 0x0;
SGPIO_RXInitStruct->RxData = 0x0;
SGPIO_RXInitStruct->RxData_DP = 0x0;
SGPIO_RXInitStruct->RxData_Dir = RX_DATA_DIR_MSB;
SGPIO_RXInitStruct->RxPosTC = (8-1);
}
/**
* @brief Initializes the SGPIOx peripheral according to the specified
* parameters in the SGPIO_RXInitTypeDef.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_RXInitStruct: pointer to a SGPIO_RXInitTypeDef structure that contains
* the configuration information for the specified SGPIO peripheral.
* @retval None
*/
void SGPIO_RX_Init(SGPIO_TypeDef *SGPIOx, SGPIO_RXInitTypeDef* SGPIO_RXInitStruct)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(IS_RX_DATA_SRC(SGPIO_RXInitStruct->RxDataSrc_Sel));
assert_param(IS_RX_TIMER_TRIGGER_MODE(SGPIO_RXInitStruct->RxTimerEdge_Sel));
assert_param(SGPIO_RXInitStruct->RxPRVal <= 0xffff);
assert_param(SGPIO_RXInitStruct->RxPRTC <= 0xffff);
assert_param(SGPIO_RXInitStruct->RxTC <= 0xffff);
assert_param(SGPIO_RXInitStruct->RxPosTC <= 0x1f);
assert_param(IS_RX_DATA_DIR(SGPIO_RXInitStruct->RxData_Dir));
/* Mask all interrupt */
SGPIOx->SGPIO_IMR |= BIT_SGPIO_INTR_MASK;
/* Disable the SGPIO RX Timer and RX Prescale Timer*/
SGPIOx->SGPIO_RXTMR_CTRL &= (~BIT_SGPIO_RXTMR_CEN);
/*Avoid clock domain crossing issue*/
while(SGPIOx->SGPIO_RXTMR_CTRL & BIT_SGPIO_RXTMR_CEN) {
}
/* Set RX Timer Trigger Mode */
TempVal = SGPIOx->SGPIO_RXTMR_CTRL;
TempVal &= (~BIT_SGPIO_RXTMREDGE_SEL);
TempVal |= SGPIO_RXInitStruct->RxTimerEdge_Sel;
SGPIOx->SGPIO_RXTMR_CTRL = TempVal;
SGPIOx->SGPIO_RXPRVAL = SGPIO_RXInitStruct->RxPRVal;
SGPIOx->SGPIO_RXPRTC = SGPIO_RXInitStruct->RxPRTC;
SGPIOx->SGPIO_RXTC = SGPIO_RXInitStruct->RxPRTC;
/* Set RX Data Source */
TempVal = SGPIOx->SGPIO_DATA_CTRL;
TempVal &= (~BIT_SGPIO_RXDATASRC_SEL);
TempVal |= SGPIO_RXInitStruct->RxDataSrc_Sel;
SGPIOx->SGPIO_DATA_CTRL = TempVal;
/* Set RX Data Direction */
TempVal = SGPIOx->SGPIO_DATA_CTRL;
TempVal &= (~BIT_SGPIO_RXDATA_DIR);
TempVal |= SGPIO_RXInitStruct->RxData_Dir;
SGPIOx->SGPIO_DATA_CTRL = TempVal;
SGPIOx->SGPIO_RXPOSR = SGPIO_RXInitStruct->RxPosTC;
/* Unmask all interrupt */
SGPIOx->SGPIO_IMR &= (~BIT_SGPIO_INTR_MASK);
}
/**
* @brief Set the Multiple Timer control when RXMR0 matches RXTC.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_RXMR0Val: specifies the value of SGPIO RX Match 0 Register.
* @param SGPIO_RXMR0MULCtl: specifies the control of MULTC when RXMR0 matches RXTC.
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_RX_MR0MULRST_EN: Reset MULTC .
* @arg BIT_SGPIO_RX_MR0MULSTOP_EN: MULTC will stop and MULTMR_CEN will be cleared.
* @retval None
*/
void SGPIO_RXMR0MULConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR0Val, u32 SGPIO_RXMR0MULCtl)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_RXMR0Val <= 0xffff);
SGPIOx->SGPIO_RXMR0 = SGPIO_RXMR0Val;
TempVal = SGPIOx->SGPIO_RXMC_CTRL;
TempVal &= (~BIT_SGPIO_RX_MR0MUL_CTRL);
TempVal |= SGPIO_RXMR0MULCtl;
SGPIOx->SGPIO_RXMC_CTRL = TempVal;
}
/**
* @brief Get RX Data from rx data duplicate register.
* @param SGPIOx: selected SGPIO peripheral.
* @retval RX Data in duplicate register
*/
u32 SGPIO_GetRXData(SGPIO_TypeDef *SGPIOx)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
return SGPIOx->SGPIO_RXDATA_DP;
}
/**
* @brief Set the reload value of RXPOSTC and control of RXTC.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_PosRstVal: specifies the reload value of RXPOSTC.
* @param SGPIO_RXPOSCtl: specifies the control of RXTC when RXPOSTC reaches 0.
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_RX_POSRST_EN: Reset RXTC .
* @arg BIT_SGPIO_RX_POSSTOP_EN: RXTC will stop and MULTMR_CEN will be cleared.
* @retval None
*/
void SGPIO_RXPosConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_PosRstVal, u32 SGPIO_RXPOSCtl)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_PosRstVal <= 0x1f);
TempVal = SGPIOx->SGPIO_RXMC_CTRL;
TempVal &= (~BIT_SGPIO_RX_POS_CTRL);
TempVal |= SGPIO_RXPOSCtl;
SGPIOx->SGPIO_RXMC_CTRL = TempVal;
TempVal = SGPIOx->SGPIO_RXPOSR;
TempVal &= (~BIT_SGPIO_RXPOSRST);
TempVal |= (SGPIO_PosRstVal << 8);
SGPIOx->SGPIO_RXPOSR = TempVal;
}
/**
* @brief Set the SGPIO RXMR0.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_RXMR0Val: specifies the value of SGPIO RX Match 0 Register.
* @param SGPIO_RXMR0Ctl: specifies the control of RXTC when RXMR0 matches RXTC.
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_RX_MR0_IE: Generate an interrupt .
* @arg BIT_SGPIO_RX_MR0RST_EN: Reset RXTC .
* @arg BIT_SGPIO_RX_MR0STOP_EN: RXTC will stop and RXTMR_CEN will be cleared.
* @arg BIT_SGPIO_RX_MR0SCLK_EN: Generate a shift clock for RX Data Register.
* @retval None
*/
void SGPIO_RXMR0Config(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR0Val, u32 SGPIO_RXMR0Ctl)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_RXMR0Val <= 0xffff);
SGPIOx->SGPIO_RXMR0 = SGPIO_RXMR0Val;
TempVal = SGPIOx->SGPIO_RXMC_CTRL;
TempVal &= (~BIT_SGPIO_RX_MR0_CTRL);
TempVal |= SGPIO_RXMR0Ctl;
SGPIOx->SGPIO_RXMC_CTRL = TempVal;
}
/**
* @brief Set the SGPIO RXMR1.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_RXMR1Val: specifies the value of SGPIO RX Match 1 Register.
* @param SGPIO_RXMR1Ctl: specifies the control of RXTC when RXMR1 matches RXTC.
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_RX_MR1_IE: Generate an interrupt .
* @arg BIT_SGPIO_RX_MR1RST_EN: Reset RXTC .
* @arg BIT_SGPIO_RX_MR1STOP_EN: RXTC will stop and RXTMR_CEN will be cleared.
* @arg BIT_SGPIO_RX_MR1SCLK_EN: Generate a shift clock for RX Data Register.
* @retval None
*/
void SGPIO_RXMR1Config(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR1Val, u32 SGPIO_RXMR1Ctl)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_RXMR1Val <= 0xffff);
SGPIOx->SGPIO_RXMR1 = SGPIO_RXMR1Val;
TempVal = SGPIOx->SGPIO_RXMC_CTRL;
TempVal &= (~BIT_SGPIO_RX_MR1_CTRL);
TempVal |= SGPIO_RXMR1Ctl;
SGPIOx->SGPIO_RXMC_CTRL = TempVal;
}
/**
* @brief Set the SGPIO RXMR2.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_RXMR2Val: specifies the value of SGPIO RX Match 2 Register.
* @param SGPIO_RXMR2Ctl: specifies the control of RXTC when RXMR0 matches RXTC.
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_RX_MR2_IE: Generate an interrupt .
* @arg BIT_SGPIO_RX_MR2RST_EN: Reset RXTC .
* @arg BIT_SGPIO_RX_MR2STOP_EN: RXTC will stop and RXTMR_CEN will be cleared.
* @arg BIT_SGPIO_RX_MR2SCLK_EN: Generate a shift clock for RX Data Register.
* @retval None
*/
void SGPIO_RXMR2Config(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR2Val, u32 SGPIO_RXMR2Ctl)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_RXMR2Val <= 0xffff);
SGPIOx->SGPIO_RXMR2 = SGPIO_RXMR2Val;
TempVal = SGPIOx->SGPIO_RXMC_CTRL;
TempVal &= (~BIT_SGPIO_RX_MR2_CTRL);
TempVal |= SGPIO_RXMR2Ctl;
SGPIOx->SGPIO_RXMC_CTRL = TempVal;
}
/**
* @brief Set the SGPIO RX Match Register Output control.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_RXMR0TXCtl: specifies the output control when RXMR0 matches RXTC.
* This parameter can be a value of @ref RXMR0_Output_Control_Options
* @param SGPIO_RXMR1TXCtl: specifies the output control when RXMR1 matches RXTC.
* This parameter can be a value of @ref RXMR1_Output_Control_Options
* @param SGPIO_RXMR2TXCtl: specifies the output control when RXMR2 matches RXTC.
* This parameter can be a value of @ref RXMR2_Output_Control_Options
* @retval None
*/
void SGPIO_RXMRxTXConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_RXMR0TXCtl, u32 SGPIO_RXMR1TXCtl, u32 SGPIO_RXMR2TXCtl)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(IS_RXMR0_OUTCTRL_OPTION(SGPIO_RXMR0TXCtl));
assert_param(IS_RXMR1_OUTCTRL_OPTION(SGPIO_RXMR1TXCtl));
assert_param(IS_RXMR2_OUTCTRL_OPTION(SGPIO_RXMR2TXCtl));
TempVal = SGPIOx->SGPIO_MULEMR;
TempVal &= (~BIT_SGPIO_RXEMC_CTRL);
TempVal |= (SGPIO_RXMR0TXCtl | SGPIO_RXMR1TXCtl | SGPIO_RXMR2TXCtl);
SGPIOx->SGPIO_MULEMR = TempVal;
}
/**
* @brief Reset the SGPIO RX Timer and RX Prescale Timer.
* @param SGPIOx: selected SGPIO peripheral.
* @retval None
*/
void SGPIO_RXTmr_Reset(SGPIO_TypeDef *SGPIOx)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
/* Reset the SGPIO RX Timer and RX Prescale Timer*/
SGPIOx->SGPIO_RXTMR_CTRL |= BIT_SGPIO_RXTMR_CRST;
}
/**
* @brief Enables or disables the SGPIO RX Timer and RX Prescale Timer.
* @param SGPIOx: selected SGPIO peripheral.
* @param NewState: new state of the RX Timer and RX Prescale Timer.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SGPIO_RXTmr_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
if (NewState != DISABLE) {
/* Enable the SGPIO RX Timer and RX Prescale Timer*/
SGPIOx->SGPIO_RXTMR_CTRL |= BIT_SGPIO_RXTMR_CEN;
/*Avoid clock domain crossing issue*/
while(!(SGPIOx->SGPIO_RXTMR_CTRL & BIT_SGPIO_RXTMR_CEN)) {
}
} else {
/* Disable the SGPIO RX Timer and RX Prescale Timer*/
SGPIOx->SGPIO_RXTMR_CTRL &= (~BIT_SGPIO_RXTMR_CEN);
/*Avoid clock domain crossing issue*/
while(SGPIOx->SGPIO_RXTMR_CTRL & BIT_SGPIO_RXTMR_CEN) {
}
}
}
/**
* @brief Set RX Pattern Match Mode.
* @param SGPIOx: selected SGPIO peripheral.
* @param RXDATADP: the specific value of RXDATA match pattern should be set.
* @param RXDATAMask: mask for pattern match function.
* @param NewState: new state of the patten match function.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SGPIO_RXPatternMatchConfig(SGPIO_TypeDef *SGPIOx, u32 RXDATADP, u32 RXDATAMask, u8 NewState)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
if (NewState != DISABLE) {
SGPIOx->SGPIO_RXDATAMASK = RXDATAMask & BIT_SGPIO_RXDATAMASK;
SGPIOx->SGPIO_RXDATA_DP = RXDATADP;
/* Enable the patten match function*/
SGPIOx->SGPIO_DATA_CTRL |= BIT_SGPIO_PATTERN_MATCH_MODE;
} else {
/* Disable the patten match function*/
SGPIOx->SGPIO_DATA_CTRL &= (~BIT_SGPIO_PATTERN_MATCH_MODE);
}
}
/**
* @brief Fills each SGPIO_MULInitStruct member with its default value.
* @param SGPIO_MULInitStruct: pointer to an SGPIO_MULInitTypeDef structure which will be initialized.
* @retval None
*/
void SGPIO_MUL_StructInit(SGPIO_MULInitTypeDef* SGPIO_MULInitStruct)
{
/* Load HAL initial data structure default value */
SGPIO_MULInitStruct->BiOut = MUL_DISABLE_BIOUT;
SGPIO_MULInitStruct->MulMode_Sel = MUL_TIMER_MODE;
SGPIO_MULInitStruct->MulPRVal = (2-1);
SGPIO_MULInitStruct->MulPRTC = 0x0;
SGPIO_MULInitStruct->MulTC = 0x0;
SGPIO_MULInitStruct->MulData_Dir = MUL_DATA_DIR_LSB;
SGPIO_MULInitStruct->MulPosTC = (8-1);
SGPIO_MULInitStruct->MulPosRST = (8-1);
}
/**
* @brief Initializes the SGPIOx peripheral according to the specified
* parameters in the SGPIO_MULInitTypeDef.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_MULInitStruct: pointer to a SGPIO_MULInitTypeDef structure that contains
* the configuration information for the specified SGPIO peripheral.
* @retval None
*/
void SGPIO_MUL_Init(SGPIO_TypeDef *SGPIOx, SGPIO_MULInitTypeDef* SGPIO_MULInitStruct)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(IS_MUL_BIOUT_MODE(SGPIO_MULInitStruct->BiOut));
assert_param(IS_MUL_MODE(SGPIO_MULInitStruct->MulMode_Sel));
assert_param(SGPIO_MULInitStruct->MulPRVal <= 0xffff);
assert_param(SGPIO_MULInitStruct->MulPRTC <= 0xffff);
assert_param(SGPIO_MULInitStruct->MulTC <= 0xffff);
assert_param(SGPIO_MULInitStruct->MulPosTC <= 0x1f);
assert_param(SGPIO_MULInitStruct->MulPosRST <= 0x1f);
assert_param(IS_MUL_DATA_DIR(SGPIO_MULInitStruct->MulData_Dir));
/* Mask all interrupt */
SGPIOx->SGPIO_IMR |= BIT_SGPIO_INTR_MASK;
/* Disable the SGPIO Multiple Timer and Multiple Prescale Timer*/
SGPIOx->SGPIO_MULTMR_CTRL &= (~BIT_SGPIO_MULTMR_CEN);
/*Avoid clock domain crossing issue*/
while(SGPIOx->SGPIO_MULTMR_CTRL & BIT_SGPIO_MULTMR_CEN) {
}
/* Set Multiple Timer TX pin */
TempVal = SGPIOx->SGPIO_MULEMR;
TempVal &= (~BIT_SGPIO_BIOUT);
TempVal |= SGPIO_MULInitStruct->BiOut;
SGPIOx->SGPIO_MULEMR = TempVal;
/* Set Multiple Timer Work Mode */
TempVal = SGPIOx->SGPIO_MULTMR_CTRL;
TempVal &= (~BIT_SGPIO_MULMODE_SEL);
TempVal |= SGPIO_MULInitStruct->MulMode_Sel;
SGPIOx->SGPIO_MULTMR_CTRL = TempVal;
SGPIOx->SGPIO_MULPRVAL = SGPIO_MULInitStruct->MulPRVal;
SGPIOx->SGPIO_MULPRTC = SGPIO_MULInitStruct->MulPRTC;
SGPIOx->SGPIO_MULTC = SGPIO_MULInitStruct->MulPRTC;
/* Set MUL Data Direction */
TempVal = SGPIOx->SGPIO_DATA_CTRL;
TempVal &= (~BIT_SGPIO_TXDATA_DIR);
TempVal |= SGPIO_MULInitStruct->MulData_Dir;
SGPIOx->SGPIO_DATA_CTRL = TempVal;
SGPIOx->SGPIO_MULPOSR = (SGPIO_MULInitStruct->MulPosRST << 8) |SGPIO_MULInitStruct->MulPosTC;
/* Unmask all interrupt */
SGPIOx->SGPIO_IMR &= (~BIT_SGPIO_INTR_MASK);
}
/**
* @brief Set the SGPIO MULMR0.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_MULMR0Val0: specifies the value of MULMR0 when TXDATA[0] is 0.
* @param SGPIO_MULMR0Val1: specifies the value of MULMR0 when TXDATA[0] is 1.
* @param SGPIO_MULMR0Ctl: specifies the control of MULTC when MULMR0 matches MULTC.
* This parameter can be one or combinations of the following values:
* @arg NULL: No control.
* @arg BIT_SGPIO_MUL_MR0_IE: Generate an interrupt.
* @arg BIT_SGPIO_MUL_MR0RST_EN: Reset MULTC.
* @arg BIT_SGPIO_MUL_MR0STOP_EN: MULTC will stop and MULTMR_CEN will be cleared.
* @arg BIT_SGPIO_MUL_MR0SCLK_EN: Generate a shift clock for Multiple Data Register.
* @retval None
*/
void SGPIO_MULMR0MulConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0Val0, u32 SGPIO_MULMR0Val1, u32 SGPIO_MULMR0Ctl)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_MULMR0Val0 <= 0xffff);
assert_param(SGPIO_MULMR0Val1 <= 0xffff);
TempVal = SGPIOx->SGPIO_MULMR01GP0;
TempVal &= (~BIT_SGPIO_MULMR0_GP0);
TempVal |= SGPIO_MULMR0Val0;
SGPIOx->SGPIO_MULMR01GP0 = TempVal;
TempVal = SGPIOx->SGPIO_MULMR01GP1;
TempVal &= (~BIT_SGPIO_MULMR0_GP1);
TempVal |= SGPIO_MULMR0Val1;
SGPIOx->SGPIO_MULMR01GP1 = TempVal;
TempVal = SGPIOx->SGPIO_MULMC_CTRL;
TempVal &= (~BIT_SGPIO_MUL_MR0_CTRL);
TempVal |= SGPIO_MULMR0Ctl;
SGPIOx->SGPIO_MULMC_CTRL = TempVal;
}
/**
* @brief Set the SGPIO MULMR0 and control of RXTC.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_MULMR0Val0: specifies the value of MULMR0 when TXDATA[0] is 0.
* @param SGPIO_MULMR0Val1: specifies the value of MULMR0 when TXDATA[0] is 1.
* @param SGPIO_MULMR0RXCtl: specifies the control of RXTC when MULMR0 matches MULTC.
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_MUL_MR0RXRST_EN: Reset RXTC .
* @arg BIT_SGPIO_MUL_MR0RXSTOP_EN: RXTC will stop and RXTMR_CEN will be cleared.
* @retval None
*/
void SGPIO_MULMR0RXConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0Val0, u32 SGPIO_MULMR0Val1, u32 SGPIO_MULMR0RXCtl)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_MULMR0Val0 <= 0xffff);
assert_param(SGPIO_MULMR0Val1 <= 0xffff);
TempVal = SGPIOx->SGPIO_MULMR01GP0;
TempVal &= (~BIT_SGPIO_MULMR0_GP0);
TempVal |= SGPIO_MULMR0Val0;
SGPIOx->SGPIO_MULMR01GP0 = TempVal;
TempVal = SGPIOx->SGPIO_MULMR01GP1;
TempVal &= (~BIT_SGPIO_MULMR0_GP1);
TempVal |= SGPIO_MULMR0Val1;
SGPIOx->SGPIO_MULMR01GP1 = TempVal;
TempVal = SGPIOx->SGPIO_MULMC_CTRL;
TempVal &= (~BIT_SGPIO_MUL_MR0RX_CTRL);
TempVal |= SGPIO_MULMR0RXCtl;
SGPIOx->SGPIO_MULMC_CTRL = TempVal;
}
/**
* @brief Set the SGPIO MULMRx register for group 0.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_MULMR0GP0: specifies the value of MULMR0 when TXDATA[0] is 0.
* @param SGPIO_MULMR1GP0: specifies the value of MULMR1 when TXDATA[0] is 0.
* @param SGPIO_MULMR2GP0: specifies the value of MULMR2 when TXDATA[0] is 0.
* @param SGPIO_MULMR3GP0: specifies the value of MULMR3 when TXDATA[0] is 0.
* @retval None
*/
void SGPIO_MULMRxGP0ValConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0GP0, u32 SGPIO_MULMR1GP0, u32 SGPIO_MULMR2GP0, u32 SGPIO_MULMR3GP0)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_MULMR0GP0 <= 0xffff);
assert_param(SGPIO_MULMR1GP0 <= 0xffff);
assert_param(SGPIO_MULMR2GP0 <= 0xffff);
assert_param(SGPIO_MULMR3GP0 <= 0xffff);
SGPIOx->SGPIO_MULMR01GP0 = (SGPIO_MULMR1GP0 << 16) | SGPIO_MULMR0GP0;
SGPIOx->SGPIO_MULMR23GP0 = (SGPIO_MULMR3GP0 << 16) | SGPIO_MULMR2GP0;
}
/**
* @brief Set the SGPIO MULMRx register for group 1.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_MULMR0GP1: specifies the value of MULMR0 when TXDATA[0] is 1.
* @param SGPIO_MULMR1GP1: specifies the value of MULMR1 when TXDATA[0] is 1.
* @param SGPIO_MULMR2GP1: specifies the value of MULMR2 when TXDATA[0] is 1.
* @param SGPIO_MULMR3GP1: specifies the value of MULMR3 when TXDATA[0] is 1.
* @retval None
*/
void SGPIO_MULMRxGP1ValConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0GP1, u32 SGPIO_MULMR1GP1, u32 SGPIO_MULMR2GP1, u32 SGPIO_MULMR3GP1)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_MULMR0GP1 <= 0xffff);
assert_param(SGPIO_MULMR1GP1 <= 0xffff);
assert_param(SGPIO_MULMR2GP1 <= 0xffff);
assert_param(SGPIO_MULMR3GP1 <= 0xffff);
SGPIOx->SGPIO_MULMR01GP1 = (SGPIO_MULMR1GP1 << 16) | SGPIO_MULMR0GP1;
SGPIOx->SGPIO_MULMR23GP1 = (SGPIO_MULMR3GP1 << 16) | SGPIO_MULMR2GP1;
}
/**
* @brief Set the SGPIO MULMRx control.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_MULMR0TXCtl: specifies the control of MULTC when MULMR0 matches MULTC.
* This parameter can be one or combinations of the following values:
* @arg NULL: No control.
* @arg BIT_SGPIO_MUL_MR0_IE: Generate an interrupt.
* @arg BIT_SGPIO_MUL_MR0RST_EN: Reset MULTC.
* @arg BIT_SGPIO_MUL_MR0STOP_EN: MULTC will stop and MULTMR_CEN will be cleared.
* @arg BIT_SGPIO_MUL_MR0SCLK_EN: Generate a shift clock for Multiple Data Register.
* @param SGPIO_MULMR1TXCtl: specifies the output control when MULMR1 matches MULTC.
* This parameter can be a value of @ref MULMR1_Output_Control_Option
* @param SGPIO_MULMR2TXCtl: specifies the output control when MULMR2 matches MULTC.
* This parameter can be a value of @ref MULMR2_Output_Control_Option
* @param SGPIO_MULMR3TXCtl: specifies the output control when MULMR3 matches MULTC.
* This parameter can be a value of @ref MULMR3_Output_Control_Option
* @retval None
*/
void SGPIO_MULMRxTXCtlConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMR0TXCtl, u32 SGPIO_MULMR1TXCtl, u32 SGPIO_MULMR2TXCtl, u32 SGPIO_MULMR3TXCtl)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(IS_MULMR1_OUTCTRL_OPTION(SGPIO_MULMR1TXCtl));
assert_param(IS_MULMR2_OUTCTRL_OPTION(SGPIO_MULMR2TXCtl));
assert_param(IS_MULMR3_OUTCTRL_OPTION(SGPIO_MULMR3TXCtl));
/*set MULMR0 control*/
TempVal = SGPIOx->SGPIO_MULMC_CTRL;
TempVal &= (~BIT_SGPIO_MUL_MR0_CTRL);
TempVal |= SGPIO_MULMR0TXCtl;
SGPIOx->SGPIO_MULMC_CTRL = TempVal;
/*set MULMRx output control*/
TempVal = SGPIOx->SGPIO_MULEMR;
TempVal &= (~(BIT_SGPIO_MULEMC1 | BIT_SGPIO_MULEMC2 | BIT_SGPIO_MULEMC3));
TempVal |= (SGPIO_MULMR1TXCtl | SGPIO_MULMR2TXCtl | SGPIO_MULMR3TXCtl);
SGPIOx->SGPIO_MULEMR = TempVal;
}
/**
* @brief Set TX Data to multiple data register.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_MulDataVal: specifies the value of SGPIO_MULDATA
* @param SGPIO_MulDataDPVal: specifies the reload value of SGPIO_MULDATA
* @retval None
*/
void SGPIO_SetTXData(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MulDataVal, u32 SGPIO_MulDataDPVal)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_MulDataVal <= 0xffffffff);
assert_param(SGPIO_MulDataDPVal <= 0xffffffff);
SGPIOx->SGPIO_MULDATA = SGPIO_MulDataVal;
SGPIOx->SGPIO_MULDATA_DP = SGPIO_MulDataDPVal;
}
/**
* @brief Config output level.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_OutputCtl: specifies the value of SGPIO_OUTPUT
* This parameter can be one of the following values:
* @arg BIT_SGPIO_OUTPUT_LOW: output low.
* @arg BIT_SGPIO_OUTPUT_HIGH: output high.
* @retval None
*/
void SGPIO_OutputConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_OutputCtl)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
SGPIOx->SGPIO_OUTPUT = SGPIO_OutputCtl;
}
/**
* @brief Reset the SGPIO Multiple Timer and Multiple Prescale Timer.
* @param SGPIOx: selected SGPIO peripheral.
* @retval None
*/
void SGPIO_MULTmr_Reset(SGPIO_TypeDef *SGPIOx)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
/* Reset the SGPIO Multiple Timer and Multiple Prescale Timer*/
SGPIOx->SGPIO_MULTMR_CTRL |= BIT_SGPIO_MULTMR_CRST;
}
/**
* @brief Enables or disables the SGPIO Multiple Timer and Multiple Prescale Timer.
* @param SGPIOx: selected SGPIO peripheral.
* @param NewState: new state of the Multiple Timer and Multiple Prescale Timer.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SGPIO_MULTmr_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
if (NewState != DISABLE) {
/* Enable the SGPIO Multiple Timer and Multiple Prescale Timer*/
SGPIOx->SGPIO_MULTMR_CTRL |= BIT_SGPIO_MULTMR_CEN;
/*Avoid clock domain crossing issue*/
while(!(SGPIOx->SGPIO_MULTMR_CTRL & BIT_SGPIO_MULTMR_CEN)) {
}
} else {
/* Disable the SGPIO Multiple Timer and Multiple Prescale Timer*/
SGPIOx->SGPIO_MULTMR_CTRL &= (~BIT_SGPIO_MULTMR_CEN);
/*Avoid clock domain crossing issue*/
while(SGPIOx->SGPIO_MULTMR_CTRL & BIT_SGPIO_MULTMR_CEN) {
}
}
}
/**
* @brief Set the SGPIO MULMR0.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_MULMCNTVal: specifies the value of MUL_MCNT.
* @param SGPIO_MULMR0Ctl: specifies the control of MULTC when MUL_MCNT reaches zero.
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_MUL_MCNT_IE: Generate an interrupt .
* @arg BIT_SGPIO_MUL_MCNTRST_EN: Reset MULTC .
* @arg BIT_SGPIO_MUL_MCNTSTOP_EN: MULTC will stop and MULTMR_CEN will be cleared.
* @retval None
*/
void SGPIO_MULMCNTConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULMCNTVal, u32 SGPIO_MULMCNTCtl)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(SGPIO_MULMCNTVal <= 0xff);
SGPIOx->SGPIO_MUL_MCNT = SGPIO_MULMCNTVal;
TempVal = SGPIOx->SGPIO_MULMC_CTRL;
TempVal &= (~BIT_SGPIO_MUL_MCNT_CTRL);
TempVal |= SGPIO_MULMCNTCtl;
SGPIOx->SGPIO_MULMC_CTRL = TempVal;
}
/**
* @brief Enables or disables the SGPIO MCNT function.
* @param SGPIOx: selected SGPIO peripheral.
* @param NewState: new state of the MCNT function.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SGPIO_MULMCNT_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
if (NewState != DISABLE) {
/* Enable the SGPIO MCNT function*/
SGPIOx->SGPIO_MULMC_CTRL |= BIT_SGPIO_MUL_MR0MCNT_EN;
} else {
/* Disable the SGPIO MCNT function*/
SGPIOx->SGPIO_MULMC_CTRL &= (~BIT_SGPIO_MUL_MR0MCNT_EN);
}
}
/**
* @brief Fills each SGPIO_CAPInitStruct member with its default value.
* @param SGPIO_CAPInitStruct: pointer to an SGPIO_CAPInitTypeDef structure which will be initialized.
* @retval None
*/
void SGPIO_CAP_StructInit(SGPIO_CAPInitTypeDef* SGPIO_CAPInitStruct)
{
/* Load HAL initial data structure default value */
SGPIO_CAPInitStruct->CapSrc_Sel = CAPSRC_RX_INPUT;
SGPIO_CAPInitStruct->CapEdge_Sel = CAP_RX_FALLING_EDGE;
SGPIO_CAPInitStruct->Cap_ValidEn = CAP_RX_VALID_ENABLE;
SGPIO_CAPInitStruct->Cap_RxTCStop_Ctrl = CAP_RX_STOP_ENABLE;
SGPIO_CAPInitStruct->Cap_RxTCRst_Ctrl = CAP_RX_RESET_ENABLE;
SGPIO_CAPInitStruct->CapI_En = CAP_INTR_ENABLE;
}
/**
* @brief Initializes the SGPIOx peripheral according to the specified
* parameters in the SGPIO_CAPInitTypeDef.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_CAPInitStruct: pointer to a SGPIO_CAPInitTypeDef structure that contains
* the configuration information for the specified SGPIO peripheral.
* @retval None
*/
void SGPIO_CAP_Init(SGPIO_TypeDef *SGPIOx, SGPIO_CAPInitTypeDef* SGPIO_CAPInitStruct)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(IS_CAPSRC_SEL_OPTION(SGPIO_CAPInitStruct->CapSrc_Sel));
assert_param(IS_CAPEDGE_SEL_OPTION(SGPIO_CAPInitStruct->CapEdge_Sel));
assert_param(IS_CAP_RX_VALID_OPTION(SGPIO_CAPInitStruct->Cap_ValidEn));
assert_param(IS_CAP_RX_STOP_OPTION(SGPIO_CAPInitStruct->Cap_RxTCStop_Ctrl));
assert_param(IS_CAP_RX_RESET_OPTION(SGPIO_CAPInitStruct->Cap_RxTCRst_Ctrl));
assert_param(IS_CAP_INTR_OPTION(SGPIO_CAPInitStruct->CapI_En));
TempVal = SGPIOx->SGPIO_CAP_CTRL;
TempVal &= (~(BIT_SGPIO_CAPVALID_EN | BIT_SGPIO_CAP_RXTCSTOP_EN | BIT_SGPIO_CAP_RXTCRST_EN |\
BIT_SGPIO_CAP_RXEDGE_SEL | BIT_SGPIO_CAPSRC_SEL | BIT_SGPIO_CAP_IE));
if (CAPSRC_RX_INPUT == SGPIO_CAPInitStruct->CapSrc_Sel) {
TempVal |= (SGPIO_CAPInitStruct->CapSrc_Sel | SGPIO_CAPInitStruct->CapEdge_Sel);
} else {
TempVal |= SGPIO_CAPInitStruct->CapSrc_Sel;
SGPIOx->SGPIO_MULMC_CTRL |= BIT_SGPIO_MUL_MR0CAPSRC_EN;
}
TempVal |= (SGPIO_CAPInitStruct->Cap_ValidEn | SGPIO_CAPInitStruct->Cap_RxTCStop_Ctrl |\
SGPIO_CAPInitStruct->Cap_RxTCRst_Ctrl | SGPIO_CAPInitStruct->CapI_En);
SGPIOx->SGPIO_CAP_CTRL = TempVal;
}
/**
* @brief Get SGPIO RX timer counter capture value.
* @param SGPIOx: selected SGPIO peripheral.
* @retval RX timer counter capture Value
*/
u32 SGPIO_GetCapVal(SGPIO_TypeDef *SGPIOx)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
return SGPIOx->SGPIO_CAPR;
}
/**
* @brief set SGPIO Capture compare function.
* @param SGPIOx: selected SGPIO peripheral.
* @param CapComp_Val: compare this value with CAPR.
* @param CapComp_Mode: RXDATA receives value set when CAPR is bigger than CapComp_Val.
* This parameter can be a value of @ref Cap_CmpVal_Sel_definitions.
* @retval None
*/
void SGPIO_Cap_CompConfig(SGPIO_TypeDef *SGPIOx, u32 CapComp_Val, u32 CapComp_Mode)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
assert_param(CapComp_Val <= 0xffff);
assert_param(IS_CAP_CMPVAL_SEL_OPTION(CapComp_Mode));
TempVal = SGPIOx->SGPIO_CAP_CTRL;
TempVal &= (~(BIT_SGPIO_CAP_CMPVAL | BIT_SGPIO_CAP_CMPVAL_SEL));
TempVal |= ((CapComp_Val << 16) | CapComp_Mode);
SGPIOx->SGPIO_CAP_CTRL = TempVal;
}
/**
* @brief Enables or disables the SGPIO Capture Function.
* @param SGPIOx: selected SGPIO peripheral.
* @param NewState: new state of the Capture function.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SGPIO_Cap_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
if (NewState != DISABLE) {
/* Enable the CAPR load with RXTC when there is an event*/
SGPIOx->SGPIO_CAP_CTRL |= BIT_SGPIO_CAP_EN;
} else {
/* Disable the CAPR load with RXTC when there is an event*/
SGPIOx->SGPIO_CAP_CTRL &= (~BIT_SGPIO_CAP_EN);
}
}
/**
* @brief Set the SGPIO Interrupt Enable.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_IT: specifies the SGPIO interrupt sources to be enabled or disabled.
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_PATTERN_MATCH_IE: Matching pattern Interrupt Enable.
* @arg BIT_SGPIO_MULLOAD_IE: Loading multiple data Interrupt Enable.
* @arg BIT_SGPIO_RXLOAD_IE: Loading RX data Interrupt Enable.
* @arg BIT_SGPIO_MULSFT_IE: Multiple shift clock Interrupt Enable.
* @arg BIT_SGPIO_RXSFT_IE: RX shift clock Interrupt Enable.
* @param NewState: specifies the state of the interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SGPIO_INTConfig(SGPIO_TypeDef *SGPIOx, u32 SGPIO_IT, u32 NewState)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
TempVal = SGPIOx->SGPIO_DATA_CTRL;
if (NewState == ENABLE) {
TempVal |= SGPIO_IT;
} else {
TempVal &= (~SGPIO_IT);
}
SGPIOx->SGPIO_DATA_CTRL = TempVal;
}
/**
* @brief Set the SGPIO Interrupt Mask.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_IT: specifies the SGPIO Interrupt sources to be masked or not.
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_MULMCNT_IM: MUL_MCNT counts to zero Interrupt Mask.
* @arg BIT_SGPIO_PATTERN_MATCH_IM: Matching pattern Interrupt Mask.
* @arg BIT_SGPIO_MULLOAD_IM: Loading multiple data Interrupt Mask.
* @arg BIT_SGPIO_RXLOAD_IM: Loading RX data Interrupt Mask.
* @arg BIT_SGPIO_MULSFT_IM: Multiple shift clock Interrupt Mask.
* @arg BIT_SGPIO_RXSFT_IM: RX shift clock Interrupt Mask.
* @arg BIT_SGPIO_CAPI_IM: Capture load event Interrupt Mask.
* @arg BIT_SGPIO_MUL_MR0I_IM: Multiple MR0 match Interrupt Mask.
* @arg BIT_SGPIO_RX_MR2I_IM: RX MR2 match Interrupt Mask.
* @arg BIT_SGPIO_RX_MR1I_IM: RX MR1 match Interrupt Mask.
* @arg BIT_SGPIO_RX_MR0I_IM: RX MR0 match Interrupt Mask.
* @param NewState: specifies the mask state of the interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SGPIO_INTMask(SGPIO_TypeDef *SGPIOx, u32 SGPIO_IT, u32 NewState)
{
u32 TempVal;
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
TempVal = SGPIOx->SGPIO_IMR;
if (NewState == ENABLE) {
TempVal |= SGPIO_IT;
} else {
TempVal &= (~SGPIO_IT);
}
SGPIOx->SGPIO_IMR = TempVal;
}
/**
* @brief Get SGPIO Raw Interrupt Status.
* @param SGPIOx: selected SGPIO peripheral.
* @retval SGPIO raw interrupt status
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_MULMCNT_IS: MUL_MCNT counts to zero Interrupt Raw Status.
* @arg BIT_SGPIO_PATTERN_MATCH_IS: Matching pattern Interrupt Raw Status.
* @arg BIT_SGPIO_MULLOAD_IS: Loading multiple data Interrupt Raw Status.
* @arg BIT_SGPIO_RXLOAD_IS: Loading RX data Interrupt Raw Status.
* @arg BIT_SGPIO_MULSFT_IS: Multiple shift clock Interrupt Raw Status.
* @arg BIT_SGPIO_RXSFT_IS: RX shift clock Interrupt Raw Status.
* @arg BIT_SGPIO_CAPI_IS: Capture load event Interrupt Raw Status.
* @arg BIT_SGPIO_MUL_MR0I_IS: Multiple MR0 match Interrupt Raw Status.
* @arg BIT_SGPIO_RX_MR2I_IS: RX MR2 match Interrupt Raw Status.
* @arg BIT_SGPIO_RX_MR1I_IS: RX MR1 match Interrupt Raw Status.
* @arg BIT_SGPIO_RX_MR0I_IS: RX MR0 match Interrupt Raw Status.
*/
u32 SGPIO_GetRawINT(SGPIO_TypeDef *SGPIOx)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
return SGPIOx->SGPIO_ISR;
}
/**
* @brief clear SGPIO Interrupt Status.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_IT: SGPIO interrupt status to be cleared
* This parameter can be one or combinations of the following values:
* @arg BIT_SGPIO_MULMCNT_IS: MUL_MCNT counts to zero Interrupt Raw Status.
* @arg BIT_SGPIO_PATTERN_MATCH_IS: Matching pattern Interrupt Raw Status.
* @arg BIT_SGPIO_MULLOAD_IS: Loading multiple data Interrupt Raw Status.
* @arg BIT_SGPIO_RXLOAD_IS: Loading RX data Interrupt Raw Status.
* @arg BIT_SGPIO_MULSFT_IS: Multiple shift clock Interrupt Raw Status.
* @arg BIT_SGPIO_RXSFT_IS: RX shift clock Interrupt Raw Status.
* @arg BIT_SGPIO_CAPI_IS: Capture load event Interrupt Raw Status.
* @arg BIT_SGPIO_MUL_MR0I_IS: Multiple MR0 match Interrupt Raw Status.
* @arg BIT_SGPIO_RX_MR2I_IS: RX MR2 match Interrupt Raw Status.
* @arg BIT_SGPIO_RX_MR1I_IS: RX MR1 match Interrupt Raw Status.
* @arg BIT_SGPIO_RX_MR0I_IS: RX MR0 match Interrupt Raw Status.
*/
void SGPIO_ClearRawINT(SGPIO_TypeDef *SGPIOx, u32 SGPIO_IT)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
SGPIOx->SGPIO_ISR = SGPIO_IT;
}
/**
* @brief Enables or disables the SGPIO multiple match FIFO mode.
* @param SGPIOx: selected SGPIO peripheral.
* @param NewState: new state of the multiple match FIFO mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SGPIO_MULFIFO_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
if (NewState != DISABLE) {
/* Enable the SGPIO multiple match FIFO mode*/
SGPIOx->SGPIO_MULMC_CTRL |= BIT_SGPIO_MUL_FMODE_EN;
} else {
/* Disable the SGPIO multiple match FIFO mode*/
SGPIOx->SGPIO_MULMC_CTRL &= (~BIT_SGPIO_MUL_FMODE_EN);
}
}
/**
* @brief Set SGPIO multiple match FIFO data.
* @param SGPIOx: selected SGPIO peripheral.
* @param SGPIO_MULFIFOVal: new data to be pushed into multiple match FIFO.
* @retval None
*/
void SGPIO_MULFIFO_Set(SGPIO_TypeDef *SGPIOx, u32 SGPIO_MULFIFOVal)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
SGPIOx->SGPIO_MULFDATA = SGPIO_MULFIFOVal;
}
/**
* @brief Enables or disables the SGPIO multiple match DMA mode.
* @param SGPIOx: selected SGPIO peripheral.
* @param NewState: new state of the multiple match FIFO mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SGPIO_MULDMA_Cmd(SGPIO_TypeDef *SGPIOx, u8 NewState)
{
/* Check the parameters */
assert_param(IS_SGPIO_ALL_PERIPH(SGPIOx));
if (NewState != DISABLE) {
/* Enable the SGPIO multiple match DMA mode*/
SGPIOx->SGPIO_MULMC_CTRL |= BIT_SGPIO_MUL_DMA_EN;
/* Trigger the SGPIO multiple match FIFO load with data for the first time*/
SGPIOx->SGPIO_MULMC_CTRL |= BIT_SGPIO_MUL_DMA_START;
while((1 == SGPIOx->SGPIO_MULMC_CTRL) & BIT_SGPIO_MUL_DMA_START);
} else {
/* Disable the SGPIO multiple match DMA mode*/
SGPIOx->SGPIO_MULMC_CTRL &= (~BIT_SGPIO_MUL_DMA_EN);
}
}
/**
* @brief Init and Enable SGPIO TX GDMA.
* @param SGPIOx: selected SGPIO peripheral.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pTxBuf: Tx Buffer.
* @param TxCount: Tx Count.
* @retval TRUE/FLASE
*/
BOOL SGPIO_MULGDMA_Init(
SGPIO_TypeDef *SGPIOx,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u32 *pTxBuf,
int TxCount
)
{
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);
if (GdmaChnl == 0xFF) {
/* No Available DMA channel */
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_InitStruct->GDMA_DIR = TTFCMemToPeri;
GDMA_InitStruct->GDMA_DstHandshakeInterface = GDMA_HANDSHAKE_INTERFACE_SGPIO_TX;
GDMA_InitStruct->GDMA_DstAddr = (u32)&(SGPIOx->SGPIO_MULFDATA);
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (TransferType|ErrType);
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_DstInc = NoChange;
GDMA_InitStruct->GDMA_SrcInc = IncType;
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_BlockSize = 4 * TxCount;
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
GDMA_InitStruct->GDMA_SrcAddr = (u32)(pTxBuf);
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_sgpio.c
|
C
|
apache-2.0
| 39,030
|
/**
******************************************************************************
* @file rtl8721d_tim.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of the Timer peripheral:
* - Initialization
* - TimeBase configuration and management
* - Intput Capture/Output Compare configuration and management
* - Interrupt and DMA management
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
int TIMx_irq[6] = {
TIMER0_IRQ,
TIMER1_IRQ,
TIMER2_IRQ,
TIMER3_IRQ,
TIMER4_IRQ,
TIMER5_IRQ,
};
RTIM_TypeDef* TIMx[6] = {
TIM0,
TIM1,
TIM2,
TIM3,
TIM4,
TIM5
};
u32 TIM_IT_CCx[18] = {
TIM_IT_CC0,
TIM_IT_CC1,
TIM_IT_CC2,
TIM_IT_CC3,
TIM_IT_CC4,
TIM_IT_CC5,
TIM_IT_CC6,
TIM_IT_CC7,
TIM_IT_CC8,
TIM_IT_CC9,
TIM_IT_CC10,
TIM_IT_CC11,
TIM_IT_CC12,
TIM_IT_CC13,
TIM_IT_CC14,
TIM_IT_CC15,
TIM_IT_CC16,
TIM_IT_CC17
};
int TIMx_irq_LP[6] = {
TIMER0_IRQ_LP,
TIMER1_IRQ_LP,
TIMER2_IRQ_LP,
TIMER3_IRQ_LP,
TIMER4_IRQ_LP,
TIMER5_IRQ_LP,
};
RTIM_TypeDef* TIMx_LP[6] = {
TIMM00,
TIMM01,
TIMM02,
TIMM03,
TIMM04,
TIMM05
};
u32 TIM_IT_CCx_LP[6] = {
TIM_IT_CC0,
TIM_IT_CC1,
TIM_IT_CC2,
TIM_IT_CC3,
TIM_IT_CC4,
TIM_IT_CC5
};
/**
* @brief Enables or Disables the TIMx Update event(UEV).
* @param TIMx: where x can be 0-5 to select the TIM peripheral.
* @param NewState: new state of the TIMx UDIS bit
* This parameter can be:ENABLE or DISABLE
* @note
* - If NewState is ENABLE, Update Disable Bit is set, UEV disable and shadow registers keep their value.
* - If NewState is DISABLE, Update Disable Bit is clear, UEV enable and buffered registers are loaded with
* their preload values when UEV happen.
* @retval None
*/
void RTIM_UpdateDisableConfig(RTIM_TypeDef* TIMx, u32 NewState)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_TIM(TIMx));
if (NewState != DISABLE) {
/* Set the Update Disable Bit */
TIMx->CR |= TIM_CR_UDIS;
} else {
/* Reset the Update Disable Bit */
TIMx->CR &= ~TIM_CR_UDIS;
}
}
/**
* @brief Enables or disables TIMx peripheral Preload register on ARR.
* @param TIMx: where x can be 0-5 to select the TIM peripheral.
* @param NewState: new state of the TIMx peripheral Preload register
* This parameter can be: ENABLE or DISABLE.
* @note
* - DISABLE: TIMx_ARR register is not buffered, and shadow register will update immediately
* - ENABLE: TIMx_ARR register is buffered, and shadow register will update after overflow
* @retval None
*/
void RTIM_ARRPreloadConfig(RTIM_TypeDef* TIMx, u32 NewState)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_TIM(TIMx));
if (NewState != DISABLE) {
/* Set the ARR Preload Bit */
TIMx->CR |= TIM_CR_ARPE;
} else {
/* Reset the ARR Preload Bit */
TIMx->CR &= ~TIM_CR_ARPE;
}
}
/**
* @brief Configures the TIMx Update Request Interrupt source.
* @param TIMx: where x can be 0-5 to select the TIM peripheral.
* @param TIM_UpdateSource: specifies the Update source.
* This parameter can be one of the following values:
* @arg TIM_UpdateSource_Global: Source of update is the counter
* overflow or the setting of UG bit.
* @arg TIM_UpdateSource_Overflow: Source of update is counter overflow.
* @retval None
*/
void RTIM_UpdateRequestConfig(RTIM_TypeDef* TIMx, u32 TIM_UpdateSource)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_TIM(TIMx));
assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
if (TIM_UpdateSource != TIM_UpdateSource_Global) {
/* Set the URS Bit */
TIMx->CR |= TIM_CR_URS;
} else {
/* Reset the URS Bit */
TIMx->CR &= (u32)~TIM_CR_URS;
}
}
/**
* @brief Configures the TIMx Prescaler.
* @param TIMx: where x can be 4 or 5 to select the TIM peripheral.
* @param Prescaler: specifies the Prescaler Register value,which can be a number in 0~0xFF range.
* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
* This parameter can be one of the following values:
* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
* @retval None
*/
void RTIM_PrescalerConfig(RTIM_TypeDef* TIMx, u32 Prescaler, u32 TIM_PSCReloadMode)
{
/* Check the parameters */
assert_param(IS_TIM_40M_TIM(TIMx));
assert_param(IS_TIM_PSC(Prescaler));
assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
/* Set the Prescaler value */
TIMx->PSC = Prescaler;
/* Set or reset the UG Bit */
TIMx->EGR = TIM_PSCReloadMode;
}
/**
* @brief Configures the TIMx event to be generate by software.
* @param TIMx: where x can be 0-5 to select the TIM peripheral.
* @param TIM_EventSource: specifies the event source.
* This parameter can be one or more of the following values @ref TIMx_Event_Generation_definitons
* @note
* - TIM0~5/TIMM00~05 have Timer update Event source TIM_EventSource_Update
* - TIM4/TIMM04 have Timer Capture Compare 1 Event source TIM_EventSource_CC0
* - TIMM05 has 6 Timer Capture Compare x Event source TIM_EventSource_CC0-5.
* - TIM5 has 18 Timer Capture Compare x Event source TIM_EventSource_CC0-17.
* @retval None
*/
void RTIM_GenerateEvent(RTIM_TypeDef* TIMx, u32 TIM_EventSource)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_TIM(TIMx));
assert_param((IS_HP_TIM_EVENT_SOURCE(TIM_EventSource) || IS_LP_TIM_EVENT_SOURCE(TIM_EventSource)));
/* Set the event sources */
TIMx->EGR = TIM_EventSource;
}
/**
* @brief Sets the TIMx Autoreload Register(TIMx_ARR) value to change period
* @param TIMx: where x can be 0-5 to select the TIM peripheral.
* @param Autoreload: specifies the Autoreload register new value.
* To TIM0~3/TIMM00~TIMM03 this value can be a number in 0~0xFFFFFFFF range.
* To TIM4~5/TIMM04~TIMM05 this value can be a number in 0~0xFFFF range.
* @retval None
*/
void RTIM_ChangePeriodImmediate(RTIM_TypeDef* TIMx, u32 Autoreload)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_TIM(TIMx));
/* Reset the ARR Preload Bit */
/* period will update immediatly */
TIMx->CR &= ~TIM_CR_ARPE;
/* Set the Autoreload Register value */
TIMx->ARR = Autoreload;
/* Generate an update event */
/* 1) reload the Prescaler immediatly */
/* 2) reload the ARR immediatly */
/* 3) hadrware will clear this bit after reload */
/* 4) UEV will reset counter, and counter will start from 0 */
/* 5) gen a interrupt if use TIM_UpdateSource_Global */
TIMx->EGR = TIM_PSCReloadMode_Immediate;
/* poll EGR UG done */
while (1) {
if (TIMx->SR & TIM_SR_UG_DONE)
break;
}
}
/**
* @brief Sets the TIMx Autoreload Register(TIMx_ARR) value to change period with protection
* @param TIMx: where x can be 0-5 to select the TIM peripheral.
* @param Autoreload: specifies the Autoreload register new value.
* To TIM0~3/TIMM00~TIMM03 this value can be a number in 0~0xFFFFFFFF range.
* To TIM4~5/TIMM04~TIMM05 this value can be a number in 0~0xFFFF range.
* @retval None
*/
void RTIM_ChangePeriod(RTIM_TypeDef* TIMx, u32 Autoreload)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_TIM(TIMx));
/* Set the Autoreload Register value */
TIMx->ARR = Autoreload;
}
/**
* @brief Reset timer, counter will start from 0
* @param TIMx: where x can be 0-5 to select the TIM peripheral.
* @retval None
*/
void RTIM_Reset(RTIM_TypeDef* TIMx)
{
/* Check the parameters */
assert_param(IS_TIM_ALL_TIM(TIMx));
/* Generate an update event */
/* 1) reload the Prescaler immediatly */
/* 2) reload the ARR immediatly */
/* 3) hadrware will clear this bit after reload */
/* 4) UEV will reset counter, and counter will start from 0 */
/* 5) gen a interrupt if use TIM_UpdateSource_Global */
TIMx->EGR = TIM_PSCReloadMode_Immediate;
}
/**
* @brief Fills each TIM_CCInitStruct member with its default value.
* @param TIM_CCInitStruct: pointer to a TIM_CCInitTypeDef structure which will
* be initialized.
* @retval None
*/
void RTIM_CCStructInit(TIM_CCInitTypeDef* TIM_CCInitStruct)
{
/* Set the default configuration */
TIM_CCInitStruct->TIM_CCMode = TIM_CCMode_PWM;
TIM_CCInitStruct->TIM_CCPolarity = TIM_CCPolarity_High;
TIM_CCInitStruct->TIM_OCProtection = TIM_OCPreload_Enable;
TIM_CCInitStruct->TIM_OCPulse = 0xFFF;
}
/**
* @brief Initializes the TIMx Channel 0-5 according to the specified parameters in
* the TIM_CCInitStruct.
* @param TIMx: where x can be 4/5, to select the TIM peripheral.
* @param TIM_CCInitStruct: pointer to a TIM_CCInitTypeDef structure that contains
* the configuration information for the specified TIM peripheral.
* @param TIM_Channel: the channel need to be initialized,
* which can be one of the following parameters @ref TIM_Channel_definitions
* @note
* - TIM4/TIMM04 only has 1 channel: TIM_Channel_0
* - TIMM05 has 6 channels: TIM_Channel_0-5.
* - TIM5 has 18 channels: TIM_Channel_0-17.
* @retval None
*/
void RTIM_CCxInit(RTIM_TypeDef* TIMx, TIM_CCInitTypeDef* TIM_CCInitStruct, u16 TIM_Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCM_TIM(TIMx));
assert_param(IS_TIM_CC_MODE(TIM_CCInitStruct->TIM_CCMode));
assert_param(IS_TIM_CC_POLARITY(TIM_CCInitStruct->TIM_CCPolarity));
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_CCInitStruct->TIM_OCProtection));
assert_param(IS_TIM_CHANNEL(TIM_Channel));
/* Reset the CCMR Bit */
TIMx->CCMRx[TIM_Channel] = 0;
/* Write to TIMx CCMR */
if (IS_TIM_PWM_TIM(TIMx)) {
TIMx->CCMRx[TIM_Channel] = (TIM_CCInitStruct->TIM_CCPolarity |
TIM_CCInitStruct->TIM_OCProtection |
TIM_CCInitStruct->TIM_CCMode |
TIM_CCInitStruct->TIM_OCPulse);
} else if (IS_TIM_INPULSE_TIM(TIMx)) {
TIMx->CCMRx[TIM_Channel] = (TIM_CCInitStruct->TIM_CCPolarity |
TIM_CCInitStruct->TIM_ICPulseMode);
}
}
/**
* @brief Initializes the TIMx Channel 0-5 CCmode.
* @param TIMx: where x can be 5, to select the TIM peripheral.
* @param TIM_Channel: the channel need to be set mode,
* which can be one of the following parameters @ref TIM_Channel_definitions.
* @param TIM_CCMode: CCx working mode which can be one of the following parameters:
* @arg TIM_CCMode_PWM
* @arg TIM_CCMode_Inputcapture
* @note
* - TIM4/TIMM04 only has 1 channel: TIM_Channel_0
* - TIMM05 has 6 channels: TIM_Channel_0-5.
* - TIM5 has 18 channels: TIM_Channel_0-17.
* @retval None
*/
void RTIM_CCRxMode(RTIM_TypeDef* TIMx, u16 TIM_Channel, u32 TIM_CCMode)
{
u32 tmpccmr = TIMx->CCMRx[TIM_Channel];
/* Check the parameters */
assert_param(IS_TIM_PWM_TIM(TIMx));
assert_param(IS_TIM_CC_MODE(TIM_CCMode));
tmpccmr &= ~TIM_CCER_CCxM;
tmpccmr |= TIM_CCMode;
/* Write to TIMx CCMR */
TIMx->CCMRx[TIM_Channel] = tmpccmr;
}
/**
* @brief Sets the TIMx Capture Compare X register value
* @param TIMx: where x can be 5, to select the TIM peripheral.
* @param Compare: the value specifies pulsewidth, which is in the 0x00~0xFFFF range.
* Duty cycle = Compare / (ARR+1).
* @param TIM_Channel: the channel to be set,
* which can be one of the following parameters @ref TIM_Channel_definitions.
* @retval None
* @note
* - CCRx=0 will give 0% cycle pwm pulse.
* - CCRx>=TIM_Period there will be 100% pwm pulse.
* - TIMM05 has 6 channels: TIM_Channel_0-5.
* - TIM5 has 18 channels: TIM_Channel_0-17.
*/
void RTIM_CCRxSet(RTIM_TypeDef* TIMx, u32 Compare, u16 TIM_Channel)
{
u32 PulseWidth = 0;
u32 tmpccmr = 0;
/* Check the parameters */
assert_param(IS_TIM_PWM_TIM(TIMx));
assert_param(IS_TIM_CHANNEL(TIM_Channel));
assert_param(IS_TIM_CC_PULSEWIDTH(Compare));
/* CCRx=0 will give 0% cycle pwm pulse */
PulseWidth = Compare;
tmpccmr = TIMx->CCMRx[TIM_Channel];
/* reset Compare val */
tmpccmr &= ~TIM_CCMode_CCR;
/* Set the Capture CompareX Register value */
tmpccmr |= (u32)PulseWidth;
/* set CCMR */
TIMx->CCMRx[TIM_Channel] = tmpccmr;
}
/**
* @brief Gets the TIMx Capture Compare X register value.
* @param TIMx: where x can be 4/5, to select the TIM peripheral.
* @param TIM_Channel: the channel to be read,
* which can be one of the following parameters @ref TIM_Channel_definitions.
* @retval Capture Compare x Register value.
* @note If you want to get pulse width of PWM, remember to plus 1 to
* the retval of this function.
* - TIMM05 has 6 channels: TIM_Channel_0-5.
* - TIM5 has 18 channels: TIM_Channel_0-17.
*/
u32 RTIM_CCRxGet(RTIM_TypeDef* TIMx, u16 TIM_Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCM_TIM(TIMx));
assert_param(IS_TIM_CHANNEL(TIM_Channel));
/* Get the Capture Compare x Register value */
return (TIMx->CCMRx[TIM_Channel] & TIM_CCMode_CCR);
}
/**
* @brief Enables or disables the TIMx peripheral Preload register on CCRx.
* @param TIMx: where x can be 5, to select the TIM peripheral.
* @param TIM_OCProtection: new state of the TIMx peripheral Preload register
* This parameter can be one of the following values:
* @arg TIM_OCPreload_Enable: value is loaded in the active register at each update event.
* @arg TIM_OCPreload_Disable: new value is taken in account immediately
* @param TIM_Channel: the channel need to be set,
* which can be one of the following parameters @ref TIM_Channel_definitions
* @note
* - TIMM05 has 6 channels: TIM_Channel_0-5.
* - TIM5 has 18 channels: TIM_Channel_0-17.
* @retval None
*/
void RTIM_OCxPreloadConfig(RTIM_TypeDef* TIMx, u32 TIM_OCProtection, u16 TIM_Channel)
{
u32 tmpccmr = 0;
/* Check the parameters */
assert_param(IS_TIM_PWM_TIM(TIMx));
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCProtection));
assert_param(IS_TIM_CHANNEL(TIM_Channel));
tmpccmr = TIMx->CCMRx[TIM_Channel];
/* Reset the OC1PE Bit */
tmpccmr &= ~(TIM_OCER_CCxPE);
/* Enable or Disable the Output Compare Preload feature */
tmpccmr |= TIM_OCProtection;
/* Write to TIMx CCMR1 register */
TIMx->CCMRx[TIM_Channel] = tmpccmr;
}
/**
* @brief Configures the TIMx channel x polarity.
* @param TIMx: where x can be 5, to select the TIM peripheral.
* @param TIM_OCPolarity: specifies the OCx Polarity
* This parameter can be one of the following values:
* @arg TIM_CCPolarity_High: Output Compare active high
* @arg TIM_CCPolarity_Low: Output Compare active low
* @retval None
* @note
* -TIMM05 have CCR0-5
* -TIM5 have CCR0-17
* -TIM4/TIMM04 have CCR0
* -TIM0-3/TIMM00-3 dont have CCMR
*/
void RTIM_CCxPolarityConfig(RTIM_TypeDef* TIMx, u32 TIM_OCPolarity, u16 TIM_Channel)
{
u32 tmpccmr = 0;
/* Check the parameters */
assert_param(IS_TIM_PWM_TIM(TIMx));
assert_param(IS_TIM_CC_POLARITY(TIM_OCPolarity));
assert_param(IS_TIM_CHANNEL(TIM_Channel));
tmpccmr = TIMx->CCMRx[TIM_Channel];
/* Set or Reset the CCxP Bit */
tmpccmr &= ~(TIM_CCER_CCxP);
tmpccmr |= TIM_OCPolarity;
/* Write to TIMx CCER register */
TIMx->CCMRx[TIM_Channel] = tmpccmr;
}
/**
* @brief Enables or disables the TIM Capture Compare Channel x.
* @param TIMx: where x can be 4/5, to select the TIM peripheral.
* @param TIM_Channel: specifies the TIM Channel
* This parameter can be one of the following values @ref TIM_Channel_definitions
* @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
* This parameter can be one of the following values:
* @arg TIM_CCx_Enable
* @arg TIM_CCx_Disable
* @note
* - TIMM05 has 6 channels: TIM_Channel_0-5.
* - TIM5 has 18 channels: TIM_Channel_0-17.
* @retval None
*/
void RTIM_CCxCmd(RTIM_TypeDef* TIMx, u16 TIM_Channel, u32 TIM_CCx)
{
u32 tmpccmr = TIMx->CCMRx[TIM_Channel];
/* Check the parameters */
assert_param(IS_TIM_CCM_TIM(TIMx));
assert_param(IS_TIM_CHANNEL(TIM_Channel));
assert_param(IS_TIM_CCX(TIM_CCx));
tmpccmr &= ~TIM_CCER_CCxE;
tmpccmr |= TIM_CCx;
/* Set or reset the CCxE Bit */
TIMx->CCMRx[TIM_Channel] = tmpccmr;
}
/**
* @brief Set the TIMx's One Pulse Mode (output one pulse PWM mode).
* @param TIMx: where x can be 5 to select the TIM peripheral.
* @param TIM_OPMode: specifies the OPM Mode to be used.
* This parameter can be one of the following values:
* @arg TIM_OPMode_Single
* @arg TIM_OPMode_Repetitive
* @param TrigerPolarity: specifies the OPM Mode Triger Polarity.
* This parameter can be one of the following values:
* @arg TIM_OPMode_ETP_positive
* @arg TIM_OPMode_ETP_negative
* @note You must select TIM_OPMode_Single if you want to set One Pluse Mode,
* which makes the counter stop automatically at the next UEV.
* @retval None
*/
void RTIM_SetOnePulseOutputMode(RTIM_TypeDef* TIMx, u32 TIM_OPMode, u32 TrigerPolarity)
{
/* Check the parameters */
assert_param(IS_TIM_ONE_PULSE_TIM(TIMx));
assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
assert_param(IS_TIM_OPM_ETP_MODE(TrigerPolarity));
/* Reset the OPM & ETP Bit */
TIMx->CR &= (u32)~(TIM_CR_OPM | TIM_CR_ETP);
/* Configure the OPM Mode */
TIMx->CR |= TIM_OPMode | TrigerPolarity;
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_tim.c
|
C
|
apache-2.0
| 17,890
|
/**
******************************************************************************
* @file rtl8721d_uart.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for the UART firmware
* library, including the following functionalities of the Universal Asynchronous
* Receiver/Transmitter (UART) peripheral:
* - Uart DMA mode Initialization
* - Uart DMA mode config
* - Uart DMA mode control(enable or disable)
* - Uart Low Power Rx Initialization
* - Uart Low Power Rx Monitor Function config
* - Low Power Rx Baud Rate Setting
* - Uart IrDA Function Initialization
* - Uart IrDA Function control(enable or disable)
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable peripheral clock using the following functions
* RCC_PeriphClockCmd(APBPeriph_UARTx, APBPeriph_UARTx_CLOCK, ENABLE);
*
* 2. configure the UART pinmux.
* Pinmux_Config(Pin_Num, PINMUX_FUNCTION_UART)
*
* 3. disable uart rx path
*
* 4. select rx path clock source(XTAL 40M Hz/XTAL 2M Hz/OSC 2M Hz)
*
* 5. clear rx fifo.
*
* 6. Program Word Length , Stop Bit, Parity, Hardware flow control and DMA Mode(ENABLE/DISABLE)
* using the UART_Init() function.
*
* 7. Program the Baud Rate, using function UART_SetBaud().
*
* 8. Enable the NVIC and the corresponding interrupt using the function
* UART_INTConfig() and register the uart irq handler if you need to use interrupt mode.
*
* 9. When using the DMA mode
* - GDMA related configurations(source address/destination address/block size etc.)
* - Configure the uart DMA burst size using UART_TXDMAConfig()/UART_RXDMAConfig() function
* - Active the UART TX/RX DMA Request using UART_TXDMACmd()/UART_RXDMACmd() function
*
* 10. enable uart rx path
*
* Refer to related specifications for more details about IrDA function and Low Power Rx Path(monitoring and clock
* swicth).
*
* In order to reach higher communication baudrates, high rate rx path can be used.
* Low power rx can be used for saving power.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
const UART_DevTable UART_DEV_TABLE[4] = {
{UART0_DEV, GDMA_HANDSHAKE_INTERFACE_UART0_TX, GDMA_HANDSHAKE_INTERFACE_UART0_RX, UART0_IRQ}, /*uart0 */
{UART1_DEV, GDMA_HANDSHAKE_INTERFACE_UART1_TX, GDMA_HANDSHAKE_INTERFACE_UART1_RX, UART1_IRQ}, /*uart1_bt */
{UART2_DEV, 0xFF, 0xFF, UART_LOG_IRQ}, /*log uart */
{UART3_DEV, GDMA_HANDSHAKE_INTERFACE_UART3_TX, GDMA_HANDSHAKE_INTERFACE_UART3_RX, UARTLP_IRQ}, /*luart */
};
u32 UART_StateTx[4];
u32 UART_StateRx[4];
/**
* @brief configure UART TX DMA burst size .
* @param UARTx: where x can be 0/1/3.
* @param TxDmaBurstSize: UART TX DMA burst size.
* @note Because UART tx fifo depth is 16 in hardware.
* Therefore this value must be no more than 16.
* @retval None
*/
void
UART_TXDMAConfig(UART_TypeDef* UARTx, u32 TxDmaBurstSize)
{
u32 TempMiscr;
/* Set UART TX DMA burst size.*/
TempMiscr = UARTx->MISCR;
TempMiscr &= ~(RUART_TXDMA_BURSTSIZE_MASK);
TempMiscr |= ((TxDmaBurstSize << 3) & RUART_TXDMA_BURSTSIZE_MASK);
UARTx->MISCR = TempMiscr;
}
/**
* @brief configure UART RX DMA burst size .
* @param UARTx: where x can be 0/1/3.
* @param RxDmaBurstSize: UART RX DMA burst size.
* @note Because UART rx fifo depth is 16 in hardare.
* Therefore this value must be no more than 16.
* @retval None
*/
void
UART_RXDMAConfig(UART_TypeDef* UARTx, u32 RxDmaBurstSize)
{
u32 TempMiscr;
/* Set UART Rx DMA burst size */
TempMiscr = UARTx->MISCR;
TempMiscr &= ~(RUART_RXDMA_BURSTSIZE_MASK);
TempMiscr |= ((RxDmaBurstSize << 8) & RUART_RXDMA_BURSTSIZE_MASK);
UARTx->MISCR = TempMiscr;
}
/**
* @brief enable or disable UART TX DMA .
* @param UARTx: where x can be 0/1/3.
* @param NewState: the new state of UART TX DMA.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void
UART_TXDMACmd(UART_TypeDef* UARTx, u32 NewState)
{
if(NewState != DISABLE ){
/* enable the UART TX DMA */
UARTx->MISCR |= RUART_TXDMA_ENABLE;
} else {
/* disable the UART TX DMA */
UARTx->MISCR &= (~ RUART_TXDMA_ENABLE);
}
}
/**
* @brief enable or disable UART RX DMA .
* @param UARTx: where x can be 0/1/3.
* @param NewState: the new state of UART RX DMA.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void
UART_RXDMACmd(UART_TypeDef* UARTx, u32 NewState)
{
if(NewState != DISABLE ){
/* enable the UART RX DMA */
UARTx->MISCR |= RUART_RXDMA_ENABLE;
} else {
/* disable the UART RX DMA */
UARTx->MISCR &= (~ RUART_RXDMA_ENABLE);
}
}
/**
* @brief Init and Enable UART TX GDMA.
* @param UartIndex: 0/1/3.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pTxBuf: Tx Buffer.
* @param TxCount: Tx Count.
* @retval TRUE/FLASE
*/
BOOL UART_TXGDMA_Init(
u8 UartIndex,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pTxBuf,
int TxCount
)
{
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);//ACUT is 0x10, BCUT is 12
if (GdmaChnl == 0xFF) {
/* No Available DMA channel */
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_InitStruct->GDMA_DIR = TTFCMemToPeri;
GDMA_InitStruct->GDMA_DstHandshakeInterface = UART_DEV_TABLE[UartIndex].Tx_HandshakeInterface;
GDMA_InitStruct->GDMA_DstAddr = (u32)&UART_DEV_TABLE[UartIndex].UARTx->RB_THR;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_DstInc = NoChange;
GDMA_InitStruct->GDMA_SrcInc = IncType;
if (((TxCount & 0x03)==0) && (((u32)(pTxBuf) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeOne;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_BlockSize = TxCount >> 2;
} else {
/* move 1 byte each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_BlockSize = TxCount;
}
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
GDMA_InitStruct->GDMA_SrcAddr = (u32)(pTxBuf);
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Init and Enable UART RX GDMA.
* @param UartIndex:0/1/3.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pRxBuf: Rx Buffer.
* @param RxCount: Rx Count, 0 will use UART as DMA controller.
* @retval TRUE/FLASE
*/
BOOL UART_RXGDMA_Init(
u8 UartIndex,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pRxBuf,
int RxCount
)
{
u8 GdmaChnl;
UART_TypeDef* UARTx;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);
if (GdmaChnl == 0xFF) {
/* No Available DMA channel */
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
UARTx = UART_DEV_TABLE[UartIndex].UARTx;
if(RxCount == 0) {
/*if length is 0, configure uart as the flow controller*/
GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem_PerCtrl;
UARTx->MISCR |= RUART_RXDMA_OWNER;
} else {
/*if length is 0, configure GDMA as the flow controller*/
GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem;
UARTx->MISCR &= (~RUART_RXDMA_OWNER);
}
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->GDMA_SrcHandshakeInterface = UART_DEV_TABLE[UartIndex].Rx_HandshakeInterface;
GDMA_InitStruct->GDMA_SrcAddr = (u32)&UART_DEV_TABLE[UartIndex].UARTx->RB_THR;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_DstInc = IncType;
GDMA_InitStruct->GDMA_SrcInc = NoChange;
if (((u32)(pRxBuf) & 0x03)==0) {
/* 4-bytes aligned, move 4 bytes each DMA transaction */
GDMA_InitStruct->GDMA_DstMsize = MsizeOne;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
} else {
/* move 1 byte each DMA transaction */
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
}
GDMA_InitStruct->GDMA_BlockSize = RxCount;
GDMA_InitStruct->GDMA_DstAddr = (u32)(pRxBuf);
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
/* multi block close */
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief configure uart monitor parameters.
* @param BitNumThres: Configure bit number threshold of one monitor period.
* @param OscPerbitUpdCtrl: the OSC cycnum_perbit update bit(can be ENABLE or DISABLE).
* @retval None
*/
void UART_MonitorParaConfig(UART_TypeDef* UARTx, u32 BitNumThres, u32 OscPerbitUpdCtrl)
{
u32 RegValue = 0;
/*check the parameters*/
assert_param((BitNumThres>0) && (BitNumThres<128));
/* Step 1: Reset Low Power Rx Path */
UARTx->RX_PATH &= ~RUART_REG_LP_RX_PATH_RESET;
RegValue = UARTx->MON_BAUD_CTRL;
/*step 2: Configure bit number threshold of one monitor period.*/
RegValue &= (~ RUART_LP_RX_BIT_NUM_THRES);
RegValue |= ((BitNumThres << 1) & RUART_LP_RX_BIT_NUM_THRES);
/*step 3: Configure the OSC cycnum_perbit update bit (REG_MON_BAUD_CTRL[29])*/
if(OscPerbitUpdCtrl != DISABLE){
/*enable OSC cycnum_perbit update*/
RegValue |= RUART_LP_RX_OSC_UPD_IN_XTAL;
} else {
/*disable OSC cycnum_perbit update*/
RegValue &= ~ RUART_LP_RX_OSC_UPD_IN_XTAL;
}
UARTx->MON_BAUD_CTRL = RegValue;
}
/**
* @brief set uart baud rate of low power rx path
* @param UARTx: where x can be 0/1/3.
* @param BaudRate: the desired baud rate
* @param RxIPClockHz: the uart rx clock. unit: [Hz]
* @note according to the baud rate calculation formlula in low power rx path, method
* implemented is as follows:
* - CycPerbit = round( fpclock/BaudRate)
* @retval None
*/
void
UART_LPRxBaudSet(UART_TypeDef* UARTx, u32 BaudRate, u32 RxIPClockHz)
{
u32 CycPerbit = 0;
u32 RegValue = 0;
u32 RegOscBaud = 0;
/*check the parameters*/
assert_param((BaudRate > 0 && BaudRate <= 500000));
/*Calculate the r_cycnum_perbit field of REG_ MON_BAUD_STS,
according to clock and the desired baud rate*/
if((RxIPClockHz % BaudRate) >= (BaudRate + 1) / 2){
CycPerbit = RxIPClockHz / BaudRate + 1;
} else {
CycPerbit = RxIPClockHz / BaudRate;
}
/* Average clock cycle number of one bit. MON_BAUD_STS[19:0] */
RegValue = UARTx->MON_BAUD_STS;
RegValue &= (~ RUART_LP_RX_XTAL_CYCNUM_PERBIT);
RegValue |= (CycPerbit & RUART_LP_RX_XTAL_CYCNUM_PERBIT);
/* set CycPerbit */
UARTx->MON_BAUD_STS = RegValue;
/* Average clock cycle number of one bit OSC. REG_MON_BAUD_CTRL[28:9] */
RegOscBaud = UARTx->MON_BAUD_CTRL;
RegOscBaud &= (~ RUART_LP_RX_OSC_CYCNUM_PERBIT);
RegOscBaud |= ((CycPerbit << 9) & RUART_LP_RX_OSC_CYCNUM_PERBIT);
/*set the OSC CycPerbit*/
UARTx->MON_BAUD_CTRL = RegOscBaud;
UARTx->RX_PATH &= (~RUART_REG_RX_XFACTOR_ADJ);
}
/**
* @brief enable or disable the monitor function in Low Power Rx Path( REG_MON_BAUD_CTRL[0] ).
* @param UARTx: where x can be 0/1/3.
* @param NewState: the new state of monitoring.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void
UART_RxMonitorCmd(UART_TypeDef* UARTx, u32 NewState)
{
/* configure Low Power rx monitoring function*/
if(NewState != DISABLE ){
/* Function enable of monitoring rx baud */
UARTx->MON_BAUD_CTRL |= RUART_LP_RX_MON_ENABLE;
} else {
/* Function disable of monitoring rx baud */
UARTx->MON_BAUD_CTRL &= (~ RUART_LP_RX_MON_ENABLE);
}
}
/**
* @brief Get the Monitor Baud Rate control register value of the Low Power Rx Path.
* @param UARTx: where x can be 0/1/3.
* @note MON_BAUD_CTRL[28:9] field value is the monitor result under OSC 2M Hz Clock.
* @retval the value of the MON_BAUD_CTRL register
*/
u32
UART_RxMonBaudCtrlRegGet(UART_TypeDef* UARTx)
{
/*return the monitor baud rate control register value(MON_BAUD_CTRL)*/
return UARTx->MON_BAUD_CTRL;
}
/**
* @brief Get the status of the Low Power Rx Monitoring.
* @param UARTx: where x can be 0/1/3.
* @note Read this register can clear the monitor interrupt status.
* Besides,REG_MON_BAUD_STS[19:0] field value is the monitor
* result under XTAL 2M Hz Clock.
* @retval the value of the REG_MON_BAUD_STS register
*/
u32
UART_RxMonitorSatusGet(UART_TypeDef* UARTx)
{
/*return the monitor status register value*/
return UARTx->MON_BAUD_STS;
}
/**
* @brief Fills each IrDA_InitStruct member with its default value.
* @param IrDA_InitStruct : pointer to a IrDA_InitTypeDef
* structure which will be initialized.
* @retval None
*/
void
UART_IrDAStructInit(IrDA_InitTypeDef * IrDA_InitStruct)
{
/* Set the default value */
IrDA_InitStruct->UART_IrDARxInv = DISABLE;
IrDA_InitStruct->UART_IrDATxInv = DISABLE;
IrDA_InitStruct->UART_LowShift = UART_IRDA_PULSE_LEFT_SHIFT;
IrDA_InitStruct->UART_LowShiftVal = 0;
IrDA_InitStruct->UART_UpperShift = UART_IRDA_PULSE_LEFT_SHIFT;
IrDA_InitStruct->UART_UpperShiftVal = 0;
IrDA_InitStruct->UART_RxFilterCmd = ENABLE;
IrDA_InitStruct->UART_RxFilterThres = 7;
}
/**
* @brief Configures the UART's IrDA interface .
* @param UARTx: where x can be 0/1/3.
* @param IrDA_InitStruct: pointer to a IrDA_InitTypeDef structure that contains
* the configuration information for the IrDA module.
* @note the details of IrDA_InitStruct members are:
* @verbatim
* IrDA_InitStruct-> UART_IrDARxInv:
* IrDA Rx invert bit--------------------MISCR[14]
* ENABLE: invert irda rx
* DISABLE: not invert irda rx
*
* IrDA_InitStruct->UART_IrDATxInv:
* IrDA Tx invert bit---------------------MISCR[13]
* ENABLE: invert irda tx
* DISABLE: not invert irda tx
*
* IrDA_InitStruct->UART_UpperShift:
* Upperbound(right edge) Shift direction---TXPLSR[31]
* UART_IRDA_PULSE_LEFT_SHIFT: shift left
* UART_IRDA_PULSE_RIGHT_SHIFT: shift right
* IrDA_InitStruct->UpperShiftVal:
* Upperbound Shift value---------------TXPLSR[30:16]
*
* IrDA_InitStruct->UART_LowShift:
* Lowbound(left edge) Shift direction-----TXPLSR[15]
* UART_IRDA_PULSE_LEFT_SHIFT: shift left
* UART_IRDA_PULSE_RIGHT_SHIFT: shift right
* IrDA_InitStruct->UART_LowShiftVal:
* Lowbound Shift value----------------TXPLSR[14:0]
*
* IrDA_InitStruct->UART_RxFilterThres:
* IrDA RX filter threshold---------------RXPLSR[15:1]
*
* IrDA_InitStruct->UART_RxFilterCmd:
* IrDA RX filter enable or disable---------RXPLSR[0]
* ENABLE: enable IrDA rx filter
* DISABLE: disable IrDA rx filter
* @endverbatim
* @retval None
*/
void
UART_IrDAInit(UART_TypeDef* UARTx, IrDA_InitTypeDef * IrDA_InitStruct)
{
u32 TempMiscr;
u32 TempTxpulse;
u32 TempRxPulse;
/* Check the parameters */
assert_param(IrDA_InitStruct->UART_UpperShiftVal <= 0x7fff );
assert_param(IrDA_InitStruct->UART_LowShiftVal <= 0x7fff);
assert_param(IS_IRDA_PUL_SHIFT(IrDA_InitStruct->UART_LowShift));
assert_param(IS_IRDA_PUL_SHIFT(IrDA_InitStruct->UART_UpperShift));
assert_param((IrDA_InitStruct->UART_RxFilterThres <= 0x7fff));
/*Get the MISCR register value*/
TempMiscr = UARTx->MISCR;
/*configure the IrDA RX invert bit*/
if(IrDA_InitStruct->UART_IrDARxInv != DISABLE){
/*invert the irda_rx_i*/
TempMiscr |= RUART_IRDA_RX_INVERT;
} else {
/*not invert the irda_rx_i*/
TempMiscr &= (~ RUART_IRDA_RX_INVERT);
}
/*configure the IrDA TX invert bit*/
if(IrDA_InitStruct->UART_IrDATxInv != DISABLE){
/*invert the irda_tx_o*/
TempMiscr |= RUART_IRDA_TX_INVERT;
} else {
/*not invert the irda_tx_o*/
TempMiscr &= (~ RUART_IRDA_TX_INVERT);
}
UARTx->MISCR = TempMiscr;
/*Get the TXPLSR register value*/
TempTxpulse = UARTx->TXPLSR;
/*configure IrDA SIR TX Pulse Width*/
/*configure Upperbound(right edge) shift direction*/
TempTxpulse &= (~ RUART_IRDA_TX_PUL_UP_BUND_SHIFT);
TempTxpulse |= (IrDA_InitStruct->UART_UpperShift << 31);
/*configure the Upperbound shift value*/
TempTxpulse &= (~ RUART_IRDA_TX_PUL_UP_BUND_VAL);
TempTxpulse |= (IrDA_InitStruct->UART_UpperShiftVal << 16);
/*configure Lowbound(left edge) shift direction*/
TempTxpulse &= (~ RUART_IRDA_TX_PUL_LOW_BUND_SHIFT);
TempTxpulse |= (IrDA_InitStruct->UART_LowShift << 15);
/*configure the Lowbound shift value*/
TempTxpulse &= (~ RUART_IRDA_TX_PUL_LOW_BUND_VAL);
TempTxpulse |= (IrDA_InitStruct->UART_LowShiftVal);
UARTx->TXPLSR = TempTxpulse;
/*Get the RXPLSR register value*/
TempRxPulse = UARTx->RXPLSR;
/*configure IrDA RX filter threshold*/
TempRxPulse &= (~ RUART_IRDA_RX_FILTER_THRES);
TempRxPulse |= (IrDA_InitStruct->UART_RxFilterThres << 1);
if(IrDA_InitStruct->UART_RxFilterCmd != DISABLE){
/*enable IrDA rx filter*/
TempRxPulse |= RUART_IRDA_RX_FILTER_ENABLE;
} else {
/*disable IrDA rx filter*/
TempRxPulse &= (~ RUART_IRDA_RX_FILTER_ENABLE);
}
UARTx->RXPLSR = TempRxPulse;
}
/**
* @brief enable or disable the IrDA function.
* @param UARTx: where x can be 0/1/3.
* @param NewState: the new state of the IrDA.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void
UART_IrDACmd(UART_TypeDef* UARTx, u32 NewState)
{
if(NewState != DISABLE ){
/* enable the IrDA */
UARTx->MISCR |= RUART_IRDA_ENABLE;
} else {
/* disable the IrDA */
UARTx->MISCR &= (~ RUART_IRDA_ENABLE);
}
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_uart.c
|
C
|
apache-2.0
| 20,034
|
/**
******************************************************************************
* @file rtl8721d_wdg.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of the Watch Dog (WDG) peripheral:
* - Initialization
* - WDG refresh
* - Interrupts and flags management
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief Get WDG dividor parameters based on Period
* @param Period: WDG timeout (ms).
* @param pCountProcess: count id of WDG.
* This parameter can be set: 0 ~ 11, represent count value: 0x001~0xFFF
* @note The relationship between count id and count: Count = ((0x00000001 << (CountId+1))-1)
* @param pDivFacProcess: clock divisor of WDG timeout count.
* @note Minimum dividing factor is 1
* @note The formula to calculate dividing factor: DivFactor = (u16)(( TimeoutMs * 100)/(Count * 3))
* @retval None
*/
void WDG_Scalar(u32 Period, u32 *pCountProcess, u32 *pDivFacProcess)
{
u8 CountId;
u16 DivFactor;
u32 CountTemp;
u32 PeriodProcess = 100*Period;
u32 MinPeriodTemp = 0xFFFFFFFF;
u32 PeriodTemp = 0;
for (CountId = 0; CountId < 12; CountId++) {
CountTemp = ((0x00000001 << (CountId+1))-1);
DivFactor = (u16)((PeriodProcess)/(CountTemp*3));
if (DivFactor > 0) {
PeriodTemp = 3*(DivFactor+1)*CountTemp;
if (PeriodProcess < PeriodTemp) {
if (MinPeriodTemp > PeriodTemp) {
MinPeriodTemp = PeriodTemp;
*pCountProcess = CountId;
*pDivFacProcess = DivFactor;
}
}
}
}
}
/**
* @brief Initializes the WDG registers according to the specified parameters
* get from WDG_Scalar.
* @param WDG_InitStruct: pointer to a WDG_InitTypeDef structure that contains
* the configuration information for the WDG peripheral.
* @retval None
*/
void WDG_Init(WDG_InitTypeDef *WDG_InitStruct)
{
WDG_TypeDef* WDG = ((WDG_TypeDef *) WDG_REG_BASE);
u32 wdg_reg = 0;
u32 temp = 0;
wdg_reg = WDG_InitStruct->DivFacProcess & 0xFFFF; /* WdgScalar */
wdg_reg &= ~(0x00FF0000); /* WdgEnByte */
wdg_reg |= (WDG_InitStruct->CountProcess & 0xF) << 25;
wdg_reg |= WDG_BIT_CLEAR;
wdg_reg |= WDG_BIT_RST_MODE; /* RESET_MODE */
wdg_reg |= WDG_BIT_ISR_CLEAR; /*Clear ISR*/
WDG->VENDOR = wdg_reg;
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_KM0_CTRL);
if (WDG_InitStruct->RstAllPERI == 0)
temp &= ~BIT_LSYS_WDT_RESET_HS_ALL;
else
temp |= BIT_LSYS_WDT_RESET_HS_ALL;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_KM0_CTRL, temp);
}
/**
* @brief Clear WDG interrupt when WDG init use WDG_IrqInit .
* @param None
* @note This function only used in interrupt mode
* @retval None
*/
void WDG_IrqClear(void)
{
WDG_TypeDef* WDG = ((WDG_TypeDef *) WDG_REG_BASE);
u32 temp = WDG->VENDOR;
/* Clear ISR */
temp |= WDG_BIT_ISR_CLEAR;
WDG->VENDOR = temp;
}
/**
* @brief init WDG as interrupt mode (close reset mode).
* @param handler: WDG interrupt handler
* @param Id: WDG interrupt handler parameter
* @retval None
*/
void WDG_IrqInit(void *handler, u32 Id)
{
WDG_TypeDef* WDG = ((WDG_TypeDef *) WDG_REG_BASE);
u32 temp = WDG->VENDOR;
InterruptRegister((IRQ_FUN)handler, WDG_IRQ, Id, 0);
InterruptEn(WDG_IRQ, 0);
temp |= WDG_BIT_ISR_CLEAR;
temp &= ~WDG_BIT_RST_MODE; /* INT_MODE */
WDG->VENDOR = temp;
}
/**
* @brief Disable/Enable WDG
* @param NewState: new state of the WDG.
* This parameter can be: ENABLE or DISABLE
* @note To enable WDG timer, set 0x1 to WDG register Bit[16]
* @retval None
*/
void WDG_Cmd(u32 NewState)
{
WDG_TypeDef* WDG = ((WDG_TypeDef *) WDG_REG_BASE);
u32 temp = WDG->VENDOR;
/* WdgEnBit */
if (NewState == ENABLE)
temp |= WDG_BIT_ENABLE;
else
temp &= ~WDG_BIT_ENABLE;
WDG->VENDOR = temp;
WDG_IrqClear();
}
/**
* @brief Clear WDG timer
* @param None
* @note If call this function to refresh WDG before timeout period,
* then MCU reset or WDG interrupt won't generate
* @retval None
*/
void WDG_Refresh(void)
{
WDG_TypeDef* WDG = ((WDG_TypeDef *) WDG_REG_BASE);
u32 temp = WDG->VENDOR;
temp |= WDG_BIT_CLEAR;
WDG->VENDOR = temp;
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_common/rtl8721d_wdg.c
|
C
|
apache-2.0
| 4,698
|
#include <k_api.h>
#include "sys_api.h"
#include "sleep_ex_api.h"
//#include "alios_service.h"
uint32_t missing_tick = 0;
static uint32_t wakelock = DEFAULT_WAKELOCK;
static uint32_t sleepwakelock_timeout = 0;
static u32 system_can_yield = 1; /* default is can */
static uint32_t sleep_type = SLEEP_PG; /* 0 is power gate, 1 is clock gate */
static uint32_t max_sleep_time = 0; /* if user want wakeup peridically, can set this timer*/
KM4SLEEP_ParamDef sleep_param;
static uint32_t deepwakelock = DEFAULT_DEEP_WAKELOCK;
static uint32_t deepwakelock_timeout = 0;
static uint32_t sysactive_timeout_temp = 0;
static uint32_t sysactive_timeout_flag = 0;
static int cpu_pwr_init_flag = 0;
static kspinlock_t cpu_pwr_spin;
static uint32_t wakeup_time_ms = 0;
uint32_t missing_tick_alios = 0;
u32 tickless_debug = 0;
void pmu_acquire_wakelock(uint32_t nDeviceId)
{
wakelock |= BIT(nDeviceId);
}
void pmu_release_wakelock(uint32_t nDeviceId)
{
wakelock &= ~BIT(nDeviceId);
}
uint32_t pmu_get_wakelock_status(void)
{
return wakelock;
}
/* can not yield CPU under suspend/resume process */
uint32_t pmu_yield_os_check(void)
{
return system_can_yield;
}
CONFIG_FW_CRITICAL_CODE_SECTION
int freertos_ready_to_sleep(void)
{
u32 current_tick = SYSTIMER_TickGet();
/* timeout */
if (current_tick < sleepwakelock_timeout) {
return FALSE;
}
if (wakelock == 0) {
return TRUE;
}
else
return FALSE;
}
/*
* It is called in freertos pre_sleep_processing.
*
* @return true : System is ready to check conditions that if it can enter dsleep.
* false : System can't enter deep sleep.
**/
CONFIG_FW_CRITICAL_CODE_SECTION
int freertos_ready_to_dsleep(void)
{
u32 current_tick = SYSTIMER_TickGet();
/* timeout */
if (current_tick < deepwakelock_timeout) {
return FALSE;
}
if (deepwakelock == 0)
return TRUE;
else
return FALSE;
}
#define AliOS_ready_to_sleep freertos_ready_to_sleep
uint32_t pmu_set_sysactive_time(uint32_t timeout)
{
u32 TimeOut = 0;
if(sysactive_timeout_flag){
if (timeout > sysactive_timeout_temp) {
sysactive_timeout_temp = timeout;
}
return 1;
}
if(sysactive_timeout_temp > timeout) {
timeout = sysactive_timeout_temp;
}
sysactive_timeout_temp = 0;
TimeOut = SYSTIMER_TickGet() + timeout; //xTaskGetTickCount() + timeout;
if (TimeOut > sleepwakelock_timeout) {
sleepwakelock_timeout = TimeOut;
}
return 0;
}
uint32_t pmu_yield_os_set(int value)
{
system_can_yield = value;
}
/*
* It is called in idle task.
*
* @return true : System is ready to check conditions that if it can enter sleep.
* false : System keep awake.
**/
/**
* tickless_announce_n() is called to announces elapsed ticks to the kernel.
*/
static void tickless_announce_n(tick_t n_ticks)
{
tick_list_update((tick_t)n_ticks);
}
/**
* tickless_enter() is called when a CPU is going to enter idle state, a one
* shot interrupt is planned at sametime which is used to wake up CPU.
* @return N/A
*/
static void tickless_enter(void)
{
uint32_t tick_before_sleep;
uint32_t tick_passed;
uint32_t tick_after_sleep;
volatile uint32_t ms_passed = 0;
uint32_t ms_before_sleep = SYSTIMER_GetPassTime(0);
uint32_t wakeup_time_ms = 0;
if (freertos_ready_to_dsleep()) {
sleep_param.sleep_time = 0;// do not wake on system schedule tick
sleep_param.dlps_enable = ENABLE;
} else {
sleep_param.sleep_time = max_sleep_time;//*expected_idle_time;
max_sleep_time = 0;
sleep_param.dlps_enable = DISABLE;
}
sleep_param.sleep_type = sleep_type;
//*expected_idle_time = 0;
/* Store gtimer timestamp before sleep */
tick_before_sleep = SYSTIMER_TickGet();
sysactive_timeout_flag = 1;
IPCM0_DEV->IPCx_USR[IPC_INT_CHAN_SHELL_SWITCH] = 0x00000000;
InterruptDis(UART_LOG_IRQ);
//BKUP_Set(BKUP_REG0, BIT_KM4_WAKE_DELAY);
if (sleep_type == SLEEP_PG) {
SOCPS_SleepPG();
} else {
SOCPS_SleepCG();
}
//BKUP_Clear(BKUP_REG0, BIT_KM4_WAKE_DELAY);
/* update kernel tick by calculating passed tick from gtimer */
/* get current gtimer timestamp */
tick_after_sleep = SYSTIMER_TickGet();
/* calculated passed time */
if (tick_after_sleep > tick_before_sleep) {
tick_passed = tick_after_sleep - tick_before_sleep;
} else {
/* overflow */
tick_passed = (0xffffffff - tick_before_sleep) + tick_after_sleep;
}
tick_passed += missing_tick;
missing_tick = tick_passed & 0x1F;
/* timer clock is 32768, 0x20 is 1ms */
ms_passed = (((tick_passed & 0xFFFFFFE0) * 1000)/32768);
tickless_announce_n(ms_passed); /* update kernel tick */
wakeup_time_ms = SYSTIMER_GetPassTime(0);
sysactive_timeout_flag = 0;
pmu_set_sysactive_time(2);
if (tickless_debug) {
DBG_8195A("m4 sleeped:[%d] ms\n", wakeup_time_ms - ms_before_sleep);
}
}
/**
* tickless_exit() is called when a CPU gets interrupted. If it determeines
* that the system is waking up from tickless idle, it re-enables tick
* interrupts and stop the one shot interrupt plan, also announces elapsed
* ticks to the kernel.
*
* @return N/A
*/
static void tickless_exit(void)
{
}
/**
* cpu_pwrmgmt_init() is the entry of whole cpu power manamgement system.
*/
void cpu_pwrmgmt_init(void)
{
/* avoid reentry */
if (cpu_pwr_init_flag) {
return;
}
// tickless_debug = 1;
krhino_spin_lock_init(&cpu_pwr_spin);
/* create cpu power management framework and cpu topology structure */
//cpu_pwr_hal_lib_init();
/* init cpu tickless framework */
//tickless_init();
/* save the job complete flag */
cpu_pwr_init_flag = 1;
}
/**
* cpu_pwr_down() is invoked from idle task when it detects that the kernel
* can go idle. cpu_pwr_down() checks the current cpu idle mode and put
* cpu into lower power mode according different idle mode.
*/
void cpu_pwr_down(void)
{
if (cpu_pwr_init_flag == 0) {
return;
}
krhino_spin_lock_irq_save(&cpu_pwr_spin);
pmu_yield_os_set(0);
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
if(!AliOS_ready_to_sleep()){
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
pmu_yield_os_set(1);
krhino_spin_unlock_irq_restore(&cpu_pwr_spin);
return;
}
/* Enter a critical section but don't use the taskENTER_CRITICAL()
method as that will mask interrupts that should exit sleep mode. */
//__asm volatile( "cpsid i" );
tickless_enter();
/* Re-enable interrupts - see comments above the cpsid instruction()
above. */
//__asm volatile( "cpsie i" );
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
pmu_yield_os_set(1);
krhino_spin_unlock_irq_restore(&cpu_pwr_spin);
}
void cpu_pwr_up(void)
{
if (cpu_pwr_init_flag == 0) {
return;
}
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721d_alios_pmu.c
|
C
|
apache-2.0
| 7,049
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "ameba_soc.h"
#include "rtl8721d_system.h"
#include "psram_reserve.h"
#if defined ( __ICCARM__ )
#pragma section=".ram_image2.bss"
#pragma section=".ram_image2.nocache.data"
#pragma section=".psram.bss"
SECTION(".data") u8* __bss_start__ = 0;
SECTION(".data") u8* __bss_end__ = 0;
SECTION(".data") u8* __ram_nocache_start__ = 0;
SECTION(".data") u8* __ram_nocache_end__ = 0;
SECTION(".data") u8* __psram_bss_start__ = 0;
SECTION(".data") u8* __psram_bss_end__ = 0;
#endif
extern int main(void);
extern u32 GlobalDebugEnable;
void NS_ENTRY BOOT_IMG3(void);
extern void INT_HardFault_C(uint32_t mstack[], uint32_t pstack[], uint32_t lr_value, uint32_t fault_id);
void app_init_psram(void);
void app_section_init(void)
{
#if defined ( __ICCARM__ )
__bss_start__ = (u8*)__section_begin(".ram_image2.bss");
__bss_end__ = (u8*)__section_end(".ram_image2.bss");
__ram_nocache_start__ = (u8*)__section_begin(".ram_image2.nocache.data");
__ram_nocache_end__ = (u8*)__section_end(".ram_image2.nocache.data");
__ram_nocache_end__ = (u8*) (((((u32)__ram_nocache_end__-1) >> 5) + 1) << 5); //32-byte aligned
#endif
}
u32 app_mpu_nocache_check(u32 mem_addr) {
mpu_region_config mpu_cfg;
if (wifi_config.km4_cache_enable) {
mpu_cfg.region_base = (uint32_t)__ram_nocache_start__;
mpu_cfg.region_size = __ram_nocache_end__-__ram_nocache_start__;
} else {
mpu_cfg.region_base = 0x10000000;
mpu_cfg.region_size = 512*1024;
}
if((mem_addr >= mpu_cfg.region_base) && (mem_addr < (mpu_cfg.region_base + mpu_cfg.region_size)))
return TRUE;
else
return FALSE;
}
u32 app_mpu_nocache_init(void)
{
mpu_region_config mpu_cfg;
u32 mpu_entry = 0;
mpu_entry = mpu_entry_alloc();
if (wifi_config.km4_cache_enable) {
mpu_cfg.region_base = (uint32_t)__ram_nocache_start__;
mpu_cfg.region_size = __ram_nocache_end__-__ram_nocache_start__;
} else {
mpu_cfg.region_base = 0x10000000;
mpu_cfg.region_size = 512*1024;
}
mpu_cfg.xn = MPU_EXEC_ALLOW;
mpu_cfg.ap = MPU_UN_PRIV_RW;
mpu_cfg.sh = MPU_NON_SHAREABLE;
mpu_cfg.attr_idx = MPU_MEM_ATTR_IDX_NC;
if (mpu_cfg.region_size >= 32) {
mpu_region_cfg(mpu_entry, &mpu_cfg);
}
/* close 216K irom_ns cache */
mpu_entry = mpu_entry_alloc();
mpu_cfg.region_base = 0x1010A000;
mpu_cfg.region_size = 0x10140000 - 0x1010A000;
mpu_cfg.xn = MPU_EXEC_ALLOW;
mpu_cfg.ap = MPU_UN_PRIV_RW;
mpu_cfg.sh = MPU_NON_SHAREABLE;
mpu_cfg.attr_idx = MPU_MEM_ATTR_IDX_NC;
mpu_region_cfg(mpu_entry, &mpu_cfg);
/* close 80K drom_ns cache */
mpu_entry = mpu_entry_alloc();
mpu_cfg.region_base = 0x101C0000;
mpu_cfg.region_size = 0x101D4000 - 0x101C0000;
mpu_cfg.xn = MPU_EXEC_ALLOW;
mpu_cfg.ap = MPU_UN_PRIV_RW;
mpu_cfg.sh = MPU_NON_SHAREABLE;
mpu_cfg.attr_idx = MPU_MEM_ATTR_IDX_NC;
mpu_region_cfg(mpu_entry, &mpu_cfg);
/* set 1KB retention ram no-cache */
mpu_entry = mpu_entry_alloc();
mpu_cfg.region_base = 0x000C0000;
mpu_cfg.region_size = 0x400;
mpu_cfg.xn = MPU_EXEC_ALLOW;
mpu_cfg.ap = MPU_UN_PRIV_RW;
mpu_cfg.sh = MPU_NON_SHAREABLE;
mpu_cfg.attr_idx = MPU_MEM_ATTR_IDX_NC;
mpu_region_cfg(mpu_entry, &mpu_cfg);
return 0;
}
VOID app_vdd1833_detect(VOID)
{
u32 temp;
if (FALSE == is_power_supply18()) {
temp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_RFAFE_IND_VIO1833);
temp |= BIT_RFAFE_IND_VIO1833;
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_RFAFE_IND_VIO1833, temp);
}
DBG_8195A("REG_HS_RFAFE_IND_VIO1833 (0 is 1.8V): %x\n", HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_RFAFE_IND_VIO1833));
}
#if defined (__GNUC__)
/* Add This for C++ support to avoid compile error */
void _init(void) {}
#endif
void INT_HardFault_Patch_C(uint32_t mstack[], uint32_t pstack[], uint32_t lr_value, uint32_t fault_id)
{
DBG_8195A("\r\nHard Fault Patch\r\n");
INT_HardFault_C(mstack, pstack, lr_value, fault_id);
}
VOID
INT_HardFault_Patch(void)
{
__ASM volatile(
"MRS R0, MSP\n\t"
"MRS R1, PSP\n\t"
"MOV R2, LR\n\t" /* second parameter is LR current value */
"MOV R3, #0\n\t"
"SUB.W R4, R0, #128\n\t"
"MSR MSP, R4\n\t" // Move MSP to upper to for we can dump current stack contents without chage contents
"LDR R4,=INT_HardFault_Patch_C\n\t"
"BX R4\n\t"
);
}
VOID
INT_UsageFault_Patch(void)
{
__ASM volatile(
"MRS R0, MSP\n\t"
"MRS R1, PSP\n\t"
"MOV R2, LR\n\t" /* second parameter is LR current value */
"MOV R3, #1\n\t"
"SUB.W R4, R0, #128\n\t"
"MSR MSP, R4\n\t" // Move MSP to upper to for we can dump current stack contents without chage contents
"LDR R4,=INT_HardFault_Patch_C\n\t"
"BX R4\n\t"
);
}
VOID
INT_BusFault_Patch(void)
{
__ASM volatile(
"MRS R0, MSP\n\t"
"MRS R1, PSP\n\t"
"MOV R2, LR\n\t" /* second parameter is LR current value */
"MOV R3, #2\n\t"
"SUB.W R4, R0, #128\n\t"
"MSR MSP, R4\n\t" // Move MSP to upper to for we can dump current stack contents without chage contents
"LDR R4,=INT_HardFault_Patch_C\n\t"
"BX R4\n\t"
);
}
VOID
INT_MemFault_Patch(void)
{
__ASM volatile(
"MRS R0, MSP\n\t"
"MRS R1, PSP\n\t"
"MOV R2, LR\n\t" /* second parameter is LR current value */
"MOV R3, #3\n\t"
"SUB.W R4, R0, #128\n\t"
"MSR MSP, R4\n\t" // Move MSP to upper to for we can dump current stack contents without chage contents
"LDR R4,=INT_HardFault_Patch_C\n\t"
"BX R4\n\t"
);
}
extern void HardFault_Handler(void);
VOID VectorTableOverride(VOID)
{
NewVectorTable[3] = (HAL_VECTOR_FUN)HardFault_Handler;
NewVectorTable[4] = (HAL_VECTOR_FUN)HardFault_Handler;
NewVectorTable[5] = (HAL_VECTOR_FUN)HardFault_Handler;
NewVectorTable[6] = (HAL_VECTOR_FUN)HardFault_Handler;
}
extern void PendSV_Handler (void);
void SysTick_Handler( void )
{
krhino_intrpt_enter();
krhino_tick_proc();
krhino_intrpt_exit();
}
void app_init_psram(void)
{
u32 temp;
PCTL_InitTypeDef PCTL_InitStruct;
/*set rwds pull down*/
temp = HAL_READ32(PINMUX_REG_BASE, 0x104);
temp &= ~(PAD_BIT_PULL_UP_RESISTOR_EN | PAD_BIT_PULL_DOWN_RESISTOR_EN);
temp |= PAD_BIT_PULL_DOWN_RESISTOR_EN;
HAL_WRITE32(PINMUX_REG_BASE, 0x104, temp);
PSRAM_CTRL_StructInit(&PCTL_InitStruct);
PSRAM_CTRL_Init(&PCTL_InitStruct);
PSRAM_PHY_REG_Write(REG_PSRAM_CAL_PARA, 0x02030310);
/*check psram valid*/
HAL_WRITE32(PSRAM_BASE, 0, 0);
assert_param(0 == HAL_READ32(PSRAM_BASE, 0));
if(_FALSE == PSRAM_calibration())
return;
if(FALSE == psram_dev_config.psram_dev_cal_enable) {
temp = PSRAM_PHY_REG_Read(REG_PSRAM_CAL_CTRL);
temp &= (~BIT_PSRAM_CFG_CAL_EN);
PSRAM_PHY_REG_Write(REG_PSRAM_CAL_CTRL, temp);
}
#if defined ( __ICCARM__ )
__psram_bss_start__ = (u8*)__section_begin(".psram.bss");
__psram_bss_end__ = (u8*)__section_end(".psram.bss");
#endif
/*init psram bss area*/
memset(__psram_bss_start__, 0, __psram_bss_end__ - __psram_bss_start__);
//pmu_register_sleep_callback(PMU_PSRAM_DEVICE, (PSM_HOOK_FUN)app_psram_suspend, NULL, (PSM_HOOK_FUN)app_psram_resume, NULL);
}
static void* app_psram_load_ns()
{
IMAGE_HEADER *Image2Hdr = (IMAGE_HEADER *)((__flash_text_start__) - IMAGE_HEADER_LEN);
IMAGE_HEADER * Image2DataHdr = (IMAGE_HEADER *)(__flash_text_start__ + Image2Hdr->image_size);
IMAGE_HEADER *PsramHdr = (IMAGE_HEADER *)((u32)Image2DataHdr + IMAGE_HEADER_LEN + Image2DataHdr->image_size);
DBG_PRINTF(MODULE_BOOT, LEVEL_INFO,"IMG2 PSRAM_NS:[0x%x:%d:0x%x]\n", (u32)(PsramHdr + 1),
PsramHdr->image_size, PsramHdr->image_addr);
/* load psram code+data into PSRAM */
if((PsramHdr->image_size != 0) && \
(PsramHdr->image_addr == 0x02000020) && \
(PsramHdr->signature[0] == 0x35393138) && \
(PsramHdr->signature[1] == 0x31313738)) {
_memcpy((void*)PsramHdr->image_addr, (void*)(PsramHdr + 1), PsramHdr->image_size);
}
}
// The Main App entry point
void app_start(void)
{
//cmse_address_info_t cmse_address_info = cmse_TT((void *)DiagPrintf);
#if defined (configUSE_SAU) && (configUSE_SAU == 1U)
irq_table_init(MSP_RAM_HP_NS); /* NS Vector table init */
#endif
VectorTableOverride();
app_section_init();
_memset((void *) __bss_start__, 0, (__bss_end__ - __bss_start__));
if(HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_BOOT_CFG) & BIT_BOOT_IMG3_EXIST) {
BOOT_IMG3();
}
/* enable non-secure cache */
Cache_Enable(ENABLE);
DBG_PRINTF(MODULE_BOOT, LEVEL_INFO,"KM4 BOOT REASON: %x \n", BOOT_Reason());
SystemCoreClockUpdate();
SOCPS_InitSYSIRQ_HP();
/* Init PSRAM */
if(TRUE == psram_dev_config.psram_dev_enable) {
app_init_psram();
}
__NVIC_SetVector(SVCall_IRQn, (u32)(VOID*)NULL);
__NVIC_SetVector(PendSV_IRQn, (u32)(VOID*)PendSV_Handler);
__NVIC_SetVector(SysTick_IRQn, (u32)(VOID*)SysTick_Handler);
/* load psram image if needed */
if(TRUE == psram_dev_config.psram_dev_enable) {
app_psram_load_ns();
}
#if defined (__GNUC__)
extern void __libc_init_array(void);
/* Add This for C++ support */
// __libc_init_array();
#endif
// force SP align to 8 byte not 4 byte (initial SP is 4 byte align)
__asm(
"mov r0, sp\n"
"bic r0, r0, #7\n"
"mov sp, r0\n"
);
mpu_init();
app_mpu_nocache_init();
app_vdd1833_detect();
memcpy_gdma_init();
//retention Ram space should not exceed 0xB0
assert_param(sizeof(RRAM_TypeDef) <= 0xB0);
main(); /* project/xxxx/src/main.c */
#if defined ( __ICCARM__ )
//__iar_cstart_call_ctors(NULL);
/* it is dummy code, but IAR linker need this */
__iar_data_init3();
#endif
}
IMAGE2_VALID_PATTEN_SECTION
const u8 RAM_IMG2_VALID_PATTEN[20] = {
'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff),
(FW_CHIP_VER),
(FW_BUS_TYPE),
(FW_INFO_RSV1),
(FW_INFO_RSV2),
(FW_INFO_RSV3),
(FW_INFO_RSV4)
};
IMAGE2_ENTRY_SECTION
RAM_START_FUNCTION Img2EntryFun0 = {
app_start,
NULL,//BOOT_RAM_WakeFromPG,
(u32)NewVectorTable
};
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_app_start.c
|
C
|
apache-2.0
| 10,041
|
/**
******************************************************************************
* @file rtl8721dhp_audio.c
* @author
* @version V1.0.0
* @date 2017-12-13
* @brief This file provides firmware functions to manage the following
* functionalities of the Audio codec peripheral:
* - SPORT Initialization
* - SPORT parameters management
* - Data transfers configuration
* - GDMA configuration
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
const AUDIO_DevTable AUDIO_DEV_TABLE[1] = {
{AUDIO_SPORT_DEV, GDMA_HANDSHAKE_INTERFACE_AUDIO_TX, GDMA_HANDSHAKE_INTERFACE_AUDIO_RX}, /*audio sport */
};
/**
* @brief Fills each SP_StructInit member with its default value.
* @param SP_StructInit: pointer to an SP_StructInit structure which will be
* initialized.
* @retval None
*/
void AUDIO_SP_StructInit(SP_InitTypeDef* SP_InitStruct)
{
SP_InitStruct->SP_WordLen = SP_WL_16;
SP_InitStruct->SP_DataFormat = SP_DF_I2S;
SP_InitStruct->SP_MonoStereo = SP_CH_STEREO;
SP_InitStruct->SP_SelRxCh = SP_RX_CH_LR;
}
/**
* @brief Initializes the AUDIO SPORT registers according to the specified parameters
* in SP_InitStruct.
* @param SPORTx: pointer to the base addr of AUDIO SPORT peripheral.
* @param SP_InitStruct: pointer to an SP_InitTypeDef structure that contains
* the configuration information for the specified AUDIO SPORT peripheral
* @note AUDIO SPORT has two clock sources, one is 98.304MHz, the other is 45.1584MHz.
* BIT_CTRL_CTLX_I2S_CLK_SRC can used to select the clock source.
* @retval None
*/
void AUDIO_SP_Init(AUDIO_SPORT_TypeDef* SPORTx, SP_InitTypeDef* SP_InitStruct)
{
u32 Tmp;
/* Check the parameters */
assert_param(IS_SP_WORD_LEN(SP_InitStruct->SP_WordLen));
assert_param(IS_SP_DATA_FMT(SP_InitStruct->SP_DataFormat));
assert_param(IS_SP_CHN_NUM(SP_InitStruct->SP_MonoStereo));
assert_param(IS_SP_SEL_RX_CH(SP_InitStruct->SP_SelRxCh));
/* Reset SPORT module */
SPORTx->SP_CTRLR0 |= SP_CTRLR0_RST;
SPORTx->SP_CTRLR0 &= ~ SP_CTRLR0_RST;
/* Configure parameters: BCLK = 16*16K */
SPORTx->SP_CLK_DIV = 0x271 | (0x10 << 16) | SP_CLK_MI_NI_UPDATE;
/* Configure parameters: disable RX, disable TX, AUDIO SPORT mode */
AUDIO_SP_TxStart(SPORTx, DISABLE);
AUDIO_SP_RxStart(SPORTx, DISABLE);
/* Configure parameters: data format, word length, channel number, etc */
Tmp = SPORTx->SP_CTRLR0;
Tmp &= ~(SP_CTRLR0_DATA_LEN_SEL |SP_CTRLR0_DATA_FORMAT_SEL | SP_CTRLR0_EN_I2S_MONO | SP_CTRLR0_SEL_I2S_RX_CH);
Tmp |= ((SP_InitStruct->SP_WordLen << 12) |
(SP_InitStruct->SP_DataFormat << 8) |
(SP_InitStruct->SP_MonoStereo << 11) |
(SP_InitStruct->SP_SelRxCh << 28));
SPORTx->SP_CTRLR0 = Tmp;
}
/**
* @brief Start or stop SPORT Tx.
* @param SPORTx: pointer to the base addr of AUDIO SPORT peripheral.
* @param NewState: new state of the SPORT Tx.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void AUDIO_SP_TxStart(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState)
{
if (NewState == ENABLE) {
SPORTx->SP_CTRLR0 &= ~ SP_CTRLR0_TX_DISABLE;
SPORTx->SP_CTRLR0 |= SP_CTRLR0_START_TX;
} else {
SPORTx->SP_CTRLR0 |= SP_CTRLR0_TX_DISABLE;
SPORTx->SP_CTRLR0 &= ~ SP_CTRLR0_START_TX;
}
}
/**
* @brief Start or stop SPORT Rx.
* @param SPORTx: pointer to the base addr of AUDIO SPORT peripheral.
* @param NewState: new state of the SPORT Rx.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void AUDIO_SP_RxStart(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState)
{
if (NewState == ENABLE) {
SPORTx->SP_CTRLR0 &= ~ SP_CTRLR0_RX_DISABLE;
SPORTx->SP_CTRLR0 |= SP_CTRLR0_START_RX;
} else {
SPORTx->SP_CTRLR0 |= SP_CTRLR0_RX_DISABLE;
SPORTx->SP_CTRLR0 &= ~ SP_CTRLR0_START_RX;
}
}
/**
* @brief SPORT Tx DMA request on or off.
* @param SPORTx: pointer to the base addr of AUDIO SPORT peripheral.
* @param NewState: new state of the SPORT Tx DMA request.
* This parameter can be: ENABLE or DISABLE.
* @note If Tx DMA request is not enable, then should start Tx when GDMA complete every time.
* @retval None
*/
void AUDIO_SP_TdmaCmd(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState)
{
if (NewState == ENABLE) {
SPORTx->SP_CTRLR1 |= SP_CTRLR1_TDMA_REQ;
SPORTx->SP_DSP_INT_CR &= ~ SP_TX_DMA_SINGLE_NO_REQ;
} else {
SPORTx->SP_CTRLR1 &= ~ SP_CTRLR1_TDMA_REQ;
SPORTx->SP_DSP_INT_CR |= SP_TX_DMA_SINGLE_NO_REQ;
}
}
/**
* @brief SPORT Rx DMA request on or off.
* @param SPORTx: pointer to the base addr of AUDIO SPORT peripheral.
* @param NewState: new state of the SPORT Rx DMA request.
* This parameter can be: ENABLE or DISABLE.
* @note If Rx DMA request is not enable, then should start Rx when GDMA complete every time.
* @retval None
*/
void AUDIO_SP_RdmaCmd(AUDIO_SPORT_TypeDef* SPORTx, u32 NewState)
{
if (NewState == ENABLE) {
SPORTx->SP_CTRLR1 |= SP_CTRLR1_RDMA_REQ;
SPORTx->SP_DSP_INT_CR &= ~ SP_RX_DMA_SINGLE_NO_REQ;
} else {
SPORTx->SP_CTRLR1 &= ~ SP_CTRLR1_RDMA_REQ;
SPORTx->SP_DSP_INT_CR |= SP_RX_DMA_SINGLE_NO_REQ;
}
}
/**
* @brief Set the AUDIO SPORT word length.
* @param SPORTx: pointer to the base addr of AUDIO SPORT peripheral.
* @param SP_WordLen: the value of word length.
* This parameter can be one of the following values:
* @arg SP_WL_16: sample bit is 16 bit
* @arg SP_WL_24: sample bit is 24 bit
* @arg SP_WL_8: sample bit is 8 bit
* @retval None
*/
void AUDIO_SP_SetWordLen(AUDIO_SPORT_TypeDef* SPORTx, u32 SP_WordLen)
{
u32 reg_value;
assert_param(IS_SP_WORD_LEN(SP_WordLen));
reg_value = SPORTx->SP_CTRLR0;
reg_value &= ~(SP_CTRLR0_DATA_LEN_SEL);
reg_value |= (SP_WordLen << 12);
SPORTx->SP_CTRLR0 = reg_value;
}
/**
* @brief Get AUDIO SPORT word length.
* @param SPORTx: pointer to the base addr of AUDIO SPORT peripheral.
* @retval the value of word length.
* @arg 0: sample bit is 16 bit
* @arg 2: sample bit is 24 bit
* @arg 3: sample bit is 8 bit
*/
u32 AUDIO_SP_GetWordLen(AUDIO_SPORT_TypeDef* SPORTx)
{
u32 len = ((SPORTx->SP_CTRLR0) & SP_CTRLR0_DATA_LEN_SEL) >> 12;
return len;
}
/**
* @brief Set the AUDIO SPORT channel number.
* @param SPORTx: pointer to the base addr of AUDIO SPORT peripheral.
* @param SP_MonoStereo: mono or stereo.
* This parameter can be one of the following values:
* @arg SP_CH_STEREO: stereo channel, channel number is 2
* @arg SP_CH_MONO: mono channel, channel number is 1
* @retval None
*/
void AUDIO_SP_SetMonoStereo(AUDIO_SPORT_TypeDef* SPORTx, u32 SP_MonoStereo)
{
u32 reg_value;
assert_param(IS_SP_CHN_NUM(SP_MonoStereo));
reg_value = SPORTx->SP_CTRLR0;
reg_value &= ~(SP_CTRLR0_EN_I2S_MONO);
reg_value |= (SP_MonoStereo << 11);
SPORTx->SP_CTRLR0 = reg_value;
}
/**
* @brief Initialize GDMA peripheral for sending data.
* @param Index: 0.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pTxData: Tx Buffer.
* @param Length: Tx Count.
* @retval TRUE/FLASE
*/
BOOL AUDIO_SP_TXGDMA_Init(
u32 Index,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pTxData,
u32 Length
)
{
u8 GdmaChnl;
AUDIO_SPORT_TypeDef *SPORTx = AUDIO_DEV_TABLE[Index].SPORTx;
u32 WordLen = AUDIO_SP_GetWordLen(SPORTx);
assert_param(GDMA_InitStruct != NULL);
/*obtain a DMA channel and register DMA interrupt handler*/
GdmaChnl = GDMA_ChnlAlloc(0, CallbackFunc, (u32)CallbackData, 12);
if (GdmaChnl == 0xFF) {
// No Available DMA channel
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
/*set GDMA initial structure member value*/
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_InitStruct->GDMA_DIR = TTFCMemToPeri;
GDMA_InitStruct->GDMA_DstHandshakeInterface = AUDIO_DEV_TABLE[Index].Tx_HandshakeInterface;
GDMA_InitStruct->GDMA_DstAddr = (u32)&AUDIO_DEV_TABLE[Index].SPORTx->SP_TX_DR;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_DstInc = NoChange;
GDMA_InitStruct->GDMA_SrcInc = IncType;
/* Cofigure GDMA transfer */
if (WordLen == SP_WL_8) {
/* 8bits mode */
if (((Length & 0x03)==0) && (((u32)(pTxData) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeOne;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 2;
} else {
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_BlockSize = Length;
}
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
} else {
/* 24bits or 16bits mode */
if (((Length & 0x03)==0) && (((u32)(pTxData) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 2;
} else if (((Length & 0x01)==0) && (((u32)(pTxData) & 0x01)==0)) {
/* 2-bytes aligned, move 2 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeEight;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 1;
} else {
DBG_8195A("AUDIO_SP_TXGDMA_Init: Aligment Err: pTxData=0x%x, Length=%d\n", pTxData, Length);
return _FALSE;
}
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
}
/*check GDMA block size*/
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
/*configure GDMA source address */
GDMA_InitStruct->GDMA_SrcAddr = (u32)pTxData;
/* Enable GDMA for TX */
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
DCache_CleanInvalidate((u32)pTxData, Length);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Initialize GDMA peripheral for receiving data.
* @param Index: 0.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pRxData: Rx Buffer.
* @param Length: Rx Count.
* @retval TRUE/FLASE
*/
BOOL AUDIO_SP_RXGDMA_Init(
u32 Index,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pRxData,
u32 Length
)
{
u8 GdmaChnl;
AUDIO_SPORT_TypeDef *SPORTx = AUDIO_DEV_TABLE[Index].SPORTx;
u32 WordLen = AUDIO_SP_GetWordLen(SPORTx);
assert_param(GDMA_InitStruct != NULL);
/*obtain a DMA channel and register DMA interrupt handler*/
GdmaChnl = GDMA_ChnlAlloc(0, CallbackFunc, (u32)CallbackData, 12);
if (GdmaChnl == 0xFF) {
// No Available DMA channel
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
/*set GDMA initial structure member value*/
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem;
GDMA_InitStruct->GDMA_SrcHandshakeInterface = AUDIO_DEV_TABLE[Index].Rx_HandshakeInterface;
GDMA_InitStruct->GDMA_SrcAddr = (u32)&AUDIO_DEV_TABLE[Index].SPORTx->SP_RX_DR;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_DstInc = IncType;
GDMA_InitStruct->GDMA_SrcInc = NoChange;
/* Cofigure GDMA transfer */
if (WordLen == SP_WL_8) {
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstMsize = MsizeOne;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_BlockSize = Length;
} else {
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_SrcMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 2;
}
/*check GDMA block size*/
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
/*configure GDMA destination address */
GDMA_InitStruct->GDMA_DstAddr = (u32)pRxData;
/* Enable GDMA for RX */
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
DCache_CleanInvalidate((u32)pRxData, Length);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Audio GDMA Tx restart in isr
* @param GDMA_Index: GDMA index used in this routine.
* @param GDMA_ChNum: GDMA channel number used in this routine.
* @param tx_addr: Address of data to be sent.
* @param tx_length: Length of data to be sent.
* @retval TRUE
*/
BOOL AUDIO_SP_TXGDMA_Restart(
u8 GDMA_Index,
u8 GDMA_ChNum,
u32 tx_addr,
u32 tx_length
)
{
GDMA_SetSrcAddr(GDMA_Index, GDMA_ChNum, tx_addr);
GDMA_SetBlkSize(GDMA_Index, GDMA_ChNum, tx_length>>2);
DCache_CleanInvalidate(tx_addr, tx_length);
GDMA_Cmd(GDMA_Index, GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Audio GDMA Rx restart in isr
* @param GDMA_Index: GDMA index used in this routine.
* @param GDMA_ChNum: GDMA channel number used in this routine.
* @param tx_addr: Address of data to be received.
* @param tx_length: Length of data to be received.
* @retval TRUE
*/
BOOL AUDIO_SP_RXGDMA_Restart(
u8 GDMA_Index,
u8 GDMA_ChNum,
u32 rx_addr,
u32 rx_length
)
{
GDMA_SetDstAddr(GDMA_Index, GDMA_ChNum, rx_addr);
GDMA_SetBlkSize(GDMA_Index, GDMA_ChNum, rx_length>>2);
DCache_CleanInvalidate(rx_addr, rx_length);
GDMA_Cmd(GDMA_Index, GDMA_ChNum, ENABLE);
return _TRUE;
}
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_audio.c
|
C
|
apache-2.0
| 14,718
|
/**
******************************************************************************
* @file rtl8721dhp_clk.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware rom patch functions to manage clk
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief Configure NCO 2M Clock
* @param clk_out_Hz: the NCO output clock(unit: Hz).
* @note [14:0]: expected frequency of nco output clk, unit is 1KHz
* @note [16]: function enable
* @retval none
*/
void NCO2M_Init(u32 clk_out_Hz)
{
u32 Temp;
u32 clk_out = clk_out_Hz / 1000;
/* Check the parameters */
assert_param((clk_out > 0 && clk_out <= 0x7FFF));
/*disable the NCO clock and configure NCO output clock*/
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_UART_XTAL_DIV_CTRL);
Temp &= (~(BIT_LSYS_UART_XTAL_DIV_EN |BIT_LSYS_MASK_UART_XTAL_DIV_FREQ));
Temp |= clk_out;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_UART_XTAL_DIV_CTRL, Temp);
}
/**
* @brief enable or disable the NCO2M Clock
* @param NewState: the new state of the NCO 2M clock.
* This parameter can be: ENABLE or DISABLE.
* @retval none
*/
void NCO2M_Cmd(u32 NewState)
{
u32 Temp;
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_UART_XTAL_DIV_CTRL);
if(NewState != DISABLE) {
/*enable XTAL division circuit for UART*/
Temp |= BIT_LSYS_UART_XTAL_DIV_EN;
} else {
/*disable XTAL division circuit for UART*/
Temp &= (~BIT_LSYS_UART_XTAL_DIV_EN);
}
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_UART_XTAL_DIV_CTRL, Temp);
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_clk.c
|
C
|
apache-2.0
| 2,040
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "ameba_soc.h"
#if (defined(CONFIG_CP))
BOOT_RAM_TEXT_SECTION
VOID CPTest_GPIOCtrl(u32 GPIO_Pin, u32 Val)
{
GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.GPIO_Pin = GPIO_Pin;
GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(&GPIO_InitStruct);
GPIO_WriteBit(GPIO_Pin, Val);
}
BOOT_RAM_TEXT_SECTION
VOID CPTest_Init(VOID)
{
BKUP_Write(BKUP_REG2, 0x00);
CPTest_GPIOCtrl(_PA_0, 0);
CPTest_GPIOCtrl(_PA_1, 0);
CPTest_GPIOCtrl(_PA_2, 0);
CPTest_GPIOCtrl(_PA_3, 0);
CPTest_GPIOCtrl(_PA_4, 0);
CPTest_GPIOCtrl(_PA_5, 0);
CPTest_GPIOCtrl(_PA_16, 0);
DelayUs(1000);
BKUP_Write(BKUP_REG2, 0x01);
GPIO_WriteBit(_PA_0, 1);
}
BOOT_RAM_TEXT_SECTION
VOID CPTest_FlashCalibrationOk(VOID)
{
BKUP_Write(BKUP_REG2, 0x03);
GPIO_WriteBit(_PA_1, 1);
}
BOOT_RAM_TEXT_SECTION
VOID CPTest_EnterImg2Ok(VOID)
{
BKUP_Write(BKUP_REG2, 0x07);
GPIO_WriteBit(_PA_2, 1);
}
BOOT_RAM_TEXT_SECTION
void CPTest_UARTInit(u8 uart_idx, u8 pin_mux, u32 baud_rate)
{
UART_InitTypeDef UART_InitStruct;
switch (uart_idx) {
case 0:
RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
PinCtrl(PERIPHERAL_UART0, pin_mux, ON);
break;
case 1:
RCC_PeriphClockCmd(APBPeriph_UART1, APBPeriph_UART1_CLOCK, ENABLE);
PinCtrl(PERIPHERAL_UART1, pin_mux, ON);
break;
case 2:
/* UART2 is LogUART */
RCC_PeriphClockCmd(APBPeriph_LOGUART, APBPeriph_LOGUART_CLOCK, ENABLE);
PinCtrl(PERIPHERAL_LOG_UART, pin_mux, ON);
break;
default:
return;
}
UART_StructInit(&UART_InitStruct);
UART_InitStruct.DmaModeCtrl = DISABLE;
UART_InitStruct.WordLen = RUART_WLS_8BITS;
UART_InitStruct.StopBit = RUART_STOP_BIT_1; // word length select: 0 -> no stop bit, 1 -> 1 stop bit
UART_InitStruct.Parity = DISABLE; // parity check enable
UART_InitStruct.ParityType = RUART_ODD_PARITY;
UART_InitStruct.StickParity = DISABLE;
UART_InitStruct.FlowControl = DISABLE;
UART_InitStruct.RxFifoTrigLevel = UART_RX_FIFOTRIG_LEVEL_1BYTES;
UART_InitStruct.RxErReportCtrl = UART_RX_EEROR_REPORT_ENABLE;
UART_Init(UART_DEV_TABLE[uart_idx].UARTx, &UART_InitStruct);
UART_SetBaud(UART_DEV_TABLE[uart_idx].UARTx, baud_rate);
UART_INTConfig(UART_DEV_TABLE[uart_idx].UARTx, RUART_IER_ERBI | RUART_IER_ELSI, DISABLE);
UART_RxCmd(UART_DEV_TABLE[uart_idx].UARTx, ENABLE);
}
BOOT_RAM_TEXT_SECTION
static VOID CPTest_UART(VOID)
{
char rx_char = 0;
u32 timeout = 10000;
CPTest_UARTInit(1, S0, 1500000);
CPTest_UARTInit(0, S1, 1500000);
BKUP_Write(BKUP_REG2, 0x1F);
GPIO_WriteBit(_PA_4, 1);
/* clear UART 1 RX */
while (1) {
if (UART_Readable(UART1_DEV)) {
UART_CharGet(UART1_DEV, &rx_char);
} else {
break;
}
}
/* clear UART 0 RX */
while (1) {
if (UART_Readable(UART0_DEV)) {
UART_CharGet(UART0_DEV, &rx_char);
} else {
break;
}
}
rx_char = 0;
UART_CharPut(UART1_DEV, 0xAA);
do {
if (UART_Readable(UART0_DEV)) {
UART_CharGet(UART0_DEV, &rx_char);
break;
}
timeout--;
} while (timeout != 0);
if (rx_char == 0xAA) {
BKUP_Write(BKUP_REG2, 0x3F);
GPIO_WriteBit(_PA_5, 1);
}
}
BOOT_RAM_TEXT_SECTION
VOID CPTest_OSCCalibrationOk(VOID)
{
int i = 5;
BKUP_Write(BKUP_REG2, 0x0F);
GPIO_WriteBit(_PA_3, 1);
CPTest_UART();
if (BKUP_Read(BKUP_REG2) == 0x3F) {
while(i--){
GPIO_WriteBit(_PA_16, 1);
DelayUs(100);
GPIO_WriteBit(_PA_16, 0);
DelayUs(100);
}
}
DiagPrintf("\n");
DiagPrintf("<<<< >>>>\n");
DiagPrintf("<<<< Flash boot SUCCESS >>>>\n");
DiagPrintf("<<<< >>>>\n");
DiagPrintf("\n");
}
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_cpft.c
|
C
|
apache-2.0
| 3,881
|
/**
******************************************************************************
* @file rtl8721dhp_i2s.c
* @author
* @version V1.0.0
* @date 2017-11-03
* @brief This file provides firmware functions to manage the following
* functionalities of the Inter-IC Sound (I2S) peripheral:
* - Initialization and Deinitialization
* - Interrupts management
* - Data transfers configuration
* - Pinmux clock configuration
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
u32 i2s_page_num; /* page num: 2~4 */
u32 i2s_cur_tx_page; /* this is the dma page last time */
u32 i2s_cur_rx_page; /*I2S RX page index */
u32 i2s_txpage_entry[4]; /* The Tx DAM buffer: pointer of each page */
u32 i2s_rxpage_entry[4]; /* The Rx DAM buffer: pointer of each page */
/**
* @brief Fills each I2S_InitStruct member with its default value.
* @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure which will be
* initialized.
* @note I2S_InterLoopback parameter is only used for loopback test.
* @retval None
*/
void
I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
{
I2S_InitStruct->I2S_SlaveMode = I2S_MASTER_MODE;
I2S_InitStruct->I2S_WordLen = I2S_WL_16;
I2S_InitStruct->I2S_Justify = I2S_JY_I2S;
I2S_InitStruct->I2S_EndianSwap = I2S_ES_BIG;
I2S_InitStruct->I2S_ChNum = I2S_CH_STEREO;
I2S_InitStruct->I2S_PageNum = 4;
I2S_InitStruct->I2S_PageSize = (768/4);
I2S_InitStruct->I2S_Rate = I2S_SR_48KHZ;
I2S_InitStruct->I2S_TRxAct = I2S_TXRX;
I2S_InitStruct->I2S_InterLoopback = 0;
I2S_InitStruct->I2S_Mute = I2S_UNMUTE;
I2S_InitStruct->I2S_BurstSize = I2S_BURST_16;
I2S_InitStruct->I2S_SckSwap = I2S_SCK_NOINV;
I2S_InitStruct->I2S_WsSwap = I2S_WS_LEFT_PHA;
I2S_InitStruct->I2S_EdgeSwap = I2S_NEGATIVE_EDGE;
}
/**
* @brief Initializes the I2S registers according to the specified parameters
* in I2S_InitStruct.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that contains
* the configuration information for the specified I2S peripheral
* @note I2S has two clock sources, one is 98.304MHz, the other is 45.1584MHz.
* BIT_CTRL_CTLX_I2S_CLK_SRC can used to select the clock source.
* @retval None
*/
void
I2S_Init(
I2S_TypeDef* I2Sx, I2S_InitTypeDef* I2S_InitStruct
)
{
u32 Tmp;
/* Check the parameters */
assert_param(IS_I2S_WORD_LEN(I2S_InitStruct->I2S_WordLen));
assert_param(IS_I2S_JUSTIFY(I2S_InitStruct->I2S_Justify));
assert_param(IS_I2S_ENDIAN_SWAP(I2S_InitStruct->I2S_EndianSwap));
assert_param(IS_I2S_CHN_NUM(I2S_InitStruct->I2S_ChNum));
assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_SlaveMode));
assert_param(IS_I2S_DIR(I2S_InitStruct->I2S_TRxAct));
assert_param(IS_I2S_SAMPLE_RATE(I2S_InitStruct->I2S_Rate));
assert_param(IS_I2S_MUTE(I2S_InitStruct->I2S_Mute));
assert_param(IS_I2S_BST_NUM(I2S_InitStruct->I2S_BurstSize));
assert_param(IS_I2S_SCK_SWAP(I2S_InitStruct->I2S_SckSwap));
assert_param(IS_I2S_WS_SWAP(I2S_InitStruct->I2S_WsSwap));
assert_param(IS_I2S_EDGE_SWAP(I2S_InitStruct->I2S_EdgeSwap));
assert_param((I2S_InitStruct->I2S_PageNum >= 2) && (I2S_InitStruct->I2S_PageNum <= 4));
/* Disable the I2S first, and reset to default */
I2Sx->IS_CTL = BIT_CTRL_CTLX_I2S_SW_RSTN;
I2Sx->IS_CTL &= ~(BIT_CTRL_CTLX_I2S_SW_RSTN);
I2Sx->IS_CTL = BIT_CTRL_CTLX_I2S_SW_RSTN;
Tmp = I2Sx->IS_CTL;
Tmp |= ((I2S_InitStruct->I2S_WordLen << 29) |
(I2S_InitStruct->I2S_ChNum << 3) |
(I2S_InitStruct->I2S_SlaveMode << 28) |
(I2S_InitStruct->I2S_EndianSwap << 12) |
(I2S_InitStruct->I2S_InterLoopback << 7) |
(I2S_InitStruct->I2S_TRxAct << 1) |
(I2S_InitStruct->I2S_Mute << 27) |
(I2S_InitStruct->I2S_BurstSize << 18) |
(I2S_InitStruct->I2S_SckSwap << 11) |
(I2S_InitStruct->I2S_WsSwap << 10) |
(I2S_InitStruct->I2S_EdgeSwap << 5) |
(I2S_InitStruct->I2S_Justify << 8));
/* set mute, burst size, word length, channel number, master or slave, trx act */
I2Sx->IS_CTL = Tmp;
Tmp = (I2S_InitStruct->I2S_PageSize - 1) |
((I2S_InitStruct->I2S_PageNum - 1) << 12) |
(I2S_InitStruct->I2S_Rate << 14);
if (I2S_InitStruct->I2S_Rate & 0x10)
{
Tmp |= BIT_CTRL_CTLX_I2S_CLK_SRC;
}
/* set clock source, page size, page number, sample rate */
I2Sx->IS_SETTING = Tmp;
/* I2S Clear all interrupts first */
I2S_INTClearAll(I2Sx);
/* clear all dma own bit first */
I2S_TxDmaCmd(I2Sx, DISABLE);
I2S_RxDmaCmd(I2Sx, DISABLE);
/* I2S Disable all interrupts first */
I2S_INTConfig(I2Sx, 0, 0);
/* init current page */
i2s_cur_tx_page = 0;
i2s_cur_rx_page = 0;
i2s_page_num = I2S_InitStruct->I2S_PageNum;
}
/**
* @brief Enables or disables the specified I2S peripheral.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param NewState: new state of the I2Sx peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void
I2S_Cmd(
I2S_TypeDef* I2Sx,
u8 NewState
)
{
u32 Tmp;
Tmp = I2Sx->IS_CTL;
if (NewState == ENABLE)
Tmp |= (BIT_CTRL_CTLX_I2S_EN | BIT_CTRL_CTLX_I2S_SW_RSTN);
else
Tmp &= ~(BIT_CTRL_CTLX_I2S_EN | BIT_CTRL_CTLX_I2S_SW_RSTN);
I2Sx->IS_CTL = Tmp;
}
/**
* @brief Start or stop Tx DMA. When stop Tx DMA, clear DMA OWM bit.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param NewState: new state of the Tx DMA.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void
I2S_TxDmaCmd(I2S_TypeDef* I2Sx, u32 NewState)
{
u32 i;
u32 own = 0x00000000;
/* TX owned by CPU, We should set it to I2S when we I2S_TxPageDMA_EN */
if (NewState == DISABLE) {
own &= ~BIT_IS_PAGE_OWN;
} else {
own = BIT_IS_PAGE_OWN;
}
for (i = 0; i < 4; i++) {
I2Sx->IS_TX_PAGE_OWN[i] = own;
}
}
/**
* @brief Start or stop Rx DMA. When stop RX DMA, clear DMA OWM bit.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param NewState: new state of the Rx DMA.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void
I2S_RxDmaCmd(I2S_TypeDef* I2Sx, u32 NewState)
{
u32 i;
u32 own = 0x00000000;
/* RX owned by CPU, We should set it to I2S when we need recv */
if (NewState == DISABLE) {
own &= ~BIT_IS_PAGE_OWN;
} else {
own = BIT_IS_PAGE_OWN;
}
for (i = 0; i < 4; i++) {
I2Sx->IS_RX_PAGE_OWN[i] = own;
}
}
/**
* @brief Enables or disables the specified I2S interrupts.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2STxIntrMSK: specifies the I2S Tx interrupt to be enabled or disabled.
* This parameter can be one or combinations of the following values:
* @arg I2S_TX_INT_PAGE0_OK: Tx page0 OK interrupt
* @arg I2S_TX_INT_PAGE1_OK: Tx page1 OK interrupt
* @arg I2S_TX_INT_PAGE2_OK: Tx page2 OK interrupt
* @arg I2S_TX_INT_PAGE3_OK: Tx page3 OK interrupt
* @arg I2S_TX_INT_PAGE0_UNAVA: Tx page0 unavailable interrupt
* @arg I2S_TX_INT_PAGE1_UNAVA: Tx page1 unavailable interrupt
* @arg I2S_TX_INT_PAGE2_UNAVA: Tx page2 unavailable interrupt
* @arg I2S_TX_INT_PAGE3_UNAVA: Tx page3 unavailable interrupt
* @arg I2S_TX_INT_EMPTY: Tx FIFO empty interrupt
* @param I2SRxIntrMSK: specifies the I2S Rx interrupt to be enabled or disabled.
* This parameter can be one or combinations of the following values:
* @arg I2S_RX_INT_PAGE0_OK: Rx page0 OK interrupt
* @arg I2S_RX_INT_PAGE1_OK: Rx page1 OK interrupt
* @arg I2S_RX_INT_PAGE2_OK: Rx page2 OK interrupt
* @arg I2S_RX_INT_PAGE3_OK: Rx page3 OK interrupt
* @arg I2S_RX_INT_PAGE0_UNAVA: Rx page0 unavailable interrupt
* @arg I2S_RX_INT_PAGE1_UNAVA: Rx page1 unavailable interrupt
* @arg I2S_RX_INT_PAGE2_UNAVA: Rx page2 unavailable interrupt
* @arg I2S_RX_INT_PAGE3_UNAVA: Rx page3 unavailable interrupt
* @arg I2S_RX_INT_FULL: Rx FIFO full interrupt
* @retval None
*/
void
I2S_INTConfig(
I2S_TypeDef* I2Sx,
u32 I2STxIntrMSK,
u32 I2SRxIntrMSK
)
{
I2Sx->IS_TX_MASK_INT = I2STxIntrMSK;
I2Sx->IS_RX_MASK_INT = I2SRxIntrMSK;
}
/**
* @brief Clears the specified I2S interrupt pending bit.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2STxIntrClr: specifies the I2S Tx interrupt pending bit to clear.
* @param I2SRxIntrClr: specifies the I2S Rx interrupt pending bit to clear.
* @retval None
*/
void
I2S_INTClear(
I2S_TypeDef* I2Sx,
u32 I2STxIntrClr,
u32 I2SRxIntrClr
)
{
I2Sx->IS_TX_STATUS_INT = I2STxIntrClr;
I2Sx->IS_RX_STATUS_INT = I2SRxIntrClr;
}
/**
* @brief Clears all of the I2S interrupt pending bit.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @retval None
*/
void
I2S_INTClearAll(
I2S_TypeDef* I2Sx
)
{
I2Sx->IS_TX_STATUS_INT = 0x1ff;
I2Sx->IS_RX_STATUS_INT = 0x1ff;
}
/**
* @brief Get all of the I2S interrupt status.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2STxIsr: pointer to the I2S Tx interrupt status.
* @param I2SRxIsr: pointer to the I2S Rx interrupt status.
* @retval None
*/
void
I2S_ISRGet(
I2S_TypeDef* I2Sx,
u32* I2STxIsr,
u32* I2SRxIsr
)
{
*I2STxIsr = I2Sx->IS_TX_STATUS_INT;
*I2SRxIsr = I2Sx->IS_RX_STATUS_INT;
}
/**
* @brief Set the I2S sample rate.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2SRate: the value of sample rate.
* This parameter can be one of the following values:
* @arg I2S_SR_8KHZ: sample rate is 8kHz
* @arg I2S_SR_12KHZ: sample rate is 12kHz
* @arg I2S_SR_16KHZ: sample rate is 16kHz
* @arg I2S_SR_24KHZ: sample rate is 24kHz
* @arg I2S_SR_32KHZ: sample rate is 32kHz
* @arg I2S_SR_48KHZ: sample rate is 48kHz
* @arg I2S_SR_64KHZ: sample rate is 64kHz
* @arg I2S_SR_96KHZ: sample rate is 96kHz
* @arg I2S_SR_192KHZ: sample rate is 192kHz
* @arg I2S_SR_384KHZ: sample rate is 384kHz
* @arg I2S_SR_7p35KHZ: sample rate is 7.35kHz
* @arg I2S_SR_11p025KHZ: sample rate is 11.025kHz
* @arg I2S_SR_14p7KHZ: sample rate is 14.7kHz
* @arg I2S_SR_22p05KHZ: sample rate is 22.05kHz
* @arg I2S_SR_29p4KHZ: sample rate is 29.4kHz
* @arg I2S_SR_44p1KHZ: sample rate is 44.1kHz
* @arg I2S_SR_58p8KHZ: sample rate is 58.8kHz
* @arg I2S_SR_88p2KHZ: sample rate is 88.2kHz
* @arg I2S_SR_176p4KHZ: sample rate is 176.4kHz
* @retval None
*/
void
I2S_SetRate(
I2S_TypeDef* I2Sx, u32 I2S_Rate
)
{
u32 reg_value;
assert_param(IS_I2S_SAMPLE_RATE(I2S_Rate));
reg_value = I2Sx->IS_SETTING;
reg_value &= ~(BIT_SETTING_I2S_RATE_MASK | BIT_CTRL_CTLX_I2S_CLK_SRC);
if (I2S_Rate & 0x10)
{
reg_value |= BIT_CTRL_CTLX_I2S_CLK_SRC;
}
reg_value |= ((I2S_Rate << 14) & BIT_SETTING_I2S_RATE_MASK);
I2Sx->IS_SETTING = reg_value;
}
/**
* @brief Get I2S version ID .
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @retval The value of version ID.
*/
u32
I2S_GetVersion(
I2S_TypeDef* I2Sx
)
{
return I2Sx->IS_VERSION_ID;
}
/**
* @brief Set the I2S mute function.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param NewState: enable or disable mute function.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void
I2S_SetMute(
I2S_TypeDef* I2Sx, u32 NewState
)
{
u32 Tmp;
Tmp = I2Sx->IS_CTL;
if (NewState == ENABLE)
Tmp |= BIT_CTRL_CTLX_I2S_MUTE;
else
Tmp &= ~BIT_CTRL_CTLX_I2S_MUTE;
I2Sx->IS_CTL = Tmp;
}
/**
* @brief Set the I2S burst size.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2S_BurstSize: the value of burst size.
* This parameter can be one of the following values:
* @arg I2S_BURST_4: sample bit is 16 byte
* @arg I2S_BURST_8: sample bit is 32 byte
* @arg I2S_BURST_12: sample bit is 48 byte
* @arg I2S_BURST_16: burst size is 64 byte
* @retval None
*/
void
I2S_SetBurstSize(
I2S_TypeDef* I2Sx, u32 I2S_BurstSize
)
{
u32 reg_value;
assert_param(IS_I2S_BST_NUM(I2S_BurstSize));
reg_value = I2Sx->IS_CTL;
reg_value &= ~(BIT_CTRL_CTLX_I2S_BURST_SIZE_MASK);
reg_value |= (I2S_BurstSize << 18);
I2Sx->IS_CTL = reg_value;
}
/**
* @brief Set the I2S word length.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2SWordLen: the value of word length.
* This parameter can be one of the following values:
* @arg I2S_WL_16: sample bit is 16 bit
* @arg I2S_WL_24: sample bit is 24 bit
* @arg I2S_WL_32: sample bit is 32 bit
* @retval None
*/
void
I2S_SetWordLen(
I2S_TypeDef* I2Sx, u32 I2S_WordLen
)
{
u32 reg_value;
assert_param(IS_I2S_WORD_LEN(I2S_WordLen));
reg_value = I2Sx->IS_CTL;
reg_value &= ~(BIT_CTRL_CTLX_I2S_WORD_LEN_MASK);
reg_value |= (I2S_WordLen << 29);
I2Sx->IS_CTL = reg_value;
}
/**
* @brief Set the I2S channel number.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2SChNum: the value of channel number.
* This parameter can be one of the following values:
* @arg I2S_CH_STEREO: stereo channel, channel number is 2
* @arg I2S_CH_MONO: mono channel, channel number is 1
* @arg I2S_CH_5p1: 5.1 channel, channel number is 3
* @retval None
*/
void
I2S_SetChNum(
I2S_TypeDef* I2Sx, u32 I2S_ChNum
)
{
u32 reg_value;
assert_param(IS_I2S_CHN_NUM(I2S_ChNum));
reg_value = I2Sx->IS_CTL;
reg_value &= ~(BIT_CTRL_CTLX_I2S_CHN_NUM_MASK);
reg_value |= (I2S_ChNum << 3);
I2Sx->IS_CTL = reg_value;
}
/**
* @brief Set the I2S page number.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2SPageNum: the value of page number.
* This parameter can be one of the following values:
* @arg 2: two pages
* @arg 3: three pages
* @arg 4: four pages
* @retval None
*/
void
I2S_SetPageNum(
I2S_TypeDef* I2Sx, u32 I2S_PageNum
)
{
u32 reg_value;
assert_param((I2S_PageNum >= 2) && (I2S_PageNum <= 4));
reg_value = I2Sx->IS_SETTING;
reg_value &= ~(BIT_SETTING_I2S_PAGE_NUM_MASK);
reg_value |= ((I2S_PageNum - 1) << 12);
I2Sx->IS_SETTING = reg_value;
i2s_page_num = I2S_PageNum;
}
/**
* @brief Set the I2S page size.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2SPageSize: the value of page size.
* This parameter must be set to a value in the 1~4096 Word range
* @note I2S page size in unit of word
* @retval None
*/
void
I2S_SetPageSize(
I2S_TypeDef* I2Sx, u32 I2S_PageSize
)
{
u32 reg_value;
reg_value = I2Sx->IS_SETTING;
reg_value &= ~(BIT_SETTING_I2S_PAGE_SIZE_MASK);
reg_value |= (I2S_PageSize - 1);
I2Sx->IS_SETTING = reg_value;
}
/**
* @brief Get the I2S page size.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @note I2S page size in unit of word
* @retval the value of page size, 1~4096
*/
u32
I2S_GetPageSize(
I2S_TypeDef* I2Sx
)
{
u32 reg_value;
reg_value = I2Sx->IS_SETTING;
reg_value &= (BIT_SETTING_I2S_PAGE_SIZE_MASK);
reg_value += 1;
return reg_value;
}
/**
* @brief Set the I2S data transfer direction.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2STRxAct: specifies the data transfer direction.
* This parameter can be one of the following values:
* @arg I2S_ONLY_RX: Selects Rx receive direction
* @arg I2S_ONLY_TX: Selects Tx transmission direction
* @arg I2S_TXRX: Selects Tx & Rx bi-direction
* @retval None
*/
void
I2S_SetDirection(
I2S_TypeDef* I2Sx, u32 I2S_TRxAct
)
{
u32 reg_value;
assert_param(IS_I2S_DIR(I2S_TRxAct));
reg_value = I2Sx->IS_CTL;
reg_value &= ~(BIT_CTRL_CTLX_I2S_TX_ACT_MASK);
reg_value |= (I2S_TRxAct << 1);
I2Sx->IS_CTL = reg_value;
}
/**
* @brief Set tx&rx page start address and initialize page own.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2STxData: pointer to the start address of Tx page.
* @param I2SRxData: pointer to the start address of Rx page.
* @retval None
*/
void
I2S_SetDMABuf(
I2S_TypeDef* I2Sx,
u8 *I2STxData,
u8 *I2SRxData
)
{
if (I2STxData) {
I2Sx->IS_TX_PAGE_PTR = (u32)I2STxData;
/* TX owned by CPU, We should set it to I2S when we I2S_TxPageDMA_EN */
I2S_TxDmaCmd(I2Sx, DISABLE);
}
if (I2SRxData) {
I2Sx->IS_RX_PAGE_PTR = (u32)I2SRxData;
/* RX owned by i2s, we should set it to CPU when we recv Rx interrupt */
I2S_RxDmaCmd(I2Sx, ENABLE);
}
}
/**
* @brief Check tx page is own by CPU or I2S.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param page_index: specifies page index.
* @retval The state of page own
* - 0: tx page is own by CPU
* - 1: tx page is own by I2S
*/
u32
I2S_TxPageBusy(
I2S_TypeDef* I2Sx,
u32 page_index
)
{
u32 reg;
reg = I2Sx->IS_TX_PAGE_OWN[page_index];
if ((reg & (1<<31)) == 0) { //zero is by CPU
return 0;
} else {
return 1;
}
}
/**
* @brief Get current tx page .
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @retval The value of current tx page
*/
u32
I2S_GetTxPage(
I2S_TypeDef* I2Sx
)
{
/* To avoid gcc warnings */
( void ) I2Sx;
return i2s_cur_tx_page;
}
/**
* @brief Get current rx page .
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @retval The value of current rx page
*/
u32
I2S_GetRxPage(
I2S_TypeDef* I2Sx
)
{
/* To avoid gcc warnings */
( void ) I2Sx;
return i2s_cur_rx_page;
}
/**
* @brief Set the address of specified tx page.
* @param page_index: specifies tx page index.
* @param page_address: the address set to tx page.
* @retval None
*/
void
I2S_SetTxPageAddr(
u32 page_index,
u32 page_address
)
{
i2s_txpage_entry[page_index] = page_address;
}
/**
* @brief Get the address of specified tx page.
* @param page_index: specifies tx page index.
* @retval Address of the specified tx page
*/
u32
I2S_GetTxPageAddr(
u32 page_index
)
{
return i2s_txpage_entry[page_index];
}
/**
* @brief Set the address of specified rx page.
* @param page_index: specifies rx page index.
* @param page_address: the address set to rx page.
* @retval None
*/
void
I2S_SetRxPageAddr(
u32 page_index,
u32 page_address
)
{
i2s_rxpage_entry[page_index] = page_address;
}
/**
* @brief Get the address of specified rx page.
* @param page_index: specifies rx page index.
* @retval Address of the specified rx page
*/
u32
I2S_GetRxPageAddr(
u32 page_index
)
{
return i2s_rxpage_entry[page_index];
}
/**
* @brief set i2s_cur_tx_page own by i2s.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2STxIdx: specifies tx current page index.
* @retval None
* @note i2s_cur_tx_page index is managed by this function
* @note i2s_cur_tx_page++ in this function
* @note you should check txpage busy use I2S_TxPageBusy before this function
*/
void
I2S_TxPageDMA_EN(
I2S_TypeDef* I2Sx,
u32 I2STxIdx
)
{
u32 I2STxIdxTmp = I2STxIdx;
I2Sx->IS_TX_PAGE_OWN[I2STxIdxTmp] = (1<<31);
I2STxIdxTmp++;
if (I2STxIdxTmp == i2s_page_num) {
I2STxIdxTmp = 0;
}
i2s_cur_tx_page = I2STxIdxTmp;
}
/**
* @brief set i2s_cur_rx_page own by i2s.
* @param I2Sx: pointer to the base addr of I2S peripheral.
* @param I2SRxIdx: specifies rx current page index.
* @retval None
* @note i2s_cur_rx_page index is managed by this function
* @note i2s_cur_rx_page++ in this function
*/
void
I2S_RxPageDMA_EN(
I2S_TypeDef* I2Sx,
u32 I2SRxIdx
)
{
u32 I2SRxIdxTmp = I2SRxIdx;
u32 reg;
reg = I2Sx->IS_RX_PAGE_OWN[I2SRxIdxTmp];
if ((reg & (1<<31)) != 0) {
DBG_8195A("I2S_RxPageDMA_EN: No Idle Rx Page\r\n");
return;
}
I2Sx->IS_RX_PAGE_OWN[I2SRxIdxTmp] = (1 <<31);
I2SRxIdxTmp++;
if (I2SRxIdxTmp == i2s_page_num) {
I2SRxIdxTmp = 0;
}
i2s_cur_rx_page = I2SRxIdxTmp;
}
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_i2s.c
|
C
|
apache-2.0
| 20,689
|
/**
******************************************************************************
* @file rtl8721dhp_lcdc.c
* @author
* @version V1.0.0
* @date 2017-08-14
* @brief This file contains all the functions prototypes for the LCDC firmware
* library, including the following functionalities of LCD controller:
* - MCU I/F Initialization
* - TE mode configuration in MCU I/F mode
* - VSYNC mode configuration in MCU I/F mode
* - trigger DMA mode configuration in MCU I/F mode
* - write/read data through MCU I/F in IO mode
* - write command through MCU I/F in IO mode
* - RGB I/F Initialization
* - RGB I/F configuration for DE mode
* - RGB I/F configuration for HV mode
* - Synchronization status acquisition in RGB I/F mode
* - LED I/F Initialization
* - Color channel and color numbers configuration in LED I/F mode
* - Timing configuration in LED I/F mode
* - OE active width configuration in LED I/F mode
* - LCDC DMA configurations
* - Interrupts and flags management
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
#include "rtl8721d_lcdc.h"
/*-----------------------------------------------MCU I/F functions----------------------------------------------------*/
/**
* @brief Fills each LCDC_MCUInitStruct member with its default value.
* @param LCDC_MCUInitStruct: pointer to an LCDC_MCUInitTypeDef structure which will be initialized.
* @retval None
*/
void LCDC_MCUStructInit(LCDC_MCUInitTypeDef* LCDC_MCUInitStruct)
{
/* LCDC_MCUInitStruct members default value */
LCDC_MCUInitStruct->LCDC_MCUIfMode = LCDC_MCU_IF_16_BIT;
LCDC_MCUInitStruct->LCDC_MCUMode = LCDC_MCU_IO_MODE;
LCDC_MCUInitStruct->LCDC_MCUDMAMode = LCDC_AUTO_DMA_MODE;
LCDC_MCUInitStruct->LCDC_MCUImgHeight = 320;
LCDC_MCUInitStruct->LCDC_MCUImgWidth = 240;
LCDC_MCUInitStruct->LCDC_MCUSyncMode = LCDC_MCU_SYNC_WITH_INTERNAL_CLK;
LCDC_MCUInitStruct->LCDC_MCUVsyncPulPlrty = LCDC_MCU_VSYNC_PUL_LOW_LEV_ACTIVE;
LCDC_MCUInitStruct->LCDC_MCUTEPulPlrty = LCDC_MCU_TE_PUL_HIGH_LEV_ACTIVE;
LCDC_MCUInitStruct->LCDC_MCUTEDelay = 5;
LCDC_MCUInitStruct->LCDC_MCUDataPulPlrty = LCDC_MCU_DAT_PUL_NORMAL;
LCDC_MCUInitStruct->LCDC_MCURdPulPlrty = LCDC_MCU_RD_PUL_RISING_EDGE_FETCH;
LCDC_MCUInitStruct->LCDC_MCUWrPulPlrty = LCDC_MCU_WR_PUL_RISING_EDGE_FETCH;
LCDC_MCUInitStruct->LCDC_MCURsPulPlrty = LCDC_MCU_RS_PUL_LOW_LEV_CMD_ADDR;
LCDC_MCUInitStruct->LCDC_MCUCsPulPlrty = LCDC_MCU_CS_PUL_LOW_LEV_ACTIVE;
LCDC_MCUInitStruct->LCDC_MCUVsyncIdlePrd = 128;
LCDC_MCUInitStruct->LCDC_MCUVsyncSigWidth = 1;
LCDC_MCUInitStruct->LCDC_MCURdInacvWidth = 2;
LCDC_MCUInitStruct->LCDC_MCURdAcvWidth = 2;
LCDC_MCUInitStruct->LCDC_MCUWrPulWidth = 4;
LCDC_MCUInitStruct->LCDC_MCUIOTimeOutClkNum = 32;
}
/**
* @brief Initializes the LCDC peripheral according to the specified
* parameters in the LCDC_MCUInitStruct.
* @param LCDCx: where LCDCx can be LCDC.
* @param LCDC_MCUInitStruct: pointer to a LCDC_MCUInitTypeDef structure that contains
* the configuration information for the specified LCDC peripheral.
* @retval None
*/
void LCDC_MCUInit(LCDC_TypeDef* LCDCx, LCDC_MCUInitTypeDef* LCDC_MCUInitStruct)
{
/*variables for reading register*/
u32 McuCfgReg;
u32 McuSyncCfg;
u32 McuTimingCfg;
u32 DmaModeCfg;
u32 PlaneSize;
u32 LcdcCtrl;
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
assert_param(IS_LCDC_MCU_IF_MODE(LCDC_MCUInitStruct->LCDC_MCUIfMode));
assert_param(IS_LCDC_MCU_MODE(LCDC_MCUInitStruct->LCDC_MCUMode));
assert_param(IS_LCDC_DMA_MODE(LCDC_MCUInitStruct->LCDC_MCUDMAMode));
assert_param(IS_LCDC_MCU_SYNC_MODE(LCDC_MCUInitStruct->LCDC_MCUSyncMode));
assert_param(IS_LCDC_MCU_VSYNC_PUL_POLARITY(LCDC_MCUInitStruct->LCDC_MCUVsyncPulPlrty));
assert_param(IS_LCDC_MCU_TE_PUL_POLARITY(LCDC_MCUInitStruct->LCDC_MCUTEPulPlrty));
assert_param(IS_LCDC_MCU_DAT_PUL_POLARITY(LCDC_MCUInitStruct->LCDC_MCUDataPulPlrty));
assert_param(IS_LCDC_MCU_RD_PUL_POLARITY(LCDC_MCUInitStruct->LCDC_MCURdPulPlrty));
assert_param(IS_LCDC_MCU_WR_PUL_POLARITY(LCDC_MCUInitStruct->LCDC_MCUWrPulPlrty));
assert_param(IS_LCDC_MCU_RS_PUL_POLARITY(LCDC_MCUInitStruct->LCDC_MCURsPulPlrty));
assert_param(IS_LCDC_MCU_CS_PUL_POLARITY(LCDC_MCUInitStruct->LCDC_MCUCsPulPlrty));
assert_param((LCDC_MCUInitStruct->LCDC_MCUImgHeight <= 0xfff)&&(LCDC_MCUInitStruct->LCDC_MCUImgWidth <= 0xfff));
assert_param((LCDC_MCUInitStruct->LCDC_MCUTEDelay>=5) && (LCDC_MCUInitStruct->LCDC_MCUTEDelay<=65539));
assert_param((LCDC_MCUInitStruct->LCDC_MCUVsyncIdlePrd>=5) && (LCDC_MCUInitStruct->LCDC_MCUVsyncIdlePrd<=0x100000-5));
assert_param((LCDC_MCUInitStruct->LCDC_MCUVsyncSigWidth>=1) && (LCDC_MCUInitStruct->LCDC_MCUVsyncSigWidth<=0x100));
assert_param((LCDC_MCUInitStruct->LCDC_MCURdInacvWidth>=1) && (LCDC_MCUInitStruct->LCDC_MCURdInacvWidth<=0x800));
assert_param((LCDC_MCUInitStruct->LCDC_MCURdAcvWidth>=1) && (LCDC_MCUInitStruct->LCDC_MCURdAcvWidth<=0x800));
assert_param((LCDC_MCUInitStruct->LCDC_MCUWrPulWidth>=2)&&(LCDC_MCUInitStruct->LCDC_MCUWrPulWidth<=0x400));
assert_param(LCDC_MCUInitStruct->LCDC_MCUIOTimeOutClkNum<=0xffff);
/*disable LCDC befrore all operations*/
/*write 1 to LCDCINSDIS field in register LCDC_CTRL to disable LCDC instantly*/
LCDCx->LCDC_CTRL |= LCDC_CTRL_LCDCINSDIS;
/*read registers for configurartion*/
McuCfgReg = LCDCx->LCDC_MCU_CFG;
McuSyncCfg = LCDCx->LCDC_MCU_VSYNC_CFG;
McuTimingCfg = LCDCx->LCDC_MCU_TIMING_CFG;
DmaModeCfg = LCDCx->LCDC_DMA_MODE_CFG;
PlaneSize = LCDCx->LCDC_PLANE_SIZE;
LcdcCtrl = LCDCx->LCDC_CTRL;
/*IO mode*/
if(LCDC_MCUInitStruct->LCDC_MCUMode == LCDC_MCU_IO_MODE) {
/*if enable IO mode, the internal clock sychronization must be selected*/
assert_param(LCDC_MCUInitStruct->LCDC_MCUSyncMode == LCDC_MCU_SYNC_WITH_INTERNAL_CLK);
} else { /*DMA mode*/
/*trigger DMA mode*/
if(LCDC_MCUInitStruct->LCDC_MCUDMAMode == LCDC_TRIGGER_DMA_MODE) {
/*if enable trigger DMA mode, the internal clock sychronization must be selected*/
assert_param(LCDC_MCUInitStruct->LCDC_MCUSyncMode == LCDC_MCU_SYNC_WITH_INTERNAL_CLK || \
LCDC_MCUInitStruct->LCDC_MCUSyncMode == LCDC_MCU_SYNC_WITH_VSYNC);
} else {/*auto DMA mode*/
/*if auto DMA mode is enabled, VSYNC mode or TE mode must be selected*/
assert_param(LCDC_MCUInitStruct->LCDC_MCUSyncMode != LCDC_MCU_SYNC_WITH_INTERNAL_CLK);
/*Vsync mode*/
if(LCDC_MCUInitStruct->LCDC_MCUSyncMode == LCDC_MCU_SYNC_WITH_VSYNC) {
/*if MCU VSYNC mode is used, the VSYNC pulse polarity, VSYNC idle period, VSYNC signal width should be configured*/
/*VSYNC pulse polarity configuration*/
McuCfgReg &= (~LCDC_MCU_CFG_MCUSYPL);
McuCfgReg |= LCDC_MCUInitStruct->LCDC_MCUVsyncPulPlrty;
/*VSYNC idle period*/
McuSyncCfg &= (~LCDC_MCU_VSYNC_CFG_MCUVSPD);
McuSyncCfg |= ((LCDC_MCUInitStruct->LCDC_MCUVsyncIdlePrd-5)<<12);
/*VSYNC signal width*/
McuSyncCfg &= (~LCDC_MCU_VSYNC_CFG_MCUVSW);
McuSyncCfg |= (LCDC_MCUInitStruct->LCDC_MCUVsyncSigWidth-1);
} else {/*TE mode*/
/*if MCU TE mode is used, the TE delay interval, TE pulse polarity should be configured*/
/* TE delay interval configuration*/
McuCfgReg &= (~LCDC_MCU_CFG_IOMODE_TEDELAY);
McuCfgReg |= ((LCDC_MCUInitStruct->LCDC_MCUTEDelay-5)<<16);
/* TE pulse polarityl configuration*/
McuCfgReg &= (~LCDC_MCU_CFG_TEPL);
McuCfgReg |= (LCDC_MCUInitStruct->LCDC_MCUTEPulPlrty);
}
}
/*if MCU I/F DMA mode is used, the PLANE size should be configured*/
PlaneSize &= (~(LCDC_PLANE_SIZE_IMG_HEIGHT | LCDC_PLANE_SIZE_IMG_WIDTH));
PlaneSize |= LCDC_MCUInitStruct->LCDC_MCUImgWidth;
PlaneSize |= (LCDC_MCUInitStruct->LCDC_MCUImgHeight<<16);
}
/*configure MCU mode*/
McuCfgReg &= (~LCDC_MCU_CFG_IOMODE_EN);
McuCfgReg |= LCDC_MCUInitStruct->LCDC_MCUMode;
/*configure MCU sync mode*/
McuCfgReg &= (~LCDC_MCU_CFG_MCUSYNCMODE);
McuCfgReg |= LCDC_MCUInitStruct->LCDC_MCUSyncMode;
/*configure trigger mode or auto DMA*/
DmaModeCfg &= (~LCDC_DMA_MODE_CFG_TRIGGER_MODE);
DmaModeCfg |= LCDC_MCUInitStruct->LCDC_MCUDMAMode;
/*configure MCU I/F mode(8 bit or 16bit)*/
LcdcCtrl &= (~LCDC_CTRL_IF_MODE);
LcdcCtrl |= LCDC_MCUInitStruct->LCDC_MCUIfMode;
/*configure write, read, RS, CS, data pulse polarity*/
McuCfgReg &= (~(LCDC_MCU_CFG_CSPL|LCDC_MCU_CFG_RSPL|LCDC_MCU_CFG_WRPL|LCDC_MCU_CFG_RDPL|LCDC_MCU_CFG_DATAPL));
McuCfgReg |= LCDC_MCUInitStruct->LCDC_MCUCsPulPlrty;
McuCfgReg |= LCDC_MCUInitStruct->LCDC_MCURsPulPlrty;
McuCfgReg |= LCDC_MCUInitStruct->LCDC_MCUWrPulPlrty;
McuCfgReg |= LCDC_MCUInitStruct->LCDC_MCURdPulPlrty;
McuCfgReg |= LCDC_MCUInitStruct->LCDC_MCUDataPulPlrty;
/*WR/RD pulse width*/
McuTimingCfg &= (~(LCDC_MCU_TIMING_CFG_WRPULW|LCDC_MCU_TIMING_CFG_RDACTW|LCDC_MCU_TIMING_CFG_RDINACTW));
LCDC_MCUInitStruct->LCDC_MCUWrPulWidth &= (~0x01);
McuTimingCfg |= (LCDC_MCUInitStruct->LCDC_MCUWrPulWidth-2);
McuTimingCfg |= ((LCDC_MCUInitStruct->LCDC_MCURdAcvWidth-1)<<10);
McuTimingCfg |= ((LCDC_MCUInitStruct->LCDC_MCURdInacvWidth-1)<<21);
/*configure timeout clock number according to write/read clock*/
LCDC_MCUInitStruct->LCDC_MCUIOTimeOutClkNum = (LCDC_MCUInitStruct->LCDC_MCUWrPulWidth*16 + LCDC_MCUInitStruct->LCDC_MCURdAcvWidth + \
LCDC_MCUInitStruct->LCDC_MCURdInacvWidth);
/*configure IO write/read timeout clock number*/
LCDCx->LCDC_MCU_IO_TO_CFG &= (~LCDC_MCU_IO_TIMEOUT_CLK_NUM);
LCDCx->LCDC_MCU_IO_TO_CFG |= LCDC_MCUInitStruct->LCDC_MCUIOTimeOutClkNum;
/*write the value configured back to registers*/
LCDCx->LCDC_MCU_CFG = McuCfgReg;
LCDCx->LCDC_MCU_VSYNC_CFG = McuSyncCfg;
LCDCx->LCDC_MCU_TIMING_CFG = McuTimingCfg;
LCDCx->LCDC_DMA_MODE_CFG = DmaModeCfg;
LCDCx->LCDC_PLANE_SIZE = PlaneSize;
LCDCx->LCDC_CTRL = LcdcCtrl;
}
/**
* @brief Trigger the hardware to transfer one frame from DMA buffer based
* on sync signal.
* @param LCDCx: where LCDCx can be LCDC.
* @retval None
*/
void LCDC_MCUDMATrigger(LCDC_TypeDef* LCDCx)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*write 1 to TRIGER_ONETIME field in register LCDC_DMA_MODE_CFG*/
LCDCx->LCDC_DMA_MODE_CFG |= LCDC_DMA_MODE_CFG_TRIGGER_ONE_TIME;
}
/**
* @brief Get the MCU I/F IO mode run status.
* @param LCDCx: where LCDCx can be LCDC.
* @retval status value:
* - 1: IO mode run
* - 0: DMA mode run
*/
u32 LCDC_MCUGetRunStatus(LCDC_TypeDef* LCDCx)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*aquire the IO mode run status*/
if(LCDCx->LCDC_MCU_CFG & LCDC_MCU_CFG_IOMODE_RUN) {
return 1;
} else {
return 0;
}
}
/**
* @brief write data to MCU I/F bus.
* @param LCDCx: where LCDCx can be LCDC.
* @param Data: the data to transmit.
* @retval None
*/
void LCDC_MCUIOWriteData(LCDC_TypeDef* LCDCx, u16 Data)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*write data to tx fifo*/
LCDCx->LCDC_MCU_IO_DATA= ((u32)Data&LCDC_MCU_IO_WR_DAT_FG);
}
/**
* @brief read data from MCU I/F bus.
* @param LCDCx: where LCDCx can be LCDC.
* @retval the read value
*/
u16 LCDC_MCUIOReadData(LCDC_TypeDef* LCDCx)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*read data from bus*/
return (u16)LCDCx->LCDC_MCU_IO_DATA;
}
/**
* @brief write command to MCU I/F bus.
* @param LCDCx: where LCDCx can be LCDC.
* @param Cmd: the command to transmit.
* @retval None
*/
void LCDC_MCUIOWriteCmd(LCDC_TypeDef* LCDCx, u16 Cmd)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*write command to tx fifo*/
LCDCx->LCDC_MCU_IO_DATA = ((u32)Cmd|LCDC_MCU_IO_WR_CMD_FG);
}
/*--------------------------------------------RGB I/F functions-----------------------------------------------*/
/**
* @brief Fills each LCDC_RGBInitStruct member with its default value.
* @param LCDC_RGBInitStruct: pointer to an LCDC_RGBInitTypeDef structure which will be initialized.
* @retval None
*/
void LCDC_RGBStructInit(LCDC_RGBInitTypeDef * LCDC_RGBInitStruct)
{
/* LCDC_MCUInitStruct members default value */
LCDC_RGBInitStruct->LCDC_RGBIfMode = LCDC_RGB_IF_16_BIT;
LCDC_RGBInitStruct->LCDC_RGBImgHeight = 272;
LCDC_RGBInitStruct->LCDC_RGBImgWidth = 480;
LCDC_RGBInitStruct->LCDC_RGBRefreshFreq = 60;
LCDC_RGBInitStruct->LCDC_RGBSyncMode = LCDC_RGB_HV_MODE;
LCDC_RGBInitStruct->LCDC_RGBDatPulPlrty = LCDC_RGB_DAT_PUL_NORMAL;
LCDC_RGBInitStruct->LCDC_RGBEnPulPlrty = LCDC_RGB_EN_PUL_HIGH_LEV_ACTIVE;
LCDC_RGBInitStruct->LCDC_RGBHsPulPlrty = LCDC_RGB_HS_PUL_LOW_LEV_SYNC;
LCDC_RGBInitStruct->LCDC_RGBVsPulPlrty = LCDC_RGB_VS_PUL_LOW_LEV_SYNC;
LCDC_RGBInitStruct->LCDC_RGBDclkActvEdge = LCDC_RGB_DCLK_RISING_EDGE_FETCH;
LCDC_RGBInitStruct->LCDC_RGBVFP = 8;
LCDC_RGBInitStruct->LCDC_RGBVBP = 8;
LCDC_RGBInitStruct->LCDC_RGBVSW = 1;
LCDC_RGBInitStruct->LCDC_RGBHFP= 5;
LCDC_RGBInitStruct->LCDC_RGBHBP = 40;
LCDC_RGBInitStruct->LCDC_RGBHSW = 1;
}
/**
* @brief Initializes the LCDC peripheral according to the specified
* parameters in the LCDC_RGBInitStruct.
* @param LCDCx: where LCDCx can be LCDC.
* @param LCDC_RGBInitStruct: pointer to a LCDC_RGBInitTypeDef structure that contains
* the configuration information for the specified LCDC peripheral.
* @retval None
*/
void LCDC_RGBInit(LCDC_TypeDef* LCDCx, LCDC_RGBInitTypeDef* LCDC_RGBInitStruct)
{
/*variables for reading register*/
u32 RgbCfg;
u32 RgbVsyncCfg;
u32 RgbHsyncCfg;
u32 DmaModeCfg;
u32 PlaneSize;
u32 LcdcCtrl;
/*variables for calculating DCLK divider*/
u32 LcdcClkDiv;
u32 HDotNum;
u32 VLineNum;
u32 TempFreq;
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
assert_param(IS_LCDC_RGB_IF_MODE(LCDC_RGBInitStruct->LCDC_RGBIfMode));
assert_param(IS_LCDC_RGB_SYNC_MODE(LCDC_RGBInitStruct->LCDC_RGBSyncMode));
assert_param(IS_LCDC_RGB_DAT_PUL_POLARITY(LCDC_RGBInitStruct->LCDC_RGBDatPulPlrty));
assert_param(IS_LCDC_RGB_EN_PUL_POLARITY(LCDC_RGBInitStruct->LCDC_RGBEnPulPlrty));
assert_param(IS_LCDC_RGB_HS_PUL_POLARITY(LCDC_RGBInitStruct->LCDC_RGBHsPulPlrty));
assert_param(IS_LCDC_RGB_VS_PUL_POLARITY(LCDC_RGBInitStruct->LCDC_RGBVsPulPlrty));
assert_param(IS_LCDC_RGB_DCLK_EDGE(LCDC_RGBInitStruct->LCDC_RGBDclkActvEdge));
assert_param((LCDC_RGBInitStruct->LCDC_RGBImgHeight <= 0xfff)&&(LCDC_RGBInitStruct->LCDC_RGBImgWidth<=0xfff));
assert_param((LCDC_RGBInitStruct->LCDC_RGBVBP>=1)&&(LCDC_RGBInitStruct->LCDC_RGBVBP<=0x10));
assert_param((LCDC_RGBInitStruct->LCDC_RGBVFP>=1)&&(LCDC_RGBInitStruct->LCDC_RGBVFP<=0x10));
assert_param((LCDC_RGBInitStruct->LCDC_RGBVSW>=1)&&(LCDC_RGBInitStruct->LCDC_RGBVSW<=0x10));
assert_param((LCDC_RGBInitStruct->LCDC_RGBHFP>=1)&&(LCDC_RGBInitStruct->LCDC_RGBHFP<=0x100));
assert_param((LCDC_RGBInitStruct->LCDC_RGBHBP>=1)&&(LCDC_RGBInitStruct->LCDC_RGBHBP<=0x100));
assert_param((LCDC_RGBInitStruct->LCDC_RGBHSW>=1)&&(LCDC_RGBInitStruct->LCDC_RGBHSW<=0x100));
/*disable LCDC befrore all operations*/
/*write 1 to LCDCINSDIS field in register LCDC_CTRL to disable LCDC instantly*/
LCDCx->LCDC_CTRL |= LCDC_CTRL_LCDCINSDIS;
/*read registers for configurartion*/
RgbCfg = LCDCx->LCDC_RGB_CFG;
RgbVsyncCfg = LCDCx->LCDC_RGB_VSYNC_CFG;
RgbHsyncCfg = LCDCx->LCDC_RGB_HSYNC_CFG;
DmaModeCfg = LCDCx->LCDC_DMA_MODE_CFG;
PlaneSize = LCDCx->LCDC_PLANE_SIZE;
LcdcCtrl = LCDCx->LCDC_CTRL;
/*if the RGB DE mode is used, configure the DE pulse polarity*/
if(LCDC_RGBInitStruct->LCDC_RGBSyncMode == LCDC_RGB_DE_MODE) {
RgbCfg &= (~LCDC_RGB_CFG_ENPL);
RgbCfg |= LCDC_RGBInitStruct->LCDC_RGBEnPulPlrty;
}
/*configure RGB sync mode*/
RgbCfg &= (~LCDC_RGB_CFG_RGB_SYNC_MODE);
RgbCfg |= LCDC_RGBInitStruct->LCDC_RGBSyncMode;
/*configure plane size*/
PlaneSize &= (~(LCDC_PLANE_SIZE_IMG_HEIGHT | LCDC_PLANE_SIZE_IMG_WIDTH));
PlaneSize |= LCDC_RGBInitStruct->LCDC_RGBImgWidth;
PlaneSize |= (LCDC_RGBInitStruct->LCDC_RGBImgHeight<<16);
/*configure RGB I/F mode*/
LcdcCtrl &= (~LCDC_CTRL_IF_MODE);
LcdcCtrl |= LCDC_RGBInitStruct->LCDC_RGBIfMode;
/*configure RGB data, VSYNC, HSYNC pulse polarity and DCLK active edge*/
RgbCfg &= (~(LCDC_RGB_CFG_DATPL|LCDC_RGB_CFG_HSPL|LCDC_RGB_CFG_VSPL|LCDC_RGB_CFG_DCLKPL));
RgbCfg |= LCDC_RGBInitStruct->LCDC_RGBDatPulPlrty;
RgbCfg |= LCDC_RGBInitStruct->LCDC_RGBHsPulPlrty;
RgbCfg |= LCDC_RGBInitStruct->LCDC_RGBVsPulPlrty;;
RgbCfg |= LCDC_RGBInitStruct->LCDC_RGBDclkActvEdge;
/*configure vertical synchronization parameters: VFP, VBP, VSW*/
RgbVsyncCfg &= (~(LCDC_RGB_VSYNC_CFG_VSW|LCDC_RGB_VSYNC_CFG_VBP|LCDC_RGB_VSYNC_CFG_VFP));
RgbVsyncCfg |= (LCDC_RGBInitStruct->LCDC_RGBVSW-1);
RgbVsyncCfg |= ((LCDC_RGBInitStruct->LCDC_RGBVBP-1)<<8);
RgbVsyncCfg |= ((LCDC_RGBInitStruct->LCDC_RGBVFP-1)<<16);
/*configure horizontal synchronization parameters: HFP, HBP, HSW*/
RgbHsyncCfg &= (~(LCDC_RGB_HSYNC_CFG_HSW|LCDC_RGB_HSYNC_CFG_HBP|LCDC_RGB_HSYNC_CFG_HFP));
RgbHsyncCfg |= (LCDC_RGBInitStruct->LCDC_RGBHSW-1);
RgbHsyncCfg |= ((LCDC_RGBInitStruct->LCDC_RGBHBP-1)<<8);
RgbHsyncCfg |= ((LCDC_RGBInitStruct->LCDC_RGBHFP-1)<<16);
/*configure auto DMA mode; if LCDC RGB I/F mode is used, the auto DMA mode must be enabled*/
DmaModeCfg &= (~LCDC_DMA_MODE_CFG_TRIGGER_MODE);
DmaModeCfg |= LCDC_AUTO_DMA_MODE;
/*calculate the DCLK clock divider according to the plane size, refreh frequency and LCDC_SYS_CLK*/
HDotNum = LCDC_RGBInitStruct->LCDC_RGBImgWidth + LCDC_RGBInitStruct->LCDC_RGBHSW + LCDC_RGBInitStruct->LCDC_RGBHBP + \
LCDC_RGBInitStruct->LCDC_RGBHFP;
VLineNum = LCDC_RGBInitStruct->LCDC_RGBImgHeight + LCDC_RGBInitStruct->LCDC_RGBVSW + LCDC_RGBInitStruct->LCDC_RGBVBP + \
LCDC_RGBInitStruct->LCDC_RGBVFP;
/*if RGB 6bit mode is used, triple the DCLK number in each line*/
if(LCDC_RGBInitStruct->LCDC_RGBIfMode == LCDC_RGB_IF_6_BIT) {
HDotNum = 3*HDotNum;
}
/*calculate the actual divider*/
TempFreq = LCDC_RGBInitStruct->LCDC_RGBRefreshFreq*HDotNum*VLineNum;
if((LCDC_SYS_CLK % TempFreq) >= (TempFreq + 1) / 2){
LcdcClkDiv = LCDC_SYS_CLK / TempFreq + 1;
} else {
LcdcClkDiv = LCDC_SYS_CLK / TempFreq;
}
/*Because DCLK=SYS_CLK/(CLKDIV+2), the actual divider must be not less than 2 and not more than 65536*/
assert_param((LcdcClkDiv>=2)&&((LcdcClkDiv<=65536)));
/*ensure CLKDIV is a even value*/
if(LcdcClkDiv%2 != 0){
LcdcClkDiv = LcdcClkDiv - 1;
}
/*fill the CLKDIV field in the register LCDC_CLK_DIV*/
LCDCx->LCDC_CLK_DIV &= (~LCDC_CLK_DIV_DCLKDIV);
LCDCx->LCDC_CLK_DIV |= (LcdcClkDiv-2);
/*write the value configured back to registers*/
LCDCx->LCDC_RGB_CFG = RgbCfg;
LCDCx->LCDC_RGB_VSYNC_CFG = RgbVsyncCfg;
LCDCx->LCDC_RGB_HSYNC_CFG = RgbHsyncCfg;
LCDCx->LCDC_DMA_MODE_CFG = DmaModeCfg;
LCDCx->LCDC_PLANE_SIZE = PlaneSize;
LCDCx->LCDC_CTRL = LcdcCtrl;
}
/**
* @brief Get the RGB synchronization status.
* @param LCDCx: where LCDCx can be LCDC.
* @param pHSStatus: horizontal synchronization status pointer.
* HSStatus can be one of the following values:
* @arg LCDC_RGB_SYNC_STATUS_HSYNC: HSYNC
* @arg LCDC_RGB_SYNC_STATUS_HFP : HFP
* @arg LCDC_RGB_SYNC_STATUS_HACTIVE: ACTIVE
* @arg LCDC_RGB_SYNC_STATUS_HBP : HBP
* @param pVSStatus: vertical synchronization status pointer.
* VSStatus can be one of the following values:
* @arg LCDC_RGB_SYNC_STATUS_VSYNC: VSYNC
* @arg LCDC_RGB_SYNC_STATUS_VFP : VFP
* @arg LCDC_RGB_SYNC_STATUS_VACTIVE: ACTIVE
* @arg LCDC_RGB_SYNC_STATUS_VBP : VBP
* @retval None
*/
void LCDC_RGBGetSyncStatus(LCDC_TypeDef* LCDCx, u32 * pHSStatus, u32 * pVSStatus)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*Get horizontal synchronization status*/
*pHSStatus = (LCDCx->LCDC_RGB_SYNC_STATUS & LCDC_RGB_SYNC_STATUS_HSSTATUS);
/*Get vertical synchronization status*/
*pVSStatus = (LCDCx->LCDC_RGB_SYNC_STATUS & LCDC_RGB_SYNC_STATUS_VSSTATUS);
}
/*----------------------------------------------LED I/F functions---------------------------------------------*/
/**
* @brief Fills each LCDC_LEDInitStruct member with its default value.
* @param LCDC_LEDInitStruct: pointer to an LCDC_LEDInitTypeDef structure which will be initialized.
* @retval None
*/
void LCDC_LEDStructInit(LCDC_LEDInitTypeDef * LCDC_LEDInitStruct)
{
/* LCDC_MCUInitStruct members default value */
LCDC_LEDInitStruct->LCDC_LEDIfMode = LCDC_LED_IF;
LCDC_LEDInitStruct->LCDC_LEDImgHeight = 16;
LCDC_LEDInitStruct->LCDC_LEDImgWidth = 64;
LCDC_LEDInitStruct->LCDC_LEDRefreshFreq = 100;
LCDC_LEDInitStruct->LCDC_LEDColorChnl = LCDC_LED_ONE_CHANNEL;
LCDC_LEDInitStruct->LCDC_LEDColorNum = LCDC_LED_ONE_COLOR;
LCDC_LEDInitStruct->LCDC_LEDOEActw = 7;
LCDC_LEDInitStruct->LCDC_LEDLatchWidth = 2;
LCDC_LEDInitStruct->LCDC_LEDFrmIdlePd = 2;
LCDC_LEDInitStruct->LCDC_LEDClkPlrty = LCDC_LED_DCLK_RISING_EDGE_FETCH;
LCDC_LEDInitStruct->LCDC_LEDLatPlrty = LCDC_LED_LACTH_RISING_EDGE_FETCH;
LCDC_LEDInitStruct->LCDC_LEDOePlrty = LCDC_LED_OE_LOW_LEV_ACTIVE;
LCDC_LEDInitStruct->LCDC_LEDDatPlrty = LCDC_LED_DAT_PUL_NORMAL;
LCDC_LEDInitStruct->LCDC_LEDLineIdlePd = 1;
}
/**
* @brief Initializes the LCDC peripheral according to the specified
* parameters in the LCDC_LEDInitStruct.
* @param LCDCx: where LCDCx can be LCDC.
* @param LCDC_LEDInitStruct: pointer to a LCDC_LEDInitTypeDef structure that contains
* the configuration information for the specified LCDC peripheral.
* @retval None
*/
void LCDC_LEDInit(LCDC_TypeDef* LCDCx, LCDC_LEDInitTypeDef* LCDC_LEDInitStruct)
{
/*variables for reading register*/
u32 LedCfg;
u32 LedTiming;
u32 DmaModeCfg;
u32 PlaneSize;
u32 LcdcCtrl;
u32 LedIdle;
/*variables for calculating DCLK divider*/
u32 LcdcClkDiv;
u32 HDotNum;
u32 VLineNum;
u32 TempFreq;
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
assert_param(IS_LCDC_LED_IF_MODE(LCDC_LEDInitStruct->LCDC_LEDIfMode));
assert_param(IS_LCDC_LED_CHANNEL(LCDC_LEDInitStruct->LCDC_LEDColorChnl));
assert_param(IS_LCDC_LED_COLOR_NUM(LCDC_LEDInitStruct->LCDC_LEDColorNum));
assert_param(IS_LCDC_LED_DCLK_EDGE(LCDC_LEDInitStruct->LCDC_LEDClkPlrty));
assert_param(IS_LCDC_LED_LATCH_EDGE(LCDC_LEDInitStruct->LCDC_LEDLatPlrty));
assert_param(IS_LCDC_LED_OE_PUL_POLARITY(LCDC_LEDInitStruct->LCDC_LEDOePlrty));
assert_param(IS_LCDC_LED_DAT_PUL_POLARITY(LCDC_LEDInitStruct->LCDC_LEDDatPlrty));
assert_param((LCDC_LEDInitStruct->LCDC_LEDImgHeight <= 0xfff)&&(LCDC_LEDInitStruct->LCDC_LEDImgWidth <= 0xfff));
assert_param((LCDC_LEDInitStruct->LCDC_LEDOEActw >= 1) && (LCDC_LEDInitStruct->LCDC_LEDOEActw <= 0x10000));
assert_param((LCDC_LEDInitStruct->LCDC_LEDFrmIdlePd >= 1) && (LCDC_LEDInitStruct->LCDC_LEDFrmIdlePd <= 0x1000));
assert_param((LCDC_LEDInitStruct->LCDC_LEDLatchWidth >= 1) && (LCDC_LEDInitStruct->LCDC_LEDLatchWidth <= 0x100));
assert_param((LCDC_LEDInitStruct->LCDC_LEDLineIdlePd >= 1) && (LCDC_LEDInitStruct->LCDC_LEDLineIdlePd <= 0x100));
/*disable LCDC befrore all operations*/
/*write 1 to LCDCINSDIS field in register LCDC_CTRL to disable LCDC instantly*/
LCDCx->LCDC_CTRL |= LCDC_CTRL_LCDCINSDIS;
/*read register for configuration*/
LedCfg = LCDCx->LCDC_LED_CFG;
LedTiming = LCDCx->LCDC_LED_TIMING;
DmaModeCfg = LCDCx->LCDC_DMA_MODE_CFG;
PlaneSize = LCDCx->LCDC_PLANE_SIZE;
LcdcCtrl = LCDCx->LCDC_CTRL;
LedIdle = LCDCx->LCDC_LED_IDLE;
/*configure LED I/F mode*/
LcdcCtrl &= (~LCDC_CTRL_IF_MODE);
LcdcCtrl |= LCDC_LEDInitStruct->LCDC_LEDIfMode;
/*configure LED plane size*/
PlaneSize &= (~(LCDC_PLANE_SIZE_IMG_HEIGHT | LCDC_PLANE_SIZE_IMG_WIDTH));
PlaneSize |= LCDC_LEDInitStruct->LCDC_LEDImgWidth;
PlaneSize |= (LCDC_LEDInitStruct->LCDC_LEDImgHeight<<16);
/*configure color channel and color number*/
LedCfg &= (~(LCDC_LED_CFG_COLORNUM | LCDC_LED_CFG_COLORCHAN));
LedCfg |= LCDC_LEDInitStruct->LCDC_LEDColorNum;
LedCfg |= LCDC_LEDInitStruct->LCDC_LEDColorChnl;
/*configure LED I/F bus polarity*/
LedCfg &= (~(LCDC_LED_CFG_CLKPL|LCDC_LED_CFG_LATPL|LCDC_LED_CFG_OEPL|LCDC_LED_CFG_DATPL));
LedCfg |= LCDC_LEDInitStruct->LCDC_LEDClkPlrty;
LedCfg |= LCDC_LEDInitStruct->LCDC_LEDLatPlrty;
LedCfg |= LCDC_LEDInitStruct->LCDC_LEDOePlrty;
LedCfg |= LCDC_LEDInitStruct->LCDC_LEDDatPlrty;
/*configure LED I/F timing*/
LedTiming &= (~(LCDC_LED_TIMING_LATW | LCDC_LED_TIMING_OEACTW));
LedTiming |= LCDC_LEDInitStruct->LCDC_LEDLatchWidth-1;
LedTiming |= ((LCDC_LEDInitStruct->LCDC_LEDOEActw-1)<<8);
/*configure LED I/F line and frame idle timing*/
LedIdle &= (~(LCDC_LED_TIMING_LINEIDLE | LCDC_LED_TIMING_FRMIDLEPD));
LedIdle |= LCDC_LEDInitStruct->LCDC_LEDLineIdlePd-1;
LedIdle |= ((LCDC_LEDInitStruct->LCDC_LEDFrmIdlePd-1)<<20);
/*configure auto DMA mode, if LCDC LED I/F mode is used, the auto DMA mode must be enabled*/
DmaModeCfg &= (~LCDC_DMA_MODE_CFG_TRIGGER_MODE);
DmaModeCfg |= LCDC_AUTO_DMA_MODE;
HDotNum = LCDC_LEDInitStruct->LCDC_LEDImgWidth + LCDC_LEDInitStruct->LCDC_LEDLineIdlePd;
VLineNum = LCDC_LEDInitStruct->LCDC_LEDImgHeight;
if(LCDC_LEDInitStruct->LCDC_LEDColorChnl == LCDC_LED_TWO_CHANNEL) {
VLineNum = VLineNum/2;
}
TempFreq = (HDotNum*VLineNum+LCDC_LEDInitStruct->LCDC_LEDFrmIdlePd)*LCDC_LEDInitStruct->LCDC_LEDRefreshFreq;
/*calculate the actual divider*/
if((LCDC_SYS_CLK % TempFreq) >= (TempFreq + 1) / 2){
LcdcClkDiv = LCDC_SYS_CLK / TempFreq + 1;
} else {
LcdcClkDiv = LCDC_SYS_CLK / TempFreq;
}
/*Because DCLK=SYS_CLK/(CLKDIV+2), the actual divider must be not less than 2*/
assert_param((LcdcClkDiv>=2)&&(LcdcClkDiv<=65536));
/*ensure CLKDIV is a even value*/
if(LcdcClkDiv%2 != 0){
LcdcClkDiv = LcdcClkDiv - 1;
}
/*fill the CLKDIV field in the register LCDC_CLK_DIV*/
LCDCx->LCDC_CLK_DIV &= (~LCDC_CLK_DIV_DCLKDIV);
LCDCx->LCDC_CLK_DIV |= (LcdcClkDiv-2);
/*write the value configured back to registers*/
LCDCx->LCDC_LED_CFG = LedCfg;
LCDCx->LCDC_LED_TIMING = LedTiming;
LCDCx->LCDC_DMA_MODE_CFG = DmaModeCfg;
LCDCx->LCDC_PLANE_SIZE = PlaneSize;
LCDCx->LCDC_CTRL = LcdcCtrl;
LCDCx->LCDC_LED_IDLE = LedIdle;
}
/**
* @brief Confugure OE active width.
* @param LCDCx: where LCDCx can be LCDC.
* @param OEActvWidth: the OE signal active width; Unit: DCLK.
* @retval None
*/
void LCDC_LEDSetOEWidth(LCDC_TypeDef* LCDCx, u32 OEActvWidth)
{
u32 LedTiming;
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
assert_param((OEActvWidth >= 1) && (OEActvWidth <= 0x1000));
LedTiming = LCDCx->LCDC_LED_TIMING;
/*fill the OEACTW field in register LCDC_LED_TIMING*/
LedTiming &= ~LCDC_LED_TIMING_OEACTW;
LedTiming |= ((OEActvWidth-1)<<8);
LCDCx->LCDC_LED_TIMING = LedTiming;
/*set the bit LEDIFUPDATE in register LCDC_LED_CFG*/
LCDCx->LCDC_LED_CFG |= LCDC_LED_CFG_LEDIFUPDATE;
}
/*-----------------------------------------------DMA functions------------------------------------------------*/
/**
* @brief Configure LCDC DMA burst size .
* @param LCDCx: where LCDCx can be LCDC.
* @param BurstSize: DMA burst size; Unit 64 Bytes.
* @note If BurstSize=1, the actual burstsize = 1x64 Bytes; if the BurstSize=2,
* the actual burstsize = 2x64 = 128 Bytes.... The parameter "BurstSize" is not more
* than 8.
* @retval None
*/
void LCDC_DMAModeConfig(LCDC_TypeDef* LCDCx, u32 BurstSize)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
assert_param((BurstSize>=1) && (BurstSize<=8));
/*fill the RDOTST field in register LCDC_DMA_MODE_CFG*/
LCDCx->LCDC_DMA_MODE_CFG &= ~LCDC_DMA_MODE_CFG_RDOTST;
LCDCx->LCDC_DMA_MODE_CFG |= (BurstSize-1)<<2;
}
/**
* @brief Configure LCDC DMA under flow mode and under flow error data .
* @param LCDCx: where LCDCx can be LCDC.
* @param DmaUnFlwMode: DMA under flow mode, this parameter
* can be one of the following values:
* @arg LCDC_DMAUNFW_OUTPUT_LASTDATA: output last data
* @arg LCDC_DMAUNFW_OUTPUT_ERRORDATA: output error data
* @param ErrorData: the output data when DMA FIFO underflow occurred. When under flow mode is configured as
* LCDC_DMAUNFW_OUTPUT_ERRORDATA, this parameter is needed, and otherwise it can be ignored.
* @retval None
*/
void LCDC_DMAUnderFlowConfig(LCDC_TypeDef* LCDCx, u32 DmaUnFlwMode, u32 ErrorData)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
assert_param(IS_LCDC_DMA_DMA_UNDERFLOW_MODE(DmaUnFlwMode));
assert_param(ErrorData <= 0xFFFF);
/*fill the DMAUNMODE field in register LCDC_UNDFLW_CFG*/
LCDCx->LCDC_UNDFLW_CFG &= ~LCDC_UNDFLW_CFG_UNDMODE;
LCDCx->LCDC_UNDFLW_CFG |= DmaUnFlwMode;
if(DmaUnFlwMode==LCDC_DMAUNFW_OUTPUT_ERRORDATA) {
/*fill the ERROUTDATA field in register LCDC_UNDFLW_CFG*/
LCDCx->LCDC_UNDFLW_CFG &= ~LCDC_UNDFLW_CFG_ERROUTDATA;
LCDCx->LCDC_UNDFLW_CFG |= ErrorData;
}
}
/**
* @brief Configure image base address.
* @param LCDCx: where LCDCx can be LCDC.
* @param ImgBaseAddr: the image base address.
* @retval None
*/
void LCDC_DMAImageBaseAddrConfig(LCDC_TypeDef* LCDCx, u32 ImgBaseAddr)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*fill the register LCDC_IMG_BASE_ADDR*/
LCDCx->LCDC_IMG_BASE_ADDR = ImgBaseAddr;
}
/*---------------------------------------Interrupt functions--------------------------------------------*/
/**
* @brief Enables or disables the specified LCDC interrupts.
* @param LCDCx: where LCDCx can be LCDC.
* @param LCDC_IT: specifies the LCDC interrupts sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg LCDC_IT_DMAUNDFW: DMA FIFO underflow interrupt
* @arg LCDC_IT_FRDN: LCD refresh done interrupt
* @arg LCDC_IT_LINE: line interrupt
* @arg LCDC_IT_IO_TIMEOUT: IO write/read timeout interrupt
* @arg LCDC_IT_FRM_START: Frame Start interrupt
* @param NewState: new state of the specified LCDC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void LCDC_INTConfig(LCDC_TypeDef* LCDCx, u32 LCDC_IT, u32 NewState)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
if (NewState != DISABLE) {
/* Enable the selected LCDC interrupts */
LCDCx->LCDC_IRQ_EN |= LCDC_IT;
} else {
/* Disable the selected LCDC interrupts */
LCDCx->LCDC_IRQ_EN &= (~LCDC_IT);
}
}
/**
* @brief Configure line interrupt position.
* @param LCDCx: where LCDCx can be LCDC.
* @param LineNum: the line number.
* @retval None
*/
void LCDC_LineINTPosConfig(LCDC_TypeDef* LCDCx, u32 LineNum)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
assert_param(LineNum<=0xFFF);
/*fill the LINE_INT_POS field in register LCDC_LINE_INT_POS*/
LCDCx->LCDC_LINE_INT_POS &= (~LCDC_LINE_INTPOS);
LCDCx->LCDC_LINE_INT_POS |= LineNum;
}
/**
* @brief Get lcdc interrupt status.
* @param LCDCx: where LCDCx can be LCDC.
* @retval interrupt status
*/
u32 LCDC_GetINTStatus(LCDC_TypeDef* LCDCx)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
return LCDCx->LCDC_IRQ_STATUS;
}
/**
* @brief Get LCDC Raw Interrupt Status.
* @param LCDCx: where LCDCx can be LCDC.
* @retval raw interrupt status
*/
u32 LCDC_GetRawINTStatus(LCDC_TypeDef* LCDCx)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
return LCDCx->LCDC_IRQ_RAW;
}
/**
* @brief Clears all of the LCDC interrupt pending bit.
* @param LCDCx: where LCDCx can be LCDC.
* @retval None
*/
void LCDC_ClearAllINT(LCDC_TypeDef* LCDCx)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*write 1 to clear all interrupts*/
LCDCx->LCDC_IRQ_STATUS = 0xFFFFFFFF;
}
/**
* @brief Clears the LCDC's interrupt pending bits.
* @param LCDCx: where LCDCx can be LCDC.
* @param LCDC_IT: specifies the interrupt to be cleared.
* This parameter can be any combination of the following values:
* @arg LCDC_IT_LINE:line interrupt
* @arg LCDC_IT_FRDN: refresh frame done interrupt
* @arg LCDC_IT_DMAUNDFW: DMA FIFO under flow interrupt
* @arg LCDC_IT_IO_TIMEOUT: IO write/read timeout interrupt
* @arg LCDC_IT_FRM_START: Frame Start interrupt
* @retval None
*/
void LCDC_ClearINT(LCDC_TypeDef* LCDCx, u32 LCDC_IT)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
assert_param(IS_LCDC_CLEAR_IT(LCDC_IT));
/*clear the specified interrupt*/
LCDCx->LCDC_IRQ_STATUS = LCDC_IT;
}
/**
* @brief Get the current position.
* @param LCDCx: where LCDCx can be LCDC.
* @param pCurPosX: the current X position pointer.
* @param pCurPosY: the current Y position pointer.
* @retval None
*/
void LCDC_GetCurPosStatus(LCDC_TypeDef* LCDCx, u32* pCurPosX, u32* pCurPosY)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*Get the X position*/
*pCurPosX = (LCDCx->LCDC_CUR_POS_STATUS & LCDC_CUR_POS_STS_X);
/*Get the Y position*/
*pCurPosY = ((LCDCx->LCDC_CUR_POS_STATUS & LCDC_CUR_POS_STS_Y)>>16);
}
/**
* @brief Get the DMA FIFO under flow interrupt count.
* @param LCDCx: where LCDCx can be LCDC.
* @param DmaUnIntCnt: the DMA under flow interrupt count pointer.
* @retval None
*/
void LCDC_GetDmaUnINTCnt(LCDC_TypeDef* LCDCx, u32* DmaUnIntCnt)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*get the DMA under flow interrupt count*/
*DmaUnIntCnt = (LCDCx->LCDC_STATUS & LCDC_STATUS_DMAUNINTCNT);
}
/*------------------------------------------------Global APIs------------------------------------------------*/
/**
* @brief Enables or disables the LCDC.
* @param LCDCx: where LCDCx can be LCDC.
* @param NewState: new state of the LCDC.
* This parameter can be: ENABLE or DISABLE.
* @note when NewState is DISABLE, during the period of valid line(VTIMING =valid data),
* the disable action will be performed after the last valid line had transferred. During
* the other periods, performed the disable action instantly. If disable the LCDC instantly,
* use the API LCDC_InsDisable().
* @retval None
*/
void LCDC_Cmd(LCDC_TypeDef* LCDCx, u32 NewState)
{
u32 TempCtrl;
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
TempCtrl = LCDCx->LCDC_CTRL;
if (NewState != DISABLE) {
/* clear DISABLE bits, or it leads to enable LCDC unsuccessfully*/
TempCtrl &= ~(LCDC_CTRL_LCDCDIS|LCDC_CTRL_LCDCINSDIS);
/*set ENBALE bit*/
TempCtrl |= LCDC_CTRL_LCDCEN;
} else {
/*clear instant disable bit*/
TempCtrl &= ~LCDC_CTRL_LCDCINSDIS;
/*set DISABLE bit*/
TempCtrl |= LCDC_CTRL_LCDCDIS;
}
LCDCx->LCDC_CTRL = TempCtrl;
}
/**
* @brief Disable the LCDC instantly.
* @param LCDCx: where LCDCx can be LCDC.
* @note Disable LCDC instantly. HW will reset LCDC internal states and disable LCDC
* then clear both this bit and LCDCEN.
* @retval None
*/
void LCDC_InsDisable(LCDC_TypeDef* LCDCx)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*write 1 to LCDCINSDIS field in register LCDC_CTRL to disable LCDC instantly*/
LCDCx->LCDC_CTRL |= LCDC_CTRL_LCDCINSDIS;
}
/**
* @brief Deinitializes the LCDC.
* @param LCDCx: where LCDCx can be LCDC.
* @note Disable LCDC instantly, clear and disable all interrupts.
* @retval None
*/
void LCDC_DeInit(LCDC_TypeDef* LCDCx)
{
/*check the parameters*/
assert_param(IS_LCDC_ALL_PERIPH(LCDCx));
/*disable LCDC instantly*/
LCDCx->LCDC_CTRL |= LCDC_CTRL_LCDCINSDIS;
/*clear all interrupts*/
LCDCx->LCDC_IRQ_STATUS = 0xFFFFFFFF;
/*disable all interrupts*/
LCDCx->LCDC_IRQ_EN = 0;
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_lcdc.c
|
C
|
apache-2.0
| 36,545
|
/**
******************************************************************************
* @file rtl8721dhp_ota_ram.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the OTA functions.
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
#include "strproc.h"
/**
* @brief Set OTA image index.
* @param OTAIdx: This parameter can be one of the following values:
* @arg OTA_INDEX_1: select OTA1(low flash address) as image2
* @arg OTA_INDEX_2: select OTA2(high flash address) as image2
* @retval status value:
* - 1: set ok
* - 0: set fail
* @note SelectOTA2: will set LSB odd bits 0, 0xFFFFFFFE/0xFFFFFFF8... means select OTA2
* @note SelectOTA1: will set LSB even bits 0, 0xFFFFFFFF/0xFFFFFFFC... means select OTA1
*/
IMAGE2_RAM_TEXT_SECTION
u32 OTA_Change(u32 OTAIdx)
{
u32 BitIdx = 0;
u32 ValidIMG2 = HAL_READ32(SPI_FLASH_BASE, FLASH_SYSTEM_DATA_ADDR + 4);
/* erase ValidIMG2 when all 32bits cleared */
if (ValidIMG2 == 0x00000000) {
FLASH_EreaseDwordsXIP(FLASH_SYSTEM_DATA_ADDR + 4, 1);
ValidIMG2 = 0xFFFFFFFF;
}
/* get first bit which is not cleared */
for (BitIdx = 0; BitIdx <= 31; BitIdx++) {
if ((ValidIMG2 & BIT(BitIdx)) != 0) {
break;
}
}
DBG_8195A("BitIdx: %d \n", BitIdx);
/* even bits 0 currrent is OTA1 */
if ((BitIdx % 2) == 0) {
if (OTAIdx == OTA_INDEX_1) {
DBG_8195A("currrent is OTA1, select OTA1 \n");
return _TRUE;
} else {
DBG_8195A("currrent is OTA1, select OTA2 \n");
ValidIMG2 &= ~BIT(BitIdx);
FLASH_TxData12BXIP(FLASH_SYSTEM_DATA_ADDR + 4, 4, (u8*)&ValidIMG2);
}
} else { /* odd bits 0 currrent is OTA2 */
if (OTAIdx == OTA_INDEX_1) {
DBG_8195A("currrent is OTA2, select OTA1 \n");
ValidIMG2 &= ~BIT(BitIdx);
FLASH_TxData12BXIP(FLASH_SYSTEM_DATA_ADDR + 4, 4, (u8*)&ValidIMG2);
} else {
DBG_8195A("currrent is OTA2, select OTA2 \n");
return _TRUE;
}
}
return _TRUE;
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_ota_ram.c
|
C
|
apache-2.0
| 2,483
|
#include "ameba_soc.h"
extern SDIOHCFG_TypeDef sdioh_config;
SRAM_NOCACHE_DATA_SECTION
SD_CardInfo card_info;
static void SDIOH_Pinmux(void)
{
u32 tmp;
/* SDIOH pinmux enable */
tmp = HAL_READ32(SYSTEM_CTRL_BASE, REG_HS_SDIO_CTRL);
tmp |= BIT_HS_SDIOH_PIN_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_HS_SDIO_CTRL, tmp);
Pinmux_Config(_PB_20, PINMUX_FUNCTION_SDIOH); /* CMD */
Pinmux_Config(_PB_21, PINMUX_FUNCTION_SDIOH); /* CLK */
Pinmux_Config(_PB_22, PINMUX_FUNCTION_SDIOH); /* D0 */
PAD_PullCtrl(_PB_20, GPIO_PuPd_UP);
PAD_PullCtrl(_PB_21, GPIO_PuPd_UP);
PAD_PullCtrl(_PB_22, GPIO_PuPd_UP);
if(sdioh_config.sdioh_bus_width == SDIOH_BUS_WIDTH_4BIT) {
Pinmux_Config(_PB_18, PINMUX_FUNCTION_SDIOH); /* D2 */
Pinmux_Config(_PB_19, PINMUX_FUNCTION_SDIOH); /* D3 */
Pinmux_Config(_PB_23, PINMUX_FUNCTION_SDIOH); /* D1 */
PAD_PullCtrl(_PB_18, GPIO_PuPd_UP);
PAD_PullCtrl(_PB_19, GPIO_PuPd_UP);
PAD_PullCtrl(_PB_23, GPIO_PuPd_UP);
}
if(sdioh_config.sdioh_cd_pin != _PNC) { /* CD */
Pinmux_Config((u8)sdioh_config.sdioh_cd_pin, PINMUX_FUNCTION_SDIOH);
PAD_PullCtrl((u8)sdioh_config.sdioh_cd_pin, GPIO_PuPd_UP);
}
if(sdioh_config.sdioh_wp_pin != _PNC) { /* WP */
Pinmux_Config((u8)sdioh_config.sdioh_wp_pin, PINMUX_FUNCTION_SDIOH);
PAD_PullCtrl((u8)sdioh_config.sdioh_wp_pin, GPIO_PuPd_UP);
}
}
/**
* @brief Check SDIOH response is valid or not.
* @param resp_type: which can be a value of @ref SDIOH_Card_Response_Byte_Index.
* @param cmd: indicate the command of which the response to be checked
* @retval 0: response is valid
* others: response is invalid
*/
static u32 CmdRespError(u8 resp_type, u8 cmd)
{
u32 ret = HAL_OK;
u16 err_status;
u8 resp_byte0, resp_byte1, resp_byte3, resp_byte4, t_cmd = cmd;
ret = SDIOH_CheckTxError(&err_status);
if (ret != HAL_OK) {
if(err_status & SDIOH_SD_CMD_RSP_TO_ERR)
return HAL_TIMEOUT;
else if (err_status & SDIOH_SD_TUNNING_PAT_COMP_ERR)
return HAL_ERR_HW;
else
return ret;
}
/* For R1, R6, R7 */
if((resp_type == SDIOH_RESP_R1) || (resp_type == SDIOH_RESP_R6) || (resp_type == SDIOH_RESP_R7)) {
if((cmd == SD_CMD_WrMulBlk) ||(cmd == SD_CMD_RdMulBlk))
t_cmd = SD_CMD_StopXsmission;
resp_byte0 = SDIOH_GetResponse(SDIO_RESP0);
resp_byte1 = SDIOH_GetResponse(SDIO_RESP1);
resp_byte3 = SDIOH_GetResponse(SDIO_RESP3);
resp_byte4 = SDIOH_GetResponse(SDIO_RESP4);
if((resp_byte0 & SDIOH_CMD_IDX_MASK) != t_cmd) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Command index error !!\r\n");
return HAL_ERR_UNKNOWN;
}
if(cmd == SD_CMD_AppCmd) {
if(!(resp_byte4 & SD_APP_CMD)) {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "ACMD isn't expected !!\r\n");
return HAL_ERR_UNKNOWN;
}
} else if((cmd == SD_CMD_RdSingleBlk) || (cmd == SD_CMD_RdMulBlk)) {
if((resp_byte1 & SD_ADDRESS_ERROR) || (resp_byte1 & SD_BLOCK_LEN_ERROR))
return HAL_ERR_UNKNOWN;
} else if((cmd == SD_CMD_WrBlk) || (cmd == SD_CMD_WrMulBlk)) {
if((resp_byte1 & SD_ADDRESS_ERROR) || (resp_byte1 & SD_BLOCK_LEN_ERROR) || (resp_byte1 & SD_WP_VIOLATION))
return HAL_ERR_UNKNOWN;
}
}
/* For R7 */
if(resp_type == SDIOH_RESP_R7) {
// check the echo-back of check pattern
if(resp_byte4 != SDIOH_CMD8_CHK_PATN) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Check pattern error !!\r\n");
return HAL_ERR_UNKNOWN;
}
// check the VHS
if((resp_byte3 & 0xF) != SDIOH_CMD8_VHS) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Voltage accepted error !!\r\n");
return HAL_ERR_UNKNOWN;
}
}
return HAL_OK;
}
/**
* @brief Reset SD card.
* @param None.
* @retval 0: reset SD card successfully
* others: fail to reset SD card
*/
static u32 SD_ResetCard(void)
{
u32 ret;
SDIOH_CmdTypeDef cmd_attr;
/***** CMD0 *****/
cmd_attr.arg = 0;
cmd_attr.idx = SD_CMD_GoIdleSte;
cmd_attr.rsp_type = SDIOH_NO_RESP;
cmd_attr.rsp_crc_chk = DISABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
// check if any errors
ret = CmdRespError(SDIOH_NO_RESP, SD_CMD_GoIdleSte);
if (ret != HAL_OK) {
return ret;
}
return HAL_OK;
}
/**
* @brief Sends SD Memory Card interface condition, which includes host supply voltage information
* and asks the card whether card supports voltage.
* @param voltage_mismatch: pointer to a variable to indicate SD card responds to CMD8 or not.
* @retval HAL_OK: SD card responds to CMD8 successfully
* HAL_TIMEOUT: SD card does not respond to CMD8
*/
static u32 SD_VoltageCheck(u8 * voltage_mismatch)
{
/* To avoid gcc warnings */
( void ) voltage_mismatch;
u32 ret;
SDIOH_CmdTypeDef cmd_attr;
/***** CMD8 *****/
cmd_attr.arg = (SDIOH_CMD8_VHS << 8) | SDIOH_CMD8_CHK_PATN;
cmd_attr.idx = SD_CMD_SendIfCond;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R7, SD_CMD_SendIfCond);
if(ret == HAL_TIMEOUT) {
//voltage_mismatch = 1; /* for Ver1.x SD card*/
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO,"voltage mismatch\n");
ret = HAL_OK;
} else if(ret == HAL_OK) {
//voltage_mismatch = 0;
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO,"voltage match\n");
}
return ret;
}
/**
* @brief Forces the card to stop transmission.
* @param None
* @retval HAL_OK: Transmission is stopped successfully
* Others: Fail to stop transmisstion
*/
u32 SD_StopTransfer(void)
{
u32 ret;
SDIOH_CmdTypeDef cmd_attr;
SDIOH_TypeDef *psdioh = SDIOH_BASE;
/***** CMD12 *****/
cmd_attr.arg = 0;
cmd_attr.idx = SD_CMD_StopXsmission;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_StopXsmission);
if (ret != HAL_OK) {
return ret;
}
// stop the transfer & the transfer state machine returns to idle state
psdioh->CARD_STOP = SDIOH_TARGET_MODULE_SD;
return HAL_OK;
}
/**
* @brief Get operating condition register(OCR) value in response.
* @param voltage_mismatch: indicate voltage mismatch or not when check voltage.
* @retval HAL_OK: Get OCR successfully
* Others: Fail to get OCR
*/
#if defined(SDIO) && (SDIO == SD)
static u32 SD_GetOCR(u8 voltage_mismatch)
{
u32 ret;
SDIOH_CmdTypeDef cmd_attr;
u32 retry = 100;
while(retry--) {
// Normal ACMD41 (CMD55)
cmd_attr.arg = 0;
cmd_attr.idx = SD_CMD_AppCmd;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_AppCmd);
if(ret != HAL_OK)
break;
// Normal ACMD41 (CMD41)
#ifdef SDIOH_SUPPORT_SD30
if (voltage_mismatch)
cmd_attr.arg = (SD_SUPPORT_SDSC_ONLY << 30) | (SD_MAX_PERFORM << 28) | (SD_USE_CUR_VOL << 24) | SDIOH_OCR_VDD_WIN; // 3.3V
else
cmd_attr.arg = (SD_SUPPORT_SDHC_SDXC << 30) | (SD_MAX_PERFORM << 28) | (SD_SWITCH_18V << 24) | SDIOH_OCR_VDD_WIN; // 1.8V
#else
if(voltage_mismatch)
cmd_attr.arg = (SD_SUPPORT_SDSC_ONLY << 30) | SDIOH_OCR_VDD_WIN;
else
cmd_attr.arg = (SD_SUPPORT_SDHC_SDXC << 30) | SDIOH_OCR_VDD_WIN;
#endif
cmd_attr.idx = SD_CMD_SdSendOpCond;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = DISABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr , SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R3, SD_CMD_SdSendOpCond);
if (ret != HAL_OK) {
return ret;
}
// check if initialization is complete, Card power up status bit, OCR bit31
if(SDIOH_GetResponse(SDIO_RESP1) & BIT7) {
break;
}
DelayUs(10000);
}
if(ret != HAL_OK) {
return ret;
}
if(!retry) {
return HAL_TIMEOUT;
}
// check CCS(Card Capacity Status) bit, OCR bit30
if(SDIOH_GetResponse(SDIO_RESP1) & BIT6) {
card_info.is_sdhc_sdxc = 1;
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "This is a SDHC/SDXC card...\r\n");
#ifdef SDIOH_SUPPORT_SD30
// check S18A(Switching to 1.8V Accepted) bit, OCR bit24
if(SDIOH_GetResponse(SDIO_RESP1) & BIT0) {
ret = SD_VoltageSwitch();
if (ret != HAL_OK)
return ret;
}else {
card_info.sig_level = SDIOH_SIG_VOL_33;
card_info.bus_spd = SD_SPEED_DS;
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Keep 3.3V...\r\n");
}
#else
card_info.sig_level = SDIOH_SIG_VOL_33;
card_info.bus_spd = SD_SPEED_DS;
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Keep 3.3V...\r\n");
#endif
} else {
card_info.is_sdhc_sdxc = 0;
card_info.sig_level = SDIOH_SIG_VOL_33;
card_info.bus_spd = SD_SPEED_DS;
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "This is a SDSC card...\r\n");
}
return HAL_OK;
}
#else
static SD_RESULT SD_GetOCR(u8 voltage_mismatch)
{
u32 ret, cnt = 1000;
SDIOH_CmdTypeDef cmd_attr;
u8 resp_byte1;
card_info.is_sdhc_sdxc = 1;
resp_byte1 = SDIOH_GetResponse(SDIO_RESP1);
do{
cmd_attr.arg = 0x40FF8080;
cmd_attr.idx = EMMC_CMD_SendOpCond;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = DISABLE;
cmd_attr.data_present = SDIOH_DATA_EXIST;
ret = SDIOH_SendCommand(&cmd_attr , SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R3, EMMC_CMD_SendOpCond);
if(ret != HAL_OK)
return ret;
resp_byte1 = SDIOH_GetResponse(SDIO_RESP1);
DelayMs(1);
if(resp_byte1&BIT7) {
return HAL_OK;
}
}while(cnt--);
return HAL_ERR_UNKNOWN;
}
#endif
/**
* @brief Asks any card to send the CID numbers on the CMD line (any card that is connected to the host will respond)
* @param None.
* @retval HAL_OK: Get CID successfully
* Others: Fail to get CID
*/
static u32 SD_GetCID(void)
{
u32 ret;
SDIOH_DmaCtl dma_cfg;
SDIOH_CmdTypeDef cmd_attr;
u8* pbuf = card_info.dma_buf;
/***** CMD2 *****/
_memset((void *)(pbuf), 0, SDIOH_C6R2_BUF_LEN);
dma_cfg.op = SDIOH_DMA_READ;
dma_cfg.start_addr = ((u32)(pbuf))/8;
dma_cfg.blk_cnt = 1;
dma_cfg.type = SDIOH_DMA_R2;
SDIOH_DMAConfig(&dma_cfg);
cmd_attr.arg = 0;
cmd_attr.idx = SD_CMD_AllSendCid;
cmd_attr.rsp_type = SDIOH_RSP_17B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, 0);
if(ret != HAL_OK)
return ret;
ret = SDIOH_WaitDMADone(SDIOH_XFER_CPLT_TIMEOUT);
if (ret != HAL_OK) {
return ret;
}
//DCache_Invalidate((u32)pbuf, SDIOH_C6R2_BUF_LEN);
ret = CmdRespError(SDIOH_RESP_R2, SD_CMD_AllSendCid);
if (ret != HAL_OK) {
return ret;
}
#if defined(SDIO) && (SDIO == EMMC)
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Manufacturer ID:%d\r\n", pbuf[1]);
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "OEM/Application ID:%x\r\n", pbuf[3]);
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Product name:%x%x%x%x%x%x\r\n", pbuf[4], pbuf[5], pbuf[6], pbuf[7], pbuf[8], pbuf[9]);
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Product serial number:%02X%02X%02X%02X\r\n", pbuf[11], pbuf[12], pbuf[13], pbuf[14]);
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Manufacturing date:%d/%d\r\n", 2013+(pbuf[15]&0xf) ,pbuf[15]>>4);
#else
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Manufacturer ID:%d\r\n", pbuf[1]);
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "OEM/Application ID:%c%c\r\n", pbuf[2], pbuf[3]);
//DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Product name:%c%c%c%c%c\r\n", pbuf[4], pbuf[5], pbuf[6], pbuf[7], pbuf[8]);
//DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Product serial number:%02X%02X%02X%02X\r\n", pbuf[10], pbuf[11], pbuf[12], pbuf[13]);
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Manufacturing date:%d/%d\r\n", 2000 + (((pbuf[14] & 0xF) << 4) | (pbuf[15] >> 4)), pbuf[15] & 0xF);
#endif
return HAL_OK;
}
/**
* @brief Ask the card to publish a new relative address (RCA)
* @param None.
* @retval HAL_OK: Get RCA successfully
* Others: Fail to get RCA
*/
static u32 SD_GetRCA(void)
{
u32 ret;
SDIOH_CmdTypeDef cmd_attr;
/***** CMD3 *****/
cmd_attr.arg = 0;
cmd_attr.idx = SD_CMD_SendRelAddr;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R6, SD_CMD_SendRelAddr);
if (ret != HAL_OK) {
return ret;
}
// get RCA
card_info.rca = (SDIOH_GetResponse(SDIO_RESP1) << 8) | (SDIOH_GetResponse(SDIO_RESP2));
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "RCA = %04X\r\n", card_info.rca);
return HAL_OK;
}
/**
* @brief Ask the Addressed card sends its card-specific data (CSD) on the CMD line.
* @param None.
* @retval HAL_OK: Get CSD successfully
* Others: Fail to get CSD
*/
static u32 SD_GetCSD(void)
{
u32 ret;
SDIOH_DmaCtl dma_cfg;
SDIOH_CmdTypeDef cmd_attr;
u8* pbuf = card_info.dma_buf;
u32 c_size, n;
/***** CMD9 *****/
_memset((void *)(pbuf), 0, SDIOH_C6R2_BUF_LEN);
dma_cfg.op = SDIOH_DMA_READ;
dma_cfg.start_addr = ((u32)(pbuf))/8;
dma_cfg.blk_cnt = 1;
dma_cfg.type = SDIOH_DMA_R2;
SDIOH_DMAConfig(&dma_cfg);
cmd_attr.arg = (card_info.rca) << 16;
cmd_attr.idx = SD_CMD_SendCsd;
cmd_attr.rsp_type = SDIOH_RSP_17B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, 0);
if(ret != HAL_OK)
return ret;
ret = SDIOH_WaitDMADone( SDIOH_XFER_CPLT_TIMEOUT);
if (ret != HAL_OK) {
return ret;
}
//DCache_Invalidate((u32)pbuf, SDIOH_C6R2_BUF_LEN);
ret = CmdRespError(SDIOH_RESP_R2, SD_CMD_SendCsd);
if (ret != HAL_OK) {
return ret;
}
_memcpy (card_info.csd, pbuf + 1, SDIOH_CSD_LEN);
#if defined(SDIO) && (SDIO == SD)
if(card_info.csd[0] >> 6) {
c_size = (((card_info.csd[7] & 0x3F) << 16) | (card_info.csd[8] << 8) | (card_info.csd[9]))+1;
card_info.capaticy = c_size << 9; //KB
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "CSD Version:2.0\r\n");
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "User data area capacity: %d GB\r\n", card_info.capaticy / 1024 / 1024);
} else {
c_size = (((card_info.csd[6] & 0x3) << 10) | (card_info.csd[7] << 2) | (card_info.csd[8] >> 6)) + 1;
n = ((((card_info.csd[9] & 0x3) << 1) |(card_info.csd[10] >> 7))+2) + (card_info.csd[5] & 0xF);
card_info.capaticy = (u32)(c_size << (n - 10)); //KB
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "CSD Version:1.0\r\n");
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "User data area capacity: %d MB\r\n", card_info.capaticy /1024);
}
#endif
card_info.read_bl_len = 1 << (card_info.csd[5] & 0xF);
card_info.write_bl_len = 1 << (((card_info.csd[12] & 0x3) << 2) | (card_info.csd[13] >> 6));
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Max. read data block length: %d Bytes\r\n", card_info.read_bl_len);
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Max. write data block length: %d Bytes\r\n", card_info.write_bl_len);
return HAL_OK;
}
/**
* @brief Select/Deselect the SD card.
* @param select: can be _TRUE or _FALSE.
* @retval HAL_OK: Select/Deselect card successfully
* Others: Fail to Select/Deselect card
*/
static u32 SD_SelectDeselect(u8 select)
{
u32 ret;
SDIOH_CmdTypeDef cmd_attr;
/***** CMD7 *****/
if (select == _TRUE) {
cmd_attr.arg = (card_info.rca) << 16;
cmd_attr.idx = SD_CMD_SelDeselCard;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_SelDeselCard);
if (ret != HAL_OK) {
return ret;
}
} else {
// address 0 deselects all
cmd_attr.arg = 0;
cmd_attr.idx = SD_CMD_SelDeselCard;
cmd_attr.rsp_type = SDIOH_NO_RESP;
cmd_attr.rsp_crc_chk = DISABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
// check if any errors
ret = CmdRespError(SDIOH_NO_RESP, SD_CMD_SelDeselCard);
if (ret != HAL_OK) {
return ret;
}
}
return HAL_OK;
}
/**
* @brief Set the bus width of the SD card.
* @param bus_width: can be one of the @ref SDIOH_Bus_Width
* @retval HAL_OK: Set bus width successfully
* Others: Fail to set bus width
*/
static u32 SD_SetBusWidth(u8 bus_width)
{
u32 ret, wid_arg_4bit, wid_arg_1bit;
SDIOH_CmdTypeDef cmd_attr;
if (bus_width > SDIOH_BUS_WIDTH_4BIT) {
return HAL_ERR_PARA;
}
if (SDIOH_GetBusWidth() == bus_width) {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Current SD bus width is already the specified setting...\r\n");
return HAL_OK;
}
#if defined(SDIO) && (SDIO == SD)
/***** ACMD6 (CMD55) *****/
cmd_attr.arg = (card_info.rca) << 16;
cmd_attr.idx = SD_CMD_AppCmd;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_AppCmd);
if (ret != HAL_OK) {
return ret;
}
wid_arg_4bit = 0x2;
wid_arg_1bit = 0x0;
#else
wid_arg_4bit = 0x03B70100; //EXT_CSD register B7 byte: 01, 4bit mode; 00, 1bit mode
wid_arg_1bit = 0x03B70000;
#endif
/***** ACMD6 (CMD6) *****/
if(bus_width == SDIOH_BUS_WIDTH_4BIT) {
cmd_attr.arg = wid_arg_4bit; // 4-bit bus
} else {
cmd_attr.arg = wid_arg_1bit; // 1-bit bus
}
cmd_attr.idx = SD_CMD_SetBusWidth;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_SetBusWidth);
if (ret != HAL_OK) {
return ret;
}
// Host also selects the specified mode
SDIOH_SetBusWidth(bus_width);
return HAL_OK;
}
/**
* @brief Get the SD Configuration Register (SCR).
* @param None
* @retval HAL_OK: Get SCR successfully
* Others: Fail to get SCR
*/
static u32 SD_GetSCR(void)
{
u32 ret;
SDIOH_DmaCtl dma_cfg;
SDIOH_CmdTypeDef cmd_attr;
u8* pbuf = card_info.dma_buf;
/***** ACMD51 (CMD55) *****/
cmd_attr.arg = (card_info.rca) << 16;
cmd_attr.idx = SD_CMD_AppCmd;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_AppCmd);
if (ret != HAL_OK) {
return ret;
}
/***** ACMD51 (CMD51) *****/
_memset((void *)(pbuf), 0, SDIOH_C6R2_BUF_LEN);
dma_cfg.op = SDIOH_DMA_READ;
dma_cfg.start_addr = ((u32)(pbuf))/8;
dma_cfg.blk_cnt = 1;
dma_cfg.type = SDIOH_DMA_64B;
SDIOH_DMAConfig(&dma_cfg);
cmd_attr.arg = 0;
cmd_attr.idx = SD_CMD_SendScr;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_DATA_EXIST;
ret = SDIOH_SendCommand(&cmd_attr, 0);
if(ret != HAL_OK)
return ret;
ret = SDIOH_WaitDMADone( SDIOH_XFER_CPLT_TIMEOUT);
if (ret != HAL_OK) {
ret = SD_StopTransfer();
if (ret != HAL_OK) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Stop transmission error !!\r\n");
}
return HAL_ERR_UNKNOWN;
}
//DCache_Invalidate((u32)pbuf, SDIOH_C6R2_BUF_LEN);
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_SendScr);
if (ret != HAL_OK) {
return ret;
}
switch (pbuf[0] & 0xF) {
case 2:
if(pbuf[2] >> 7) {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "SD specification version: 3.0X\r\n");
card_info.sd_spec_ver = SD_SPEC_V300;
} else {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "SD specification version: 2.00\r\n");
card_info.sd_spec_ver = SD_SPEC_V200;
}
break;
case 1:
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "SD specification version: 1.10\r\n");
card_info.sd_spec_ver = SD_SPEC_V110;
break;
case 0:
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "SD specification version: 1.01\r\n");
card_info.sd_spec_ver = SD_SPEC_V101;
break;
default:
DBG_PRINTF(MODULE_SDIO, LEVEL_WARN,"SD specification version: Unknown\r\n");
card_info.sd_spec_ver = 0xFF;
}
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "Data status after erase: %d\r\n", pbuf[1] >> 7);
return HAL_OK;
}
/**
* @brief Checks switchable function (mode 0) and switch card function (mode 1).
* @param mode: can be a value of @ref SD_CMD6_operation_mode
* @param speed: can be a value of @SD_CMD6_Function_Group1
* @param buf_32align: pointer to a buffer to save the switch function status
* @retval HAL_OK: Check/Set function successfully
* Others: Fail to get check/Set function
*/
static u32 SD_SwitchFunction(u8 mode, u8 speed, u8 *buf_32align)
{
u32 ret;
SDIOH_DmaCtl dma_cfg;
SDIOH_CmdTypeDef cmd_attr;
if ((buf_32align == NULL) || (((u32)buf_32align) & 0x1F)) {
return HAL_ERR_PARA;
}
/***** CMD6 *****/
_memset((void *)buf_32align, 0, SDIOH_C6R2_BUF_LEN);
dma_cfg.op = SDIOH_DMA_READ;
dma_cfg.start_addr = ((u32)buf_32align)/8;
dma_cfg.blk_cnt = 1;
dma_cfg.type = SDIOH_DMA_64B;
SDIOH_DMAConfig(&dma_cfg);
cmd_attr.arg = (mode << 31) | (0xF << 20) | (0xF << 16) | (0xF << 12) | (0xF << 8) | (0xF << 4) | speed;
cmd_attr.idx = SD_CMD_SwitchFunc;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_DATA_EXIST;
ret = SDIOH_SendCommand(&cmd_attr, 0);
if(ret != HAL_OK)
return ret;
ret = SDIOH_WaitDMADone( SDIOH_XFER_CPLT_TIMEOUT);
if (ret != HAL_OK) {
ret = SD_StopTransfer();
if (ret != HAL_OK) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Stop transmission error !!\r\n");
}
return HAL_ERR_UNKNOWN;
}
DCache_Invalidate((u32)buf_32align, SDIOH_C6R2_BUF_LEN);
// check if any errors
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_SwitchFunc);
if (ret != HAL_OK) {
return ret;
}
return HAL_OK;
}
/**
* @brief SD card interrupt handler.
* @param None
* @retval None
*/
static void SD_IRQHandler (void)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
volatile u32 tmp1;
volatile u8 tmp2 = 0;
tmp1 = SDIOH_GetISR();
if(tmp1)
SDIOH_INTClearPendingBit(tmp1);
if(psdioh->CARD_INT_PEND & SDIOH_SDMMC_INT_PEND) {
tmp2 = psdioh->CARD_EXIST;
if(tmp2 & SDIOH_SD_EXIST) {
if(tmp2 & SDIOH_SD_WP)
card_info.sd_status = SD_PROTECTED;
else
card_info.sd_status = SD_INSERT;
DBG_8195A("Card Detect\n");
} else {
card_info.sd_status = SD_NODISK;
DBG_8195A("Card Remove\n");
}
psdioh->CARD_INT_PEND |= SDIOH_SDMMC_INT_PEND;
}
__DSB();
}
SD_RESULT SD_GetEXTCSD(u8 *pbuf)
{
u32 ret, start;
SDIOH_DmaCtl dma_cfg;
SDIOH_CmdTypeDef cmd_attr;
/***** CMD8 *****/
dma_cfg.op = SDIOH_DMA_READ;
dma_cfg.start_addr = ((u32)(pbuf))/8;
dma_cfg.blk_cnt = 1;
dma_cfg.type = SDIOH_DMA_NORMAL;
SDIOH_DMAConfig(&dma_cfg);
cmd_attr.arg = 0;
cmd_attr.idx = EMMC_CMD_SendExtCsd;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_DATA_EXIST;
ret = SDIOH_SendCommand(&cmd_attr, 100);
if(ret != HAL_OK){
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Send CMD8 error !!\r\n");
return ret;
}
ret = SDIOH_WaitDMADone(SDIOH_READ_TIMEOUT);
if (ret != HAL_OK) {
ret = SD_StopTransfer();
if (ret != HAL_OK)
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Stop transmission error !!\r\n");
return HAL_ERR_UNKNOWN;
}
//DCache_Invalidate((u32)card_info.ext_csd, SD_BLOCK_SIZE);
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_SendIfCond);
return ret;
}
/**
* @brief To read one block from the SD card.
* @param ReadAddr: The start address to begin to read from the card.
* @param readbuff: The buffer to read data blocks (must be 32-Byte alignment).
* @retval HAL_OK: Read data successfully
* Others: Fail to read data
*/
u32 SD_ReadBlock(uint8_t *readbuff, uint32_t ReadAddr)
{
u32 ret, start;
SDIOH_DmaCtl dma_cfg;
SDIOH_CmdTypeDef cmd_attr;
assert_param((readbuff != NULL) && ((((u32)readbuff) & 0x1F) == 0));
if (card_info.is_sdhc_sdxc)
start = (u32)(ReadAddr/SD_BLOCK_SIZE); // unit: block
else
start = (u32)ReadAddr;
/***** CMD17 *****/
dma_cfg.op = SDIOH_DMA_READ;
dma_cfg.start_addr = ((u32)readbuff)/8;
dma_cfg.blk_cnt = 1;
dma_cfg.type = SDIOH_DMA_NORMAL;
SDIOH_DMAConfig(&dma_cfg);
cmd_attr.arg = start;
cmd_attr.idx = SD_CMD_RdSingleBlk;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_DATA_EXIST;
ret = SDIOH_SendCommand(&cmd_attr, 0);
if(ret != HAL_OK){
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Send CMD17 error !!\r\n");
return ret;
}
ret = SDIOH_WaitDMADone(SDIOH_READ_TIMEOUT);
if (ret != HAL_OK) {
ret = SD_StopTransfer();
if (ret != HAL_OK)
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Stop transmission error !!\r\n");
return HAL_ERR_UNKNOWN;
}
DCache_Invalidate((u32)readbuff, SD_BLOCK_SIZE);
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_RdSingleBlk);
return ret;
}
/**
* @brief To read multi-block from the SD card.
* @param ReadAddr: The start address to begin to read from the card.
* @param readbuff: The buffer to read data blocks (must be 32-Byte alignment).
* @param NumberOfBlocks: the number of blocks to be read
* @retval HAL_OK: Read data successfully
* Others: Fail to read data
*/
u32 SD_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint32_t NumberOfBlocks)
{
u32 ret, start;
SDIOH_DmaCtl dma_cfg;
SDIOH_CmdTypeDef cmd_attr;
assert_param(NumberOfBlocks > 1);
assert_param((readbuff != NULL) && ((((u32)readbuff) & 0x1F) == 0));
if (card_info.is_sdhc_sdxc)
start = (u32)(ReadAddr/SD_BLOCK_SIZE); // unit: block
else
start = (u32)ReadAddr;
/***** CMD18 *****/
dma_cfg.op = SDIOH_DMA_READ;
dma_cfg.start_addr = ((u32)readbuff)/8;
dma_cfg.blk_cnt = NumberOfBlocks;
dma_cfg.type = SDIOH_DMA_NORMAL;
SDIOH_DMAConfig(&dma_cfg);
cmd_attr.arg = start;
cmd_attr.idx = SD_CMD_RdMulBlk;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_DATA_EXIST;
ret = SDIOH_SendCommand(&cmd_attr, 0);
if(ret != HAL_OK)
return ret;
ret = SDIOH_WaitDMADone(SDIOH_READ_TIMEOUT * NumberOfBlocks);
if (ret != HAL_OK) {
return ret;
}
DCache_Invalidate((u32)readbuff, NumberOfBlocks * SD_BLOCK_SIZE);
ret = CmdRespError(SDIOH_RESP_R1 , SD_CMD_RdMulBlk);
return ret;
}
/**
* @brief To write one block to the SD card.
* @param WriteAddr: The start address to begin writing to the card.
* @param writebuff: The buffer to write data blocks (must be 32-Byte alignment).
* @retval HAL_OK: Write data successfully
* Others: Fail to write data
*/
u32 SD_WriteBlock(uint8_t *writebuff, uint32_t WriteAddr)
{
u32 ret, start;
SDIOH_DmaCtl dma_cfg;
SDIOH_CmdTypeDef cmd_attr;
assert_param((writebuff != NULL) && ((((u32)writebuff) & 0x1F) == 0));
if (card_info.is_sdhc_sdxc)
start = (u32)(WriteAddr/SD_BLOCK_SIZE); // unit: block
else
start = (u32)WriteAddr;
/***** CMD24 *****/
DCache_Clean((u32)writebuff, SD_BLOCK_SIZE);
dma_cfg.op = SDIOH_DMA_WRITE;
dma_cfg.start_addr = ((u32)writebuff)/8;
dma_cfg.blk_cnt = 1;
dma_cfg.type = SDIOH_DMA_NORMAL;
SDIOH_DMAConfig(&dma_cfg);
cmd_attr.arg = start;
cmd_attr.idx = SD_CMD_WrBlk;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_DATA_EXIST;
ret = SDIOH_SendCommand(&cmd_attr, 0);
if(ret != HAL_OK)
return ret;
ret = SDIOH_WaitDMADone(SDIOH_WRITE_TIMEOUT);
if (ret != HAL_OK) {
ret = SD_StopTransfer();
if (ret != HAL_OK)
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Stop transmission error !!\r\n");
return HAL_ERR_UNKNOWN;
}
// check if any errors
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_WrBlk);
return ret;
}
/**
* @brief To write multi-block to the SD card.
* @param WriteAddr: The start address to begin writing to the card.
* @param NumberOfBlocks: The block count.
* @param writebuff: The buffer to write data blocks (must be 32-Byte alignment).
* @retval HAL_OK: Write data successfully
* Others: Fail to write data
*/
u32 SD_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint32_t NumberOfBlocks)
{
u32 start, ret;
SDIOH_DmaCtl dma_cfg;
SDIOH_CmdTypeDef cmd_attr;
assert_param(NumberOfBlocks > 1);
assert_param((writebuff != NULL) && ((((u32)writebuff) & 0x1F) == 0));
if (card_info.is_sdhc_sdxc)
start = (u32)(WriteAddr/SD_BLOCK_SIZE); // unit: block
else
start = (u32)WriteAddr;
#if defined(SDIO) && (SDIO == SD)
/***** ACMD23 (CMD55) *****/
cmd_attr.arg = (card_info.rca) << 16;
cmd_attr.idx = SD_CMD_AppCmd;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_AppCmd);
if (ret != HAL_OK) {
return ret;
}
/***** ACMD23 (CMD23) *****/
cmd_attr.arg = NumberOfBlocks;
cmd_attr.idx = SD_CMD_SetWrBlkEraseCnt;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_SetWrBlkEraseCnt);
if (ret != HAL_OK) {
return ret;
}
#endif
DCache_Clean((u32)writebuff, NumberOfBlocks * SD_BLOCK_SIZE);
/***** CMD25 *****/
dma_cfg.op = SDIOH_DMA_WRITE;
dma_cfg.start_addr = ((u32)writebuff)/8;
dma_cfg.blk_cnt = NumberOfBlocks;
dma_cfg.type = SDIOH_DMA_NORMAL;
SDIOH_DMAConfig(&dma_cfg);
cmd_attr.arg = start;
cmd_attr.idx = SD_CMD_WrMulBlk;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_DATA_EXIST;
ret = SDIOH_SendCommand(&cmd_attr, 0);
if(ret != HAL_OK)
return ret;
ret = SDIOH_WaitDMADone(SDIOH_WRITE_TIMEOUT * NumberOfBlocks);
if (ret != HAL_OK) {
return ret;
}
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_WrMulBlk);
return ret;
}
/**
* @brief To erase data in the SD card.
* @param startaddr: The start address to begin erasing.
* @param endaddr: The end address to begin erasing.
* @retval HAL_OK: Erase data successfully
* Others: Fail to Erase data.
*/
u32 SD_Erase(uint32_t startaddr, uint32_t endaddr)
{
SDIOH_CmdTypeDef cmd_attr;
u32 start, end, ret, blk_cnt, start_cmd, end_cmd;
#if defined(SDIO) && (SDIO == EMMC)
start_cmd = EMMC_CMD_EraseAddrSt;
end_cmd = EMMC_CMD_EraseAddrEd;
#else
start_cmd = SD_CMD_EraseBlkSt;
end_cmd = SD_CMD_EraseBlkEd;
#endif
assert_param(startaddr <= endaddr);
if (card_info.is_sdhc_sdxc) {
start = (u32)(startaddr/SD_BLOCK_SIZE);
end = (u32)(endaddr/SD_BLOCK_SIZE); // unit: block
} else {
start = (u32)startaddr;
end = (u32)endaddr;
}
blk_cnt = endaddr/SD_BLOCK_SIZE - startaddr/SD_BLOCK_SIZE + 1;
/***** CMD32 *****/
cmd_attr.arg = start;
cmd_attr.idx = start_cmd;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK){
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Send CMD32 error !!\r\n");
}
ret = CmdRespError(SDIOH_RESP_R1, start_cmd);
if (ret != HAL_OK) {
return ret;
}
/***** CMD33 *****/
cmd_attr.arg = end;
cmd_attr.idx = end_cmd;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK){
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Send CMD33 error !!\r\n");
}
ret = CmdRespError(SDIOH_RESP_R1, end_cmd);
if (ret != HAL_OK) {
return ret;
}
/***** CMD38 *****/
cmd_attr.arg = 0;
cmd_attr.idx = SD_CMD_Erase;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_ERASE_TIMEOUT * blk_cnt);
if(ret != HAL_OK){
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Send CMD38 error !!\r\n");
return ret;
}
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_Erase);
return ret;
}
/**
* @brief To get the current state of the SD card.
* @param None.
* @retval Current state of SD card, which is one of the @ref SD_Card_States values.
*/
u8 SD_GetCardStatus(void)
{
u32 ret;
u8 state;
SDIOH_CmdTypeDef cmd_attr;
/***** CMD13 *****/
cmd_attr.arg = (card_info.rca) << 16;
cmd_attr.idx = SD_CMD_SendSts;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_SendSts);
if (ret != HAL_OK) {
return SD_CARD_ERROR;
}
// get card's current state
state = (SDIOH_GetResponse(SDIO_RESP3) >> 1) & 0xF;
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO,"card_curr_ste = %d\r\n", state);
return state;
}
/**
* @brief To get the SD status from the SD card.
* @param buf_32align: The buffer to store the SD status (must be 32-Byte alignment).
* @retval HAL_OK: Get SD status successfully
* Others: Fail to get SD status.
*/
u32 SD_GetSDStatus(u8 *buf_32align)
{
u32 ret;
SDIOH_DmaCtl dma_cfg;
SDIOH_CmdTypeDef cmd_attr;
assert_param((buf_32align != NULL) && ((((u32)buf_32align) & 0x1F) == 0));
/***** ACMD13 (CMD55) *****/
cmd_attr.arg = (card_info.rca) << 16;
cmd_attr.idx = SD_CMD_AppCmd;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret= CmdRespError(SDIOH_RESP_R1, SD_CMD_AppCmd);
if (ret != HAL_OK) {
return ret;
}
/***** ACMD13 (CMD13) *****/
_memset((void *)buf_32align, 0, SDIOH_C6R2_BUF_LEN);
dma_cfg.op = SDIOH_DMA_READ;
dma_cfg.start_addr = ((u32)buf_32align)/8;
dma_cfg.blk_cnt = 1;
dma_cfg.type = SDIOH_DMA_64B;
SDIOH_DMAConfig(&dma_cfg);
cmd_attr.arg = 0;
cmd_attr.idx = SD_CMD_SendSts;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_DATA_EXIST;
ret = SDIOH_SendCommand(&cmd_attr, 0);
if(ret != HAL_OK)
return ret;
ret = SDIOH_WaitDMADone(SDIOH_XFER_CPLT_TIMEOUT);
if (ret != HAL_OK) {
ret = SD_StopTransfer();
if (ret != HAL_OK) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Stop transmission error !!\r\n");
}
return HAL_ERR_UNKNOWN;
}
DCache_Invalidate((u32)buf_32align, SDIOH_C6R2_BUF_LEN);
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_SendSts);
return ret;
}
/**
* @brief To switch the SD bus speed.
* @param speed: can be SD_SPEED_DS or SD_SPEED_HS of @ref SD_access_mode
* @retval HAL_OK: switch speed successfully
* Others: Fail to switch speed.
*/
#if defined(SDIO) && (SDIO == SD)
u32 SD_SwitchBusSpeed(u8 speed)
{
u32 ret;
u8 sw_spd, support_spd;
u8* pbuf = card_info.dma_buf;
assert_param(speed <= SD_SPEED_HS);
if ((card_info.bus_spd) == speed) {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO,"Current SD bus speed is already the specified setting.\r\n");
return HAL_OK;
}
/* Get spec version to check if card supports CMD6 which was added in version 1.10 */
ret = SD_GetSCR();
if (ret != HAL_OK)
return ret;
if((card_info.sd_spec_ver) >= SD_SPEC_V110) {
/* get the supported speed modes */
ret = SD_SwitchFunction(SD_CMD6_CHECK_MODE, SD_KEEP_CUR_SPEED, pbuf);
if (ret != HAL_OK)
return ret;
sw_spd = speed;
support_spd = pbuf[13];
if(support_spd & (1 << sw_spd)) {
if((pbuf[16] & 0xF) == sw_spd) {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO,"SD card's current speed mode is already the specified setting !!\r\n");
} else {
/* check if the specified speed can be switched */
ret = SD_SwitchFunction(SD_CMD6_CHECK_MODE, sw_spd, pbuf);
if (ret != HAL_OK)
return ret;
if((pbuf[16] & 0xF) == sw_spd) {
/* Switch to the specified speed */
ret = SD_SwitchFunction(SD_CMD6_SWITCH_MODE, sw_spd, pbuf);
if (ret != HAL_OK)
return ret;
if((pbuf[16] & 0xF) == sw_spd) {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO,"SD card changes to the specified speed mode successfully\r\n");
if(speed == SD_SPEED_DS) {
SDIOH_SwitchSpeed(SDIOH_CLK_DIV4, SDIOH_SD20_MODE); // 25 MHz
card_info.bus_spd = SD_SPEED_DS;
} else if (speed == SD_SPEED_HS) {
SDIOH_SwitchSpeed(SDIOH_CLK_DIV2, SDIOH_SD20_MODE); // 50 MHz
card_info.bus_spd = SD_SPEED_HS;
}
} else {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "The switch request is canceled !!\r\n");
return HAL_ERR_UNKNOWN;
}
} else {
DBG_PRINTF(MODULE_SDIO, LEVEL_WARN, "The specified speed mode can't be switched !!\r\n");
return HAL_ERR_UNKNOWN;
}
}
} else {
DBG_PRINTF(MODULE_SDIO, LEVEL_WARN, "This card doesn't support the specified speed mode !!\r\n");
return HAL_ERR_HW;
}
} else {
DBG_PRINTF(MODULE_SDIO, LEVEL_WARN,"This card doesn't support CMD6 and can't switch the bus speed !!\r\n");
return HAL_ERR_HW;
}
return HAL_OK;
}
#else
SD_RESULT SD_SwitchBusSpeed(u8 speed)
{
u32 ret;
SDIOH_CmdTypeDef cmd_attr;
if ((card_info.bus_spd) == speed) {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO,"Current SD bus speed is already the specified setting.\r\n");
return HAL_OK;
}
/***** CMD6 (CMD6) *****/
if(speed == SD_SPEED_HS) {
cmd_attr.arg = 0x03B90100; //EXT_CSD register B9 byte: 01, high speed mode;
} else {
cmd_attr.arg = 0x03B90000;
}
cmd_attr.idx = SD_CMD_SetBusWidth;
cmd_attr.rsp_type = SDIOH_RSP_6B;
cmd_attr.rsp_crc_chk = ENABLE;
cmd_attr.data_present = SDIOH_NO_DATA;
ret = SDIOH_SendCommand(&cmd_attr, SDIOH_CMD_CPLT_TIMEOUT);
if(ret != HAL_OK)
return ret;
ret = CmdRespError(SDIOH_RESP_R1, SD_CMD_SetBusWidth);
if (ret != HAL_OK) {
return ret;
}
// Host also selects the specified mode
if(speed == SD_SPEED_DS) {
SDIOH_SwitchSpeed(SDIOH_CLK_DIV4, SDIOH_SD20_MODE); // 25 MHz
card_info.bus_spd = SD_SPEED_DS;
} else if (speed == SD_SPEED_HS) {
SDIOH_SwitchSpeed(SDIOH_CLK_DIV2, SDIOH_SD20_MODE); // 50 MHz
card_info.bus_spd = SD_SPEED_HS;
}
return HAL_OK;
}
#endif
/****************************** The following functions are for FATFS call **************************************/
/**
* @brief To get the current state of the SDIOH and card.
* @param None.
* @retval SD_OK: SD card is initialized.
* SD_NODISK: SD card is removed.
* SD_INSERT: SD card is inserted.
* SD_INITERR: SD card is init fail.
* SD_PROTECTED: SD card is write-protected.
* SD_ERROR: Some errors occur.
*/
SD_RESULT SD_Status(void)
{
return card_info.sd_status;
}
/**
* @brief To write blocks of data to the SD card.
* @param sector: the start index of blocks to write to.
* @param data: pointer to data buffer. If the address of data buffer is 32-byte alinged,
* the write performance would be higher.
* @param count: specify how many blocks to be written.
* @retval SD_OK: Success to write blocks.
* SD_ERROR: Fail to write blocks.
*/
SD_RESULT SD_WriteBlocks(u32 sector,const u8 *data,u32 count)
{
u8 res, i = 0;
u8 *ptr;
if((u32)data & 0x1F) { /* Not 32-byte aligned */
ptr = pvPortMalloc(SD_BLOCK_SIZE + 0x1F);
if(ptr == NULL) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR,"Allocate buffer error !!\r\n");
return SD_ERROR;
}
ptr = (u8*)(((((u32)ptr-1) >> 5) + 1) << 5); /*next 32-byte aligned*/
do {
_memcpy(ptr, data + i * SD_BLOCK_SIZE, SD_BLOCK_SIZE);
res = SD_WriteBlock(ptr, (sector + i) * SD_BLOCK_SIZE);
if(res != HAL_OK)
break;
} while(++i < count);
vPortFree(ptr);
} else { /*32-byte aligned */
if(count == 1)
res = SD_WriteBlock((uint8_t *)data, sector * SD_BLOCK_SIZE);
else
res = SD_WriteMultiBlocks((uint8_t *)data, sector * SD_BLOCK_SIZE, count);
}
if(res == HAL_OK)
return SD_OK;
return SD_ERROR;
}
/**
* @brief To read blocks of data from the SD card.
* @param sector: the start index of blocks to read from.
* @param data: pointer to data buffer. If the address of data buffer is 32-byte alinged,
* the read performance would be higher.
* @param count: specify how many blocks to be read.
* @retval SD_OK: Success to read blocks.
* SD_ERROR: Fail to read blocks.
*/
SD_RESULT SD_ReadBlocks(u32 sector,u8 *data,u32 count)
{
u8 res, i = 0;
u8 *ptr;
if((u32)data & 0x1F) { /* Not 32-byte aligned */
ptr = pvPortMalloc(SD_BLOCK_SIZE + 0x1F);
if(ptr == NULL) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR,"Allocate buffer error !!\r\n");
return SD_ERROR;
}
ptr = (u8*)(((((u32)ptr-1) >> 5) + 1) << 5); /*next 32-byte aligned*/
do {
res = SD_ReadBlock(ptr, (sector + i) * SD_BLOCK_SIZE);
if(res != HAL_OK)
break;
_memcpy(data + i * SD_BLOCK_SIZE, ptr, SD_BLOCK_SIZE);
} while(++i < count);
vPortFree(ptr);
} else { /*32-byte aligned */
if(count == 1)
res = SD_ReadBlock(data, sector * SD_BLOCK_SIZE);
else
res = SD_ReadMultiBlocks(data, sector * SD_BLOCK_SIZE, count);
}
if(res == HAL_OK)
return SD_OK;
return SD_ERROR;
}
/**
* @brief To get the capacity of the SD card.
* @param sector_count: the capacity in blocks.
* @retval SD_OK: Success to get capacity.
* SD_ERROR: Fail to get capacity.
*/
SD_RESULT SD_GetCapacity(u32* sector_count)
{
if (card_info.capaticy == 0)
SD_GetCSD();
*sector_count = card_info.capaticy * (1024 / SD_BLOCK_SIZE); //capacity in block counts
if(*sector_count)
return SD_OK;
return SD_ERROR;
}
/**
* @brief To initialize the SD memory card.
* @param None.
* @retval SD_OK: Initialize SD card successfully
* Others: Fail to initialize SD card
*/
SD_RESULT SD_Init(void)
{
u32 ret;
u8 voltage_mismatch;
_memset(&card_info, 0, sizeof(SD_CardInfo));
card_info.sd_status = SD_NODISK;
/* Configure pinmux */
SDIOH_Pinmux();
/* Initialize SDIOH */
SDIOH_Init(sdioh_config.sdioh_bus_width);
#if defined(SDIO) &&(SDIO == EMMC)
card_info.sd_status = SD_INSERT;
#else
InterruptRegister((IRQ_FUN)SD_IRQHandler, SDIO_HOST_IRQ, NULL, 5);
InterruptEn(SDIO_HOST_IRQ, 5);
#endif
/* Initialize SD card */
if(card_info.sd_status == SD_INSERT) {
do {
/* Card Identification */
ret = SD_ResetCard();
if (ret != HAL_OK)
break;
#if defined(SDIO) && (SDIO == SD)
ret = SD_VoltageCheck(&voltage_mismatch);
if (ret != HAL_OK)
break;
#endif
ret = SD_GetOCR(voltage_mismatch);
if (ret != HAL_OK)
break;
ret = SD_GetCID();
if (ret != HAL_OK)
break;
ret = SD_GetRCA();
if (ret != HAL_OK)
break;
/* switch to non-initial mode */
ret = SDIOH_InitialModeCmd(DISABLE, card_info.sig_level);
if (ret != HAL_OK) {
break;
} else {
if(card_info.sig_level == SDIOH_SIG_VOL_18)
card_info.bus_spd = SD_SPEED_SDR12;
else
card_info.bus_spd = SD_SPEED_DS;
}
ret = SD_GetCSD();
if (ret != HAL_OK)
break;
ret = SD_SelectDeselect(_TRUE);
if (ret != HAL_OK)
break;
if(sdioh_config.sdioh_bus_width == SDIOH_BUS_WIDTH_4BIT) {
ret = SD_SetBusWidth(SDIOH_BUS_WIDTH_4BIT);
if (ret != HAL_OK)
break;
}
if(sdioh_config.sdioh_bus_speed == SD_SPEED_HS) {
ret = SD_SwitchBusSpeed(SD_SPEED_HS);
if (ret != HAL_OK)
break;
}
} while(0);
if(ret == HAL_OK) {
card_info.sd_status = SD_OK;
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO,"SD card is initialized\r\n");
} else {
card_info.sd_status = SD_INITERR;
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR,"Init FAIL, ret: %d\n", ret);
}
} else if (card_info.sd_status == SD_PROTECTED) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR,"Card is write protected !!\r\n");
} else if (card_info.sd_status == SD_NODISK) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR,"Card is removed\r\n");
return SD_INITERR;
}
return card_info.sd_status;
}
/**
* @brief To de-initialize the SDIO host controller.
* @param None.
* @retval SD_OK: SDIO host controller is de-initialize successfully.
*/
SD_RESULT SD_DeInit(void)
{
SDIOH_DeInit();
RCC_PeriphClockCmd(APBPeriph_SDIOH, APBPeriph_SDIOH_CLOCK, DISABLE);
InterruptUnRegister(SDIO_HOST_IRQ);
InterruptDis(SDIO_HOST_IRQ);
return SD_OK;
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_sd.c
|
C
|
apache-2.0
| 44,235
|
/**
******************************************************************************
* @file rtl8721dhp_sdio.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the
* functionalities of the SDIO device peripheral:
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/**
* @brief Fills each SDIO_InitStruct member with its default value.
* @param SDIO_InitStruct: pointer to a SDIO_InitTypeDef structure which will be
* initialized.
* @retval None
*/
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
{
/* TXBD */
SDIO_InitStruct->TXBD_BAR = (u32)NULL; /* init txbd_bar */
SDIO_InitStruct->TXBD_RING_SIZE = 20; /* init TXBD ring size */
SDIO_InitStruct->TX_BUFFER_SIZE = 0xFF; /* init txbuf_size */
/* RXBD */
SDIO_InitStruct->RXBD_BAR = (u32)NULL; /* init rxbd_bar reg */
SDIO_InitStruct->RXBD_RING_SIZE = 32; /* init rxbd ring size */
SDIO_InitStruct->RXBD_FREE_TH = 5; /* init AHB rx_blk_size */
}
/**
* @brief Initializes the SDIO registers according to the specified parameters
* in SDIO_InitStruct.
* @param SDIO_InitStruct: pointer to a SDIO_InitTypeDef structure that contains
* the configuration information for the SDIO peripheral.
* @retval none
*/
void SDIO_Init(SDIO_InitTypeDef* SDIOInit_Struct)
{
u16 Temp = 0;
/* Reset SDIO DMA */
HAL_SDIO_WRITE8(REG_SPDIO_CPU_RST_DMA, BIT_CPU_RST_SDIO_DMA);
/* initial TX BD */
HAL_SDIO_WRITE32(REG_SPDIO_TXBD_ADDR, SDIOInit_Struct->TXBD_BAR);
HAL_SDIO_WRITE16(REG_SPDIO_TXBD_SIZE, SDIOInit_Struct->TXBD_RING_SIZE);
/* Set TX_BUFF_UNIT_SIZE */
HAL_SDIO_WRITE8(REG_SPDIO_TX_BUF_UNIT_SZ, SDIOInit_Struct->TX_BUFFER_SIZE);
/* Set DISPATCH_TXAGG_PKT */
HAL_SDIO_WRITE32(REG_SPDIO_AHB_DMA_CTRL, HAL_SDIO_READ32(REG_SPDIO_AHB_DMA_CTRL)|BIT31);
/* Reset HW TX BD pointer */
HAL_SDIO_WRITE32(REG_SPDIO_TXBD_RPTR, HAL_SDIO_READ32(REG_SPDIO_TXBD_WPTR));
/* Init RX BD and RX Buffer */
HAL_SDIO_WRITE32(REG_SPDIO_RXBD_ADDR, SDIOInit_Struct->RXBD_BAR);
HAL_SDIO_WRITE16(REG_SPDIO_RXBD_SIZE, SDIOInit_Struct->RXBD_RING_SIZE);
/* Reset HW RX BD pointer */
HAL_SDIO_WRITE16(REG_SPDIO_RXBD_C2H_WPTR, HAL_SDIO_READ16(REG_SPDIO_RXBD_C2H_RPTR));
/* Set the threshold of free RX BD count to trigger interrupt */
HAL_SDIO_WRITE16(REG_SPDIO_RX_BD_FREE_CNT, SDIOInit_Struct->RXBD_FREE_TH);
/* Indicate Host this is a iNIC FW */
Temp = HAL_SDIO_READ16(REG_SPDIO_CCPWM2);
Temp |= CPWM2_INIC_FW_RDY_BIT;
Temp ^= CPWM2_TOGGLE_BIT;
HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, Temp);
}
/**
* @brief SDIO interrupt clear
* @note clear all interrupt of SDIO
* @retval None
*/
void SDIO_INTClear(void)
{
u16 IntStatus;
IntStatus = HAL_SDIO_READ16(REG_SPDIO_CPU_INT_STAS);
HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_STAS, IntStatus); // clean the ISR
}
/**
* @brief SDIO disable or enable interrupt by modify the interrupt mask
* @param IntMask: The bit map to enable the interrupt.
* This parameter can be one or combinations of the following values:
* @arg BIT_TXFIFO_H2C_OVF:
* @arg BIT_H2C_BUS_RES_FAIL:
* @arg BIT_H2C_DMA_OK:
* @arg BIT_C2H_DMA_OK:
* @arg BIT_H2C_MSG_INT:
* @arg BIT_RPWM1_INT:
* @arg BIT_RPWM2_INT:
* @arg BIT_SDIO_RST_CMD_INT:
* @arg BIT_RXBD_FLAG_ERR_INT:
* @arg BIT_RX_BD_AVAI_INT:
* @arg BIT_HOST_WAKE_CPU_INT:
* @param NewState: ENABLE or DISABLE.
* @retval None
*/
VOID SDIO_INTConfig(u16 IntMask, u32 NewState)
{
u16 IntMaskTmp = HAL_SDIO_READ16(REG_SPDIO_CPU_INT_MASK);
if (NewState == ENABLE) {
IntMaskTmp |= IntMask;
} else {
IntMaskTmp &= ~IntMask;
}
HAL_SDIO_WRITE16(REG_SPDIO_CPU_INT_MASK, IntMaskTmp);
}
/**
* @brief Get RPWM1 from host.
* @param none.
* @retval RPWM1 val.
*/
u8 SDIO_RPWM1_Get(void)
{
return HAL_SDIO_READ8(REG_SPDIO_CRPWM);
}
/**
* @brief Get RPWM2 from host.
* @param none.
* @retval RPWM2 val.
*/
u16 SDIO_RPWM2_Get(void)
{
return HAL_SDIO_READ16(REG_SPDIO_CRPWM2);
}
/**
* @brief Set CPWM1 to host
* @param Val: CPWM msg to send.
* @retval None
*/
void SDIO_CPWM1_Set(u8 Val)
{
u8 Temp = HAL_SDIO_READ8(REG_SPDIO_CCPWM);
Temp ^= CPWM1_TOGGLE_BIT;
Temp |= Val;
HAL_SDIO_WRITE8(REG_SPDIO_CCPWM, Temp);
}
/**
* @brief Set CPWM2 to host
* @param Val: CPWM msg to send.
* @param Newstate: DISABLE/ENABLE.
* @retval None
*/
void SDIO_CPWM2_Set(u16 Val, u32 Newstate)
{
u16 Temp = HAL_SDIO_READ16(REG_SPDIO_CCPWM2);
Temp ^= CPWM2_TOGGLE_BIT;
if (Newstate == ENABLE)
Temp |= Val;
else
Temp &= ~Val;
HAL_SDIO_WRITE16(REG_SPDIO_CCPWM2, Temp);
}
/**
* @brief Get RXBD read pointer, updated by SDIO IP.
* @param none
* @retval RXBD read pointer
*/
u16 SDIO_RXBD_RPTR_Get(void)
{
return HAL_SDIO_READ16(REG_SPDIO_RXBD_C2H_RPTR);
}
/**
* @brief Set RXBD write pointer, updated by cpu CM4 driver.
* @param Val: RXBD write pointer
* @retval none
*/
void SDIO_RXBD_WPTR_Set(u16 Val)
{
HAL_SDIO_WRITE16(REG_SPDIO_RXBD_C2H_WPTR, Val);
}
/**
* @brief Get TXBD write pointer, updated by SDIO IP.
* @param none
* @retval TXBD write pointer
*/
u16 SDIO_TXBD_WPTR_Get(void)
{
return HAL_SDIO_READ16(REG_SPDIO_TXBD_WPTR);
}
/**
* @brief Set TXBD read pointer, updated by CM4 driver.
* @param none
* @retval TXBD read pointer
*/
void SDIO_TXBD_RPTR_Set(u16 Val)
{
HAL_SDIO_WRITE16(REG_SPDIO_TXBD_RPTR, Val);
}
/**
* @brief Reset SDIO DMA.
* @param none
* @retval TXBD read pointer
*/
void SDIO_DMA_Reset(void)
{
HAL_SDIO_WRITE8(REG_SPDIO_CPU_RST_DMA, BIT_CPU_RST_SDIO_DMA);
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_sdio.c
|
C
|
apache-2.0
| 6,237
|
#include "ameba_soc.h"
SDIOH_InitTypeDef sdioh_init_para;
/**
* @brief Check SDIOH is busy or not.
* @param None
* @retval SDIOH busy status value:
* - HAL_BUSY: Busy
* - HAL_OK: Not Busy
*/
u32 SDIOH_Busy(void)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
u8 idle_level = sdioh_init_para.SDIOH_idle_level;
/* check the SD bus status */
if((psdioh->SD_BUS_STATUS & idle_level) == idle_level) {
/* check the CMD & DATA state machine */
if((psdioh->SD_CMD_STATE & SDIOH_CMD_FSM_IDLE) && (psdioh->SD_DATA_STATE & SDIOH_DATA_FSM_IDLE)) {
/* check the SD card module state machine */
if((psdioh->SD_TRANSFER & SDIOH_SD_MODULE_FSM_IDLE)) {
return HAL_OK;
} else {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "SD card module state machine isn't in the idle state !\r\n");
return HAL_BUSY;
}
} else {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "CMD or DATA state machine isn't in the idle state !!\r\n");
return HAL_BUSY;
}
} else {
DBG_PRINTF(MODULE_SDIO, LEVEL_INFO, "CMD or DAT[3:0] pin isn't in the idle state !!\r\n");
return HAL_BUSY;
}
}
/**
* @brief Check if some error occurs when SDIOH transfer.
* @param status: pointer to word which is used to save error status.
* @retval SDIOH status:
* - HAL_ERR_UNKNOWN: Some error occurs when transfer, detailed error information
* can be found in status parameter.
* - HAL_OK: No error occurs when transfer.
*/
u32 SDIOH_CheckTxError(u16 *status)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
if(psdioh->SD_TRANSFER & SDIOH_ERR_OCCUR) {
if(status != NULL)
*status = psdioh->SD_STATUS1 | (psdioh->SD_STATUS2 << 8);
return HAL_ERR_UNKNOWN;
} else
return HAL_OK;
}
/**
* @brief Wait some time for SDIOH tx done.
* @param timeout_us: timeout value in microseconds.
* @retval SDIOH tx status value:
* - HAL_TIMEOUT: SDIOH tx timeout.
* - HAL_OK: SDIOH tx done within a specified time.
*/
u32 SDIOH_WaitTxDone(u32 timeout_us)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
u32 tmp;
do {
tmp = psdioh->SD_TRANSFER & (SDIOH_TRANSFER_END | SDIOH_SD_MODULE_FSM_IDLE);
if(tmp == (SDIOH_TRANSFER_END | SDIOH_SD_MODULE_FSM_IDLE))
return HAL_OK;
DelayUs(1);
} while (timeout_us-- != 0);
return HAL_TIMEOUT;
}
/**
* @brief Wait some time for SDIOH DMA done.
* @param timeout_us: timeout value in microseconds.
* @retval SDIOH dma status:
* - HAL_TIMEOUT: SDIOH DMA timeout.
* - HAL_OK: SDIOH DMA done within a specified time.
*/
u32 SDIOH_WaitDMADone(u32 timeout_us)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
do {
if((psdioh->SD_TRANSFER & SDIOH_TRANSFER_END) && (!(psdioh->DMA_CRL3 & SDIOH_DMA_XFER))) {
SDIOH_DMAReset();
return HAL_OK;
}
DelayUs(1);
} while (timeout_us-- != 0);
return HAL_TIMEOUT;
}
/**
* @brief Get SDIOH interrupt status.
* @param timeout_us: None.
* @retval SDIOH interrupt status.
*/
u32 SDIOH_GetISR(void)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
return psdioh->SD_ISR;
}
/**
* @brief SDIOH interrupt configure.
* @param SDIO_IT: SDIOH interrupt source, which can be one or combination of the following values:
* @arg SDIOH_DMA_CTL_INT_EN
* @arg SDIOH_CARD_ERR_INT_EN
* @arg SDIOH_CARD_END_INT_EN
* @param newState: can be ENABLE or Disable
* @retval None.
*/
void SDIOH_INTConfig(u8 SDIO_IT, u32 newState)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
if(newState == ENABLE)
psdioh->SD_ISREN |= SDIO_IT;
else
psdioh->SD_ISREN &= ~SDIO_IT;
}
/**
* @brief Clear SDIOH pending interrupt status.
* @param SDIO_IT: SDIOH interrupt pending bit, which can be one or combination of the following values:
* @arg SDIOH_DMA_TRANSFER_DONE
* @arg SDIOH_CARD_ERROR
* @arg SDIOH_CARD_END
* @retval None.
*/
void SDIOH_INTClearPendingBit(u8 SDIO_IT)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
psdioh->SD_ISR = SDIO_IT;
}
/**
* @brief Check if SDIOH bus switch to a specified state in some time.
* @param status: SDIOH bus state, which can be 0 or 1:
* @arg 0: bus switch to low level
* @arg 1: bus switch to high level
* @param timeout_us: timeout value in microseconds.
* @retval None.
*/
u32 SDIOH_CheckBusState(u8 status, u32 timeout_us)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
u8 idle_level = sdioh_init_para.SDIOH_idle_level;
u32 tmp;
do {
tmp = psdioh->SD_BUS_STATUS & idle_level;
if(status) {
if(tmp == idle_level)
return HAL_OK;
} else {
if(tmp == 0)
return HAL_OK;
}
DelayUs(1);
} while (timeout_us-- != 0);
return HAL_TIMEOUT;
}
/**
* @brief Get SDIOH bus width.
* @param None.
* @retval Bus width: 0 or 1:
* 0: 1-bit bus
* 1: 4-bit bus
*/
u8 SDIOH_GetBusWidth(void)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
return psdioh->SD_CONFIG1 & SDIOH_MASK_BUS_WIDTH;
}
/**
* @brief Set SDIOH bus width.
* @param width: can be SDIOH_BUS_WIDTH_1BIT or SDIOH_BUS_WIDTH_4BIT.
* @retval None
*/
void SDIOH_SetBusWidth(u8 width)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
u8 tmp;
tmp = psdioh->SD_CONFIG1;
tmp &= ~SDIOH_MASK_BUS_WIDTH;
tmp |= (width & SDIOH_MASK_BUS_WIDTH);
psdioh->SD_CONFIG1 = tmp;
}
/**
* @brief Set SDIOH DMA configuration.
* @param dma_ctl: pointer to a SDIOH_DmaCtl structure which keep the dma parameters.
* @retval None
*/
void SDIOH_DMAConfig(SDIOH_DmaCtl *dma_ctl)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
u32 tmp= 0;
/* set block length and count */
if((dma_ctl->type) == SDIOH_DMA_NORMAL) {
/* 512 bytes (one block size) */
psdioh->SD_BYTE_CNT_L = 0;
psdioh->SD_BYTE_CNT_H = 2;
} else {
/* 64 bytes( CMD6, R2 response...) */
psdioh->SD_BYTE_CNT_L = SDIOH_C6R2_BUF_LEN;
psdioh->SD_BYTE_CNT_H = 0;
}
psdioh->SD_BLOCK_CNT_L = (dma_ctl->blk_cnt) & SDIOH_MASK_BLOCL_CNT_L;
psdioh->SD_BLOCK_CNT_H = ((dma_ctl->blk_cnt) >> 8) & SDIOH_MASK_BLOCL_CNT_H;
/* set the DMA control register */
psdioh->DMA_CRL1 = (dma_ctl->start_addr) & SDIOH_MASK_DRAM_SA; /* DMA start address (unit: 8 Bytes) */
psdioh->DMA_CRL2 = (dma_ctl->blk_cnt) & SDIOH_MASK_DMA_LEN; /* DMA transfer length (unit: 512 Bytes) */
if((dma_ctl->type) == SDIOH_DMA_64B)
tmp = SDIOH_DAT64_SEL;
else if((dma_ctl->type) == SDIOH_DMA_R2)
tmp = SDIOH_RSP17_SEL;
tmp |= (dma_ctl->op << SDIOH_SHIFT_DDR_WR);
psdioh->DMA_CRL3 = tmp;
/* clear pending interrupt */
SDIOH_INTClearPendingBit(SDIOH_DMA_TRANSFER_DONE | SDIOH_CARD_ERROR |SDIOH_CARD_END);
/* enable DMA transfer */
tmp = psdioh->DMA_CRL3;
tmp |= SDIOH_DMA_XFER;
psdioh->DMA_CRL3 = tmp;
}
/**
* @brief Reset SDIOH DMA configuration.
* @param None.
* @retval None
*/
void SDIOH_DMAReset(void)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
psdioh->SD_BYTE_CNT_L = 0;
psdioh->SD_BYTE_CNT_H = 0;
psdioh->SD_BLOCK_CNT_L = 0;
psdioh->SD_BLOCK_CNT_H = 0;
psdioh->DMA_CRL1 = 0;
psdioh->DMA_CRL2 = 0;
psdioh->DMA_CRL3 = 0;
}
/**
* @brief SDIOH send command to card.
* @param cmd_attrib: pointer to a SDIOH_CmdTypeDef structure which keeps the command attributes.
* @param timeout_us: timeout value
* @retval 0: Send command ok.
* Other values: error occurs
*/
u32 SDIOH_SendCommand(SDIOH_CmdTypeDef *cmd_attrib, u32 timeout_us)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
u8 cmd = cmd_attrib->idx, cmd_code, tmp;
u32 val0 = 0, ret;
ret = SDIOH_Busy();
if (ret != HAL_OK)
return ret;
/* set SD_CONFIGURE2 (0x581) */
val0 = SDIOH_CRC7_CAL_EN | (cmd_attrib->rsp_type);
if(cmd_attrib->rsp_crc_chk)
val0 |= SDIOH_CRC7_CHK_EN;
else
val0 |= SDIOH_CRC7_CHK_DIS;
if((cmd == SD_CMD_RdSingleBlk) || (cmd == SD_CMD_RdMulBlk) || (cmd == SD_CMD_SendTuningBlk))
val0 |= SDIOH_CRC16_CHK_EN;
else
val0 |= SDIOH_CRC16_CHK_DIS;
if((cmd == SD_CMD_WrBlk) || (cmd == SD_CMD_WrMulBlk))
val0 |= SDIOH_WAIT_WR_CRCSTA_TO_EN | SDIOH_IGNORE_WR_CRC_ERR_EN;
else
val0 |= SDIOH_WAIT_WR_CRCSTA_TO_DIS | SDIOH_IGNORE_WR_CRC_ERR_DIS;
if(cmd == SD_CMD_VolSwitch)
val0 |= SDIOH_WAIT_BUSY_END_DIS;
else
val0 |= SDIOH_WAIT_BUSY_END_EN;
psdioh->SD_CONFIG2 = val0;
/* set SD_CONFIGURE3 (0x582) */
val0 = SDIOH_STOP_STA_WAIT_BUSY_EN | SDIOH_SD30_CLK_STOP_DIS | SDIOH_SD20_CLK_STOP_DIS | \
SDIOH_SD_CMD_RESP_CHK_DIS | SDIOH_ADDR_MODE_SECTOR;
if((cmd == SD_CMD_RdMulBlk) || (cmd == SD_CMD_WrMulBlk) || (cmd == SD_CMD_StopXsmission))
val0 |= SDIOH_CMD_STA_WAIT_BUSY_DIS;
else
val0 |= SDIOH_CMD_STA_WAIT_BUSY_EN;
if((cmd == SD_CMD_VolSwitch) || (cmd == SD_CMD_StopXsmission))
val0 |= SDIOH_DATA_PHA_WAIT_BUSY_DIS;
else
val0 |= SDIOH_DATA_PHA_WAIT_BUSY_EN;
if((cmd_attrib->rsp_type) == SDIOH_NO_RESP)
val0 |= SDIOH_CMD_RESP_TO_DIS;
else
val0 |= SDIOH_CMD_RESP_TO_EN;
psdioh->SD_CONFIG3 = val0;
/* fill the command register */
psdioh->SD_CMD[0]= HOST_COMMAND | (cmd & 0x3F);
psdioh->SD_CMD[1] = ((cmd_attrib->arg) >> 24) & 0xFF;
psdioh->SD_CMD[2] = ((cmd_attrib->arg) >> 16) & 0xFF;
psdioh->SD_CMD[3] = ((cmd_attrib->arg) >> 8) & 0xFF;
psdioh->SD_CMD[4] = (cmd_attrib->arg) & 0xFF;
psdioh->SD_CMD[5] = 0x0;
/* set the command code */
switch (cmd) {
case SD_CMD_SwitchFunc:
case SD_CMD_SendSts:
cmd_code = ((cmd_attrib->data_present) == SDIOH_NO_DATA) ? \
SDIOH_SEND_CMD_GET_RSP : SDIOH_NORMAL_READ;
break;
case SD_CMD_SendTuningBlk:
cmd_code = SDIOH_TUNING;
break;
case SD_CMD_RdSingleBlk:
#if defined(SDIO) && (SDIO == EMMC)
case EMMC_CMD_SendExtCsd:
#endif
cmd_code = SDIOH_AUTO_READ2;
break;
case SD_CMD_RdMulBlk:
cmd_code = SDIOH_AUTO_READ1;
break;
case SD_CMD_WrBlk:
cmd_code = SDIOH_AUTO_WRITE2;
break;
case SD_CMD_WrMulBlk:
cmd_code = SDIOH_AUTO_WRITE1;
break;
case SD_CMD_SendScr:
cmd_code = SDIOH_NORMAL_READ;
break;
default:
cmd_code = SDIOH_SEND_CMD_GET_RSP;
}
tmp = psdioh->SD_TRANSFER;
tmp &= ~SDIOH_MASK_COM_CODE;
tmp |= cmd_code;
psdioh->SD_TRANSFER = tmp;
/* start to transfer */
psdioh->SD_TRANSFER |= SDIOH_START_TRANSFER;
if(timeout_us != 0)
ret = SDIOH_WaitTxDone(timeout_us);
return ret;
}
/**
* @brief SDIOH get command response.
* @param byte_index: which byte of the response to be read
* @retval the specified byte value of Response
*/
u8 SDIOH_GetResponse(u8 byte_index)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
return psdioh->SD_CMD[byte_index];
}
/**
* @brief Switch speed of SDIOH.
* @param clk_div: can be one of the following values:
* @arg SDIOH_CLK_DIV1: divide by 1
* @arg SDIOH_CLK_DIV2: divide by 2
* @arg SDIOH_CLK_DIV4: divide by 4
* @arg SDIOH_CLK_DIV8: divide by 8
* @param mode: mode selection, can be one of the following values:
* @arg SDIOH_SD20_MODE
* @retval None
* @note AmebaD only support SD20_MODE
*/
void SDIOH_SwitchSpeed(u8 clk_div, u8 mode)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
u32 value32;
u8 value8;
value32 = psdioh->CKGEN_CTL;
value32 &= ~SDIOH_MASK_CLKDIV;
value32 |= clk_div;
psdioh->CKGEN_CTL = value32;
value8 = psdioh->SD_CONFIG1;
value8 &= ~SDIOH_MASK_MODE_SEL;
value8 |= (mode << SDIOH_SHIFT_MODE_SEL);
psdioh->SD_CONFIG1 = value8;
}
/**
* @brief Configure SDIOH to initialization mode or not.
* @param NewState: can be ENABLE/DISABLE
* @param level: signal level, which can be @arg SDIOH_SIG_VOL_33.
* @retval 0: SDIOH is configured successfully
* others: SDIOH is fail to configure.
*/
u32 SDIOH_InitialModeCmd(u8 NewState, u8 Level)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
u32 ret = HAL_OK;
ret = SDIOH_Busy();
if (ret != HAL_OK) {
return ret;
}
if (NewState) {
psdioh->CKGEN_CTL = SDIOH_SD30_SAMP_CLK_VP1 | SDIOH_SD30_PUSH_CLK_VP0 | \
SDIOH_CRC_CLK_SSC | SDIOH_CLK_DIV4;
/* SDCLK (Card Identification mode) : 390.625 KHz */
psdioh->SD_CONFIG1 = (SDIOH_SD20_MODE << SDIOH_SHIFT_MODE_SEL) | \
SDIOH_CLK_DIV_BY_128 | SDIOH_INITIAL_MODE | SDIOH_SD30_ASYNC_FIFO_RST_N |\
(SDIOH_BUS_WIDTH_1BIT << SDIOH_SHIFT_BUS_WIDTH);
} else {
/* Switch to DS mode (3.3V) or SDR12 (1.8V). SDCLK (Data Transfer mode) : 25 MHz */
if(Level == SDIOH_SIG_VOL_18) {
psdioh->CKGEN_CTL = SDIOH_SD30_SAMP_CLK_VP1 | SDIOH_SD30_PUSH_CLK_VP0 | \
SDIOH_CRC_CLK_SSC | SDIOH_CLK_DIV4;
psdioh->SD_CONFIG1 = (SDIOH_SD30_MODE << SDIOH_SHIFT_MODE_SEL) | \
SDIOH_CLK_DIV_BY_128 | SDIOH_SD30_ASYNC_FIFO_RST_N |\
(SDIOH_BUS_WIDTH_1BIT << SDIOH_SHIFT_BUS_WIDTH);
} else {
psdioh->CKGEN_CTL = SDIOH_SD30_SAMP_CLK_VP1 | SDIOH_SD30_PUSH_CLK_VP0 | \
SDIOH_CRC_CLK_SSC | (SDIOH_CLK_DIV4);
psdioh->SD_CONFIG1 = (SDIOH_SD20_MODE << SDIOH_SHIFT_MODE_SEL) | \
SDIOH_CLK_DIV_BY_128 |(SDIOH_BUS_WIDTH_1BIT << SDIOH_SHIFT_BUS_WIDTH);
}
}
return ret;
}
/**
* @brief Initialize SDIOH peripheral.
* @param None
* @retval 0: SDIOH is initialized successfully
* others: SDIOH is fail to initialize
*/
u32 SDIOH_Init (u8 BusBitMode)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
u32 ret = HAL_OK;
u32 tmp, i = 0;
/* Set pin idle level */
if(BusBitMode == SDIOH_BUS_WIDTH_4BIT)
sdioh_init_para.SDIOH_idle_level = 0x1F;
else
sdioh_init_para.SDIOH_idle_level = 0x03;
/* SDIOH func & clock enable */
RCC_PeriphClockCmd(APBPeriph_SDIOH, APBPeriph_SDIOH_CLOCK, ENABLE);
/* Wait for SDIOH clock ready */
while(1) {
tmp = HAL_READ32(SYSTEM_CTRL_BASE, REG_HS_SDIO_CTRL);
if(tmp & BIT_HS_SDIOH_CLK_READY)
break;
DelayUs(1);
if(i++ > 10000) {
DBG_PRINTF(MODULE_SDIO, LEVEL_ERROR, "Wait SDIOH clock ready timeout !\r\n");
return HAL_TIMEOUT;
}
}
/* Enable interrupt */
psdioh->CARD_INT_EN = SDIOH_SDMMC_INT_EN;
psdioh->SRAM_CRL = SDIOH_LX_BURST_SIZE_64B | SDIOH_MAP_SEL_DEC;
psdioh->CARD_SELECT = SDIOH_CARD_SEL_SD_MODULE;
psdioh->CARD_STOP = SDIOH_TARGET_MODULE_SD;
/* Initial mode */
ret = SDIOH_InitialModeCmd(ENABLE, 0);
if (ret != HAL_OK) {
return ret;
}
psdioh->CARD_CLK_EN_CTL = SDIOH_SD_CARD_MOUDLE_EN;
return ret;
}
/**
* @brief De-initialize SDIOH peripheral.
* @param None
* @retval None
*/
void SDIOH_DeInit (void)
{
SDIOH_TypeDef *psdioh = SDIOH_BASE;
/* disable interrupt & clear all pending interrupts */
psdioh->CARD_INT_PEND |= SDIOH_SDMMC_INT_PEND;
psdioh->CARD_INT_EN &= ~ SDIOH_SDMMC_INT_EN;
SDIOH_INTClearPendingBit(SDIOH_SD_ISR_ALL);
SDIOH_INTConfig(SDIOH_SD_ISR_ALL, DISABLE);
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_sdio_host.c
|
C
|
apache-2.0
| 14,280
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "ameba_soc.h"
VOID app_simulation_task(VOID *Data)
{
/* To avoid gcc warnings */
( void ) Data;
//u8 *argv[6];
static u32 test_done = 0;
do{
/* this is an example, you can change to yourself code if needed */
if (test_done == 0) {
simulation_stage_set(SIMULATION_KM0_CPUID, BIT_KM0_SIMULATION_START);
#if 0
//add simulation code here
argv[1] = "0";
argv[2] = "1";
argv[3] = "0";
argv[4] = "0";
argv[5] = "1";
AudioTestVera(argv);
#endif
test_done = 1;
simulation_stage_set(SIMULATION_KM0_CPUID, BIT_KM0_SIMULATION_END);
} else {
vTaskDelay(1000);
}
} while (1);
}
VOID app_simulation_init(VOID *Data)
{
/* To avoid gcc warnings */
( void ) Data;
if (pdTRUE != xTaskCreate(app_simulation_task, (const char * const)"simulation_task", 1024,
NULL, tskIDLE_PRIORITY + 5 , NULL))
{
DiagPrintf("Create simulation_task Err!!\n");
}
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_simulation.c
|
C
|
apache-2.0
| 1,151
|
/**
******************************************************************************
* @file rtl8721dhp_ssi.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file contains all the functions prototypes for Serial peripheral interface (SPI):
* - Initialization
* - Clock polarity and phase setting
* - SPI data frame size setting
* - SPI baud rate setting
* - Receive/Send data interface
* - Get TRx FIFO valid entries
* - check SPI device busy status
* - SPI device pinmux initialization and deinitialization
* - DMA transfers management
* - Interrupts and management
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/** @addtogroup SPI_Exported_Functions
*@verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable peripheral clock using the following functions
* RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE) for SPI0;
* RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE) for SPI1;
*
* 2. Configure the SPIx pinmux.
* PinCtrl(PERIPHERAL_SPI0, PinmuxSelect, ON) for SPI0;
* PinCtrl(PERIPHERAL_SPI1, PinmuxSelect, ON) for SPI1;
*
* 3. Disable the SPI using the SSI_Cmd() function
*
* 4. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
* the SSI_Init() function.
*
* 5. Enable the SPI using the SSI_Cmd() function
*
* 6. When using poll:
* -Using SSI_Writeable() function make sure that the transmit FIFO is not full,
* then using SSI_WriteData() function to send data
*
* -Using SSI_Readable() function make sure that the receive FIFO is not empty,
* then using SSI_ReadData() function to receive data
*
* 7. Enable corresponding interrupt using the function SSI_INTConfig() if you need to
* use interrupt mode.
*
* 8. When using the DMA mode
* - Configure & Initialize the DMA
* - Active the DMA Tx or Rx using SSI_SetDmaEnable() function
*
* @endverbatim
*/
const SPI_DevTable SPI_DEV_TABLE[2] = {
{SPI0_DEV, GDMA_HANDSHAKE_INTERFACE_SPI0_TX, GDMA_HANDSHAKE_INTERFACE_SPI0_RX, SPI0_IRQ},
{SPI1_DEV, GDMA_HANDSHAKE_INTERFACE_SPI1_TX, GDMA_HANDSHAKE_INTERFACE_SPI1_RX, SPI1_IRQ},
};
/**
* @brief Fills each SSI_InitStruct member with its default value.
* @param SSI_InitStruct: pointer to a SSI_InitTypeDef structure which will be
* initialized.
* @retval None
*/
void
SSI_StructInit(SSI_InitTypeDef* SSI_InitStruct)
{
SSI_InitStruct->SPI_RxThresholdLevel = 0; // if number of entries in th RX FIFO >= (RxThresholdLevel+1), RX interrupt asserted
SSI_InitStruct->SPI_TxThresholdLevel = 32; // if number of entries in th TX FIFO <= TxThresholdLevel, TX interrupt asserted
SSI_InitStruct->SPI_DmaRxDataLevel = 3;
#ifdef SPI_SLAVE_TXERR_WORK_AROUND
SSI_InitStruct->SPI_DmaTxDataLevel = 48;
#else
SSI_InitStruct->SPI_DmaTxDataLevel = 56;
#endif
SSI_InitStruct->SPI_SlaveSelectEnable = 0;
SSI_InitStruct->SPI_ClockDivider = 6;
SSI_InitStruct->SPI_DataFrameNumber = 0;
SSI_InitStruct->SPI_DataFrameFormat = FRF_MOTOROLA_SPI;
SSI_InitStruct->SPI_DataFrameSize = DFS_8_BITS;
SSI_InitStruct->SPI_InterruptMask = 0x0;
SSI_InitStruct->SPI_SclkPhase = SCPH_TOGGLES_AT_START;
SSI_InitStruct->SPI_SclkPolarity = SCPOL_INACTIVE_IS_HIGH;
SSI_InitStruct->SPI_TransferMode = TMOD_TR;
SSI_InitStruct->SPI_MicrowireControlFrameSize = CFS_1_BIT;
SSI_InitStruct->SPI_MicrowireDirection = MW_DIRECTION_MASTER_TO_SLAVE;
SSI_InitStruct->SPI_MicrowireHandshaking = MW_HANDSHAKE_DISABLE;
SSI_InitStruct->SPI_MicrowireTransferMode = MW_TMOD_NONSEQUENTIAL;
}
/**
* @brief Initializes the SPI registers according to the specified parameters
* in SSI_InitStruct.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param SSI_InitStruct: pointer to a SSI_InitTypeDef structure that contains
* the configuration information for the SPI peripheral.
* @retval None
*/
void SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct)
{
u32 TempValue = 0;
SSI_Cmd(spi_dev, DISABLE);
/* REG_DW_SSI_CTRLR0 */
TempValue |= SSI_InitStruct->SPI_DataFrameSize;
TempValue |= (SSI_InitStruct->SPI_DataFrameFormat << 4);
TempValue |= (SSI_InitStruct->SPI_SclkPhase << 6);
TempValue |= (SSI_InitStruct->SPI_SclkPolarity << 7);
TempValue |= (SSI_InitStruct->SPI_TransferMode << 8);
TempValue |= (SSI_InitStruct->SPI_MicrowireControlFrameSize << 12);
TempValue &= ~BIT_CTRLR0_SLV_OE;//(SlaveOutputEnable);
spi_dev->CTRLR0 = TempValue;
/* REG_DW_SSI_TXFTLR */
spi_dev->TXFTLR = SSI_InitStruct->SPI_TxThresholdLevel;
/* REG_DW_SSI_RXFTLR */
spi_dev->RXFTLR = SSI_InitStruct->SPI_RxThresholdLevel;
/* Master Only:REG_DW_SSI_CTRLR1, REG_DW_SSI_SER, REG_DW_SSI_BAUDR*/
if (SSI_InitStruct->SPI_Role & SSI_MASTER) {
spi_dev->CTRLR1 = SSI_InitStruct->SPI_DataFrameNumber;
SSI_SetSlaveEnable(spi_dev, SSI_InitStruct->SPI_SlaveSelectEnable);
spi_dev->BAUDR = SSI_InitStruct->SPI_ClockDivider;
}
// Microwire
TempValue = 0;
TempValue |= SSI_InitStruct->SPI_MicrowireTransferMode;
TempValue |= (SSI_InitStruct->SPI_MicrowireDirection << 1);
TempValue |= (SSI_InitStruct->SPI_MicrowireHandshaking << 2);
spi_dev->MWCR = TempValue;
/* REG_DW_SSI_IMR */
spi_dev->IMR = SSI_InitStruct->SPI_InterruptMask;
/*DMA level set */
SSI_SetDmaLevel(spi_dev, SSI_InitStruct->SPI_DmaTxDataLevel, SSI_InitStruct->SPI_DmaRxDataLevel);
SSI_Cmd(spi_dev, ENABLE);
}
/**
* @brief Enables or disables SPIx peripheral.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param NewStatus: This parameter can be one of the following values:
* @arg ENABLE
* @arg DISABLE
* @retval None
*/
void SSI_Cmd(SPI_TypeDef *spi_dev, u32 NewStatus)
{
if (NewStatus != DISABLE) {
spi_dev->SSIENR |= BIT_SSIENR_SSI_EN;
} else {
spi_dev->SSIENR &= ~BIT_SSIENR_SSI_EN;
}
}
/**
* @brief Masks or unmasks SPIx interrupt.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param SSI_IT: This parameter can be one of the following values or mixed:
* @arg BIT_IMR_TXEIM
* @arg BIT_IMR_TXOIM
* @arg BIT_IMR_RXUIM
* @arg BIT_IMR_RXOIM
* @arg BIT_IMR_RXFIM
* @arg BIT_IMR_MSTIM
* @arg BIT_IMR_FAEIM
* @arg BIT_IMR_TXUIM
* @arg BIT_IMR_SSRIM
* @param newState:This parameter can be one of the following values:
* @arg ENABLE
* @arg DISABLE
* @retval None
* @note BIT_IMR_MSTIM is for Master only, and BIT_IMR_FAEIM, BIT_IMR_TXUIM, BIT_IMR_SSRIM
* are for Slave only.
*/
VOID
SSI_INTConfig(SPI_TypeDef* spi_dev, u32 SSI_IT, u32 newState)
{
if (newState == ENABLE) {
/* Enable the selected SSI interrupts */
spi_dev->IMR |= SSI_IT;
} else {
/* Disable the selected SSI interrupts */
spi_dev->IMR &= ~SSI_IT;
}
}
/**
* @brief Set SPI0 as Master or Slave.
* @param spi_dev: where spi_dev can be SPI0_DEV.
* @param role: This parameter can be one of the following values:
* @arg SSI_MASTER
* @arg SSI_SLAVE
* @retval None
*/
void SSI_SetRole(SPI_TypeDef *spi_dev, u32 role)
{
u32 Temp;
assert_param(spi_dev == SPI0_DEV);
Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_HS_SPI_CTRL);
Temp &= ~BIT_HS_SPI0_ROLE_SELECT;
Temp |= (role << 3);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_HS_SPI_CTRL, Temp);
}
/**
* @brief Set SPIx clock polarity.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param SclkPolarity: This parameter can be one of the following values:
* @arg SCPOL_INACTIVE_IS_HIGH
* @arg SCPOL_INACTIVE_IS_LOW
* @retval None
*/
void SSI_SetSclkPolarity(SPI_TypeDef *spi_dev, u32 SclkPolarity)
{
u32 Ctrlr0Value;
Ctrlr0Value = spi_dev->CTRLR0;
Ctrlr0Value &= ~BIT_CTRLR0_SCPOL;
Ctrlr0Value |= (SclkPolarity << 7);
SSI_Cmd(spi_dev, DISABLE);
spi_dev->CTRLR0 = Ctrlr0Value;
SSI_Cmd(spi_dev, ENABLE);
}
/**
* @brief Set SPIx clock phase.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param SclkPhase: This parameter can be one of the following values:
* @arg SCPH_TOGGLES_AT_START
* @arg SCPH_TOGGLES_IN_MIDDLE
* @retval None
*/
void SSI_SetSclkPhase(SPI_TypeDef *spi_dev, u32 SclkPhase)
{
u32 Ctrlr0Value;
Ctrlr0Value = spi_dev->CTRLR0;
Ctrlr0Value &= ~BIT_CTRLR0_SCPH;
Ctrlr0Value |= (SclkPhase << 6);
SSI_Cmd(spi_dev, DISABLE);
spi_dev->CTRLR0 = Ctrlr0Value;
SSI_Cmd(spi_dev, ENABLE);
}
/**
* @brief Set SPIx data frame size.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param DataFrameSize: This parameter can be one of the following values:
* @arg DFS_4_BITS
* @arg DFS_5_BITS
* @arg DFS_6_BITS
* @arg DFS_7_BITS
* @arg DFS_8_BITS
* @arg DFS_9_BITS
* @arg DFS_10_BITS
* @arg DFS_11_BITS
* @arg DFS_12_BITS
* @arg DFS_13_BITS
* @arg DFS_14_BITS
* @arg DFS_15_BITS
* @arg DFS_16_BITS
* @retval None
*/
void SSI_SetDataFrameSize(SPI_TypeDef *spi_dev, u32 DataFrameSize)
{
u32 Ctrlr0Value;
Ctrlr0Value = spi_dev->CTRLR0;
Ctrlr0Value &= ~BIT_CTRLR0_DFS;
Ctrlr0Value |= DataFrameSize;
SSI_Cmd(spi_dev, DISABLE);
spi_dev->CTRLR0 = Ctrlr0Value;
SSI_Cmd(spi_dev, ENABLE);
}
/**
* @brief Set SPI SS Toggle Phase.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param TogglePhase: This parameter can be one of the following values:
* @arg SPI_SS_NOT_TOGGLE , means SPI support continuous transfer when spi_cph=0
* @arg SPI_SS_TOGGLE, means SPI donot support continuous transfer when spi_cph=0
* and SS(CS) needs break.
* @retval None
* @note SS Toggle function is valid only for master.
*/
void SSI_SetSSTogglePhase(SPI_TypeDef *spi_dev, u32 TogglePhase)
{
u32 Ctrlr0Value;
Ctrlr0Value = spi_dev->CTRLR0;
Ctrlr0Value &= ~BIT_CTRLR0_SSTOGGLE;
Ctrlr0Value |= (TogglePhase << 31);
SSI_Cmd(spi_dev, DISABLE);
spi_dev->CTRLR0 = Ctrlr0Value;
SSI_Cmd(spi_dev, ENABLE);
}
/**
* @brief Set or reset SPIx data swap bit.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param SwapStatus: This parameter can be one of the following values or mixed:
* @arg BIT_CTRLR0_TXBYTESWP
* @arg BIT_CTRLR0_TXBITSWP
* @arg BIT_CTRLR0_RXBYTESWP
* @arg BIT_CTRLR0_RXBITSWP
* @param newState:This parameter can be one of the following values:
* @arg ENABLE
* @arg DISABLE
* @retval None
*/
void SSI_SetDataSwap(SPI_TypeDef *spi_dev, u32 SwapStatus, u32 newState)
{
u32 Ctrlr0Value = spi_dev->CTRLR0;
if(newState == ENABLE)
Ctrlr0Value |= SwapStatus;
else
Ctrlr0Value &= ~SwapStatus;
SSI_Cmd(spi_dev, DISABLE);
spi_dev->CTRLR0 = Ctrlr0Value;
SSI_Cmd(spi_dev, ENABLE);
}
/**
* @brief Set SPIx Rx Sample Dealy. support form AZ BCUT
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param SampleDelay: The number of ssi_clk cycles that to be delayed.
* @retval None
*/
void SSI_SetSampleDelay(SPI_TypeDef *spi_dev, u32 SampleDelay)
{
SSI_Cmd(spi_dev, DISABLE);
spi_dev->RX_SAMPLE_DLY = (SampleDelay & BIT_RX_SAMPLE_DELAY);
SSI_Cmd(spi_dev, ENABLE);
}
/**
* @brief Set SPI1 the number of data frame to be received.
* @note Valid only when the device is configured as a master in following mode:
* TMOD_RO || TMOD_EEPROM_R || (FRF_NS_MICROWIRE && MW_TMOD_SEQUENTIAL)
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param DataFrameNumber: The number of data frames that to be received.
* @retval None
*/
void SSI_SetReadLen(SPI_TypeDef *spi_dev, u32 DataFrameNumber)
{
assert_param((DataFrameNumber >= 1)&&(DataFrameNumber <= 0x10000));
SSI_Cmd(spi_dev, DISABLE);
spi_dev->CTRLR1 = DataFrameNumber - 1;
SSI_Cmd(spi_dev, ENABLE);
}
/**
* @brief Set SPI1 clock divider.
* @note Valid only when the device is configured as a master.
* And The LSB is always set to 0,and is unaffected by a write operation.
* @param spi_dev: where spi_dev can only be SPI1_DEV.
* @param ClockDivider: Even value between 2 and 65534.
* And Fsclk_out=Fssi_clk/ClockDivider.
* @retval None
*/
void SSI_SetBaudDiv(SPI_TypeDef *spi_dev, u32 ClockDivider)
{
SSI_Cmd(spi_dev, DISABLE);
spi_dev->BAUDR = (ClockDivider & BIT_BAUDR_SCKDV);
SSI_Cmd(spi_dev, ENABLE);
}
/**
* @brief Enables or disables SPIx TDMA and RDMA .
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param newState: This parameter can be one of the following values:
* @arg ENABLE
* @arg DISABLE
* @param Mask: This parameter can be one of the following values or mixed:
* @arg BIT_SHIFT_DMACR_RDMAE
* @arg BIT_SHIFT_DMACR_TDMAE
* @retval None
*/
void SSI_SetDmaEnable(SPI_TypeDef *spi_dev, u32 newState, u32 Mask)
{
if (newState == DISABLE)
spi_dev->DMACR &= ~Mask;
else
spi_dev->DMACR |= Mask;
}
/**
* @brief Set SPIx DMA TxLevel and RxLevel.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param TxLevel: Transmit FIFO Threshold level.Value range: 0 to 63.
* The dma_tx_req is generated when the number of valid data entries in
* the transmit FIFO is equal to or below this field value.
* @param RxLevel: Receive FIFO Threshold level.Value range: 0 to 63.
* The dma_rx_req is generated when the number of valid data entries in the
* receive FIFO is equal to or above this field value + 1.
* @retval None
*/
void SSI_SetDmaLevel(SPI_TypeDef *spi_dev, u32 TxLevel, u32 RxLevel)
{
/* Set TX FIFO water level to trigger Tx DMA transfer */
spi_dev->DMATDLR = TxLevel;
/* Set RX FIFO water level to trigger Rx DMA transfer */
spi_dev->DMARDLR = RxLevel;
}
/**
* @brief Init and Enable SPI TX GDMA.
* @param Index: 0 or 1.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pTxData: Tx Buffer.
* @param Length: Tx Count.
* @retval TRUE/FLASE
*/
BOOL SSI_TXGDMA_Init(
u32 Index,
PGDMA_InitTypeDef GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pTxData,
u32 Length
)
{
SPI_TypeDef *SPIx = SPI_DEV_TABLE[Index].SPIx;
u32 DataFrameSize = SSI_GetDataFrameSize(SPIx);
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, CallbackFunc, (u32)CallbackData, 12);//ACUT is 0x10, BCUT is 12
if (GdmaChnl == 0xFF) {
// No Available DMA channel
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->GDMA_DIR = TTFCMemToPeri;
GDMA_InitStruct->GDMA_DstHandshakeInterface = SPI_DEV_TABLE[Index].Tx_HandshakeInterface;
GDMA_InitStruct->GDMA_DstAddr = (u32)&SPI_DEV_TABLE[Index].SPIx->DR;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_SrcMsize = MsizeOne;
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_DstInc = NoChange;
GDMA_InitStruct->GDMA_SrcInc = IncType;
/* Cofigure GDMA transfer */
if (DataFrameSize > 8) {
/* 16~9 bits mode */
if (((Length & 0x03)==0) && (((u32)(pTxData) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_DstMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 2;
} else if (((Length & 0x01)==0) && (((u32)(pTxData) & 0x01)==0)) {
/* 2-bytes aligned, move 2 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeEight;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_DstMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 1;
} else {
DBG_8195A("SSI_TXGDMA_Init: Aligment Err: pTxData=0x%x, Length=%d\n", pTxData, Length);
return _FALSE;
}
} else {
/* 8~4 bits mode */
if (((Length & 0x03)==0) && (((u32)(pTxData) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeOne;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 2;
} else {
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_BlockSize = Length;
}
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
}
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
GDMA_InitStruct->GDMA_SrcAddr = (u32)pTxData;
/* Enable GDMA for TX */
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Init and Enable SPI RX GDMA.
* @param Index: 0 or 1.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pRxData: Rx Buffer.
* @param Length: Rx Count.
* @retval TRUE/FLASE
*/
BOOL
SSI_RXGDMA_Init(
u8 Index,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pRxData,
u32 Length
)
{
SPI_TypeDef *SPIx = SPI_DEV_TABLE[Index].SPIx;
u32 DataFrameSize = SSI_GetDataFrameSize(SPIx);
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, CallbackFunc, (u32)CallbackData, 12);//ACUT is 0x10, BCUT is 12
if (GdmaChnl == 0xFF) {
// No Available DMA channel
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem;
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->GDMA_SrcHandshakeInterface = SPI_DEV_TABLE[Index].Rx_HandshakeInterface;
GDMA_InitStruct->GDMA_SrcAddr = (u32)&SPI_DEV_TABLE[Index].SPIx->DR;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_SrcMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_DstInc = IncType;
GDMA_InitStruct->GDMA_SrcInc = NoChange;
/* Cofigure GDMA transfer */
if (DataFrameSize > 8) {
/* 16~9 bits mode */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 1;
if (((Length & 0x03)==0) && (((u32)(pRxData) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
} else if (((Length & 0x01)==0) && (((u32)(pRxData) & 0x01)==0)) {
/* 2-bytes aligned, move 2 bytes each transfer */
GDMA_InitStruct->GDMA_DstMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthTwoBytes;
} else {
DBG_8195A("SSI_RXGDMA_Init: Aligment Err: pTxData=0x%x, Length=%d\n", pRxData, Length);
return _FALSE;
}
} else {
/* 8~4 bits mode */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_BlockSize = Length;
if (((Length & 0x03)==0) && (((u32)(pRxData) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_DstMsize = MsizeOne;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
} else {
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
}
}
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
GDMA_InitStruct->GDMA_DstAddr = (u32)pRxData;
/* Enable GDMA for RX */
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Clear SPIx interrupt status.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param InterruptStatus: The value of current interrupt status .
* @retval None
*/
void SSI_SetIsrClean(SPI_TypeDef *spi_dev, u32 InterruptStatus)
{
if (InterruptStatus & BIT_ISR_TXOIS) {
spi_dev->TXOICR;
}
if (InterruptStatus & BIT_ISR_RXUIS) {
spi_dev->RXUICR;
}
if (InterruptStatus & BIT_ISR_RXOIS) {
spi_dev->RXOICR;
}
if (InterruptStatus & BIT_ISR_MSTIS) {
/* Another master is actively transferring data */
/* TODO: Do reading data... */
spi_dev->MSTICR;
}
if(InterruptStatus & BIT_ISR_TXUIS) {
/* For slave only. This register is used as TXUICR in slave mode*/
spi_dev->IDR;
}
if(InterruptStatus & BIT_ISR_SSRIS) {
/* For slave only. This register is used as SSRICR in slave mode*/
spi_dev->SSI_COMP_VERSION;
}
}
/**
* @brief Write data to SPIx transmit FIFO.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param value: The data value that is to be transmitted .
* @retval None
*/
void SSI_WriteData(SPI_TypeDef *spi_dev, u32 value)
{
spi_dev->DR[0] = (value & BIT_DR_DR);
}
/**
* @brief Set SPIx Rx FIFO threshold level
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param RxThresholdLevel: Rx FIFO Threshold Level.Value range: 0 to 63.
* When the number of receive FIFO entries is greater than or equal to
* this value + 1, the receive FIFO full interrupt is triggered.
* @retval None
*/
void SSI_SetRxFifoLevel(SPI_TypeDef *spi_dev, u32 RxThresholdLevel)
{
spi_dev->RXFTLR = RxThresholdLevel;
}
/**
* @brief Set SPIx Tx FIFO threshold level.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param TxThresholdLevel: Tx FIFO Threshold Level.Value range: 0 to 63.
* When the number of transmit FIFO entries is less than or equal to this
* value, the transmit FIFO empty interrupt is triggered.
* @retval None
*/
void SSI_SetTxFifoLevel(SPI_TypeDef *spi_dev, u32 TxThresholdLevel)
{
spi_dev->TXFTLR = TxThresholdLevel;
}
/**
* @brief Enables or disables slave .
* @note Valid only when the device is configured as a master.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param SlaveIndex: the index of slave to be selected.
* @retval None
*/
void SSI_SetSlaveEnable(SPI_TypeDef *spi_dev, u32 SlaveIndex)
{
if (SSI_Busy(spi_dev)) {
DBG_8195A("SSI%d is busy\n", SlaveIndex);
return;
}
spi_dev->SER = (1 << SlaveIndex);
}
/**
* @brief Detemines whether SPIx transmit FIFO is full or not
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval Transmit FIFO is full or not:
* - 1: Not Full
* - 0: Full
*/
u32 SSI_Writeable(SPI_TypeDef *spi_dev)
{
u8 status = 0;
u32 value = 0;
#ifdef SPI_SLAVE_TXERR_WORK_AROUND
value = SSI_GetTxCount(spi_dev);
status = ((value < SSI_TX_FIFO_DEPTH - 1) ? 1 : 0);
#else
value = SSI_GetStatus(spi_dev);
status = (((value & BIT_SR_TFNF) != 0) ? 1 : 0);
#endif
return status;
}
/**
* @brief Detemine SPIx Receive FIFO is empty or not.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval Receive FIFO is empty or not:
* - 1: Not Empty
* - 0: Empty
*/
u32 SSI_Readable(SPI_TypeDef *spi_dev)
{
u32 Status = SSI_GetStatus(spi_dev);
u32 Readable = (((Status & BIT_SR_RFNE) != 0) ? 1 : 0);
return Readable;
}
/**
* @brief Read data from SPIx receive FIFO .
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval The data received.
*/
u32 SSI_ReadData(SPI_TypeDef *spi_dev)
{
return spi_dev->DR[0];
}
/**
* @brief receive data from rx FIFO
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param RxData: buffer to save data read from SPI FIFO.
* @param Length: number of data to be read.
* @retval transfer len
*/
u32 SSI_ReceiveData(SPI_TypeDef *spi_dev,
void* RxData,
u32 Length
)
{
u32 ReceiveLevel;
u32 DataFrameSize = SSI_GetDataFrameSize(spi_dev);
volatile u32 Readable = SSI_Readable(spi_dev);
u32 RxLength = Length;
while (Readable) {
ReceiveLevel = SSI_GetRxCount(spi_dev);
while (ReceiveLevel--) {
if (RxData != NULL) {
if (DataFrameSize > 8) {
/* 16~9 bits mode */
*((u16*)(RxData)) = (u16)SSI_ReadData(spi_dev);
RxData = (VOID*)(((u16*)RxData) + 1);
} else {
/* 8~4 bits mode */
*((u8*)(RxData)) = (u8)SSI_ReadData(spi_dev);
RxData = (VOID*)(((u8*)RxData) + 1);
}
} else {
/* for Master mode, doing TX also will got RX data, so drop the dummy data */
SSI_ReadData(spi_dev);
}
if (RxLength > 0) {
RxLength--;
}
if (RxLength == 0) {
break;
}
}
if (RxLength == 0) {
break;
}
Readable = SSI_Readable(spi_dev);
}
return (Length - RxLength);
}
/**
* @brief Send data to tx FIFO
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @param TxData: buffer to be written to Tx FIFO.
* @param Length: number of data to be written.
* @param Role: SSI_MASTER or SSI_SLAVE.
* @retval transfer len
*/
u32 SSI_SendData(SPI_TypeDef *spi_dev,
void* TxData,
u32 Length,
u32 Role
)
{
u32 Writeable = SSI_Writeable(spi_dev);
u32 TxWriteMax = SSI_TX_FIFO_DEPTH - SSI_GetTxCount(spi_dev);
u32 DataFrameSize = SSI_GetDataFrameSize(spi_dev);
u32 TxLength = Length;
#ifdef SPI_SLAVE_TXERR_WORK_AROUND
if (Role == SSI_SLAVE)
TxWriteMax = (TxWriteMax > 0) ? (TxWriteMax - 1) : 0;
#endif
if (Writeable) {
/* Disable Tx FIFO Empty IRQ */
SSI_INTConfig(spi_dev, BIT_IMR_TXEIM, DISABLE);
while (TxWriteMax--) {
if (DataFrameSize > 8) {
// 16~9 bits mode
if (TxData != NULL) {
SSI_WriteData(spi_dev, *((u16*)(TxData)));
TxData = (VOID*)(((u16*)TxData) + 1);
} else {
// For master mode: Push a dummy to TX FIFO for Read
if (Role == SSI_MASTER) {
SSI_WriteData(spi_dev, (u16)0);// Dummy byte
}
}
} else {
// 8~4 bits mode
if (TxData != NULL) {
SSI_WriteData(spi_dev, *((u8*)(TxData)));
TxData = (VOID*)(((u8*)TxData) + 1);
} else {
// For master mode: Push a dummy to TX FIFO for Read
if (Role == SSI_MASTER) {
SSI_WriteData(spi_dev, (u8)0);// Dummy byte
}
}
}
TxLength--;
if (TxLength == 0)
break;
}
/* Enable Tx FIFO Empty IRQ */
SSI_INTConfig(spi_dev, BIT_IMR_TXEIM, ENABLE);
}
return (Length - TxLength);
}
/**
* @brief Get SPIx the number of valid entries in receive FIFO.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval The number of valid entries in receive FIFO.Value range:0-64.
*/
u32 SSI_GetRxCount(SPI_TypeDef *spi_dev)
{
return spi_dev->RXFLR & BIT_MASK_RXFLR_RXTFL;
}
/**
* @brief Get SPIx the number of valid entries in transmit FIFO.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval The number of valid entries in transmit FIFO.Value range:0-64.
*/
u32 SSI_GetTxCount(SPI_TypeDef *spi_dev)
{
return spi_dev->TXFLR & BIT_MASK_TXFLR_TXTFL;
}
/**
* @brief Get SPIx transfer status.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval Current transfer status,each bit of this value represents one
* transfer status which is as follows:
*
* bit 6 : DCOL Data Collision Error.(valid when device is master)
* - 0 : No Error
* - 1 : Transmit data collision error
*
* bit 5 : TXE Transmission Error.(valid when device is slave)
* - 0 : No Error
* - 1 : Transmission error
*
* bit 4 : RFF Receive FIFO Full.
* - 0 : Receive FIFO is not full
* - 1 : Receive FIFO is full
*
* bit 3 : RFNE Receive FIFO Not Empty.
* - 0 : Receive FIFO is empty
* - 1 : Receive FIFO is not empty
*
* bit 2 : TFE Transmit FIFO Empty.
* - 0 : Transmit FIFO is not empty
* - 1 : Transmit FIFO is empty
*
* bit 1 : TFNF Transmit FIFO Not Full.
* - 0 : Transmit FIFO is full
* - 1 : Transmit FIFO is not full
*
* bit 0 : BUSY SSI Busy Flag.
* - 0 : idle or disable
* - 1 : active transferring data
*
*/
u32 SSI_GetStatus(SPI_TypeDef *spi_dev)
{
return spi_dev->SR;
}
/**
* @brief Get SPIx data frame size.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval Data frame size(value range : 4-16):
* - n : current data frame length is n bits
*/
u32 SSI_GetDataFrameSize(SPI_TypeDef *spi_dev)
{
u32 size = ((spi_dev->CTRLR0) & BIT_CTRLR0_DFS) + 1;
return size;
}
/**
* @brief Detemine SPIx is busy or not.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval SPIx busy status value:
* - 1: Busy
* - 0: Not Busy
*/
u32 SSI_Busy(SPI_TypeDef *spi_dev)
{
u32 Status = SSI_GetStatus(spi_dev);
u32 Busy = (((Status & BIT_SR_BUSY) != 0) ? 1 : 0);
return Busy;
}
/**
* @brief Get SPIx Interrupt Status.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval Current Interrupt Status,each bit of this value represents one
* interrupt status which is as follows:
*
* bit 7 : SSRIS SS_N Rising Edge Detect Interrupt Status. (valid when device is slave)
* - 0 : ssi_ssr_intr interrupt not active after masking
* - 1 : ssi_ssr_intr interrupt is active after masking
*
* bit 6 : TXUIS Transmit FIFO Under Flow Interrupt Status. (valid when device is slave)
* - 0 : ssi_txu_intr interrupt is not active after masking
* - 1 : ssi_txu_intr interrupt is active after masking
*
* bit 5 : FAEIS Frame Alignment Interrupt Status. (valid when device is slave)
* - 0 : ssi_fae_intr interrupt not active after masking
* - 1 : ssi_fae_intr interrupt is active after masking
*
* bit 5 : MSTIS Multi-Master Contention Interrupt Status. (valid when device is master)
* - 0 : ssi_mst_intr interrupt not active after masking
* - 1 : ssi_mst_intr interrupt is active after masking
*
* bit 4 : RXFIS Receive FIFO Full Interrupt Status.
* - 0 : ssi_rxf_intr interrupt is not active after masking
* - 1 : ssi_rxf_intr interrupt is full after masking
*
* bit 3 : RXOIS Receive FIFO Overflow Interrupt Status.
* - 0 : ssi_rxo_intr interrupt is not active after masking
* - 1 : ssi_rxo_intr interrupt is active after masking
*
* bit 2 : RXUIS Receive FIFO Underflow Interrupt Status.
* - 0 : ssi_rxu_intr interrupt is not active after masking
* - 1 : ssi_rxu_intr interrupt is active after masking
*
* bit 1 : TXOIS Transmit FIFO Overflow Interrupt Status.
* - 0 : ssi_txo_intr interrupt is not active after masking
* - 1 : ssi_txo_intr interrupt is active after masking
*
* bit 0 : TXEIS Transmit FIFO Empty Interrupt Status.
* - 0 : ssi_txe_intr interrupt is not active after masking
* - 1 : ssi_txe_intr interrupt is active after masking
*/
u32 SSI_GetIsr(SPI_TypeDef *spi_dev)
{
return spi_dev->ISR;
}
/**
* @brief Get SPIx Raw Interrupt Status.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval Current Raw Interrupt Status,each bit of this value represents one
* raw interrupt status which is as follows:
*
* bit 7 : SSRIR SS_N Rising Edge Detect Interrupt Status. (valid when device is slave)
* - 0 : ssi_ssr_intr interrupt not active after masking
* - 1 : ssi_ssr_intr interrupt is active after masking
*
* bit 6 : TXUIR Transmit FIFO Under Flow Interrupt Status. (valid when device is slave)
* - 0 : ssi_txu_intr interrupt is not active after masking
* - 1 : ssi_txu_intr interrupt is active after masking
*
* bit 5 : FAEIR Frame Alignment Interrupt Status. (valid when device is slave)
* - 0 : ssi_fae_intr interrupt not active after masking
* - 1 : ssi_fae_intr interrupt is active after masking
*
* bit 5 : MSTIR Multi-Master Contention Raw Interrupt Status.(valid when device is master)
* - 0 : ssi_mst_intr interrupt not active prior to masking
* - 1 : ssi_mst_intr interrupt is active prior to masking
*
* bit 4 : RXFIR Receive FIFO Full Raw Interrupt Status.
* - 0 : ssi_rxf_intr interrupt is not active prior to masking
* - 1 : ssi_rxf_intr interrupt is full prior to masking
*
* bit 3 : RXOIR Receive FIFO Overflow Raw Interrupt Status.
* - 0 : ssi_rxo_intr interrupt is not active prior to masking
* - 1 : ssi_rxo_intr interrupt is active prior to masking
*
* bit 2 : RXUIR Receive FIFO Underflow Raw Interrupt Status.
* - 0 : ssi_rxu_intr interrupt is not active prior to masking
* - 1 : ssi_rxu_intr interrupt is active prior to masking
*
* bit 1 : TXOIR Transmit FIFO Overflow Raw Interrupt Status.
* - 0 : ssi_txo_intr interrupt is not active prior to masking
* - 1 : ssi_txo_intr interrupt is active prior to masking
*
* bit 0 : TXEIR Transmit FIFO Empty Raw Interrupt Status.
* - 0 : ssi_txe_intr interrupt is not active prior to masking
* - 1 : ssi_txe_intr interrupt is active prior to masking
*/
u32 SSI_GetRawIsr(SPI_TypeDef *spi_dev)
{
return spi_dev->RISR;
}
/**
* @brief Get which slave is selected.
* @note Valid only when the device is configured as a master.
* @param spi_dev: where spi_dev can be SPI0_DEV or SPI1_DEV.
* @retval Each bit of this value which is set to 1 corresponds to the slave being slected.
*/
u32 SSI_GetSlaveEnable(SPI_TypeDef *spi_dev)
{
return spi_dev->SER;
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_ssi.c
|
C
|
apache-2.0
| 35,222
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_startup.c
|
C
|
apache-2.0
| 247
|
/**************************************************************************//**
* @file rtl8721dhp_system.c
* @brief CMSIS Device System Source File for
* ARMCM3 Device Series
* @version V1.08
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include "basic_types.h"
#include "ameba_soc.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __SYSTEM_CLOCK PLATFORM_CLOCK
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
u32
SystemGetCpuClk(void)
{
return CPU_ClkGet(IS_FPGA_VERIF);
}
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
SystemCoreClock = SystemGetCpuClk();
}
/**
* @brief Set CPU clock.
* @param CpuClk: This parameter can be one of the following values
* @arg CLK_KM4_200M
* @arg CLK_KM4_100M
* @arg CLK_KM4_50M
* @arg CLK_KM4_25M
* @arg CLK_KM4_XTAL
*/
void SystemSetCpuClk(u8 CpuClk)
{
CPU_ClkSet(CpuClk);
SystemCoreClockUpdate();
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
DiagPrintf("---SystemInit--\r\n");
// TODO: Hardware initial
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClockUpdate();
}
/**
* @brief Generate random seed
* @param none
* @return value: random seed value
*/
u32 Gen_RandomSeed(VOID)
{
#ifdef AMEBAD_TODO
u32 adc_tmp, isr, AdcTempDat;
u8 random_tmp, random[4];
ADC_TypeDef *adc = ADC;
int i, j;
/* init ADC*/
ADC_InitTypeDef AdcInitStruct;
ADC_InitStruct(&AdcInitStruct);
AdcInitStruct.ADC_BurstSz = 2;
ADC_AnaparAd[1] = 0x41004;
InterruptDis(ADC_IRQ);
PLL2_Set(BIT_SYS_SYSPLL_CK_ADC_EN, ENABLE);
ADC_Init(&AdcInitStruct);
/* Clear ADC Status */
ADC_INTClear();
ADC_INTConfig(BIT_ADC_FIFO_FULL_EN|BIT_ADC_FIFO_RD_REQ_EN, ENABLE);
ADC_Cmd(ENABLE);
/* B CUT ADD patch for reset fail */
AdcTempDat = adc->ANAPAR_AD1;
AdcTempDat |= BIT(0);
adc->ANAPAR_AD1 = AdcTempDat;
for(i = 0; i < 4; i++){
retry:
random_tmp = 0;
for (j = 0; j < 8; j++){
while (1) {
isr = ADC_GetISR();
if (isr & (BIT_ADC_FIFO_FULL | BIT_ADC_FIFO_RD_REQ)) {
adc_tmp = ADC_Read();
ADC_Read();
ADC_INTClear();
ADC_INTConfig(BIT_ADC_FIFO_FULL_EN|BIT_ADC_FIFO_RD_REQ_EN, DISABLE);
break;
}
}
random_tmp |= ((adc_tmp & 0x1) << j);
}
if((random_tmp == 0x00) || (random_tmp == 0xff)){
goto retry;
}
random[i] = random_tmp;
}
/* B CUT ADD patch for reset fail */
AdcTempDat = adc->ANAPAR_AD1;
AdcTempDat &= ~ BIT(0);
adc->ANAPAR_AD1 = AdcTempDat;
/* disable ADC*/
ADC_Cmd(DISABLE);
ADC_INTClear();
PLL2_Set(BIT_SYS_SYSPLL_CK_ADC_EN, DISABLE);
return *(u32*)random;
#else
return 0;
#endif
}
/**
* @brief get the state of rdp, enable or disable
* @retval : This parameter can be one of the following values:
* @arg TRUE: rdp is enable
* @arg FALSE: rdp is disable
*/
u32 IsRDPenabled(void)
{
return FALSE;
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_system.c
|
C
|
apache-2.0
| 5,280
|
/**
******************************************************************************
* @file rtl8721dhp_usi_i2c.c
* @author
* @version V1.0.0
* @date 2017-12-18
* @brief This file contains all the functions prototypes for the I2C firmware
* library, including the following functionalities of theIntel-Integrated
* Circuit (I2C) peripheral:
* - Initialization
* - I2C Speed Setting
* - I2C Slave Address Updating
* - Receive/Send Data Interface
* - I2C Peripheral Control (disable/enable)
* - I2C SleepMode Control
* - Output pin Configuration
* - Interrupts and flags management
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
#include "rtl8721d_usi_i2c.h"
u32 USI_I2C_SLAVEWRITE_PATCH;
u32 USI_IC_FS_SCL_HCNT_TRIM;
u32 USI_IC_FS_SCL_LCNT_TRIM;
/**
* @brief Fills each USI_I2C_StructInit member with its default value.
* @param USI_I2C_StructInit: pointer to an USI_I2C_InitTypeDef structure which will be initialized.
* @retval None
*/
void USI_I2C_StructInit(USI_I2C_InitTypeDef* USI_I2C_InitStruct)
{
/* Load HAL initial data structure default value */
USI_I2C_InitStruct->USI_I2CMaster = USI_I2C_MASTER_MODE;
USI_I2C_InitStruct->USI_I2CAddrMod = USI_I2C_ADDR_7BIT;
USI_I2C_InitStruct->USI_I2CSpdMod = USI_I2C_SS_MODE;
USI_I2C_InitStruct->USI_I2CClk = 100;
USI_I2C_InitStruct->USI_I2CIPClk = 50000000;
USI_I2C_InitStruct->USI_I2CAckAddr = 0x11;
USI_I2C_InitStruct->USI_I2CSdaHd = 1;
USI_I2C_InitStruct->USI_I2CSlvSetup = 0x3;
USI_I2C_InitStruct->USI_I2CRXTL = 0x01;
USI_I2C_InitStruct->USI_I2CTXTL = 0x10;
USI_I2C_InitStruct->USI_I2CMstReSTR = DISABLE;
USI_I2C_InitStruct->USI_I2CMstGC = DISABLE;
USI_I2C_InitStruct->USI_I2CMstStartB = DISABLE;
USI_I2C_InitStruct->USI_I2CSlvNoAck = DISABLE;
USI_I2C_InitStruct->USI_I2CFilter = 0x11;
USI_I2C_InitStruct->USI_I2CTxDMARqLv = 0x09;
USI_I2C_InitStruct->USI_I2CRxDMARqLv = 0x04;
}
/**
* @brief Initializes the USIx peripheral according to the specified
* parameters in the USI_I2C_InitStruct.
* @param USIx: where USIx can be USI0_DEV.
* @param USI_I2C_InitStruct: pointer to a USI_I2C_InitTypeDef structure that contains
* the configuration information for the specified I2C peripheral.
* @retval None
*/
void USI_I2C_Init(USI_TypeDef *USIx, USI_I2C_InitTypeDef* USI_I2C_InitStruct)
{
u8 Specical;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
assert_param(IS_USI_I2C_ADDR_MODE(USI_I2C_InitStruct->USI_I2CAddrMod));
assert_param(IS_USI_I2C_SPEED_MODE(USI_I2C_InitStruct->USI_I2CSpdMod));
/* Disable the IC first */
USIx->I2C_ENABLE &= ~USI_I2C_ENABLE;
/*reset USI all logic, this step will clear tx/rx fifo*/
USIx->SW_RESET &=(~USI_SW_RESET_RSTB);
USIx->SW_RESET = 0x1f;
/*disable USI all mode, configure USI with I2C mode*/
USIx->USI_MODE_CTRL &= (~USI_SERIAL_MODE);
USIx->USI_MODE_CTRL |= USI_SERIAL_I2C_MODE;
/* Master case*/
if (USI_I2C_InitStruct->USI_I2CMaster) {
/*RESTART MUST be set in these condition in Master mode.
But it might be NOT compatible in old slaves.*/
if ((USI_I2C_InitStruct->USI_I2CAddrMod == USI_I2C_ADDR_10BIT) || (USI_I2C_InitStruct->USI_I2CSpdMod == USI_I2C_HS_MODE) || (USI_I2C_InitStruct->USI_I2CMstStartB != 0))
USI_I2C_InitStruct->USI_I2CMstReSTR = ENABLE;
USIx->I2C_CTRL = (USI_I2C_SLV_DISABLE |
(USI_I2C_InitStruct->USI_I2CSpdMod << 2) |
(USI_I2C_InitStruct->USI_I2CMstReSTR << 1) |
(USI_I2C_InitStruct->USI_I2CMaster));
/* To set target addr.*/
Specical = 0;
if ((USI_I2C_InitStruct->USI_I2CMstGC != 0) || (USI_I2C_InitStruct->USI_I2CMstStartB != 0))
Specical = 1;
USIx->I2C_TAR = ((USI_I2C_InitStruct->USI_I2CAddrMod << 12) |
(Specical << 11) |
(USI_I2C_InitStruct->USI_I2CMstStartB << 10) |
(USI_I2C_InitStruct->USI_I2CAckAddr & USI_I2C_IC_TAR));
/* To Set I2C clock*/
USI_I2C_SetSpeed(USIx, USI_I2C_InitStruct->USI_I2CSpdMod, USI_I2C_InitStruct->USI_I2CClk, USI_I2C_InitStruct->USI_I2CIPClk);
} /*if (Master)*/
else {
USIx->I2C_CTRL = (((USI_I2C_InitStruct->USI_I2CAckAddr <<12) & USI_I2C_SAR) |
(USI_I2C_InitStruct->USI_I2CAddrMod << 9) |
(USI_I2C_InitStruct->USI_I2CMaster << 8) |
(USI_I2C_InitStruct->USI_I2CSpdMod << 2) |
(USI_I2C_InitStruct->USI_I2CMaster));
/* To set slave no ack and ack general call*/
USIx->I2C_SLV_ACK_CTRL = USI_I2C_InitStruct->USI_I2CSlvNoAck |(USI_I2C_InitStruct->USI_I2CSlvAckGC << 1);
/* to set SDA setup time */
USIx->I2C_SDA_TIMING = (USI_I2C_InitStruct->USI_I2CSlvSetup & USI_I2C_SDA_SETUP);
}
/* To set SDA hold time */
USIx->I2C_SDA_TIMING = (((USI_I2C_InitStruct->USI_I2CSdaHd << 16) & USI_I2C_SDA_HOLD) | (USIx->I2C_SDA_TIMING & USI_I2C_SDA_SETUP));
/* To set TX almost empty Level */
USIx->TX_FIFO_CTRL= USI_I2C_InitStruct->USI_I2CTXTL;
/* To set RX almost full Level */
USIx->RX_FIFO_CTRL = USI_I2C_InitStruct->USI_I2CRXTL;
/* To set IC_FILTER */
USIx->I2C_DIG_FILTER= USI_I2C_InitStruct->USI_I2CFilter;
/* To set DMA TX/RX level */
USIx->DMA_REQ_SIZE &= (~(USI_TX_DMA_BURST_SIZE | USI_RX_DMA_BURST_SIZE));
USIx->DMA_REQ_SIZE |= (USI_I2C_InitStruct->USI_I2CTxDMARqLv | (USI_I2C_InitStruct->USI_I2CRxDMARqLv << 16));
/*I2C Clear all interrupts first*/
USI_I2C_ClearAllINT(USIx);
/*I2C Disable all interrupts first*/
USI_I2C_INTConfig(USIx, 0xFFFFFFFF, DISABLE);
}
/**
* @brief Master sets I2C Speed Mode.
* @param USIx: where USIx can be USI0_DEV.
* @param SpdMd: I2C Speed Mode.
* This parameter can be one of the following values:
* @arg USI_I2C_SS_MODE:
* @arg USI_I2C_FS_MODE:
* @arg USI_I2C_HS_MODE:
* @param I2Clk: I2C Bus Clock, unit is KHz.
* This parameter can be one of the following values:
* @arg 50:
* @arg 100:
* @arg 400:
* @arg 1000:
* @arg 3000:
* @param IPClk: I2C IP Clock, unit is Hz.
* @retval None
*/
void USI_I2C_SetSpeed(USI_TypeDef *USIx, u32 SpdMd, u32 I2Clk, u32 I2CIPClk)
{
u32 ICHLcnt;
u32 ICHtime;
u32 ICLtime;
u32 IPClkM = I2CIPClk /1000000;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
switch (SpdMd)
{
case USI_I2C_SS_MODE:
{
ICHtime = ((1000000/I2Clk)*USI_I2C_SS_MIN_SCL_HTIME)/(USI_I2C_SS_MIN_SCL_HTIME+USI_I2C_SS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2Clk)*USI_I2C_SS_MIN_SCL_LTIME)/(USI_I2C_SS_MIN_SCL_HTIME+USI_I2C_SS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IPClkM)/1000;
USIx->I2C_SS_SCL_CNT = (ICHLcnt & USI_I2C_SS_SCL_HCNT) + 1;
ICHLcnt = (ICLtime * IPClkM)/1000;
USIx->I2C_SS_SCL_CNT |= (ICHLcnt << 16) & USI_I2C_SS_SCL_LCNT;
break;
}
case USI_I2C_FS_MODE:
{
ICHtime = ((1000000/I2Clk)*USI_I2C_FS_MIN_SCL_HTIME)/(USI_I2C_FS_MIN_SCL_HTIME+USI_I2C_FS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2Clk)*USI_I2C_FS_MIN_SCL_LTIME)/(USI_I2C_FS_MIN_SCL_HTIME+USI_I2C_FS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IPClkM)/1000;
if (ICHLcnt > IC_FS_SCL_HCNT_TRIM)/*this part is according to the fine-tune result*/
ICHLcnt -= IC_FS_SCL_HCNT_TRIM;
USIx->I2C_FS_SCL_CNT = (ICHLcnt & USI_I2C_FS_SCL_HCNT) + 1;
ICHLcnt = (ICLtime * IPClkM)/1000;
if (ICHLcnt > IC_FS_SCL_LCNT_TRIM)/*this part is according to the fine-tune result*/
ICHLcnt -= IC_FS_SCL_LCNT_TRIM;
USIx->I2C_FS_SCL_CNT |= (ICHLcnt << 16) & USI_I2C_FS_SCL_LCNT;
break;
}
case USI_I2C_HS_MODE:
{
/*set Fast mode count for Master code*/
ICHtime = ((1000000/400)*USI_I2C_FS_MIN_SCL_HTIME)/(USI_I2C_FS_MIN_SCL_HTIME+USI_I2C_FS_MIN_SCL_LTIME);
ICLtime = ((1000000/400)*USI_I2C_FS_MIN_SCL_LTIME)/(USI_I2C_FS_MIN_SCL_HTIME+USI_I2C_FS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IPClkM)/1000;
USIx->I2C_FS_SCL_CNT = ICHLcnt & USI_I2C_FS_SCL_HCNT;
ICHLcnt = (ICLtime * IPClkM)/1000;
USIx->I2C_FS_SCL_CNT |= (ICHLcnt << 16) & USI_I2C_FS_SCL_LCNT;
ICHtime = ((1000000/I2Clk)*USI_I2C_HS_MIN_SCL_HTIME_100)/(USI_I2C_HS_MIN_SCL_HTIME_100+USI_I2C_HS_MIN_SCL_LTIME_100);
ICLtime = ((1000000/I2Clk)*USI_I2C_HS_MIN_SCL_LTIME_100)/(USI_I2C_HS_MIN_SCL_HTIME_100+USI_I2C_HS_MIN_SCL_LTIME_100);
ICHLcnt = (ICHtime * IPClkM)/1000;
//if (ICHLcnt>8)/*this part is according to the fine-tune result*/
// ICHLcnt -= 3;
USIx->I2C_HS_SCL_CNT = (ICHLcnt & USI_I2C_HS_SCL_HCNT)+1;
ICHLcnt = (ICLtime * IPClkM)/1000;
//if (ICHLcnt>6)/*this part is according to the fine-tune result*/
// ICHLcnt -= 6;
USIx->I2C_HS_SCL_CNT |= (ICHLcnt << 16) & USI_I2C_HS_SCL_LCNT;
break;
}
default:
break;
}
}
/**
* @brief Master transmits the address byte to select the slave device.
* @param USIx: where USIx can be USI0_DEV.
* @param Address: specifies the slave address which will be transmitted
* @retval None.
*/
void USI_I2C_SetSlaveAddress(USI_TypeDef *USIx, u16 Address)
{
u32 tar = USIx->I2C_TAR & ~(USI_I2C_IC_TAR);
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
/*set target address to generate start signal*/
USIx->I2C_TAR = (Address & USI_I2C_IC_TAR) | tar;
}
/**
* @brief Checks whether the specified I2C flag is set or not.
* @param USIx: where USIx can be USI0_DEV.
* @param USI_I2C_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg USI_I2C_BUS_ACTIVITY: BUS FSM Activity Status.
* @arg USI_I2C_SLV_ACTIVITY: Slave FSM Activity Status.
* @arg USI_I2C_MST_ACTIVITY: Master FSM Activity Status.
* @arg USI_I2C_ACTIVITY_COMB: I2C Activity Status, combine Master and Slave.
* @arg USI_I2C_ENABLE_COPY: i2c_enable copy to here
* @retval The new state of USI_I2C_FLAG:
* - 1: the specified I2C flag is set
* - 0: the specified I2C flag is not set
*/
u8 USI_I2C_CheckFlagState(USI_TypeDef *USIx, u32 USI_I2C_FLAG)
{
u8 bit_status = 0;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
if((USIx->I2C_STATUS & USI_I2C_FLAG) != 0)
{
/* USI_I2C_FLAG is set */
bit_status = 1;
}
/* Return the USI_I2C_FLAG status */
return bit_status;
}
/**
* @brief Checks whether the specified I2C TXFIFO flag is set or not.
* @param USIx: where USIx can be USI0_DEV.
* @param USI_I2C_TXFIFO_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg USI_TXFIFO_ALMOST_EMPTY_COPY: TX FIFO ALMOST EMPTY status
* @arg USI_TXFIFO_EMPTY: TX FIFO EMPTY status
* @arg USI_TXFIFO_FULL: TX FIFO FULL status
* @retval The new state of USI_I2C_TXFIFO_FLAG:
* - 1: the specified I2C flag is set
* - 0: the specified I2C flag is not set
*/
u8 USI_I2C_CheckTXFIFOState(USI_TypeDef *USIx, u32 USI_I2C_TXFIFO_FLAG)
{
u8 bit_status = 0;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
if((USIx->TX_FIFO_STATUS & USI_I2C_TXFIFO_FLAG) != 0)
{
/* USI_I2C_TXFIFO_FLAG is set */
bit_status = 1;
}
/* Return the USI_I2C_TXFIFO_FLAG status */
return bit_status;
}
/**
* @brief Checks whether the specified I2C RXFIFO flag is set or not.
* @param USIx: where USIx can be USI0_DEV.
* @param USI_I2C_RXFIFO_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg USI_RXFIFO_ALMOST_FULL_COPY: RX FIFO ALMOST EMPTY status
* @arg USI_RXFIFO_EMPTY: RX FIFO EMPTY status
* @arg USI_RXFIFO_FULL: RX FIFO FULL status
* @retval The new state of USI_I2C_RXFIFO_FLAG:
* - 1: the specified I2C flag is set
* - 0: the specified I2C flag is not set
*/
u8 USI_I2C_CheckRXFIFOState(USI_TypeDef *USIx, u32 USI_I2C_RXFIFO_FLAG)
{
u8 bit_status = 0;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
if((USIx->RX_FIFO_STATUS & USI_I2C_RXFIFO_FLAG) != 0)
{
/* USI_I2C_RXFIFO_FLAG is set */
bit_status = 1;
}
/* Return the USI_I2C_RXFIFO_FLAG status */
return bit_status;
}
/**
* @brief ENABLE/DISABLE the I2C's interrupt bits..
* @param USIx: where USIx can be USI0_DEV.
* @param USI_I2C_IT: specifies the USIx interrupt sources to be enabled or disabled.
* This parameter can be one or combinations of the following values:
* @arg USI_I2C_DMA_DONE_INTER_EN: I2C DMA Done Interrupt
* @arg USI_I2C_LP_WAKE_INTER_EN: I2C Low power wakeup Interrupt
* @arg USI_I2C_GEN_CALL_INTER_EN: General Call Interrupt
* @arg USI_I2C_START_DET_INTER_EN: Start or Restart Condition Interrupt
* @arg USI_I2C_STOP_DET_INTER_EN: Stop Condition Interrupt
* @arg USI_I2C_ACTIVITY_INTER_EN: I2C Activity Interrupt
* @arg USI_I2C_RX_DONE_INTER_EN: Slave Transmitter RX Done Interrupt
* @arg USI_I2C_TX_ABRT_INTER_EN: Transmit Abort Interrupt
* @arg USI_I2C_RD_REQ_INTER_EN: Read Request Interrupt
* @arg USI_RXFIFO_UNDERFLOW_INTR_EN: RX FIFO underflow Interrupt
* @arg USI_RXFIFO_OVERFLOW_INTR_EN: RX FIFO overflow Interrupt
* @arg USI_RXFIFO_ALMOST_FULL_INTR_EN: RX FIFO almost Full Interrupt
* @arg USI_TXFIFO_OVERFLOW_INTR_EN: TX FIFO overflow Interrupt
* @arg USI_TXFIFO_ALMOST_EMTY_INTR_EN: TX FIFO almost Empty Interrupt
* @param NewState: specifies the state of the interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USI_I2C_INTConfig(USI_TypeDef *USIx, u32 USI_I2C_IT, u32 NewState)
{
u32 TempVal = USIx->INTERRUPT_ENABLE;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
if (NewState == ENABLE) {
TempVal |= USI_I2C_IT;
} else {
TempVal &= ~USI_I2C_IT;
}
USIx->INTERRUPT_ENABLE = TempVal;
}
/**
* @brief Clears the specified I2C interrupt pending bit.
* @param USIx: where USIx can be USI0_DEV.
* @param INTrBit: specifies the interrupt to be cleared.
* This parameter can be one of the following values:
* @arg USI_I2C_DMA_DONE_CLR: clear I2C DMA Done interrupt
* @arg USI_I2C_LP_WAKE_CLR: clear I2C Low Power wakeup Interrupt
* @arg USI_I2C_GEN_CALL_CLR: clear General Call Interrupt
* @arg USI_I2C_START_DET_CLR: clear Start or Restart Condition Interrupt
* @arg USI_I2C_STOP_DET_CLR: clear Stop Condition Interrupt
* @arg USI_I2C_ACTIVITY_CLR: clear I2C Activity Interrupt
* @arg USI_I2C_RX_DONE_CLR: clear Slave Transmitter RX Done Interrupt
* @arg USI_I2C_TX_ABRT_CLR: clear Transmit Abort Interrupt
* @arg USI_I2C_RD_REQ_CLR: clear Read Request Interrupt
* @arg USI_RXFIFO_UNDERFLOW_CLR: clear RX FIFO underflow Interrupt
* @arg USI_RXFIFO_OVERFLOW_CLR: clear RX FIFO overflow Interrupt
* @arg USI_TXFIFO_OVERFLOW_CLR: clear TX FIFO overflow Interrupt
* @note USI_TXFIFO_ALMOST_EMTY_INTS is automatically cleared by hardware when the buffer
* level goes above the TX_FIFO_CTRL threshold.
* USI_RXFIFO_ALMOST_FULL_INTS is automatically cleared by hardware when the buffer
* level goes below the RX_FIFO_CTRL threshold.
* @retval None
*/
void USI_I2C_ClearINT(USI_TypeDef *USIx, u32 INTrBit)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
/*write 1 to clear all interrupts*/
USIx->INTERRUPT_STATUS_CLR = INTrBit;
}
/**
* @brief Clears all of the I2C interrupt pending bit.
* @param USIx: where USIx can be USI0_DEV.
* @retval None
*/
void USI_I2C_ClearAllINT(USI_TypeDef *USIx)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
/*write 1 to clear all interrupts*/
USIx->INTERRUPT_ALL_CLR = USI_INT_ALL_CLEAR;
}
/**
* @brief Get I2C Raw Interrupt Status.
* @param USIx: where USIx can be USI0_DEV.
* @retval raw interrupt status
*/
u32 USI_I2C_GetRawINT(USI_TypeDef *USIx)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
return USIx->RAW_INTERRUPT_STATUS;
}
/**
* @brief Get I2C interrupt status.
* @param USIx: where USIx can be USI0_DEV.
* @retval interrupt status
*/
u32 USI_I2C_GetINT(USI_TypeDef *USIx)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
return USIx->INTERRUPT_STATUS;
}
/**
* @brief Master sends single byte through the USIx peripheral according to the set of the upper layer.
* @param USIx: where USIx can be USI0_DEV.
* @param pBuf: point to the data that to be write.
* @param I2CCmd: specifies whether a read from FIFO or a write to FIFO is performed.
* @param I2CStop: specifies whether a STOP is issued after the byte is sent or received.
* @param I2CReSTR: specifies whether a RESTART is issued after the byte is sent or received.
* @retval None
*/
void USI_I2C_MasterSendNullData(USI_TypeDef *USIx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
USIx->TX_FIFO_WRITE = *(pBuf) |
(1 << 11) |
(I2CReSTR << 10) |
(I2CCmd << 8) |
(I2CStop << 9);
}
/**
* @brief Master sends single byte through the USIx peripheral according to the set of the upper layer.
* @param USIx: where USIx can be USI0_DEV.
* @param pBuf: point to the data that to be write.
* @param I2CCmd: specifies whether a read from FIFO or a write to FIFO is performed.
* @param I2CStop: specifies whether a STOP is issued after the byte is sent or received.
* @param I2CReSTR: specifies whether a RESTART is issued after the byte is sent or received.
* @retval None
*/
void USI_I2C_MasterSend(USI_TypeDef *USIx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
USIx->TX_FIFO_WRITE = *(pBuf) |
(I2CReSTR << 10) |
(I2CCmd << 8) |
(I2CStop << 9);
}
/**
* @brief Slave sends single byte through the USIx peripheral after receiving read request of Master.
* @param USIx: where USIx can be USI0_DEV.
* @param Data: data to be transmitted.
* @param StopState: specifies whether a STOP is issued after the byte is sent.
* @retval None
*/
void USI_I2C_SlaveSend(USI_TypeDef *USIx, u8 Data)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
USIx->TX_FIFO_WRITE = Data;
}
/**
* @brief Returns the most recent received data by the USIx peripheral.
* @param USIx: where USIx can be USI0_DEV.
* @retval The value of the received data.
*/
u8 USI_I2C_ReceiveData(USI_TypeDef *USIx)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
/* Return the data in the DR register */
return (u8)USIx->RX_FIFO_READ;
}
/**
* @brief Send data with special length in master mode through the USIx peripheral.
* @param USIx: where USIx can be USI0_DEV.
* @param pBuf: point to the data to be transmitted.
* @param len: the length of data that to be transmitted.
* @note deal with condition that master send address or data while slave no ack
* @retval The length of data that have been sent to tx fifo
*/
u8 USI_I2C_MasterWrite(USI_TypeDef *USIx, u8* pBuf, u8 len)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
/* Write in the DR register the data to be sent */
for(cnt = 0; cnt < len; cnt++)
{
while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_ALMOST_EMPTY_COPY)) == 0);
if(cnt >= len - 1)
{
/*generate stop signal*/
USIx->TX_FIFO_WRITE = (*pBuf++) | (1 << 9);
}
else
{
USIx->TX_FIFO_WRITE = (*pBuf++);
}
while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_EMPTY)) == 0) {
if(USI_I2C_GetRawINT(USIx) & USI_I2C_TX_ABRT_RSTS) {
USI_I2C_ClearAllINT(USIx);
return cnt;
}
}
}
return cnt;
}
/**
* @brief Read data with special length in master mode through the USIx peripheral under in-house IP.
* @param USIx: where USIx can be USI0_DEV.
* @param pBuf: point to the buffer to hold the received data.
* @param len: the length of data that to be received.
* @retval The length of data that have received from rx fifo
*/
u8 USI_I2C_MasterRead(USI_TypeDef *USIx, u8* pBuf, u8 len)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
/* read in the DR register the data to be received */
for(cnt = 0; cnt < len; cnt++)
{
if(cnt >= len - 1)
{
/* generate stop singal */
USIx->TX_FIFO_WRITE = 0x0003 << 8;
}
else
{
USIx->TX_FIFO_WRITE = 0x0001 << 8;
}
/* wait for USI_I2C_FLAG_RFNE flag */
while((USI_I2C_CheckRXFIFOState(USIx, USI_RXFIFO_EMPTY)) == 1) {
if(USI_I2C_GetRawINT(USIx) & USI_I2C_TX_ABRT_RSTS) {
USI_I2C_ClearAllINT(USIx);
return cnt;
}
}
*pBuf++ = (u8)USIx->RX_FIFO_READ;
}
return cnt;
}
/**
* @brief Send data with special length in slave mode through the USIx peripheral.
* @param USIx: where USIx can be USI0_DEV.
* @param pBuf: point to the data to be transmitted.
* @param len: the length of data that to be transmitted.
* @retval None
*/
void USI_I2C_SlaveWrite(USI_TypeDef *USIx, u8* pBuf, u8 len)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
for(cnt = 0; cnt < len; cnt++) {
/* Check I2C RD Request flag */
while((USI_I2C_GetRawINT(USIx) & USI_I2C_RD_REQ_RSTS) == 0);
if (USI_I2C_SLAVEWRITE_PATCH) {
USIx->INTERRUPT_STATUS_CLR = USI_I2C_RD_REQ_CLR;
}
/* Check I2C TX FIFO status */
while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_ALMOST_EMPTY_COPY)) == 0);
USIx->TX_FIFO_WRITE = (*pBuf++);
}
while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_EMPTY)) == 0);
}
/**
* @brief Read data with special length in slave mode through the USIx peripheral.
* @param USIx: where USIx can be USI0_DEV.
* @param pBuf: point to the buffer to hold the received data.
* @param len: the length of data that to be received.
* @retval None
*/
void USI_I2C_SlaveRead(USI_TypeDef *USIx, u8* pBuf, u8 len)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
for(cnt = 0; cnt < len; cnt++) {
/* Check I2C RX FIFO status */
while((USI_I2C_CheckRXFIFOState(USIx, USI_RXFIFO_EMPTY)) == 1);
*pBuf++ = (u8)USIx->RX_FIFO_READ;
}
}
/**
* @brief Sends data and read data in master mode through the USIx peripheral.
* @param USIx: where USIx can be USI0_DEV to select the I2C peripheral.
* @param pWriteBuf: Byte to be transmitted.
* @param Writelen: Byte number to be transmitted (the length should less then buffer depth for A CUT).
* @param pReadBuf: Byte to be received.
* @param Readlen: Byte number to be received.
* @retval None
*/
void USI_I2C_MasterRepeatRead(USI_TypeDef* USIx, u8* pWriteBuf, u8 Writelen, u8* pReadBuf, u8 Readlen)
{
u8 cnt = 0;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
/* write in the DR register the data to be sent */
for(cnt = 0; cnt < Writelen; cnt++)
{
while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_ALMOST_EMPTY_COPY)) == 0);
if(cnt >= Writelen - 1)
{
/*generate restart signal*/
USIx->TX_FIFO_WRITE = (*pWriteBuf++) | (1 << 10);
}
else
{
USIx->TX_FIFO_WRITE = (*pWriteBuf++);
}
}
/*Wait I2C TX FIFO not full*/
while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_ALMOST_EMPTY_COPY)) == 0);
USI_I2C_MasterRead(USIx, pReadBuf, Readlen);
}
/**
* @brief Enables or disables the specified I2C peripheral, this is one bit register.
* @param USIx: where USIx can be USI0_DEV.
* @param NewState: new state of the USIx peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USI_I2C_Cmd(USI_TypeDef *USIx, u8 NewState)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
if (NewState != DISABLE)
{
/* Enable the selected I2C peripheral */
USIx->I2C_ENABLE |= USI_I2C_ENABLE;
}
else
{
/* Disable the selected I2C peripheral */
USIx->I2C_ENABLE &= ~USI_I2C_ENABLE;
}
}
/**
* @brief Enable I2C Tx or Rx DMA.
* @param USIx: where USIx can be USI0_DEV.
* @param DmaCtrl: control Transmit DMA Enable or Receive DMA Enable
* This parameter can be one of the following values:
* @arg USI_TX_DMA_ENABLE:
* @arg USI_RX_DMA_ENABLE:
* @param NewState: the new state of the DMA function.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USI_I2C_DMAControl(USI_TypeDef *USIx, u32 DmaCtrl, u8 NewState)
{
u32 I2CDMAEn = USIx->DMA_ENABLE;
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
if (NewState == ENABLE)
I2CDMAEn |= DmaCtrl;
else
I2CDMAEn &= ~DmaCtrl;
USIx->DMA_ENABLE = I2CDMAEn;
}
/**
* @brief Initializes the USIx Control Register DMA mode.
* @param USIx: where USIx can be USI0_DEV.
* @param USI_I2C_DmaCmd: Command to control the read or write operation and
* the action after the last data transferred.
* This parameter can be one or combinations of the following values:
* @arg USI_I2C_DMODE_RESTART
* @arg USI_I2C_DMODE_STOP
* @arg USI_I2C_DMODE_WRITE_CMD
* @arg USI_I2C_DMODE_READ_CMD
* @arg USI_I2C_DMODE_ENABLE
* @param USI_I2C_DmaBLen: length of data.
* This parameter must be set to a value in the 0-0xFFFF range.
* @retval None
*/
void USI_I2C_DmaRegModeConfig(USI_TypeDef *USIx, u32 USI_I2C_DmaCmd, u32 USI_I2C_DmaBLen)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
assert_param(IS_USI_I2C_DMA_DATA_LEN(USI_I2C_DmaBLen));
USIx->I2C_DMA_CMD = ((USI_I2C_DmaBLen << 16) | USI_I2C_DMA_CTRL_REG_MODE | USI_I2C_DmaCmd);
}
/**
* @brief Init and Enable I2C TX GDMA.
* @param Index: 0 .
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pTxBuf: Tx Buffer.
* @param TxCount: Tx Count.
* @retval TRUE/FLASE
* @note can not support legacy DMA mode
*/
BOOL USI_I2C_TXGDMA_Init(
u8 Index,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pTxBuf,
int TxCount
)
{
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);
if (GdmaChnl == 0xFF) {
/* No Available DMA channel */
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_InitStruct->GDMA_DIR = TTFCMemToPeri;
GDMA_InitStruct->GDMA_DstHandshakeInterface = USI_DEV_TABLE[Index].Tx_HandshakeInterface;
GDMA_InitStruct->GDMA_DstAddr = (u32)&USI_DEV_TABLE[Index].USIx->TX_FIFO_WRITE;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_DstInc = NoChange;
GDMA_InitStruct->GDMA_SrcInc = IncType;
if (((TxCount & 0x03)==0) && (((u32)(pTxBuf) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeOne;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_BlockSize = TxCount >> 2;
} else {
/* move 1 byte each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_BlockSize = TxCount;
}
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
GDMA_InitStruct->GDMA_SrcAddr = (u32)(pTxBuf);
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Init and Enable I2C RX GDMA.
* @param I2C: 0.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pRxBuf: Rx Buffer.
* @param RxCount: Rx Count.
* @retval TRUE/FLASE
* @note support Master or Slave RXDMA
*/
BOOL USI_I2C_RXGDMA_Init(
u8 Index,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pRxBuf,
int RxCount
)
{
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);
if (GdmaChnl == 0xFF) {
/* No Available DMA channel */
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem;
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->GDMA_SrcHandshakeInterface = USI_DEV_TABLE[Index].Rx_HandshakeInterface;
GDMA_InitStruct->GDMA_SrcAddr = (u32)&USI_DEV_TABLE[Index].USIx->RX_FIFO_READ;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_DstInc = IncType;
GDMA_InitStruct->GDMA_SrcInc = NoChange;
if (((u32)(pRxBuf) & 0x03)==0) {
/* 4-bytes aligned, move 4 bytes each DMA transaction */
GDMA_InitStruct->GDMA_DstMsize = MsizeOne;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
} else {
/* move 1 byte each DMA transaction */
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
}
GDMA_InitStruct->GDMA_BlockSize = RxCount;
GDMA_InitStruct->GDMA_DstAddr = (u32)(pRxBuf);
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
/* multi block close */
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Clock-gated I2C clock domain for address matching interrupts wake up.
* @param USIx: where USIx can be USI0_DEV.
* @param NewState: the new state of the Rx Path.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USI_I2C_Sleep_Cmd(USI_TypeDef *USIx, u32 NewStatus)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
if (NewStatus != DISABLE) {
USI_I2C_INTConfig(USIx, USI_I2C_LP_WAKE_INTER_EN, ENABLE);
USIx->I2C_DIG_FILTER &= ~ USI_I2C_DIG_FLTR_SEL;
USIx->I2C_CTRL &= ~(USI_I2C_SLV_DISABLE);
USIx->I2C_ENABLE |= USI_I2C_SLEEP;
} else {
USI_I2C_INTConfig(USIx, USI_I2C_LP_WAKE_INTER_EN, DISABLE);
USIx->I2C_DIG_FILTER |= USI_I2C_DIG_FLTR_SEL;
USIx->I2C_ENABLE &= ~USI_I2C_SLEEP;
}
}
/**
* @brief Wake up clock domain of Clock-gated I2C after address matching interrupts.
* @param USIx: where USIx can be USI0_DEV.
* @retval None
*/
void USI_I2C_WakeUp(USI_TypeDef *USIx)
{
/* Check the parameters */
assert_param(IS_USI_I2C_ALL_PERIPH(USIx));
USI_I2C_ClearINT(USIx, USI_I2C_LP_WAKE_CLR);
USI_I2C_Sleep_Cmd(USIx, DISABLE);
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_usi_i2c.c
|
C
|
apache-2.0
| 31,967
|
/**
******************************************************************************
* @file rtl8721dhp_usi_ssi.c
* @author
* @version V1.0.0
* @date 2017-11-27
* @brief This file contains all the functions prototypes for USI-SPI:
* - Initialization
* - Clock polarity and phase setting
* - SPI data frame size setting
* - SPI baud rate setting
* - Receive/Send data interface
* - Get TRx FIFO valid entries
* - check SPI device busy status
* - DMA transfers management
* - Interrupts and management
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
/** @addtogroup USI_SPI_Exported_Functions
*@verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable peripheral clock using the following functions
*
*
* 2. Configure the SPIx pinmux.
*
*
* 3. Disable the SPI using the USI_SSI_Cmd() function
*
* 4. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize,
* Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using
* the USI_SSI_Init() function.
*
* 5. Enable the USI-SPI using the USI_SSI_Cmd() function
*
* 6. When using poll:
* -Using USI_SSI_Writeable() function make sure that the transmit FIFO is not full,
* then using USI_SSI_WriteData() function to send data
*
* -Using USI_SSI_Readable() function make sure that the receive FIFO is not empty,
* then using USI_SSI_ReadData() function to receive data
*
* 7. Enable corresponding interrupt using the function USI_SSI_INTConfig() if you need to
* use interrupt mode.
*
* 8. When using the DMA mode
* - Configure & Initialize the DMA
* - Active the DMA Tx or Rx using USI_SSI_SetDmaEnable() function
*
* @endverbatim
*/
/**
* @brief Fills each USI_SSI_InitStruct member with its default value.
* @param USI_SSI_InitStruct: pointer to a USI_SSI_InitTypeDef structure which will be
* initialized.
* @retval None
*/
void
USI_SSI_StructInit(USI_SSI_InitTypeDef* USI_SSI_InitStruct)
{
USI_SSI_InitStruct->USI_SPI_RxThresholdLevel = 0; // if number of entries in the RX FIFO >= RxThresholdLevel + 1, RX interrupt asserted
USI_SSI_InitStruct->USI_SPI_TxThresholdLevel = 32; // if number of empty entries in th TX FIFO >= TxThresholdLevel, TX interrupt asserted
USI_SSI_InitStruct->USI_SPI_DmaRxDataLevel = 3;
USI_SSI_InitStruct->USI_SPI_DmaTxDataLevel = 56;
USI_SSI_InitStruct->USI_SPI_ClockDivider = 6;
USI_SSI_InitStruct->USI_SPI_DataFrameNumber = 0;
USI_SSI_InitStruct->USI_SPI_DataFrameSize = USI_SPI_DFS_8_BITS;
USI_SSI_InitStruct->USI_SPI_InterruptMask = 0x0;
USI_SSI_InitStruct->USI_SPI_SclkPhase = USI_SPI_SCPH_TOGGLES_AT_START;
USI_SSI_InitStruct->USI_SPI_SclkPolarity = USI_SPI_SCPOL_INACTIVE_IS_HIGH;
USI_SSI_InitStruct->USI_SPI_TransferMode = USI_SPI_TMOD_TR;
USI_SSI_InitStruct->USI_SPI_RxSampleDelay = 0;
USI_SSI_InitStruct->USI_SPI_SSTogglePhase = 0;
}
/**
* @brief Initializes the USI-SPI registers according to the specified parameters
* in USI_SSI_InitStruct.
* @param usi_dev: where spi_dev can be USI0_DEV.
* @param USI_SSI_InitStruct: pointer to a USI_SSI_InitTypeDef structure that contains
* the configuration information for the USI-SPI peripheral.
* @retval None
*/
void USI_SSI_Init(USI_TypeDef *usi_dev, USI_SSI_InitTypeDef *USI_SSI_InitStruct)
{
u32 TempValue1 = 0, TempValue2 = 0;
assert_param(IS_USI_SPI_RxThresholdLevel(USI_SSI_InitStruct->USI_SPI_RxThresholdLevel));
assert_param(IS_USI_SPI_TxThresholdLevel(USI_SSI_InitStruct->USI_SPI_TxThresholdLevel));
/* Set USI to SPI mode */
TempValue1 = usi_dev->USI_MODE_CTRL;
TempValue1 &= ~USI_SERIAL_MODE;
TempValue1 |= USI_SERIAL_SPI_MODE;
usi_dev->USI_MODE_CTRL = TempValue1;
/* Disable SPI and Tx/Rx Path, for some bits in SPI_CTRL are writeable only when Tx/Rx path are both disable.*/
USI_SSI_Cmd(usi_dev, DISABLE);
USI_SSI_TRxPath_Cmd(usi_dev, USI_SPI_RX_ENABLE | USI_SPI_TX_ENABLE, DISABLE);
/* Set SPI Control Register */
TempValue1 = 0;
TempValue1 |= USI_SSI_InitStruct->USI_SPI_DataFrameSize;
TempValue1 |= (USI_SSI_InitStruct->USI_SPI_SclkPhase << 6);
TempValue1 |= (USI_SSI_InitStruct->USI_SPI_SclkPolarity << 7);
/* Master Only */
if (USI_SSI_InitStruct->USI_SPI_Role & USI_SPI_MASTER) {
TempValue1 |= (USI_SSI_InitStruct->USI_SPI_ClockDivider) << 16;
TempValue1 |= (USI_SSI_InitStruct->USI_SPI_RxSampleDelay) << 8;
TempValue1 |= (USI_SSI_InitStruct->USI_SPI_SSTogglePhase) << 5;
TempValue1 |= USI_SPI_MASTER_MODE;
TempValue2 |= (USI_SSI_InitStruct->USI_SPI_DataFrameNumber) << 16;
}
usi_dev->SPI_CTRL = TempValue1;
/* Set Tx/Rx FIFO Threshold Level*/
usi_dev->TX_FIFO_CTRL = USI_SPI_TX_FIFO_DEPTH - USI_SSI_InitStruct->USI_SPI_TxThresholdLevel;
usi_dev->RX_FIFO_CTRL = USI_SSI_InitStruct->USI_SPI_RxThresholdLevel + 1;
/* Set interrupt */
usi_dev->INTERRUPT_ENABLE = USI_SSI_InitStruct->USI_SPI_InterruptMask & USI_SPI_INTERRUPT_MASK;
/*DMA level set */
USI_SSI_SetDmaLevel(usi_dev, USI_SSI_InitStruct->USI_SPI_DmaTxDataLevel, USI_SSI_InitStruct->USI_SPI_DmaRxDataLevel);
/* Set Tx/Rx Path enable */
switch(USI_SSI_InitStruct->USI_SPI_TransferMode){
case USI_SPI_TMOD_TO:
TempValue2 |= USI_SPI_TX_ENABLE;
break;
case USI_SPI_TMOD_RO:
TempValue2 |= USI_SPI_RX_ENABLE;
break;
case USI_SPI_TMOD_TR:
TempValue2 |= (USI_SPI_TX_ENABLE | USI_SPI_RX_ENABLE);
break;
default:
break;
}
usi_dev->SPI_TRANS_EN = TempValue2;
/* Enable SPI. SPI can work normally when Tx/Rx Path and all logic are released.*/
USI_SSI_Cmd(usi_dev, ENABLE);
}
/**
* @brief Enables or disables USI-SPI peripheral.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param NewStatus: This parameter can be one of the following values:
* @arg ENABLE
* @arg DISABLE
* @retval None
*/
void USI_SSI_Cmd(USI_TypeDef *usi_dev, u32 NewStatus)
{
if (NewStatus != DISABLE) {
usi_dev->SW_RESET |= USI_SW_RESET_RSTB | USI_SW_RESET_RXFIFO_RSTB |
USI_SW_RESET_TXFIFO_RSTB | USI_SW_RESET_RX_RSTB | USI_SW_RESET_TX_RSTB;
} else {
usi_dev->SW_RESET &= ~USI_SW_RESET_RSTB;
}
}
/**
* @brief Enables or disables USI-SPI Tx or Rx path.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param path: Tx or Rx path control bit, which can be
* @arg USI_SPI_TX_ENABLE
* @arg USI_SPI_RX_ENABLE
* @param NewStatus: This parameter can be one of the following values:
* @arg ENABLE
* @arg DISABLE
* @retval None
*/
void USI_SSI_TRxPath_Cmd(USI_TypeDef *usi_dev, u32 path, u32 NewStatus)
{
if(NewStatus != DISABLE){
usi_dev->SPI_TRANS_EN |= path;
} else {
usi_dev->SPI_TRANS_EN &= ~path;
}
}
/**
* @brief Get USI-SPI Tx/Rx path configuration.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval Current TRx Path setting, each bit of this value represents one
* path which is as follows:
*
* bit 1 : USI_SPI_RX_ENABLE
* - 0 : Rx Path is disable
* - 1 : Rx Path is enable
*
* bit 0 : USI_SPI_TX_ENABLE
* - 0 : Tx Path is disable
* - 1 : Tx Path is enable
*
* @retval None
*/
u32 USI_SSI_GetTRxPath(USI_TypeDef *usi_dev)
{
return usi_dev->SPI_TRANS_EN & (USI_SPI_RX_ENABLE | USI_SPI_TX_ENABLE);
}
/**
* @brief Set USI SPI as Master or Slave.
* @param usi_dev: where spi_dev can be USI0_DEV.
* @param role: This parameter can be one of the following values:
* @arg USI_SPI_MASTER
* @arg USI_SPI_SLAVE
* @retval None
*/
void USI_SSI_SetRole(USI_TypeDef *usi_dev, u32 role)
{
u32 Temp;
u32 trxpath = USI_SSI_GetTRxPath(usi_dev);
Temp = usi_dev->SPI_CTRL;
Temp &= ~USI_SPI_MASTER_MODE;
Temp |= (role << 4);
/* USI_SPI_MASTER_MODE is writeable only when Tx and Rx path are both disable */
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, DISABLE);
usi_dev->SPI_CTRL = Temp;
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, ENABLE);
}
/**
* @brief Enable or Disable USI-SPI interrupt.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param USI_SSI_IT: This parameter can be one of the following values or mixed:
* @arg USI_TXFIFO_ALMOST_EMTY_INTR_EN
* @arg USI_TXFIFO_OVERFLOW_INTR_EN
* @arg USI_TXFIFO_UNDERFLOW_INTR_EN
* @arg USI_RXFIFO_ALMOST_FULL_INTR_EN
* @arg USI_RXFIFO_OVERFLOW_INTR_EN
* @arg USI_RXFIFO_UNDERFLOW_INTR_EN
* @arg USI_SPI_RX_DATA_FRM_ERR_INTER_EN
* @param newState:This parameter can be one of the following values:
* @arg ENABLE
* @arg DISABLE
* @retval None
*/
VOID
USI_SSI_INTConfig(USI_TypeDef* usi_dev, u32 USI_SSI_IT, u32 newState)
{
if (newState == ENABLE) {
/* Enable the selected SSI interrupts */
usi_dev->INTERRUPT_ENABLE |= USI_SSI_IT;
} else {
/* Disable the selected SSI interrupts */
usi_dev->INTERRUPT_ENABLE &= ~USI_SSI_IT;
}
}
/**
* @brief Set USI-SPI clock polarity.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param SclkPolarity: This parameter can be one of the following values:
* @arg USI_SPI_SCPOL_INACTIVE_IS_HIGH
* @arg USI_SPI_SCPOL_INACTIVE_IS_LOW
* @retval None
*/
void USI_SSI_SetSclkPolarity(USI_TypeDef *usi_dev, u32 SclkPolarity)
{
u32 Value;
u32 trxpath = USI_SSI_GetTRxPath(usi_dev);
Value = usi_dev->SPI_CTRL;
Value &= ~ USI_SPI_CPOL;
Value |= (SclkPolarity << 7);
/* SPI_CPOL is writeable only when Tx and Rx path are both disable */
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, DISABLE);
usi_dev->SPI_CTRL = Value;
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, ENABLE);
}
/**
* @brief Set USI-SPI clock phase.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param SclkPhase: This parameter can be one of the following values:
* @arg USI_SPI_SCPH_TOGGLES_IN_MIDDLE
* @arg USI_SPI_SCPH_TOGGLES_AT_START
* @retval None
*/
void USI_SSI_SetSclkPhase(USI_TypeDef *usi_dev, u32 SclkPhase)
{
u32 Value;
u32 trxpath = USI_SSI_GetTRxPath(usi_dev);
Value = usi_dev->SPI_CTRL;
Value &= ~USI_SPI_CPH;
Value |= (SclkPhase << 6);
/* SPI_CPH is writeable only when Tx and Rx path are both disable */
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, DISABLE);
usi_dev->SPI_CTRL = Value;
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, ENABLE);
}
/**
* @brief Set USI-SPI SS Toggle Phase.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param TogglePhase: This parameter can be one of the following values:
* @arg USI_SPI_SS_NOT_TOGGLE , means SPI support continuous transfer when spi_cph=0
* @arg USI_SPI_SS_TOGGLE, means SPI donot support continuous transfer when spi_cph=0
* and SS(CS) needs break.
* @retval None
*/
void USI_SSI_SetSSTogglePhase(USI_TypeDef *usi_dev, u32 TogglePhase)
{
u32 Value;
u32 trxpath = USI_SSI_GetTRxPath(usi_dev);
Value = usi_dev->SPI_CTRL;
Value &= ~USI_SPI_SS_TOG_PHASE;
Value |= (TogglePhase << 5);
/* SPI_SS_TOG_PHASE is writeable only when Tx and Rx path are both disable */
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, DISABLE);
usi_dev->SPI_CTRL = Value;
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, ENABLE);
}
/**
* @brief Set USI-SPI data frame size.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param DataFrameSize: This parameter can be one of the following values:
* @arg USI_SPI_DFS_4_BITS
* @arg USI_SPI_DFS_5_BITS
* @arg USI_SPI_DFS_6_BITS
* @arg USI_SPI_DFS_7_BITS
* @arg USI_SPI_DFS_8_BITS
* @arg USI_SPI_DFS_9_BITS
* @arg USI_SPI_DFS_10_BITS
* @arg USI_SPI_DFS_11_BITS
* @arg USI_SPI_DFS_12_BITS
* @arg USI_SPI_DFS_13_BITS
* @arg USI_SPI_DFS_14_BITS
* @arg USI_SPI_DFS_15_BITS
* @arg USI_SPI_DFS_16_BITS
* @retval None
*/
void USI_SSI_SetDataFrameSize(USI_TypeDef *usi_dev, u32 DataFrameSize)
{
u32 Value;
u32 trxpath = USI_SSI_GetTRxPath(usi_dev);
Value = usi_dev->SPI_CTRL;
Value &= ~USI_SPI_DAT_FRM_SIZE;
Value |= DataFrameSize;
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, DISABLE);
usi_dev->SPI_CTRL = Value;
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, ENABLE);
}
/**
* @brief Set USI-SPI Rx Sample Dealy.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param SampleDelay: The number of ssi_clk cycles that to be delayed.
* @retval None
*/
void USI_SSI_SetSampleDelay(USI_TypeDef *usi_dev, u32 SampleDelay)
{
u32 Value;
u32 trxpath = USI_SSI_GetTRxPath(usi_dev);
Value = usi_dev->SPI_CTRL;
Value &= ~USI_SPI_RX_SAMPLE_DLY;
Value |= (SampleDelay << 8);
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, DISABLE);
usi_dev->SPI_CTRL = Value;
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, ENABLE);
}
/**
* @brief Set the number of data frame to be received.
* @note Valid only when the device is configured as a master in RX Only mode.
* @param usi_dev: where usi_dev can only be USI0_DEV.
* @param DataFrameNumber: The number of data frames that to be received.
* @retval None
*/
void USI_SSI_SetReadLen(USI_TypeDef *usi_dev, u32 DataFrameNumber)
{
u32 Value;
u32 trxpath = USI_SSI_GetTRxPath(usi_dev);
assert_param((DataFrameNumber >= 1)&&(DataFrameNumber <= 0x10000));
Value = usi_dev->SPI_TRANS_EN;
Value &= ~USI_SPI_RXONLY_NUM;
Value |= ((DataFrameNumber - 1) << 16);
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, DISABLE);
usi_dev->SPI_TRANS_EN = Value;
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, ENABLE);
}
/**
* @brief Set USI-SPI clock divider.
* @note Valid only when the device is configured as a master.
* And The LSB is always set to 0,and is unaffected by a write operation.
* @param usi_dev: where usi_dev can only be USI0_DEV.
* @param ClockDivider: Even value between 2 and 65534.
* And Fsclk_out=Fssi_clk/ClockDivider.
* @retval None
*/
void USI_SSI_SetBaudDiv(USI_TypeDef *usi_dev, u32 ClockDivider)
{
u32 Value;
u32 trxpath = USI_SSI_GetTRxPath(usi_dev);
Value = usi_dev->SPI_CTRL;
Value &= ~USI_SPI_MST_BAUD;
Value |= (ClockDivider << 16);
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, DISABLE);
usi_dev->SPI_CTRL = Value;
USI_SSI_TRxPath_Cmd(usi_dev, trxpath, ENABLE);
}
/**
* @brief Set USI-SPI Master clock.
* @param USIx: where SPIx can be USI0_DEV.
* @param BaudRate: baudrate for SPI bus, unit is HZ.
* @param IpClk: IP Clock
* @retval None
* @note Valid only when the device is configured as a master.
* @note BaudRate <= (IpClk/2).
* @note As the clock divider can only be an even number. The final baudrate this function generates
* may be a little lower than the value of BaudRate,which is setted by user.
* @note Fsclk_out = Fssi_clk /SCKDV
* @note for FPGA IpClk = CPU_ClkGet(_TRUE)
* @note for ASIC IpClk = CPU_ClkGet(_FALSE)/2
*/
void USI_SSI_SetBaud(USI_TypeDef *USIx, u32 BaudRate, u32 IpClk)
{
u32 ClockDivider;
assert_param(USIx == USI0_DEV);
assert_param(BaudRate <= (IpClk/2));
/*Adjust SCKDV-Parameter to an even number */
ClockDivider = IpClk/BaudRate + 1;
if ((IpClk%BaudRate) > (BaudRate/2)) {
ClockDivider++;
}
if (ClockDivider >= 0xFFFF) {
/* devider is 16 bits */
ClockDivider = 0xFFFE;
}
ClockDivider &= 0xFFFE; // bit 0 always is 0
USI_SSI_SetBaudDiv(USIx, ClockDivider);
}
/**
* @brief Enables or disables USI-SPI TDMA and RDMA .
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param newState: This parameter can be one of the following values:
* @arg ENABLE
* @arg DISABLE
* @param Mask: This parameter can be one of the following values or mixed:
* @arg USI_TX_DMA_ENABLE
* @arg USI_RX_DMA_ENABLE
* @retval None
*/
void USI_SSI_SetDmaEnable(USI_TypeDef *usi_dev, u32 newState, u32 Mask)
{
if (newState == DISABLE)
usi_dev->DMA_ENABLE &= ~Mask;
else
usi_dev->DMA_ENABLE |= Mask;
}
/**
* @brief Set USI-SPI DMA TxLevel and RxLevel.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param TxLevel: Transmit FIFO Threshold level.Value range: 0 to 63.
* The dma_tx_req is generated when the number of valid data entries in
* the transmit FIFO is equal to or below this field value.
* @param RxLevel: Receive FIFO Threshold level.Value range: 0 to 63.
* The dma_rx_req is generated when the number of valid data entries in the
* receive FIFO is equal to or above this field value + 1.
* @retval None
*/
void USI_SSI_SetDmaLevel(USI_TypeDef *usi_dev, u32 TxLevel, u32 RxLevel)
{
u32 value = usi_dev->DMA_REQ_SIZE;
assert_param(IS_USI_SPI_TxDMALevel(TxLevel));
assert_param(IS_USI_SPI_RxDMALevel(RxLevel));
/* Set TX FIFO water level to trigger Tx DMA transfer */
value &= ~USI_TX_DMA_BURST_SIZE;
value |= (USI_SPI_TX_FIFO_DEPTH - TxLevel);
/* Set RX FIFO water level to trigger Rx DMA transfer */
value &= ~USI_RX_DMA_BURST_SIZE;
value |= ((RxLevel + 1) << 16);
usi_dev->DMA_REQ_SIZE = value;
}
/**
* @brief Init and Enable USI-SPI TX GDMA.
* @param Index: 0.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pTxData: Tx Buffer.
* @param Length: Tx Count.
* @retval TRUE/FLASE
*/
BOOL USI_SSI_TXGDMA_Init(
u32 Index,
PGDMA_InitTypeDef GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pTxData,
u32 Length
)
{
USI_TypeDef *USIx = USI_DEV_TABLE[Index].USIx;
u32 DataFrameSize = USI_SSI_GetDataFrameSize(USIx);
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, CallbackFunc, (u32)CallbackData, 12);//ACUT is 0x10, BCUT is 12
if (GdmaChnl == 0xFF) {
// No Available DMA channel
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->GDMA_DIR = TTFCMemToPeri;
GDMA_InitStruct->GDMA_DstHandshakeInterface = USI_DEV_TABLE[Index].Tx_HandshakeInterface;
GDMA_InitStruct->GDMA_DstAddr = (u32)&USI_DEV_TABLE[Index].USIx->TX_FIFO_WRITE;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_SrcMsize = MsizeOne;
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_DstInc = NoChange;
GDMA_InitStruct->GDMA_SrcInc = IncType;
/* Cofigure GDMA transfer */
if (DataFrameSize > 8) {
/* 16~9 bits mode */
if (((Length & 0x03)==0) && (((u32)(pTxData) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_DstMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 2;
} else if (((Length & 0x01)==0) && (((u32)(pTxData) & 0x01)==0)) {
/* 2-bytes aligned, move 2 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeEight;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_DstMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 1;
} else {
DBG_8195A("SSI_TXGDMA_Init: Aligment Err: pTxData=0x%x, Length=%d\n", pTxData, Length);
return _FALSE;
}
} else {
/* 8~4 bits mode */
if (((Length & 0x03)==0) && (((u32)(pTxData) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeOne;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 2;
} else {
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_BlockSize = Length;
}
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
}
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
GDMA_InitStruct->GDMA_SrcAddr = (u32)pTxData;
/* Enable GDMA for TX */
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Init and Enable USI-SPI RX GDMA.
* @param Index: 0.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pRxData: Rx Buffer.
* @param Length: Rx Count.
* @retval TRUE/FLASE
*/
BOOL
USI_SSI_RXGDMA_Init(
u8 Index,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pRxData,
u32 Length
)
{
USI_TypeDef *USIx = USI_DEV_TABLE[Index].USIx;
u32 DataFrameSize = USI_SSI_GetDataFrameSize(USIx);
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, CallbackFunc, (u32)CallbackData, 12);//ACUT is 0x10, BCUT is 12
if (GdmaChnl == 0xFF) {
// No Available DMA channel
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem;
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->GDMA_SrcHandshakeInterface = USI_DEV_TABLE[Index].Rx_HandshakeInterface;
GDMA_InitStruct->GDMA_SrcAddr = (u32)&USI_DEV_TABLE[Index].USIx->RX_FIFO_READ;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_SrcMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_DstInc = IncType;
GDMA_InitStruct->GDMA_SrcInc = NoChange;
/* Cofigure GDMA transfer */
if (DataFrameSize > 8) {
/* 16~9 bits mode */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthTwoBytes;
GDMA_InitStruct->GDMA_BlockSize = Length >> 1;
if (((Length & 0x03)==0) && (((u32)(pRxData) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
} else if (((Length & 0x01)==0) && (((u32)(pRxData) & 0x01)==0)) {
/* 2-bytes aligned, move 2 bytes each transfer */
GDMA_InitStruct->GDMA_DstMsize = MsizeEight;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthTwoBytes;
} else {
DBG_8195A("SSI_RXGDMA_Init: Aligment Err: pTxData=0x%x, Length=%d\n", pRxData, Length);
return _FALSE;
}
} else {
/* 8~4 bits mode */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_BlockSize = Length;
if (((Length & 0x03)==0) && (((u32)(pRxData) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_DstMsize = MsizeOne;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
} else {
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
}
}
assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096);
GDMA_InitStruct->GDMA_DstAddr = (u32)pRxData;
/* Enable GDMA for RX */
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Clear USI-SPI interrupt status.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param InterruptStatus: The value of current interrupt status .
* @retval None
*/
void USI_SSI_SetIsrClean(USI_TypeDef *usi_dev, u32 InterruptStatus)
{
usi_dev->INTERRUPT_STATUS_CLR = InterruptStatus & USI_SPI_INTERRUPT_CLEAR_MASK;
}
/**
* @brief Write data to USI-SPI transmit FIFO.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param value: The data value that is to be transmitted .
* @retval None
*/
void USI_SSI_WriteData(USI_TypeDef *usi_dev, u32 value)
{
usi_dev->TX_FIFO_WRITE = (value & USI_TX_FIFO_WRITE_DATA);
}
/**
* @brief Set USI-SPI Rx FIFO threshold level
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param RxThresholdLevel: Rx FIFO Threshold Level.Value range: 0 to 63.
* When the number of receive FIFO entries is greater than or equal to
* this value + 1, the receive FIFO full interrupt is triggered.
* @retval None
*/
void USI_SSI_SetRxFifoLevel(USI_TypeDef *usi_dev, u32 RxThresholdLevel)
{
assert_param(IS_USI_SPI_RxThresholdLevel(RxThresholdLevel));
usi_dev->RX_FIFO_CTRL = RxThresholdLevel + 1;
}
/**
* @brief Set USI-SPI Tx FIFO threshold level.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param TxThresholdLevel: Tx FIFO Threshold Level.Value range: 0 to 63.
* When the number of transmit FIFO entries is less than or equal to this
* value, the transmit FIFO empty interrupt is triggered.
* @retval None
*/
void USI_SSI_SetTxFifoLevel(USI_TypeDef *usi_dev, u32 TxThresholdLevel)
{
assert_param(IS_USI_SPI_TxThresholdLevel(TxThresholdLevel));
usi_dev->TX_FIFO_CTRL = USI_SPI_TX_FIFO_DEPTH - TxThresholdLevel;
}
/**
* @brief Detemines whether USI-SPI transmit FIFO is full or not
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval Transmit FIFO is full or not:
* - 1: Not Full
* - 0: Full
*/
u32 USI_SSI_Writeable(USI_TypeDef *usi_dev)
{
u32 Status = USI_SSI_GetTxFIFOStatus(usi_dev);
u32 Writeable = (((Status & USI_TXFIFO_FULL) == 0) ? 1 : 0);
return Writeable;
}
/**
* @brief Detemine USI-SPI Receive FIFO is empty or not.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval Receive FIFO is empty or not:
* - 1: Not Empty
* - 0: Empty
*/
u32 USI_SSI_Readable(USI_TypeDef *usi_dev)
{
u32 Status = USI_SSI_GetRxFIFOStatus(usi_dev);
u32 Readable = (((Status & USI_RXFIFO_EMPTY) == 0) ? 1 : 0);
return Readable;
}
/**
* @brief Read data from USI-SPI receive FIFO .
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval The data received.
*/
u32 USI_SSI_ReadData(USI_TypeDef *usi_dev)
{
return usi_dev->RX_FIFO_READ;
}
/**
* @brief receive data from rx FIFO
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param RxData: buffer to save data read from USI-SPI FIFO.
* @param Length: number of data to be read.
* @retval transfer len
*/
u32 USI_SSI_ReceiveData(USI_TypeDef *usi_dev,
void* RxData,
u32 Length
)
{
u32 ReceiveLevel;
u32 DataFrameSize = USI_SSI_GetDataFrameSize(usi_dev);
volatile u32 Readable = USI_SSI_Readable(usi_dev);
u32 RxLength = Length;
while (Readable) {
ReceiveLevel = USI_SSI_GetRxCount(usi_dev);
while (ReceiveLevel--) {
if (RxData != NULL) {
if (DataFrameSize > 8) {
/* 16~9 bits mode */
*((u16*)(RxData)) = (u16)USI_SSI_ReadData(usi_dev);
RxData = (VOID*)(((u16*)RxData) + 1);
} else {
/* 8~4 bits mode */
*((u8*)(RxData)) = (u8)USI_SSI_ReadData(usi_dev);
RxData = (VOID*)(((u8*)RxData) + 1);
}
} else {
/* for Master mode, doing TX also will got RX data, so drop the dummy data */
USI_SSI_ReadData(usi_dev);
}
if (RxLength > 0) {
RxLength--;
}
if (RxLength == 0) {
break;
}
}
if (RxLength == 0) {
break;
}
Readable = USI_SSI_Readable(usi_dev);
}
return (Length - RxLength);
}
/**
* @brief Send data to tx FIFO
* @param usi_dev: where usi_dev can be USI0_DEV.
* @param TxData: buffer to be written to Tx FIFO.
* @param Length: number of data to be written.
* @param Role: USI_SPI_MASTER or USI_SPI_SLAVE.
* @retval transfer len
*/
u32 USI_SSI_SendData(USI_TypeDef *usi_dev,
void* TxData,
u32 Length,
u32 Role
)
{
u32 Writeable = USI_SSI_Writeable(usi_dev);
u32 TxWriteMax = USI_SPI_TX_FIFO_DEPTH - USI_SSI_GetTxCount(usi_dev);
u32 DataFrameSize = USI_SSI_GetDataFrameSize(usi_dev);
u32 TxLength = Length;
if (Writeable) {
/* Disable Tx FIFO Empty IRQ */
USI_SSI_INTConfig(usi_dev, USI_TXFIFO_ALMOST_EMTY_INTR_EN, DISABLE);
while (TxWriteMax--) {
if (DataFrameSize > 8) {
// 16~9 bits mode
if (TxData != NULL) {
USI_SSI_WriteData(usi_dev, *((u16*)(TxData)));
TxData = (VOID*)(((u16*)TxData) + 1);
} else {
// For master mode: Push a dummy to TX FIFO for Read
if (Role == USI_SPI_MASTER) {
USI_SSI_WriteData(usi_dev, (u16)0);// Dummy byte
}
}
} else {
// 8~4 bits mode
if (TxData != NULL) {
USI_SSI_WriteData(usi_dev, *((u8*)(TxData)));
TxData = (VOID*)(((u8*)TxData) + 1);
} else {
// For master mode: Push a dummy to TX FIFO for Read
if (Role == USI_SPI_MASTER) {
USI_SSI_WriteData(usi_dev, (u8)0);// Dummy byte
}
}
}
TxLength--;
if (TxLength == 0)
break;
}
/* Enable Tx FIFO Empty IRQ */
USI_SSI_INTConfig(usi_dev, USI_TXFIFO_ALMOST_EMTY_INTR_EN, ENABLE);
}
return (Length - TxLength);
}
/**
* @brief Get the number of valid entries in receive FIFO.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval The number of valid entries in receive FIFO.Value range:0-64.
*/
u32 USI_SSI_GetRxCount(USI_TypeDef *usi_dev)
{
u32 valid_cnt = (USI_SSI_GetRxFIFOStatus(usi_dev) & USI_RXFIFO_VALID_CNT) >> 8;
return valid_cnt;
}
/**
* @brief Get the number of valid entries in transmit FIFO.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval The number of valid entries in transmit FIFO.Value range:0-64.
*/
u32 USI_SSI_GetTxCount(USI_TypeDef *usi_dev)
{
u32 empty_cnt = (USI_SSI_GetTxFIFOStatus(usi_dev) & USI_TXFIFO_EMPTY_SPACE) >> 8;
return USI_SPI_TX_FIFO_DEPTH - empty_cnt;
}
/**
* @brief Get USI-SPI Tx FIFO status.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval Current Tx FIFO status:
*
* bit [8:14] : USI_TXFIFO_EMPTY_SPACE
* - Tx FIFO empty entry count
*
* bit 2 : USI_TXFIFO_ALMOST_EMPTY_COPY
* - 0 : Tx FIFO not almost empty
* - 1 : Tx FIFO almost empty
*
* bit 1 : USI_TXFIFO_EMPTY
* - 0 : Tx FIFO not empty
* - 1 : Tx FIFO is empty
*
* bit 0 : USI_TXFIFO_FULL
* - 0 : Tx FIFO not full
* - 1 : Tx FIFO is full
*
*/
u32 USI_SSI_GetTxFIFOStatus(USI_TypeDef *usi_dev)
{
return usi_dev->TX_FIFO_STATUS;
}
/**
* @brief Get USI-SPI Rx FIFO status.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval Current Rx FIFO status:
*
* bit [8:14] : USI_RXFIFO_VALID_CNT
* - Rx FIFO valid count
*
* bit 2 : USI_RXFIFO_ALMOST_FULL_COPY
* - 0 : Rx FIFO not almost full
* - 1 : Rx FIFO almost full
*
* bit 1 : USI_RXFIFO_EMPTY
* - 0 : Rx FIFO not empty
* - 1 : Rx FIFO is empty
*
* bit 0 : USI_RXFIFO_FULL
* - 0 : Rx FIFO not full
* - 1 : Rx FIFO is full
*
*/
u32 USI_SSI_GetRxFIFOStatus(USI_TypeDef *usi_dev)
{
return usi_dev->RX_FIFO_STATUS;
}
/**
* @brief Get USI-SPI transfer status.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval Current transfer status,each bit of this value represents one
* transfer status which is as follows:
*
* bit 4 : USI_SPI_SLV_RX_ACTIVITY
* - 0 : SPI slave Rx path idle
* - 1 : SPI slave Rx path is active
*
* bit 3 : USI_SPI_SLV_TX_ACTIVITY
* - 0 : SPI slave Tx path idle
* - 1 : SPI slave Tx path is active
*
* bit 2 : USI_SPI_MST_RX_ACTIVITY
* - 0 : SPI master Rx path idle
* - 1 : SPI master Rx path is active
*
* bit 1 : USI_SPI_MST_TX_ACTIVITY
* - 0 : SPI master Tx path idle
* - 1 : SPI master Tx path is active
*
* bit 0 : USI_SPI_ACTIVITY
* - 0 : idle
* - 1 : active transferring data
*
*/
u32 USI_SSI_GetTransStatus(USI_TypeDef *usi_dev)
{
return usi_dev->SPI_TRANS_STATUS;
}
/**
* @brief Get USI-SPI data frame size.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval Data frame size(value range : 4-16):
* - n : current data frame length is n bits
*/
u32 USI_SSI_GetDataFrameSize(USI_TypeDef *usi_dev)
{
u32 size = ((usi_dev->SPI_CTRL) & USI_SPI_DAT_FRM_SIZE) + 1;
return size;
}
/**
* @brief Detemine USI-SPI is busy or not.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval USI-SPI busy status value:
* - 1: Busy
* - 0: Not Busy
*/
u32 USI_SSI_Busy(USI_TypeDef *usi_dev)
{
u32 Status = USI_SSI_GetTransStatus(usi_dev);
u32 Busy = (((Status & USI_SPI_ACTIVITY) != 0) ? 1 : 0);
return Busy;
}
/**
* @brief Get USI-SPI Interrupt Status.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval Current Interrupt Status,each bit of this value represents one
* interrupt status which is as follows:
*
* bit 16: USI_SPI_RX_DATA_FRM_ERR_INTS
* - 0 : spi_rx_data_frame_err_intr interrupt not active after masking
* - 1 : spi_rx_data_frame_err_intr interrupt is active after masking
* bit 6 : USI_RXFIFO_UNDERFLOW_INTS
* - 0 : rxfifo_underflow_intr interrupt not active after masking
* - 1 : rxfifo_underflow_intr interrupt is active after masking
*
* bit 5 : USI_RXFIFO_OVERFLOW_INTS
* - 0 : rxfifo_overflow_intr interrupt is not active after masking
* - 1 : rxfifo_overflow_intr interrupt is full after masking
*
* bit 4 : USI_RXFIFO_ALMOST_FULL_INTS
* - 0 : rxfifo_almost_full_intr interrupt is not active after masking
* - 1 : rxfifo_almost_full_intr interrupt is active after masking
*
* bit 2 : USI_TXFIFO_UNDERFLOW_INTS
* - 0 : txfifo_underflow_intr interrupt is not active after masking
* - 1 : txfifo_underflow_intr interrupt is active after masking
*
* bit 1 : USI_TXFIFO_OVERFLOW_INTS
* - 0 : txfifo_overflow_intr interrupt is not active after masking
* - 1 : txfifo_overflow_intr interrupt is active after masking
*
* bit 0 : USI_TXFIFO_ALMOST_EMTY_INTS
* - 0 : txfifo_almost_empty_intr interrupt is not active after masking
* - 1 : txfifo_almost_empty_intr interrupt is active after masking
*/
u32 USI_SSI_GetIsr(USI_TypeDef *usi_dev)
{
return usi_dev->INTERRUPT_STATUS;
}
/**
* @brief Get USI-SPI Raw Interrupt Status.
* @param usi_dev: where usi_dev can be USI0_DEV.
* @retval Current Raw Interrupt Status,each bit of this value represents one
* raw interrupt status which is as follows:
*
* bit 16: USI_SPI_RX_DATA_FRM_ERR_RSTS
* - 0 : spi_rx_data_frame_err_intr interrupt not active before masking
* - 1 : spi_rx_data_frame_err_intr interrupt is active before masking
*
* bit 6 : USI_RXFIFO_UNDERFLOW_RSTS
* - 0 : rxfifo_underflow_intr interrupt not active before masking
* - 1 : rxfifo_underflow_intr interrupt is active before masking
*
* bit 5 : USI_RXFIFO_OVERFLOW_RSTS
* - 0 : rxfifo_overflow_intr interrupt is not active before masking
* - 1 : rxfifo_overflow_intr interrupt is full before masking
*
* bit 4 : USI_RXFIFO_ALMOST_FULL_RSTS
* - 0 : rxfifo_almost_full_intr interrupt is not active before masking
* - 1 : rxfifo_almost_full_intr interrupt is active before masking
*
* bit 2 : USI_TXFIFO_UNDERFLOW_RSTS
* - 0 : txfifo_underflow_intr interrupt is not active before masking
* - 1 : txfifo_underflow_intr interrupt is active before masking
*
* bit 1 : USI_TXFIFO_OVERFLOW_RSTS
* - 0 : txfifo_overflow_intr interrupt is not active before masking
* - 1 : txfifo_overflow_intr interrupt is active before masking
*
* bit 0 : USI_TXFIFO_ALMOST_EMTY_RSTS
* - 0 : txfifo_almost_empty_intr interrupt is not active before masking
* - 1 : txfifo_almost_empty_intr interrupt is active before masking
*
*/
u32 USI_SSI_GetRawIsr(USI_TypeDef *usi_dev)
{
return usi_dev->RAW_INTERRUPT_STATUS;
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_usi_ssi.c
|
C
|
apache-2.0
| 36,965
|
/**
******************************************************************************
* @file rtl8721dhp_usi_uart.c
* @author
* @version V1.0.0
* @date 2017-09-30
* @brief This file contains all the functions prototypes for the USI UART firmware
* library, including the following functionalities of the Universal Asynchronous
* Receiver/Transmitter (UART) peripheral:
* - Initialization
* - Clear UART TX/RX FIFO
* - Uart Rx Path Control (disable/enable)
* - Baud Rate Setting
* - Receive/Send Data Interface
* - Uart Low Power Rx Initialization
* - Uart Low Power Rx Monitor Function Initialization
* - Low Power Rx Baud Rate Setting
* - Uart IrDA Function Initialization
* - Uart Rx Byte Counter Interface
* - Interrupts and flags management
*
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
#include "rtl8721d_usi_uart.h"
const USI_DevTable USI_DEV_TABLE[1] = {
{USI0_DEV, GDMA_HANDSHAKE_INTERFACE_USI0_TX, GDMA_HANDSHAKE_INTERFACE_USI0_RX, USI_IRQ}
};
u32 USI_UART_StateTx[1];
u32 USI_UART_StateRx[1];
USI_UARTCFG_TypeDef usi_uart_config[2]=
{
/* USI0-UART */
{
.LOW_POWER_RX_ENABLE = DISABLE, /*Enable low power RX*/
},
/* USI1-UART */
{
.LOW_POWER_RX_ENABLE = DISABLE,
},
};
/**
* @brief Deinitializes the USIx peripheral registers to their default reset values in USI UART mode.
* @param USIx: where x can be 0.
* @retval None
*/
void USI_UARTDeInit(USI_TypeDef* USIx)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*reset USI all logic*/
USIx->SW_RESET &=(~USI_SW_RESET_RSTB);
USIx->SW_RESET |=USI_SW_RESET_RSTB;
/*disable USI UART*/
USIx->USI_MODE_CTRL &= (~USI_SERIAL_MODE);
/*clear all USI UART interrupts*/
USIx->INTERRUPT_ALL_CLR = USI_INT_ALL_CLEAR;
/*disable all interrupts*/
USIx->INTERRUPT_ENABLE = 0x00000000;
}
/**
* @brief Fills each USI_UARTInitStruct member with its default value.
* @param USI_UARTInitStruct: pointer to an USI_UARTInitTypeDef structure which will be initialized.
* @retval None
*/
void USI_UARTStructInit(USI_UARTInitTypeDef* USI_UARTInitStruct)
{
/* USI_UARTInitStruct members default value */
USI_UARTInitStruct->USI_UARTParity = USI_RUART_PARITY_ENABLE;
USI_UARTInitStruct->USI_UARTParityType = USI_RUART_ODD_PARITY;
USI_UARTInitStruct->USI_UARTStickParity = USI_RUART_STICK_PARITY_DISABLE;
USI_UARTInitStruct->USI_UARTStopBit = USI_RUART_STOP_BIT_1;
USI_UARTInitStruct->USI_UARTWordLen = USI_RUART_WLS_8BITS;
USI_UARTInitStruct->USI_UARTRxFifoTrigLevel = 1;
USI_UARTInitStruct->USI_UARTDmaModeCtrl = ENABLE;
USI_UARTInitStruct->USI_UARTFlowControl = DISABLE;
USI_UARTInitStruct->USI_UARTTxFifoTrigLevel = 0x40;
USI_UARTInitStruct->USI_UARTFlwCtrlRxHoldThd = 0x04;
}
/**
* @brief Initializes the USIx peripheral according to the specified
* parameters in the USI_UARTInitStruct.
* @param USIx: where x can be 0.
* @param USI_UARTInitStruct: pointer to a USI_UARTInitTypeDef structure that contains
* the configuration information for the specified USART peripheral.
* @retval None
*/
void USI_UARTInit(USI_TypeDef* USIx, USI_UARTInitTypeDef *USI_UARTInitStruct)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
assert_param(USI_UARTInitStruct->USI_UARTRxFifoTrigLevel <= 0x40);
assert_param(IS_USI_UART_PARITY_ENABLE(USI_UARTInitStruct->USI_UARTParity));
assert_param(IS_USI_UART_PARITY_TYPE(USI_UARTInitStruct->USI_UARTParityType));
assert_param(IS_USI_UART_STICK_PARITY_ENABLE(USI_UARTInitStruct->USI_UARTStickParity));
assert_param(IS_USI_UART_STOP_BIT(USI_UARTInitStruct->USI_UARTStopBit));
assert_param(IS_USI_UART_WLS(USI_UARTInitStruct->USI_UARTWordLen));
assert_param(USI_UARTInitStruct->USI_UARTTxFifoTrigLevel <= 0x40);
assert_param(USI_UARTInitStruct->USI_UARTFlwCtrlRxHoldThd <= 0x40);
/*reset USI all logic, this step will clear tx/rx fifo*/
USIx->SW_RESET &=(~USI_SW_RESET_RSTB);
USIx->SW_RESET |=USI_SW_RESET_RSTB;
/*clear rx fifo and release rx fifo logic*/
USIx->SW_RESET &= (~USI_SW_RESET_RXFIFO_RSTB);
USIx->SW_RESET |= USI_SW_RESET_RXFIFO_RSTB;
/*clear tx fifo and release tx fifo logic*/
USIx->SW_RESET &= (~USI_SW_RESET_TXFIFO_RSTB);
USIx->SW_RESET |= USI_SW_RESET_TXFIFO_RSTB;
/*disable USI all mode, configure USI with UART mode*/
USIx->USI_MODE_CTRL &= (~USI_SERIAL_MODE);
USIx->USI_MODE_CTRL |= USI_SERIAL_UART_MODE;
/*reset RX path*/
USIx->SW_RESET &= (~USI_SW_RESET_RX_RSTB);
/*release TX path*/
USIx->SW_RESET |= USI_SW_RESET_TX_RSTB;
/*disable all interrupts*/
USIx->INTERRUPT_ENABLE = 0x00000000;
/*clear all USI UART interrupts*/
USIx->INTERRUPT_ALL_CLR = USI_INT_ALL_CLEAR;
/*configure RX fifo trigger level*/
USIx->RX_FIFO_CTRL &= (~USI_RXFIFO_ALMOST_FULL_TH);
USIx->RX_FIFO_CTRL |= USI_UARTInitStruct->USI_UARTRxFifoTrigLevel;
/*configure TX fifo trigger level*/
USIx->TX_FIFO_CTRL &= (~USI_TXFIFO_ALMOST_EMPTY_TH);
USIx->TX_FIFO_CTRL |= USI_UARTInitStruct->USI_UARTTxFifoTrigLevel;
/*set auto flow control RTS hold level*/
USIx->UART_FLOW_CTRL &= (~USI_UART_RX_HOLD_THRD);
USIx->UART_FLOW_CTRL |= USI_UARTInitStruct->USI_UARTFlwCtrlRxHoldThd<<8;
/* Configure FlowControl */
if (USI_UARTInitStruct->USI_UARTFlowControl == ENABLE) {
USIx->UART_FLOW_CTRL |= (USI_UART_AUTO_FLOW_EN|USI_UART_RX_RTS);
} else {
USIx->UART_FLOW_CTRL &= (~(USI_UART_AUTO_FLOW_EN|USI_UART_RX_RTS));
}
/*configure word length, stop bit, parity, parity type, stickparity*/
USIx->UART_CTRL &= (~(USI_UART_WORD_LEN_MD|USI_UART_STOP_BIT_MD|USI_UART_PARITY_ENABLE|USI_UART_PARITY_EVEN|USI_UART_STICK_PARITY_BIT));
USIx->UART_CTRL |= ((USI_UARTInitStruct->USI_UARTWordLen) |
(USI_UARTInitStruct->USI_UARTStopBit) |
(USI_UARTInitStruct->USI_UARTParity) |
(USI_UARTInitStruct->USI_UARTParityType) |
(USI_UARTInitStruct->USI_UARTStickParity));
if(USI_UARTInitStruct->USI_UARTDmaModeCtrl != ENABLE) {
/* disable the USI UART TX/RX DMA */
USIx->DMA_ENABLE &= ~ (USI_TX_DMA_ENABLE|USI_RX_DMA_ENABLE);
}
}
/**
* @brief get ovsr & ovsr_adj parameters for the given baudrate
* @param USIx: where x can be 0.
* @param baudrate: the desired baudrate
* @param ovsr: the pointer to ovsr parameter
* @param ovsr_adj: the pointer to ovsr_adj parameter
* @retval searching status:
* - 1: found
* - 0: not found
*/
u32 USI_UARTBaudParaGet(u32 baudrate, u32 *ovsr, u32 *ovsr_adj)
{
USI_UARTBaudParaGetFull(XTAL_ClkGet(), baudrate, ovsr, ovsr_adj);
return 1;
}
/**
* @brief get ovsr & ovsr_adj parameters according to the given baudrate and UART IP clock.
* @param USIx: where x can be 0.
* @param IPclk: the given UART IP clock, Unit: [ Hz ]
* @param baudrate: the desired baudrate, Unit: bps[ bit per second ]
* @param ovsr: integer parameter related to the desired baud rate
* @param ovsr_adj: fractional parameter related to the desired baud rate
* @retval None
*/
void USI_UARTBaudParaGetFull(u32 IPclk, u32 baudrate, u32 *ovsr, u32 *ovsr_adj)
{
u32 i;
u32 Remainder;
u32 TempAdj = 0;
u32 TempMultly;
/*obtain the ovsr parameter*/
*ovsr = IPclk / baudrate;
/*get the remainder related to the ovsr_adj parameter*/
Remainder = IPclk % baudrate;
/*calculate the ovsr_adj parameter*/
for(i = 0; i < 11; i++){
TempAdj = TempAdj << 1;
TempMultly = (Remainder * (12-i));
TempAdj |= ((TempMultly / baudrate - (TempMultly - Remainder) / baudrate) ? 1 : 0);
}
/*obtain the ovsr_adj parameter*/
*ovsr_adj = TempAdj;
}
/**
* @brief Set Uart Baud Rate use baudrate val.
* @param USIx: where x can be 0.
* @param BaudRate: Baud Rate Val, like 115200 (unit is HZ).
* @retval None
*/
void USI_UARTSetBaud(USI_TypeDef* USIx, u32 BaudRate)
{
u32 Ovsr;
u32 Ovsr_adj;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/* get baud rate parameter based on baudrate */
USI_UARTBaudParaGetFull(XTAL_ClkGet(), BaudRate, &Ovsr, &Ovsr_adj);
/*confgure TX path baudrate*/
USIx->UART_TX_FRACTION_BAUD &=(~(USI_UART_TX_XFACTOR|USI_UART_TX_XFACTOR_ADJ));
USIx->UART_TX_FRACTION_BAUD |= (Ovsr|(Ovsr_adj<<20));
/*configure RX path baudrate*/
USIx->UART_RX_BAUD_XTAL &= (~USI_RUART_LPRX_XTAL_CYCNUM_PERBIT);
USIx->UART_RX_BAUD_XTAL |= Ovsr;
USIx->UART_RX_FRACTION_BAUD_CTRL &= (~USI_UART_RX_XFACTOR_ADJ);
USIx->UART_RX_FRACTION_BAUD_CTRL |= Ovsr_adj;
}
/**
* @brief Set Uart Baud Rate use baudrate parameter Ovsr & Ovsr_adj.
* @param USIx: where x can be 0.
* @param Ovsr: Specifies the ovsr parameter related to baud rate.
* This parameter is caculated by using uart IP clock and the desired baud rate
* @param Ovsr_adj: Specifies the ovsr_adj parameter related fractional part for the desired baud rate.
* This parameter is also caculated by using uart IP clock and the desired baud rate
* @retval None
*/
void USI_UARTSetBaudExt(USI_TypeDef* USIx, u32 Ovsr, u32 Ovsr_adj)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*confgure TX path baudrate*/
USIx->UART_TX_FRACTION_BAUD &=(~(USI_UART_TX_XFACTOR|USI_UART_TX_XFACTOR_ADJ));
USIx->UART_TX_FRACTION_BAUD |= (Ovsr|(Ovsr_adj<<20));
/*configure RX path baudrate*/
USIx->UART_RX_BAUD_XTAL &= (~USI_RUART_LPRX_XTAL_CYCNUM_PERBIT);
USIx->UART_RX_BAUD_XTAL |= Ovsr;
USIx->UART_RX_FRACTION_BAUD_CTRL &= (~USI_UART_RX_XFACTOR_ADJ);
USIx->UART_RX_FRACTION_BAUD_CTRL |= Ovsr_adj;
}
/**
* @brief to set the RX FIFO level to trigger RX interrupt/RTS de-assert
* @param USIx: where x can be 0.
* @param FifoLv: USI UART RX FIFO level, this value can be 1 to 62.
*/
void USI_UARTSetRxLevel(USI_TypeDef* USIx, u32 FifoLv)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*configure RX interrupt trigger level*/
USIx->RX_FIFO_CTRL &= (~USI_RXFIFO_ALMOST_FULL_TH);
USIx->RX_FIFO_CTRL |= FifoLv;
/*configure RX CTS hold level*/
USIx->UART_FLOW_CTRL &=(~USI_UART_RX_HOLD_THRD);
USIx->UART_FLOW_CTRL |= (FifoLv<<8);
}
/**
* @brief enable or disable USI Uart Rx Path
* @param USIx: where x can be 0.
* @param NewState: the new state of the Rx Path.
* This parameter can be: ENABLE or DISABLE.
* @note Because the TX/RX of the IrDA transceiver are in the same module,
* RX fifo can also receive available data when in the process of TX.Therefore,
* the RX Path must be disabled when TX is going on.Namely, IrDA must work
* in the Half duplex mode, though normal UART IP supports Full duplex.
* @retval None
*/
void USI_UARTRxCmd(USI_TypeDef* USIx, u32 NewState)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
if (NewState != DISABLE) {
/*enable uart receiver*/
USIx->SW_RESET |= USI_SW_RESET_RX_RSTB;
} else {
/*disable uart receiver*/
USIx->SW_RESET &= (~USI_SW_RESET_RX_RSTB);
}
}
/**
* @brief check if write data to tx fifo.
* @param USIx: where x can be 0.
* @retval status value:
* - 1: tx fifo is empty and can write data to tx fifo
* - 0: tx fifo is not empty
*/
u32 USI_UARTWritable(USI_TypeDef* USIx)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*check if tx fifo is empty or not. empty return 1 and not empty return 0.*/
if (USIx->TX_FIFO_STATUS & USI_TXFIFO_EMPTY) {
return 1;
}
else {
return 0;
}
}
/**
* @brief check if there is data in rx fifo.
* @param USIx: where x can be 0.
* @retval status value:
* - 1: rx fifo has valid data and can read data from rx fifo
* - 0: rx fifo is empty
*/
u32 USI_UARTReadable(USI_TypeDef* USIx)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*check if rx fifo has available data.
available data return 1 and no available data return 0.*/
if (!(USIx->RX_FIFO_STATUS & USI_RXFIFO_EMPTY)) {
return 1;
}
else {
return 0;
}
}
/**
* @brief Transmits single data through the USIx peripheral.
* @param USIx: where x can be 0.
* @param TxData: the data to transmit.
* @retval None
*/
void USI_UARTCharPut(USI_TypeDef* USIx, u8 TxData)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*write one byte to tx fifo*/
USIx->TX_FIFO_WRITE = TxData;
}
/**
* @brief Get the received data by the USIx peripheral.
* @param USIx: where x can be 0.
* @param pRxByte: the pointer to received data.
* @retval None.
*/
void USI_UARTCharGet(USI_TypeDef* USIx, u8 *pRxByte)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*read one byte from rx fifo*/
*pRxByte = (u8)USIx->RX_FIFO_READ;
}
/**
* @brief Receive data from rx FIFO, poll USI_UARTReadable.
* @param USIx: selected UART peripheral, where x can be 0.
* @param[out] outBuf: buffer to save data read from UART FIFO.
* @param count: number of data to be read.
* @retval none
*/
void USI_UARTReceiveData(
USI_TypeDef* USIx,
u8* OutBuf,
u32 Count
)
{
u32 cnt = 0;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
for(cnt = 0; cnt < Count; cnt++) {
while (USI_UARTReadable(USIx) == 0);
*OutBuf++ = (u8)USIx->RX_FIFO_READ;
}
}
/**
* @brief Send data to tx FIFO, poll USI_UARTWritable.
* @param USIx: selected UART peripheral, where x can be 0.
* @param inBuf: buffer to be written to Tx FIFO.
* @param count: number of data to be written.
* @retval none
*/
void USI_UARTSendData(
USI_TypeDef* USIx,
u8* InBuf,
u32 Count
)
{
u32 cnt = 0;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
for(cnt = 0; cnt < Count; cnt++) {
while (USI_UARTWritable(USIx) == 0);
USIx->TX_FIFO_WRITE = *InBuf++;
}
}
/**
* @brief Receive data from rx FIFO, with timeout.
* @param USIx: selected UART peripheral, where x can be 0.
* @param[out] outBuf: buffer to save data read from UART FIFO.
* @param count: number of data to be read.
* @param Times: poll USI_UARTReadable times before timeout.
* @retval transfer len
*/
u32 USI_UARTReceiveDataTO(
USI_TypeDef* USIx,
u8* OutBuf,
u32 Count,
u32 Times
)
{
u32 cnt = 0;
u32 polltimes = 0;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
while (1) {
if (USI_UARTReadable(USIx)) {
*(OutBuf + cnt) = (u8)USIx->RX_FIFO_READ;
cnt++;
polltimes = 0;
if (cnt >= Count) {
break;
}
} else {
polltimes++;
/* time out */
if (polltimes > Times) {
break;
}
}
}
return (cnt);
}
/**
* @brief Send data to tx FIFO, with timeout.
* @param USIx: selected UART peripheral, where x can be 0.
* @param InBuf: buffer to be written to Tx FIFO.
* @param Count: number of data to be written.
* @param Times: poll USI_UARTWritable times before timeout.
* @retval transfer len
*/
u32 USI_UARTSendDataTO(
USI_TypeDef* USIx,
u8* InBuf,
u32 Count,
u32 Times
)
{
u32 cnt = 0;
u32 polltimes = 0;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
while (1) {
if (USI_UARTWritable(USIx)) {
USIx->TX_FIFO_WRITE = *(InBuf + cnt);
cnt++;
polltimes = 0;
if (cnt >= Count) {
break;
}
} else {
polltimes++;
/* time out */
if (polltimes > Times) {
break;
}
}
}
return (cnt);
}
/**
* @brief Clear Rx Byte Counter.
* @param USIx: where x can be 0.
* @retval None
*/
void USI_UARTRxByteCntClear(USI_TypeDef* USIx)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*write 1 to clear*/
USIx->RX_FIFO_RD_CNT |= USI_RX_FIFO_RD_CNT_CLR;
}
/**
* @brief Get the Rx Byte Counter Value.
* @param USIx: where x can be 0.
* @note Get the Rx Byte Counter Value
* @note this counter will increase 1 for each reading the rx fifo, no matter rx fifo is empty or not.
* @retval the value of Rx Byte Counter
*/
u32 USI_UARTRxByteCntGet(USI_TypeDef* USIx)
{
u32 RegValue;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*Read the REG_RX_BYTE_CNT register value*/
RegValue = USIx->RX_FIFO_RD_CNT;
/*Get the rx byte counter field (REG_RX_BYTE_CNT[15:0]) value*/
RegValue &= USI_RX_FIFO_RD_CNT;
return RegValue;
}
/**
* @brief enable or disable UART break contol function .
* @param USIx: where x can be 0.
* @param NewState: This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USI_UARTBreakCtl(USI_TypeDef* USIx, u32 NewState)
{
u32 RegValue;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*get the Line Control Register(LCR) value*/
RegValue = USIx->UART_CTRL;
if(NewState == ENABLE)
/*enable break control*/
RegValue |= USI_UART_BREAK_CTRL;
else
/*disable break control*/
RegValue &= (~ USI_UART_BREAK_CTRL);
USIx->UART_CTRL = RegValue;
}
/**
* @brief Clear Rx fifo
* @param USIx: where x can be 0.
* @retval None
*/
u32 USI_UARTClearRxFifo(USI_TypeDef* USIx)
{
u32 Temp;
u32 WaitTime = 5;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*write 0 to clear rx fifo*/
USIx->SW_RESET &= (~USI_SW_RESET_RXFIFO_RSTB);
while(WaitTime > 0) {
/*check Rx fifo if empty or not*/
Temp = USIx->RX_FIFO_STATUS & USI_RXFIFO_EMPTY;
if (Temp != 0)
break;
WaitTime--;
}
USIx->SW_RESET |= USI_SW_RESET_RXFIFO_RSTB;
if (Temp != 0)
return _TRUE;
else
return _FALSE;
}
/**
* @brief Clear Tx fifo .
* @param USIx: where x can be 0.
* @retval None
*/
void USI_UARTClearTxFifo(USI_TypeDef* USIx)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*clear tx fifo*/
USIx->SW_RESET &= (~USI_SW_RESET_TXFIFO_RSTB);
USIx->SW_RESET |= USI_SW_RESET_TXFIFO_RSTB;
}
/**
* @brief USI UART get valid entry count in RX FIFO .
* @param USIx: where x can be 0.
* @retval None
*/
u32 USI_UARTGetRxFifoValidCnt(USI_TypeDef* USIx)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*acquire RX FIFO valid count*/
return (u32)((USIx->RX_FIFO_STATUS & USI_RXFIFO_VALID_CNT)>>8);
}
/**
* @brief USI UART get empty entry count in TX FIFO .
* @param USIx: where x can be 0.
* @retval None
*/
u32 USI_UARTGetTxFifoEmptyCnt(USI_TypeDef* USIx)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*acquire TX FIFO empty count*/
return (u32)((USIx->TX_FIFO_STATUS & USI_TXFIFO_EMPTY_SPACE)>>8);
}
/**
* @brief Enables or disables the specified USIx UART interrupts.
* @param USIx: where x can be 0.
* @param USI_UARTIT: specifies the USIx interrupt sources to be enabled or disabled.
* This parameter can be one or combinations of the following values:
* @arg USI_TX_FIFO_ALMOST_EMPTY_INTER: tx fifo almost empty interrupt
* @arg USI_TX_FIFO_OVERFLOW_INTER: tx fifo overflow interrupt
* @arg USI_RX_FIFO_ALMOST_FULL_INTER: rx fifo almost full interrupt
* @arg USI_RX_FIFO_OVERFLOW_INTER: rx fifo overflow interrupt
* @arg USI_RX_FIFO_UNDERFLOW_INTER: rx fifo underflow interrupt
* @arg USI_UART_PARITY_ERROR_INTER: uart parity error interrupt
* @arg USI_UART_STOP_ERROR_INTER: uart stop bit error interrupt
* @arg USI_UART_BREAK_INTER: uart break interrupt
* @arg USI_RX_FIFO_TIMEOUT_INTER: rx fifo timeout interrupt
* @arg USI_RX_BAUDMON_DONE_INTER: uart baud rate monitor done interrupt
* @arg USI_TX_CTS_CHANGE_INTER: uart CTS change interrupt
* @param newState: new state of the specified USIx interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USI_UARTINTConfig(
USI_TypeDef* USIx,
u32 USI_UARTIT,
u32 newState
)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
assert_param(IS_USI_UART_IT(USI_UARTIT));
if (newState == ENABLE) {
/* Enable the selected USIx interrupts */
USIx->INTERRUPT_ENABLE |= USI_UARTIT;
} else {
/* Disable the selected USIx interrupts */
USIx->INTERRUPT_ENABLE &= (u32)~USI_UARTIT;
}
}
/**
* @brief get the interrupt identification register value.
* @param USIx: where x can be 0.
* @retval the interrupt identification register value.
*/
u32 USI_UARTIntStatus(USI_TypeDef* USIx)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*return the uart interrupt identification register value*/
return USIx->INTERRUPT_STATUS;
}
/**
* @brief get the raw interrupt register value.
* @param USIx: where x can be 0.
* @retval the interrupt raw status value.
*/
u32 USI_UARTGetRawIntStatus(USI_TypeDef* USIx)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*return the uart interrupt raw status register value*/
return USIx->RAW_INTERRUPT_STATUS;
}
/**
* @brief Clear all USI UART interrupt status.
* @param USIx: where x can be 0.
* @note Write "1" to this register to clear the combined interrupt, all individual interrupts,
* interrupt status register and raw interrupt status register. This bit does not clear
* hardware clearable interrupts but software dis-clearable interrupts, and the relate register
* (include txfifo_almost_empty, rxfifo_almost_full, uart_rxfifo_timeout).
* @retval None
*/
void USI_UARTClearAllIntStatus(USI_TypeDef* USIx)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/*write 1 to clear all interrupts*/
USIx->INTERRUPT_ALL_CLR = USI_INT_ALL_CLEAR;
}
/**
* @brief Clear specified USI UART interrupt pending bits.
* @param USIx: where x can be 0.
* @param USIUART_IT: specifies the interrupt to be cleared.
* This parameter can be any combination of the following values:
* @arg USI_TX_FIFO_OVERFLOW_INTER: tx fifo overflow interrupt
* @arg USI_RX_FIFO_OVERFLOW_INTER: rx fifo overflow interrupt
* @arg USI_RX_FIFO_UNDERFLOW_INTER: rx fifo underflow interrupt
* @arg USI_UART_PARITY_ERROR_INTER: uart parity error interrupt
* @arg USI_UART_STOP_ERROR_INTER: uart stop bit error interrupt
* @arg USI_UART_BREAK_INTER: uart break interrupt
* @arg USI_RX_BAUDMON_DONE_INTER: uart baud rate monitor done interrupt
* @arg USI_TX_CTS_CHANGE_INTER: uart CTS change interrupt
* @retval None
*/
void USI_UARTClearIntStatus(USI_TypeDef* USIx, u32 USIUART_IT)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
assert_param(IS_USI_UART_CLEAR_IT(USIUART_IT));
/*write 1 to clear all interrupts*/
USIx->INTERRUPT_STATUS_CLR = USIUART_IT;
}
/**
* @brief wait uart tx complete.
* @param USIx: where x can be 0.
* @retval: none
*/
void USI_UARTWaitBusy(USI_TypeDef* USIx, u32 PollTimes)
{
u32 times = 0;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/* Wait for Uart print out */
while(1) {
if (USIx->TX_FIFO_STATUS & USI_TXFIFO_EMPTY){
break;
}
DelayUs(100);
times++;
if (times > PollTimes)
break;
}
}
/**
* @brief USI-UART RX timeout configuration .
* @param USIx: where x can be 0.
* @param TimeOutCnt: timeout counter, unit: bit period.
* @retval None
*/
void USI_UARTRxTimeOutConfig(USI_TypeDef* USIx, u32 TimeOutCnt)
{
u32 TempReg;
/* Set rx timeout threshold.*/
TempReg = USIx->UART_RXFIFO_TO_TH;
TempReg &= ~(USI_UART_RXFIFO_TO_TH);
TempReg |= TimeOutCnt;
USIx->UART_RXFIFO_TO_TH = TempReg;
}
/**
* @brief USI UART RX DMA flow control mode configuration .
* @param USIx: where x can be 0
* @param Mode: DMA flow control mode.
This parameter can be: USI_UART_RX_UART_IS_DMA_FLOW_CTRL or USI_UART_RX_GDMA_IS_DMA_FLOW_CTRL.
* @retval None
*/
void USI_UARTRxDMAModeConfig(USI_TypeDef* USIx, u32 Mode)
{
u32 TempReg;
assert_param(IS_USI_UART_RX_DMA_MODE(Mode));
/* Set USI UART RX DMA flow control mode.*/
TempReg = USIx->UART_RXDMA_FLOW_CTRL;
TempReg &= ~(USI_UART_RXDMA_RXDMA_OWNER);
TempReg |= Mode;
USIx->UART_RXDMA_FLOW_CTRL = TempReg;
}
/**
* @brief USI UART RX DMA dummy data configuration .
* @param USIx: where x can be 0~1.
* @param Byte: dummy data.
* @retval None
*/
void USI_UARTRxDMADummyDataConfig(USI_TypeDef* USIx, u8 Byte)
{
u32 TempReg;
/* Set UART RX DMA flow control mode.*/
TempReg = USIx->UART_RXDMA_FLOW_CTRL;
TempReg &= ~(USI_UART_RXDMA_DUMMY_DATA);
TempReg |= (Byte<<8);
USIx->UART_RXDMA_FLOW_CTRL = TempReg;
}
/**
* @brief Get USI UART RX DMA dummy flag .
* @param USIx: where x can be 0.
* @retval status value:
- 0: master not read dummy data from rx fifo
- 1: master read dummy data from rx fifo
*/
u32 USI_UARTGetRxDMADummyFlag(USI_TypeDef* USIx)
{
if(USIx->UART_RXDMA_FLOW_CTRL & USI_UART_RXDMA_DUMMY_FLAG) {
return 1;
} else {
return 0;
}
}
/**
* @brief Clear USI UART RX DMA dummy flag .
* @param USIx: where x can be 0.
* @retval None
*/
void USI_UARTRxClearDMADummyFlag(USI_TypeDef* USIx)
{
USIx->UART_RXDMA_FLOW_CTRL |= USI_UART_RXDMA_DUMMY_FLAG;
}
/**
* @brief configure USI UART TX DMA burst size .
* @param USIx: where x can be 0.
* @param TxDmaBurstSize: UART TX DMA burst size.
* @note Because UART tx fifo depth is 64 in hardware.
* Therefore this value must be no more than 64.
* @retval None
*/
void USI_UARTTXDMAConfig(USI_TypeDef* USIx, u32 TxDmaBurstSize)
{
u32 Temp;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/* Set UART TX DMA burst size.*/
Temp = USIx->DMA_REQ_SIZE;
Temp &= ~(USI_TX_DMA_BURST_SIZE|USI_TX_DMA_SINGLE_SIZE);
Temp |= (TxDmaBurstSize|(1<<8));
USIx->DMA_REQ_SIZE = Temp;
}
/**
* @brief configure UART RX DMA burst size .
* @param USIx: where x can be 0.
* @param RxDmaBurstSize: UART RX DMA burst size.
* @note Because UART rx fifo depth is 64 in hardare.
* Therefore this value must be no more than 64.
* @retval None
*/
void USI_UARTRXDMAConfig(USI_TypeDef* USIx, u32 RxDmaBurstSize)
{
u32 Temp;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
/* Set UART RX DMA burst size.*/
Temp = USIx->DMA_REQ_SIZE;
Temp &= ~(USI_RX_DMA_BURST_SIZE|USI_RX_DMA_BURST_SIZE);
Temp |= ((RxDmaBurstSize<<16)|(1<<24));
USIx->DMA_REQ_SIZE = Temp;
}
/**
* @brief enable or disable USI UART TX DMA .
* @param USIx: where x can be 0.
* @param NewState: the new state of UART TX DMA.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USI_UARTTXDMACmd(USI_TypeDef* USIx, u32 NewState)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
if(NewState != DISABLE ){
/* enable the UART TX DMA */
USIx->DMA_ENABLE |= USI_TX_DMA_ENABLE;
} else {
/* disable the UART TX DMA */
USIx->DMA_ENABLE &= (~ USI_TX_DMA_ENABLE);
}
}
/**
* @brief enable or disable USI UART RX DMA .
* @param USIx: where x can be 0.
* @param NewState: the new state of UART RX DMA.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USI_UARTRXDMACmd(USI_TypeDef* USIx, u32 NewState)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
if(NewState != DISABLE ){
/* enable the UART RX DMA */
USIx->DMA_ENABLE |= USI_RX_DMA_ENABLE;
} else {
/* disable the UART RX DMA */
USIx->DMA_ENABLE &= (~ USI_RX_DMA_ENABLE);
}
}
/**
* @brief Init and Enable USI UART TX GDMA.
* @param USIIndex: 0.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pTxBuf: Tx Buffer.
* @param TxCount: Tx Count.
* @retval TRUE/FLASE
*/
BOOL USI_UARTTXGDMA_Init(
u8 USIIndex,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pTxBuf,
int TxCount
)
{
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);//ACUT is 0x10, BCUT is 12
if (GdmaChnl == 0xFF) {
/* No Available DMA channel */
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_InitStruct->GDMA_DIR = TTFCMemToPeri;
GDMA_InitStruct->GDMA_DstHandshakeInterface = USI_DEV_TABLE[USIIndex].Tx_HandshakeInterface;
GDMA_InitStruct->GDMA_DstAddr = (u32)&USI_DEV_TABLE[USIIndex].USIx->TX_FIFO_WRITE;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_DstInc = NoChange;
GDMA_InitStruct->GDMA_SrcInc = IncType;
if (((TxCount & 0x03)==0) && (((u32)(pTxBuf) & 0x03)==0)) {
/* 4-bytes aligned, move 4 bytes each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeOne;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes;
GDMA_InitStruct->GDMA_BlockSize = TxCount >> 2;
} else {
/* move 1 byte each transfer */
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_BlockSize = TxCount;
}
assert_param(GDMA_InitStruct->GDMA_BlockSize < 4096);
GDMA_InitStruct->GDMA_SrcAddr = (u32)(pTxBuf);
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Init and Enable UART RX GDMA.
* @param USIIndex: 0.
* @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
* the configuration information for the GDMA peripheral.
* @param CallbackData: GDMA callback data.
* @param CallbackFunc: GDMA callback function.
* @param pRxBuf: Rx Buffer.
* @param RxCount: Rx Count.
* @retval TRUE/FLASE
*/
BOOL USI_UARTRXGDMA_Init(
u8 USIIndex,
GDMA_InitTypeDef *GDMA_InitStruct,
void *CallbackData,
IRQ_FUN CallbackFunc,
u8 *pRxBuf,
int RxCount
)
{
u8 GdmaChnl;
assert_param(GDMA_InitStruct != NULL);
GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);//ACUT is 0x10, BCUT is 12
if (GdmaChnl == 0xFF) {
/* No Available DMA channel */
return _FALSE;
}
_memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem;
GDMA_InitStruct->GDMA_ReloadSrc = 1;
GDMA_InitStruct->GDMA_SrcHandshakeInterface = USI_DEV_TABLE[USIIndex].Rx_HandshakeInterface;
GDMA_InitStruct->GDMA_SrcAddr = (u32)&USI_DEV_TABLE[USIIndex].USIx->RX_FIFO_READ;
GDMA_InitStruct->GDMA_Index = 0;
GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
GDMA_InitStruct->GDMA_SrcMsize = MsizeFour;
GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte;
GDMA_InitStruct->GDMA_DstInc = IncType;
GDMA_InitStruct->GDMA_SrcInc = NoChange;
if (((u32)(pRxBuf) & 0x03)==0) {
/* 4-bytes aligned, move 4 bytes each DMA transaction */
GDMA_InitStruct->GDMA_DstMsize = MsizeOne;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes;
} else {
/* move 1 byte each DMA transaction */
GDMA_InitStruct->GDMA_DstMsize = MsizeFour;
GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte;
}
GDMA_InitStruct->GDMA_BlockSize = RxCount;
GDMA_InitStruct->GDMA_DstAddr = (u32)(pRxBuf);
assert_param(GDMA_InitStruct->GDMA_BlockSize < 4096);
/* multi block close */
GDMA_InitStruct->MuliBlockCunt = 0;
GDMA_InitStruct->GDMA_ReloadSrc = 0;
GDMA_InitStruct->MaxMuliBlock = 1;
GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
return _TRUE;
}
/**
* @brief Fills USI_LPUARTInitStruct member low power rx path related with its default value.
* @param USI_LPUARTInitStruct: pointer to an USI_LPUARTInitTypeDef structure which will be initialized.
* @retval None
*/
void USI_UARTLPRxStructInit(USI_LPUARTInitTypeDef* USI_LPUARTInitStruct)
{
/* USI_LPUARTInitStruct members default value */
USI_LPUARTInitStruct->USI_LPUARTBitNumThres = 100;
USI_LPUARTInitStruct->USI_LPUARTOscPerbitUpdCtrl = ENABLE;
}
/**
* @brief Initializes the the UART Low Power RX path peripheral according to the specified
* parameters in the USI_LPUARTInitStruct.
* @param USIx: where x can be 0.
* @param USI_LPUARTInitStruct: pointer to an USI_LPUARTInitTypeDef structure which has been configured.
* @note Initial UART Low Power Rx path steps:
* - step1: Reset Low Power Rx Path.
* - step2: Configure bit number threshold of one monitor period.
* - step3: Configure the update OSC cycnum_perbit bit.
* @retval None
*/
void USI_UARTLPRxInit(USI_TypeDef* USIx, USI_LPUARTInitTypeDef *USI_LPUARTInitStruct)
{
u32 RegValue = 0;
/*check the parameters*/
assert_param(IS_ALL_USI_LP_PERIPH(USIx));
assert_param((USI_LPUARTInitStruct->USI_LPUARTBitNumThres>0) && (USI_LPUARTInitStruct->USI_LPUARTBitNumThres<128));
/* Step 1: Reset Low Power Rx Path */
USIx->SW_RESET &= (~USI_SW_RESET_RX_RSTB);
RegValue = USIx->UART_BAUD_MON_CTRL;
/*step 2: Configure bit number threshold of one monitor period.*/
RegValue &= (~ USI_UART_LP_RX_BIT_NUM_THRES);
RegValue |= (USI_LPUARTInitStruct->USI_LPUARTBitNumThres << 8);
/*step 3: Configure the OSC cycnum_perbit update bit*/
if(USI_LPUARTInitStruct->USI_LPUARTOscPerbitUpdCtrl != DISABLE){
/*enable OSC cycnum_perbit update*/
RegValue |= USI_UART_LP_RX_OSC_UPD_IN_XTAL;
} else {
/*disable OSC cycnum_perbit update*/
RegValue &= ~ USI_UART_LP_RX_OSC_UPD_IN_XTAL;
}
USIx->UART_BAUD_MON_CTRL = RegValue;
}
/**
* @brief set uart baud rate of low power rx path
* @param USIx: where x can be 0.
* @param BaudRate: the desired baud rate
* @param RxIPClockHz: the uart rx clock. unit: [Hz]
* @note according to the baud rate calculation formlula in low power rx path, method
* implemented is as follows:
* - CycPerbit = round( fpclock/BaudRate)
* @retval None
*/
void USI_UARTLPRxBaudSet(USI_TypeDef* USIx, u32 BaudRate, u32 RxIPClockHz)
{
u32 CycPerbit = 0;
u32 RegValue = 0;
u32 RegOscBaud = 0;
/*check the parameters*/
assert_param(IS_ALL_USI_LP_PERIPH(USIx));
assert_param((BaudRate > 0 && BaudRate <= 500000));
/*Calculate the r_cycnum_perbit field,
according to clock and the desired baud rate*/
if((RxIPClockHz % BaudRate) >= (BaudRate + 1) / 2){
CycPerbit = RxIPClockHz / BaudRate + 1;
} else {
CycPerbit = RxIPClockHz / BaudRate;
}
/* Average clock cycle number of XTAL clock. */
RegValue = USIx->UART_RX_BAUD_XTAL;
RegValue &= (~ USI_RUART_LPRX_XTAL_CYCNUM_PERBIT);
RegValue |= CycPerbit;
/* set XTAL CycPerbit */
USIx->UART_RX_BAUD_OSC= RegValue;
/* Average clock cycle number of one bit OSC. */
RegOscBaud = USIx->UART_RX_BAUD_OSC;
RegOscBaud &= (~ USI_UART_LPRX_OSC_CYCNUM_PERBIT);
RegOscBaud |= CycPerbit;
/*set the OSC CycPerbit*/
USIx->UART_RX_BAUD_OSC = RegOscBaud;
/*set uart_rxbaud_adj = 0*/
USIx->UART_RX_FRACTION_BAUD_CTRL &= (~USI_UART_RX_XFACTOR_ADJ);
}
/**
* @brief enable or disable the monitor function in Low Power Rx Path.
* @param USIx: where x can be 0.
* @param NewState: the new state of monitoring.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USI_UARTLPRxMonitorCmd(USI_TypeDef* USIx, u32 NewState)
{
/*check the parameters*/
assert_param(IS_ALL_USI_LP_PERIPH(USIx));
/* configure Low Power rx monitoring function*/
if(NewState != DISABLE ){
/* Function enable of monitoring rx baud */
USIx->UART_BAUD_MON_CTRL |= USI_UART_LP_RX_MON_ENABLE;
} else {
/* Function disable of monitoring rx baud */
USIx->UART_BAUD_MON_CTRL &= (~ USI_UART_LP_RX_MON_ENABLE);
}
}
/**
* @brief select uart rx path.
* @param USIx: where x can be 0.
* @param LPRxpath: the new state of uart rx path.
* This parameter can be: ENABLE or DISABLE.
* DISABLE is high rate rx path, ENABLE is low power rx path
* @retval None
*/
void USI_UARTLPRxpathSet(USI_TypeDef* USIx, u32 LPRxpath)
{
/* To avoid gcc warnings */
( void ) USIx;
( void ) LPRxpath;
/*AmebaZ's API, AmebaD doesn't use this API any more; this API is reserved for compatibility with AmebaZ*/
}
/**
* @brief Configure USI UART RX Clock.
* @param USIx: where x can be 0.
* @param RxClock: This parameter can be one of the following values:
* @retval None
* @note USI V01(Ameba-D) not support this function.
*/
void USI_UARTLPRxIPClockSet(USI_TypeDef* USIx, u32 RxIPClock)
{
/* To avoid gcc warnings */
( void ) RxIPClock;
/* Check the parameters */
assert_param(IS_ALL_USI_PERIPH(USIx));
//assert_param(IS_USI_UART_RX_CLK(RxIPClock));
/* not support */
}
/**
* @brief enable or disable Uart Low Power Rx Path
* @param USIx: where x can be 0.
* @param NewState: the new state of the Rx Path.
* This parameter can be: ENABLE or DISABLE.
* @note Because the TX/RX of the IrDA transceiver are in the same module,
* RX fifo can also receive available data when in the process of TX.Therefore,
* the RX Path must be disabled when TX is going on.Namely, IrDA must work
* in the Half duplex mode, though normal UART IP supports Full duplex.
* @retval None
*/
void USI_UARTLPRxCmd(USI_TypeDef* USIx, u32 NewState)
{
/*check the parameters*/
assert_param(IS_ALL_USI_LP_PERIPH(USIx));
if (NewState != DISABLE) {
/*enable uart receiver*/
USIx->SW_RESET |= USI_SW_RESET_RX_RSTB;
} else {
/*disable uart receiver*/
USIx->SW_RESET &= (~USI_SW_RESET_RX_RSTB);
}
}
/**
* @brief Fills each IrDA_InitStruct member with its default value.
* @param IrDA_InitStruct : pointer to a USI_UartIrDAInitTypeDef
* structure which will be initialized.
* @retval None
*/
void USI_UARTIrDAStructInit(USI_UartIrDAInitTypeDef * IrDA_InitStruct)
{
/* Set the default value */
IrDA_InitStruct->USI_UARTIrDARxInv = DISABLE;
IrDA_InitStruct->USI_UARTIrDATxInv = DISABLE;
IrDA_InitStruct->USI_UARTLowShift = USI_UART_IRDA_PULSE_LEFT_SHIFT;
IrDA_InitStruct->USI_UARTLowShiftVal = 0;
IrDA_InitStruct->USI_UARTUpperShift = USI_UART_IRDA_PULSE_LEFT_SHIFT;
IrDA_InitStruct->USI_UARTUpperShiftVal = 0;
IrDA_InitStruct->USI_UARTRxFilterCmd = ENABLE;
IrDA_InitStruct->USI_UARTRxFilterThres = 7;
}
/**
* @brief Configures the USI UART's IrDA interface .
* @param USIx: where x can be 0.
* @param IrDA_InitStruct: pointer to a USI_UartIrDAInitTypeDef structure that contains
* the configuration information for the IrDA module.
* @note the details of IrDA_InitStruct members are:
* @verbatim
* IrDA_InitStruct-> USI_UARTIrDARxInv:
* IrDA Rx invert bit:
* ENABLE: invert irda rx
* DISABLE: not invert irda rx
*
* IrDA_InitStruct->USI_UARTIrDATxInv:
* IrDA Tx invert bit:
* ENABLE: invert irda tx
* DISABLE: not invert irda tx
*
* IrDA_InitStruct->USI_UARTUpperShift:
* Upperbound(right edge) Shift direction:
* UART_IRDA_PULSE_LEFT_SHIFT: shift left
* UART_IRDA_PULSE_RIGHT_SHIFT: shift right
* IrDA_InitStruct->UpperShiftVal:
* Upperbound Shift value
*
* IrDA_InitStruct->USI_UARTLowShift:
* Lowbound(left edge) Shift direction:
* UART_IRDA_PULSE_LEFT_SHIFT: shift left
* UART_IRDA_PULSE_RIGHT_SHIFT: shift right
* IrDA_InitStruct->USI_UARTLowShiftVal:
* Lowbound Shift value
*
* IrDA_InitStruct->USI_UARTRxFilterThres:
* IrDA RX filter threshold
*
* IrDA_InitStruct->USI_UARTRxFilterCmd:
* IrDA RX filter enable or disable:
* ENABLE: enable IrDA rx filter
* DISABLE: disable IrDA rx filter
* @endverbatim
* @retval None
*/
void USI_UARTIrDAInit(USI_TypeDef* USIx, USI_UartIrDAInitTypeDef * IrDA_InitStruct)
{
u32 TempCtrl;
u32 TempTxpulse;
u32 TempRxPulse;
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
assert_param(IrDA_InitStruct->USI_UARTUpperShiftVal <= 0x7fff );
assert_param(IrDA_InitStruct->USI_UARTLowShiftVal <= 0x7fff);
assert_param(IS_USI_IRDA_PUL_SHIFT(IrDA_InitStruct->USI_UARTLowShift));
assert_param(IS_USI_IRDA_PUL_SHIFT(IrDA_InitStruct->USI_UARTUpperShift));
assert_param((IrDA_InitStruct->USI_UARTRxFilterThres <= 0x7fff));
/*Get the UART_IRDA_CTRL register value*/
TempCtrl = USIx->UART_IRDA_CTRL;
/*configure the IrDA RX invert bit*/
if(IrDA_InitStruct->USI_UARTIrDARxInv != DISABLE){
/*invert the irda_rx_i*/
TempCtrl |= USI_UART_IRDA_RX_INV;
} else {
/*not invert the irda_rx_i*/
TempCtrl &= (~ USI_UART_IRDA_RX_INV);
}
/*configure the IrDA TX invert bit*/
if(IrDA_InitStruct->USI_UARTIrDATxInv != DISABLE){
/*invert the irda_tx_o*/
TempCtrl |= USI_UART_IRDA_TX_INV;
} else {
/*not invert the irda_tx_o*/
TempCtrl &= (~ USI_UART_IRDA_TX_INV);
}
USIx->UART_IRDA_CTRL = TempCtrl;
/*Get the UART_IRDA_TX_PULSE_WD register value*/
TempTxpulse = USIx->UART_IRDA_TX_PULSE_WD;
/*configure IrDA SIR TX Pulse Width*/
/*configure Upperbound(right edge) shift direction*/
TempTxpulse &= (~ USI_UART_IRDA_TX_PUL_UP_BUND_SHIFT);
TempTxpulse |= (IrDA_InitStruct->USI_UARTUpperShift << 31);
/*configure the Upperbound shift value*/
TempTxpulse &= (~ USI_UART_IRDA_TX_PUL_UP_BUND_VAL);
TempTxpulse |= (IrDA_InitStruct->USI_UARTUpperShiftVal << 16);
/*configure Lowbound(left edge) shift direction*/
TempTxpulse &= (~ USI_UART_IRDA_TX_PUL_LOW_BUND_SHIFT);
TempTxpulse |= (IrDA_InitStruct->USI_UARTLowShift << 15);
/*configure the Lowbound shift value*/
TempTxpulse &= (~ USI_UART_IRDA_TX_PUL_LOW_BUND_VAL);
TempTxpulse |= (IrDA_InitStruct->USI_UARTLowShiftVal);
USIx->UART_IRDA_TX_PULSE_WD = TempTxpulse;
/*Get the RXPLSR register value*/
TempRxPulse = USIx->UART_IRDA_RX_PULSE_WD;
/*configure IrDA RX filter threshold*/
TempRxPulse &= (~ USI_UART_IRDA_RX_FILTER_THRES);
TempRxPulse |= (IrDA_InitStruct->USI_UARTRxFilterThres << 1);
if(IrDA_InitStruct->USI_UARTRxFilterCmd != DISABLE){
/*enable IrDA rx filter*/
TempRxPulse |= USI_UART_IRDA_RX_FILTER_ENABLE;
} else {
/*disable IrDA rx filter*/
TempRxPulse &= (~ USI_UART_IRDA_RX_FILTER_ENABLE);
}
USIx->UART_IRDA_RX_PULSE_WD = TempRxPulse;
}
/**
* @brief enable or disable the IrDA function.
* @param USIx: where x can be 0.
* @param NewState: the new state of the IrDA.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void USI_UARTIrDACmd(USI_TypeDef* USIx, u32 NewState)
{
/*check the parameters*/
assert_param(IS_ALL_USI_PERIPH(USIx));
if(NewState != DISABLE ){
/* enable the IrDA */
USIx->UART_IRDA_CTRL|= USI_UART_IRDA_ENABLE;
} else {
/* disable the IrDA */
USIx->UART_IRDA_CTRL &= (~ USI_UART_IRDA_ENABLE);
}
}
/******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/rtl8721dhp_usi_uart.c
|
C
|
apache-2.0
| 44,089
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "ameba_soc.h"
#include "rtl8721d_system.h"
#if defined ( __ICCARM__ )
#pragma section=".ram_image2.bss"
u8* __bss_start__;
u8* __bss_end__;
#endif
static u32 Cutversion;
extern int main(void);
void app_section_init(void)
{
#if defined ( __ICCARM__ )
__bss_start__ = (u8*)__section_begin(".ram_image2.bss");
__bss_end__ = (u8*)__section_end(".ram_image2.bss");
#endif
}
/* The binary data of generated ram_retention.bin should copy into retention_ram_patch_array.
Then fill in the patch size at the second dword */
const u32 retention_ram_patch_array[2][RETENTION_RAM_SYS_OFFSET/4] = {
{
0x000c0009,
0x00000080,
0x2210f240,
0x0200f6c4,
0x49106813,
0xf240400b,
0x430b2100,
0x22906013,
0x05d22380,
0x045b6811,
0xd1124219,
0x6013430b,
0x3300f240,
0x0300f6c4,
0x4907681a,
0x601a400a,
0x3318f240,
0xf6c42101,
0x681a0300,
0x601a430a,
0x4770bf30,
0xfffff9ff,
0xdfffffff,
},
{
0x000c0009,
0x00000080,
0x2210f240,
0x0200f6c4,
0x49036813,
0xf240400b,
0x430b2100,
0x47706013,
0xfffff9ff,
}
};
void app_load_patch_to_retention(void)
{
u32 Temp = 0;
if(Cutversion<=0x1){
_memcpy(__retention_entry_func__, retention_ram_patch_array[0], RETENTION_RAM_SYS_OFFSET);
}else {
_memcpy(__retention_entry_func__, retention_ram_patch_array[1], RETENTION_RAM_SYS_OFFSET);
}
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_BOOT_REASON1);
Temp |= BIT_DSLP_RETENTION_RAM_PATCH;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_BOOT_REASON1, Temp);
}
RETENTION_TEXT_SECTION
void app_retention_ram_patch(void)
{
u32 Temp = 0;
/* SPIC clock source switch */
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL0);
Temp &= ~ (BIT_MASK_FLASH_CLK_SEL << BIT_SHIFT_FLASH_CLK_SEL);
Temp |= BIT_SHIFT_FLASH_CLK_XTAL;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_CLK_CTRL0, Temp);
if( Cutversion<=0x1){
/* dslp again to fix pad shutdown flashdownload issue */
Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_PWR_CTRL);
if ((Temp & BIT_DSLP_SNOOZE_MODE_LSPAD_SHUTDOWN) == 0) {
Temp |= BIT_DSLP_SNOOZE_MODE_LSPAD_SHUTDOWN;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_PWR_CTRL, Temp);
/* Set Event */
Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LP_SLP_WAKE_EVENT_MSK0);
Temp &= ~BIT_LP_WEVT_AON_MSK;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LP_SLP_WAKE_EVENT_MSK0, Temp);
Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LP_PWRMGT_CTRL);
Temp |= BIT_LSYS_PMC_PMEN_DSLP;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LP_PWRMGT_CTRL, Temp);
__WFI();
}
}
}
RETENTION_ENTRY_SECTION
DSLP_RETENTION_FUNC_TABLE app_dslp_patch_table = {
.DSLPPatchFun0 = app_retention_ram_patch,
.PatchLen = 0,
};
//set all KM0 memory no-cachable, just flash cachable
//0x0000_0000 0x0001_FFFF 128K KM0 ITCM ROM (actually 96K)
//0x0002_0000 0x0002_7FFF 32K KM0 DTCM ROM (actually 16K)
//0x0002_8000 0x0007_FFFF 352K RSVD
//0x0008_0000 0x0008_FFFF 64K KM0 SRAM
//0x0008_8000 0x000B_FFFF 224K RSVD
//0x000C_0000 0x000C_3FFF 16K Retention SRAM (1KB) (The same port with KM0 SRAM)
u32 app_mpu_nocache_init(void)
{
mpu_region_config mpu_cfg;
u32 mpu_entry = 0;
#if 0
mpu_entry = mpu_entry_alloc();
mpu_cfg.region_base = 0x00080000;//__ram_nocache_start__;
mpu_cfg.region_size = 0x0008F000 - 0x00080000;//__ram_nocache_end__-__ram_nocache_start__;
mpu_cfg.xn = MPU_EXEC_ALLOW;
mpu_cfg.ap = MPU_UN_PRIV_RW;
mpu_cfg.sh = MPU_NON_SHAREABLE;
mpu_cfg.attr_idx = MPU_MEM_ATTR_IDX_NC;
//DBG_8195A("app_mpu_nocache_init entry: %x[%x:%x]\n", mpu_entry,
// mpu_cfg.region_base, mpu_cfg.region_size);
if (mpu_cfg.region_size >= 32) {
mpu_region_cfg(mpu_entry, &mpu_cfg);
}
/* close 96K irom cache */
mpu_entry = mpu_entry_alloc();
mpu_cfg.region_base = 0x00000000;
mpu_cfg.region_size = 0x18000;
mpu_cfg.xn = MPU_EXEC_ALLOW;
mpu_cfg.ap = MPU_UN_PRIV_RW;
mpu_cfg.sh = MPU_NON_SHAREABLE;
mpu_cfg.attr_idx = MPU_MEM_ATTR_IDX_NC;
mpu_region_cfg(mpu_entry, &mpu_cfg);
/* close 16K drom cache */
mpu_entry = mpu_entry_alloc();
mpu_cfg.region_base = 0x00020000;
mpu_cfg.region_size = 0x4000;
mpu_cfg.xn = MPU_EXEC_ALLOW;
mpu_cfg.ap = MPU_UN_PRIV_RW;
mpu_cfg.sh = MPU_NON_SHAREABLE;
mpu_cfg.attr_idx = MPU_MEM_ATTR_IDX_NC;
mpu_region_cfg(mpu_entry, &mpu_cfg);
#else
mpu_entry = mpu_entry_alloc();
mpu_cfg.region_base = 0x00000000;
mpu_cfg.region_size = 0x000C4000;
mpu_cfg.xn = MPU_EXEC_ALLOW;
mpu_cfg.ap = MPU_UN_PRIV_RW;
mpu_cfg.sh = MPU_NON_SHAREABLE;
mpu_cfg.attr_idx = MPU_MEM_ATTR_IDX_NC;
mpu_region_cfg(mpu_entry, &mpu_cfg);
#endif
return 0;
}
VOID app_start_autoicg(VOID)
{
u32 temp = 0;
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_KM0_CTRL);
temp |= BIT_LSYS_PLFM_AUTO_ICG_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_KM0_CTRL, temp);
}
VOID app_pmc_patch(VOID)
{
/* flash pin floating issue */
//0x4800_00B0[31:0] = 0x0080_1A12
//0x4800_00B8[31:0] = 0x0A00_301A
//0x4800_00BC[31:0] = 0x0801_3802
//0x4800_00C0[31:0] = 0x00C0_0123
Cutversion = SYSCFG_CUTVersion();
//DBG_8195A("cut version:%d\n", Cutversion);
if(Cutversion<=0x1){
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, 0xB0, 0x00801A12);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, 0xB8, 0x0A00301A);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, 0xBC, 0x08013802);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, 0xC0, 0x00C00123);
}
/*PMC gateclock delay 8us patch*/
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYSON_PMC_PATCH_GRP1_L, 0x0080B482);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYSON_PMC_PATCH_GRP2_L, 0x3CC00FB4);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYSON_PMC_PATCH_GRP2_H, 0x080BC300);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYSON_PMC_PATCH_GRP3_L, 0x0E05DDBC);
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYSON_PMC_PATCH_GRP3_H, 0x00000202);
/* SPIC clock source switch patch */
app_load_patch_to_retention();
}
VOID app_vdd1833_detect(VOID)
{
u32 temp = 0;
u32 vdd33_detected = 0;
u32 data = 0;
u8 swr_vol = 0;
ADC_InitTypeDef ADC_InitStruct;
u16 buf[16], i =0;
/* check vddcore is 1.8V or 3.3V, default is 1.8V */
RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE);
ADC_StructInit(&ADC_InitStruct);
ADC_InitStruct.ADC_OpMode = ADC_AUTO_MODE;
ADC_InitStruct.ADC_CvlistLen = 0;
ADC_InitStruct.ADC_Cvlist[0]= ADC_CH10;
ADC_Init(&ADC_InitStruct);
ADC_Cmd(ENABLE);
ADC_ReceiveBuf(buf, 16);
ADC_Cmd(DISABLE);
while(i < 16)
data += buf[i++];
data = data >> 4;
if(data > 3000) {
vdd33_detected = 1;
DBG_8195A("VDDIO 3.3V\n");
} else {
vdd33_detected = 0;
DBG_8195A("VDDIO 1.8V\n");
}
if (vdd33_detected) {
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0);
temp |= BIT_AON_V1833_SEL;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0, temp);
/*This value is given by MAC team yx_qi*/
swr_vol = 0x0A;
} else {
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0);
temp &= ~BIT_AON_V1833_SEL;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_LDO_CTRL0, temp);
/*This value is given by MAC team yx_qi*/
swr_vol =0x08;
}
/* To reduce the differ between 1.8v and 3.3v's SWR output value*/
temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_SYS_EFUSE_SYSCFG1);
temp &= ~BIT_MASK_SWR_VOL_L1;
temp |= swr_vol;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYS_EFUSE_SYSCFG1,temp);
}
void app_dslp_wake_check(void)
{
DBG_8195A("BOOT_Reason:%x %x\n", BOOT_Reason(), BIT_BOOT_DSLP_RESET_HAPPEN);
/* set deep sleep wakeup status, you can use SOCPS_DsleepWakeStatusGet */
/* to get this status after this point, some function like: */
/* RTC/TOUCH/WIFI DLPS/Key-Scan and so on need this status */
if(BIT_BOOT_DSLP_RESET_HAPPEN & BOOT_Reason()) {
SOCPS_DsleepWakeStatusSet(TRUE);
} else {
SOCPS_DsleepWakeStatusSet(FALSE);
}
}
static void app_gen_random_seed(void)
{
u32 data;
int i = 0, j = 0;
u8 random[4], tmp;
CAPTOUCH_TypeDef *CapTouch = (CAPTOUCH_TypeDef*) CTC_REG_BASE;
PAD_PullCtrl((_PB_4), GPIO_PuPd_NOPULL);
/* Set CTC to debug mode */
CapTouch_Cmd(CAPTOUCH_DEV, DISABLE);
CapTouch->CT_IER = 0;
CapTouch->CT_ICR_ALL = 1;
CapTouch->CT_MODE_CTRL = 0;
CapTouch->CT_SP_CTRL = 0x00070000;
CapTouch->CT_ETC_CTRL = 0;
CapTouch->CT_CH[0].CTRL = 0;
CapTouch->CT_CH[0].MBIAS = 0x6;
CapTouch_DbgCmd(CAPTOUCH_DEV, ENABLE);
CapTouch_Cmd(CAPTOUCH_DEV, ENABLE);
/* continuous sample in debug mode */
for(i = 0; i < 4; i++) {
retry:
tmp = 0;
for(j = 0; j < 8; j++) {
data = CapTouch_DbgRawData(CAPTOUCH_DEV);
tmp |= ((data & BIT(0)) << j);
}
if(tmp == 0 || tmp == 0xFF)
goto retry;
random[i] = tmp;
}
/* Disable debug mode */
CapTouch_DbgCmd(CAPTOUCH_DEV, DISABLE);
CapTouch_Cmd(CAPTOUCH_DEV, DISABLE);
rand_first = 1;
data = (random[3] << 24) | (random[2] << 16) | (random[1] << 8) | (random[0]);
rand_seed[0] = data;
rand_seed[1] = data;
rand_seed[2] = data;
rand_seed[3] = data;
BKUP_Write(BKUP_REG6, data);
return;
}
extern void TaskIdle_8721D(void);
IMAGE2_RAM_TEXT_SECTION
void
app_taskidle_handler(
void
)
{
#if CONFIG_WIFI_FW_EN
TaskIdle_8721D();
#endif
}
// The Main App entry point
void app_start(void)
{
app_section_init();
_memset((void *) __bss_start__, 0, (__bss_end__ - __bss_start__));
SystemCoreClockUpdate();
DBG_PRINTF(MODULE_BOOT, LEVEL_INFO,"KM0 BOOT_IMG2 BOOT REASON: %x \n", BOOT_Reason());
/* check if enable WIFI */
if (ps_config.km0_config_wifi_enable) {
BKUP_Set(0, BIT_WIFI_ENABLE);
}
/* setting key & captouch information */
if (ps_config.km0_enable_key_touch & BIT_KEY_ENABLE)
BKUP_Set(0, BIT_KEY_ENABLE);
if (ps_config.km0_enable_key_touch & BIT_CAPTOUCH_ENABLE)
BKUP_Set(0, BIT_CAPTOUCH_ENABLE);
if (ps_config.km0_enable_key_touch & BIT_GPIO_ENABLE)
BKUP_Set(0, BIT_GPIO_ENABLE);
/* check and set dsleep wakeup status */
app_dslp_wake_check();
/* do it before pinmap_init, or power leakage will happened */
app_gen_random_seed();
/* low power pin dont need pinmap init again after wake from dslp */
pinmap_init(); /* 1.7ms */
if(SOCPS_DsleepWakeStatusGet() == FALSE) {
OSC131K_Calibration(30000); /* PPM=30000=3% *//* 7.5ms */
SDM32K_Enable(SDM32K_ALWAYS_CAL); /* 0.6ms */
SDM32K_RTCCalEnable(ps_config.km0_rtc_calibration); /* 0.3ms */
// Retention Ram reset
_memset((void*)RETENTION_RAM_BASE,0,1024);
assert_param(sizeof(RRAM_TypeDef) <= 0xB0);
} else {
SOCPS_DsleepWakeStatusSet(TRUE); /* KM4 boot check it */
}
OSC4M_Init();
OSC2M_Calibration(OSC2M_CAL_CYC_128, 30000); /* PPM=30000=3% *//* 0.5 */
SYSTIMER_Init(); /* 0.2ms */
SOCPS_InitSYSIRQ();
km4_pm_init();
app_start_autoicg();
app_pmc_patch();
if(!(BIT_BOOT_BOD_RESET_HAPPEN & BOOT_Reason())) {
app_vdd1833_detect();
}
__NVIC_SetVector(SVCall_IRQn, (u32)vPortSVCHandler);
__NVIC_SetVector(PendSV_IRQn, (u32)xPortPendSVHandler);
__NVIC_SetVector(SysTick_IRQn, (u32)xPortSysTickHandler);
#if defined ( __ICCARM__ )
/* it is dummy code, but IAR linker need this */
__iar_data_init3();
#endif
mpu_init();
app_mpu_nocache_init();
main();
}
IMAGE2_VALID_PATTEN_SECTION
const u8 RAM_IMG2_VALID_PATTEN[20] = {
'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff),
(FW_CHIP_VER),
(FW_BUS_TYPE),
(FW_INFO_RSV1),
(FW_INFO_RSV2),
(FW_INFO_RSV3),
(FW_INFO_RSV4)
};
IMAGE2_ENTRY_SECTION
RAM_START_FUNCTION Img2EntryFun0 = {
app_start,
NULL,//SOCPS_WakeFromPG
NULL,
};
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_lp/rtl8721dlp_app_start.c
|
C
|
apache-2.0
| 11,592
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "ameba_soc.h"
#if (defined(CONFIG_CP))
BOOT_RAM_TEXT_SECTION
VOID CPTest_GPIOCtrl(u32 GPIO_Pin, u32 Val)
{
GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.GPIO_Pin = GPIO_Pin;
GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
GPIO_Init(&GPIO_InitStruct);
GPIO_WriteBit(GPIO_Pin, Val);
}
BOOT_RAM_TEXT_SECTION
VOID CPTest_Init(VOID)
{
BKUP_Write(BKUP_REG2, 0x00);
CPTest_GPIOCtrl(_PA_0, 0);
CPTest_GPIOCtrl(_PA_1, 0);
CPTest_GPIOCtrl(_PA_2, 0);
CPTest_GPIOCtrl(_PA_3, 0);
CPTest_GPIOCtrl(_PA_4, 0);
CPTest_GPIOCtrl(_PA_5, 0);
CPTest_GPIOCtrl(_PA_16, 0);
DelayUs(1000);
BKUP_Write(BKUP_REG2, 0x01);
GPIO_WriteBit(_PA_0, 1);
}
BOOT_RAM_TEXT_SECTION
VOID CPTest_FlashCalibrationOk(VOID)
{
BKUP_Write(BKUP_REG2, 0x03);
GPIO_WriteBit(_PA_1, 1);
}
BOOT_RAM_TEXT_SECTION
VOID CPTest_EnterImg2Ok(VOID)
{
BKUP_Write(BKUP_REG2, 0x07);
GPIO_WriteBit(_PA_2, 1);
}
BOOT_RAM_TEXT_SECTION
void CPTest_UARTInit(u8 uart_idx, u8 pin_mux, u32 baud_rate)
{
UART_InitTypeDef UART_InitStruct;
switch (uart_idx) {
case 0:
RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
PinCtrl(PERIPHERAL_UART0, pin_mux, ON);
break;
case 1:
RCC_PeriphClockCmd(APBPeriph_UART1, APBPeriph_UART1_CLOCK, ENABLE);
PinCtrl(PERIPHERAL_UART1, pin_mux, ON);
break;
case 2:
/* UART2 is LogUART */
RCC_PeriphClockCmd(APBPeriph_LOGUART, APBPeriph_LOGUART_CLOCK, ENABLE);
PinCtrl(PERIPHERAL_LOG_UART, pin_mux, ON);
break;
default:
return;
}
UART_StructInit(&UART_InitStruct);
UART_InitStruct.DmaModeCtrl = DISABLE;
UART_InitStruct.WordLen = RUART_WLS_8BITS;
UART_InitStruct.StopBit = RUART_STOP_BIT_1; // word length select: 0 -> no stop bit, 1 -> 1 stop bit
UART_InitStruct.Parity = DISABLE; // parity check enable
UART_InitStruct.ParityType = RUART_ODD_PARITY;
UART_InitStruct.StickParity = DISABLE;
UART_InitStruct.FlowControl = DISABLE;
UART_InitStruct.RxFifoTrigLevel = UART_RX_FIFOTRIG_LEVEL_1BYTES;
UART_InitStruct.RxErReportCtrl = UART_RX_EEROR_REPORT_ENABLE;
UART_Init(UART_DEV_TABLE[uart_idx].UARTx, &UART_InitStruct);
UART_SetBaud(UART_DEV_TABLE[uart_idx].UARTx, baud_rate);
UART_INTConfig(UART_DEV_TABLE[uart_idx].UARTx, RUART_IER_ERBI | RUART_IER_ELSI, DISABLE);
UART_RxCmd(UART_DEV_TABLE[uart_idx].UARTx, ENABLE);
}
BOOT_RAM_TEXT_SECTION
static VOID CPTest_UART(VOID)
{
char rx_char = 0;
u32 timeout = 10000;
CPTest_UARTInit(1, S0, 1500000);
CPTest_UARTInit(0, S1, 1500000);
BKUP_Write(BKUP_REG2, 0x1F);
GPIO_WriteBit(_PA_4, 1);
/* clear UART 1 RX */
while (1) {
if (UART_Readable(UART1_DEV)) {
UART_CharGet(UART1_DEV, &rx_char);
} else {
break;
}
}
/* clear UART 0 RX */
while (1) {
if (UART_Readable(UART0_DEV)) {
UART_CharGet(UART0_DEV, &rx_char);
} else {
break;
}
}
rx_char = 0;
UART_CharPut(UART1_DEV, 0xAA);
do {
if (UART_Readable(UART0_DEV)) {
UART_CharGet(UART0_DEV, &rx_char);
break;
}
timeout--;
} while (timeout != 0);
if (rx_char == 0xAA) {
BKUP_Write(BKUP_REG2, 0x3F);
GPIO_WriteBit(_PA_5, 1);
}
}
BOOT_RAM_TEXT_SECTION
VOID CPTest_OSCCalibrationOk(VOID)
{
int i = 5;
BKUP_Write(BKUP_REG2, 0x0F);
GPIO_WriteBit(_PA_3, 1);
CPTest_UART();
if (BKUP_Read(BKUP_REG2) == 0x3F) {
while(i--){
GPIO_WriteBit(_PA_16, 1);
DelayUs(100);
GPIO_WriteBit(_PA_16, 0);
DelayUs(100);
}
}
DiagPrintf("\n");
DiagPrintf("<<<< >>>>\n");
DiagPrintf("<<<< Flash boot SUCCESS >>>>\n");
DiagPrintf("<<<< >>>>\n");
DiagPrintf("\n");
}
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_lp/rtl8721dlp_cpft.c
|
C
|
apache-2.0
| 3,881
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "ameba_soc.h"
static FlashInfo_TypeDef *current_IC;
/* Flag to check configuration register or not. Necessary for wide-range VCC MXIC flash */
static u8 check_config_reg = 0;
extern FlashInfo_TypeDef Flash_AVL[];
extern u16 Flash_ReadMode;
extern u16 Flash_Speed;
IMAGE2_RAM_TEXT_SECTION
BOOL _flash_calibration_highspeed(u8 SpicBitMode, u8 div)
{
u32 window_size = 0;
u32 phase_shift_idx = 0;
u32 line_delay = 0;
u32 line_delay_temp = 0;
u32 window_temp = 0;
u32 window_size_temp = 0;
//u32 window_start_temp = 0;
//u32 window_end_temp = 0;
/* init last point before calibration */
FLASH_CalibrationInit(30);
/* 4.808 ms take when enter this function */
/* 511us will take for flash full calibration */
for (line_delay_temp = 1; line_delay_temp <= 5; line_delay_temp++) {
window_temp = FLASH_CalibrationNew(&flash_init_para, SpicBitMode, div, 2, line_delay_temp, 1);
window_size_temp = (window_temp & 0xFF);
//window_start_temp = ((window_temp >> 16) & 0xFF);
//window_end_temp = ((window_temp >> 24) & 0xFF);
if (flash_init_para.phase_shift_idx != 0) {
flash_init_para.phase_shift_idx |= BIT(0); /* odd is better */
}
//DBG_8195A("calibration_result:[%d:%d:%d][%x:%x] \n", line_delay_temp, window_size_temp, flash_init_para.phase_shift_idx,
// window_start_temp, window_end_temp);
//BKUP_Write(BKUP_REG3, ((window_start_temp << 24) | (line_delay_temp << 16) | (window_size_temp << 8) | flash_init_para.phase_shift_idx));
if (window_size_temp > window_size) {
window_size = window_size_temp;
line_delay = line_delay_temp;
phase_shift_idx = flash_init_para.phase_shift_idx;
}
flash_init_para.phase_shift_idx = 0;
}
if (window_size > 0) {
DBG_8195A("calibration_ok:[%d:%d:%d] \n", line_delay, window_size, phase_shift_idx);
flash_init_para.phase_shift_idx = phase_shift_idx;
flash_init_para.FLASH_rd_sample_phase_cal = line_delay;
flash_init_para.FLASH_rd_sample_phase = flash_init_para.FLASH_rd_sample_phase_cal;
return _TRUE;
} else {
flash_init_para.phase_shift_idx = 0;
flash_init_para.FLASH_rd_sample_phase = SPIC_LOWSPEED_SAMPLE_PHASE;
}
return _FALSE;
}
void flash_calibration_backup(u8 flash_speed, u8 read_mode)
{
RRAM_TypeDef* RRAM = ((RRAM_TypeDef *) RRAM_BASE);
DBG_8195A("RRAM: %x %dB \n", RRAM_BASE, sizeof(RRAM_TypeDef));
RRAM->FLASH_ClockDiv = flash_speed;
RRAM->FLASH_ReadMode = read_mode;
RRAM->FLASH_phase_shift_idx = flash_init_para.phase_shift_idx;
RRAM->FLASH_rd_sample_phase_cal = flash_init_para.FLASH_rd_sample_phase;
RRAM->FLASH_cur_bitmode = flash_init_para.FLASH_cur_bitmode;
RRAM->FLASH_cur_cmd = flash_init_para.FLASH_cur_cmd;
RRAM->FALSH_quad_valid_cmd = flash_init_para.FALSH_quad_valid_cmd;
RRAM->FALSH_dual_valid_cmd = flash_init_para.FALSH_dual_valid_cmd;
RRAM->FLASH_pseudo_prm_en = flash_init_para.FLASH_pseudo_prm_en;
RRAM->FLASH_addr_phase_len = flash_init_para.FLASH_addr_phase_len;
RRAM->FLASH_cmd_wr_status2 = flash_init_para.FLASH_cmd_wr_status2;
RRAM->FLASH_QuadEn_bit = flash_init_para.FLASH_QuadEn_bit;
RRAM->FLASH_rd_dummy_cyle0 = flash_init_para.FLASH_rd_dummy_cyle[0];
RRAM->FLASH_rd_dummy_cyle1 = flash_init_para.FLASH_rd_dummy_cyle[1];
RRAM->FLASH_rd_dummy_cyle2 = flash_init_para.FLASH_rd_dummy_cyle[2];
}
IMAGE2_RAM_TEXT_SECTION
u32 flash_calibration_highspeed(u8 div)
{
u32 Ret = _SUCCESS;
u8 spic_mode = flash_init_para.FLASH_cur_bitmode;
flash_init_para.debug = 0;
/* SPIC clock switch to PLL */
FLASH_ClockDiv(div);
if (_flash_calibration_highspeed(spic_mode, div) == _TRUE) {
/* we should open calibration new first, and then set phase index */
FLASH_CalibrationNewCmd(ENABLE);
FLASH_CalibrationPhaseIdx(flash_init_para.phase_shift_idx);
/* this code is rom code, so it is safe */
FLASH_Init(spic_mode);
DBG_8195A("FLASH CALIB[NEW OK]\n");
} else {
/* calibration fail, revert SPIC clock to XTAL */
RCC_PeriphClockSource_SPIC(BIT_SHIFT_FLASH_CLK_XTAL);
DBG_8195A("FLASH CALIB[NEW FAIL]\n");
Ret = _FAIL;
}
return Ret;
}
static u8 flash_get_option(u32 sys_data, BOOL is_speed)
{
u16 tmp = 0x8000;
u8 cnt = 0;
while(tmp){
if((sys_data & tmp) != 0){
break;
}else{
tmp = tmp >> 1;
cnt++;
}
}
if(is_speed) {
if(cnt == 0)
cnt = 1;
else if(cnt == 1)
cnt = 0;
else if(cnt > 4)
cnt = 4;
}
return cnt;
}
static FlashInfo_TypeDef *flash_get_chip_info(u32 flash_id)
{
u32 i = 0;
u32 temp;
while(Flash_AVL[i].flash_class != FlashClassNone) {
temp = flash_id & Flash_AVL[i].id_mask;
if(Flash_AVL[i].flash_id == temp)
return &Flash_AVL[i];
i++;
}
return NULL;
}
static void flash_get_vendor(void)
{
RRAM_TypeDef* RRAM = ((RRAM_TypeDef *) RRAM_BASE);
u8 flash_ID[4];
/* Read flash ID */
FLASH_RxCmd(flash_init_para.FLASH_cmd_rd_id, 3, flash_ID);
DBG_8195A("Flash ID:%x, %x, %x\n", flash_ID[0], flash_ID[1], flash_ID[2]);
/* Get flash chip information */
current_IC = flash_get_chip_info((flash_ID[2] << 16) |(flash_ID[1] << 8) |flash_ID[0]);
if(current_IC == NULL) {
DBG_8195A("This flash type is not supported!\n");
assert_param(0);
}
RRAM->FLASH_class = current_IC->flash_class;
RRAM->FLASH_ID2 = flash_ID[2];
/* Re-initialize flash init structure according to classification */
switch (current_IC->flash_class) {
case FlashClass1:
FLASH_StructInit(&flash_init_para);
RRAM->FLASH_StructInit = (u32)FLASH_StructInit;
break;
case FlashClass2:
FLASH_StructInit_GD(&flash_init_para);
if(flash_ID[2] > 0x15) /* GD capacity more than 2MB */
flash_init_para.FLASH_cmd_wr_status2 = 0x31;
RRAM->FLASH_StructInit = (u32)FLASH_StructInit_GD;
break;
case FlashClass3:
FLASH_StructInit_MXIC(&flash_init_para);
RRAM->FLASH_StructInit = (u32)FLASH_StructInit_MXIC;
break;
case FlashClass4: /* EON without QE bit */
FLASH_StructInit_MXIC(&flash_init_para);
flash_init_para.FLASH_QuadEn_bit = 0;
RRAM->FLASH_StructInit = (u32)FLASH_StructInit_MXIC;
break;
case FlashClass5:
FLASH_StructInit_Micron(&flash_init_para);
RRAM->FLASH_StructInit = (u32)FLASH_StructInit_Micron;
break;
case FlashClass6: /* MXIC wide-range VCC chip */
FLASH_StructInit_MXIC(&flash_init_para);
check_config_reg = 1;
RRAM->FLASH_StructInit = (u32)FLASH_StructInit_MXIC;
break;
case FlashClassUser:
assert_param(current_IC->FlashInitHandler != NULL);
current_IC->FlashInitHandler();
RRAM->FLASH_StructInit = (u32)NULL;
break;
default:
break;
}
if(HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_SYS_EFUSE_SYSCFG3) & BIT_SYS_SPIC_ADDR_4BYTE_EN)
flash_init_para.FLASH_addr_phase_len = ADDR_4_BYTE;
}
static void flash_set_status_register(void)
{
u8 StatusLen = 1;
u32 data = 0;
u32 status;
u32 mask = current_IC->sta_mask;
if (flash_init_para.FLASH_QuadEn_bit !=0)
data |= flash_init_para.FLASH_QuadEn_bit;
/* read status1 register */
FLASH_RxCmd(flash_init_para.FLASH_cmd_rd_status, 1, (u8*)&status);
/* check if status2 exist */
if (flash_init_para.FLASH_Status2_exist) {
StatusLen = 2;
FLASH_RxCmd(flash_init_para.FLASH_cmd_rd_status2, 1, ((u8*)&status) + 1);
} else if (check_config_reg) { /* for MXIC wide-range flash, 1 status register + 2 config register */
/* Read configuration register */
FLASH_RxCmd(0x15, 2, ((u8*)&status) + 1);
StatusLen = 3;
/* L/H Switch */
data |= (BIT(9) << 8);
}
status &= mask;
if(_memcmp((void*)&status, (void*)&data, StatusLen)) {
if(!flash_init_para.FLASH_cmd_wr_status2) {
FLASH_SetStatus(flash_init_para.FLASH_cmd_wr_status, StatusLen, (u8*)&data);
} else {
FLASH_SetStatus(flash_init_para.FLASH_cmd_wr_status, 1, (u8*)&data);
FLASH_SetStatus(flash_init_para.FLASH_cmd_wr_status2, 1, ((u8*)&data) + 1);
}
}
}
IMAGE2_RAM_TEXT_SECTION
u32 flash_rx_mode_switch(u8 read_mode)
{
u32 Ret = _SUCCESS;
u8 tmp_dc = 0, status = 0, spic_mode = 0, i;
u32 pdata[2];
for(i = read_mode; i < 5; i++) {
if(i == ReadQuadIOMode){
flash_init_para.FLASH_pseudo_prm_en = 1;
flash_init_para.FALSH_quad_valid_cmd = (BIT_WR_BLOCKING | BIT_RD_QUAD_IO | BIT_PRM_EN);
tmp_dc = flash_init_para.FLASH_rd_dummy_cyle[2];
flash_init_para.FLASH_rd_dummy_cyle[2] -= QUAD_PRM_CYCLE_NUM;
spic_mode = SpicQuadBitMode;
flash_init_para.FLASH_cur_cmd = FLASH_CMD_4READ;
}else if(i == ReadQuadOMode){
flash_init_para.FLASH_pseudo_prm_en = 0;
flash_init_para.FALSH_quad_valid_cmd = (BIT_WR_BLOCKING | BIT_RD_QUAD_O);
flash_init_para.FLASH_rd_dummy_cyle[2] = FLASH_DM_CYCLE_4O;
tmp_dc = flash_init_para.FLASH_rd_dummy_cyle[2];
spic_mode = SpicQuadBitMode;
flash_init_para.FLASH_cur_cmd = FLASH_CMD_QREAD;
}else if(i == ReadDualIOMode){
flash_init_para.FLASH_pseudo_prm_en = 1;
flash_init_para.FALSH_dual_valid_cmd = (BIT_WR_BLOCKING |BIT_FRD_SINGEL | BIT_CTRLR0_CH | BIT_PRM_EN);
tmp_dc = flash_init_para.FLASH_rd_dummy_cyle[1];
flash_init_para.FLASH_rd_dummy_cyle[1] -= DUAL_PRM_CYCLE_NUM;
spic_mode = SpicDualBitMode;
flash_init_para.FLASH_cur_cmd = FLASH_CMD_2READ;
}else if(i == ReadDualOMode){
flash_init_para.FLASH_pseudo_prm_en = 0;
flash_init_para.FALSH_dual_valid_cmd = (BIT_WR_BLOCKING | BIT_RD_DUAL_I);
flash_init_para.FLASH_rd_dummy_cyle[1] = FLASH_DM_CYCLE_2O;
tmp_dc = flash_init_para.FLASH_rd_dummy_cyle[1];
spic_mode = SpicDualBitMode;
flash_init_para.FLASH_cur_cmd = FLASH_CMD_DREAD;
}else{
flash_init_para.FLASH_pseudo_prm_en = 0;
tmp_dc = flash_init_para.FLASH_rd_dummy_cyle[0];
spic_mode = SpicOneBitMode;
flash_init_para.FLASH_cur_cmd = FLASH_CMD_READ;
}
if(flash_init_para.FLASH_Id == FLASH_ID_MICRON){
FLASH_RxCmd(0x85, 1, &status);
status = (status & 0x0f) | (tmp_dc << 4);
FLASH_SetStatus(0x81, 1, &status);
}
flash_init_para.FLASH_rd_sample_phase = SPIC_LOWSPEED_SAMPLE_PHASE;
FLASH_Init(spic_mode);
DCache_Invalidate(SPI_FLASH_BASE, 8);
pdata[0] = HAL_READ32(SPI_FLASH_BASE, 0x00);
pdata[1] = HAL_READ32(SPI_FLASH_BASE, 0x04);
if(_memcmp(pdata, SPIC_CALIB_PATTERN, 8) == 0) {
DBG_8195A("read_mode:%d\n", i);
break;
} else {
if(flash_init_para.debug)
DBG_8195A("read mode %d fail\n", i);
}
}
if(i == 5) {
DBG_8195A("Flash read mode switch FAIL!\n");
Ret = _FAIL;
}
return Ret;
}
void flash_operation_config(void)
{
u8 read_mode;
u8 flash_speed;
if (SOCPS_DsleepWakeStatusGet() == TRUE) {
return;
}
read_mode = flash_get_option(Flash_ReadMode, _FALSE);
flash_speed = flash_get_option(Flash_Speed, _TRUE);
//DBG_8195A("flash_speed: %d\n", flash_speed);
__asm volatile( "cpsid i" );
/* Get flash ID to reinitialize FLASH_InitTypeDef structure */
flash_get_vendor();
/* Set flash status register: set QE, clear protection bits */
if (SOCPS_DsleepWakeStatusGet() == FALSE) {
flash_set_status_register();
}
/* Set flash I/O mode and high-speed calibration */
flash_rx_mode_switch(read_mode);
flash_calibration_highspeed(flash_speed);
flash_calibration_backup(flash_speed, read_mode);
__asm volatile( "cpsie i" );
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_lp/rtl8721dlp_flashclk.c
|
C
|
apache-2.0
| 11,281
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "ameba_soc.h"
CPU_PWR_SEQ SYSPLL_ON_SEQ[] = {
/* Enable SYS PLL */
{0x48000208, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 28)},
{0x48000280, CPU_PWRSEQ_CMD_WRITE, 0x00000000, 0x00000003},
{0x00000000, CPU_PWRSEQ_CMD_DELAY, 0x00000000, 4}, //delay 2us
{0x48000280, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 2)},
{0x480002B0, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 31)},
{0x00000000, CPU_PWRSEQ_CMD_DELAY, 0x00000000, 4}, //delay 400us
{0x48000264, CPU_PWRSEQ_CMD_WRITE, (0x01 << 29), 0x00000000},
{0x480002B0, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x03 << 29)},
{0x48000200, CPU_PWRSEQ_CMD_WRITE, (0x01 << 21), 0x00000000},
{0x480003F4, CPU_PWRSEQ_CMD_POLLING, (0x01 << 12), (0x01 << 12)}, /* temp use delay because FPGA dont have this function */
//{0x00000000, CPU_PWRSEQ_CMD_DELAY, 0x00000000, 100}, //delay 100us
{0x480002B0, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 8)},
/* End */
{0xFFFFFFFF, CPU_PWRSEQ_CMD_END, 0x00000000, 0x00000000},
};
CPU_PWR_SEQ SYSPLL_OFF_SEQ[] = {
/* Disable SYS PLL */
{0x480002B0, CPU_PWRSEQ_CMD_WRITE, (0x001 << 8), 0x00000000},
{0x48000200, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x001 << 21)},
{0x48000264, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x001 << 29)},
{0x480002B0, CPU_PWRSEQ_CMD_WRITE, (0x007 << 29), 0x00000000},
/* End */
{0xFFFFFFFF, CPU_PWRSEQ_CMD_END, 0x00000000, 0x00000000},
};
CPU_PWR_SEQ HSPWR_ON_SEQ[] = {
{0x00000000, CPU_PWRSEQ_CMD_LOGE, 0x00000000, 0x00000000/* or 1 */}, /* Enable LOG or not */
/* 1. Enable SWR */ //PMC
//{0x48000240, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 0)},
//{0x480003F4, CPU_PWRSEQ_CMD_POLLING, (0x01 << 11), (0x01 << 11)}, /* temp use delay because FPGA dont have this function */
//{0x00000000, CPU_PWRSEQ_CMD_DELAY, 0x00000000, 100}, //delay 100us
//{0x48000240, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 2)},
/* 2. Enable xtal/banggap */ //PMC
//{0x48000260, CPU_PWRSEQ_CMD_WRITE, 0x00000000, 0x03},
//{0x00000000, CPU_PWRSEQ_CMD_DELAY, 0x00000000, 750}, //delay 750us
/* 4. Enable HS power */
{0x48000200, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 1)},
{0x48000200, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 2)},
{0x00000000, CPU_PWRSEQ_CMD_DELAY, 0x00000000, 200}, //delay 100us
{0x48000200, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 3)},
{0x48000200, CPU_PWRSEQ_CMD_WRITE, (0x03 << 17), 0x00000000},
/* 5. Enable clock and reset */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 0)},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 4)},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x1FF << 16), (0x101 << 16)}, /* BIT24 is just for FPGA, ASIC dont need */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x07 << 1)},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x07 << 25), 0x00000000}, //set KM4 200MHz
/* 1. Recover KM4 Memory power, the memory low power config in sleep_hsram_config[] */
{0x48000B08, CPU_PWRSEQ_CMD_WRITE, (0xFFFFFFFF), 0x00000000},
/* 6. Enable WIFI related */
{0x48000314, CPU_PWRSEQ_CMD_WRITE, 0x00000000, 0x00000001}, // enable HW auto response
/* 7. HS IPC Enable*/
{0x40000200, CPU_PWRSEQ_CMD_WRITE, 0x00000000, BIT_HS_IPC_FEN}, //function enable
{0x40000210, CPU_PWRSEQ_CMD_WRITE, 0x00000000, BIT_HS_IPC_CKE}, //clock enable
/* End */
{0xFFFFFFFF, CPU_PWRSEQ_CMD_END, 0x00000000, 0x00000000},
};
CPU_PWR_SEQ HSPWR_OFF_SEQ[] = {
/* 1. HSSYSON clock switch to 4M */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 17)},
/* 2. Delay 20us for clock switch down*/
{0x00000000, CPU_PWRSEQ_CMD_DELAY, 0x00000000, 20},
/* 3. Gate CPU & Platform Clock */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x001 << 16), 0x00000000},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x001 << 24), 0x00000000}, /* BIT24 is just for FPGA, ASIC dont need */
/* 4. Reset CPU & Platform */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x01F << 0), 0x00000000},
/* 6. Disable HS Platform/HSSYSON power */
{0x48000200, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x003 << 17)},
{0x48000200, CPU_PWRSEQ_CMD_WRITE, (0x007 << 1), 0x00000000},
/* End */
{0xFFFFFFFF, CPU_PWRSEQ_CMD_END, 0x00000000, 0x00000000},
};
CPU_PWR_SEQ HSCLK_GATE_SEQ[] = {
/* 1. HSSYSON clock switch to 4M */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 17)},
/* 2. Delay 20us for clock switch down*/
{0x00000000, CPU_PWRSEQ_CMD_DELAY, 0x00000000, 20},
/* 3. Gate CPU & Platform Clock */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x001 << 16), 0x00000000},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x001 << 24), 0x00000000}, /* BIT24 is just for FPGA, ASIC dont need */
/* 4. Disable clock generator*/
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x001 << 4), 0x0000000F},
/* End */
{0xFFFFFFFF, CPU_PWRSEQ_CMD_END, 0x00000000, 0x00000000},
};
CPU_PWR_SEQ HSCLK_ON_SEQ[] = {
/* 1. Recover KM4 Memory power, the memory low power config in sleep_hsram_config[] */
{0x48000B08, CPU_PWRSEQ_CMD_WRITE, (0xFFFFFFFF), 0x00000000},
/* 3. Enable clock and reset */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 4)},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 24)},/* BIT24 is just for FPGA, ASIC dont need */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 16)},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x01 << 17), 0x00000000},
/* End */
{0xFFFFFFFF, CPU_PWRSEQ_CMD_END, 0x00000000, 0x00000000},
};
/*It is different from HSPWR_OFF_SEQ[] for some peripheral to work in KM4 power gate mode*/
CPU_PWR_SEQ HSPWR_GATE_SEQ[] = {
/* 1. Disable SDIO dev func en off */
{0x40000208, CPU_PWRSEQ_CMD_WRITE, (0x01 << 1), 0x00000000},
/* 2. HSSYSON clock switch to 4M */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 17)},
/* 3. Delay 20us for clock switch down*/
{0x00000000, CPU_PWRSEQ_CMD_DELAY, 0x00000000, 20},
/* 4. Gate CPU & Platform Clock */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x001 << 16), 0x00000000},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x001 << 24), 0x00000000}, /* BIT24 is just for FPGA, ASIC dont need */
/* 5. Reset CPU & Platform*/
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x01F << 0), 0x00000001},
/* End */
{0xFFFFFFFF, CPU_PWRSEQ_CMD_END, 0x00000000, 0x00000000},
};
CPU_PWR_SEQ HSPWR_WAKE_SEQ[] = {
/* 1. Recover KM4 Memory power, the memory low power config in sleep_hsram_config[] */
{0x48000B08, CPU_PWRSEQ_CMD_WRITE, (0xFFFFFFFF), 0x00000000},
/* 2. Enable HS power */
{0x48000200, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 2)},
{0x00000000, CPU_PWRSEQ_CMD_DELAY, 0x00000000, 200}, //delay 100us
{0x48000200, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 3)},
{0x48000200, CPU_PWRSEQ_CMD_WRITE, (0x01 << 18), 0x00000000},
/* 3. Enable clock and reset */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 4)},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 24)},/* BIT24 is just for FPGA, ASIC dont need */
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 16)},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, (0x01 << 17), 0x00000000},
{0x4800021C, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x07 << 1)},
/* 4. Enable SDIO dev func off */
{0x40000208, CPU_PWRSEQ_CMD_WRITE, 0x00000000, (0x01 << 1)},
/* End */
{0xFFFFFFFF, CPU_PWRSEQ_CMD_END, 0x00000000, 0x00000000},
};
u8 km4_sleep_type;
u32 km4_sleep_timeout = 0xffffffff;
u32 km4_wake_event;
u32 km4_status_on(void)
{
u32 Temp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_KM4_CTRL);
if (Temp & BIT_LSYS_HPLAT_CKE){
return 1;
} else {
return 0;
}
}
void km4_pm_init(void)
{
}
void km4_boot_on(void)
{
u32 Temp;
pmu_acquire_wakelock(PMU_KM4_RUN);
/* Let KM4 RUN */
Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LP_BOOT_CFG) | BIT_SOC_BOOT_PATCH_KM4_RUN;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LP_BOOT_CFG, Temp);
BOOT_ROM_CM4PON((u32)HSPWR_ON_SEQ);
/*IPC table initialization*/
ipc_table_init();
}
void km4_power_gate(void)
{
u32 temp = 0;
if (!km4_status_on())
return;
DBG_PRINTF(MODULE_KM4, LEVEL_INFO, "M4G\n");
/* poll KM4 clock gate */
while (1) {
temp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLATFORM_PARA); /*get KM4 sleep status*/
if(temp & BIT_KM4_SLEEP_STATUS) {
break;
}
}
BOOT_ROM_CM4PON((u32)HSPWR_GATE_SEQ);
pmu_release_wakelock(PMU_KM4_RUN);
pmu_release_wakelock(PMU_OS);
}
void km4_power_wake(void)
{
u32 Temp = 0;
if (km4_status_on())
return;
DBG_PRINTF(MODULE_KM4, LEVEL_INFO, "M4W\n");
pmu_acquire_wakelock(PMU_KM4_RUN);
/* Let KM4 RUN */
Temp = HAL_READ32(SYSTEM_CTRL_BASE, REG_LP_BOOT_CFG) | BIT_SOC_BOOT_PATCH_KM4_RUN;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_LP_BOOT_CFG, Temp);
BOOT_ROM_CM4PON((u32)HSPWR_WAKE_SEQ);
}
void km4_clock_gate(void)
{
u32 temp = 0;
if (!km4_status_on())
return;
DBG_PRINTF(MODULE_KM4, LEVEL_INFO, "M4CG\n");
/* poll KM4 clock gate */
while (1) {
temp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLATFORM_PARA); /*get KM4 sleep status*/
if(temp & BIT_KM4_SLEEP_STATUS) {
break;
}
}
BOOT_ROM_CM4PON((u32)HSCLK_GATE_SEQ);
DBG_PRINTF(MODULE_KM4, LEVEL_INFO, "M4CG-\n");
pmu_release_wakelock(PMU_KM4_RUN);
pmu_release_wakelock(PMU_OS);
}
void km4_clock_on(void)
{
if (km4_status_on())
return;
DBG_PRINTF(MODULE_KM4, LEVEL_INFO, "M4CW\n");
pmu_acquire_wakelock(PMU_KM4_RUN);
BOOT_ROM_CM4PON((u32)HSCLK_ON_SEQ);
/* tell KM4 wake */
asm volatile ("sev");
DBG_PRINTF(MODULE_KM4, LEVEL_INFO, "M4CW-\n");
}
u32 km4_suspend(u32 type)
{
u32 ret =_SUCCESS;
KM4SLEEP_ParamDef * sleep_param;
u32 duration = 0;
sleep_param = (KM4SLEEP_ParamDef *)ipc_get_message(IPC_INT_KM4_TICKLESS_INDICATION);
if(sleep_param != NULL)
duration = sleep_param->sleep_time;
if (duration > 0) {
/* used for resume delay */
km4_sleep_timeout = xTaskGetTickCount() + duration;
}
if (type == SLEEP_CG) {
km4_clock_gate();
} else {
km4_power_gate();
}
return ret;
}
void km4_wake_event_update(void)
{
/*the timer is used to control KM4 max sleep time*/
u32 current_tick = xTaskGetTickCount();
if (current_tick >= km4_sleep_timeout) {
km4_wake_event |=BIT_HP_WEVT_TIMER_STS;
km4_sleep_timeout = 0xffffffff;
}
/*when keyScan is used as a wake up source,*/
if ((ps_config.km0_enable_key_touch | BIT_KEY_ENABLE)
&& KeyScan_GetINT(KEYSCAN_DEV))
km4_wake_event |=BIT_HP_WEVT_KEYSCAN_STS;
/*when CAPTOUCH is used as a wake up source,*/
if ((ps_config.km0_enable_key_touch | BIT_CAPTOUCH_ENABLE)
&& CapTouch_GetISR(CAPTOUCH_DEV))
km4_wake_event |=BIT_HP_WEVT_CAPTOUCH_STS;
/*when GPIO is used as a wake up source,*/
//if ((ps_config.km0_enable_key_touch | BIT_GPIO_ENABLE)
// && GPIO trigger wake KM4)
// km4_wake_event |=BIT_HP_WEVT_GPIO_STS;
}
void km4_set_wake_event(u32 wevt)
{
km4_wake_event |= wevt;
}
u32 km4_get_wake_event(void)
{
return km4_wake_event ;
}
void km4_resume(void)
{
if (km4_status_on())
goto exit;
pmu_acquire_wakelock(PMU_KM4_RUN);
if (km4_sleep_type == SLEEP_CG) {
km4_clock_on();
} else {
km4_power_wake();
}
/*set wake up status*/
HAL_WRITE32(SYSTEM_CTRL_BASE_HP, REG_HS_WAKE_EVENT_STATUS1, km4_wake_event);
SOCPS_AudioLDO(ENABLE);
exit:
km4_wake_event = 0;
}
void km4_flash_highspeed_suspend(u32 Protection)
{
FLASH_ClockSwitch(BIT_SHIFT_FLASH_CLK_XTAL, Protection);
BOOT_ROM_CM4PON((u32)SYSPLL_OFF_SEQ);
}
void km4_flash_highspeed_init(void)
{
BOOT_ROM_CM4PON((u32)SYSPLL_ON_SEQ);
/* calibration high speed before KM4 run */
flash_operation_config();
}
void km4_flash_highspeed_resume(u32 Protection)
{
BOOT_ROM_CM4PON((u32)SYSPLL_ON_SEQ);
FLASH_ClockSwitch(BIT_SHIFT_FLASH_CLK_PLL, Protection);
}
void km4_tickless_ipc_int(VOID *Data, u32 IrqStatus, u32 ChanNum)
{
/* To avoid gcc warnings */
( void ) Data;
( void ) IrqStatus;
( void ) ChanNum;
u32 Rtemp;
KM4SLEEP_ParamDef * psleep_param;
InterruptEn(UART_LOG_IRQ_LP, 10);
IPCM0_DEV->IPCx_USR[IPC_INT_CHAN_SHELL_SWITCH] = 0x00000000;
psleep_param = (KM4SLEEP_ParamDef *)ipc_get_message(IPC_INT_KM4_TICKLESS_INDICATION);
DCache_Invalidate((u32)psleep_param, sizeof(KM4SLEEP_ParamDef));
//set dlps
if (psleep_param->dlps_enable){
SOCPS_AONTimer(psleep_param->sleep_time);
if (psleep_param->sleep_time) {
SOCPS_AONTimerCmd(ENABLE);
}
SOCPS_DeepSleep_RAM();
}
km4_sleep_type = psleep_param->sleep_type;
switch (psleep_param->sleep_type) {
case SLEEP_PG:
if(_SUCCESS == km4_suspend(SLEEP_PG)) {
Rtemp = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_BOOT_CFG);
Rtemp |= BIT_SOC_BOOT_WAKE_FROM_PS_HS;
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_BOOT_CFG, Rtemp);
}
break;
case SLEEP_CG:
if(_SUCCESS ==km4_suspend(SLEEP_CG)) {
pmu_set_sysactive_time(2);
}
break;
default:
DBG_8195A("unknow sleep type\n");
}
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_lp/rtl8721dlp_km4.c
|
C
|
apache-2.0
| 13,052
|
/**
******************************************************************************
* @file rtl8721dlp_pinmap.c
* @author
* @version V1.0.0
* @date 2016-05-17
* @brief This file provides firmware functions to manage the following
* functionalities of pin control:
* - pinmux
* - active pad pull up & pull down
* - sleep pad pull up & pull down
******************************************************************************
* @attention
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*
* Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
******************************************************************************
*/
#include "ameba_soc.h"
extern const PMAP_TypeDef pmap_func[];
extern const PMAP_TypeDef pmap_func_sleep[];
CONFIG_FW_CRITICAL_CODE_SECTION
static u32 pinmap_touchpin(u32 PinName)
{
if ((PinName == _PB_4) || (PinName == _PB_5) ||
(PinName == _PB_6) || (PinName == _PB_7)) {
return TRUE;
}
return FALSE;
}
/**
* @brief Config all pins to the right function and pull state based on pmap_func table.
* @note should set pmap_func. Function & FuncPuPd corectly based on your board.
* @retval None
*/
CONFIG_FW_CRITICAL_CODE_SECTION
void pinmap_init(void)
{
int i = 0;
u32 dslp_wakeup = SOCPS_DsleepWakeStatusGet();
for (;;) {
/* Check if search to end */
if (pmap_func[i].PinName == _PNC) {
break;
}
/* keep active level when GPIO_PuPd_KEEP */
if (pmap_func[i].FuncPuPd == GPIO_PuPd_KEEP)
goto next;
if (dslp_wakeup) {
/* low power pin, dont pull low power pins ex. keyscan */
if (pmap_func[i].LowPowerPin)
goto next;
/* touch pin, dont pull captouch enabled pin */
if (pinmap_touchpin(pmap_func[i].PinName) == TRUE) {
if (CapTouch_GetChStatus(CAPTOUCH_DEV, (pmap_func[i].PinName - _PB_4))) {
goto next;
}
}
}
/* active PuPd set */
if (pmap_func[i].FuncPuPd == GPIO_PuPd_SHUTDOWN) {
PAD_CMD(pmap_func[i].PinName, DISABLE);
} else {
PAD_PullCtrl(pmap_func[i].PinName, pmap_func[i].FuncPuPd);
}
next:
i++;
}
}
/**
* @brief Config all pins to the right pull state based on pmap_func table before soc sleep.
* @note should set pmap_func.SleepPuPd corectly based on your board.
* @retval None
*/
CONFIG_FW_CRITICAL_CODE_SECTION
void pinmap_sleep(void)
{
int i = 0;
int PinName = 0;
for (;;) {
/* Check if search to end */
if (pmap_func_sleep[i].PinName == _PNC) {
break;
}
/* keep active level when GPIO_PuPd_KEEP */
if (pmap_func_sleep[i].SleepPuPd == GPIO_PuPd_KEEP)
goto next;
PinName = pmap_func_sleep[i].PinName;
/* sleep PuPd set */
if (pmap_func_sleep[i].SleepPuPd == GPIO_PuPd_SHUTDOWN) {
PAD_CMD(PinName, DISABLE);
} else {
PAD_CMD(PinName, ENABLE);
PAD_PullCtrl(PinName, pmap_func_sleep[i].SleepPuPd);
//DBG_8195A("%08x: %08x\n", &(PINMUX->PADCTR[pmap_func[i].PinName]), (PINMUX->PADCTR[pmap_func[i].PinName]));
}
next:
i++;
}
}
/**
* @brief Config all pins to the right pull state based on pmap_func table before soc deep sleep.
* @note should set pmap_func.DSleepPuPd corectly based on your board.
* @retval None
*/
CONFIG_FW_CRITICAL_CODE_SECTION
void pinmap_deepsleep(void)
{
int i = 0;
for (;;) {
/* Check if search to end */
if (pmap_func[i].PinName == _PNC) {
break;
}
/* keep active level when GPIO_PuPd_NOPULL */
if (pmap_func[i].DSleepPuPd == GPIO_PuPd_KEEP)
goto next;
/* sleep PuPd set */
if (pmap_func[i].DSleepPuPd == GPIO_PuPd_SHUTDOWN)
PAD_CMD(pmap_func[i].PinName, DISABLE);
else
PAD_PullCtrl(pmap_func[i].PinName, pmap_func[i].DSleepPuPd);
next:
i++;
}
}
/**
* @brief Config all pins to the right pull state based on pmap_func table after soc wakeup from sleep.
* @note should set pmap_func.FuncPuPd corectly based on your board.
* @retval None
*/
CONFIG_FW_CRITICAL_CODE_SECTION
void pinmap_wake(void)
{
int i = 0;
int PinName = 0;
for (;;) {
/* Check if search to end */
if (pmap_func_sleep[i].PinName == _PNC) {
break;
}
/* pupd not change when sleep */
if (pmap_func_sleep[i].SleepPuPd == GPIO_PuPd_KEEP)
goto next;
PinName = pmap_func_sleep[i].PinName;
/* active PuPd set */
if (pmap_func[PinName].FuncPuPd == GPIO_PuPd_SHUTDOWN) {
PAD_CMD(PinName, DISABLE);
} else {
PAD_PullCtrl(PinName, pmap_func[PinName].FuncPuPd);
}
next:
i++;
}
}
/******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_lp/rtl8721dlp_pinmap.c
|
C
|
apache-2.0
| 4,683
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "ameba_soc.h"
VOID app_simulation_task(VOID *Data)
{
/* To avoid gcc warnings */
( void ) Data;
//u32 argc = 4;
//u8 *argv[5];
static u32 test_done = 0;
do{
/* this is an example, you can change to yourself code if needed */
if (test_done == 0) {
//u32 temp = 0;
simulation_stage_set(SIMULATION_KM0_CPUID, BIT_KM0_SIMULATION_START);
//DCache_Disable();
//simulation_stage_set(SIMULATION_KM0_CPUID, BIT(29));
//DCache_Enable();
//simulation_stage_set(SIMULATION_KM0_CPUID, BIT(30));
//argv[0] = "aon_timer";
//argv[1] = "4";
//pg_sleep_Test(argc, argv);
//argv[0] = "block";
//argv[1] = "3";
//argv[2] = "0";
//argv[3] = "single";
//hs_power_onoff_test(argc, argv);
//while (1) {
// temp = HAL_READ32(SYSTEM_CTRL_BASE_HP, REG_HS_PLATFORM_PARA); /*get KM4 sleep status*/
// if(temp & BIT_KM4_SLEEP_STATUS) {
// break;
// }
// DBG_8195A("BIT_KM4_SLEEP_STATUS:%x \n", temp);
//}
//ICache_Disable();
//km4_suspend(KM4_STATUS_CG_BIT);
//km4_resume();
//asm volatile ("sev");
pmu_set_sleep_type(SLEEP_CG);
pmu_acquire_wakelock(PMU_KM4_RUN);
pmu_release_wakelock(PMU_OS);
test_done = 1;
simulation_stage_set(SIMULATION_KM0_CPUID, BIT_KM0_SIMULATION_END);
} else {
vTaskDelay(1000);
}
} while (1);
}
VOID app_simulation_init(VOID *Data)
{
/* To avoid gcc warnings */
( void ) Data;
if (pdTRUE != xTaskCreate(app_simulation_task, (const char * const)"simulation_task", 1024,
NULL, tskIDLE_PRIORITY + 5 , NULL))
{
DiagPrintf("Create simulation_task Err!!\n");
}
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_lp/rtl8721dlp_simulation.c
|
C
|
apache-2.0
| 1,844
|
/**************************************************************************//**
* @file rtl8721dlp_system.c
* @brief CMSIS Device System Source File for
* ARMCM3 Device Series
* @version V1.08
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include "basic_types.h"
#include "ameba_soc.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __SYSTEM_CLOCK PLATFORM_CLOCK
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
u32
SystemGetCpuClk(void)
{
return CPU_ClkGet(IS_FPGA_VERIF);
}
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
SystemCoreClock = SystemGetCpuClk();
}
/**
* @brief Set CPU clock.
* @param CpuType: For KM0, this parameter can be one of the following values
* @arg CLK_KM0_XTAL
* @arg CLK_KM0_XTALDIV2
* @arg CLK_KM0_ANA_4M
* @note NA
*/
void SystemSetCpuClk(u8 CpuClk)
{
CPU_ClkSet(CpuClk);
SystemCoreClockUpdate();
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
// TODO: Hardware initial
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClockUpdate();
}
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_lp/rtl8721dlp_system.c
|
C
|
apache-2.0
| 3,481
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_OTG_H_
#define _RTL8195A_OTG_H_
#define OTG_FAST_INIT 1
#define DWC_EN_ISOC 1
//#define DWC_EN_ISOC 0
#if defined(DWC_EN_ISOC)
#define USB_REQ_ISO_ASAP 1
#endif
#if defined(DWC_DEVICE_ONLY)
//#define USB_DEV_FULL_SPEED
#endif
#define DWC_RM_DEV_RDNT_SRC
#define DWC_RM_HOST_RDNT_SRC
#define HAL_OTG_READ32(addr) HAL_READ32(USB_OTG_REG_BASE, (u32)addr)
#define HAL_OTG_WRITE32(addr, value) HAL_WRITE32(USB_OTG_REG_BASE, (u32)addr, value)
#define HAL_OTG_MODIFY32(addr, clrmsk, setmsk) HAL_WRITE32(USB_OTG_REG_BASE,(u32)addr,\
((HAL_READ32(USB_OTG_REG_BASE, (u32)addr) & (~clrmsk)) | setmsk))
#define DWC_READ_REG32(_reg_) HAL_OTG_READ32((u32)_reg_)
#define DWC_WRITE_REG32(_reg_, _val_) HAL_OTG_WRITE32((u32)_reg_,_val_)
#define DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_) HAL_OTG_MODIFY32((u32)_reg_,_cmsk_,_smsk_)
// USB OTG addon register
#define REG_OTG_PWCSEQ_IP_OFF 0x30004 //This is in OTG IP
#define REG_OTG_PS_INTR_STS 0x30008 //This is in OTG IP
#define REG_OTG_PS_INTR_MSK 0x3000C //This is in OTG IP
/* #define REG_OTG_PWCSEQ_IP_OFF 0x30004 */
#define BIT_UPLL_CKRDY BIT(5) /* R/W 0 1: USB PHY clock ready */
#define BIT_USBOTG_EN BIT(8) /* R/W 0 1: Enable USB OTG */
#define BIT_USBPHY_EN BIT(9) /* R/W 0 1: Enable USB PHY */
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/ameba_otg.h
|
C
|
apache-2.0
| 1,632
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef RTL8195A_OTG_ZERO_H
#define RTL8195A_OTG_ZERO_H
#include "usb_ch9.h"
#include "usb_gadget.h"
struct zero_dev {
//ModifiedByJD spinlock_t lock;
struct usb_gadget *gadget;
struct usb_request *req; /* for control responses */
/* when configured, we have one of two configs:
* - source data (in to host) and sink it (out from host)
* - or loop it back (out from host back in to host)
*/
u8 config;
struct usb_ep *in_ep, *out_ep, *status_ep;//ModifiedByJD
const struct usb_endpoint_descriptor
*in, *out, *status; //ModifiedByJD
/* autoresume timer */
//ModifiedByJD struct timer_list resume;
};
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/ameba_otg_zero.h
|
C
|
apache-2.0
| 916
|
//#include "../otg/osk/sys-support.h" //ModifiedByJD
/*
* USB Communications Device Class (CDC) definitions
*
* CDC says how to talk to lots of different types of network adapters,
* notably ethernet adapters and various modems. It's used mostly with
* firmware based USB peripherals.
*/
#define USB_CDC_SUBCLASS_ACM 0x02
#define USB_CDC_SUBCLASS_ETHERNET 0x06
#define USB_CDC_SUBCLASS_WHCM 0x08
#define USB_CDC_SUBCLASS_DMM 0x09
#define USB_CDC_SUBCLASS_MDLM 0x0a
#define USB_CDC_SUBCLASS_OBEX 0x0b
#define USB_CDC_PROTO_NONE 0
#define USB_CDC_ACM_PROTO_AT_V25TER 1
#define USB_CDC_ACM_PROTO_AT_PCCA101 2
#define USB_CDC_ACM_PROTO_AT_PCCA101_WAKE 3
#define USB_CDC_ACM_PROTO_AT_GSM 4
#define USB_CDC_ACM_PROTO_AT_3G 5
#define USB_CDC_ACM_PROTO_AT_CDMA 6
#define USB_CDC_ACM_PROTO_VENDOR 0xff
/*-------------------------------------------------------------------------*/
//#define UPACKED __attribute__ ((packed))
#define UPACKED
/*
* Class-Specific descriptors ... there are a couple dozen of them
*/
#define USB_CDC_HEADER_TYPE 0x00 /* header_desc */
#define USB_CDC_CALL_MANAGEMENT_TYPE 0x01 /* call_mgmt_descriptor */
#define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */
#define USB_CDC_UNION_TYPE 0x06 /* union_desc */
#define USB_CDC_COUNTRY_TYPE 0x07
#define USB_CDC_NETWORK_TERMINAL_TYPE 0x0a /* network_terminal_desc */
#define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */
#define USB_CDC_WHCM_TYPE 0x11
#define USB_CDC_MDLM_TYPE 0x12 /* mdlm_desc */
#define USB_CDC_MDLM_DETAIL_TYPE 0x13 /* mdlm_detail_desc */
#define USB_CDC_DMM_TYPE 0x14
#define USB_CDC_OBEX_TYPE 0x15
//ModifiedByJD (>>>) modify the data type to useable ones.
/* "Header Functional Descriptor" from CDC spec 5.2.3.1 */
struct usb_cdc_header_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u16 bcdCDC;
} UPACKED;
/* "Call Management Descriptor" from CDC spec 5.2.3.2 */
struct usb_cdc_call_mgmt_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bmCapabilities;
#define USB_CDC_CALL_MGMT_CAP_CALL_MGMT 0x01
#define USB_CDC_CALL_MGMT_CAP_DATA_INTF 0x02
u8 bDataInterface;
} UPACKED;
/* "Abstract Control Management Descriptor" from CDC spec 5.2.3.3 */
struct usb_cdc_acm_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bmCapabilities;
} UPACKED;
/* "Union Functional Descriptor" from CDC spec 5.2.3.8 */
struct usb_cdc_union_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bMasterInterface0;
u8 bSlaveInterface0;
/* ... and there could be other slave interfaces */
} UPACKED;
/* "Network Channel Terminal Functional Descriptor" from CDC spec 5.2.3.11 */
struct usb_cdc_network_terminal_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bEntityId;
u8 iName;
u8 bChannelIndex;
u8 bPhysicalInterface;
} UPACKED;
/* "Ethernet Networking Functional Descriptor" from CDC spec 5.2.3.16 */
struct usb_cdc_ether_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 iMACAddress;
u32 bmEthernetStatistics;
u16 wMaxSegmentSize;
u16 wNumberMCFilters;
u8 bNumberPowerFilters;
} UPACKED;
/* "MDLM Functional Descriptor" from CDC WMC spec 6.7.2.3 */
struct usb_cdc_mdlm_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u16 bcdVersion;
u8 bGUID[16];
}UPACKED;
/* "MDLM Detail Functional Descriptor" from CDC WMC spec 6.7.2.4 */
struct usb_cdc_mdlm_detail_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
/* type is associated with mdlm_desc.bGUID */
u8 bGuidDescriptorType;
u8 bDetailData[0];
} UPACKED;
/*-------------------------------------------------------------------------*/
/*
* Class-Specific Control Requests (6.2)
*
* section 3.6.2.1 table 4 has the ACM profile, for modems.
* section 3.8.2 table 10 has the ethernet profile.
*
* Microsoft's RNDIS stack for Ethernet is a vendor-specific CDC ACM variant,
* heavily dependent on the encapsulated (proprietary) command mechanism.
*/
#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00
#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01
#define USB_CDC_REQ_SET_LINE_CODING 0x20
#define USB_CDC_REQ_GET_LINE_CODING 0x21
#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22
#define USB_CDC_REQ_SEND_BREAK 0x23
#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER 0x41
#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER 0x42
#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43
#define USB_CDC_GET_ETHERNET_STATISTIC 0x44
/* Line Coding Structure from CDC spec 6.2.13 */
struct usb_cdc_line_coding {
u32 dwDTERate;
u8 bCharFormat;
#define USB_CDC_1_STOP_BITS 0
#define USB_CDC_1_5_STOP_BITS 1
#define USB_CDC_2_STOP_BITS 2
u8 bParityType;
#define USB_CDC_NO_PARITY 0
#define USB_CDC_ODD_PARITY 1
#define USB_CDC_EVEN_PARITY 2
#define USB_CDC_MARK_PARITY 3
#define USB_CDC_SPACE_PARITY 4
u8 bDataBits;
} UPACKED;
/* table 62; bits in multicast filter */
#define USB_CDC_PACKET_TYPE_PROMISCUOUS (1 << 0)
#define USB_CDC_PACKET_TYPE_ALL_MULTICAST (1 << 1) /* no filter */
#define USB_CDC_PACKET_TYPE_DIRECTED (1 << 2)
#define USB_CDC_PACKET_TYPE_BROADCAST (1 << 3)
#define USB_CDC_PACKET_TYPE_MULTICAST (1 << 4) /* filtered */
/*-------------------------------------------------------------------------*/
/*
* Class-Specific Notifications (6.3) sent by interrupt transfers
*
* section 3.8.2 table 11 of the CDC spec lists Ethernet notifications
* section 3.6.2.1 table 5 specifies ACM notifications, accepted by RNDIS
* RNDIS also defines its own bit-incompatible notifications
*/
#define USB_CDC_NOTIFY_NETWORK_CONNECTION 0x00
#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE 0x01
#define USB_CDC_NOTIFY_SERIAL_STATE 0x20
#define USB_CDC_NOTIFY_SPEED_CHANGE 0x2a
struct usb_cdc_notification {
u8 bmRequestType;
u8 bNotificationType;
u16 wValue;
u16 wIndex;
u16 wLength;
}UPACKED;
//ModifiedByJD (<<<)
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/cdc.h
|
C
|
apache-2.0
| 5,962
|
/* $OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $ */
/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */
/*
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)queue.h 8.5 (Berkeley) 8/20/94
*/
#ifndef _DWC_LIST_H_
#define _DWC_LIST_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @file
*
* This file defines linked list operations. It is derived from BSD with
* only the MACRO names being prefixed with DWC_. This is because a few of
* these names conflict with those on Linux. For documentation on use, see the
* inline comments in the source code. The original license for this source
* code applies and is preserved in the dwc_list.h source file.
*/
/*
* This file defines five types of data structures: singly-linked lists,
* lists, simple queues, tail queues, and circular queues.
*
*
* A singly-linked list is headed by a single forward pointer. The elements
* are singly linked for minimum space and pointer manipulation overhead at
* the expense of O(n) removal for arbitrary elements. New elements can be
* added to the list after an existing element or at the head of the list.
* Elements being removed from the head of the list should use the explicit
* macro for this purpose for optimum efficiency. A singly-linked list may
* only be traversed in the forward direction. Singly-linked lists are ideal
* for applications with large datasets and few or no removals or for
* implementing a LIFO queue.
*
* A list is headed by a single forward pointer (or an array of forward
* pointers for a hash table header). The elements are doubly linked
* so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before
* or after an existing element or at the head of the list. A list
* may only be traversed in the forward direction.
*
* A simple queue is headed by a pair of pointers, one the head of the
* list and the other to the tail of the list. The elements are singly
* linked to save space, so elements can only be removed from the
* head of the list. New elements can be added to the list before or after
* an existing element, at the head of the list, or at the end of the
* list. A simple queue may only be traversed in the forward direction.
*
* A tail queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or
* after an existing element, at the head of the list, or at the end of
* the list. A tail queue may be traversed in either direction.
*
* A circle queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or after
* an existing element, at the head of the list, or at the end of the list.
* A circle queue may be traversed in either direction, but has a more
* complex end of list detection.
*
* For details on the use of these macros, see the queue(3) manual page.
*/
/*
* Double-linked List.
*/
typedef struct dwc_list_link {
struct dwc_list_link *next;
struct dwc_list_link *prev;
} dwc_list_link_t;
#define DWC_LIST_INIT(link) do { \
(link)->next = (link); \
(link)->prev = (link); \
} while (0)
#define DWC_LIST_FIRST(link) ((link)->next)
#define DWC_LIST_LAST(link) ((link)->prev)
#define DWC_LIST_END(link) (link)
#define DWC_LIST_NEXT(link) ((link)->next)
#define DWC_LIST_PREV(link) ((link)->prev)
#define DWC_LIST_EMPTY(link) \
(DWC_LIST_FIRST(link) == DWC_LIST_END(link))
#define DWC_LIST_ENTRY(link, type, field) \
(type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
#if 0
#define DWC_LIST_INSERT_HEAD(list, link) do { \
(link)->next = (list)->next; \
(link)->prev = (list); \
(list)->next->prev = (link); \
(list)->next = (link); \
} while (0)
#define DWC_LIST_INSERT_TAIL(list, link) do { \
(link)->next = (list); \
(link)->prev = (list)->prev; \
(list)->prev->next = (link); \
(list)->prev = (link); \
} while (0)
#else
#define DWC_LIST_INSERT_HEAD(list, link) do { \
dwc_list_link_t *__next__ = (list)->next; \
__next__->prev = (link); \
(link)->next = __next__; \
(link)->prev = (list); \
(list)->next = (link); \
} while (0)
#define DWC_LIST_INSERT_TAIL(list, link) do { \
dwc_list_link_t *__prev__ = (list)->prev; \
(list)->prev = (link); \
(link)->next = (list); \
(link)->prev = __prev__; \
__prev__->next = (link); \
} while (0)
#endif
#if 0
static inline void __list_add(struct list_head *new,
struct list_head *prev,
struct list_head *next)
{
next->prev = new;
new->next = next;
new->prev = prev;
prev->next = new;
}
static inline void list_add(struct list_head *new, struct list_head *head)
{
__list_add(new, head, head->next);
}
static inline void list_add_tail(struct list_head *new, struct list_head *head)
{
__list_add(new, head->prev, head);
}
static inline void __list_del(struct list_head * prev, struct list_head * next)
{
next->prev = prev;
prev->next = next;
}
static inline void list_del(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
entry->next = LIST_POISON1;
entry->prev = LIST_POISON2;
}
#endif
#define DWC_LIST_REMOVE(link) do { \
(link)->next->prev = (link)->prev; \
(link)->prev->next = (link)->next; \
} while (0)
#define DWC_LIST_REMOVE_INIT(link) do { \
DWC_LIST_REMOVE(link); \
DWC_LIST_INIT(link); \
} while (0)
#define DWC_LIST_MOVE_HEAD(list, link) do { \
DWC_LIST_REMOVE(link); \
DWC_LIST_INSERT_HEAD(list, link); \
} while (0)
#define DWC_LIST_MOVE_TAIL(list, link) do { \
DWC_LIST_REMOVE(link); \
DWC_LIST_INSERT_TAIL(list, link); \
} while (0)
#define DWC_LIST_FOREACH(var, list) \
for((var) = DWC_LIST_FIRST(list); \
(var) != DWC_LIST_END(list); \
(var) = DWC_LIST_NEXT(var))
#define DWC_LIST_FOREACH_SAFE(var, var2, list) \
for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \
(var) != DWC_LIST_END(list); \
(var) = (var2), (var2) = DWC_LIST_NEXT(var2))
#define DWC_LIST_FOREACH_REVERSE(var, list) \
for((var) = DWC_LIST_LAST(list); \
(var) != DWC_LIST_END(list); \
(var) = DWC_LIST_PREV(var))
/*
* Singly-linked List definitions.
*/
#define DWC_SLIST_HEAD(name, type) \
struct name { \
struct type *slh_first; /* first element */ \
}
#define DWC_SLIST_HEAD_INITIALIZER(head) \
{ NULL }
#define DWC_SLIST_ENTRY(type) \
struct { \
struct type *sle_next; /* next element */ \
}
/*
* Singly-linked List access methods.
*/
#define DWC_SLIST_FIRST(head) ((head)->slh_first)
#define DWC_SLIST_END(head) NULL
#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head))
#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next)
#define DWC_SLIST_FOREACH(var, head, field) \
for((var) = SLIST_FIRST(head); \
(var) != SLIST_END(head); \
(var) = SLIST_NEXT(var, field))
#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \
for((varp) = &SLIST_FIRST((head)); \
((var) = *(varp)) != SLIST_END(head); \
(varp) = &SLIST_NEXT((var), field))
/*
* Singly-linked List functions.
*/
#define DWC_SLIST_INIT(head) { \
SLIST_FIRST(head) = SLIST_END(head); \
}
#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \
(elm)->field.sle_next = (slistelm)->field.sle_next; \
(slistelm)->field.sle_next = (elm); \
} while (0)
#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \
(elm)->field.sle_next = (head)->slh_first; \
(head)->slh_first = (elm); \
} while (0)
#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \
(elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \
} while (0)
#define DWC_SLIST_REMOVE_HEAD(head, field) do { \
(head)->slh_first = (head)->slh_first->field.sle_next; \
} while (0)
#define DWC_SLIST_REMOVE(head, elm, type, field) do { \
if ((head)->slh_first == (elm)) { \
SLIST_REMOVE_HEAD((head), field); \
} \
else { \
struct type *curelm = (head)->slh_first; \
while( curelm->field.sle_next != (elm) ) \
curelm = curelm->field.sle_next; \
curelm->field.sle_next = \
curelm->field.sle_next->field.sle_next; \
} \
} while (0)
/*
* Simple queue definitions.
*/
#define DWC_SIMPLEQ_HEAD(name, type) \
struct name { \
struct type *sqh_first; /* first element */ \
struct type **sqh_last; /* addr of last next element */ \
}
#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).sqh_first }
#define DWC_SIMPLEQ_ENTRY(type) \
struct { \
struct type *sqe_next; /* next element */ \
}
/*
* Simple queue access methods.
*/
#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first)
#define DWC_SIMPLEQ_END(head) NULL
#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
#define DWC_SIMPLEQ_FOREACH(var, head, field) \
for((var) = SIMPLEQ_FIRST(head); \
(var) != SIMPLEQ_END(head); \
(var) = SIMPLEQ_NEXT(var, field))
/*
* Simple queue functions.
*/
#define DWC_SIMPLEQ_INIT(head) do { \
(head)->sqh_first = NULL; \
(head)->sqh_last = &(head)->sqh_first; \
} while (0)
#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
(head)->sqh_last = &(elm)->field.sqe_next; \
(head)->sqh_first = (elm); \
} while (0)
#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
(elm)->field.sqe_next = NULL; \
*(head)->sqh_last = (elm); \
(head)->sqh_last = &(elm)->field.sqe_next; \
} while (0)
#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
(head)->sqh_last = &(elm)->field.sqe_next; \
(listelm)->field.sqe_next = (elm); \
} while (0)
#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \
if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
(head)->sqh_last = &(head)->sqh_first; \
} while (0)
/*
* Tail queue definitions.
*/
#define DWC_TAILQ_HEAD(name, type) \
struct name { \
struct type *tqh_first; /* first element */ \
struct type **tqh_last; /* addr of last next element */ \
}
#define DWC_TAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).tqh_first }
#define DWC_TAILQ_ENTRY(type) \
struct { \
struct type *tqe_next; /* next element */ \
struct type **tqe_prev; /* address of previous next element */ \
}
/*
* tail queue access methods
*/
#define DWC_TAILQ_FIRST(head) ((head)->tqh_first)
#define DWC_TAILQ_END(head) NULL
#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
#define DWC_TAILQ_LAST(head, headname) \
(*(((struct headname *)((head)->tqh_last))->tqh_last))
/* XXX */
#define DWC_TAILQ_PREV(elm, headname, field) \
(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
#define DWC_TAILQ_EMPTY(head) \
(TAILQ_FIRST(head) == TAILQ_END(head))
#define DWC_TAILQ_FOREACH(var, head, field) \
for((var) = TAILQ_FIRST(head); \
(var) != TAILQ_END(head); \
(var) = TAILQ_NEXT(var, field))
#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \
for((var) = TAILQ_LAST(head, headname); \
(var) != TAILQ_END(head); \
(var) = TAILQ_PREV(var, headname, field))
/*
* Tail queue functions.
*/
#define DWC_TAILQ_INIT(head) do { \
(head)->tqh_first = NULL; \
(head)->tqh_last = &(head)->tqh_first; \
} while (0)
#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \
if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
(head)->tqh_first->field.tqe_prev = \
&(elm)->field.tqe_next; \
else \
(head)->tqh_last = &(elm)->field.tqe_next; \
(head)->tqh_first = (elm); \
(elm)->field.tqe_prev = &(head)->tqh_first; \
} while (0)
#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \
(elm)->field.tqe_next = NULL; \
(elm)->field.tqe_prev = (head)->tqh_last; \
*(head)->tqh_last = (elm); \
(head)->tqh_last = &(elm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
(elm)->field.tqe_next->field.tqe_prev = \
&(elm)->field.tqe_next; \
else \
(head)->tqh_last = &(elm)->field.tqe_next; \
(listelm)->field.tqe_next = (elm); \
(elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
(elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
(elm)->field.tqe_next = (listelm); \
*(listelm)->field.tqe_prev = (elm); \
(listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_REMOVE(head, elm, field) do { \
if (((elm)->field.tqe_next) != NULL) \
(elm)->field.tqe_next->field.tqe_prev = \
(elm)->field.tqe_prev; \
else \
(head)->tqh_last = (elm)->field.tqe_prev; \
*(elm)->field.tqe_prev = (elm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \
if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \
(elm2)->field.tqe_next->field.tqe_prev = \
&(elm2)->field.tqe_next; \
else \
(head)->tqh_last = &(elm2)->field.tqe_next; \
(elm2)->field.tqe_prev = (elm)->field.tqe_prev; \
*(elm2)->field.tqe_prev = (elm2); \
} while (0)
/*
* Circular queue definitions.
*/
#define DWC_CIRCLEQ_HEAD(name, type) \
struct name { \
struct type *cqh_first; /* first element */ \
struct type *cqh_last; /* last element */ \
}
#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \
{ DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
#define DWC_CIRCLEQ_ENTRY(type) \
struct { \
struct type *cqe_next; /* next element */ \
struct type *cqe_prev; /* previous element */ \
}
/*
* Circular queue access methods
*/
#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first)
#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last)
#define DWC_CIRCLEQ_END(head) ((void *)(head))
#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
#define DWC_CIRCLEQ_EMPTY(head) \
(DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
#define DWC_CIRCLEQ_FOREACH(var, head, field) \
for((var) = DWC_CIRCLEQ_FIRST(head); \
(var) != DWC_CIRCLEQ_END(head); \
(var) = DWC_CIRCLEQ_NEXT(var, field))
#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \
for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
(var) != DWC_CIRCLEQ_END(head); \
(var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \
for((var) = DWC_CIRCLEQ_LAST(head); \
(var) != DWC_CIRCLEQ_END(head); \
(var) = DWC_CIRCLEQ_PREV(var, field))
/*
* Circular queue functions.
*/
#define DWC_CIRCLEQ_INIT(head) do { \
(head)->cqh_first = DWC_CIRCLEQ_END(head); \
(head)->cqh_last = DWC_CIRCLEQ_END(head); \
} while (0)
#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \
(elm)->field.cqe_next = NULL; \
(elm)->field.cqe_prev = NULL; \
} while (0)
#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
(elm)->field.cqe_next = (listelm)->field.cqe_next; \
(elm)->field.cqe_prev = (listelm); \
if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
(head)->cqh_last = (elm); \
else \
(listelm)->field.cqe_next->field.cqe_prev = (elm); \
(listelm)->field.cqe_next = (elm); \
} while (0)
#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
(elm)->field.cqe_next = (listelm); \
(elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
(head)->cqh_first = (elm); \
else \
(listelm)->field.cqe_prev->field.cqe_next = (elm); \
(listelm)->field.cqe_prev = (elm); \
} while (0)
#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
(elm)->field.cqe_next = (head)->cqh_first; \
(elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \
if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \
(head)->cqh_last = (elm); \
else \
(head)->cqh_first->field.cqe_prev = (elm); \
(head)->cqh_first = (elm); \
} while (0)
#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
(elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \
(elm)->field.cqe_prev = (head)->cqh_last; \
if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \
(head)->cqh_first = (elm); \
else \
(head)->cqh_last->field.cqe_next = (elm); \
(head)->cqh_last = (elm); \
} while (0)
#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \
if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
(head)->cqh_last = (elm)->field.cqe_prev; \
else \
(elm)->field.cqe_next->field.cqe_prev = \
(elm)->field.cqe_prev; \
if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
(head)->cqh_first = (elm)->field.cqe_next; \
else \
(elm)->field.cqe_prev->field.cqe_next = \
(elm)->field.cqe_next; \
} while (0)
#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \
DWC_CIRCLEQ_REMOVE(head, elm, field); \
DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
} while (0)
#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \
if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \
DWC_CIRCLEQ_END(head)) \
(head).cqh_last = (elm2); \
else \
(elm2)->field.cqe_next->field.cqe_prev = (elm2); \
if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \
DWC_CIRCLEQ_END(head)) \
(head).cqh_first = (elm2); \
else \
(elm2)->field.cqe_prev->field.cqe_next = (elm2); \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* _DWC_LIST_H_ */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_list.h
|
C
|
apache-2.0
| 19,974
|
/* =========================================================================
* $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $
* $Revision: #14 $
* $Date: 2010/11/04 $
* $Change: 1621695 $
*
* Synopsys Portability Library Software and documentation
* (hereinafter, "Software") is an Unsupported proprietary work of
* Synopsys, Inc. unless otherwise expressly agreed to in writing
* between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product
* under any End User Software License Agreement or Agreement for
* Licensed Product with Synopsys or any supplement thereto. You are
* permitted to use and redistribute this Software in source and binary
* forms, with or without modification, provided that redistributions
* of source code must retain this notice. You may not view, use,
* disclose, copy or distribute this file or any information contained
* herein except pursuant to this license grant from Synopsys. If you
* do not agree with this notice, including the disclaimer below, then
* you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
* SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================= */
#ifndef _DWC_OS_H_
#define _DWC_OS_H_
#include "basic_types.h"
//#include "va_list.h"
#include <stdarg.h>
#include "diag.h"
#include "dwc_otg_dbg.h"
#include "freertos_service.h"
#ifdef __cplusplus
extern "C" {
#endif
extern
_LONG_CALL_ u32
DiagPrintf(
IN const char *fmt, ...
);
#define DBG_8195A_OTG(...) do{\
if (ConfigDebug[LEVEL_INFO] & BIT(MODULE_USB_OTG)) \
DiagPrintf("\r" __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_INFO(...) do{\
if (ConfigDebug[LEVEL_INFO] & BIT(MODULE_USB_OTG)) \
DiagPrintf("\r" __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_WARN(...) do{\
if (ConfigDebug[LEVEL_WARN] & BIT(MODULE_USB_OTG)) \
DiagPrintf("\r" __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_ERR(...) do{\
if (ConfigDebug[LEVEL_ERROR] & BIT(MODULE_USB_OTG)) \
DiagPrintf("\r" __VA_ARGS__);\
}while(0)
#define DBG_8195A_OTG_LVL(LVL,...) do{\
if (ConfigDebug[LEVEL_INFO] & BIT(MODULE_USB_OTG)){ \
DiagPrintf("\rRTL8195A[OTG_LVL_%2x]: ",LVL);\
DiagPrintf(__VA_ARGS__);\
}\
}while(0)
/** @file
*
* DWC portability library, low level os-wrapper functions
*
*/
/* These basic types need to be defined by some OS header file or custom header
* file for your specific target architecture.
*
* uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
*
* Any custom or alternate header file must be added and enabled here.
*/
#if 0//8195A_PORTING
#else
#define DWC_OS_PORTING 1
#endif
#include "usb_errno.h"
/** @name Primitive Types and Values */
/** We define a boolean type for consistency. Can be either YES or NO */
typedef uint8_t dwc_bool_t;
#define YES 1
#define NO 0
/** Compile Flag Definition */
#define __OTG_LITTLE_ENDIAN
#undef DWC_CRYPTOLIB
#undef DWC_DEBUG_REGS
#undef DWC_DEBUG_MEMORY
#undef DWC_UTFLIB
#undef CONFIG_DEBUG_MUTEXES
#define DWC_WITH_WLAN_OSDEP 1
#ifdef DWC_OS_PORTING
/** @name Error Codes */
#define DWC_E_INVALID EINVAL
#define DWC_E_NO_MEMORY ENOMEM
#define DWC_E_NO_DEVICE ENODEV
#define DWC_E_NOT_SUPPORTED EOPNOTSUPP
#define DWC_E_TIMEOUT ETIMEDOUT
#define DWC_E_BUSY EBUSY
#define DWC_E_AGAIN EAGAIN
#define DWC_E_RESTART ERESTART
#define DWC_E_ABORT ECONNABORTED
#define DWC_E_SHUTDOWN ESHUTDOWN
#define DWC_E_NO_DATA ENODATA
#define DWC_E_DISCONNECT ECONNRESET
#define DWC_E_UNKNOWN EINVAL
#define DWC_E_NO_STREAM_RES ENOSR
#define DWC_E_COMMUNICATION ECOMM
#define DWC_E_OVERFLOW EOVERFLOW
#define DWC_E_PROTOCOL EPROTO
#define DWC_E_IN_PROGRESS EINPROGRESS
#define DWC_E_PIPE EPIPE
#define DWC_E_IO EIO
#define DWC_E_NO_SPACE ENOSPC
#else
/** @name Error Codes */
#define DWC_E_INVALID 1001
#define DWC_E_NO_MEMORY 1002
#define DWC_E_NO_DEVICE 1003
#define DWC_E_NOT_SUPPORTED 1004
#define DWC_E_TIMEOUT 1005
#define DWC_E_BUSY 1006
#define DWC_E_AGAIN 1007
#define DWC_E_RESTART 1008
#define DWC_E_ABORT 1009
#define DWC_E_SHUTDOWN 1010
#define DWC_E_NO_DATA 1011
#define DWC_E_DISCONNECT 2000
#define DWC_E_UNKNOWN 3000
#define DWC_E_NO_STREAM_RES 4001
#define DWC_E_COMMUNICATION 4002
#define DWC_E_OVERFLOW 4003
#define DWC_E_PROTOCOL 4004
#define DWC_E_IN_PROGRESS 4005
#define DWC_E_PIPE 4006
#define DWC_E_IO 4007
#define DWC_E_NO_SPACE 4008
#endif
/** @name Tracing/Logging Functions
*
* These function provide the capability to add tracing, debugging, and error
* messages, as well exceptions as assertions. The WUDEV uses these
* extensively. These could be logged to the main console, the serial port, an
* internal buffer, etc. These functions could also be no-op if they are too
* expensive on your system. By default undefining the DEBUG macro already
* no-ops some of these functions. */
/** Returns non-zero if in interrupt context. */
extern _LONG_CALL_ dwc_bool_t DWC_IN_IRQ(void);
#define dwc_in_irq DWC_IN_IRQ
/** Returns "IRQ" if DWC_IN_IRQ is true. */
extern _LONG_CALL_ char *dwc_irq(void);
/** Returns non-zero if in bottom-half context. */
extern _LONG_CALL_ dwc_bool_t DWC_IN_BH(void);
#define dwc_in_bh DWC_IN_BH
/** Returns "BH" if DWC_IN_BH is true. */
extern _LONG_CALL_ char *dwc_bh(void);
/**
* A vprintf() clone. Just call vprintf if you've got it.
*/
#if 0
extern void DWC_VPRINTF(char *format, va_list args);
#define dwc_vprintf DWC_VPRINTF
#endif
/**
* A vsnprintf() clone. Just call vprintf if you've got it.
*/
extern _LONG_CALL_ int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
#define dwc_vsnprintf DWC_VSNPRINTF
/**
* printf() clone. Just call printf if you've go it.
*/
#ifdef OTGDEBUG
#define DWC_PRINTF(format...) do{ DBG_8195A_OTG(format); }while(0)
#else
#define DWC_PRINTF(format...)
#endif
//extern void DWC_PRINTF(char *format, ...)
/* This provides compiler level static checking of the parameters if you're
* using GCC. */
#if 0
#ifdef __GNUC__
__attribute__ ((format(printf, 1, 2)));
#else
;
#endif
#endif
#define dwc_printf DWC_PRINTF
/**
* sprintf() clone. Just call sprintf if you've got it.
*/
extern _LONG_CALL_ int DWC_SPRINTF(char *string, char *format, ...)
#if 0//def __GNUC__
__attribute__ ((format(prvDiagPrintf, 2, 3)));
#else
;
#endif
#define dwc_sprintf DWC_SPRINTF
/**
* snprintf() clone. Just call snprintf if you've got it.
*/
extern _LONG_CALL_ int DWC_SNPRINTF(char *string, int size, char *format, ...)
#if 0//def __GNUC__
__attribute__ ((format(prvDiagPrintf, 3, 4)));
#else
;
#endif
#define dwc_snprintf DWC_SNPRINTF
/**
* Prints a WARNING message. On systems that don't differentiate between
* warnings and regular log messages, just print it. Indicates that something
* may be wrong with the driver. Works like printf().
*
* Use the DWC_WARN macro to call this function.
*/
extern _LONG_CALL_ void __DWC_WARN(char *format, ...)
#if 0//def __GNUC__
__attribute__ ((format(prvDiagPrintf, 1, 2)));
#else
;
#endif
/**
* Prints an error message. On systems that don't differentiate between errors
* and regular log messages, just print it. Indicates that something went wrong
* with the driver. Works like printf().
*
* Use the DWC_ERROR macro to call this function.
*/
extern _LONG_CALL_ void __DWC_ERROR(char *format, ...)
#if 0//def __GNUC__
__attribute__ ((format(prvDiagPrintf, 1, 2)));
#else
;
#endif
/**
* Prints an exception error message and takes some user-defined action such as
* print out a backtrace or trigger a breakpoint. Indicates that something went
* abnormally wrong with the driver such as programmer error, or other
* exceptional condition. It should not be ignored so even on systems without
* printing capability, some action should be taken to notify the developer of
* it. Works like printf().
*/
extern _LONG_CALL_ void DWC_EXCEPTION(char *format, ...)
#if 0//def __GNUC__
__attribute__ ((format(prvDiagPrintf, 1, 2)));
#else
;
#endif
#define dwc_exception DWC_EXCEPTION
#ifdef OTGDEBUG
/**
* Prints out a debug message. Used for logging/trace messages.
*
* Use the DWC_DEBUG macro to call this function
*/
extern _LONG_CALL_ void __DWC_DEBUG(char *format, ...);
#if 0
#ifdef __GNUC__
__attribute__ ((format(printf, 1, 2)));
#else
;
#endif
#endif
#else
#define __DWC_DEBUG(...)
#endif
/**
* Prints out a Debug message.
*/
#define DWC_DEBUG(fmt, args...) DBG_8195A_OTG("\n\rDWC_DEBUG:" fmt, ## args)
#define dwc_debug DWC_DEBUG
/**
* Prints out an informative message.
*/
#define DWC_INFO(_format, _args...) DBG_8195A_OTG_INFO("INFO:%s: " _format "\n", \
dwc_irq(), ## _args)
#define dwc_info DWC_INFO
/**
* Prints out a warning message.
*/
#define DWC_WARN(_format, _args...) DBG_8195A_OTG_WARN("WARN:%s: " _format "\n", \
dwc_irq(), ## _args)
#define dwc_warn DWC_WARN
/**
* Prints out an error message.
*/
#define DWC_ERROR(_format, _args...) DBG_8195A_OTG_ERR("ERROR:%s: " _format "\n", \
dwc_irq(), ## _args)
#define dwc_error DWC_ERROR
#define DWC_PROTO_ERROR(_format, _args...) DBG_8195A_OTG_ERR("ERROR:%s: " _format "\n", \
dwc_irq(), ## _args)
#define dwc_proto_error DWC_PROTO_ERROR
#ifdef OTGDEBUG
/** Prints out a exception error message if the _expr expression fails. Disabled
* if DEBUG is not enabled. */
#define DWC_ASSERT(_expr, _format, _args...) do { \
if (!(_expr)) { DBG_8195A_OTG("%s: " _format "\n", dwc_irq(), \
## _args); } \
} while (0)
#else
#define DWC_ASSERT(_x...)
#endif
#define dwc_assert DWC_ASSERT
/** @name Byte Ordering
* The following functions are for conversions between processor's byte ordering
* and specific ordering you want.
*/
/** Converts 32 bit data in CPU byte ordering to little endian. */
extern _LONG_CALL_ uint32_t DWC_CPU_TO_LE32(uint32_t *p);
#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
/** Converts 32 bit data in CPU byte orderint to big endian. */
extern _LONG_CALL_ uint32_t DWC_CPU_TO_BE32(uint32_t *p);
#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
/** Converts 32 bit little endian data to CPU byte ordering. */
extern _LONG_CALL_ uint32_t DWC_LE32_TO_CPU(uint32_t *p);
#define dwc_le32_to_cpu DWC_LE32_TO_CPU
/** Converts 32 bit big endian data to CPU byte ordering. */
extern _LONG_CALL_ uint32_t DWC_BE32_TO_CPU(uint32_t *p);
#define dwc_be32_to_cpu DWC_BE32_TO_CPU
/** Converts 16 bit data in CPU byte ordering to little endian. */
extern _LONG_CALL_ uint16_t DWC_CPU_TO_LE16(uint16_t *p);
#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
/** Converts 16 bit data in CPU byte orderint to big endian. */
extern _LONG_CALL_ uint16_t DWC_CPU_TO_BE16(uint16_t *p);
#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
/** Converts 16 bit little endian data to CPU byte ordering. */
extern _LONG_CALL_ uint16_t DWC_LE16_TO_CPU(uint16_t *p);
#define dwc_le16_to_cpu DWC_LE16_TO_CPU
/** Converts 16 bit bi endian data to CPU byte ordering. */
extern _LONG_CALL_ uint16_t DWC_BE16_TO_CPU(uint16_t *p);
#define dwc_be16_to_cpu DWC_BE16_TO_CPU
/** @name Register Read/Write
*
* The following six functions should be implemented to read/write registers of
* 32-bit and 64-bit sizes. All modules use this to read/write register values.
* The reg value is a pointer to the register calculated from the void *base
* variable passed into the driver when it is started. */
/** @cond */
/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the
* register writes. */
#ifdef DWC_OS_PORTING
# ifdef DWC_DEBUG_REGS
XXXX
#define dwc_define_read_write_reg_n(_reg,_container_type) \
static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
return DWC_READ_REG32(&container->regs->_reg[num]); \
} \
static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
&(((uint32_t*)container->regs->_reg)[num]), data); \
DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
}
#define dwc_define_read_write_reg(_reg,_container_type) \
static inline uint32_t dwc_read_##_reg(_container_type *container) { \
return DWC_READ_REG32(&container->regs->_reg); \
} \
static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
DWC_WRITE_REG32(&container->regs->_reg, data); \
}
# else /* DWC_DEBUG_REGS */
#define dwc_define_read_write_reg_n(_reg,_container_type) \
static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
return DWC_READ_REG32(&container->regs->_reg[num]); \
} \
static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
}
#define dwc_define_read_write_reg(_reg,_container_type) \
static inline uint32_t dwc_read_##_reg(_container_type *container) { \
return DWC_READ_REG32(&container->regs->_reg); \
} \
static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
DWC_WRITE_REG32(&container->regs->_reg, data); \
}
# endif /* DWC_DEBUG_REGS */
#endif /* DWC_OS_PORTING */
/** @endcond */
#ifdef DWC_CRYPTOLIB
XXX
/** @name Crypto Functions
*
* These are the low-level cryptographic functions used by the driver. */
/** Perform AES CBC */
extern _LONG_CALL_ int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
#define dwc_aes_cbc DWC_AES_CBC
/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */
extern _LONG_CALL_ void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
#define dwc_random_bytes DWC_RANDOM_BYTES
/** Perform the SHA-256 hash function */
extern _LONG_CALL_ int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
#define dwc_sha256 DWC_SHA256
/** Calculated the HMAC-SHA256 */
extern _LONG_CALL_ int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
#define dwc_hmac_sha256 DWC_HMAC_SHA256
#endif /* DWC_CRYPTOLIB */
/** @name Memory Allocation
*
* These function provide access to memory allocation. There are only 2 DMA
* functions and 3 Regular memory functions that need to be implemented. None
* of the memory debugging routines need to be implemented. The allocation
* routines all ZERO the contents of the memory.
*
* Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.
* This checks for memory leaks, keeping track of alloc/free pairs. It also
* keeps track of how much memory the driver is using at any given time. */
#define DWC_PAGE_SIZE 4096
#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
#define DWC_INVALID_DMA_ADDR 0x0
#ifdef DWC_OS_PORTING
/** Type for a DMA address */
typedef dma_addr_t dwc_dma_t;
#endif
#if 0//defined(DWC_FREEBSD) || defined(DWC_NETBSD)
typedef bus_addr_t dwc_dma_t;
#endif
#if 0//def DWC_FREEBSD
typedef struct dwc_dmactx {
struct device *dev;
bus_dma_tag_t dma_tag;
bus_dmamap_t dma_map;
bus_addr_t dma_paddr;
void *dma_vaddr;
} dwc_dmactx_t;
#endif
#if 0//def DWC_NETBSD
typedef struct dwc_dmactx {
struct device *dev;
bus_dma_tag_t dma_tag;
bus_dmamap_t dma_map;
bus_dma_segment_t segs[1];
int nsegs;
bus_addr_t dma_paddr;
void *dma_vaddr;
} dwc_dmactx_t;
#endif
/* @todo these functions will be added in the future */
#if 0
/**
* Creates a DMA pool from which you can allocate DMA buffers. Buffers
* allocated from this pool will be guaranteed to meet the size, alignment, and
* boundary requirements specified.
*
* @param[in] size Specifies the size of the buffers that will be allocated from
* this pool.
* @param[in] align Specifies the byte alignment requirements of the buffers
* allocated from this pool. Must be a power of 2.
* @param[in] boundary Specifies the N-byte boundary that buffers allocated from
* this pool must not cross.
*
* @returns A pointer to an internal opaque structure which is not to be
* accessed outside of these library functions. Use this handle to specify
* which pools to allocate/free DMA buffers from and also to destroy the pool,
* when you are done with it.
*/
extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
/**
* Destroy a DMA pool. All buffers allocated from that pool must be freed first.
*/
extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
/**
* Allocate a buffer from the specified DMA pool and zeros its contents.
*/
extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
/**
* Free a previously allocated buffer from the DMA pool.
*/
extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
#endif
/** Allocates a DMA capable buffer and zeroes its contents. */
extern _LONG_CALL_ void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
extern _LONG_CALL_ void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
/** Frees a previously allocated buffer. */
extern _LONG_CALL_ void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
/** Allocates a block of memory and zeroes its contents. */
extern _LONG_CALL_ void *__DWC_ALLOC(void *mem_ctx, uint32_t size);
/** Allocates a block of memory and zeroes its contents, in an atomic manner
* which can be used inside interrupt context. The size should be sufficiently
* small, a few KB at most, such that failures are not likely to occur. Can just call
* __DWC_ALLOC if it is atomic. */
extern _LONG_CALL_ void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);
/** Frees a previously allocated buffer. */
extern _LONG_CALL_ void __DWC_FREE(void *mem_ctx, void *addr);
#ifndef DWC_DEBUG_MEMORY
#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)
#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)
#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)
#ifdef DWC_OS_PORTING
#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_)
#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_)
#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_)
#endif
#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
XXX
#define DWC_DMA_ALLOC __DWC_DMA_ALLOC
#define DWC_DMA_FREE __DWC_DMA_FREE
#endif
#else /* DWC_DEBUG_MEMORY */
XXX
extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);
extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);
extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);
extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
char const *func, int line);
extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
char const *func, int line);
extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
dwc_dma_t dma_addr, char const *func, int line);
extern int dwc_memory_debug_start(void *mem_ctx);
extern void dwc_memory_debug_stop(void);
extern void dwc_memory_debug_report(void);
#endif /* DWC_DEBUG_MEMORY */
#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)
#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)
#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)
#ifdef DWC_OS_PORTING
/* Linux doesn't need any extra parameters for DMA buffer allocation, so we
* just throw away the DMA context parameter.
*/
#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)
#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)
#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)
#endif
#if 0//defined(DWC_FREEBSD) || defined(DWC_NETBSD)
/** BSD needs several extra parameters for DMA buffer allocation, so we pass
* them in using the DMA context parameter.
*/
#define dwc_dma_alloc DWC_DMA_ALLOC
#define dwc_dma_free DWC_DMA_FREE
#endif
/** @name Memory and String Processing */
/** memset() clone */
extern _LONG_CALL_ void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
#define dwc_memset DWC_MEMSET
/** memcpy() clone */
extern _LONG_CALL_ void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
#define dwc_memcpy DWC_MEMCPY
/** memmove() clone */
extern _LONG_CALL_ void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
#define dwc_memmove DWC_MEMMOVE
/** memcmp() clone */
extern _LONG_CALL_ int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
#define dwc_memcmp DWC_MEMCMP
/** strcmp() clone */
extern _LONG_CALL_ int DWC_STRCMP(void *s1, void *s2);
#define dwc_strcmp DWC_STRCMP
/** strncmp() clone */
extern _LONG_CALL_ int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
#define dwc_strncmp DWC_STRNCMP
/** strlen() clone, for NULL terminated ASCII strings */
extern _LONG_CALL_ int DWC_STRLEN(char const *str);
#define dwc_strlen DWC_STRLEN
/** strcpy() clone, for NULL terminated ASCII strings */
extern _LONG_CALL_ char *DWC_STRCPY(char *to, const char *from);
#define dwc_strcpy DWC_STRCPY
/** strdup() clone. If you wish to use memory allocation debugging, this
* implementation of strdup should use the DWC_* memory routines instead of
* calling a predefined strdup. Otherwise the memory allocated by this routine
* will not be seen by the debugging routines. */
extern _LONG_CALL_ char *DWC_STRDUP(char const *str);
#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)
/** NOT an atoi() clone. Read the description carefully. Returns an integer
* converted from the string str in base 10 unless the string begins with a "0x"
* in which case it is base 16. String must be a NULL terminated sequence of
* ASCII characters and may optionally begin with whitespace, a + or -, and a
* "0x" prefix if base 16. The remaining characters must be valid digits for
* the number and end with a NULL character. If any invalid characters are
* encountered or it returns with a negative error code and the results of the
* conversion are undefined. On sucess it returns 0. Overflow conditions are
* undefined. An example implementation using atoi() can be referenced from the
* Linux implementation. */
extern _LONG_CALL_ int DWC_ATOI(const char *str, int32_t *value);
#define dwc_atoi DWC_ATOI
/** Same as above but for unsigned. */
extern _LONG_CALL_ int DWC_ATOUI(const char *str, uint32_t *value);
#define dwc_atoui DWC_ATOUI
#ifdef DWC_UTFLIB
XXX
/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
#endif
/** @name Wait queues
*
* Wait queues provide a means of synchronizing between threads or processes. A
* process can block on a waitq if some condition is not true, waiting for it to
* become true. When the waitq is triggered all waiting process will get
* unblocked and the condition will be check again. Waitqs should be triggered
* every time a condition can potentially change.*/
//struct dwc_waitq;
/** Type for a waitq */
//typedef struct dwc_waitq dwc_waitq_t;
/** The type of waitq condition callback function. This is called every time
* condition is evaluated. */
//typedef int (*dwc_waitq_condition_t)(void *data);
/** Allocate a waitq */
//extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
//#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()
/** Free a waitq */
//extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
//#define dwc_waitq_free DWC_WAITQ_FREE
/** Check the condition and if it is false, block on the waitq. When unblocked, check the
* condition again. The function returns when the condition becomes true. The return value
* is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
//extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);
//#define dwc_waitq_wait DWC_WAITQ_WAIT
/** Check the condition and if it is false, block on the waitq. When unblocked,
* check the condition again. The function returns when the condition become
* true or the timeout has passed. The return value is 0 on condition true or
* DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
* error. */
//extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
// void *data, int32_t msecs);
//#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
/** Trigger a waitq, unblocking all processes. This should be called whenever a condition
* has potentially changed. */
//extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
//#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
/** Unblock all processes waiting on the waitq with an ABORTED result. */
//extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
//#define dwc_waitq_abort DWC_WAITQ_ABORT
/** @name Threads
*
* A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP
* whenever it is woken up, and then return. The DWC_THREAD_STOP function
* returns the value from the thread.
*/
/** @name Work queues
*
* Workqs are used to queue a callback function to be called at some later time,
* in another thread. */
//struct dwc_workq;
/** Type for a workq */
typedef struct dwc_workq dwc_workq_t;
/** The type of the callback function to be called. */
//typedef void (*dwc_work_callback_t)(void *data);
/** Allocate a workq */
//extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
//#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)
/** Free a workq. All work must be completed before being freed. */
//extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
//#define dwc_workq_free DWC_WORKQ_FREE
/** Schedule a callback on the workq, passing in data. The function will be
* scheduled at some later time. */
//extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,
// void *data, char *format, ...)
#if 0//def __GNUC__
__attribute__ ((format(printf, 4, 5)));
#else
;
#endif
//#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
/** Schedule a callback on the workq, that will be called until at least
* given number miliseconds have passed. */
//extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,
// void *data, uint32_t time, char *format, ...)
#if 0//def __GNUC__
__attribute__ ((format(printf, 5, 6)));
#else
;
#endif
//#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
/** The number of processes in the workq */
//extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
//#define dwc_workq_pending DWC_WORKQ_PENDING
/** Blocks until all the work in the workq is complete or timed out. Returns <
* 0 on timeout. */
//extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
//#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
/** @name Tasklets
*
*/
//struct dwc_tasklet;
/** Type for a tasklet */
typedef struct dwc_tasklet dwc_tasklet_t;
/** The type of the callback function to be called */
//typedef void (*dwc_tasklet_callback_t)(void *data);
/** Allocates a tasklet */
//extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);
//#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)
/** Frees a tasklet */
//extern void DWC_TASK_FREE(dwc_tasklet_t *task);
//#define dwc_task_free DWC_TASK_FREE
/** Schedules a tasklet to run */
//extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
//#define dwc_task_schedule DWC_TASK_SCHEDULE
/** @name Timer
*
* Callbacks must be small and atomic.
*/
struct dwc_timer;
/** Type for a timer */
typedef struct dwc_timer dwc_timer_t;
/** The type of the callback function to be called */
typedef void (*dwc_timer_callback_t)(void *data);
/** Allocates a timer */
extern _LONG_CALL_ dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)
/** Frees a timer */
extern _LONG_CALL_ void DWC_TIMER_FREE(dwc_timer_t *timer);
#define dwc_timer_free DWC_TIMER_FREE
/** Schedules the timer to run at time ms from now. And will repeat at every
* repeat_interval msec therafter
*
* Modifies a timer that is still awaiting execution to a new expiration time.
* The mod_time is added to the old time. */
extern _LONG_CALL_ void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
#define dwc_timer_schedule DWC_TIMER_SCHEDULE
/** Disables the timer from execution. */
extern _LONG_CALL_ void DWC_TIMER_CANCEL(dwc_timer_t *timer);
#define dwc_timer_cancel DWC_TIMER_CANCEL
/** @name Spinlocks
*
* These locks are used when the work between the lock/unlock is atomic and
* short. Interrupts are also disabled during the lock/unlock and thus they are
* suitable to lock between interrupt/non-interrupt context. They also lock
* between processes if you have multiple CPUs or Preemption. If you don't have
* multiple CPUS or Preemption, then the you can simply implement the
* DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because
* the work between the lock/unlock is atomic, the process context will never
* change, and so you never have to lock between processes. */
struct dwc_spinlock;
/** Type for a spinlock */
//typedef struct dwc_spinlock dwc_spinlock_t;
typedef _lock dwc_spinlock_t;
/** Type for the 'flags' argument to spinlock funtions */
typedef unsigned long dwc_irqflags_t;
/** Returns an initialized lock variable. This function should allocate and
* initialize the OS-specific data structure used for locking. This data
* structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
* be freed by the DWC_FREE_LOCK when it is no longer used. */
extern _LONG_CALL_ dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()
/** Frees an initialized lock variable. */
extern _LONG_CALL_ void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)
/** Disables interrupts and blocks until it acquires the lock.
*
* @param lock Pointer to the spinlock.
* @param flags Unsigned long for irq flags storage.
*/
extern _LONG_CALL_ void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);
#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
/** Re-enables the interrupt and releases the lock.
*
* @param lock Pointer to the spinlock.
* @param flags Unsigned long for irq flags storage. Must be the same as was
* passed into DWC_LOCK.
*/
extern _LONG_CALL_ void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);
#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
/** Blocks until it acquires the lock.
*
* @param lock Pointer to the spinlock.
*/
extern _LONG_CALL_ void DWC_SPINLOCK(dwc_spinlock_t *lock);
#define dwc_spinlock DWC_SPINLOCK
/** Releases the lock.
*
* @param lock Pointer to the spinlock.
*/
extern _LONG_CALL_ void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
#define dwc_spinunlock DWC_SPINUNLOCK
/** @name Mutexes
*
* Unlike spinlocks Mutexes lock only between processes and the work between the
* lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
*/
struct dwc_mutex;
/** Type for a mutex */
typedef struct dwc_mutex dwc_mutex_t;
/* For Linux Mutex Debugging make it inline because the debugging routines use
* the symbol to determine recursive locking. This makes it falsely think
* recursive locking occurs. */
#if defined(DWC_OS_PORTING) && defined(CONFIG_DEBUG_MUTEXES)
#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
__mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
mutex_init((struct mutex *)__mutexp); \
})
#endif
/** Allocate a mutex */
extern _LONG_CALL_ dwc_mutex_t *DWC_MUTEX_ALLOC(void);
#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()
/* For memory leak debugging when using Linux Mutex Debugging */
#if defined(DWC_OS_PORTING) && defined(CONFIG_DEBUG_MUTEXES)
XXX
#define DWC_MUTEX_FREE(__mutexp) do { \
mutex_destroy((struct mutex *)__mutexp); \
DWC_FREE(__mutexp); \
} while(0)
#else
/** Free a mutex */
extern _LONG_CALL_ void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)
#endif
/** Lock a mutex */
extern _LONG_CALL_ void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
#define dwc_mutex_lock DWC_MUTEX_LOCK
/** Non-blocking lock returns 1 on successful lock. */
extern _LONG_CALL_ int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
/** Unlock a mutex */
extern _LONG_CALL_ void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
/** @name Time */
/** Microsecond delay.
*
* @param usecs Microseconds to delay.
*/
extern _LONG_CALL_ void DWC_UDELAY(uint32_t usecs);
#define dwc_udelay DWC_UDELAY
/** Millisecond delay.
*
* @param msecs Milliseconds to delay.
*/
extern _LONG_CALL_ void DWC_MDELAY(uint32_t msecs);
#define dwc_mdelay DWC_MDELAY
/** Non-busy waiting.
* Sleeps for specified number of milliseconds.
*
* @param msecs Milliseconds to sleep.
*/
extern _LONG_CALL_ void DWC_MSLEEP(uint32_t msecs);
#define dwc_msleep DWC_MSLEEP
extern _LONG_CALL_ void DWC_ENTER_CRITICAL(VOID);
extern _LONG_CALL_ void DWC_EXIT_CRITICAL(VOID);
extern _LONG_CALL_ uint8_t DWC_IN_CRITICAL(VOID);
/**
* Returns number of milliseconds since boot.
*/
//extern uint32_t DWC_TIME(void);
//#define dwc_time DWC_TIME
/* @mainpage DWC Portability and Common Library
*
* This is the documentation for the DWC Portability and Common Library.
*
* @section intro Introduction
*
* The DWC Portability library consists of wrapper calls and data structures to
* all low-level functions which are typically provided by the OS. The WUDEV
* driver uses only these functions. In order to port the WUDEV driver, only
* the functions in this library need to be re-implemented, with the same
* behavior as documented here.
*
* The Common library consists of higher level functions, which rely only on
* calling the functions from the DWC Portability library. These common
* routines are shared across modules. Some of the common libraries need to be
* used directly by the driver programmer when porting WUDEV. Such as the
* parameter and notification libraries.
*
* @section low Portability Library OS Wrapper Functions
*
* Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
* needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of
* these functions are included in the dwc_os.h file.
*
* There are many functions here covering a wide array of OS services. Please
* see dwc_os.h for details, and implementation notes for each function.
*
* @section common Common Library Functions
*
* Any function starting with dwc and in all lowercase is a common library
* routine. These functions have a portable implementation and do not need to
* be reimplemented when porting. The common routines can be used by any
* driver, and some must be used by the end user to control the drivers. For
* example, you must use the Parameter common library in order to set the
* parameters in the WUDEV module.
*
* The common libraries consist of the following:
*
* - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h
* - Parameters - Used internally and can be used by end-user. See dwc_params.h
* - Notifications - Used internally and can be used by end-user. See dwc_notifier.h
* - Lists - Used internally and can be used by end-user. See dwc_list.h
* - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h
* - Modpow - Used internally only. See dwc_modpow.h
* - DH - Used internally only. See dwc_dh.h
* - Crypto - Used internally only. See dwc_crypto.h
*
*
* @section prereq Prerequistes For dwc_os.h
* @subsection types Data Types
*
* The dwc_os.h file assumes that several low-level data types are pre defined for the
* compilation environment. These data types are:
*
* - uint8_t - unsigned 8-bit data type
* - int8_t - signed 8-bit data type
* - uint16_t - unsigned 16-bit data type
* - int16_t - signed 16-bit data type
* - uint32_t - unsigned 32-bit data type
* - int32_t - signed 32-bit data type
* - uint64_t - unsigned 64-bit data type
* - int64_t - signed 64-bit data type
*
* Ensure that these are defined before using dwc_os.h. The easiest way to do
* that is to modify the top of the file to include the appropriate header.
* This is already done for the Linux environment. If the DWC_OS_PORTING macro is
* defined, the correct header will be added. A standard header <stdint.h> is
* also used for environments where standard C headers are available.
*
* @subsection stdarg Variable Arguments
*
* Variable arguments are provided by a standard C header <stdarg.h>. it is
* available in Both the Linux and ANSI C enviornment. An equivalent must be
* provided in your enviornment in order to use dwc_os.h with the debug and
* tracing message functionality.
*
* @subsection thread Threading
*
* WUDEV Core must be run on an operating system that provides for multiple
* threads/processes. Threading can be implemented in many ways, even in
* embedded systems without an operating system. At the bare minimum, the
* system should be able to start any number of processes at any time to handle
* special work. It need not be a pre-emptive system. Process context can
* change upon a call to a blocking function. The hardware interrupt context
* that calls the module's ISR() function must be differentiable from process
* context, even if your processes are impemented via a hardware interrupt.
* Further locking mechanism between process must exist (or be implemented), and
* process context must have a way to disable interrupts for a period of time to
* lock them out. If all of this exists, the functions in dwc_os.h related to
* threading should be able to be implemented with the defined behavior.
*
*/
#ifdef __cplusplus
}
#endif
#endif /* _DWC_OS_H_ */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_os.h
|
C
|
apache-2.0
| 39,100
|
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
* $Revision: #8 $
* $Date: 2013/04/09 $
* $Change: 2201932 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_ADP_H__
#define __DWC_OTG_ADP_H__
/**
* @file
*
* This file contains the Attach Detect Protocol interfaces and defines
* (functions) and structures for Linux.
*
*/
#define DWC_OTG_ADP_UNATTACHED 0
#define DWC_OTG_ADP_ATTACHED 1
#define DWC_OTG_ADP_UNKOWN 2
#define HOST_RTIM_THRESHOLD 5
#define DEVICE_RTIM_THRESHOLD 3
typedef struct dwc_otg_adp {
uint32_t adp_started;
uint32_t initial_probe;
int32_t probe_timer_values[2];
uint32_t probe_enabled;
uint32_t sense_enabled;
dwc_timer_t *sense_timer;
uint32_t sense_timer_started;
dwc_timer_t *vbuson_timer;
uint32_t vbuson_timer_started;
uint32_t attached;
uint32_t probe_counter;
uint32_t gpwrdn;
} dwc_otg_adp_t;
/**
* Attach Detect Protocol functions
*/
extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
#endif //__DWC_OTG_ADP_H__
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_adp.h
|
C
|
apache-2.0
| 3,501
|
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
* $Revision: #13 $
* $Date: 2010/06/21 $
* $Change: 1532021 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_ATTR_H__)
#define __DWC_OTG_ATTR_H__
#if 0
/** @file
* This file contains the interface to the Linux device attributes.
*/
extern struct device_attribute dev_attr_regoffset;
extern struct device_attribute dev_attr_regvalue;
extern struct device_attribute dev_attr_mode;
extern struct device_attribute dev_attr_hnpcapable;
extern struct device_attribute dev_attr_srpcapable;
extern struct device_attribute dev_attr_hnp;
extern struct device_attribute dev_attr_srp;
extern struct device_attribute dev_attr_buspower;
extern struct device_attribute dev_attr_bussuspend;
extern struct device_attribute dev_attr_mode_ch_tim_en;
extern struct device_attribute dev_attr_fr_interval;
extern struct device_attribute dev_attr_busconnected;
extern struct device_attribute dev_attr_gotgctl;
extern struct device_attribute dev_attr_gusbcfg;
extern struct device_attribute dev_attr_grxfsiz;
extern struct device_attribute dev_attr_gnptxfsiz;
extern struct device_attribute dev_attr_gpvndctl;
extern struct device_attribute dev_attr_ggpio;
extern struct device_attribute dev_attr_guid;
extern struct device_attribute dev_attr_gsnpsid;
extern struct device_attribute dev_attr_devspeed;
extern struct device_attribute dev_attr_enumspeed;
extern struct device_attribute dev_attr_hptxfsiz;
extern struct device_attribute dev_attr_hprt0;
#ifdef CONFIG_USB_DWC_OTG_LPM
extern struct device_attribute dev_attr_lpm_response;
extern struct device_attribute devi_attr_sleep_status;
#endif
void dwc_otg_attr_create(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif PCI_INTERFACE
struct pci_dev *dev
#endif
);
void dwc_otg_attr_remove(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif PCI_INTERFACE
struct pci_dev *dev
#endif
);
#endif
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_attr.h
|
C
|
apache-2.0
| 3,730
|
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
* $Revision: #128 $
* $Date: 2013/05/16 $
* $Change: 2231774 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_CIL_H__)
#define __DWC_CIL_H__
#include "dwc_list.h"
#include "dwc_otg_dbg.h"
#include "dwc_otg_regs.h"
#include "dwc_otg_core_if.h"
#include "dwc_otg_adp.h"
#include "ameba_otg.h"
#include "ameba_soc.h"
/**
* @file
* This file contains the interface to the Core Interface Layer.
*/
//#define DWC_DEVICE_ONLY 0
#ifdef DWC_UTE_CFI
#define MAX_DMA_DESCS_PER_EP 256
/**
* Enumeration for the data buffer mode
*/
typedef enum _data_buffer_mode {
BM_STANDARD = 0, /* data buffer is in normal mode */
BM_SG = 1, /* data buffer uses the scatter/gather mode */
BM_CONCAT = 2, /* data buffer uses the concatenation mode */
BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */
BM_ALIGN = 4 /* data buffer is in buffer alignment mode */
} data_buffer_mode_e;
#endif //DWC_UTE_CFI
/** Macros defined for DWC OTG HW Release version */
#define OTG_CORE_REV_2_60a 0x4F54260A
#define OTG_CORE_REV_2_71a 0x4F54271A
#define OTG_CORE_REV_2_72a 0x4F54272A
#define OTG_CORE_REV_2_80a 0x4F54280A
#define OTG_CORE_REV_2_81a 0x4F54281A
#define OTG_CORE_REV_2_90a 0x4F54290A
#define OTG_CORE_REV_2_91a 0x4F54291A
#define OTG_CORE_REV_2_92a 0x4F54292A
#define OTG_CORE_REV_2_93a 0x4F54293A
#define OTG_CORE_REV_2_94a 0x4F54294A
#define OTG_CORE_REV_3_00a 0x4F54300A
#define OTG_CORE_REV_3_10a 0x4F54310A
/**
* Information for each ISOC packet.
*/
typedef struct iso_pkt_info {
uint32_t offset;
uint32_t length;
int32_t status;
} iso_pkt_info_t;
/**
* The <code>dwc_ep</code> structure represents the state of a single
* endpoint when acting in device mode. It contains the data items
* needed for an endpoint to be activated and transfer packets.
*/
typedef struct dwc_ep {
/** EP number used for register address lookup */
uint8_t num;
/** EP direction 0 = OUT */
unsigned is_in:1;
/** EP active. */
unsigned active:1;
/**
* Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
* Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
unsigned tx_fifo_num:4;
/** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
unsigned type:2;
#define DWC_OTG_EP_TYPE_CONTROL 0
#define DWC_OTG_EP_TYPE_ISOC 1
#define DWC_OTG_EP_TYPE_BULK 2
#define DWC_OTG_EP_TYPE_INTR 3
/** DATA start PID for INTR and BULK EP */
unsigned data_pid_start:1;
/** Frame (even/odd) for ISOC EP */
unsigned even_odd_frame:1;
/** Max Packet bytes */
unsigned maxpacket:11;
/** Max Transfer size */
uint32_t maxxfer;
/** @name Transfer state */
/** @{ */
/**
* Pointer to the beginning of the transfer buffer -- do not modify
* during transfer.
*/
dwc_dma_t dma_addr;
dwc_dma_t dma_desc_addr;
dwc_otg_dev_dma_desc_t *desc_addr;
/* Additional desc chain for ISO transfers */
dwc_dma_t dma_desc_addr1;
dwc_otg_dev_dma_desc_t *desc_addr1;
/* Flag indicating which one of two ISO desc chains currently is in use */
uint8_t use_add_buf;
uint8_t *start_xfer_buff;
/** pointer to the transfer buffer */
uint8_t *xfer_buff;
/** Number of bytes to transfer */
unsigned xfer_len:19;
/** Number of bytes transferred. */
unsigned xfer_count:19;
/** Sent ZLP */
unsigned sent_zlp:1;
/** Total len for control transfer */
unsigned total_len:19;
/** stall clear flag */
unsigned stall_clear_flag:1;
/** SETUP pkt cnt rollover flag for EP0 out*/
unsigned stp_rollover;
#ifdef DWC_UTE_CFI
/* The buffer mode */
data_buffer_mode_e buff_mode;
/* The chain of DMA descriptors.
* MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
*/
dwc_otg_dma_desc_t *descs;
/* The DMA address of the descriptors chain start */
dma_addr_t descs_dma_addr;
/** This variable stores the length of the last enqueued request */
uint32_t cfi_req_len;
#endif //DWC_UTE_CFI
/** Max DMA Descriptor count for any EP */
#define MAX_DMA_DESC_CNT 256
/** Allocated DMA Desc count */
uint32_t desc_cnt;
/** First ISO Desc in use in the first chain*/
uint32_t iso_desc_first;
/** Last ISO Desc in use in the second chain */
uint32_t iso_desc_second;
/** Flag indicated that iso transfers were started */
uint8_t iso_transfer_started;
/** bInterval */
uint32_t bInterval;
/** Next frame num to setup next ISOC transfer */
uint32_t frame_num;
/** Indicates SOF number overrun in DSTS */
uint8_t frm_overrun;
#ifdef DWC_UTE_PER_IO
/** Next frame num for which will be setup DMA Desc */
uint32_t xiso_frame_num;
/** bInterval */
uint32_t xiso_bInterval;
/** Count of currently active transfers - shall be either 0 or 1 */
int xiso_active_xfers;
int xiso_queued_xfers;
#endif
#ifdef DWC_EN_ISOC
/**
* Variables specific for ISOC EPs
*
*/
/** DMA addresses of ISOC buffers */
dwc_dma_t dma_addr0;
dwc_dma_t dma_addr1;
dwc_dma_t iso_dma_desc_addr;
dwc_otg_dev_dma_desc_t *iso_desc_addr;
/** pointer to the transfer buffers */
uint8_t *xfer_buff0;
uint8_t *xfer_buff1;
/** number of ISOC Buffer is processing */
uint32_t proc_buf_num;
/** Interval of ISOC Buffer processing */
uint32_t buf_proc_intrvl;
/** Data size for regular frame */
uint32_t data_per_frame;
uint32_t data_per_frame1;
/* todo - pattern data support is to be implemented in the future */
/** Data size for pattern frame */
uint32_t data_pattern_frame;
/** Frame number of pattern data */
uint32_t sync_frame;
/** bInterval */
//uint32_t bInterval;
/** ISO Packet number per frame */
uint32_t pkt_per_frm;
/** Next frame num for which will be setup DMA Desc */
uint32_t next_frame;
/** Number of packets per buffer processing */
uint32_t pkt_cnt;
/** Info for all isoc packets */
iso_pkt_info_t *pkt_info;
/** current pkt number */
uint32_t cur_pkt;
/** current pkt number */
uint8_t *cur_pkt_addr;
/** current pkt number */
uint32_t cur_pkt_dma_addr;
#endif /* DWC_EN_ISOC */
/** @} */
} dwc_ep_t;
/*
* Reasons for halting a host channel.
*/
typedef enum dwc_otg_halt_status {
DWC_OTG_HC_XFER_NO_HALT_STATUS,
DWC_OTG_HC_XFER_COMPLETE,
DWC_OTG_HC_XFER_URB_COMPLETE,
DWC_OTG_HC_XFER_ACK,
DWC_OTG_HC_XFER_NAK,
DWC_OTG_HC_XFER_NYET,
DWC_OTG_HC_XFER_STALL,
DWC_OTG_HC_XFER_XACT_ERR,
DWC_OTG_HC_XFER_FRAME_OVERRUN,
DWC_OTG_HC_XFER_BABBLE_ERR,
DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
DWC_OTG_HC_XFER_AHB_ERR,
DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
DWC_OTG_HC_XFER_URB_DEQUEUE
} dwc_otg_halt_status_e;
/**
* Host channel descriptor. This structure represents the state of a single
* host channel when acting in host mode. It contains the data items needed to
* transfer packets to an endpoint via a host channel.
*/
typedef struct dwc_hc {
/** Host channel number used for register address lookup */
uint8_t hc_num;
/** Device to access */
unsigned dev_addr:7;
/** EP to access */
unsigned ep_num:4;
/** EP direction. 0: OUT, 1: IN */
unsigned ep_is_in:1;
/**
* EP speed.
* One of the following values:
* - DWC_OTG_EP_SPEED_LOW
* - DWC_OTG_EP_SPEED_FULL
* - DWC_OTG_EP_SPEED_HIGH
*/
unsigned speed:2;
#define DWC_OTG_EP_SPEED_LOW 0
#define DWC_OTG_EP_SPEED_FULL 1
#define DWC_OTG_EP_SPEED_HIGH 2
/**
* Endpoint type.
* One of the following values:
* - DWC_OTG_EP_TYPE_CONTROL: 0
* - DWC_OTG_EP_TYPE_ISOC: 1
* - DWC_OTG_EP_TYPE_BULK: 2
* - DWC_OTG_EP_TYPE_INTR: 3
*/
unsigned ep_type:2;
/** Max packet size in bytes */
unsigned max_packet:11;
/**
* PID for initial transaction.
* 0: DATA0,<br>
* 1: DATA2,<br>
* 2: DATA1,<br>
* 3: MDATA (non-Control EP),
* SETUP (Control EP)
*/
unsigned data_pid_start:2;
#define DWC_OTG_HC_PID_DATA0 0
#define DWC_OTG_HC_PID_DATA2 1
#define DWC_OTG_HC_PID_DATA1 2
#define DWC_OTG_HC_PID_MDATA 3
#define DWC_OTG_HC_PID_SETUP 3
/** Number of periodic transactions per (micro)frame */
unsigned multi_count:2;
/** @name Transfer State */
/** @{ */
/** Pointer to the current transfer buffer position. */
uint8_t *xfer_buff;
/**
* In Buffer DMA mode this buffer will be used
* if xfer_buff is not DWORD aligned.
*/
dwc_dma_t align_buff;
/** Total number of bytes to transfer. */
uint32_t xfer_len;
/** Number of bytes transferred so far. */
uint32_t xfer_count;
/** Packet count at start of transfer.*/
uint16_t start_pkt_count;
/**
* Flag to indicate whether the transfer has been started. Set to 1 if
* it has been started, 0 otherwise.
*/
uint8_t xfer_started;
/**
* Set to 1 to indicate that a PING request should be issued on this
* channel. If 0, process normally.
*/
uint8_t do_ping;
/**
* Set to 1 to indicate that the error count for this transaction is
* non-zero. Set to 0 if the error count is 0.
*/
uint8_t error_state;
/**
* Set to 1 to indicate that this channel should be halted the next
* time a request is queued for the channel. This is necessary in
* slave mode if no request queue space is available when an attempt
* is made to halt the channel.
*/
uint8_t halt_on_queue;
/**
* Set to 1 if the host channel has been halted, but the core is not
* finished flushing queued requests. Otherwise 0.
*/
uint8_t halt_pending;
/**
* Reason for halting the host channel.
*/
dwc_otg_halt_status_e halt_status;
/*
* Split settings for the host channel
*/
uint8_t do_split; /**< Enable split for the channel */
uint8_t complete_split; /**< Enable complete split */
uint8_t hub_addr; /**< Address of high speed hub */
uint8_t port_addr; /**< Port of the low/full speed device */
/** Split transaction position
* One of the following values:
* - DWC_HCSPLIT_XACTPOS_MID
* - DWC_HCSPLIT_XACTPOS_BEGIN
* - DWC_HCSPLIT_XACTPOS_END
* - DWC_HCSPLIT_XACTPOS_ALL */
uint8_t xact_pos;
/** Set when the host channel does a short read. */
uint8_t short_read;
/**
* Number of requests issued for this channel since it was assigned to
* the current transfer (not counting PINGs).
*/
uint8_t requests;
/**
* Queue Head for the transfer being processed by this channel.
*/
struct dwc_otg_qh *qh;
/** @} */
/** Entry in list of host channels. */
DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
/** @name Descriptor DMA support */
/** @{ */
/** Number of Transfer Descriptors */
uint16_t ntd;
/** Descriptor List DMA address */
dwc_dma_t desc_list_addr;
/** Scheduling micro-frame bitmap. */
uint8_t schinfo;
/** @} */
} dwc_hc_t;
/**
* The following parameters may be specified when starting the module. These
* parameters define how the DWC_otg controller should be configured.
*/
typedef struct dwc_otg_core_params {
int32_t opt;
/**
* Specifies the OTG capabilities. The driver will automatically
* detect the value for this parameter if none is specified.
* 0 - HNP and SRP capable (default)
* 1 - SRP Only capable
* 2 - No HNP/SRP capable
*/
int32_t otg_cap;
/**
* Specifies whether to use slave or DMA mode for accessing the data
* FIFOs. The driver will automatically detect the value for this
* parameter if none is specified.
* 0 - Slave
* 1 - DMA (default, if available)
*/
int32_t dma_enable;
/**
* When DMA mode is enabled specifies whether to use address DMA or DMA
* Descriptor mode for accessing the data FIFOs in device mode. The driver
* will automatically detect the value for this if none is specified.
* 0 - address DMA
* 1 - DMA Descriptor(default, if available)
*/
int32_t dma_desc_enable;
/** The DMA Burst size (applicable only for External DMA
* Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
*/
int32_t dma_burst_size; /* Translate this to GAHBCFG values */
/**
* Specifies the maximum speed of operation in host and device mode.
* The actual speed depends on the speed of the attached device and
* the value of phy_type. The actual speed depends on the speed of the
* attached device.
* 0 - High Speed (default)
* 1 - Full Speed
*/
int32_t speed;
/** Specifies whether low power mode is supported when attached
* to a Full Speed or Low Speed device in host mode.
* 0 - Don't support low power mode (default)
* 1 - Support low power mode
*/
int32_t host_support_fs_ls_low_power;
/** Specifies the PHY clock rate in low power mode when connected to a
* Low Speed device in host mode. This parameter is applicable only if
* HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
* then defaults to 6 MHZ otherwise 48 MHZ.
*
* 0 - 48 MHz
* 1 - 6 MHz
*/
int32_t host_ls_low_power_phy_clk;
/**
* 0 - Use cC FIFO size parameters
* 1 - Allow dynamic FIFO sizing (default)
*/
int32_t enable_dynamic_fifo;
/** Total number of 4-byte words in the data FIFO memory. This
* memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
* Tx FIFOs.
* 32 to 32768 (default 8192)
* Note: The total FIFO memory depth in the FPGA configuration is 8192.
*/
int32_t data_fifo_size;
/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1064)
*/
int32_t dev_rx_fifo_size;
/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
* when dynamic FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t dev_nperio_tx_fifo_size;
/** Number of 4-byte words in each of the periodic Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t host_rx_fifo_size;
/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
* when Dynamic FIFO sizing is enabled in the core.
* 16 to 32768 (default 1024)
*/
int32_t host_nperio_tx_fifo_size;
/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
int32_t host_perio_tx_fifo_size;
/** The maximum transfer size supported in bytes.
* 2047 to 65,535 (default 65,535)
*/
int32_t max_transfer_size;
/** The maximum number of packets in a transfer.
* 15 to 511 (default 511)
*/
int32_t max_packet_count;
/** The number of host channel registers to use.
* 1 to 16 (default 12)
* Note: The FPGA configuration supports a maximum of 12 host channels.
*/
int32_t host_channels;
/** The number of endpoints in addition to EP0 available for device
* mode operations.
* 1 to 15 (default 6 IN and OUT)
* Note: The FPGA configuration supports a maximum of 6 IN and OUT
* endpoints in addition to EP0.
*/
int32_t dev_endpoints;
/**
* Specifies the type of PHY interface to use. By default, the driver
* will automatically detect the phy_type.
*
* 0 - Full Speed PHY
* 1 - UTMI+ (default)
* 2 - ULPI
*/
int32_t phy_type;
/**
* Specifies the UTMI+ Data Width. This parameter is
* applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
* PHY_TYPE, this parameter indicates the data width between
* the MAC and the ULPI Wrapper.) Also, this parameter is
* applicable only if the OTG_HSPHY_WIDTH cC parameter was set
* to "8 and 16 bits", meaning that the core has been
* configured to work at either data path width.
*
* 8 or 16 bits (default 16)
*/
int32_t phy_utmi_width;
/**
* Specifies whether the ULPI operates at double or single
* data rate. This parameter is only applicable if PHY_TYPE is
* ULPI.
*
* 0 - single data rate ULPI interface with 8 bit wide data
* bus (default)
* 1 - double data rate ULPI interface with 4 bit wide data
* bus
*/
int32_t phy_ulpi_ddr;
/**
* Specifies whether to use the internal or external supply to
* drive the vbus with a ULPI phy.
*/
int32_t phy_ulpi_ext_vbus;
/**
* Specifies whether to use the I2Cinterface for full speed PHY. This
* parameter is only applicable if PHY_TYPE is FS.
* 0 - No (default)
* 1 - Yes
*/
int32_t i2c_enable;
int32_t ulpi_fs_ls;
int32_t ts_dline;
/**
* Specifies whether dedicated transmit FIFOs are
* enabled for non periodic IN endpoints in device mode
* 0 - No
* 1 - Yes
*/
int32_t en_multiple_tx_fifo;
/** Number of 4-byte words in each of the Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
/** Thresholding enable flag-
* bit 0 - enable non-ISO Tx thresholding
* bit 1 - enable ISO Tx thresholding
* bit 2 - enable Rx thresholding
*/
uint32_t thr_ctl;
/** Thresholding length for Tx
* FIFOs in 32 bit DWORDs
*/
uint32_t tx_thr_length;
/** Thresholding length for Rx
* FIFOs in 32 bit DWORDs
*/
uint32_t rx_thr_length;
/**
* Specifies whether LPM (Link Power Management) support is enabled
*/
int32_t lpm_enable;
/**
* Specifies whether LPM Errata (Link Power Management) support is enabled
*/
int32_t besl_enable;
/**
* Specifies the baseline besl value
*/
int32_t baseline_besl;
/**
* Specifies the deep besl value
*/
int32_t deep_besl;
/** Per Transfer Interrupt
* mode enable flag
* 1 - Enabled
* 0 - Disabled
*/
int32_t pti_enable;
/** Multi Processor Interrupt
* mode enable flag
* 1 - Enabled
* 0 - Disabled
*/
int32_t mpi_enable;
/** IS_USB Capability
* 1 - Enabled
* 0 - Disabled
*/
int32_t ic_usb_cap;
/** AHB Threshold Ratio
* 2'b00 AHB Threshold = MAC Threshold
* 2'b01 AHB Threshold = 1/2 MAC Threshold
* 2'b10 AHB Threshold = 1/4 MAC Threshold
* 2'b11 AHB Threshold = 1/8 MAC Threshold
*/
int32_t ahb_thr_ratio;
/** ADP Support
* 1 - Enabled
* 0 - Disabled
*/
int32_t adp_supp_enable;
/** HFIR Reload Control
* 0 - The HFIR cannot be reloaded dynamically.
* 1 - Allow dynamic reloading of the HFIR register during runtime.
*/
int32_t reload_ctl;
/** DCFG: Enable device Out NAK
* 0 - The core does not set NAK after Bulk Out transfer complete.
* 1 - The core sets NAK after Bulk OUT transfer complete.
*/
int32_t dev_out_nak;
/** DCFG: Enable Continue on BNA
* After receiving BNA interrupt the core disables the endpoint,when the
* endpoint is re-enabled by the application the core starts processing
* 0 - from the DOEPDMA descriptor
* 1 - from the descriptor which received the BNA.
*/
int32_t cont_on_bna;
/** GAHBCFG: AHB Single Support
* This bit when programmed supports SINGLE transfers for remainder
* data in a transfer for DMA mode of operation.
* 0 - in this case the remainder data will be sent using INCR burst size.
* 1 - in this case the remainder data will be sent using SINGLE burst size.
*/
int32_t ahb_single;
/** Core Power down mode
* 0 - No Power Down is enabled
* 1 - Reserved
* 2 - Complete Power Down (Hibernation)
*/
int32_t power_down;
/** OTG revision supported
* 0 - OTG 1.3 revision
* 1 - OTG 2.0 revision
*/
int32_t otg_ver;
} dwc_otg_core_params_t;
#ifdef OTGDEBUG
struct dwc_otg_core_if;
typedef struct hc_xfer_info {
struct dwc_otg_core_if *core_if;
dwc_hc_t *hc;
} hc_xfer_info_t;
#endif
typedef struct ep_xfer_info {
struct dwc_otg_core_if *core_if;
dwc_ep_t *ep;
uint8_t state;
} ep_xfer_info_t;
/*
* Device States
*/
typedef enum dwc_otg_lx_state {
/** On state */
DWC_OTG_L0,
/** LPM sleep state*/
DWC_OTG_L1,
/** USB suspend state*/
DWC_OTG_L2,
/** Off state*/
DWC_OTG_L3
} dwc_otg_lx_state_e;
struct dwc_otg_global_regs_backup {
uint32_t gotgctl_local;
uint32_t gintmsk_local;
uint32_t gahbcfg_local;
uint32_t gusbcfg_local;
uint32_t grxfsiz_local;
uint32_t gnptxfsiz_local;
#ifdef CONFIG_USB_DWC_OTG_LPM
uint32_t glpmcfg_local;
#endif
uint32_t gi2cctl_local;
uint32_t hptxfsiz_local;
uint32_t pcgcctl_local;
uint32_t gdfifocfg_local;
uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
uint32_t gpwrdn_local;
uint32_t xhib_pcgcctl;
uint32_t xhib_gpwrdn;
};
struct dwc_otg_host_regs_backup {
uint32_t hcfg_local;
uint32_t haintmsk_local;
uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
uint32_t hprt0_local;
uint32_t hfir_local;
};
struct dwc_otg_dev_regs_backup {
uint32_t dcfg;
uint32_t dctl;
uint32_t daintmsk;
uint32_t diepmsk;
uint32_t doepmsk;
uint32_t diepctl[MAX_EPS_CHANNELS];
uint32_t dieptsiz[MAX_EPS_CHANNELS];
uint32_t diepdma[MAX_EPS_CHANNELS];
};
/**
* The <code>dwc_otg_core_if</code> structure contains information needed to manage
* the DWC_otg controller acting in either host or device mode. It
* represents the programming view of the controller as a whole.
*/
struct dwc_otg_core_if {
/** Parameters that define how the core should be configured.*/
dwc_otg_core_params_t *core_params;
/** Core Global registers starting at offset 000h. */
dwc_otg_core_global_regs_t *core_global_regs;
/** Device-specific information */
dwc_otg_dev_if_t *dev_if;
/** Host-specific information */
dwc_otg_host_if_t *host_if;
/** Value from SNPSID register */
uint32_t snpsid;
/*
* Set to 1 if the core PHY interface bits in USBCFG have been
* initialized.
*/
uint8_t phy_init_done;
/*
* SRP Success flag, set by srp success interrupt in FS I2C mode
*/
uint8_t srp_success;
uint8_t srp_timer_started;
/** Timer for SRP. If it expires before SRP is successful
* clear the SRP. */
dwc_timer_t *srp_timer;
#ifdef DWC_DEV_SRPCAP
/* This timer is needed to power on the hibernated host core if SRP is not
* initiated on connected SRP capable device for limited period of time
*/
uint8_t pwron_timer_started;
dwc_timer_t *pwron_timer;
#endif
/* Common configuration information */
/** Power and Clock Gating Control Register */
volatile uint32_t *pcgcctl;
#define DWC_OTG_PCGCCTL_OFFSET 0xE00
/** Push/pop addresses for endpoints or host channels.*/
uint32_t *data_fifo[MAX_EPS_CHANNELS];
#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
#define DWC_OTG_DATA_FIFO_SIZE 0x1000
/** Total RAM for FIFOs (Bytes) */
uint16_t total_fifo_size;
/** Size of Rx FIFO (Bytes) */
uint16_t rx_fifo_size;
/** Size of Non-periodic Tx FIFO (Bytes) */
uint16_t nperio_tx_fifo_size;
/** 1 if DMA is enabled, 0 otherwise. */
uint8_t dma_enable;
/** 1 if DMA descriptor is enabled, 0 otherwise. */
uint8_t dma_desc_enable;
/** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
uint8_t pti_enh_enable;
/** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
uint8_t multiproc_int_enable;
/** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
uint8_t en_multiple_tx_fifo;
/** Set to 1 if multiple packets of a high-bandwidth transfer is in
* process of being queued */
uint8_t queuing_high_bandwidth;
/** Hardware Configuration -- stored here for convenience.*/
hwcfg1_data_t hwcfg1;
hwcfg2_data_t hwcfg2;
hwcfg3_data_t hwcfg3;
hwcfg4_data_t hwcfg4;
fifosize_data_t hptxfsiz;
/** Host and Device Configuration -- stored here for convenience.*/
hcfg_data_t hcfg;
dcfg_data_t dcfg;
/** The operational State, during transations
* (a_host>>a_peripherial and b_device=>b_host) this may not
* match the core but allows the software to determine
* transitions.
*/
uint8_t op_state;
/** Test mode for PET testing */
uint8_t test_mode;
/**
* Set to 1 if the HCD needs to be restarted on a session request
* interrupt. This is required if no connector ID status change has
* occurred since the HCD was last disconnected.
*/
uint8_t restart_hcd_on_session_req;
/** HCD callbacks */
/** A-Device is a_host */
#define A_HOST (1)
/** A-Device is a_suspend */
#define A_SUSPEND (2)
/** A-Device is a_peripherial */
#define A_PERIPHERAL (3)
/** B-Device is operating as a Peripheral. */
#define B_PERIPHERAL (4)
/** B-Device is operating as a Host. */
#define B_HOST (5)
/** HCD callbacks */
struct dwc_otg_cil_callbacks *hcd_cb;
/** PCD callbacks */
struct dwc_otg_cil_callbacks *pcd_cb;
/** Device mode Periodic Tx FIFO Mask */
uint32_t p_tx_msk;
/** Device mode Periodic Tx FIFO Mask */
uint32_t tx_msk;
/** Workqueue object used for handling several interrupts */
dwc_workq_t *wq_otg;
/** Timer object used for handling "Wakeup Detected" Interrupt */
dwc_timer_t *wkp_timer;
/** This arrays used for debug purposes for DEV OUT NAK enhancement */
uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
#ifdef OTGDEBUG
uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
uint32_t hfnum_7_samples;
uint64_t hfnum_7_frrem_accum;
uint32_t hfnum_0_samples;
uint64_t hfnum_0_frrem_accum;
uint32_t hfnum_other_samples;
uint64_t hfnum_other_frrem_accum;
#endif
#ifdef DWC_UTE_CFI
uint16_t pwron_rxfsiz;
uint16_t pwron_gnptxfsiz;
uint16_t pwron_txfsiz[15];
uint16_t init_rxfsiz;
uint16_t init_gnptxfsiz;
uint16_t init_txfsiz[15];
#endif
/** Lx state of device */
dwc_otg_lx_state_e lx_state;
/** Saved Core Global registers */
struct dwc_otg_global_regs_backup *gr_backup;
/** Saved Host registers */
struct dwc_otg_host_regs_backup *hr_backup;
/** Saved Device registers */
struct dwc_otg_dev_regs_backup *dr_backup;
/** Power Down Enable */
uint32_t power_down;
/** ADP support Enable */
uint32_t adp_enable;
/** ADP structure object */
dwc_otg_adp_t adp;
/** hibernation/suspend flag */
int hibernation_suspend;
/** Device mode extended hibernation flag */
int xhib;
/** OTG revision supported */
uint32_t otg_ver;
/** OTG status flag used for HNP polling */
uint8_t otg_sts;
/** Pointer to either hcd->lock or pcd->lock */
dwc_spinlock_t *lock;
/** Start predict NextEP based on Learning Queue if equal 1,
* also used as counter of disabled NP IN EP's */
uint8_t start_predict;
/** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
* active, 0xff otherwise */
uint8_t nextep_seq[MAX_EPS_CHANNELS];
/** Index of fisrt EP in nextep_seq array which should be re-enabled **/
uint8_t first_in_nextep_seq;
/** Frame number while entering to ISR - needed for ISOCs **/
uint32_t frame_num;
/** Flag to not perform ADP probing if IDSTS event happened */
uint8_t stop_adpprb;
};
#ifdef OTGDEBUG
/*
* This function is called when transfer is timed out.
*/
extern _LONG_CALL_ void hc_xfer_timeout(void *ptr);
#endif
/*
* This function is called when transfer is timed out on endpoint.
*/
extern _LONG_CALL_ void ep_xfer_timeout(void *ptr);
/*
* The following functions are functions for works
* using during handling some interrupts
*/
extern _LONG_CALL_ void w_conn_id_status_change(void *p);
extern _LONG_CALL_ void w_wakeup_detected(void *p);
/** Saves global register values into system memory. */
extern _LONG_CALL_ int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
/** Saves device register values into system memory. */
extern _LONG_CALL_ int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
/** Saves host register values into system memory. */
extern _LONG_CALL_ int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
/** Restore global register values. */
extern _LONG_CALL_ int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
/** Restore host register values. */
extern _LONG_CALL_ int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
/** Restore device register values. */
extern _LONG_CALL_ int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
int rem_wakeup);
extern _LONG_CALL_ int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
int is_host);
extern _LONG_CALL_ int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
int restore_mode, int reset);
extern _LONG_CALL_ int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
int rem_wakeup, int reset);
/*
* The following functions support initialization of the CIL driver component
* and the DWC_otg controller.
*/
extern _LONG_CALL_ void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
/** @name Device CIL Functions
* The following functions support managing the DWC_otg controller in device
* mode.
*/
/**@{*/
extern _LONG_CALL_ void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
uint32_t * _dest);
extern _LONG_CALL_ uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
extern _LONG_CALL_ void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
extern _LONG_CALL_ void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
extern _LONG_CALL_ void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
dwc_ep_t * _ep);
extern _LONG_CALL_ void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
dwc_ep_t * _ep);
extern _LONG_CALL_ void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
dwc_ep_t * _ep);
extern _LONG_CALL_ void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
dwc_ep_t * _ep);
extern _LONG_CALL_ void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
dwc_ep_t * _ep, int _dma);
extern _LONG_CALL_ void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
extern _LONG_CALL_ void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
dwc_ep_t * _ep);
extern _LONG_CALL_ void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
#ifdef DWC_EN_ISOC
extern _LONG_CALL_ void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
dwc_ep_t * ep);
extern _LONG_CALL_ void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
dwc_ep_t * ep);
#endif /* DWC_EN_ISOC */
/**@}*/
/** @name Host CIL Functions
* The following functions support managing the DWC_otg controller in host
* mode.
*/
/**@{*/
extern _LONG_CALL_ void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
extern _LONG_CALL_ void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
extern _LONG_CALL_ void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
extern _LONG_CALL_ void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
dwc_hc_t * _hc);
extern _LONG_CALL_ int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
dwc_hc_t * _hc);
extern _LONG_CALL_ void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
extern _LONG_CALL_ void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
dwc_hc_t * _hc);
extern _LONG_CALL_ void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
dwc_hc_t * hc);
extern _LONG_CALL_ uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ int dwc_otg_check_haps_status(dwc_otg_core_if_t * core_if);
/* Macro used to clear one channel interrupt */
#define clear_hc_int(_hc_regs_, _intr_) \
do { \
hcint_data_t hcint_clear = {.d32 = 0}; \
hcint_clear.b._intr_ = 1; \
DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
} while (0)
/*
* Macro used to disable one channel interrupt. Channel interrupts are
* disabled when the channel is halted or released by the interrupt handler.
* There is no need to handle further interrupts of that type until the
* channel is re-assigned. In fact, subsequent handling may cause crashes
* because the channel structures are cleaned up when the channel is released.
*/
#define disable_hc_int(_hc_regs_, _intr_) \
do { \
hcintmsk_data_t hcintmsk = {.d32 = 0}; \
hcintmsk.b._intr_ = 1; \
DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
} while (0)
/**
* This function Reads HPRT0 in preparation to modify. It keeps the
* WC bits 0 so that if they are read as 1, they won't clear when you
* write it back
*/
extern _LONG_CALL_ uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if);
/**@}*/
/** @name Common CIL Functions
* The following functions support managing the DWC_otg controller in either
* device or host mode.
*/
/**@{*/
extern _LONG_CALL_ void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
uint8_t * dest, uint16_t bytes);
extern _LONG_CALL_ void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
extern _LONG_CALL_ void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
/**
* This function returns the Core Interrupt register.
*/
extern _LONG_CALL_ uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if);
/**
* This function returns the OTG Interrupt register.
*/
extern _LONG_CALL_ uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if);
/**
* This function reads the Device All Endpoints Interrupt register and
* returns the IN endpoint interrupt bits.
*/
extern _LONG_CALL_ uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
core_if);
/**
* This function reads the Device All Endpoints Interrupt register and
* returns the OUT endpoint interrupt bits.
*/
extern _LONG_CALL_ uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
core_if);
/**
* This function returns the Device IN EP Interrupt register
*/
extern _LONG_CALL_ uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
dwc_ep_t * ep);
/**
* This function returns the Device OUT EP Interrupt register
*/
extern _LONG_CALL_ uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
_core_if, dwc_ep_t * _ep);
/**
* This function returns the Host All Channel Interrupt register
*/
extern _LONG_CALL_ uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
_core_if);
extern _LONG_CALL_ uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
_core_if, dwc_hc_t * _hc);
/**
* This function returns the mode of the operation, host or device.
*
* @return 0 - Device Mode, 1 - Host Mode
*/
extern _LONG_CALL_ uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if);
/**@}*/
/**
* DWC_otg CIL callback structure. This structure allows the HCD and
* PCD to register functions used for starting and stopping the PCD
* and HCD for role change on for a DRD.
*/
typedef struct dwc_otg_cil_callbacks {
/** Start function for role change */
int (*start) (void *_p);
/** Stop Function for role change */
int (*stop) (void *_p);
/** Disconnect Function for role change */
int (*disconnect) (void *_p);
/** Resume/Remote wakeup Function */
int (*resume_wakeup) (void *_p);
/** Suspend function */
int (*suspend) (void *_p);
/** Session Start (SRP) */
int (*session_start) (void *_p);
#ifdef CONFIG_USB_DWC_OTG_LPM
/** Sleep (switch to L0 state) */
int (*sleep) (void *_p);
#endif
/** Pointer passed to start() and stop() */
void *p;
} dwc_otg_cil_callbacks_t;
extern _LONG_CALL_ void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
dwc_otg_cil_callbacks_t * _cb,
void *_p);
extern _LONG_CALL_ void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
dwc_otg_cil_callbacks_t * _cb,
void *_p);
extern _LONG_CALL_ void dwc_otg_initiate_srp(void * core_if);
//////////////////////////////////////////////////////////////////////
/** Start the HCD. Helper function for using the HCD callbacks.
*
* @param core_if Programming view of DWC_otg controller.
*/
extern _LONG_CALL_ void cil_hcd_start(dwc_otg_core_if_t * core_if);
/** Stop the HCD. Helper function for using the HCD callbacks.
*
* @param core_if Programming view of DWC_otg controller.
*/
extern _LONG_CALL_ void cil_hcd_stop(dwc_otg_core_if_t * core_if);
/** Disconnect the HCD. Helper function for using the HCD callbacks.
*
* @param core_if Programming view of DWC_otg controller.
*/
extern _LONG_CALL_ void cil_hcd_disconnect(dwc_otg_core_if_t * core_if);
/** Inform the HCD the a New Session has begun. Helper function for
* using the HCD callbacks.
*
* @param core_if Programming view of DWC_otg controller.
*/
extern _LONG_CALL_ void cil_hcd_session_start(dwc_otg_core_if_t * core_if);
#ifdef CONFIG_USB_DWC_OTG_LPM
/**
* Inform the HCD about LPM sleep.
* Helper function for using the HCD callbacks.
*
* @param core_if Programming view of DWC_otg controller.
*/
extern _LONG_CALL_ void cil_hcd_sleep(dwc_otg_core_if_t * core_if);
#endif
/** Resume the HCD. Helper function for using the HCD callbacks.
*
* @param core_if Programming view of DWC_otg controller.
*/
extern _LONG_CALL_ void cil_hcd_resume(dwc_otg_core_if_t * core_if);
/** Start the PCD. Helper function for using the PCD callbacks.
*
* @param core_if Programming view of DWC_otg controller.
*/
extern _LONG_CALL_ void cil_pcd_start(dwc_otg_core_if_t * core_if);
/** Stop the PCD. Helper function for using the PCD callbacks.
*
* @param core_if Programming view of DWC_otg controller.
*/
extern _LONG_CALL_ void cil_pcd_stop(dwc_otg_core_if_t * core_if);
/** Suspend the PCD. Helper function for using the PCD callbacks.
*
* @param core_if Programming view of DWC_otg controller.
*/
extern _LONG_CALL_ void cil_pcd_suspend(dwc_otg_core_if_t * core_if);
/** Resume the PCD. Helper function for using the PCD callbacks.
*
* @param core_if Programming view of DWC_otg controller.
*/
extern _LONG_CALL_ void cil_pcd_resume(dwc_otg_core_if_t * core_if);
//////////////////////////////////////////////////////////////////////
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_cil.h
|
C
|
apache-2.0
| 39,659
|
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "basic_types.h"
//#include "va_list.h"
#include <stdarg.h>
#include "diag.h"
#include "dwc_otg_dbg.h"
#include "dwc_os.h"
typedef struct _RAM_OTG_FUNCTION_TABLE_ {
VOID* (*RamMemSet) (void *dest, int byte, SIZE_T size);
VOID* (*RamMemCpy) (void *dest, void const *src, SIZE_T size);
int (*RamMemCmp) (void const*m1, void const *m2, SIZE_T size);
int (*RamStrnCmp) (const char *s1, const char *s2, SIZE_T size);
int (*RamStrCmp) (const char *s1, const char *s2);
SIZE_T (*RamStrLen) (char const *str);
char* (*RamStrCpy) (char *to, char const *from);
char* (*RamStrDup) (char const *str);
int (*RamAtoi) (const char *str, int32_t *value);
int (*RamAtoui) (const char *str, uint32_t *value);
int (*RamVsnPrintf) (char *str, int size, const char *format, ...);
u32 (*RamSPrintf) (u8 *buf, const char *fmt, ...);
int (*RamSnPrintf) (char *dst, int count, const char * src, ...);
u8* (*RamZmalloc) (u32 sz);
u8* (*RamZmallocAtomic) (u32 sz);
VOID (*RamMfree) (u8 *pbuf, u32 sz);
dwc_spinlock_t* (*RamSpinlockAlloc) (void);
VOID (*RamSpinlockFree) (dwc_spinlock_t *lock);
VOID (*RamSpinlock) (dwc_spinlock_t *lock);
VOID (*RamSpinUnlock) (dwc_spinlock_t *lock);
VOID (*RamSpinIrqSave) (dwc_spinlock_t *lock, dwc_irqflags_t *flags);
VOID (*RamSpinIrqRestore) (dwc_spinlock_t *lock, dwc_irqflags_t flags);
dwc_mutex_t*(*RamMutexAlloc) (void);
VOID (*RamMutexFree) (dwc_mutex_t *mutex);
VOID (*RamMutexLock) (dwc_mutex_t *mutex);
int (*RamMutexTryLock) (dwc_mutex_t *mutex);
VOID (*RamMutexUnLock) (dwc_mutex_t *mutex);
uint32_t(*RamUDelay) (uint32_t usecs);
void (*RamMSleep) (uint32_t msecs);
VOID (*timer_callback) (unsigned long data);
dwc_timer_t *(*RamTimerAlloc) (char *name, dwc_timer_callback_t cb, void *data);
VOID (*RamTimerFree) (dwc_timer_t *timer);
VOID (*RamTimerSche) (dwc_timer_t *timer, uint32_t time_ms);
VOID (*RamTimerCancel) (dwc_timer_t *timer);
VOID (*RamEnterCritical) (void);
VOID (*RamExitCritical) (void);
}RAM_OTG_FUNCTION_TABLE, *PRAM_OTG_FUNCTION_TABLE;
// Global Variable
extern RAM_OTG_FUNCTION_TABLE gRamOTGFunTbl;
// Funtion Prototype
// ROM
_LONG_CALL_ void dwc_otg_wrapper_reset(IN VOID);
_LONG_CALL_ void dwc_otg_wrapper_init_boot(IN VOID);
_LONG_CALL_ void dwc_otg_power_init(IN VOID);
#if AMEBAD_TODO
_LONG_CALL_ VOID RtlInitListhead_Otg(IN _LIST *list);
_LONG_CALL_ u32 RtlIsListEmpty_Otg(IN _LIST *phead);
_LONG_CALL_ VOID RtlListInsertHead_Otg(IN _LIST *plist,IN _LIST *phead);
_LONG_CALL_ VOID RtlListInsertTail_Otg(IN _LIST *plist,IN _LIST *phead);
_LONG_CALL_ _LIST *RtlListGetNext_Otg(IN _LIST *plist);
_LONG_CALL_ VOID RtlListDelete_Otg(IN _LIST *plist);
#endif
extern _LONG_CALL_ char *DWC_STRDUP_ROM(char const *str);
extern _LONG_CALL_ int DWC_ATOI_ROM(const char *str, int32_t *value);
extern _LONG_CALL_ int DWC_ATOUI_ROM(const char *str, uint32_t *value);
// RAM
extern void dwc_otg_wrapper_init(IN VOID);
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_common.h
|
C
|
apache-2.0
| 3,664
|
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
* $Revision: #15 $
* $Date: 2012/12/10 $
* $Change: 2123206 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_CORE_IF_H__)
#define __DWC_CORE_IF_H__
#include "ameba_otg.h"
#include "dwc_os.h"
/** @file
* This file defines DWC_OTG Core API
*/
struct dwc_otg_core_if;
typedef struct dwc_otg_core_if dwc_otg_core_if_t;
/** Maximum number of Periodic FIFOs */
#define MAX_PERIO_FIFOS 15
/** Maximum number of Periodic FIFOs */
#define MAX_TX_FIFOS 15
/** Maximum number of Endpoints/HostChannels */
#define MAX_EPS_CHANNELS 8
extern _LONG_CALL_ dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr, int mode);
extern _LONG_CALL_ void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
/** This function should be called on every hardware interrupt. */
extern _LONG_CALL_ int32_t dwc_otg_handle_common_intr(void *otg_dev);
/** @name OTG Core Parameters */
/** @{ */
/**
* Specifies the OTG capabilities. The driver will automatically
* detect the value for this parameter if none is specified.
* 0 - HNP and SRP capable (default)
* 1 - SRP Only capable
* 2 - No HNP/SRP capable
*/
extern _LONG_CALL_ int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
extern _LONG_CALL_ int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
#define dwc_param_opt_default 1
/**
* Specifies whether to use slave or DMA mode for accessing the data
* FIFOs. The driver will automatically detect the value for this
* parameter if none is specified.
* 0 - Slave
* 1 - DMA (default, if available)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_dma_enable_default 1
/**
* When DMA mode is enabled specifies whether to use
* address DMA or DMA Descritor mode for accessing the data
* FIFOs in device mode. The driver will automatically detect
* the value for this parameter if none is specified.
* 0 - address DMA
* 1 - DMA Descriptor(default, if available)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_dma_desc_enable_default 1
/** The DMA Burst size (applicable only for External DMA
* Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
#define dwc_param_dma_burst_size_default 32
/**
* Specifies the maximum speed of operation in host and device mode.
* The actual speed depends on the speed of the attached device and
* the value of phy_type. The actual speed depends on the speed of the
* attached device.
* 0 - High Speed (default)
* 1 - Full Speed
*/
extern _LONG_CALL_ int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
#if !defined(USB_DEV_FULL_SPEED)
#define dwc_param_speed_default 0
#else
#define dwc_param_speed_default 1
#endif
#define DWC_SPEED_PARAM_HIGH 0
#define DWC_SPEED_PARAM_FULL 1
/** Specifies whether low power mode is supported when attached
* to a Full Speed or Low Speed device in host mode.
* 0 - Don't support low power mode (default)
* 1 - Support low power mode
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
* core_if);
#define dwc_param_host_support_fs_ls_low_power_default 0
/** Specifies the PHY clock rate in low power mode when connected to a
* Low Speed device in host mode. This parameter is applicable only if
* HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
* then defaults to 6 MHZ otherwise 48 MHZ.
*
* 0 - 48 MHz
* 1 - 6 MHz
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
core_if);
#define dwc_param_host_ls_low_power_phy_clk_default 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
/**
* 0 - Use cC FIFO size parameters
* 1 - Allow dynamic FIFO sizing (default)
*/
extern _LONG_CALL_ int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
core_if);
#define dwc_param_enable_dynamic_fifo_default 1
/** Total number of 4-byte words in the data FIFO memory. This
* memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
* Tx FIFOs.
* 32 to 32768 (default 8192)
* Note: The total FIFO memory depth in the FPGA configuration is 8192.
*/
extern _LONG_CALL_ int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
#define dwc_param_data_fifo_size_default 8192
/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1064)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
#define dwc_param_dev_rx_fifo_size_default 1064
/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
* when dynamic FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
core_if);
#define dwc_param_dev_nperio_tx_fifo_size_default 1024
/** Number of 4-byte words in each of the periodic Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
int32_t val, int fifo_num);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
core_if, int fifo_num);
#define dwc_param_dev_perio_tx_fifo_size_default 256
/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
#define dwc_param_host_rx_fifo_size_default 1024
/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
* when Dynamic FIFO sizing is enabled in the core.
* 16 to 32768 (default 1024)
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
core_if);
#define dwc_param_host_nperio_tx_fifo_size_default 1024
/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
core_if);
#define dwc_param_host_perio_tx_fifo_size_default 1024
/** The maximum transfer size supported in bytes.
* 2047 to 65,535 (default 65,535)
*/
extern _LONG_CALL_ int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
#define dwc_param_max_transfer_size_default 65535
/** The maximum number of packets in a transfer.
* 15 to 511 (default 511)
*/
extern _LONG_CALL_ int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
#define dwc_param_max_packet_count_default 511
/** The number of host channel registers to use.
* 1 to 16 (default 12)
* Note: The FPGA configuration supports a maximum of 12 host channels.
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
#define dwc_param_host_channels_default 12
/** The number of endpoints in addition to EP0 available for device
* mode operations.
* 1 to 15 (default 6 IN and OUT)
* Note: The FPGA configuration supports a maximum of 6 IN and OUT
* endpoints in addition to EP0.
*/
extern _LONG_CALL_ int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
#define dwc_param_dev_endpoints_default 6
/**
* Specifies the type of PHY interface to use. By default, the driver
* will automatically detect the phy_type.
*
* 0 - Full Speed PHY
* 1 - UTMI+ (default)
* 2 - ULPI
*/
extern _LONG_CALL_ int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
#define DWC_PHY_TYPE_PARAM_FS 0
#define DWC_PHY_TYPE_PARAM_UTMI 1
#define DWC_PHY_TYPE_PARAM_ULPI 2
#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
/**
* Specifies the UTMI+ Data Width. This parameter is
* applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
* PHY_TYPE, this parameter indicates the data width between
* the MAC and the ULPI Wrapper.) Also, this parameter is
* applicable only if the OTG_HSPHY_WIDTH cC parameter was set
* to "8 and 16 bits", meaning that the core has been
* configured to work at either data path width.
*
* 8 or 16 bits (default 16)
*/
extern _LONG_CALL_ int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
#define dwc_param_phy_utmi_width_default 16
/**
* Specifies whether the ULPI operates at double or single
* data rate. This parameter is only applicable if PHY_TYPE is
* ULPI.
*
* 0 - single data rate ULPI interface with 8 bit wide data
* bus (default)
* 1 - double data rate ULPI interface with 4 bit wide data
* bus
*/
extern _LONG_CALL_ int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
#define dwc_param_phy_ulpi_ddr_default 0
/**
* Specifies whether to use the internal or external supply to
* drive the vbus with a ULPI phy.
*/
extern _LONG_CALL_ int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
#define DWC_PHY_ULPI_INTERNAL_VBUS 0
#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
/**
* Specifies whether to use the I2Cinterface for full speed PHY. This
* parameter is only applicable if PHY_TYPE is FS.
* 0 - No (default)
* 1 - Yes
*/
extern _LONG_CALL_ int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_i2c_enable_default 0
extern _LONG_CALL_ int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
#define dwc_param_ulpi_fs_ls_default 0
extern _LONG_CALL_ int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
#define dwc_param_ts_dline_default 0
/**
* Specifies whether dedicated transmit FIFOs are
* enabled for non periodic IN endpoints in device mode
* 0 - No
* 1 - Yes
*/
extern _LONG_CALL_ int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
core_if);
#define dwc_param_en_multiple_tx_fifo_default 1
/** Number of 4-byte words in each of the Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
//extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
// int fifo_num, int32_t val);
extern _LONG_CALL_ int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
int fifo_num);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
int fifo_num);
#define dwc_param_dev_tx_fifo_size_default 256
/** Thresholding enable flag-
* bit 0 - enable non-ISO Tx thresholding
* bit 1 - enable ISO Tx thresholding
* bit 2 - enable Rx thresholding
*/
extern _LONG_CALL_ int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
#define dwc_param_thr_ctl_default 0
/** Thresholding length for Tx
* FIFOs in 32 bit DWORDs
*/
extern _LONG_CALL_ int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
#define dwc_param_tx_thr_length_default 64
/** Thresholding length for Rx
* FIFOs in 32 bit DWORDs
*/
extern _LONG_CALL_ int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
#define dwc_param_rx_thr_length_default 64
/**
* Specifies whether LPM (Link Power Management) support is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_lpm_enable_default 1
/**
* Specifies whether LPM Errata (Link Power Management) support is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_besl_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_besl_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_besl_enable_default 0
/**
* Specifies baseline_besl default value
*/
extern _LONG_CALL_ int dwc_otg_set_param_baseline_besl(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_baseline_besl(dwc_otg_core_if_t * core_if);
#define dwc_param_baseline_besl_default 0
/**
* Specifies deep_besl default value
*/
extern _LONG_CALL_ int dwc_otg_set_param_deep_besl(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_deep_besl(dwc_otg_core_if_t * core_if);
#define dwc_param_deep_besl_default 15
/**
* Specifies whether PTI enhancement is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_pti_enable_default 0
/**
* Specifies whether MPI enhancement is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_mpi_enable_default 0
/**
* Specifies whether ADP capability is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_adp_enable_default 0
/**
* Specifies whether IC_USB capability is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
#define dwc_param_ic_usb_cap_default 0
extern _LONG_CALL_ int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
#define dwc_param_ahb_thr_ratio_default 0
extern _LONG_CALL_ int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
#define dwc_param_power_down_default 0
extern _LONG_CALL_ int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
#define dwc_param_reload_ctl_default 0
extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
#define dwc_param_dev_out_nak_default 0
extern _LONG_CALL_ int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
#define dwc_param_cont_on_bna_default 0
extern _LONG_CALL_ int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
#define dwc_param_ahb_single_default 0
extern _LONG_CALL_ int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
#define dwc_param_otg_ver_default 0
/** @} */
/** @name Access to registers and bit-fields */
/**
* Dump core registers and SPRAM
*/
extern _LONG_CALL_ void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
/**
* Get host negotiation status.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
/**
* Get srp status
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
/**
* Set hnpreq bit in the GOTGCTL register.
*/
extern _LONG_CALL_ void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get Content of SNPSID register.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
/**
* Get current mode.
* Returns 0 if in device mode, and 1 if in host mode.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
/**
* Get value of hnpcapable field in the GUSBCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
/**
* Set value of hnpcapable field in the GUSBCFG register
*/
extern _LONG_CALL_ void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of srpcapable field in the GUSBCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
/**
* Set value of srpcapable field in the GUSBCFG register
*/
extern _LONG_CALL_ void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of devspeed field in the DCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
/**
* Set value of devspeed field in the DCFG register
*/
extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get the value of busconnected field from the HPRT0 register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
/**
* Gets the device enumeration Speed.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
/**
* Get value of prtpwr field from the HPRT0 register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
/**
* Get value of flag indicating core state - hibernated or not
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
/**
* Set value of prtpwr field from the HPRT0 register
*/
extern _LONG_CALL_ void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of prtsusp field from the HPRT0 regsiter
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
/**
* Set value of prtpwr field from the HPRT0 register
*/
extern _LONG_CALL_ void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of ModeChTimEn field from the HCFG regsiter
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
/**
* Set value of ModeChTimEn field from the HCFG regsiter
*/
extern _LONG_CALL_ void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of Fram Interval field from the HFIR regsiter
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
/**
* Set value of Frame Interval field from the HFIR regsiter
*/
extern _LONG_CALL_ void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Set value of prtres field from the HPRT0 register
*FIXME Remove?
*/
extern _LONG_CALL_ void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of rmtwkupsig bit in DCTL register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
/**
* Get value of besl_reject bit in DCTL register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_beslreject(dwc_otg_core_if_t * core_if);
/**
* Set value of besl_reject bit in DCTL register
*/
extern _LONG_CALL_ void dwc_otg_set_beslreject(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of prt_sleep_sts field from the GLPMCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
/**
* Get value of rem_wkup_en field from the GLPMCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
/**
* Get value of appl_resp field from the GLPMCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
/**
* Set value of appl_resp field from the GLPMCFG register
*/
extern _LONG_CALL_ void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of hsic_connect field from the GLPMCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
/**
* Set value of hsic_connect field from the GLPMCFG register
*/
extern _LONG_CALL_ void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of inv_sel_hsic field from the GLPMCFG register.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
/**
* Set value of inv_sel_hsic field from the GLPMFG register.
*/
extern _LONG_CALL_ void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Set value of hird_thresh field from the GLPMFG register.
*/
extern _LONG_CALL_ void dwc_otg_set_hirdthresh(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of hird_thresh field from the GLPMFG register.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hirdthresh(dwc_otg_core_if_t * core_if);
/*
* Some functions for accessing registers
*/
/**
* GOTGCTL register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GUSBCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GRXFSIZ register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GNPTXFSIZ register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
extern _LONG_CALL_ uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GGPIO register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GUID register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* HPRT0 register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GHPTXFSIZE
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
/** @} */
#endif /* __DWC_CORE_IF_H__ */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_core_if.h
|
C
|
apache-2.0
| 28,346
|
/* ==========================================================================
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_DBG_H__
#define __DWC_OTG_DBG_H__
#include "section_config.h"
#define OTGDEBUG 1
#define VERBOSE 1
/** @file
* This file defines debug levels.
* Debugging support vanishes in non-debug builds.
*/
/**
* The Debug Level bit-mask variable.
*/
extern uint32_t g_dbg_lvl;
/**
* Set the Debug Level variable.
*/
extern _LONG_CALL_ uint32_t SET_DEBUG_LEVEL(const uint32_t new);
/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
#define DBG_CIL (0x2)
/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
* messages */
#define DBG_CILV (0x20)
/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
* messages */
#define DBG_PCD (0x4)
/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
* messages */
#define DBG_PCDV (0x40)
/** When debug level has the DBG_HCD bit set, display Host debug messages */
#define DBG_HCD (0x8)
/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
* messages */
#define DBG_HCDV (0x80)
/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
* mode. */
#define DBG_HCD_URB (0x800)
/** When debug level has any bit set, display debug messages */
#define DBG_ANY (0xFF)
/** All debug messages off */
#define DBG_OFF 0
/** Prefix string for DWC_DEBUG print macros. */
#define USB_DWC "DWC_otg: "
/**
* Print a debug message when the Global debug level variable contains
* the bit defined in <code>lvl</code>.
*
* @param[in] lvl - Debug level, use one of the DBG_ constants above.
* @param[in] x - like printf
*
* Example:<p>
* <code>
* DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
* </code>
* <br>
* results in:<br>
* <code>
* usb-DWC_otg: dwc_otg_cil_init(ca867000)
* </code>
*/
#ifdef OTGDEBUG
//# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)DBG_8195A_OTG(x); }while(0)
# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
#else
# define DWC_DEBUGPL(lvl, x...) do{}while(0)
# define DWC_DEBUGP(x...)
# define CHK_DEBUG_LEVEL(level) (0)
#endif /*DEBUG*/
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_dbg.h
|
C
|
apache-2.0
| 4,097
|
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
* $Revision: #19 $
* $Date: 2010/11/15 $
* $Change: 1627671 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_DRIVER_H__
#define __DWC_OTG_DRIVER_H__
/** @file
* This file contains the interface to the Linux driver.
*/
//#include "dwc_otg_os_dep.h"
#include "dwc_otg_core_if.h"
#include "osdep_service.h"
/* Type declarations */
struct dwc_otg_pcd;
struct dwc_otg_hcd;
/**
* This structure is a wrapper that encapsulates the driver components used to
* manage a single DWC_otg controller.
*/
typedef struct dwc_otg_device {
/** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
* VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
* require this. */
//struct os_dependent os_dep;
/** Base address returned from ioremap() */
void *base;
uint32_t reg_offset;
/** Pointer to the core interface structure. */
dwc_otg_core_if_t *core_if;
/** Pointer to the PCD structure. */
struct dwc_otg_pcd *pcd;
/** Pointer to the HCD structure. */
struct dwc_otg_hcd *hcd;
/** Flag to indicate whether the common IRQ handler is installed. */
uint8_t common_irq_installed;
} dwc_otg_device_t;
/*We must clear S3C24XX_EINTPEND external interrupt register
* because after clearing in this register trigerred IRQ from
* H/W core in kernel interrupt can be occured again before OTG
* handlers clear all IRQ sources of Core registers because of
* timing latencies and Low Level IRQ Type.
*/
#ifdef CONFIG_MACH_IPMATE
#define S3C2410X_CLEAR_EINTPEND() \
do { \
__raw_writel(1UL << 11,S3C24XX_EINTPEND); \
} while (0)
#else
#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
#endif
typedef struct USB_OTG_DRV_ADP {
dwc_otg_device_t *otgdev;
#if !TASK_SCHEDULER_DISABLED
#if defined(DWC_WITH_WLAN_OSDEP)
_sema Sema;
#else
_Sema Sema;
#endif
#else
u32 Sema;
#endif
#if !TASK_SCHEDULER_DISABLED
#if defined(DWC_WITH_WLAN_OSDEP)
struct task_struct OTGTask;
#else
xTaskHandle OTGTask;
#endif
#else
u32 OTGTask;
#endif
}USB_OTG_DRV_ADP,*PUSB_OTG_DRV_ADP;
typedef struct _DWC_OTG_ADAPTER_ {
u32 temp0;
dwc_otg_device_t *otgdev;
u8 TestItem;
}DWC_OTG_ADAPTER, *PDWC_OTG_ADAPTER;
void dwc_otg_disable_irq(IN VOID);
void dwc_otg_enable_irq(IN VOID);
int usb_hcd_post_init(void);
int dwc_otg_driver_remove_common(VOID);
int dwc_otg_boot_deinit(void);
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_driver.h
|
C
|
apache-2.0
| 4,334
|
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
* $Revision: #58 $
* $Date: 2011/09/15 $
* $Change: 1846647 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_DEVICE_ONLY
#ifndef __DWC_HCD_H__
#define __DWC_HCD_H__
//#include "dwc_otg_os_dep.h"
#include "usb.h"
#include "dwc_otg_hcd_if.h"
#include "dwc_otg_core_if.h"
#include "dwc_list.h"
#include "dwc_otg_cil.h"
#undef DWC_HS_ELECT_TST
/**
* @file
*
* This file contains the structures, constants, and interfaces for
* the Host Contoller Driver (HCD).
*
* The Host Controller Driver (HCD) is responsible for translating requests
* from the USB Driver into the appropriate actions on the DWC_otg controller.
* It isolates the USBD from the specifics of the controller by providing an
* API to the USBD.
*/
struct dwc_otg_hcd_pipe_info {
uint8_t dev_addr;
uint8_t ep_num;
uint8_t pipe_type;
uint8_t pipe_dir;
uint16_t mps;
};
struct dwc_otg_hcd_iso_packet_desc {
uint32_t offset;
uint32_t length;
uint32_t actual_length;
uint32_t status;
};
struct dwc_otg_qtd;
struct dwc_otg_hcd_urb {
void *priv;
struct dwc_otg_qtd *qtd;
void *buf;
dwc_dma_t dma;
void *setup_packet;
dwc_dma_t setup_dma;
uint32_t length;
uint32_t actual_length;
uint32_t status;
uint32_t error_count;
uint32_t packet_count;
uint32_t flags;
uint16_t interval;
struct dwc_otg_hcd_pipe_info pipe_info;
struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
};
extern _LONG_CALL_
uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
uint8_t devaddr, uint8_t ep_num,
uint8_t pipe_type, uint8_t pipe_dir,
uint16_t mps);
/**
* Phases for control transfers.
*/
typedef enum dwc_otg_control_phase {
DWC_OTG_CONTROL_SETUP,
DWC_OTG_CONTROL_DATA,
DWC_OTG_CONTROL_STATUS
} dwc_otg_control_phase_e;
/** Transaction types. */
typedef enum dwc_otg_transaction_type {
DWC_OTG_TRANSACTION_NONE,
DWC_OTG_TRANSACTION_PERIODIC,
DWC_OTG_TRANSACTION_NON_PERIODIC,
DWC_OTG_TRANSACTION_ALL
} dwc_otg_transaction_type_e;
struct dwc_otg_qh;
/**
* A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
* interrupt, or isochronous transfer. A single QTD is created for each URB
* (of one of these types) submitted to the HCD. The transfer associated with
* a QTD may require one or multiple transactions.
*
* A QTD is linked to a Queue Head, which is entered in either the
* non-periodic or periodic schedule for execution. When a QTD is chosen for
* execution, some or all of its transactions may be executed. After
* execution, the state of the QTD is updated. The QTD may be retired if all
* its transactions are complete or if an error occurred. Otherwise, it
* remains in the schedule so more transactions can be executed later.
*/
typedef struct dwc_otg_qtd {
/**
* Determines the PID of the next data packet for the data phase of
* control transfers. Ignored for other transfer types.<br>
* One of the following values:
* - DWC_OTG_HC_PID_DATA0
* - DWC_OTG_HC_PID_DATA1
*/
uint8_t data_toggle;
/** Current phase for control transfers (Setup, Data, or Status). */
dwc_otg_control_phase_e control_phase;
/** Keep track of the current split type
* for FS/LS endpoints on a HS Hub */
uint8_t complete_split;
/** How many bytes transferred during SSPLIT OUT */
uint32_t ssplit_out_xfer_count;
/**
* Holds the number of bus errors that have occurred for a transaction
* within this transfer.
*/
uint8_t error_count;
/**
* Index of the next frame descriptor for an isochronous transfer. A
* frame descriptor describes the buffer position and length of the
* data to be transferred in the next scheduled (micro)frame of an
* isochronous transfer. It also holds status for that transaction.
* The frame index starts at 0.
*/
uint16_t isoc_frame_index;
/** Position of the ISOC split on full/low speed */
uint8_t isoc_split_pos;
/** Position of the ISOC split in the buffer for the current frame */
uint16_t isoc_split_offset;
/** URB for this transfer */
struct dwc_otg_hcd_urb *urb;
struct dwc_otg_qh *qh;
/** This list of QTDs */
DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
/** Indicates if this QTD is currently processed by HW. */
uint8_t in_process;
/** Number of DMA descriptors for this QTD */
uint8_t n_desc;
/**
* Last activated frame(packet) index.
* Used in Descriptor DMA mode only.
*/
uint16_t isoc_frame_index_last;
} dwc_otg_qtd_t;
DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
/**
* A Queue Head (QH) holds the static characteristics of an endpoint and
* maintains a list of transfers (QTDs) for that endpoint. A QH structure may
* be entered in either the non-periodic or periodic schedule.
*/
typedef struct dwc_otg_qh {
/**
* Endpoint type.
* One of the following values:
* - UE_CONTROL
* - UE_BULK
* - UE_INTERRUPT
* - UE_ISOCHRONOUS
*/
uint8_t ep_type;
uint8_t ep_is_in;
/** wMaxPacketSize Field of Endpoint Descriptor. */
uint16_t maxp;
/**
* Device speed.
* One of the following values:
* - DWC_OTG_EP_SPEED_LOW
* - DWC_OTG_EP_SPEED_FULL
* - DWC_OTG_EP_SPEED_HIGH
*/
uint8_t dev_speed;
/**
* Determines the PID of the next data packet for non-control
* transfers. Ignored for control transfers.<br>
* One of the following values:
* - DWC_OTG_HC_PID_DATA0
* - DWC_OTG_HC_PID_DATA1
*/
uint8_t data_toggle;
/** Ping state if 1. */
uint8_t ping_state;
/**
* List of QTDs for this QH.
*/
struct dwc_otg_qtd_list qtd_list;
/** Host channel currently processing transfers for this QH. */
struct dwc_hc *channel;
/** Full/low speed endpoint on high-speed hub requires split. */
uint8_t do_split;
/** @name Periodic schedule information */
/** @{ */
/** Bandwidth in microseconds per (micro)frame. */
uint16_t usecs;
/** Interval between transfers in (micro)frames. */
uint16_t interval;
/**
* (micro)frame to initialize a periodic transfer. The transfer
* executes in the following (micro)frame.
*/
uint16_t sched_frame;
/** (micro)frame at which last start split was initialized. */
uint16_t start_split_frame;
/** @} */
/**
* Used instead of original buffer if
* it(physical address) is not dword-aligned.
*/
uint8_t *dw_align_buf;
dwc_dma_t dw_align_buf_dma;
/** Entry for QH in either the periodic or non-periodic schedule. */
dwc_list_link_t qh_list_entry;
/** @name Descriptor DMA support */
/** @{ */
/** Descriptor List. */
dwc_otg_host_dma_desc_t *desc_list;
/** Descriptor List physical address. */
dwc_dma_t desc_list_dma;
/**
* Xfer Bytes array.
* Each element corresponds to a descriptor and indicates
* original XferSize size value for the descriptor.
*/
uint32_t *n_bytes;
/** Actual number of transfer descriptors in a list. */
uint16_t ntd;
/** First activated isochronous transfer descriptor index. */
uint8_t td_first;
/** Last activated isochronous transfer descriptor index. */
uint8_t td_last;
/** @} */
} dwc_otg_qh_t;
DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
/**
* This structure holds the state of the HCD, including the non-periodic and
* periodic schedules.
*/
struct dwc_otg_hcd {
/** The DWC otg device pointer */
struct dwc_otg_device *otg_dev;
/** DWC OTG Core Interface Layer */
dwc_otg_core_if_t *core_if;
/** Function HCD driver callbacks */
struct dwc_otg_hcd_function_ops *fops;
/** Internal DWC HCD Flags */
volatile union dwc_otg_hcd_internal_flags {
uint32_t d32;
struct {
unsigned port_connect_status_change:1;
unsigned port_connect_status:1;
unsigned port_reset_change:1;
unsigned port_enable_change:1;
unsigned port_suspend_change:1;
unsigned port_over_current_change:1;
unsigned port_l1_change:1;
unsigned reserved:26;
} b;
} flags;
/**
* Inactive items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are not
* currently assigned to a host channel.
*/
dwc_list_link_t non_periodic_sched_inactive;
/**
* Active items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are
* currently assigned to a host channel.
*/
dwc_list_link_t non_periodic_sched_active;
/**
* Pointer to the next Queue Head to process in the active
* non-periodic schedule.
*/
dwc_list_link_t *non_periodic_qh_ptr;
/**
* Inactive items in the periodic schedule. This is a list of QHs for
* periodic transfers that are _not_ scheduled for the next frame.
* Each QH in the list has an interval counter that determines when it
* needs to be scheduled for execution. This scheduling mechanism
* allows only a simple calculation for periodic bandwidth used (i.e.
* must assume that all periodic transfers may need to execute in the
* same frame). However, it greatly simplifies scheduling and should
* be sufficient for the vast majority of OTG hosts, which need to
* connect to a small number of peripherals at one time.
*
* Items move from this list to periodic_sched_ready when the QH
* interval counter is 0 at SOF.
*/
dwc_list_link_t periodic_sched_inactive;
/**
* List of periodic QHs that are ready for execution in the next
* frame, but have not yet been assigned to host channels.
*
* Items move from this list to periodic_sched_assigned as host
* channels become available during the current frame.
*/
dwc_list_link_t periodic_sched_ready;
/**
* List of periodic QHs to be executed in the next frame that are
* assigned to host channels.
*
* Items move from this list to periodic_sched_queued as the
* transactions for the QH are queued to the DWC_otg controller.
*/
dwc_list_link_t periodic_sched_assigned;
/**
* List of periodic QHs that have been queued for execution.
*
* Items move from this list to either periodic_sched_inactive or
* periodic_sched_ready when the channel associated with the transfer
* is released. If the interval for the QH is 1, the item moves to
* periodic_sched_ready because it must be rescheduled for the next
* frame. Otherwise, the item moves to periodic_sched_inactive.
*/
dwc_list_link_t periodic_sched_queued;
/**
* Total bandwidth claimed so far for periodic transfers. This value
* is in microseconds per (micro)frame. The assumption is that all
* periodic transfers may occur in the same (micro)frame.
*/
uint16_t periodic_usecs;
/**
* Frame number read from the core at SOF. The value ranges from 0 to
* DWC_HFNUM_MAX_FRNUM.
*/
uint16_t frame_number;
/**
* Count of periodic QHs, if using several eps. For SOF enable/disable.
*/
uint16_t periodic_qh_count;
/**
* Free host channels in the controller. This is a list of
* dwc_hc_t items.
*/
struct hc_list free_hc_list;
/**
* Number of host channels assigned to periodic transfers. Currently
* assuming that there is a dedicated host channel for each periodic
* transaction and at least one host channel available for
* non-periodic transactions.
*/
int periodic_channels;
/**
* Number of host channels assigned to non-periodic transfers.
*/
int non_periodic_channels;
/**
* Array of pointers to the host channel descriptors. Allows accessing
* a host channel descriptor given the host channel number. This is
* useful in interrupt handlers.
*/
struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
/**
* Buffer to use for any data received during the status phase of a
* control transfer. Normally no data is transferred during the status
* phase. This buffer is used as a bit bucket.
*/
uint8_t *status_buf;
/**
* DMA address for status_buf.
*/
dma_addr_t status_buf_dma;
#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
/**
* Connection timer. An OTG host must display a message if the device
* does not connect. Started when the VBus power is turned on via
* sysfs attribute "buspower".
*/
dwc_timer_t *conn_timer;
/* Tasket to do a reset */
//dwc_tasklet_t *reset_tasklet;
/* */
dwc_spinlock_t *lock;
/**
* Private data that could be used by OS wrapper.
*/
void *priv;
uint8_t otg_port;
/** Frame List */
uint32_t *frame_list;
/** Frame List DMA address */
dma_addr_t frame_list_dma;
#ifdef OTGDEBUG
uint32_t frrem_samples;
uint64_t frrem_accum;
uint32_t hfnum_7_samples_a;
uint64_t hfnum_7_frrem_accum_a;
uint32_t hfnum_0_samples_a;
uint64_t hfnum_0_frrem_accum_a;
uint32_t hfnum_other_samples_a;
uint64_t hfnum_other_frrem_accum_a;
uint32_t hfnum_7_samples_b;
uint64_t hfnum_7_frrem_accum_b;
uint32_t hfnum_0_samples_b;
uint64_t hfnum_0_frrem_accum_b;
uint32_t hfnum_other_samples_b;
uint64_t hfnum_other_frrem_accum_b;
#endif
};
/** @name Transaction Execution Functions */
/** @{ */
extern _LONG_CALL_ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
* hcd);
extern _LONG_CALL_ void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
dwc_otg_transaction_type_e tr_type);
/** @} */
/** @name Interrupt Handler Functions */
/** @{ */
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
uint32_t num);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
/** @} */
/** @name Schedule Queue Functions */
/** @{ */
/* Implemented in dwc_otg_hcd_queue.c */
extern _LONG_CALL_ dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
dwc_otg_hcd_urb_t * urb, int atomic_alloc);
extern _LONG_CALL_ void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
int sched_csplit);
/** Remove and free a QH */
extern _LONG_CALL_
void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
dwc_otg_qh_t * qh);
/** Allocates memory for a QH structure.
* @return Returns the memory allocate or NULL on error. */
extern _LONG_CALL_
dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc);
extern _LONG_CALL_ dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
int atomic_alloc);
extern _LONG_CALL_ void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
extern _LONG_CALL_ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
dwc_otg_qh_t ** qh, int atomic_alloc);
/** Allocates memory for a QTD structure.
* @return Returns the memory allocate or NULL on error. */
extern _LONG_CALL_
dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc);
/** Frees the memory for a QTD structure. QTD should already be removed from
* list.
* @param qtd QTD to free.*/
extern _LONG_CALL_
void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd);
/** Removes a QTD from list.
* @param hcd HCD instance.
* @param qtd QTD to remove from list.
* @param qh QTD belongs to.
*/
extern _LONG_CALL_
void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
dwc_otg_qtd_t * qtd,
dwc_otg_qh_t * qh);
/** Remove and free a QTD
* Need to disable IRQ and hold hcd lock while calling this function out of
* interrupt servicing chain */
extern _LONG_CALL_
void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
dwc_otg_qtd_t * qtd,
dwc_otg_qh_t * qh);
/** @} */
/** @name Descriptor DMA Supporting Functions */
/** @{ */
extern _LONG_CALL_ void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
dwc_hc_t * hc,
dwc_otg_hc_regs_t * hc_regs,
dwc_otg_halt_status_e halt_status);
extern _LONG_CALL_ int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ void reset_tasklet_func(void *data);
/** @} */
/** @name Internal Functions */
/** @{ */
extern _LONG_CALL_ dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
/** @} */
#ifdef CONFIG_USB_DWC_OTG_LPM
extern _LONG_CALL_ int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
uint8_t devaddr);
extern _LONG_CALL_ void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
#endif
/** Gets the QH that contains the list_head */
#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
/** Gets the QTD that contains the list_head */
#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
/** Check if QH is non-periodic */
#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
(_qh_ptr_->ep_type == UE_CONTROL))
/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
/** Packet size for any kind of endpoint descriptor */
#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
/**
* Returns true if _frame1 is less than or equal to _frame2. The comparison is
* done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
* frame number when the max frame number is reached.
*/
extern _LONG_CALL_
int dwc_frame_num_le(uint16_t frame1, uint16_t frame2);
/**
* Returns true if _frame1 is greater than _frame2. The comparison is done
* modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
* number when the max frame number is reached.
*/
extern _LONG_CALL_
int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2);
/**
* Increments _frame by the amount specified by _inc. The addition is done
* modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
*/
extern _LONG_CALL_
uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc);
extern _LONG_CALL_
uint16_t dwc_full_frame_num(uint16_t frame);
extern _LONG_CALL_
uint16_t dwc_micro_frame_num(uint16_t frame);
extern _LONG_CALL_ void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
dwc_otg_hc_regs_t * hc_regs,
dwc_otg_qtd_t * qtd);
extern _LONG_CALL_ void dwc_hcd_data_init(void);
#ifdef OTGDEBUG
/**
* Macro to sample the remaining PHY clocks left in the current frame. This
* may be used during debugging to determine the average time it takes to
* execute sections of code. There are two possible sample points, "a" and
* "b", so the _letter argument must be one of these values.
*
* To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
* example, "cat /sys/devices/lm0/hcd_frrem".
*/
#define dwc_sample_frrem(_hcd, _qh, _letter) \
{ \
hfnum_data_t hfnum; \
dwc_otg_qtd_t *qtd; \
qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
switch (hfnum.b.frnum & 0x7) { \
case 7: \
_hcd->hfnum_7_samples_##_letter++; \
_hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
case 0: \
_hcd->hfnum_0_samples_##_letter++; \
_hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
default: \
_hcd->hfnum_other_samples_##_letter++; \
_hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
} \
} \
}
#else
#define dwc_sample_frrem(_hcd, _qh, _letter)
#endif
#endif
#endif /* DWC_DEVICE_ONLY */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_hcd.h
|
C
|
apache-2.0
| 23,319
|
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
* $Revision: #12 $
* $Date: 2011/10/26 $
* $Change: 1873028 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_DEVICE_ONLY
#ifndef __DWC_HCD_IF_H__
#define __DWC_HCD_IF_H__
#include "dwc_otg_core_if.h"
/** @file
* This file defines DWC_OTG HCD Core API.
*/
struct dwc_otg_hcd;
typedef struct dwc_otg_hcd dwc_otg_hcd_t;
struct dwc_otg_hcd_urb;
typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
/** @name HCD Function Driver Callbacks */
/** @{ */
/** This function is called whenever core switches to host mode. */
typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
/** This function is called when device has been disconnected */
typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle,
uint32_t * hub_addr,
uint32_t * port_addr);
/** Via this function HCD core gets device speed */
typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle);
/** This function is called when urb is completed */
typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle,
dwc_otg_hcd_urb_t * dwc_otg_urb,
int32_t status);
/** Via this function HCD core gets b_hnp_enable parameter */
typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
struct dwc_otg_hcd_function_ops {
dwc_otg_hcd_start_cb_t start;
dwc_otg_hcd_disconnect_cb_t disconnect;
dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
dwc_otg_hcd_speed_from_urb_cb_t speed;
dwc_otg_hcd_complete_urb_cb_t complete;
dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
};
/** @} */
/** @name HCD Core API */
/** @{ */
/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
extern _LONG_CALL_ dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
/** This function should be called to initiate HCD Core.
*
* @param hcd The HCD
* @param core_if The DWC_OTG Core
*
* Returns -DWC_E_NO_MEMORY if no enough memory.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
/** Frees HCD
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
/** This function should be called on every hardware interrupt.
*
* @param dwc_otg_hcd The HCD
*
* Returns non zero if interrupt is handled
* Return 0 if interrupt is not handled
*/
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
/**
* Returns private data set by
* dwc_otg_hcd_set_priv_data function.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
/**
* Set private data.
*
* @param hcd The HCD
* @param priv_data pointer to be stored in private data
*/
extern _LONG_CALL_ void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
/**
* This function initializes the HCD Core.
*
* @param hcd The HCD
* @param fops The Function Driver Operations data structure containing pointers to all callbacks.
*
* Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
struct dwc_otg_hcd_function_ops *fops);
/**
* Halts the DWC_otg host mode operations in a clean manner. USB transfers are
* stopped.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
/**
* Handles hub class-specific requests.
*
* @param dwc_otg_hcd The HCD
* @param typeReq Request Type
* @param wValue wValue from control request
* @param wIndex wIndex from control request
* @param buf data buffer
* @param wLength data buffer length
*
* Returns -DWC_E_INVALID if invalid argument is passed
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
uint16_t typeReq, uint16_t wValue,
uint16_t wIndex, uint8_t * buf,
uint16_t wLength);
/**
* Returns otg port number.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
/**
* Returns OTG version - either 1.3 or 2.0.
*
* @param core_if The core_if structure pointer
*/
extern _LONG_CALL_ uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
/**
* Returns 1 if currently core is acting as B host, and 0 otherwise.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
/**
* Returns current frame number.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
/**
* Dumps hcd state.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
/**
* Dump the average frame remaining at SOF. This can be used to
* determine average interrupt latency. Frame remaining is also shown for
* start transfer and two additional sample points.
* Currently this function is not implemented.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
/**
* Sends LPM transaction to the local device.
*
* @param hcd The HCD
* @param devaddr Device Address
* @param hird Host initiated resume duration
* @param bRemoteWake Value of bRemoteWake field in LPM transaction
*
* Returns negative value if sending LPM transaction was not succeeded.
* Returns 0 on success.
*/
extern _LONG_CALL_ int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
uint8_t hird, uint8_t bRemoteWake);
/* URB interface */
/**
* Allocates memory for dwc_otg_hcd_urb structure.
* Allocated memory should be freed by call of DWC_FREE.
*
* @param hcd The HCD
* @param iso_desc_count Count of ISOC descriptors
* @param atomic_alloc Specefies whether to perform atomic allocation.
*/
extern _LONG_CALL_ dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
int iso_desc_count,
int atomic_alloc);
/**
* Set pipe information in URB.
*
* @param hcd_urb DWC_OTG URB
* @param devaddr Device Address
* @param ep_num Endpoint Number
* @param ep_type Endpoint Type
* @param ep_dir Endpoint Direction
* @param mps Max Packet Size
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
uint8_t devaddr, uint8_t ep_num,
uint8_t ep_type, uint8_t ep_dir,
uint16_t mps);
/* Transfer flags */
#define URB_GIVEBACK_ASAP 0x1
#define URB_SEND_ZERO_PACKET 0x2
/**
* Sets dwc_otg_hcd_urb parameters.
*
* @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
* @param urb_handle Unique handle for request, this will be passed back
* to function driver in completion callback.
* @param buf The buffer for the data
* @param dma The DMA buffer for the data
* @param buflen Transfer length
* @param sp Buffer for setup data
* @param sp_dma DMA address of setup data buffer
* @param flags Transfer flags
* @param interval Polling interval for interrupt or isochronous transfers.
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
void *urb_handle, void *buf,
dwc_dma_t dma, uint32_t buflen, void *sp,
dwc_dma_t sp_dma, uint32_t flags,
uint16_t interval);
/** Gets status from dwc_otg_hcd_urb
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
/** Gets actual length from dwc_otg_hcd_urb
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
dwc_otg_urb);
/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
dwc_otg_urb);
/** Set ISOC descriptor offset and length
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
* @param offset Offset from beginig of buffer.
* @param length Transaction length
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
int desc_num, uint32_t offset,
uint32_t length);
/** Get status of ISOC descriptor, specified by desc_num
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
dwc_otg_urb, int desc_num);
/** Get actual length of ISOC descriptor, specified by desc_num
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
dwc_otg_urb,
int desc_num);
/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
*
* @param dwc_otg_hcd The HCD
* @param dwc_otg_urb DWC_OTG URB
* @param ep_handle Out parameter for returning endpoint handle
* @param atomic_alloc Flag to do atomic allocation if needed
*
* Returns -DWC_E_NO_DEVICE if no device is connected.
* Returns -DWC_E_NO_MEMORY if there is no enough memory.
* Returns 0 on success.
*/
extern _LONG_CALL_ int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
dwc_otg_hcd_urb_t * dwc_otg_urb,
void **ep_handle, int atomic_alloc);
/** De-queue the specified URB
*
* @param dwc_otg_hcd The HCD
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
dwc_otg_hcd_urb_t * dwc_otg_urb);
/** Frees resources in the DWC_otg controller related to a given endpoint.
* Any URBs for the endpoint must already be dequeued.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
* @param retry Number of retries if there are queued transfers.
*
* Returns -DWC_E_INVALID if invalid arguments are passed.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
int retry);
/* Resets the data toggle in qh structure. This function can be called from
* usb_clear_halt routine.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
*
* Returns -DWC_E_INVALID if invalid arguments are passed.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
/** Returns 1 if status of specified port is changed and 0 otherwise.
*
* @param hcd The HCD
* @param port Port number
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
/** Call this function to check if bandwidth was allocated for specified endpoint.
* Only for ISOC and INTERRUPT endpoints.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
void *ep_handle);
/** Call this function to check if bandwidth was freed for specified endpoint.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
/** Returns bandwidth allocated for specified endpoint in microseconds.
* Only for ISOC and INTERRUPT endpoints.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
void *ep_handle);
/** @} */
#endif /* __DWC_HCD_IF_H__ */
#endif /* DWC_DEVICE_ONLY */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_hcd_if.h
|
C
|
apache-2.0
| 13,528
|
#ifndef _DWC_OS_DEP_H_
#define _DWC_OS_DEP_H_
#include "usb_errno.h"
#endif /* _DWC_OS_DEP_H_ */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_os_dep.h
|
C
|
apache-2.0
| 98
|
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
* $Revision: #49 $
* $Date: 2013/05/16 $
* $Change: 2231774 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_HOST_ONLY
#if !defined(__DWC_PCD_H__)
#define __DWC_PCD_H__
#include "dwc_otg_os_dep.h"
#include "usb.h"
#include "dwc_otg_cil.h"
#include "dwc_otg_pcd_if.h"
struct cfiobject;
/**
* @file
*
* This file contains the structures, constants, and interfaces for
* the Perpherial Contoller Driver (PCD).
*
* The Peripheral Controller Driver (PCD) for Linux will implement the
* Gadget API, so that the existing Gadget drivers can be used. For
* the Mass Storage Function driver the File-backed USB Storage Gadget
* (FBS) driver will be used. The FBS driver supports the
* Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
* transports.
*
*/
/** Invalid DMA Address */
#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0)
/** Max Transfer size for any EP */
#define DDMA_MAX_TRANSFER_SIZE 65535
/**
* Get the pointer to the core_if from the pcd pointer.
*/
#define GET_CORE_IF( _pcd ) (_pcd->core_if)
/**
* States of EP0.
*/
typedef enum ep0_state {
EP0_DISCONNECT, /* no host */
EP0_IDLE,
EP0_IN_DATA_PHASE,
EP0_OUT_DATA_PHASE,
EP0_IN_STATUS_PHASE,
EP0_OUT_STATUS_PHASE,
EP0_STALL,
} ep0state_e;
/** Fordward declaration.*/
struct dwc_otg_pcd;
/** DWC_otg iso request structure.
*
*/
typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
#ifdef DWC_UTE_PER_IO
XXX
/**
* This shall be the exact analogy of the same type structure defined in the
* usb_gadget.h. Each descriptor contains
*/
struct dwc_iso_pkt_desc_port {
uint32_t offset;
uint32_t length; /* expected length */
uint32_t actual_length;
uint32_t status;
};
struct dwc_iso_xreq_port {
/** transfer/submission flag */
uint32_t tr_sub_flags;
/** Start the request ASAP */
#define DWC_EREQ_TF_ASAP 0x00000002
/** Just enqueue the request w/o initiating a transfer */
#define DWC_EREQ_TF_ENQUEUE 0x00000004
/**
* count of ISO packets attached to this request - shall
* not exceed the pio_alloc_pkt_count
*/
uint32_t pio_pkt_count;
/** count of ISO packets allocated for this request */
uint32_t pio_alloc_pkt_count;
/** number of ISO packet errors */
uint32_t error_count;
/** reserved for future extension */
uint32_t res;
/** Will be allocated and freed in the UTE gadget and based on the CFC value */
struct dwc_iso_pkt_desc_port *per_io_frame_descs;
};
#endif
/** DWC_otg request structure.
* This structure is a list of requests.
*/
typedef struct dwc_otg_pcd_request {
void *priv;
void *buf;
dwc_dma_t dma;
uint32_t length;
uint32_t actual;
unsigned sent_zlp:1;
/**
* Used instead of original buffer if
* it(physical address) is not dword-aligned.
**/
uint8_t *dw_align_buf;
dwc_dma_t dw_align_buf_dma;
DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
#ifdef DWC_UTE_PER_IO
struct dwc_iso_xreq_port ext_req;
//void *priv_ereq_nport; /* */
#endif
} dwc_otg_pcd_request_t;
#ifndef CONTAINER_OF
#define CONTAINER_OF(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#endif
DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
/** PCD EP structure.
* This structure describes an EP, there is an array of EPs in the PCD
* structure.
*/
typedef struct dwc_otg_pcd_ep {
/** USB EP Descriptor */
const usb_endpoint_descriptor_t *desc;
/** queue of dwc_otg_pcd_requests. */
struct req_list queue;
unsigned stopped:1;
unsigned disabling:1;
unsigned dma:1;
unsigned queue_sof:1;
#ifdef DWC_EN_ISOC
/** ISOC req handle passed */
void *iso_req_handle;
#endif //_EN_ISOC_
/** DWC_otg ep data. */
dwc_ep_t dwc_ep;
/** Pointer to PCD */
struct dwc_otg_pcd *pcd;
void *priv;
} dwc_otg_pcd_ep_t;
/** DWC_otg PCD Structure.
* This structure encapsulates the data for the dwc_otg PCD.
*/
struct dwc_otg_pcd {
const struct dwc_otg_pcd_function_ops *fops;
/** The DWC otg device pointer */
struct dwc_otg_device *otg_dev;
/** Core Interface */
dwc_otg_core_if_t *core_if;
/** State of EP0 */
ep0state_e ep0state;
/** EP0 Request is pending */
unsigned ep0_pending:1;
/** Indicates when SET CONFIGURATION Request is in process */
unsigned request_config:1;
/** The state of the Remote Wakeup Enable. */
unsigned remote_wakeup_enable:1;
/** The state of the B-Device HNP Enable. */
unsigned b_hnp_enable:1;
/** The state of A-Device HNP Support. */
unsigned a_hnp_support:1;
/** The state of the A-Device Alt HNP support. */
unsigned a_alt_hnp_support:1;
/** Count of pending Requests */
unsigned request_pending;
/** SETUP packet for EP0
* This structure is allocated as a DMA buffer on PCD initialization
* with enough space for up to 3 setup packets.
*/
union {
usb_device_request_t req;
uint32_t d32[2];
} *setup_pkt;
dwc_dma_t setup_pkt_dma_handle;
/* Additional buffer and flag for CTRL_WR premature case */
uint8_t *backup_buf;
unsigned data_terminated;
/** 2-byte dma buffer used to return status from GET_STATUS */
uint16_t *status_buf;
dwc_dma_t status_buf_dma_handle;
/** EP0 */
dwc_otg_pcd_ep_t ep0;
/** Array of IN EPs. */
dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
/** Array of OUT EPs. */
dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
/** number of valid EPs in the above array. */
// unsigned num_eps : 4;
dwc_spinlock_t *lock;
/** Tasklet to defer starting of TEST mode transmissions until
* Status Phase has been completed.
*/
dwc_tasklet_t *test_mode_tasklet;
/** Tasklet to delay starting of xfer in DMA mode */
dwc_tasklet_t *start_xfer_tasklet;
/** The test mode to enter when the tasklet is executed. */
unsigned test_mode;
/** The cfi_api structure that implements most of the CFI API
* and OTG specific core configuration functionality
*/
#ifdef DWC_UTE_CFI
struct cfiobject *cfi;
#endif
};
//FIXME this functions should be static, and this prototypes should be removed
extern _LONG_CALL_ void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
extern _LONG_CALL_ void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
dwc_otg_pcd_request_t * req, int32_t status);
_LONG_CALL_ void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
void *req_handle);
extern _LONG_CALL_ void dwc_otg_pcd_start_iso_ddma(dwc_otg_core_if_t * core_if,
dwc_otg_pcd_ep_t * ep);
extern _LONG_CALL_ void do_test_mode(void *data);
extern _LONG_CALL_ void dwc_pcd_data_init(VOID);
#endif
#endif /* DWC_HOST_ONLY */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_pcd.h
|
C
|
apache-2.0
| 8,317
|
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
* $Revision: #13 $
* $Date: 2012/12/12 $
* $Change: 2125019 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_HOST_ONLY
#if !defined(__DWC_PCD_IF_H__)
#define __DWC_PCD_IF_H__
//#include "dwc_os.h"
#include "dwc_otg_core_if.h"
/** @file
* This file defines DWC_OTG PCD Core API.
*/
struct dwc_otg_pcd;
typedef struct dwc_otg_pcd dwc_otg_pcd_t;
/** Maxpacket size for EP0 */
#define MAX_EP0_SIZE 64
/** Maxpacket size for any EP */
#define MAX_PACKET_SIZE 2048
/** @name Function Driver Callbacks */
/** @{ */
/** This function will be called whenever a previously queued request has
* completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a
* failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
* or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
* parameters. */
typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int32_t status,
uint32_t actual);
/**
* This function will be called whenever a previousle queued ISOC request has
* completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
* function.
* The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
* functions.
*/
typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int proc_buf_num);
/** This function should handle any SETUP request that cannot be handled by the
* PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
* class-specific requests, etc. The function must non-blocking.
*
* Returns 0 on success.
* Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
* Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
* Returns -DWC_E_SHUTDOWN on any other error. */
typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
/** This is called whenever the device has been disconnected. The function
* driver should take appropriate action to clean up all pending requests in the
* PCD Core, remove all endpoints (except ep0), and initialize back to reset
* state. */
typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has been connected. */
typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
/** This function is called when device has been suspended */
typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has received LPM tokens, i.e.
* device has been sent to sleep state. */
typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has been resumed
* from suspend(L2) or L1 sleep state. */
typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called whenever hnp params has been changed.
* User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
* to get hnp parameters. */
typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called whenever USB RESET is detected. */
typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
/**
*
* @param ep_handle Void pointer to the usb_ep structure
* @param ereq_port Pointer to the extended request structure created in the
* portable part.
*/
typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int32_t status,
void *ereq_port);
/** Function Driver Ops Data Structure */
struct dwc_otg_pcd_function_ops {
dwc_connect_cb_t connect;
dwc_disconnect_cb_t disconnect;
dwc_setup_cb_t setup;
dwc_completion_cb_t complete;
dwc_isoc_completion_cb_t isoc_complete;
dwc_suspend_cb_t suspend;
dwc_sleep_cb_t sleep;
dwc_resume_cb_t resume;
dwc_reset_cb_t reset;
dwc_hnp_params_changed_cb_t hnp_changed;
cfi_setup_cb_t cfi_setup;
#ifdef DWC_UTE_PER_IO
xiso_completion_cb_t xisoc_complete;
#endif
};
/** @} */
/** @name Function Driver Functions */
/** @{ */
/** Call this function to get pointer on dwc_otg_pcd_t,
* this pointer will be used for all PCD API functions.
*
* @param core_if The DWC_OTG Core
*/
extern _LONG_CALL_ dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
/** Frees PCD allocated by dwc_otg_pcd_init
*
* @param pcd The PCD
*/
extern _LONG_CALL_ void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
/** Call this to bind the function driver to the PCD Core.
*
* @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
* @param fops The Function Driver Ops data structure containing pointers to all callbacks.
*/
extern _LONG_CALL_ void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
const struct dwc_otg_pcd_function_ops *fops);
/** Enables an endpoint for use. This function enables an endpoint in
* the PCD. The endpoint is described by the ep_desc which has the
* same format as a USB ep descriptor. The ep_handle parameter is used to refer
* to the endpoint from other API functions and in callbacks. Normally this
* should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
* core for that interface.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success.
*
* @param pcd The PCD
* @param ep_desc Endpoint descriptor
* @param ep_handle Handle on endpoint, that will be used to identify endpoint.
*/
extern _LONG_CALL_ int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
const uint8_t * ep_desc, void *ep_handle);
/** Disable the endpoint referenced by ep_handle.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error occurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
/** Queue a data transfer request on the endpoint referenced by ep_handle.
* After the transfer is completes, the complete callback will be called with
* the request status.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param buf The buffer for the data
* @param dma_buf The DMA buffer for the data
* @param buflen The length of the data transfer
* @param zero Specifies whether to send zero length last packet.
* @param req_handle Set this handle to any value to use to reference this
* request in the ep_dequeue function or from the complete callback
* @param atomic_alloc If driver need to perform atomic allocations
* for internal data structures.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf, dwc_dma_t dma_buf,
uint32_t buflen, int zero, void *req_handle,
int atomic_alloc);
#ifdef DWC_UTE_PER_IO
XXXX
/**
*
* @param ereq_nonport Pointer to the extended request part of the
* usb_request structure defined in usb_gadget.h file.
*/
extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf, dwc_dma_t dma_buf,
uint32_t buflen, int zero,
void *req_handle, int atomic_alloc,
void *ereq_nonport);
#endif
/** De-queue the specified data transfer that has not yet completed.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle);
/** Halt (STALL) an endpoint or clear it.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
/** This function should be called on every hardware interrupt */
extern _LONG_CALL_ int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
/** This function returns current frame number */
extern _LONG_CALL_ int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
/**
* Start isochronous transfers on the endpoint referenced by ep_handle.
* For isochronous transfers duble buffering is used.
* After processing each of buffers comlete callback will be called with
* status for each transaction.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param buf0 The virtual address of first data buffer
* @param buf1 The virtual address of second data buffer
* @param dma0 The DMA address of first data buffer
* @param dma1 The DMA address of second data buffer
* @param sync_frame Data pattern frame number
* @param dp_frame Data size for pattern frame
* @param data_per_frame Data size for regular frame
* @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
* @param buf_proc_intrvl Interval of ISOC Buffer processing
* @param req_handle Handle of ISOC request
* @param atomic_alloc Specefies whether to perform atomic allocation for
* internal data structures.
*
* Returns -DWC_E_NO_MEMORY if there is no enough memory.
* Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
* Returns -DW_E_SHUTDOWN for any other error.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf0, uint8_t * buf1,
dwc_dma_t dma0, dwc_dma_t dma1,
int sync_frame, int dp_frame,
int data_per_frame, int data_per_frame1, int start_frame,
int buf_proc_intrvl, void *req_handle,
int atomic_alloc);
/** Stop ISOC transfers on endpoint referenced by ep_handle.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param req_handle Handle of ISOC request
*
* Returns -DWC_E_INVALID if incorrect arguments are passed to the function
* Returns 0 on success
*/
_LONG_CALL_ int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle);
/** Get ISOC packet status.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param iso_req_handle Isochronoush request handle
* @param packet Number of packet
* @param status Out parameter for returning status
* @param actual Out parameter for returning actual length
* @param offset Out parameter for returning offset
*
*/
extern _LONG_CALL_ void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
void *ep_handle,
void *iso_req_handle, int packet,
int *status, int *actual,
int *offset);
/** Get ISOC packet count.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param iso_req_handle
*/
extern _LONG_CALL_ int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
void *ep_handle,
void *iso_req_handle);
/** This function starts the SRP Protocol if no session is in progress. If
* a session is already in progress, but the device is suspended,
* remote wakeup signaling is started.
*/
extern _LONG_CALL_ int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
/** This function returns 1 if LPM Errata support is enabled, and 0 otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_is_besl_enabled(dwc_otg_pcd_t * pcd);
/** This function returns baseline_besl module parametr. */
extern _LONG_CALL_ int dwc_otg_pcd_get_param_baseline_besl(dwc_otg_pcd_t * pcd);
/** This function returns deep_besl module parametr. */
extern _LONG_CALL_ int dwc_otg_pcd_get_param_deep_besl(dwc_otg_pcd_t * pcd);
/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
/** Initiate SRP */
extern _LONG_CALL_ void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
/** Starts remote wakeup signaling. */
extern _LONG_CALL_ void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
/** Starts micorsecond soft disconnect. */
extern _LONG_CALL_ void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
/** This function returns whether device is dualspeed.*/
extern _LONG_CALL_ uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
/** This function returns whether device is otg. */
extern _LONG_CALL_ uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
/** These functions allow to get hnp parameters */
extern _LONG_CALL_ uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
extern _LONG_CALL_ uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
extern _LONG_CALL_ uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
/** CFI specific Interface functions */
/** Allocate a cfi buffer */
extern _LONG_CALL_ uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
dwc_dma_t * addr, size_t buflen,
int flags);
/******************************************************************************/
/** @} */
#endif /* __DWC_PCD_IF_H__ */
#endif /* DWC_HOST_ONLY */
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_pcd_if.h
|
C
|
apache-2.0
| 15,107
|
/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
* $Revision: #99 $
* $Date: 2012/12/10 $
* $Change: 2123206 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_REGS_H__
#define __DWC_OTG_REGS_H__
#include "dwc_otg_core_if.h"
/**
* @file
*
* This file contains the data structures for accessing the DWC_otg core registers.
*
* The application interfaces with the HS OTG core by reading from and
* writing to the Control and Status Register (CSR) space through the
* AHB Slave interface. These registers are 32 bits wide, and the
* addresses are 32-bit-block aligned.
* CSRs are classified as follows:
* - Core Global Registers
* - Device Mode Registers
* - Device Global Registers
* - Device Endpoint Specific Registers
* - Host Mode Registers
* - Host Global Registers
* - Host Port CSRs
* - Host Channel Specific Registers
*
* Only the Core Global registers can be accessed in both Device and
* Host modes. When the HS OTG core is operating in one mode, either
* Device or Host, the application must not access registers from the
* other mode. When the core switches from one mode to another, the
* registers in the new mode of operation must be reprogrammed as they
* would be after a power-on reset.
*/
/****************************************************************************/
/** DWC_otg Core registers .
* The dwc_otg_core_global_regs structure defines the size
* and relative field offsets for the Core Global registers.
*/
typedef struct dwc_otg_core_global_regs {
/** OTG Control and Status Register. <i>Offset: 000h</i> */
volatile uint32_t gotgctl;
/** OTG Interrupt Register. <i>Offset: 004h</i> */
volatile uint32_t gotgint;
/**Core AHB Configuration Register. <i>Offset: 008h</i> */
volatile uint32_t gahbcfg;
#define DWC_GLBINTRMASK 0x0001
#define DWC_DMAENABLE 0x0020
#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000
#define DWC_PTXEMPTYLVL_EMPTY 0x0100
#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000
/**Core USB Configuration Register. <i>Offset: 00Ch</i> */
volatile uint32_t gusbcfg;
/**Core Reset Register. <i>Offset: 010h</i> */
volatile uint32_t grstctl;
/**Core Interrupt Register. <i>Offset: 014h</i> */
volatile uint32_t gintsts;
/**Core Interrupt Mask Register. <i>Offset: 018h</i> */
volatile uint32_t gintmsk;
/**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */
volatile uint32_t grxstsr;
/**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/
volatile uint32_t grxstsp;
/**Receive FIFO Size Register. <i>Offset: 024h</i> */
volatile uint32_t grxfsiz;
/**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */
volatile uint32_t gnptxfsiz;
/**Non Periodic Transmit FIFO/Queue Status Register (Read
* Only). <i>Offset: 02Ch</i> */
volatile uint32_t gnptxsts;
/**I2C Access Register. <i>Offset: 030h</i> */
volatile uint32_t gi2cctl;
/**PHY Vendor Control Register. <i>Offset: 034h</i> */
volatile uint32_t gpvndctl;
/**General Purpose Input/Output Register. <i>Offset: 038h</i> */
volatile uint32_t ggpio;
/**User ID Register. <i>Offset: 03Ch</i> */
volatile uint32_t guid;
/**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */
volatile uint32_t gsnpsid;
/**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */
volatile uint32_t ghwcfg1;
/**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */
volatile uint32_t ghwcfg2;
#define DWC_SLAVE_ONLY_ARCH 0
#define DWC_EXT_DMA_ARCH 1
#define DWC_INT_DMA_ARCH 2
#define DWC_MODE_HNP_SRP_CAPABLE 0
#define DWC_MODE_SRP_ONLY_CAPABLE 1
#define DWC_MODE_NO_HNP_SRP_CAPABLE 2
#define DWC_MODE_SRP_CAPABLE_DEVICE 3
#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
#define DWC_MODE_SRP_CAPABLE_HOST 5
#define DWC_MODE_NO_SRP_CAPABLE_HOST 6
/**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */
volatile uint32_t ghwcfg3;
/**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/
volatile uint32_t ghwcfg4;
/** Core LPM Configuration register <i>Offset: 054h</i>*/
volatile uint32_t glpmcfg;
/** Global PowerDn Register <i>Offset: 058h</i> */
volatile uint32_t gpwrdn;
/** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */
volatile uint32_t gdfifocfg;
/** ADP Control Register <i>Offset: 060h</i> */
volatile uint32_t adpctl;
/** Reserved <i>Offset: 064h-0FFh</i> */
volatile uint32_t reserved39[39];
/** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
volatile uint32_t hptxfsiz;
/** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
otherwise Device Transmit FIFO#n Register.
* <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
volatile uint32_t dtxfsiz[15];
} dwc_otg_core_global_regs_t;
/**
* This union represents the bit fields of the Core OTG Control
* and Status Register (GOTGCTL). Set the bits using the bit
* fields then write the <i>d32</i> value to the register.
*/
typedef union gotgctl_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned sesreqscs:1;
unsigned sesreq:1;
unsigned vbvalidoven:1;
unsigned vbvalidovval:1;
unsigned avalidoven:1;
unsigned avalidovval:1;
unsigned bvalidoven:1;
unsigned bvalidovval:1;
unsigned hstnegscs:1;
unsigned hnpreq:1;
unsigned hstsethnpen:1;
unsigned devhnpen:1;
unsigned reserved12_15:4;
unsigned conidsts:1;
unsigned dbnctime:1;
unsigned asesvld:1;
unsigned bsesvld:1;
unsigned otgver:1;
unsigned reserved1:1;
unsigned multvalidbc:5;
unsigned chirpen:1;
unsigned reserved28_31:4;
} b;
} gotgctl_data_t;
/**
* This union represents the bit fields of the Core OTG Interrupt Register
* (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i>
* value to the register.
*/
typedef union gotgint_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Current Mode */
unsigned reserved0_1:2;
/** Session End Detected */
unsigned sesenddet:1;
unsigned reserved3_7:5;
/** Session Request Success Status Change */
unsigned sesreqsucstschng:1;
/** Host Negotiation Success Status Change */
unsigned hstnegsucstschng:1;
unsigned reserved10_16:7;
/** Host Negotiation Detected */
unsigned hstnegdet:1;
/** A-Device Timeout Change */
unsigned adevtoutchng:1;
/** Debounce Done */
unsigned debdone:1;
/** Multi-Valued input changed */
unsigned mvic:1;
unsigned reserved31_21:11;
} b;
} gotgint_data_t;
/**
* This union represents the bit fields of the Core AHB Configuration
* Register (GAHBCFG). Set/clear the bits using the bit fields then
* write the <i>d32</i> value to the register.
*/
typedef union gahbcfg_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned glblintrmsk:1;
#define DWC_GAHBCFG_GLBINT_ENABLE 1
unsigned hburstlen:4;
#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0
#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1
#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3
#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5
#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7
unsigned dmaenable:1;
#define DWC_GAHBCFG_DMAENABLE 1
unsigned reserved:1;
unsigned nptxfemplvl_txfemplvl:1;
unsigned ptxfemplvl:1;
#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1
#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
unsigned reserved9_20:12;
unsigned remmemsupp:1;
unsigned notialldmawrit:1;
unsigned ahbsingle:1;
unsigned reserved24_31:8;
} b;
} gahbcfg_data_t;
/**
* This union represents the bit fields of the Core USB Configuration
* Register (GUSBCFG). Set the bits using the bit fields then write
* the <i>d32</i> value to the register.
*/
typedef union gusbcfg_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned toutcal:3;
unsigned phyif:1;
unsigned ulpi_utmi_sel:1;
unsigned fsintf:1;
unsigned physel:1;
unsigned ddrsel:1;
unsigned srpcap:1;
unsigned hnpcap:1;
unsigned usbtrdtim:4;
unsigned reserved1:1;
unsigned phylpwrclksel:1;
unsigned otgutmifssel:1;
unsigned ulpi_fsls:1;
unsigned ulpi_auto_res:1;
unsigned ulpi_clk_sus_m:1;
unsigned ulpi_ext_vbus_drv:1;
unsigned ulpi_int_vbus_indicator:1;
unsigned term_sel_dl_pulse:1;
unsigned indicator_complement:1;
unsigned indicator_pass_through:1;
unsigned ulpi_int_prot_dis:1;
unsigned ic_usb_cap:1;
unsigned ic_traffic_pull_remove:1;
unsigned tx_end_delay:1;
unsigned force_host_mode:1;
unsigned force_dev_mode:1;
unsigned reserved31:1;
} b;
} gusbcfg_data_t;
/**
* This union represents the bit fields of the Core Reset Register
* (GRSTCTL). Set/clear the bits using the bit fields then write the
* <i>d32</i> value to the register.
*/
typedef union grstctl_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Core Soft Reset (CSftRst) (Device and Host)
*
* The application can flush the control logic in the
* entire core using this bit. This bit resets the
* pipelines in the AHB Clock domain as well as the
* PHY Clock domain.
*
* The state machines are reset to an IDLE state, the
* control bits in the CSRs are cleared, all the
* transmit FIFOs and the receive FIFO are flushed.
*
* The status mask bits that control the generation of
* the interrupt, are cleared, to clear the
* interrupt. The interrupt status bits are not
* cleared, so the application can get the status of
* any events that occurred in the core after it has
* set this bit.
*
* Any transactions on the AHB are terminated as soon
* as possible following the protocol. Any
* transactions on the USB are terminated immediately.
*
* The configuration settings in the CSRs are
* unchanged, so the software doesn't have to
* reprogram these registers (Device
* Configuration/Host Configuration/Core System
* Configuration/Core PHY Configuration).
*
* The application can write to this bit, any time it
* wants to reset the core. This is a self clearing
* bit and the core clears this bit after all the
* necessary logic is reset in the core, which may
* take several clocks, depending on the current state
* of the core.
*/
unsigned csftrst:1;
/** Hclk Soft Reset
*
* The application uses this bit to reset the control logic in
* the AHB clock domain. Only AHB clock domain pipelines are
* reset.
*/
unsigned hsftrst:1;
/** Host Frame Counter Reset (Host Only)<br>
*
* The application can reset the (micro)frame number
* counter inside the core, using this bit. When the
* (micro)frame counter is reset, the subsequent SOF
* sent out by the core, will have a (micro)frame
* number of 0.
*/
unsigned hstfrm:1;
/** In Token Sequence Learning Queue Flush
* (INTknQFlsh) (Device Only)
*/
unsigned intknqflsh:1;
/** RxFIFO Flush (RxFFlsh) (Device and Host)
*
* The application can flush the entire Receive FIFO
* using this bit. The application must first
* ensure that the core is not in the middle of a
* transaction. The application should write into
* this bit, only after making sure that neither the
* DMA engine is reading from the RxFIFO nor the MAC
* is writing the data in to the FIFO. The
* application should wait until the bit is cleared
* before performing any other operations. This bit
* will takes 8 clocks (slowest of PHY or AHB clock)
* to clear.
*/
unsigned rxfflsh:1;
/** TxFIFO Flush (TxFFlsh) (Device and Host).
*
* This bit is used to selectively flush a single or
* all transmit FIFOs. The application must first
* ensure that the core is not in the middle of a
* transaction. The application should write into
* this bit, only after making sure that neither the
* DMA engine is writing into the TxFIFO nor the MAC
* is reading the data out of the FIFO. The
* application should wait until the core clears this
* bit, before performing any operations. This bit
* will takes 8 clocks (slowest of PHY or AHB clock)
* to clear.
*/
unsigned txfflsh:1;
/** TxFIFO Number (TxFNum) (Device and Host).
*
* This is the FIFO number which needs to be flushed,
* using the TxFIFO Flush bit. This field should not
* be changed until the TxFIFO Flush bit is cleared by
* the core.
* - 0x0 : Non Periodic TxFIFO Flush
* - 0x1 : Periodic TxFIFO #1 Flush in device mode
* or Periodic TxFIFO in host mode
* - 0x2 : Periodic TxFIFO #2 Flush in device mode.
* - ...
* - 0xF : Periodic TxFIFO #15 Flush in device mode
* - 0x10: Flush all the Transmit NonPeriodic and
* Transmit Periodic FIFOs in the core
*/
unsigned txfnum:5;
/** Reserved */
unsigned reserved11_29:19;
/** DMA Request Signal. Indicated DMA request is in
* probress. Used for debug purpose. */
unsigned dmareq:1;
/** AHB Master Idle. Indicates the AHB Master State
* Machine is in IDLE condition. */
unsigned ahbidle:1;
} b;
} grstctl_t;
/**
* This union represents the bit fields of the Core Interrupt Mask
* Register (GINTMSK). Set/clear the bits using the bit fields then
* write the <i>d32</i> value to the register.
*/
typedef union gintmsk_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned reserved0:1;
unsigned modemismatch:1;
unsigned otgintr:1;
unsigned sofintr:1;
unsigned rxstsqlvl:1;
unsigned nptxfempty:1;
unsigned ginnakeff:1;
unsigned goutnakeff:1;
unsigned ulpickint:1;
unsigned i2cintr:1;
unsigned erlysuspend:1;
unsigned usbsuspend:1;
unsigned usbreset:1;
unsigned enumdone:1;
unsigned isooutdrop:1;
unsigned eopframe:1;
unsigned restoredone:1;
unsigned epmismatch:1;
unsigned inepintr:1;
unsigned outepintr:1;
unsigned incomplisoin:1;
unsigned incomplisoout:1;
unsigned fetsusp:1;
unsigned resetdet:1;
unsigned portintr:1;
unsigned hcintr:1;
unsigned ptxfempty:1;
unsigned lpmtranrcvd:1;
unsigned conidstschng:1;
unsigned disconnect:1;
unsigned sessreqintr:1;
unsigned wkupintr:1;
} b;
} gintmsk_data_t;
/**
* This union represents the bit fields of the Core Interrupt Register
* (GINTSTS). Set/clear the bits using the bit fields then write the
* <i>d32</i> value to the register.
*/
typedef union gintsts_data {
/** raw register data */
uint32_t d32;
#define DWC_SOF_INTR_MASK 0x0008
/** register bits */
struct {
#define DWC_HOST_MODE 1
unsigned curmode:1;
unsigned modemismatch:1;
unsigned otgintr:1;
unsigned sofintr:1;
unsigned rxstsqlvl:1;
unsigned nptxfempty:1;
unsigned ginnakeff:1;
unsigned goutnakeff:1;
unsigned ulpickint:1;
unsigned i2cintr:1;
unsigned erlysuspend:1;
unsigned usbsuspend:1;
unsigned usbreset:1;
unsigned enumdone:1;
unsigned isooutdrop:1;
unsigned eopframe:1;
unsigned restoredone:1;
unsigned epmismatch:1;
unsigned inepint:1;
unsigned outepintr:1;
unsigned incomplisoin:1;
unsigned incomplisoout:1;
unsigned fetsusp:1;
unsigned resetdet:1;
unsigned portintr:1;
unsigned hcintr:1;
unsigned ptxfempty:1;
unsigned lpmtranrcvd:1;
unsigned conidstschng:1;
unsigned disconnect:1;
unsigned sessreqintr:1;
unsigned wkupintr:1;
} b;
} gintsts_data_t;
/**
* This union represents the bit fields in the Device Receive Status Read and
* Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
* element then read out the bits using the <i>b</i>it elements.
*/
typedef union device_grxsts_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned epnum:4;
unsigned bcnt:11;
unsigned dpid:2;
#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet
#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete
#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK
#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
unsigned pktsts:4;
unsigned fn:4;
unsigned reserved25_31:7;
} b;
} device_grxsts_data_t;
/**
* This union represents the bit fields in the Host Receive Status Read and
* Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
* element then read out the bits using the <i>b</i>it elements.
*/
typedef union host_grxsts_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned chnum:4;
unsigned bcnt:11;
unsigned dpid:2;
unsigned pktsts:4;
#define DWC_GRXSTS_PKTSTS_IN 0x2
#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3
#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7
unsigned reserved21_31:11;
} b;
} host_grxsts_data_t;
/**
* This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
* GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
* then read out the bits using the <i>b</i>it elements.
*/
typedef union fifosize_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned startaddr:16;
unsigned depth:16;
} b;
} fifosize_data_t;
/**
* This union represents the bit fields in the Non-Periodic Transmit
* FIFO/Queue Status Register (GNPTXSTS). Read the register into the
* <i>d32</i> element then read out the bits using the <i>b</i>it
* elements.
*/
typedef union gnptxsts_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned nptxfspcavail:16;
unsigned nptxqspcavail:8;
/** Top of the Non-Periodic Transmit Request Queue
* - bit 24 - Terminate (Last entry for the selected
* channel/EP)
* - bits 26:25 - Token Type
* - 2'b00 - IN/OUT
* - 2'b01 - Zero Length OUT
* - 2'b10 - PING/Complete Split
* - 2'b11 - Channel Halt
* - bits 30:27 - Channel/EP Number
*/
unsigned nptxqtop_terminate:1;
unsigned nptxqtop_token:2;
unsigned nptxqtop_chnep:4;
unsigned reserved:1;
} b;
} gnptxsts_data_t;
/**
* This union represents the bit fields in the Transmit
* FIFO Status Register (DTXFSTS). Read the register into the
* <i>d32</i> element then read out the bits using the <i>b</i>it
* elements.
*/
typedef union dtxfsts_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned txfspcavail:16;
unsigned reserved:16;
} b;
} dtxfsts_data_t;
/**
* This union represents the bit fields in the I2C Control Register
* (I2CCTL). Read the register into the <i>d32</i> element then read out the
* bits using the <i>b</i>it elements.
*/
typedef union gi2cctl_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned rwdata:8;
unsigned regaddr:8;
unsigned addr:7;
unsigned i2cen:1;
unsigned ack:1;
unsigned i2csuspctl:1;
unsigned i2cdevaddr:2;
unsigned i2cdatse0:1;
unsigned reserved:1;
unsigned rw:1;
unsigned bsydne:1;
} b;
} gi2cctl_data_t;
/**
* This union represents the bit fields in the PHY Vendor Control Register
* (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
* bits using the <i>b</i>it elements.
*/
typedef union gpvndctl_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned regdata:8;
unsigned vctrl:8;
unsigned regaddr16_21:6;
unsigned regwr:1;
unsigned reserved23_24:2;
unsigned newregreq:1;
unsigned vstsbsy:1;
unsigned vstsdone:1;
unsigned reserved28_30:3;
unsigned disulpidrvr:1;
} b;
} gpvndctl_data_t;
/**
* This union represents the bit fields in the General Purpose
* Input/Output Register (GGPIO).
* Read the register into the <i>d32</i> element then read out the
* bits using the <i>b</i>it elements.
*/
typedef union ggpio_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned gpi:16;
unsigned gpo:16;
} b;
} ggpio_data_t;
/**
* This union represents the bit fields in the User ID Register
* (GUID). Read the register into the <i>d32</i> element then read out the
* bits using the <i>b</i>it elements.
*/
typedef union guid_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned rwdata:32;
} b;
} guid_data_t;
/**
* This union represents the bit fields in the Synopsys ID Register
* (GSNPSID). Read the register into the <i>d32</i> element then read out the
* bits using the <i>b</i>it elements.
*/
typedef union gsnpsid_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned rwdata:32;
} b;
} gsnpsid_data_t;
/**
* This union represents the bit fields in the User HW Config1
* Register. Read the register into the <i>d32</i> element then read
* out the bits using the <i>b</i>it elements.
*/
typedef union hwcfg1_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned ep_dir0:2;
unsigned ep_dir1:2;
unsigned ep_dir2:2;
unsigned ep_dir3:2;
unsigned ep_dir4:2;
unsigned ep_dir5:2;
unsigned ep_dir6:2;
unsigned ep_dir7:2;
unsigned ep_dir8:2;
unsigned ep_dir9:2;
unsigned ep_dir10:2;
unsigned ep_dir11:2;
unsigned ep_dir12:2;
unsigned ep_dir13:2;
unsigned ep_dir14:2;
unsigned ep_dir15:2;
} b;
} hwcfg1_data_t;
/**
* This union represents the bit fields in the User HW Config2
* Register. Read the register into the <i>d32</i> element then read
* out the bits using the <i>b</i>it elements.
*/
typedef union hwcfg2_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/* GHWCFG2 */
unsigned op_mode:3;
#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
unsigned architecture:2;
unsigned point2point:1;
unsigned hs_phy_type:2;
#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
unsigned fs_phy_type:2;
unsigned num_dev_ep:4;
unsigned num_host_chan:4;
unsigned perio_ep_supported:1;
unsigned dynamic_fifo:1;
unsigned multi_proc_int:1;
unsigned reserved21:1;
unsigned nonperio_tx_q_depth:2;
unsigned host_perio_tx_q_depth:2;
unsigned dev_token_q_depth:5;
unsigned otg_enable_ic_usb:1;
} b;
} hwcfg2_data_t;
/**
* This union represents the bit fields in the User HW Config3
* Register. Read the register into the <i>d32</i> element then read
* out the bits using the <i>b</i>it elements.
*/
typedef union hwcfg3_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/* GHWCFG3 */
unsigned xfer_size_cntr_width:4;
unsigned packet_size_cntr_width:3;
unsigned otg_func:1;
unsigned i2c:1;
unsigned vendor_ctrl_if:1;
unsigned optional_features:1;
unsigned synch_reset_type:1;
unsigned adp_supp:1;
unsigned otg_enable_hsic:1;
unsigned bc_support:1;
unsigned otg_lpm_en:1;
unsigned dfifo_depth:16;
} b;
} hwcfg3_data_t;
/**
* This union represents the bit fields in the User HW Config4
* Register. Read the register into the <i>d32</i> element then read
* out the bits using the <i>b</i>it elements.
*/
typedef union hwcfg4_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned num_dev_perio_in_ep:4;
unsigned power_optimiz:1;
unsigned min_ahb_freq:1;
unsigned hiber:1;
unsigned xhiber:1;
unsigned reserved:6;
unsigned utmi_phy_data_width:2;
unsigned num_dev_mode_ctrl_ep:4;
unsigned iddig_filt_en:1;
unsigned vbus_valid_filt_en:1;
unsigned a_valid_filt_en:1;
unsigned b_valid_filt_en:1;
unsigned session_end_filt_en:1;
unsigned ded_fifo_en:1;
unsigned num_in_eps:4;
unsigned desc_dma:1;
unsigned desc_dma_dyn:1;
} b;
} hwcfg4_data_t;
/**
* This union represents the bit fields of the Core LPM Configuration
* Register (GLPMCFG). Set the bits using bit fields then write
* the <i>d32</i> value to the register.
*/
typedef union glpmctl_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** LPM-Capable (LPMCap) (Device and Host)
* The application uses this bit to control
* the DWC_otg core LPM capabilities.
*/
unsigned lpm_cap_en:1;
/** LPM response programmed by application (AppL1Res) (Device)
* Handshake response to LPM token pre-programmed
* by device application software.
*/
unsigned appl_resp:1;
/** Host Initiated Resume Duration (HIRD) (Device and Host)
* In Host mode this field indicates the value of HIRD
* to be sent in an LPM transaction.
* In Device mode this field is updated with the
* Received LPM Token HIRD bmAttribute
* when an ACK/NYET/STALL response is sent
* to an LPM transaction.
*/
unsigned hird:4;
/** RemoteWakeEnable (bRemoteWake) (Device and Host)
* In Host mode this bit indicates the value of remote
* wake up to be sent in wIndex field of LPM transaction.
* In Device mode this field is updated with the
* Received LPM Token bRemoteWake bmAttribute
* when an ACK/NYET/STALL response is sent
* to an LPM transaction.
*/
unsigned rem_wkup_en:1;
/** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
* The application uses this bit to control
* the utmi_sleep_n assertion to the PHY when in L1 state.
*/
unsigned en_utmi_sleep:1;
/** HIRD Threshold (HIRD_Thres) (Device and Host)
*/
unsigned hird_thres:5;
/** LPM Response (CoreL1Res) (Device and Host)
* In Host mode this bit contains handsake response to
* LPM transaction.
* In Device mode the response of the core to
* LPM transaction received is reflected in these two bits.
- 0x0 : ERROR (No handshake response)
- 0x1 : STALL
- 0x2 : NYET
- 0x3 : ACK
*/
unsigned lpm_resp:2;
/** Port Sleep Status (SlpSts) (Device and Host)
* This bit is set as long as a Sleep condition
* is present on the USB bus.
*/
unsigned prt_sleep_sts:1;
/** Sleep State Resume OK (L1ResumeOK) (Device and Host)
* Indicates that the application or host
* can start resume from Sleep state.
*/
unsigned sleep_state_resumeok:1;
/** LPM channel Index (LPM_Chnl_Indx) (Host)
* The channel number on which the LPM transaction
* has to be applied while sending
* an LPM transaction to the local device.
*/
unsigned lpm_chan_index:4;
/** LPM Retry Count (LPM_Retry_Cnt) (Host)
* Number host retries that would be performed
* if the device response was not valid response.
*/
unsigned retry_count:3;
/** Send LPM Transaction (SndLPM) (Host)
* When set by application software,
* an LPM transaction containing two tokens
* is sent.
*/
unsigned send_lpm:1;
/** LPM Retry status (LPM_RetryCnt_Sts) (Host)
* Number of LPM Host Retries still remaining
* to be transmitted for the current LPM sequence
*/
unsigned retry_count_sts:3;
/** Enable Best Effort Service Latency (BESL) (Device and Host)
* This bit enables the BESL features as defined in the LPM errata
*/
unsigned en_besl:1;
unsigned reserved29:1;
/** In host mode once this bit is set, the host
* configures to drive the HSIC Idle state on the bus.
* It then waits for the device to initiate the Connect sequence.
* In device mode once this bit is set, the device waits for
* the HSIC Idle line state on the bus. Upon receving the Idle
* line state, it initiates the HSIC Connect sequence.
*/
unsigned hsic_connect:1;
/** This bit overrides and functionally inverts
* the if_select_hsic input port signal.
*/
unsigned inv_sel_hsic:1;
} b;
} glpmcfg_data_t;
/**
* This union represents the bit fields of the Core ADP Timer, Control and
* Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
* the <i>d32</i> value to the register.
*/
typedef union adpctl_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Probe Discharge (PRB_DSCHG)
* These bits set the times for TADP_DSCHG.
* These bits are defined as follows:
* 2'b00 - 4 msec
* 2'b01 - 8 msec
* 2'b10 - 16 msec
* 2'b11 - 32 msec
*/
unsigned prb_dschg:2;
/** Probe Delta (PRB_DELTA)
* These bits set the resolution for RTIM value.
* The bits are defined in units of 32 kHz clock cycles as follows:
* 2'b00 - 1 cycles
* 2'b01 - 2 cycles
* 2'b10 - 3 cycles
* 2'b11 - 4 cycles
* For example if this value is chosen to 2'b01, it means that RTIM
* increments for every 3(three) 32Khz clock cycles.
*/
unsigned prb_delta:2;
/** Probe Period (PRB_PER)
* These bits sets the TADP_PRD as shown in Figure 4 as follows:
* 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)
* 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)
* 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)
* 2'b11 - Reserved
*/
unsigned prb_per:2;
/** These bits capture the latest time it took for VBUS to ramp from
* VADP_SINK to VADP_PRB.
* 0x000 - 1 cycles
* 0x001 - 2 cycles
* 0x002 - 3 cycles
* etc
* 0x7FF - 2048 cycles
* A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
*/
unsigned rtim:11;
/** Enable Probe (EnaPrb)
* When programmed to 1'b1, the core performs a probe operation.
* This bit is valid only if OTG_Ver = 1'b1.
*/
unsigned enaprb:1;
/** Enable Sense (EnaSns)
* When programmed to 1'b1, the core performs a Sense operation.
* This bit is valid only if OTG_Ver = 1'b1.
*/
unsigned enasns:1;
/** ADP Reset (ADPRes)
* When set, ADP controller is reset.
* This bit is valid only if OTG_Ver = 1'b1.
*/
unsigned adpres:1;
/** ADP Enable (ADPEn)
* When set, the core performs either ADP probing or sensing
* based on EnaPrb or EnaSns.
* This bit is valid only if OTG_Ver = 1'b1.
*/
unsigned adpen:1;
/** ADP Probe Interrupt (ADP_PRB_INT)
* When this bit is set, it means that the VBUS
* voltage is greater than VADP_PRB or VADP_PRB is reached.
* This bit is valid only if OTG_Ver = 1'b1.
*/
unsigned adp_prb_int:1;
/**
* ADP Sense Interrupt (ADP_SNS_INT)
* When this bit is set, it means that the VBUS voltage is greater than
* VADP_SNS value or VADP_SNS is reached.
* This bit is valid only if OTG_Ver = 1'b1.
*/
unsigned adp_sns_int:1;
/** ADP Tomeout Interrupt (ADP_TMOUT_INT)
* This bit is relevant only for an ADP probe.
* When this bit is set, it means that the ramp time has
* completed ie ADPCTL.RTIM has reached its terminal value
* of 0x7FF. This is a debug feature that allows software
* to read the ramp time after each cycle.
* This bit is valid only if OTG_Ver = 1'b1.
*/
unsigned adp_tmout_int:1;
/** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
* When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
* This bit is valid only if OTG_Ver = 1'b1.
*/
unsigned adp_prb_int_msk:1;
/** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
* When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
* This bit is valid only if OTG_Ver = 1'b1.
*/
unsigned adp_sns_int_msk:1;
/** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
* When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
* This bit is valid only if OTG_Ver = 1'b1.
*/
unsigned adp_tmout_int_msk:1;
/** Access Request
* 2'b00 - Read/Write Valid (updated by the core)
* 2'b01 - Read
* 2'b00 - Write
* 2'b00 - Reserved
*/
unsigned ar:2;
/** Reserved */
unsigned reserved29_31:3;
} b;
} adpctl_data_t;
////////////////////////////////////////////
// Device Registers
/**
* Device Global Registers. <i>Offsets 800h-BFFh</i>
*
* The following structures define the size and relative field offsets
* for the Device Mode Registers.
*
* <i>These registers are visible only in Device mode and must not be
* accessed in Host mode, as the results are unknown.</i>
*/
typedef struct dwc_otg_dev_global_regs {
/** Device Configuration Register. <i>Offset 800h</i> */
volatile uint32_t dcfg;
/** Device Control Register. <i>Offset: 804h</i> */
volatile uint32_t dctl;
/** Device Status Register (Read Only). <i>Offset: 808h</i> */
volatile uint32_t dsts;
/** Reserved. <i>Offset: 80Ch</i> */
uint32_t unused;
/** Device IN Endpoint Common Interrupt Mask
* Register. <i>Offset: 810h</i> */
volatile uint32_t diepmsk;
/** Device OUT Endpoint Common Interrupt Mask
* Register. <i>Offset: 814h</i> */
volatile uint32_t doepmsk;
/** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */
volatile uint32_t daint;
/** Device All Endpoints Interrupt Mask Register. <i>Offset:
* 81Ch</i> */
volatile uint32_t daintmsk;
/** Device IN Token Queue Read Register-1 (Read Only).
* <i>Offset: 820h</i> */
volatile uint32_t dtknqr1;
/** Device IN Token Queue Read Register-2 (Read Only).
* <i>Offset: 824h</i> */
volatile uint32_t dtknqr2;
/** Device VBUS discharge Register. <i>Offset: 828h</i> */
volatile uint32_t dvbusdis;
/** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */
volatile uint32_t dvbuspulse;
/** Device IN Token Queue Read Register-3 (Read Only). /
* Device Thresholding control register (Read/Write)
* <i>Offset: 830h</i> */
volatile uint32_t dtknqr3_dthrctl;
/** Device IN Token Queue Read Register-4 (Read Only). /
* Device IN EPs empty Inr. Mask Register (Read/Write)
* <i>Offset: 834h</i> */
volatile uint32_t dtknqr4_fifoemptymsk;
/** Device Each Endpoint Interrupt Register (Read Only). /
* <i>Offset: 838h</i> */
volatile uint32_t deachint;
/** Device Each Endpoint Interrupt mask Register (Read/Write). /
* <i>Offset: 83Ch</i> */
volatile uint32_t deachintmsk;
/** Device Each In Endpoint Interrupt mask Register (Read/Write). /
* <i>Offset: 840h</i> */
volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
/** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
* <i>Offset: 880h</i> */
volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
} dwc_otg_device_global_regs_t;
/**
* This union represents the bit fields in the Device Configuration
* Register. Read the register into the <i>d32</i> member then
* set/clear the bits using the <i>b</i>it elements. Write the
* <i>d32</i> member to the dcfg register.
*/
typedef union dcfg_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Device Speed */
unsigned devspd:2;
/** Non Zero Length Status OUT Handshake */
unsigned nzstsouthshk:1;
#define DWC_DCFG_SEND_STALL 1
unsigned ena32khzs:1;
/** Device Addresses */
unsigned devaddr:7;
/** Periodic Frame Interval */
unsigned perfrint:2;
#define DWC_DCFG_FRAME_INTERVAL_80 0
#define DWC_DCFG_FRAME_INTERVAL_85 1
#define DWC_DCFG_FRAME_INTERVAL_90 2
#define DWC_DCFG_FRAME_INTERVAL_95 3
/** Enable Device OUT NAK for bulk in DDMA mode */
unsigned endevoutnak:1;
unsigned reserved14_17:4;
/** In Endpoint Mis-match count */
unsigned epmscnt:5;
/** Enable Descriptor DMA in Device mode */
unsigned descdma:1;
unsigned perschintvl:2;
unsigned resvalid:6;
} b;
} dcfg_data_t;
/**
* This union represents the bit fields in the Device Control
* Register. Read the register into the <i>d32</i> member then
* set/clear the bits using the <i>b</i>it elements.
*/
typedef union dctl_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Remote Wakeup */
unsigned rmtwkupsig:1;
/** Soft Disconnect */
unsigned sftdiscon:1;
/** Global Non-Periodic IN NAK Status */
unsigned gnpinnaksts:1;
/** Global OUT NAK Status */
unsigned goutnaksts:1;
/** Test Control */
unsigned tstctl:3;
/** Set Global Non-Periodic IN NAK */
unsigned sgnpinnak:1;
/** Clear Global Non-Periodic IN NAK */
unsigned cgnpinnak:1;
/** Set Global OUT NAK */
unsigned sgoutnak:1;
/** Clear Global OUT NAK */
unsigned cgoutnak:1;
/** Power-On Programming Done */
unsigned pwronprgdone:1;
/** Reserved */
unsigned reserved:1;
/** Global Multi Count */
unsigned gmc:2;
/** Ignore Frame Number for ISOC EPs */
unsigned ifrmnum:1;
/** NAK on Babble */
unsigned nakonbble:1;
/** Enable Continue on BNA */
unsigned encontonbna:1;
/** Enable deep sleep besl reject feature*/
unsigned besl_reject:1;
unsigned reserved17_31:13;
} b;
} dctl_data_t;
/**
* This union represents the bit fields in the Device Status
* Register. Read the register into the <i>d32</i> member then
* set/clear the bits using the <i>b</i>it elements.
*/
typedef union dsts_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Suspend Status */
unsigned suspsts:1;
/** Enumerated Speed */
unsigned enumspd:2;
#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2
#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3
/** Erratic Error */
unsigned errticerr:1;
unsigned reserved4_7:4;
/** Frame or Microframe Number of the received SOF */
unsigned soffn:14;
unsigned reserved22_31:10;
} b;
} dsts_data_t;
/**
* This union represents the bit fields in the Device IN EP Interrupt
* Register and the Device IN EP Common Mask Register.
*
* - Read the register into the <i>d32</i> member then set/clear the
* bits using the <i>b</i>it elements.
*/
typedef union diepint_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Transfer complete mask */
unsigned xfercompl:1;
/** Endpoint disable mask */
unsigned epdisabled:1;
/** AHB Error mask */
unsigned ahberr:1;
/** TimeOUT Handshake mask (non-ISOC EPs) */
unsigned timeout:1;
/** IN Token received with TxF Empty mask */
unsigned intktxfemp:1;
/** IN Token Received with EP mismatch mask */
unsigned intknepmis:1;
/** IN Endpoint NAK Effective mask */
unsigned inepnakeff:1;
/** Reserved */
unsigned emptyintr:1;
unsigned txfifoundrn:1;
/** BNA Interrupt mask */
unsigned bna:1;
unsigned reserved10_12:3;
/** BNA Interrupt mask */
unsigned nak:1;
unsigned reserved14_31:18;
} b;
} diepint_data_t;
/**
* This union represents the bit fields in the Device IN EP
* Common/Dedicated Interrupt Mask Register.
*/
typedef union diepint_data diepmsk_data_t;
/**
* This union represents the bit fields in the Device OUT EP Interrupt
* Registerand Device OUT EP Common Interrupt Mask Register.
*
* - Read the register into the <i>d32</i> member then set/clear the
* bits using the <i>b</i>it elements.
*/
typedef union doepint_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Transfer complete */
unsigned xfercompl:1;
/** Endpoint disable */
unsigned epdisabled:1;
/** AHB Error */
unsigned ahberr:1;
/** Setup Phase Done (contorl EPs) */
unsigned setup:1;
/** OUT Token Received when Endpoint Disabled */
unsigned outtknepdis:1;
unsigned stsphsercvd:1;
/** Back-to-Back SETUP Packets Received */
unsigned back2backsetup:1;
unsigned reserved7:1;
/** OUT packet Error */
unsigned outpkterr:1;
/** BNA Interrupt */
unsigned bna:1;
unsigned reserved10:1;
/** Packet Drop Status */
unsigned pktdrpsts:1;
/** Babble Interrupt */
unsigned babble:1;
/** NAK Interrupt */
unsigned nak:1;
/** NYET Interrupt */
unsigned nyet:1;
/** Bit indicating setup packet received */
unsigned sr:1;
unsigned reserved16_31:16;
} b;
} doepint_data_t;
/**
* This union represents the bit fields in the Device OUT EP
* Common/Dedicated Interrupt Mask Register.
*/
typedef union doepint_data doepmsk_data_t;
/**
* This union represents the bit fields in the Device All EP Interrupt
* and Mask Registers.
* - Read the register into the <i>d32</i> member then set/clear the
* bits using the <i>b</i>it elements.
*/
typedef union daint_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** IN Endpoint bits */
unsigned in:16;
/** OUT Endpoint bits */
unsigned out:16;
} ep;
struct {
/** IN Endpoint bits */
unsigned inep0:1;
unsigned inep1:1;
unsigned inep2:1;
unsigned inep3:1;
unsigned inep4:1;
unsigned inep5:1;
unsigned inep6:1;
unsigned inep7:1;
unsigned inep8:1;
unsigned inep9:1;
unsigned inep10:1;
unsigned inep11:1;
unsigned inep12:1;
unsigned inep13:1;
unsigned inep14:1;
unsigned inep15:1;
/** OUT Endpoint bits */
unsigned outep0:1;
unsigned outep1:1;
unsigned outep2:1;
unsigned outep3:1;
unsigned outep4:1;
unsigned outep5:1;
unsigned outep6:1;
unsigned outep7:1;
unsigned outep8:1;
unsigned outep9:1;
unsigned outep10:1;
unsigned outep11:1;
unsigned outep12:1;
unsigned outep13:1;
unsigned outep14:1;
unsigned outep15:1;
} b;
} daint_data_t;
/**
* This union represents the bit fields in the Device IN Token Queue
* Read Registers.
* - Read the register into the <i>d32</i> member.
* - READ-ONLY Register
*/
typedef union dtknq1_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** In Token Queue Write Pointer */
unsigned intknwptr:5;
/** Reserved */
unsigned reserved05_06:2;
/** write pointer has wrapped. */
unsigned wrap_bit:1;
/** EP Numbers of IN Tokens 0 ... 4 */
unsigned epnums0_5:24;
} b;
} dtknq1_data_t;
/**
* This union represents Threshold control Register
* - Read and write the register into the <i>d32</i> member.
* - READ-WRITABLE Register
*/
typedef union dthrctl_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** non ISO Tx Thr. Enable */
unsigned non_iso_thr_en:1;
/** ISO Tx Thr. Enable */
unsigned iso_thr_en:1;
/** Tx Thr. Length */
unsigned tx_thr_len:9;
/** AHB Threshold ratio */
unsigned ahb_thr_ratio:2;
/** Reserved */
unsigned reserved13_15:3;
/** Rx Thr. Enable */
unsigned rx_thr_en:1;
/** Rx Thr. Length */
unsigned rx_thr_len:9;
unsigned reserved26:1;
/** Arbiter Parking Enable*/
unsigned arbprken:1;
/** Reserved */
unsigned reserved28_31:4;
} b;
} dthrctl_data_t;
/**
* Device Logical IN Endpoint-Specific Registers. <i>Offsets
* 900h-AFCh</i>
*
* There will be one set of endpoint registers per logical endpoint
* implemented.
*
* <i>These registers are visible only in Device mode and must not be
* accessed in Host mode, as the results are unknown.</i>
*/
typedef struct dwc_otg_dev_in_ep_regs {
/** Device IN Endpoint Control Register. <i>Offset:900h +
* (ep_num * 20h) + 00h</i> */
volatile uint32_t diepctl;
/** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
uint32_t reserved04;
/** Device IN Endpoint Interrupt Register. <i>Offset:900h +
* (ep_num * 20h) + 08h</i> */
volatile uint32_t diepint;
/** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
uint32_t reserved0C;
/** Device IN Endpoint Transfer Size
* Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
volatile uint32_t dieptsiz;
/** Device IN Endpoint DMA Address Register. <i>Offset:900h +
* (ep_num * 20h) + 14h</i> */
volatile uint32_t diepdma;
/** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
* (ep_num * 20h) + 18h</i> */
volatile uint32_t dtxfsts;
/** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
* (ep_num * 20h) + 1Ch</i> */
volatile uint32_t diepdmab;
} dwc_otg_dev_in_ep_regs_t;
/**
* Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
* B00h-CFCh</i>
*
* There will be one set of endpoint registers per logical endpoint
* implemented.
*
* <i>These registers are visible only in Device mode and must not be
* accessed in Host mode, as the results are unknown.</i>
*/
typedef struct dwc_otg_dev_out_ep_regs {
/** Device OUT Endpoint Control Register. <i>Offset:B00h +
* (ep_num * 20h) + 00h</i> */
volatile uint32_t doepctl;
/** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
uint32_t reserved04;
/** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
* (ep_num * 20h) + 08h</i> */
volatile uint32_t doepint;
/** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
uint32_t reserved0C;
/** Device OUT Endpoint Transfer Size Register. <i>Offset:
* B00h + (ep_num * 20h) + 10h</i> */
volatile uint32_t doeptsiz;
/** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
* + (ep_num * 20h) + 14h</i> */
volatile uint32_t doepdma;
/** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */
uint32_t unused;
/** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
* + (ep_num * 20h) + 1Ch</i> */
uint32_t doepdmab;
} dwc_otg_dev_out_ep_regs_t;
/**
* This union represents the bit fields in the Device EP Control
* Register. Read the register into the <i>d32</i> member then
* set/clear the bits using the <i>b</i>it elements.
*/
typedef union depctl_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Maximum Packet Size
* IN/OUT EPn
* IN/OUT EP0 - 2 bits
* 2'b00: 64 Bytes
* 2'b01: 32
* 2'b10: 16
* 2'b11: 8 */
unsigned mps:11;
#define DWC_DEP0CTL_MPS_64 0
#define DWC_DEP0CTL_MPS_32 1
#define DWC_DEP0CTL_MPS_16 2
#define DWC_DEP0CTL_MPS_8 3
/** Next Endpoint
* IN EPn/IN EP0
* OUT EPn/OUT EP0 - reserved */
unsigned nextep:4;
/** USB Active Endpoint */
unsigned usbactep:1;
/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
* This field contains the PID of the packet going to
* be received or transmitted on this endpoint. The
* application should program the PID of the first
* packet going to be received or transmitted on this
* endpoint , after the endpoint is
* activated. Application use the SetD1PID and
* SetD0PID fields of this register to program either
* D0 or D1 PID.
*
* The encoding for this field is
* - 0: D0
* - 1: D1
*/
unsigned dpid:1;
/** NAK Status */
unsigned naksts:1;
/** Endpoint Type
* 2'b00: Control
* 2'b01: Isochronous
* 2'b10: Bulk
* 2'b11: Interrupt */
unsigned eptype:2;
/** Snoop Mode
* OUT EPn/OUT EP0
* IN EPn/IN EP0 - reserved */
unsigned snp:1;
/** Stall Handshake */
unsigned stall:1;
/** Tx Fifo Number
* IN EPn/IN EP0
* OUT EPn/OUT EP0 - reserved */
unsigned txfnum:4;
/** Clear NAK */
unsigned cnak:1;
/** Set NAK */
unsigned snak:1;
/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
* Writing to this field sets the Endpoint DPID (DPID)
* field in this register to DATA0. Set Even
* (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
* Writing to this field sets the Even/Odd
* (micro)frame (EO_FrNum) field to even (micro)
* frame.
*/
unsigned setd0pid:1;
/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
* Writing to this field sets the Endpoint DPID (DPID)
* field in this register to DATA1 Set Odd
* (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
* Writing to this field sets the Even/Odd
* (micro)frame (EO_FrNum) field to odd (micro) frame.
*/
unsigned setd1pid:1;
/** Endpoint Disable */
unsigned epdis:1;
/** Endpoint Enable */
unsigned epena:1;
} b;
} depctl_data_t;
/**
* This union represents the bit fields in the Device EP Transfer
* Size Register. Read the register into the <i>d32</i> member then
* set/clear the bits using the <i>b</i>it elements.
*/
typedef union deptsiz_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Transfer size */
unsigned xfersize:19;
/** Max packet count for EP (pow(2,10)-1) */
#define MAX_PKT_CNT 1023
/** Packet Count */
unsigned pktcnt:10;
/** Multi Count - Periodic IN endpoints */
unsigned mc:2;
unsigned reserved:1;
} b;
} deptsiz_data_t;
/**
* This union represents the bit fields in the Device EP 0 Transfer
* Size Register. Read the register into the <i>d32</i> member then
* set/clear the bits using the <i>b</i>it elements.
*/
typedef union deptsiz0_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Transfer size */
unsigned xfersize:7;
/** Reserved */
unsigned reserved7_18:12;
/** Packet Count */
unsigned pktcnt:2;
/** Reserved */
unsigned reserved21_28:8;
/**Setup Packet Count (DOEPTSIZ0 Only) */
unsigned supcnt:2;
unsigned reserved31;
} b;
} deptsiz0_data_t;
/////////////////////////////////////////////////
// DMA Descriptor Specific Structures
//
/** Buffer status definitions */
#define BS_HOST_READY 0x0
#define BS_DMA_BUSY 0x1
#define BS_DMA_DONE 0x2
#define BS_HOST_BUSY 0x3
/** Receive/Transmit status definitions */
#define RTS_SUCCESS 0x0
#define RTS_BUFFLUSH 0x1
#define RTS_RESERVED 0x2
#define RTS_BUFERR 0x3
/**
* This union represents the bit fields in the DMA Descriptor
* status quadlet. Read the quadlet into the <i>d32</i> member then
* set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
* <i>b_iso_in</i> elements.
*/
typedef union dev_dma_desc_sts {
/** raw register data */
uint32_t d32;
/** quadlet bits */
struct {
/** Received number of bytes */
unsigned bytes:16;
/** NAK bit - only for OUT EPs */
unsigned nak:1;
unsigned reserved17_22:6;
/** Multiple Transfer - only for OUT EPs */
unsigned mtrf:1;
/** Setup Packet received - only for OUT EPs */
unsigned sr:1;
/** Interrupt On Complete */
unsigned ioc:1;
/** Short Packet */
unsigned sp:1;
/** Last */
unsigned l:1;
/** Receive Status */
unsigned sts:2;
/** Buffer Status */
unsigned bs:2;
} b;
//#ifdef DWC_EN_ISOC
/** iso out quadlet bits */
struct {
/** Received number of bytes */
unsigned rxbytes:11;
unsigned reserved11:1;
/** Frame Number */
unsigned framenum:11;
/** Received ISO Data PID */
unsigned pid:2;
/** Interrupt On Complete */
unsigned ioc:1;
/** Short Packet */
unsigned sp:1;
/** Last */
unsigned l:1;
/** Receive Status */
unsigned rxsts:2;
/** Buffer Status */
unsigned bs:2;
} b_iso_out;
/** iso in quadlet bits */
struct {
/** Transmited number of bytes */
unsigned txbytes:12;
/** Frame Number */
unsigned framenum:11;
/** Transmited ISO Data PID */
unsigned pid:2;
/** Interrupt On Complete */
unsigned ioc:1;
/** Short Packet */
unsigned sp:1;
/** Last */
unsigned l:1;
/** Transmit Status */
unsigned txsts:2;
/** Buffer Status */
unsigned bs:2;
} b_iso_in;
//#endif /* DWC_EN_ISOC */
} dev_dma_desc_sts_t;
/**
* DMA Descriptor structure
*
* DMA Descriptor structure contains two quadlets:
* Status quadlet and Data buffer pointer.
*/
typedef struct dwc_otg_dev_dma_desc {
/** DMA Descriptor status quadlet */
dev_dma_desc_sts_t status;
/** DMA Descriptor data buffer pointer */
uint32_t buf;
} dwc_otg_dev_dma_desc_t;
/**
* The dwc_otg_dev_if structure contains information needed to manage
* the DWC_otg controller acting in device mode. It represents the
* programming view of the device-specific aspects of the controller.
*/
typedef struct dwc_otg_dev_if {
/** Pointer to device Global registers.
* Device Global Registers starting at offset 800h
*/
dwc_otg_device_global_regs_t *dev_global_regs;
#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
/**
* Device Logical IN Endpoint-Specific Registers 900h-AFCh
*/
dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
#define DWC_DEV_IN_EP_REG_OFFSET 0x900
#define DWC_EP_REG_OFFSET 0x20
/** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
/* Device configuration information */
uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */
uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */
uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/
/** Size of periodic FIFOs (Bytes) */
uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
/** Size of Tx FIFOs (Bytes) */
uint16_t tx_fifo_size[MAX_TX_FIFOS];
/** Thresholding enable flags and length varaiables **/
uint16_t rx_thr_en;
uint16_t iso_tx_thr_en;
uint16_t non_iso_tx_thr_en;
uint16_t rx_thr_length;
uint16_t tx_thr_length;
/**
* Pointers to the DMA Descriptors for EP0 Control
* transfers (virtual and physical)
*/
/** 2 descriptors for SETUP packets */
dwc_dma_t dma_setup_desc_addr[2];
dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
/** Pointer to Descriptor with latest SETUP packet */
dwc_otg_dev_dma_desc_t *psetup;
/** Index of current SETUP handler descriptor */
uint32_t setup_desc_index;
/** Descriptor for Data In or Status In phases */
dwc_dma_t dma_in_desc_addr;
dwc_otg_dev_dma_desc_t *in_desc_addr;
/** Descriptor for Data Out or Status Out phases */
dwc_dma_t dma_out_desc_addr;
dwc_otg_dev_dma_desc_t *out_desc_addr;
/** Setup Packet Detected - if set clear NAK when queueing */
uint32_t spd;
/** Isoc ep pointer on which incomplete happens */
void *isoc_ep;
} dwc_otg_dev_if_t;
/////////////////////////////////////////////////
// Host Mode Register Structures
//
/**
* The Host Global Registers structure defines the size and relative
* field offsets for the Host Mode Global Registers. Host Global
* Registers offsets 400h-7FFh.
*/
typedef struct dwc_otg_host_global_regs {
/** Host Configuration Register. <i>Offset: 400h</i> */
volatile uint32_t hcfg;
/** Host Frame Interval Register. <i>Offset: 404h</i> */
volatile uint32_t hfir;
/** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
volatile uint32_t hfnum;
/** Reserved. <i>Offset: 40Ch</i> */
uint32_t reserved40C;
/** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
volatile uint32_t hptxsts;
/** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
volatile uint32_t haint;
/** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
volatile uint32_t haintmsk;
/** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
volatile uint32_t hflbaddr;
} dwc_otg_host_global_regs_t;
/**
* This union represents the bit fields in the Host Configuration Register.
* Read the register into the <i>d32</i> member then set/clear the bits using
* the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
*/
typedef union hcfg_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** FS/LS Phy Clock Select */
unsigned fslspclksel:2;
#define DWC_HCFG_30_60_MHZ 0
#define DWC_HCFG_48_MHZ 1
#define DWC_HCFG_6_MHZ 2
/** FS/LS Only Support */
unsigned fslssupp:1;
unsigned reserved3_6:4;
/** Enable 32-KHz Suspend Mode */
unsigned ena32khzs:1;
/** Resume Validation Periiod */
unsigned resvalid:8;
unsigned reserved16_22:7;
/** Enable Scatter/gather DMA in Host mode */
unsigned descdma:1;
/** Frame List Entries */
unsigned frlisten:2;
/** Enable Periodic Scheduling */
unsigned perschedena:1;
unsigned reserved27_30:4;
unsigned modechtimen:1;
} b;
} hcfg_data_t;
/**
* This union represents the bit fields in the Host Frame Remaing/Number
* Register.
*/
typedef union hfir_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned frint:16;
unsigned hfirrldctrl:1;
unsigned reserved:15;
} b;
} hfir_data_t;
/**
* This union represents the bit fields in the Host Frame Remaing/Number
* Register.
*/
typedef union hfnum_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned frnum:16;
#define DWC_HFNUM_MAX_FRNUM 0x3FFF
unsigned frrem:16;
} b;
} hfnum_data_t;
typedef union hptxsts_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned ptxfspcavail:16;
unsigned ptxqspcavail:8;
/** Top of the Periodic Transmit Request Queue
* - bit 24 - Terminate (last entry for the selected channel)
* - bits 26:25 - Token Type
* - 2'b00 - Zero length
* - 2'b01 - Ping
* - 2'b10 - Disable
* - bits 30:27 - Channel Number
* - bit 31 - Odd/even microframe
*/
unsigned ptxqtop_terminate:1;
unsigned ptxqtop_token:2;
unsigned ptxqtop_chnum:4;
unsigned ptxqtop_odd:1;
} b;
} hptxsts_data_t;
/**
* This union represents the bit fields in the Host Port Control and Status
* Register. Read the register into the <i>d32</i> member then set/clear the
* bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
* hprt0 register.
*/
typedef union hprt0_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned prtconnsts:1;
unsigned prtconndet:1;
unsigned prtena:1;
unsigned prtenchng:1;
unsigned prtovrcurract:1;
unsigned prtovrcurrchng:1;
unsigned prtres:1;
unsigned prtsusp:1;
unsigned prtrst:1;
unsigned reserved9:1;
unsigned prtlnsts:2;
unsigned prtpwr:1;
unsigned prttstctl:4;
unsigned prtspd:2;
#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
#define DWC_HPRT0_PRTSPD_LOW_SPEED 2
unsigned reserved19_31:13;
} b;
} hprt0_data_t;
/**
* This union represents the bit fields in the Host All Interrupt
* Register.
*/
typedef union haint_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned ch0:1;
unsigned ch1:1;
unsigned ch2:1;
unsigned ch3:1;
unsigned ch4:1;
unsigned ch5:1;
unsigned ch6:1;
unsigned ch7:1;
unsigned ch8:1;
unsigned ch9:1;
unsigned ch10:1;
unsigned ch11:1;
unsigned ch12:1;
unsigned ch13:1;
unsigned ch14:1;
unsigned ch15:1;
unsigned reserved:16;
} b;
struct {
unsigned chint:16;
unsigned reserved:16;
} b2;
} haint_data_t;
/**
* This union represents the bit fields in the Host All Interrupt
* Register.
*/
typedef union haintmsk_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned ch0:1;
unsigned ch1:1;
unsigned ch2:1;
unsigned ch3:1;
unsigned ch4:1;
unsigned ch5:1;
unsigned ch6:1;
unsigned ch7:1;
unsigned ch8:1;
unsigned ch9:1;
unsigned ch10:1;
unsigned ch11:1;
unsigned ch12:1;
unsigned ch13:1;
unsigned ch14:1;
unsigned ch15:1;
unsigned reserved:16;
} b;
struct {
unsigned chint:16;
unsigned reserved:16;
} b2;
} haintmsk_data_t;
/**
* Host Channel Specific Registers. <i>500h-5FCh</i>
*/
typedef struct dwc_otg_hc_regs {
/** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
volatile uint32_t hcchar;
/** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
volatile uint32_t hcsplt;
/** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
volatile uint32_t hcint;
/** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
volatile uint32_t hcintmsk;
/** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
volatile uint32_t hctsiz;
/** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
volatile uint32_t hcdma;
volatile uint32_t reserved;
/** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
volatile uint32_t hcdmab;
} dwc_otg_hc_regs_t;
/**
* This union represents the bit fields in the Host Channel Characteristics
* Register. Read the register into the <i>d32</i> member then set/clear the
* bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
* hcchar register.
*/
typedef union hcchar_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Maximum packet size in bytes */
unsigned mps:11;
/** Endpoint number */
unsigned epnum:4;
/** 0: OUT, 1: IN */
unsigned epdir:1;
unsigned reserved:1;
/** 0: Full/high speed device, 1: Low speed device */
unsigned lspddev:1;
/** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
unsigned eptype:2;
/** Packets per frame for periodic transfers. 0 is reserved. */
unsigned multicnt:2;
/** Device address */
unsigned devaddr:7;
/**
* Frame to transmit periodic transaction.
* 0: even, 1: odd
*/
unsigned oddfrm:1;
/** Channel disable */
unsigned chdis:1;
/** Channel enable */
unsigned chen:1;
} b;
} hcchar_data_t;
typedef union hcsplt_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Port Address */
unsigned prtaddr:7;
/** Hub Address */
unsigned hubaddr:7;
/** Transaction Position */
unsigned xactpos:2;
#define DWC_HCSPLIT_XACTPOS_MID 0
#define DWC_HCSPLIT_XACTPOS_END 1
#define DWC_HCSPLIT_XACTPOS_BEGIN 2
#define DWC_HCSPLIT_XACTPOS_ALL 3
/** Do Complete Split */
unsigned compsplt:1;
/** Reserved */
unsigned reserved:14;
/** Split Enble */
unsigned spltena:1;
} b;
} hcsplt_data_t;
/**
* This union represents the bit fields in the Host All Interrupt
* Register.
*/
typedef union hcint_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Transfer Complete */
unsigned xfercomp:1;
/** Channel Halted */
unsigned chhltd:1;
/** AHB Error */
unsigned ahberr:1;
/** STALL Response Received */
unsigned stall:1;
/** NAK Response Received */
unsigned nak:1;
/** ACK Response Received */
unsigned ack:1;
/** NYET Response Received */
unsigned nyet:1;
/** Transaction Err */
unsigned xacterr:1;
/** Babble Error */
unsigned bblerr:1;
/** Frame Overrun */
unsigned frmovrun:1;
/** Data Toggle Error */
unsigned datatglerr:1;
/** Buffer Not Available (only for DDMA mode) */
unsigned bna:1;
/** Exessive transaction error (only for DDMA mode) */
unsigned xcs_xact:1;
/** Frame List Rollover interrupt */
unsigned frm_list_roll:1;
/** Reserved */
unsigned reserved14_31:18;
} b;
} hcint_data_t;
/**
* This union represents the bit fields in the Host Channel Interrupt Mask
* Register. Read the register into the <i>d32</i> member then set/clear the
* bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
* hcintmsk register.
*/
typedef union hcintmsk_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned xfercompl:1;
unsigned chhltd:1;
unsigned ahberr:1;
unsigned stall:1;
unsigned nak:1;
unsigned ack:1;
unsigned nyet:1;
unsigned xacterr:1;
unsigned bblerr:1;
unsigned frmovrun:1;
unsigned datatglerr:1;
unsigned bna:1;
unsigned xcs_xact:1;
unsigned frm_list_roll:1;
unsigned reserved14_31:18;
} b;
} hcintmsk_data_t;
/**
* This union represents the bit fields in the Host Channel Transfer Size
* Register. Read the register into the <i>d32</i> member then set/clear the
* bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
* hcchar register.
*/
typedef union hctsiz_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Total transfer size in bytes */
unsigned xfersize:19;
/** Data packets to transfer */
unsigned pktcnt:10;
/**
* Packet ID for next data packet
* 0: DATA0
* 1: DATA2
* 2: DATA1
* 3: MDATA (non-Control), SETUP (Control)
*/
unsigned pid:2;
#define DWC_HCTSIZ_DATA0 0
#define DWC_HCTSIZ_DATA1 2
#define DWC_HCTSIZ_DATA2 1
#define DWC_HCTSIZ_MDATA 3
#define DWC_HCTSIZ_SETUP 3
/** Do PING protocol when 1 */
unsigned dopng:1;
} b;
/** register bits */
struct {
/** Scheduling information */
unsigned schinfo:8;
/** Number of transfer descriptors.
* Max value:
* 64 in general,
* 256 only for HS isochronous endpoint.
*/
unsigned ntd:8;
/** Data packets to transfer */
unsigned reserved16_28:13;
/**
* Packet ID for next data packet
* 0: DATA0
* 1: DATA2
* 2: DATA1
* 3: MDATA (non-Control)
*/
unsigned pid:2;
/** Do PING protocol when 1 */
unsigned dopng:1;
} b_ddma;
} hctsiz_data_t;
/**
* This union represents the bit fields in the Host DMA Address
* Register used in Descriptor DMA mode.
*/
typedef union hcdma_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
unsigned reserved0_2:3;
/** Current Transfer Descriptor. Not used for ISOC */
unsigned ctd:8;
/** Start Address of Descriptor List */
unsigned dma_addr:21;
} b;
} hcdma_data_t;
/**
* This union represents the bit fields in the DMA Descriptor
* status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
* set/clear the bits using the <i>b</i>it elements.
*/
typedef union host_dma_desc_sts {
/** raw register data */
uint32_t d32;
/** quadlet bits */
/* for non-isochronous */
struct {
/** Number of bytes */
unsigned n_bytes:17;
/** QTD offset to jump when Short Packet received - only for IN EPs */
unsigned qtd_offset:6;
/**
* Set to request the core to jump to alternate QTD if
* Short Packet received - only for IN EPs
*/
unsigned a_qtd:1;
/**
* Setup Packet bit. When set indicates that buffer contains
* setup packet.
*/
unsigned sup:1;
/** Interrupt On Complete */
unsigned ioc:1;
/** End of List */
unsigned eol:1;
unsigned reserved27:1;
/** Rx/Tx Status */
unsigned sts:2;
#define DMA_DESC_STS_PKTERR 1
unsigned reserved30:1;
/** Active Bit */
unsigned a:1;
} b;
/* for isochronous */
struct {
/** Number of bytes */
unsigned n_bytes:12;
unsigned reserved12_24:13;
/** Interrupt On Complete */
unsigned ioc:1;
unsigned reserved26_27:2;
/** Rx/Tx Status */
unsigned sts:2;
unsigned reserved30:1;
/** Active Bit */
unsigned a:1;
} b_isoc;
} host_dma_desc_sts_t;
#define MAX_DMA_DESC_SIZE 131071
#define MAX_DMA_DESC_NUM_GENERIC 64
#define MAX_DMA_DESC_NUM_HS_ISOC 256
#define MAX_FRLIST_EN_NUM 64
/**
* Host-mode DMA Descriptor structure
*
* DMA Descriptor structure contains two quadlets:
* Status quadlet and Data buffer pointer.
*/
typedef struct dwc_otg_host_dma_desc {
/** DMA Descriptor status quadlet */
host_dma_desc_sts_t status;
/** DMA Descriptor data buffer pointer */
uint32_t buf;
} dwc_otg_host_dma_desc_t;
/** OTG Host Interface Structure.
*
* The OTG Host Interface Structure structure contains information
* needed to manage the DWC_otg controller acting in host mode. It
* represents the programming view of the host-specific aspects of the
* controller.
*/
typedef struct dwc_otg_host_if {
/** Host Global Registers starting at offset 400h.*/
dwc_otg_host_global_regs_t *host_global_regs;
#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
/** Host Port 0 Control and Status Register */
volatile uint32_t *hprt0;
#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
/** Host Channel Specific Registers at offsets 500h-5FCh. */
dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
#define DWC_OTG_CHAN_REGS_OFFSET 0x20
/* Host configuration information */
/** Number of Host Channels (range: 1-16) */
uint8_t num_host_channels;
/** Periodic EPs supported (0: no, 1: yes) */
uint8_t perio_eps_supported;
/** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
uint16_t perio_tx_fifo_size;
} dwc_otg_host_if_t;
/**
* This union represents the bit fields in the Power and Clock Gating Control
* Register. Read the register into the <i>d32</i> member then set/clear the
* bits using the <i>b</i>it elements.
*/
typedef union pcgcctl_data {
/** raw register data */
uint32_t d32;
/** register bits */
struct {
/** Stop Pclk */
unsigned stoppclk:1;
/** Gate Hclk */
unsigned gatehclk:1;
/** Power Clamp */
unsigned pwrclmp:1;
/** Reset Power Down Modules */
unsigned rstpdwnmodule:1;
/** Reserved */
unsigned reserved:1;
/** Enable Sleep Clock Gating (Enbl_L1Gating) */
unsigned enbl_sleep_gating:1;
/** PHY In Sleep (PhySleep) */
unsigned phy_in_sleep:1;
/** Deep Sleep*/
unsigned deep_sleep:1;
unsigned resetaftsusp:1;
unsigned restoremode:1;
unsigned enbl_extnd_hiber:1;
unsigned extnd_hiber_pwrclmp:1;
unsigned extnd_hiber_switch:1;
unsigned ess_reg_restored:1;
unsigned prt_clk_sel:2;
unsigned port_power:1;
unsigned max_xcvrselect:2;
unsigned max_termsel:1;
unsigned mac_dev_addr:7;
unsigned p2hd_dev_enum_spd:2;
unsigned p2hd_prt_spd:2;
unsigned if_dev_mode:1;
} b;
} pcgcctl_data_t;
/**
* This union represents the bit fields in the Global Data FIFO Software
* Configuration Register. Read the register into the <i>d32</i> member then
* set/clear the bits using the <i>b</i>it elements.
*/
typedef union gdfifocfg_data {
/* raw register data */
uint32_t d32;
/** register bits */
struct {
/** OTG Data FIFO depth */
unsigned gdfifocfg:16;
/** Start address of EP info controller */
unsigned epinfobase:16;
} b;
} gdfifocfg_data_t;
/**
* This union represents the bit fields in the Global Power Down Register
* Register. Read the register into the <i>d32</i> member then set/clear the
* bits using the <i>b</i>it elements.
*/
typedef union gpwrdn_data {
/* raw register data */
uint32_t d32;
/** register bits */
struct {
/** PMU Interrupt Select */
unsigned pmuintsel:1;
/** PMU Active */
unsigned pmuactv:1;
/** Restore */
unsigned restore:1;
/** Power Down Clamp */
unsigned pwrdnclmp:1;
/** Power Down Reset */
unsigned pwrdnrstn:1;
/** Power Down Switch */
unsigned pwrdnswtch:1;
/** Disable VBUS */
unsigned dis_vbus:1;
/** Line State Change */
unsigned lnstschng:1;
/** Line state change mask */
unsigned lnstchng_msk:1;
/** Reset Detected */
unsigned rst_det:1;
/** Reset Detect mask */
unsigned rst_det_msk:1;
/** Disconnect Detected */
unsigned disconn_det:1;
/** Disconnect Detect mask */
unsigned disconn_det_msk:1;
/** Connect Detected*/
unsigned connect_det:1;
/** Connect Detected Mask*/
unsigned connect_det_msk:1;
/** SRP Detected */
unsigned srp_det:1;
/** SRP Detect mask */
unsigned srp_det_msk:1;
/** Status Change Interrupt */
unsigned sts_chngint:1;
/** Status Change Interrupt Mask */
unsigned sts_chngint_msk:1;
/** Line State */
unsigned linestate:2;
/** Indicates current mode(status of IDDIG signal) */
unsigned idsts:1;
/** B Session Valid signal status*/
unsigned bsessvld:1;
/** ADP Event Detected */
unsigned adp_int:1;
/** Multi Valued ID pin */
unsigned mult_val_id_bc:5;
/** Reserved 24_31 */
unsigned reserved29_31:3;
} b;
} gpwrdn_data_t;
#endif
|
YifuLiu/AliOS-Things
|
hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/usb_otg/include/dwc_otg_regs.h
|
C
|
apache-2.0
| 72,243
|