code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Demux_2 (
input io_en,
input io_input_valid,
input [15:0] io_input_data,
input io_sel,
output io_outputs_0_valid,
output [15:0] io_outputs_0_data,
output io_outputs_1_valid,
output [15:0] io_outputs_1_data
);
wire [15:0] _GEN_1;
wire _GEN_2;
wire _GEN_8;
wire _GEN_9;
wire _GEN_3;
wire _GEN_10;
wire _GEN_11;
wire _T_16;
wire _GEN_18;
wire _GEN_19;
assign io_outputs_0_valid = _GEN_18;
assign io_outputs_0_data = _GEN_1;
assign io_outputs_1_valid = _GEN_19;
assign io_outputs_1_data = _GEN_1;
assign _GEN_1 = io_input_data;
assign _GEN_2 = io_input_valid;
assign _GEN_8 = 1'h0 == io_sel ? _GEN_2 : 1'h0;
assign _GEN_9 = io_sel ? _GEN_2 : 1'h0;
assign _GEN_3 = 1'h1;
assign _GEN_10 = 1'h0 == io_sel ? _GEN_3 : _GEN_8;
assign _GEN_11 = io_sel ? _GEN_3 : _GEN_9;
assign _T_16 = io_en == 1'h0;
assign _GEN_18 = _T_16 ? 1'h0 : _GEN_10;
assign _GEN_19 = _T_16 ? 1'h0 : _GEN_11;
endmodule
| 6.867226 |
module LockingRRArbiter_4 (
input clock,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input io_in_0_bits_valid,
input [15:0] io_in_0_bits_RouteID,
input [15:0] io_in_0_bits_data,
output io_in_1_ready,
input io_in_1_valid,
input io_in_1_bits_valid,
input [15:0] io_in_1_bits_RouteID,
input [15:0] io_in_1_bits_data,
input io_out_ready,
output io_out_valid,
output io_out_bits_valid,
output [15:0] io_out_bits_RouteID,
output [15:0] io_out_bits_data,
output io_chosen
);
wire choice;
wire _GEN_0_valid;
wire _GEN_5;
wire _GEN_6;
wire [15:0] _GEN_7;
wire [15:0] _GEN_8;
wire [15:0] _GEN_1_bits_data;
wire [15:0] _GEN_2_bits_RouteID;
wire _GEN_3_bits_valid;
reg value;
reg [31:0] _RAND_0;
reg _T_62;
reg [31:0] _RAND_1;
wire _T_66;
wire [1:0] _T_71;
wire _T_72;
wire _GEN_9;
wire _GEN_10;
wire _GEN_11;
reg lastGrant;
reg [31:0] _RAND_2;
wire _GEN_12;
wire grantMask_1;
wire validMask_1;
wire _T_79;
wire _T_83;
wire _T_85;
wire _T_89;
wire _T_91;
wire _T_92;
wire _T_93;
wire _T_96;
wire _T_97;
wire _GEN_13;
wire _GEN_14;
assign io_in_0_ready = _T_93;
assign io_in_1_ready = _T_97;
assign io_out_valid = _GEN_0_valid;
assign io_out_bits_valid = _GEN_3_bits_valid;
assign io_out_bits_RouteID = _GEN_2_bits_RouteID;
assign io_out_bits_data = _GEN_1_bits_data;
assign io_chosen = _GEN_11;
assign choice = _GEN_14;
assign _GEN_0_valid = _GEN_5;
assign _GEN_5 = io_chosen ? io_in_1_valid : io_in_0_valid;
assign _GEN_6 = io_chosen ? io_in_1_bits_valid : io_in_0_bits_valid;
assign _GEN_7 = io_chosen ? io_in_1_bits_RouteID : io_in_0_bits_RouteID;
assign _GEN_8 = io_chosen ? io_in_1_bits_data : io_in_0_bits_data;
assign _GEN_1_bits_data = _GEN_8;
assign _GEN_2_bits_RouteID = _GEN_7;
assign _GEN_3_bits_valid = _GEN_6;
assign _T_66 = io_out_ready & io_out_valid;
assign _T_71 = value + 1'h1;
assign _T_72 = _T_71[0:0];
assign _GEN_9 = _T_66 ? io_chosen : _T_62;
assign _GEN_10 = _T_66 ? _T_72 : value;
assign _GEN_11 = value ? _T_62 : choice;
assign _GEN_12 = _T_66 ? io_chosen : lastGrant;
assign grantMask_1 = 1'h1 > lastGrant;
assign validMask_1 = io_in_1_valid & grantMask_1;
assign _T_79 = validMask_1 | io_in_0_valid;
assign _T_83 = validMask_1 == 1'h0;
assign _T_85 = _T_79 == 1'h0;
assign _T_89 = grantMask_1 | _T_85;
assign _T_91 = _T_62 == 1'h0;
assign _T_92 = value ? _T_91 : _T_83;
assign _T_93 = _T_92 & io_out_ready;
assign _T_96 = value ? _T_62 : _T_89;
assign _T_97 = _T_96 & io_out_ready;
assign _GEN_13 = io_in_0_valid ? 1'h0 : 1'h1;
assign _GEN_14 = validMask_1 ? 1'h1 : _GEN_13;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
value = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
_T_62 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
lastGrant = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
value <= 1'h0;
end else begin
if (_T_66) begin
value <= _T_72;
end
end
if (_T_66) begin
_T_62 <= io_chosen;
end
if (_T_66) begin
lastGrant <= io_chosen;
end
end
endmodule
| 7.257641 |
module Demux_3 (
input io_en,
input io_input_valid,
input [15:0] io_input_RouteID,
input [15:0] io_input_data,
input io_sel,
output io_outputs_0_valid,
output [15:0] io_outputs_0_RouteID,
output [15:0] io_outputs_0_data,
output io_outputs_1_valid,
output [15:0] io_outputs_1_RouteID,
output [15:0] io_outputs_1_data
);
wire [15:0] _GEN_0;
wire [15:0] _GEN_1;
wire _GEN_2;
wire _GEN_8;
wire _GEN_9;
wire _GEN_3;
wire _GEN_10;
wire _GEN_11;
wire _T_16;
wire _GEN_18;
wire _GEN_19;
assign io_outputs_0_valid = _GEN_18;
assign io_outputs_0_RouteID = _GEN_1;
assign io_outputs_0_data = _GEN_0;
assign io_outputs_1_valid = _GEN_19;
assign io_outputs_1_RouteID = _GEN_1;
assign io_outputs_1_data = _GEN_0;
assign _GEN_0 = io_input_data;
assign _GEN_1 = io_input_RouteID;
assign _GEN_2 = io_input_valid;
assign _GEN_8 = 1'h0 == io_sel ? _GEN_2 : 1'h0;
assign _GEN_9 = io_sel ? _GEN_2 : 1'h0;
assign _GEN_3 = 1'h1;
assign _GEN_10 = 1'h0 == io_sel ? _GEN_3 : _GEN_8;
assign _GEN_11 = io_sel ? _GEN_3 : _GEN_9;
assign _T_16 = io_en == 1'h0;
assign _GEN_18 = _T_16 ? 1'h0 : _GEN_10;
assign _GEN_19 = _T_16 ? 1'h0 : _GEN_11;
endmodule
| 6.596027 |
module type_detect
#(
parameter EXP_SIZE = `EXP_SIZE,
parameter MANTIS_SIZE = `MANTIS_SIZE
)
(
exp,
mantis,
type
);
// Inputs
input [EXP_SIZE -1:0] exp; // input exponent
input [MANTIS_SIZE-1:0] mantis; // input mantissa
// Outputs
output reg [2:0] type; // output type
parameter [2:0] ZERO = 3'b000,
INF = 3'b001,
SUBNORMAL = 3'b010,
NORMAL = 3'b011,
NAN = 3'b100;
// Combinational block
always @(*) begin
if (|exp) begin
if (&exp) begin
if (|mantis) type = NAN;
else type = INF;
end
else type = NORMAL;
end
else begin
if (|mantis) type = SUBNORMAL;
else type = ZERO;
end
end
endmodule
| 8.1042 |
module decoder3_8_test ();
reg [2:0] A;
reg g1, g2, g3;
wire [7:0] y;
decoder3_8 decoder3to8 (
A,
g1,
g2,
g3,
y
);
initial begin
A = 3'b000;
g1 = 1;
g2 = 0;
g3 = 0;
#10 A = 3'b000;
#10 A = 3'b001;
#10 A = 3'b010;
#10 A = 3'b011;
#10 A = 3'b100;
#10 A = 3'b101;
#10 A = 3'b110;
#10 A = 3'b111;
#10 g1 = 0;
$stop();
end
endmodule
| 7.126659 |
module add16_t ();
reg [15:0] A, B;
reg CI;
wire [15:0] Sum;
wire CO, G, P;
add16 a16 (
A,
B,
CI,
Sum,
CO,
G,
P
);
integer i, j, k;
parameter TWO_POW_16 = 65536;
task doTest;
input [15:0] a, b;
input ci;
begin
A = a;
B = b;
CI = ci;
#10;
$display("%d + %d + %d = %d", A, B, CI, Sum);
if (A + B + CI !== Sum) $display("%d + %d + %d = %d. Got %d.", A, B, CI, A + B + CI, Sum);
if (A + B + CI >= TWO_POW_16 && !CO) $display("Carry failed for %d, %d, %d", A, B, CI);
end
endtask // begin
initial begin
$display("Running tests...");
doTest(1, 0, 0);
doTest(1, 1, 0);
doTest(10, 10, 0);
doTest(1, 2, 1);
for (i = 0; i < 16; i = i + 1) begin
for (j = 0; j < 2; j = j + 1) begin
A = (12701 << 2 * i) % TWO_POW_16;
B = (1027 << 1 * i) % TWO_POW_16 + 5000;
CI = j;
doTest(A, B, CI);
end
end
$display("All tests complete");
end
endmodule
| 6.739977 |
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