code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tx_checkTimeout_dev_mul_65s_67ns_131_6_1 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
tx_checkTimeout_dev_mul_65s_67ns_131_6_1_Multiplier_1 tx_checkTimeout_dev_mul_65s_67ns_131_6_1_Multiplier_1_U(
.clk(clk),
.ce (ce),
.a (din0),
.b (din1),
.p (dout)
);
endmodule
| 6.500458 |
module tx_checkTimeout_dev_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.500458 |
module tx_checkTimeout_dev_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.500458 |
module tx_clk_gen #(
parameter CLK_FREQUENCE = 50_000_000, //hz
BAUD_RATE = 9600 //9600、19200 、38400 、57600 、115200、230400、460800、921600
) (
input clk, //system_clk
input rst_n, //system_reset
input tx_done, //once_tx_done
input tx_start, //once_tx_start
output reg bps_clk //baud_rate_clk
);
localparam BPS_CNT = CLK_FREQUENCE / BAUD_RATE - 1, BPS_WD = log2(BPS_CNT);
reg [BPS_WD-1:0] count;
reg c_state;
reg n_state;
//FSM-1 1'b0:IDLE 1'b1:send_data
always @(posedge clk or negedge rst_n) begin
if (!rst_n) c_state <= 1'b0;
else c_state <= n_state;
end
//FSM-2
always @(*) begin
case (c_state)
1'b0: n_state = tx_start ? 1'b1 : 1'b0;
1'b1: n_state = tx_done ? 1'b0 : 1'b1;
default: n_state = 1'b0;
endcase
end
//FSM-3 FSM's output(count_en) is equal to c_state
//baud_rate_clk_counter
always @(posedge clk or negedge rst_n) begin
if (!rst_n) count <= {BPS_WD{1'b0}};
else if (!c_state) count <= {BPS_WD{1'b0}};
else begin
if (count == BPS_CNT) count <= {BPS_WD{1'b0}};
else count <= count + 1'b1;
end
end
//baud_rate_clk_output
always @(posedge clk or negedge rst_n) begin
if (!rst_n) bps_clk <= 1'b0;
else if (count == 'd1) bps_clk <= 1'b1;
else bps_clk <= 1'b0;
end
//get_the_width_of_
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log2 = log2 + 1;
end
endfunction
endmodule
| 7.718982 |
module tx_controller_3bytes (
input clk,
input tx_start,
input [15:0] data_in,
output UART_TxD,
output tx_done
);
reg start_byte_tx_reg = 1'd0; // s_uart_tx
wire local_uart_busy; // s_uart_tx
assign local_uart_ready = ~local_uart_busy;
reg [7:0] tx_byte_reg = 'd0; // s_uart_tx
reg [15:0] data_in_latch = 'd0;
reg tx_done_reg = 1'd1; //
assign tx_done = tx_done_reg;
s_uart_tx #(10000000, 500000) local_uart (
.clk(clk),
.TxD_start(start_byte_tx_reg),
.TxD_data(tx_byte_reg),
.TxD(UART_TxD),
.TxD_busy(local_uart_busy)
);
reg [2:0] phase_cnt = 'd0;
reg lock_flag = 'd0;
reg [1:0] trig = 'd0;
always @(posedge clk) begin
trig <= {trig[0], tx_start};
end
assign tx_start_front = (trig == 2'b01) ? 1'b1 : 1'b0; //
always @(posedge clk) begin
if (tx_start_front == 1'd1) begin
phase_cnt <= 'd0;
tx_done_reg <= 1'd0;
data_in_latch <= data_in;
end
else if ((local_uart_ready == 1'd1) && (tx_done_reg == 1'd0) && (lock_flag == 1'd0))//
begin
case (phase_cnt)
'd0: phase_cnt <= phase_cnt + 'd1;
'd1: begin
tx_byte_reg <= 'd0; // 0
start_byte_tx_reg <= 1'd1; // 1
phase_cnt <= phase_cnt + 'd1;
lock_flag <= 1'd1;
end
'd2: begin
tx_byte_reg <= data_in_latch[15:8]; // 1
start_byte_tx_reg <= 1'd1; // 2
phase_cnt <= phase_cnt + 'd1;
lock_flag <= 1'd1;
end
'd3: begin
tx_byte_reg <= data_in_latch[7:0]; // 2
start_byte_tx_reg <= 1'd1; // 3
phase_cnt <= phase_cnt + 'd1;
lock_flag <= 1'd1;
end
'd4: begin
tx_done_reg <= 1'd1;
phase_cnt <= phase_cnt + 'd1;
end
endcase
end else begin
start_byte_tx_reg <= 1'd0;
lock_flag <= 1'd0;
end
end
endmodule
| 7.938688 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_control_module(
CLK,
RST_n,
Tx_En_Sig,
Tx_Data,
BPS_CLK,
Tx_Done_Sig,
Tx_Pin_Out
);
input CLK;
input RST_n;
input Tx_En_Sig;
input [7:0]Tx_Data;
input BPS_CLK;
output Tx_Done_Sig;
output Tx_Pin_Out;
reg [3:0]i;
reg rTx;
reg isDone;
always @(posedge CLK or negedge RST_n) begin
if (!RST_n) begin
i <= 4'd0;
rTx <= 1'b1; // rx线默认高电平
isDone <= 1'b0;
end
else if (Tx_En_Sig)
case (i)
4'd0:
begin
if (BPS_CLK) begin
i <= i + 1'b1;
rTx <= 1'b0; // 开始信号
end
end
4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8: // 发送数据
begin
if (BPS_CLK) begin
i <= i + 1'b1;
rTx <= Tx_Data[i-1]; //LSB
end
end
4'd9: // 停止位
begin
if (BPS_CLK) begin
i <= i + 1'b1;
rTx <= 1'b1;
end
end
4'd10:
begin
i <= i + 1'b1;
isDone <= 1'b1;
end
4'd11:
begin
i <= 4'd0;
isDone <= 1'b0;
end
endcase
end
assign Tx_Done_Sig = isDone;
assign Tx_Pin_Out = rTx;
endmodule
| 7.088073 |
module tx_ctrl_phase_tb;
parameter VCD_FILE = "tx_ctrl_phase.vcd";
parameter NUM_LANES = 1;
parameter BEATS_PER_LMFC = 20;
`include "tb_base.v"
reg lmfc_edge = 1'b0;
reg a_sync = 1'b0;
reg b_sync = 1'b0;
wire [31:0] a_ilas_data;
wire [3:0] a_ilas_charisk;
wire [1:0] a_ilas_config_addr;
wire a_ilas_config_rd;
wire a_tx_ready;
wire a_lane_cgs_enable;
wire [31:0] b_ilas_data;
wire [3:0] b_ilas_charisk;
wire [1:0] b_ilas_config_addr;
wire b_ilas_config_rd;
wire b_tx_ready;
wire b_lane_cgs_enable;
reg reset2 = 1'b1;
integer reset_counter = 0;
integer beat_counter = 0;
integer lmfc_counter = 0;
integer b_offset = 0;
always @(posedge clk) begin
if (reset2 == 1'b1) begin
if (reset_counter == 7) begin
reset2 <= 1'b0;
reset_counter <= 0;
end else begin
reset_counter <= reset_counter + 1;
end
end
if (reset2 == 1'b1) begin
beat_counter <= 0;
a_sync <= 1'b0;
b_sync <= 1'b0;
end else begin
beat_counter <= beat_counter + 1'b1;
if (beat_counter == BEATS_PER_LMFC * 2) begin
a_sync <= 1'b1;
end
if (beat_counter == BEATS_PER_LMFC * 2 + b_offset) begin
b_sync <= 1'b1;
end
if (beat_counter == BEATS_PER_LMFC * 9) begin
b_offset <= b_offset + 1;
reset2 <= 1'b1;
end
end
if (reset2 == 1'b1) begin
lmfc_counter <= BEATS_PER_LMFC - 3;
end else begin
lmfc_counter <= lmfc_counter + 1;
if (lmfc_counter == BEATS_PER_LMFC - 1) begin
lmfc_counter <= 0;
lmfc_edge <= 1'b1;
end else begin
lmfc_edge <= 1'b0;
end
end
end
jesd204_tx_ctrl i_tx_ctrl_a (
.clk (clk),
.reset(reset2),
.sync(a_sync),
.lmfc_edge(lmfc_edge),
.lane_cgs_enable(a_lane_cgs_enable),
.tx_ready(a_tx_ready),
.ilas_data(a_ilas_data),
.ilas_charisk(a_ilas_charisk),
.ilas_config_addr(a_ilas_config_addr),
.ilas_config_rd (a_ilas_config_rd),
.ilas_config_data('h00),
.ctrl_manual_sync_request(1'b0),
.cfg_continuous_cgs(1'b0),
.cfg_continuous_ilas(1'b0),
.cfg_skip_ilas(1'b0),
.cfg_mframes_per_ilas(8'h3)
);
jesd204_tx_ctrl i_tx_ctrl_b (
.clk (clk),
.reset(reset2),
.sync(b_sync),
.lmfc_edge(lmfc_edge),
.lane_cgs_enable(b_lane_cgs_enable),
.tx_ready(b_tx_ready),
.ilas_data(b_ilas_data),
.ilas_charisk(b_ilas_charisk),
.ilas_config_addr(b_ilas_config_addr),
.ilas_config_rd (b_ilas_config_rd),
.ilas_config_data('h00),
.ctrl_manual_sync_request(1'b0),
.cfg_continuous_cgs(1'b0),
.cfg_continuous_ilas(1'b0),
.cfg_skip_ilas(1'b0),
.cfg_mframes_per_ilas(8'h3)
);
reg status = 1'b1;
always @(*) begin
if (reset2 == 1'b1) begin
status <= 1'b1;
end else if (a_ilas_data != b_ilas_data ||
a_ilas_charisk != b_ilas_charisk ||
a_ilas_config_addr != b_ilas_config_addr ||
a_ilas_config_rd != b_ilas_config_rd ||
a_lane_cgs_enable != b_lane_cgs_enable ||
a_tx_ready != b_tx_ready) begin
status <= 1'b0;
end
end
reg message_shown = 1'b0;
always @(posedge clk) begin
if (status == 1'b0 && message_shown == 1'b0 && b_offset < BEATS_PER_LMFC) begin
$display("FAILED at offset %0d", b_offset);
message_shown <= 1'b1;
end
end
always @(posedge clk) begin
if (b_offset == BEATS_PER_LMFC + 1) begin
if (message_shown == 1'b0) $display("SUCCESS");
$finish;
end
end
endmodule
| 7.280345 |
module TX_DATA_COLLECTION_STATE_MACHINE (
input i_Clk,
input [63:0] number_of_ticks,
input w_TX_Active,
output w_TX_DV,
output [7:0] w_TX_Byte_reg
);
reg [3:0] byte_counter;
reg [7:0] store_nt[7:0];
reg [7:0] w_TX_Byte_reg_0;
reg [2:0] state_TX;
reg w_TX_DV_0;
parameter WAIT_TX = 3'd0,
START = 3'd1,
SEND = 3'd2,
DATA_VALID = 3'd3,
WAIT_DONE = 3'd4,
WAIT_CYCLE = 3'd5;
assign w_TX_Byte_reg = w_TX_Byte_reg_0;
assign w_TX_DV = w_TX_DV_0;
always @(posedge i_Clk) begin
case (state_TX)
WAIT_TX: begin
w_TX_DV_0 <= 1'b0;
if (w_TX_Active == 1'b1) state_TX <= WAIT_TX;
else state_TX <= START;
end
START: begin
store_nt[0] <= 8'hBB;
store_nt[1] <= number_of_ticks[7:0];
store_nt[2] <= number_of_ticks[15:8];
store_nt[3] <= number_of_ticks[23:16];
store_nt[4] <= number_of_ticks[31:24];
store_nt[5] <= number_of_ticks[39:32];
store_nt[6] <= number_of_ticks[47:40];
store_nt[7] <= 8'hAA;
byte_counter <= 4'b0;
w_TX_DV_0 <= 1'b0;
state_TX <= SEND;
end
SEND: begin
if (byte_counter != 4'd8) begin
w_TX_Byte_reg_0 <= store_nt[byte_counter];
w_TX_DV_0 <= 1'b0;
state_TX <= DATA_VALID;
end else begin
w_TX_DV_0 <= 1'b0;
byte_counter <= 4'b0;
state_TX <= WAIT_TX;
end
end
DATA_VALID: begin
w_TX_DV_0 <= 1'b1;
state_TX <= WAIT_CYCLE;
end
WAIT_DONE: begin
if (w_TX_Active == 1'b1) begin
state_TX <= WAIT_CYCLE;
w_TX_DV_0 <= 1'b0;
end else begin
byte_counter <= byte_counter + 4'b1;
w_TX_DV_0 <= 1'b0;
state_TX <= SEND;
end
end
WAIT_CYCLE: state_TX <= WAIT_DONE;
default: state_TX <= WAIT_TX;
endcase
end
endmodule
| 6.748206 |
module tx_dev_mem_management_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.634838 |
module tx_dev_mem_management_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.634838 |
module tx_dp (
input wire rst,
input wire tx_en,
input wire [7:0] din,
input wire [9:0] bit_cnto,
output reg tx_out
);
always @* begin
casex ({
rst, tx_en, bit_cnto
})
{1'b0, 1'bx, 10'dx} : tx_out = 1'b1; // reset control
{1'b1, 1'b0, 10'dx} : tx_out = 1'b1; // No tx
{1'b1, 1'b1, 10'd0} : tx_out = 1'b0; // TX start
{1'b1, 1'b1, 10'd1} : tx_out = din[0];
{1'b1, 1'b1, 10'd2} : tx_out = din[1];
{1'b1, 1'b1, 10'd3} : tx_out = din[2];
{1'b1, 1'b1, 10'd4} : tx_out = din[3];
{1'b1, 1'b1, 10'd5} : tx_out = din[4];
{1'b1, 1'b1, 10'd6} : tx_out = din[5];
{1'b1, 1'b1, 10'd7} : tx_out = din[6];
{1'b1, 1'b1, 10'd8} : tx_out = din[7];
{1'b1, 1'b1, 10'd9} : tx_out = 1'b1; // TX end
endcase
end
endmodule
| 7.138003 |
module implements the transmitter PHY for an IEEE-1355 link.
// The TxClk signal determines the actual transmission rate: one bit
// per rising edge of TxClk.
//
// The input-side of this module consists mainly of three signals:
//
// TxReset - if asserted, it forces D and S outputs 0.
// Tx1 - If asserted, it flips D and S outputs so as to reproduce
// a binary 1 at the receiver.
// Tx0 - If asserted, it flips D and S outputs so as to reproduce
// a binary 0 at the receiver.
//
// Under normal conditions, either Tx0 or Tx1 should be asserted;
// never both at the same time. Negating both Tx0 and Tx1 is
// useful for link reset situations, where the transmitter is
// attempting to emulate a disconnect condition.
module tx_DS_SE(
input TxClk,
input TxReset,
input Tx1,
input Tx0,
output D,
output S
);
reg D, S;
wire nextD = Tx1;
wire nextS = (Tx0 & ~(D^S)) | (Tx1 & (D^S));
always @(posedge TxClk) begin
D <= D;
S <= S;
if(TxReset) begin
{D, S} <= 2'b00;
end
else if(Tx0 | Tx1) begin
{D, S} <= {nextD, nextS};
end
end
endmodule
| 7.842559 |
module tx_dual_port_ram_8bit #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 6
) (
input [(DATA_WIDTH-1):0] data_a,
data_b,
input [(ADDR_WIDTH-1):0] addr_a,
addr_b,
input we_a,
we_b,
clk,
output reg [(DATA_WIDTH-1):0] q_a,
q_b
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
initial begin : INIT
$readmemb("C:/altera/16.0/myProjects/PHYctrl_100MbpS_Slave/tx_data.txt", ram);
end
// Port A
always @(posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a;
q_a <= data_a;
end else begin
q_a <= ram[addr_a];
end
end
// Port B
always @(posedge clk) begin
if (we_b) begin
ram[addr_b] <= data_b;
q_b <= data_b;
end else begin
q_b <= ram[addr_b];
end
end
endmodule
| 8.498193 |
module tx_eight_ten (
input wire clk,
input wire rst,
input wire sel,
input wire set,
input wire [7:0] din,
input wire [19:0] baud,
output wire tx_en,
output wire tx_out,
output wire [9:0] tx_d
);
wire [9:0] bit_cnto;
wire [9:0] bit_cntn;
wire [19:0] baud_cnto;
wire [19:0] baud_cntn;
wire baud_clk;
tx_eight_ten_cp tx_eight_ten_cp (
.rst (rst),
.sel (sel),
.set (set),
.baud_clk (baud_clk),
.bit_cnto (bit_cnto),
.baud (baud),
.bit_cntn(bit_cntn),
.tx_en(tx_en)
);
tx_eight_ten_dp tx_eight_ten_dp (
.rst (rst),
.tx_en (tx_en),
.tx_d (tx_d),
.bit_cnto (bit_cnto),
.tx_out(tx_out)
);
eight_ten eight_ten (
.din(din),
.tx_d(tx_d)
);
baud_counter baud_counter (
.rst (rst),
.en (tx_en),
.baud (baud),
.baud_cnto(baud_cnto),
.baud_cntn(baud_cntn),
.baud_clk (baud_clk)
);
PipeReg #(10) bit_cnt (
.CLK(clk),
.RST(rst),
.EN (1'b1),
.D (bit_cntn),
.Q (bit_cnto)
);
PipeReg #(20) baud_cnt (
.CLK(clk),
.RST(rst),
.EN (1'b1),
.D (baud_cntn),
.Q (baud_cnto)
);
endmodule
| 6.951924 |
module tx_eight_ten_cp (
input wire rst,
input wire sel,
input wire set,
input wire baud_clk,
input wire [9:0] bit_cnto,
input wire [19:0] baud,
output reg [9:0] bit_cntn,
output reg tx_en
);
wire valid_baud;
assign valid_baud = (baud >= 20'd15) ? 1'b1 : 1'b0;
always @* begin
casex ({
rst, sel, valid_baud, set, baud_clk, bit_cnto
})
{1'b1, 1'bx, 1'bx, 1'bx, 1'bx, 10'dx} : {tx_en, bit_cntn} = {1'b0, 10'd0}; // reset control
{1'b0, 1'b0, 1'bx, 1'bx, 1'bx, 10'dx} : {tx_en, bit_cntn} = {1'b0, 10'd0}; // standby
{1'b0, 1'b1, 1'b0, 1'bx, 1'bx, 10'dx} : {tx_en, bit_cntn} = {1'b0, 10'd0}; // invalid baud
{1'b0, 1'b1, 1'b1, 1'b0, 1'bx, 10'dx} : {tx_en, bit_cntn} = {1'b0, 10'd0}; // idling
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd0} : {tx_en, bit_cntn} = {1'b1, 10'd0}; // Start bit
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd0} : {tx_en, bit_cntn} = {1'b1, 10'd1};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd1} : {tx_en, bit_cntn} = {1'b1, 10'd1}; // din[0]
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd1} : {tx_en, bit_cntn} = {1'b1, 10'd2};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd2} : {tx_en, bit_cntn} = {1'b1, 10'd2}; // din[1]
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd2} : {tx_en, bit_cntn} = {1'b1, 10'd3};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd3} : {tx_en, bit_cntn} = {1'b1, 10'd3}; // din[2]
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd3} : {tx_en, bit_cntn} = {1'b1, 10'd4};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd4} : {tx_en, bit_cntn} = {1'b1, 10'd4}; // din[3]
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd4} : {tx_en, bit_cntn} = {1'b1, 10'd5};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd5} : {tx_en, bit_cntn} = {1'b1, 10'd5}; // din[4]
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd5} : {tx_en, bit_cntn} = {1'b1, 10'd6};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd6} : {tx_en, bit_cntn} = {1'b1, 10'd6}; // din[5]
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd6} : {tx_en, bit_cntn} = {1'b1, 10'd7};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd7} : {tx_en, bit_cntn} = {1'b1, 10'd7}; // din[6]
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd7} : {tx_en, bit_cntn} = {1'b1, 10'd8};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd8} : {tx_en, bit_cntn} = {1'b1, 10'd8}; // din[7]
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd8} : {tx_en, bit_cntn} = {1'b1, 10'd9};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd9} : {tx_en, bit_cntn} = {1'b1, 10'd9}; // din[8]
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd9} : {tx_en, bit_cntn} = {1'b1, 10'd10};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd10} : {tx_en, bit_cntn} = {1'b1, 10'd10}; // din[9]
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd10} : {tx_en, bit_cntn} = {1'b1, 10'd11};
{1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 10'd11} : {tx_en, bit_cntn} = {1'b1, 10'd11}; // stop bit
{1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 10'd11} : {tx_en, bit_cntn} = {1'b1, 10'd12};
{1'b0, 1'b1, 1'b1, 1'b1, 1'bx, 10'd12} : {tx_en, bit_cntn} = {1'b0, 10'd12}; // end tx
endcase
end
endmodule
| 7.463176 |
module tx_eight_ten_dp (
input wire rst,
input wire tx_en,
input wire [9:0] tx_d,
input wire [9:0] bit_cnto,
output reg tx_out
);
always @* begin
casex ({
rst, tx_en, bit_cnto
})
{1'b1, 1'bx, 10'dx} : tx_out = 1'b1; // reset control
{1'b0, 1'b0, 10'dx} : tx_out = 1'b1; // No tx
{1'b0, 1'b1, 10'd0} : tx_out = 1'b0; // TX start
{1'b0, 1'b1, 10'd1} : tx_out = tx_d[0];
{1'b0, 1'b1, 10'd2} : tx_out = tx_d[1];
{1'b0, 1'b1, 10'd3} : tx_out = tx_d[2];
{1'b0, 1'b1, 10'd4} : tx_out = tx_d[3];
{1'b0, 1'b1, 10'd5} : tx_out = tx_d[4];
{1'b0, 1'b1, 10'd6} : tx_out = tx_d[5];
{1'b0, 1'b1, 10'd7} : tx_out = tx_d[6];
{1'b0, 1'b1, 10'd8} : tx_out = tx_d[7];
{1'b0, 1'b1, 10'd9} : tx_out = tx_d[8];
{1'b0, 1'b1, 10'd10} : tx_out = tx_d[9];
{1'b0, 1'b1, 10'd11} : tx_out = 1'b1; // TX end
endcase
end
endmodule
| 7.463176 |
module tx_eight_ten_tb ();
localparam period = 5;
localparam cycle = period * 2;
reg clk;
reg rst;
reg sel;
reg set;
reg [ 7:0] din;
reg [19:0] baud;
wire tx_en;
wire tx_out;
wire [ 9:0] tx_d;
tx_eight_ten tx_eight_ten (
.clk (clk),
.rst (rst),
.sel (sel),
.set (set),
.din (din),
.baud(baud),
.tx_en (tx_en),
.tx_out(tx_out),
.tx_d (tx_d)
);
/* ------ !! ------
Clock generation
------ !! ------ */
initial clk <= 1'b1;
always #(period) clk <= ~clk;
/* ------ !! ------
Reset COntrol
------ !! ------ */
initial begin
rst <= 1'b1;
#(cycle * 2) rst <= 1'b0;
end
/* ------ !! ------
SIMULATION !!!
------ !! ------ */
initial begin
baud <= 20'd20; // set bauddiv
sel <= 1'b1;
#(cycle * 4) din <= 8'b0011_0011;
set <= 1'b1;
#(cycle * 240) set <= 1'b0;
#(cycle * 2) $finish();
end
endmodule
| 7.463176 |
module tx_enc8 ( // input
input CLK_40,
input RST_X,
input VALID,
input SYN_RST,
input [7:0] DATA_IN,
output reg [15:0] DATA_OUT
);
reg [5:0] r_enc0;
wire [5:0] r_enc1, r_enc2, r_enc3, r_enc4, r_enc5, r_enc6, r_enc7, r_enc8;
wire [15:0] code;
assign r_enc1 = {DATA_IN[0], r_enc0[5:1]};
assign r_enc2 = {DATA_IN[1], r_enc1[5:1]};
assign r_enc3 = {DATA_IN[2], r_enc2[5:1]};
assign r_enc4 = {DATA_IN[3], r_enc3[5:1]};
assign r_enc5 = {DATA_IN[4], r_enc4[5:1]};
assign r_enc6 = {DATA_IN[5], r_enc5[5:1]};
assign r_enc7 = {DATA_IN[6], r_enc6[5:1]};
assign r_enc8 = {DATA_IN[7], r_enc7[5:1]};
assign code[0] = DATA_IN[0] ^ r_enc0[4] ^ r_enc0[3] ^ r_enc0[0] ^ r_enc0[1];
assign code[2] = DATA_IN[1] ^ r_enc1[4] ^ r_enc1[3] ^ r_enc1[0] ^ r_enc1[1];
assign code[4] = DATA_IN[2] ^ r_enc2[4] ^ r_enc2[3] ^ r_enc2[0] ^ r_enc2[1];
assign code[6] = DATA_IN[3] ^ r_enc3[4] ^ r_enc3[3] ^ r_enc3[0] ^ r_enc3[1];
assign code[8] = DATA_IN[4] ^ r_enc4[4] ^ r_enc4[3] ^ r_enc4[0] ^ r_enc4[1];
assign code[10] = DATA_IN[5] ^ r_enc5[4] ^ r_enc5[3] ^ r_enc5[0] ^ r_enc5[1];
assign code[12] = DATA_IN[6] ^ r_enc6[4] ^ r_enc6[3] ^ r_enc6[0] ^ r_enc6[1];
assign code[14] = DATA_IN[7] ^ r_enc7[4] ^ r_enc7[3] ^ r_enc7[0] ^ r_enc7[1];
assign code[1] = DATA_IN[0] ^ r_enc0[4] ^ r_enc0[3] ^ r_enc0[0] ^ r_enc0[5];
assign code[3] = DATA_IN[1] ^ r_enc1[4] ^ r_enc1[3] ^ r_enc1[0] ^ r_enc1[5];
assign code[5] = DATA_IN[2] ^ r_enc2[4] ^ r_enc2[3] ^ r_enc2[0] ^ r_enc2[5];
assign code[7] = DATA_IN[3] ^ r_enc3[4] ^ r_enc3[3] ^ r_enc3[0] ^ r_enc3[5];
assign code[9] = DATA_IN[4] ^ r_enc4[4] ^ r_enc4[3] ^ r_enc4[0] ^ r_enc4[5];
assign code[11] = DATA_IN[5] ^ r_enc5[4] ^ r_enc5[3] ^ r_enc5[0] ^ r_enc5[5];
assign code[13] = DATA_IN[6] ^ r_enc6[4] ^ r_enc6[3] ^ r_enc6[0] ^ r_enc6[5];
assign code[15] = DATA_IN[7] ^ r_enc7[4] ^ r_enc7[3] ^ r_enc7[0] ^ r_enc7[5];
always @(posedge CLK_40 or negedge RST_X)
if (!RST_X) begin
r_enc0 <= 6'd0;
DATA_OUT <= 16'd0;
end else if (SYN_RST == 1'b1) begin
r_enc0 <= 6'd0;
DATA_OUT <= 16'd0;
end else if (VALID == 1'b1) begin
r_enc0 <= r_enc8;
DATA_OUT <= code;
end
endmodule
| 7.132013 |
module tx_phi #(
parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_MUX_TYPE = "SHIFT",
parameter C_WIDTH = (C_PCI_DATA_WIDTH + 2 * (clog2s(C_PCI_DATA_WIDTH / 32) + 1))
) ( // Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: TXC Flow Control
input TXC_TLP_READY,
// Interface: TXR Flow Control
input TXR_TLP_READY,
// Interface: TXC
input [ C_PCI_DATA_WIDTH-1:0] TXC_TLP,
input TXC_TLP_VALID,
input TXC_TLP_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET,
input TXC_TLP_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET,
// Interface: TXR
input [ C_PCI_DATA_WIDTH-1:0] TXR_TLP,
input TXR_TLP_VALID,
input TXR_TLP_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET,
input TXR_TLP_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET,
// Interface: TX Classic
output [ C_PCI_DATA_WIDTH-1:0] TX_TLP,
output TX_TLP_VALID,
output TX_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_START_OFFSET,
output TX_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TX_TLP_END_OFFSET
);
// Width = 2 * (DATA WIDTH + VALID + START FLAG + START OFFSET + END FLAG + END OFFSET)
localparam C_MUX_WIDTH = C_PCI_DATA_WIDTH + 3 + 2 * clog2s(C_PCI_DATA_WIDTH / 32);
wire [2*C_MUX_WIDTH-1:0] wAggregate;
assign wAggregate = {
{
TXR_TLP,
TXR_TLP_VALID,
TXR_TLP_START_FLAG,
TXR_TLP_START_OFFSET,
TXR_TLP_END_FLAG,
TXR_TLP_END_OFFSET
},
{
TXC_TLP,
TXC_TLP_VALID,
TXC_TLP_START_FLAG,
TXC_TLP_START_OFFSET,
TXC_TLP_END_FLAG,
TXC_TLP_END_OFFSET
}
};
mux #( // Parameters
.C_NUM_INPUTS (2),
.C_CLOG_NUM_INPUTS(1),
.C_WIDTH (C_MUX_WIDTH),
.C_MUX_TYPE ("SELECT")
/*AUTOINSTPARAM*/) mux_inst ( // Outputs
.MUX_OUTPUT({
TX_TLP,
TX_TLP_VALID,
TX_TLP_START_FLAG,
TX_TLP_START_OFFSET,
TX_TLP_END_FLAG,
TX_TLP_END_OFFSET
}),
// Inputs
.MUX_INPUTS(wAggregate),
.MUX_SELECT(TXR_TLP_READY)
/*AUTOINST*/);
endmodule
| 9.141296 |
module tx_engine_formatter_128 #(
parameter C_PCI_DATA_WIDTH = 9'd128,
// Local parameters
parameter C_TRAFFIC_CLASS = 3'b0,
parameter C_RELAXED_ORDER = 1'b0,
parameter C_NO_SNOOP = 1'b0
) (
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input VALID, // Are input parameters valid?
input WNR, // Is a write request, not a read?
input [ 7:0] TAG, // External tag
input [ 3:0] CHNL, // Internal tag (just channel portion)
input [ 61:0] ADDR, // Request address
input ADDR_64, // Request address is 64 bit
input [ 9:0] LEN, // Request length
input LEN_ONE, // Request length equals 1
input [C_PCI_DATA_WIDTH-1:0] WR_DATA, // Request data, timed to arrive accordingly
output [C_PCI_DATA_WIDTH-1:0] OUT_DATA, // Formatted PCI packet data
output OUT_DATA_WEN // Write enable for formatted packet data
);
reg rState = `S_TXENGFMTR128_IDLE, _rState = `S_TXENGFMTR128_IDLE;
reg rAddr64 = 0, _rAddr64 = 0;
reg [C_PCI_DATA_WIDTH-1:0] rData = {C_PCI_DATA_WIDTH{1'd0}}, _rData = {C_PCI_DATA_WIDTH{1'd0}};
reg [C_PCI_DATA_WIDTH-1:0]
rPrevData = {C_PCI_DATA_WIDTH{1'd0}}, _rPrevData = {C_PCI_DATA_WIDTH{1'd0}};
reg rDataWen = 0, _rDataWen = 0;
reg [9:0] rLen = 0, _rLen = 0;
reg rDone = 0, _rDone = 0;
assign OUT_DATA = rData;
assign OUT_DATA_WEN = rDataWen;
// Format read and write requests into PCIe packets.
wire [63:0] wHdrData = ({WR_DATA[31:0], ADDR[29:0], 2'b00, ADDR[61:30]}) >> (32 * (!ADDR_64));
wire [C_PCI_DATA_WIDTH-1:0] wWrData = ({WR_DATA[31:0], rPrevData}) >> (32 * (!rAddr64));
always @(posedge CLK) begin
rState <= #1 (RST ? `S_TXENGFMTR128_IDLE : _rState);
rDataWen <= #1 (RST ? 1'd0 : _rDataWen);
rData <= #1 _rData;
rLen <= #1 _rLen;
rAddr64 <= #1 _rAddr64;
rPrevData <= #1 _rPrevData;
rDone <= #1 _rDone;
end
always @(*) begin
_rState = rState;
_rLen = rLen;
_rData = rData;
_rDataWen = rDataWen;
_rPrevData = WR_DATA;
_rAddr64 = rAddr64;
case (rState)
`S_TXENGFMTR128_IDLE: begin // FIFO data should be available now (if it's a write)
_rLen = LEN - !ADDR_64; // Subtract 1 for 32 bit (HDR has one)
_rAddr64 = ADDR_64;
_rData = {
wHdrData, // DW3, DW2
CONFIG_COMPLETER_ID[15:3],
3'b0,
TAG,
(LEN_ONE ? 4'b0 : 4'b1111),
4'b1111, // DW1
1'b0,
{WNR, ADDR_64, 5'd0},
1'b0,
C_TRAFFIC_CLASS,
CHNL,
1'b0,
1'b0, // Use the reserved 4 bits before traffic class to hide the internal tag
C_RELAXED_ORDER,
C_NO_SNOOP,
2'b0,
LEN
}; // DW0
_rDataWen = VALID;
_rDone = (LEN <= {1'b1, 1'b0, !ADDR_64});
_rState = (VALID & WNR & (ADDR_64 | !LEN_ONE) ? `S_TXENGFMTR128_WR : `S_TXENGFMTR128_IDLE);
end
`S_TXENGFMTR128_WR: begin
_rLen = rLen - 3'd4;
_rDone = (rLen <= 4'd8);
_rData = wWrData;
_rState = (rDone ? `S_TXENGFMTR128_IDLE : `S_TXENGFMTR128_WR);
end
endcase
end
endmodule
| 8.607781 |
module tx_engine_formatter_32 #(
parameter C_PCI_DATA_WIDTH = 9'd32,
// Local parameters
parameter C_TRAFFIC_CLASS = 3'b0,
parameter C_RELAXED_ORDER = 1'b0,
parameter C_NO_SNOOP = 1'b0
) (
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input VALID, // Are input parameters valid?
input WNR, // Is a write request, not a read?
input [ 7:0] TAG, // External tag
input [ 3:0] CHNL, // Internal tag (just channel portion)
input [ 61:0] ADDR, // Request address
input ADDR_64, // Request address is 64 bit
input [ 9:0] LEN, // Request length
input LEN_ONE, // Request length equals 1
input [C_PCI_DATA_WIDTH-1:0] WR_DATA, // Request data, timed to arrive accordingly
output [C_PCI_DATA_WIDTH-1:0] OUT_DATA, // Formatted PCI packet data
output OUT_DATA_WEN // Write enable for formatted packet data
);
reg [2:0] rState = `S_TXENGFMTR32_IDLE, _rState = `S_TXENGFMTR32_IDLE;
reg [61:0] rAddr = 62'd0, _rAddr = 62'd0;
reg rAddr64 = 0, _rAddr64 = 0;
reg [C_PCI_DATA_WIDTH-1:0] rData = {C_PCI_DATA_WIDTH{1'd0}}, _rData = {C_PCI_DATA_WIDTH{1'd0}};
reg [C_PCI_DATA_WIDTH-1:0]
rPrevData = {C_PCI_DATA_WIDTH{1'd0}}, _rPrevData = {C_PCI_DATA_WIDTH{1'd0}};
reg rDataWen = 0, _rDataWen = 0;
reg [9:0] rLen = 0, _rLen = 0;
reg rLenEQ1 = 0, _rLenEQ1 = 0;
reg rWNR = 0, _rWNR = 0;
reg [7:0] rTag = 0, _rTag = 0;
reg rInitDone = 0, _rInitDone = 0;
reg rDone = 0, _rDone = 0;
assign OUT_DATA = rData;
assign OUT_DATA_WEN = rDataWen;
// Format read and write requests into PCIe packets.
wire [31:0] wData = ({rPrevData, WR_DATA} >> (32 * rAddr64));
always @(posedge CLK) begin
rState <= #1 (RST ? `S_TXENGFMTR32_IDLE : _rState);
rDataWen <= #1 (RST ? 1'd0 : _rDataWen);
rData <= #1 _rData;
rLen <= #1 _rLen;
rAddr <= #1 _rAddr;
rAddr64 <= #1 _rAddr64;
rWNR <= #1 _rWNR;
rTag <= #1 _rTag;
rLenEQ1 <= #1 _rLenEQ1;
rInitDone <= #1 _rInitDone;
rDone <= #1 _rDone;
rPrevData <= #1 _rPrevData;
end
always @(*) begin
_rState = rState;
_rLen = rLen;
_rData = rData;
_rDataWen = rDataWen;
_rAddr64 = rAddr64;
_rAddr = rAddr;
_rWNR = rWNR;
_rTag = rTag;
_rLenEQ1 = rLenEQ1;
_rInitDone = rInitDone;
_rDone = rDone;
_rPrevData = WR_DATA;
case (rState)
`S_TXENGFMTR32_IDLE: begin
_rLen = LEN;
_rAddr64 = ADDR_64;
_rAddr = ADDR;
_rWNR = WNR;
_rTag = TAG;
_rLenEQ1 = LEN_ONE;
_rData = {
1'b0,
{WNR, ADDR_64, 5'd0},
1'b0,
C_TRAFFIC_CLASS,
CHNL,
1'b0,
1'b0, // Use the reserved 4 bits before traffic class to hide the internal tag
C_RELAXED_ORDER,
C_NO_SNOOP,
2'b0,
LEN
};
_rDataWen = VALID;
_rState = (VALID ? `S_TXENGFMTR32_HDR_0 : `S_TXENGFMTR32_IDLE);
end
`S_TXENGFMTR32_HDR_0: begin
_rData = {CONFIG_COMPLETER_ID[15:3], 3'b0, rTag, (rLenEQ1 ? 4'b0 : 4'b1111), 4'b1111};
_rInitDone = (!rAddr64 & !rWNR);
_rState = (rAddr64 ? `S_TXENGFMTR32_HDR_1 : `S_TXENGFMTR32_HDR_2);
end
`S_TXENGFMTR32_HDR_1: begin
_rData = rAddr[61:30];
_rInitDone = !rWNR;
_rState = `S_TXENGFMTR32_HDR_2;
end
`S_TXENGFMTR32_HDR_2: begin // FIFO data should be available now (if it's a write)
_rData = {rAddr[29:0], 2'b00};
_rDone = rLenEQ1;
_rState = (rInitDone ? `S_TXENGFMTR32_IDLE : `S_TXENGFMTR32_WR);
end
`S_TXENGFMTR32_WR: begin
_rLen = rLen - 1'd1;
_rData = wData;
_rDone = (rLen == 2'd2);
_rState = (rDone ? `S_TXENGFMTR32_IDLE : `S_TXENGFMTR32_WR);
end
default: begin
_rState = `S_TXENGFMTR32_IDLE;
end
endcase
end
endmodule
| 8.607781 |
module tx_engine_formatter_64 #(
parameter C_PCI_DATA_WIDTH = 9'd64,
// Local parameters
parameter C_TRAFFIC_CLASS = 3'b0,
parameter C_RELAXED_ORDER = 1'b0,
parameter C_NO_SNOOP = 1'b0
) (
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input VALID, // Are input parameters valid?
input WNR, // Is a write request, not a read?
input [ 7:0] TAG, // External tag
input [ 3:0] CHNL, // Internal tag (just channel portion)
input [ 61:0] ADDR, // Request address
input ADDR_64, // Request address is 64 bit
input [ 9:0] LEN, // Request length
input LEN_ONE, // Request length equals 1
input [C_PCI_DATA_WIDTH-1:0] WR_DATA, // Request data, timed to arrive accordingly
output [C_PCI_DATA_WIDTH-1:0] OUT_DATA, // Formatted PCI packet data
output OUT_DATA_WEN // Write enable for formatted packet data
);
(* fsm_encoding = "user" *)
reg [1:0] rState = `S_TXENGFMTR64_IDLE, _rState = `S_TXENGFMTR64_IDLE;
reg [61:0] rAddr = 62'd0, _rAddr = 62'd0;
reg rAddr64 = 0, _rAddr64 = 0;
reg [C_PCI_DATA_WIDTH-1:0] rData = {C_PCI_DATA_WIDTH{1'd0}}, _rData = {C_PCI_DATA_WIDTH{1'd0}};
reg [C_PCI_DATA_WIDTH-1:0]
rPrevData = {C_PCI_DATA_WIDTH{1'd0}}, _rPrevData = {C_PCI_DATA_WIDTH{1'd0}};
reg rDataWen = 0, _rDataWen = 0;
reg [9:0] rLen = 0, _rLen = 0;
reg rInitDone = 0, _rInitDone = 0;
reg rDone = 0, _rDone = 0;
assign OUT_DATA = rData;
assign OUT_DATA_WEN = rDataWen;
// Format read and write requests into PCIe packets.
wire [C_PCI_DATA_WIDTH-1:0] wHdrData = ({WR_DATA[31:0], rAddr[29:0], 2'b00, rAddr[61:30]})>>(32*(!rAddr64));
wire [C_PCI_DATA_WIDTH-1:0] wWrData = ({WR_DATA[31:0], rPrevData}) >> (32 * (!rAddr64));
always @(posedge CLK) begin
rState <= #1 (RST ? `S_TXENGFMTR64_IDLE : _rState);
rDataWen <= #1 (RST ? 1'd0 : _rDataWen);
rData <= #1 _rData;
rLen <= #1 _rLen;
rAddr <= #1 _rAddr;
rAddr64 <= #1 _rAddr64;
rPrevData <= #1 _rPrevData;
rInitDone <= #1 _rInitDone;
rDone <= #1 _rDone;
end
always @(*) begin
_rState = rState;
_rLen = rLen;
_rData = rData;
_rDataWen = rDataWen;
_rPrevData = WR_DATA;
_rAddr64 = rAddr64;
_rAddr = rAddr;
_rInitDone = rInitDone;
_rDone = (rLen <= 3'd4);
case (rState)
`S_TXENGFMTR64_IDLE: begin
_rLen = LEN - !ADDR_64 + 2'd2; // Subtract 1 for 32 bit (HDR has one), add 2 so we can always decrement by 2
_rAddr64 = ADDR_64;
_rAddr = ADDR;
_rData = {
CONFIG_COMPLETER_ID[15:3],
3'b0,
TAG,
(LEN_ONE ? 4'b0 : 4'b1111),
4'b1111, // DW1
1'b0,
{WNR, ADDR_64, 5'd0},
1'b0,
C_TRAFFIC_CLASS,
CHNL,
1'b0,
1'b0, // Use the reserved 4 bits before traffic class to hide the internal tag
C_RELAXED_ORDER,
C_NO_SNOOP,
2'b0,
LEN
}; // DW0
_rDataWen = VALID;
_rInitDone = ((!ADDR_64 & LEN_ONE) | !WNR);
_rState = (VALID ? `S_TXENGFMTR64_HDR : `S_TXENGFMTR64_IDLE);
end
`S_TXENGFMTR64_HDR: begin // FIFO data should be available now (if it's a write)
_rLen = rLen - 2'd2;
_rData = wHdrData;
_rState = (rInitDone ? `S_TXENGFMTR64_IDLE : `S_TXENGFMTR64_WR);
end
`S_TXENGFMTR64_WR: begin
_rLen = rLen - 2'd2;
_rData = wWrData;
_rState = (rDone ? `S_TXENGFMTR64_IDLE : `S_TXENGFMTR64_WR);
end
default: begin
_rState = `S_TXENGFMTR64_IDLE;
end
endcase
end
endmodule
| 8.607781 |
module tx_fifo (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count
);
input rst;
input wr_clk;
input rd_clk;
input [63 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
output [13 : 0] rd_data_count;
output [10 : 0] wr_data_count;
endmodule
| 7.105997 |
module tx_fifo_ext (
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full,
prog_full
);
input clk;
input [63 : 0] din;
input rd_en;
input rst;
input wr_en;
output [63 : 0] dout;
output empty;
output full;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V4_4 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(7),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(64),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex5"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(62),
.C_PROG_FULL_THRESH_NEGATE_VAL(61),
.C_PROG_FULL_TYPE(1),
.C_RD_DATA_COUNT_WIDTH(7),
.C_RD_DEPTH(64),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(6),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(7),
.C_WR_DEPTH(64),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(6),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.CLK(clk),
.DIN(din),
.RD_EN(rd_en),
.RST(rst),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.PROG_FULL(prog_full),
.INT_CLK(1'b0),
.BACKUP(0),
.BACKUP_MARKER(0),
.PROG_EMPTY_THRESH(0),
.PROG_EMPTY_THRESH_ASSERT(0),
.PROG_EMPTY_THRESH_NEGATE(0),
.PROG_FULL_THRESH(0),
.PROG_FULL_THRESH_ASSERT(0),
.PROG_FULL_THRESH_NEGATE(0),
.RD_CLK(0),
.RD_RST(1'b0),
.SRST(1'b0),
.WR_CLK(1'b0),
.WR_RST(1'b0),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 6.855826 |
module tx_fill_parts #(
parameter WIDTH = 16
) (
input reset,
input s_ul_clk,
input incb_valid,
output incb_ready,
input [WIDTH-1:0] incb_size,
input [ 4:0] incb_idx,
input decb_valid,
input [WIDTH-1:0] decb_size,
input [ 4:0] decb_idx,
input [4:0] cur_buf_num,
output inc_buf
);
reg [4:0] buf_max_written;
localparam ST_IDLE = 0;
localparam ST_CHECK = 1;
reg state;
wire [WIDTH-1:0] ram_out;
assign incb_ready = ~decb_valid && (state == ST_IDLE);
wire inc_cycle = incb_valid && incb_ready;
wire dec_cycle = decb_valid;
wire check_cycle = ~dec_cycle && ~inc_cycle;
wire [4:0] ram_addr = (dec_cycle) ? decb_idx :
(check_cycle) ? cur_buf_num /*buf_last_commited*/ : incb_idx;
wire ram_we = inc_cycle || dec_cycle;
wire [WIDTH-1:0] writeback_dec = ram_out - decb_size;
wire [WIDTH-1:0] writeback = (inc_cycle) ? incb_size : writeback_dec;
//assign decb_last = (writeback_dec == 0);
// FIXME to reg!!
assign inc_buf = ~dec_cycle && ~dec_cycle && (state == ST_CHECK) && (ram_out == 0);
always @(posedge s_ul_clk) begin
if (reset) begin
//buf_last_commited <= 5'b0_0000;
buf_max_written <= 5'b1_1111;
state <= ST_IDLE;
end else begin
if (dec_cycle) begin
state <= ST_CHECK;
end else if (inc_cycle) begin
buf_max_written <= incb_idx;
end else if (state == ST_CHECK) begin // check_cycle
if (ram_out == 0) begin
// Buffer has been filled
//buf_last_commited <= buf_last_commited + 1'b1;
if (buf_max_written == cur_buf_num /*buf_last_commited*/) state <= ST_IDLE;
end else begin
state <= ST_IDLE;
end
end
end
end
ram32xsp #(
.WIDTH(WIDTH)
) storage (
.wclk(s_ul_clk),
.we(ram_we),
.addr(ram_addr),
.datai(writeback),
.datao(ram_out)
);
endmodule
| 7.314249 |
module tx_frontend #(
parameter BASE = 0,
parameter WIDTH_OUT = 16,
parameter IQCOMP_EN = 1
) (
input clk,
input rst,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
input [23:0] tx_i,
input [23:0] tx_q,
input run,
output reg [WIDTH_OUT-1:0] dac_a,
output reg [WIDTH_OUT-1:0] dac_b
);
// IQ balance --> DC offset --> rounding --> mux
wire [23:0] i_dco, q_dco, i_ofs, q_ofs;
wire [WIDTH_OUT-1:0] i_final, q_final;
wire [7:0] mux_ctrl;
wire [35:0] corr_i, corr_q;
wire [23:0] i_bal, q_bal;
wire [17:0] mag_corr, phase_corr;
setting_reg #(
.my_addr(BASE + 0),
.width (24)
) sr_0 (
.clk(clk),
.rst(rst),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out(i_dco),
.changed()
);
setting_reg #(
.my_addr(BASE + 1),
.width (24)
) sr_1 (
.clk(clk),
.rst(rst),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out(q_dco),
.changed()
);
setting_reg #(
.my_addr(BASE + 2),
.width (18)
) sr_2 (
.clk(clk),
.rst(rst),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out(mag_corr),
.changed()
);
setting_reg #(
.my_addr(BASE + 3),
.width (18)
) sr_3 (
.clk(clk),
.rst(rst),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out(phase_corr),
.changed()
);
setting_reg #(
.my_addr(BASE + 4),
.width (8)
) sr_4 (
.clk(clk),
.rst(rst),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out(mux_ctrl),
.changed()
);
generate
if (IQCOMP_EN == 1) begin
// IQ Balance
MULT18X18S mult_mag_corr (
.P (corr_i),
.A (tx_i[23:6]),
.B (mag_corr),
.C (clk),
.CE(1),
.R (rst)
);
MULT18X18S mult_phase_corr (
.P (corr_q),
.A (tx_i[23:6]),
.B (phase_corr),
.C (clk),
.CE(1),
.R (rst)
);
add2_and_clip_reg #(
.WIDTH(24)
) add_clip_i (
.clk(clk),
.rst(rst),
.in1(tx_i),
.in2(corr_i[35:12]),
.strobe_in(1'b1),
.sum(i_bal),
.strobe_out()
);
add2_and_clip_reg #(
.WIDTH(24)
) add_clip_q (
.clk(clk),
.rst(rst),
.in1(tx_q),
.in2(corr_q[35:12]),
.strobe_in(1'b1),
.sum(q_bal),
.strobe_out()
);
// DC Offset
add2_and_clip_reg #(
.WIDTH(24)
) add_dco_i (
.clk(clk),
.rst(rst),
.in1(i_dco),
.in2(i_bal),
.strobe_in(1'b1),
.sum(i_ofs),
.strobe_out()
);
add2_and_clip_reg #(
.WIDTH(24)
) add_dco_q (
.clk(clk),
.rst(rst),
.in1(q_dco),
.in2(q_bal),
.strobe_in(1'b1),
.sum(q_ofs),
.strobe_out()
);
end // if (IQCOMP_EN==1)
else
begin
// DC Offset
add2_and_clip_reg #(
.WIDTH(24)
) add_dco_i (
.clk(clk),
.rst(rst),
.in1(i_dco),
.in2(tx_i),
.strobe_in(1'b1),
.sum(i_ofs),
.strobe_out()
);
add2_and_clip_reg #(
.WIDTH(24)
) add_dco_q (
.clk(clk),
.rst(rst),
.in1(q_dco),
.in2(tx_q),
.strobe_in(1'b1),
.sum(q_ofs),
.strobe_out()
);
end // else: !if(IQCOMP_EN==1)
endgenerate
// Rounding
round_sd #(
.WIDTH_IN (24),
.WIDTH_OUT(WIDTH_OUT)
) round_i (
.clk(clk),
.reset(rst),
.in(i_ofs),
.strobe_in(1'b1),
.out(i_final),
.strobe_out()
);
round_sd #(
.WIDTH_IN (24),
.WIDTH_OUT(WIDTH_OUT)
) round_q (
.clk(clk),
.reset(rst),
.in(q_ofs),
.strobe_in(1'b1),
.out(q_final),
.strobe_out()
);
// Mux
always @(posedge clk)
case (mux_ctrl[3:0])
0: dac_a <= i_final;
1: dac_a <= q_final;
default: dac_a <= 0;
endcase // case (mux_ctrl[3:0])
always @(posedge clk)
case (mux_ctrl[7:4])
0: dac_b <= i_final;
1: dac_b <= q_final;
default: dac_b <= 0;
endcase // case (mux_ctrl[7:4])
endmodule
| 6.690853 |
module tx_gate (
out,
sel,
in
);
output out;
input sel, in;
wire sel_bar;
pmos (out, in, sel_bar);
nmos (out, in, sel);
cmos_inverter inv (
sel_bar,
sel
);
pulldown (out);
endmodule
| 6.815097 |
module tx_get (
input clk,
input rst_n,
//ǰ
input pre_frame_vsync,
input pre_frame_href,
input pre_frame_clken,
input [7 : 0] pre_img,
input [7 : 0] A_value,
//
output post_frame_vsync,
output post_frame_href,
output post_frame_clken,
output [7 : 0] post_img
);
parameter modification_value = 8'd243; //modification_value=0.95*2^8,
reg [15 : 0] modify_A;
reg pre_frame_vsync_d1;
reg pre_frame_href_d1;
reg pre_frame_clken_d1;
reg [ 7 : 0] A_value_d1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
modify_A <= 0;
end else begin
modify_A <= (pre_img << 8) - pre_img - (pre_img << 2) - (pre_img << 3); //pre_img * modification_value
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
pre_frame_vsync_d1 <= 0;
pre_frame_href_d1 <= 0;
pre_frame_clken_d1 <= 0;
A_value_d1 <= 0;
end else begin
pre_frame_vsync_d1 <= pre_frame_vsync;
pre_frame_href_d1 <= pre_frame_href;
pre_frame_clken_d1 <= pre_frame_clken;
A_value_d1 <= A_value;
end
end
assign post_frame_vsync = pre_frame_vsync_d1;
assign post_frame_href = pre_frame_href_d1;
assign post_frame_clken = pre_frame_clken_d1;
assign post_img = 8'd255 - modify_A / A_value_d1;
endmodule
| 7.756549 |
module tx_ibuf #(
parameter AW = 9,
parameter DW = 64
) (
input [AW-1:0] a,
input [DW-1:0] d,
input we,
input [AW-1:0] dpra,
input clk,
input qdpo_clk,
output reg [DW-1:0] qdpo
);
//-------------------------------------------------------
// Local port a
//-------------------------------------------------------
reg [AW-1:0] a_reg;
reg [DW-1:0] d_reg;
reg we_reg;
reg [DW-1:0] dpram [(2**AW)-1:0];
//-------------------------------------------------------
// Local port b
//-------------------------------------------------------
reg [AW-1:0] dpra_reg;
////////////////////////////////////////////////
// port a
////////////////////////////////////////////////
always @(posedge clk) begin
a_reg <= a;
d_reg <= d;
we_reg <= we;
if (we_reg) begin
dpram[a_reg] <= d_reg;
end
end //always
////////////////////////////////////////////////
// port b
////////////////////////////////////////////////
always @(posedge qdpo_clk) begin
dpra_reg <= dpra;
qdpo <= dpram[dpra];
end //always
endmodule
| 7.694022 |
module is used to replace the K28.5 comma with K28.5+ / K28.6- when
// manchest is enable
// so the received side can detect the polarity according to the received
// K28.5 and K28.6 comma's polarity
// K28.5+: 0011111010 K28.5-: 1100000101 (lsb to msb)
// K28.6+: 0011110110 K28.6-: 1100001001
// the previous 8b10b encode will only output K28.5+ and K28.5- encoded
// commas
// so we will detect K28.5 and replace it with
// K28.5+ -> K28.2+
// K28.5- -> K28.6-
//
module TX_INSRT_POL_COMMA #(
parameter ORI_COMMA_POS = 10'b01_0111_1100 //K28.5+
,parameter REP_COMMA_POS = 10'b10_1011_1100 //K28.2+
,parameter REP_COMMA_NEG = 10'b10_0100_0011 //K28.6-
)(
input i_clk
,input i_rst_n
,input i_en
,input [9:0] i_ori_data
,output [9:0] o_rep_data
);
reg [9:0] r_rep_data;
always@(posedge i_clk or negedge i_rst_n) begin
if (~i_rst_n) begin
r_rep_data <= `DELAY ORI_COMMA_POS;
end
else begin
if(i_ori_data == ORI_COMMA_POS)
r_rep_data <= `DELAY REP_COMMA_POS;
else if(i_ori_data == (~ORI_COMMA_POS))
r_rep_data <= `DELAY REP_COMMA_NEG;
else
r_rep_data <= `DELAY i_ori_data;
end
end
assign o_rep_data = i_en ? r_rep_data : i_ori_data;
endmodule
| 9.406588 |
module tx_interrupt_selection (
// selection
input wire [2:0] src_sel,
// src
input wire s00_axis_tlast,
input wire phy_tx_start,
input wire tx_start_from_acc,
input wire tx_end_from_acc,
input wire tx_try_complete,
// to ps interrupt
output reg tx_itrpt
);
always @( src_sel, s00_axis_tlast,phy_tx_start, tx_start_from_acc, tx_end_from_acc,tx_try_complete)
begin
case (src_sel)
3'b000: begin
tx_itrpt = s00_axis_tlast;
end
3'b001: begin
tx_itrpt = phy_tx_start;
end
3'b010: begin
tx_itrpt = tx_start_from_acc;
end
3'b011: begin
tx_itrpt = tx_end_from_acc;
end
3'b100: begin
tx_itrpt = tx_try_complete;
end
default: begin
tx_itrpt = 0;
end
endcase
end
endmodule
| 7.390375 |
module tx_intf_ant_selection #(
parameter integer IQ_DATA_WIDTH = 16,
parameter integer DAC_PACK_DATA_WIDTH = 64
) (
input wire [DAC_PACK_DATA_WIDTH-1 : 0] data_in,
input wire [1:0] ant_flag,
output reg [DAC_PACK_DATA_WIDTH-1 : 0] data_out
);
localparam integer MSB_IDX = (DAC_PACK_DATA_WIDTH - 1);
localparam integer MSB_HALF_IDX = ((DAC_PACK_DATA_WIDTH / 2) - 1);
localparam integer WIDTH_HALF = (DAC_PACK_DATA_WIDTH / 2);
wire signed [(IQ_DATA_WIDTH-1):0] i0;
wire signed [(IQ_DATA_WIDTH-1):0] q0;
wire signed [(IQ_DATA_WIDTH-1):0] i1;
wire signed [(IQ_DATA_WIDTH-1):0] q1;
wire signed [(IQ_DATA_WIDTH-1):0] i_merged;
wire signed [(IQ_DATA_WIDTH-1):0] q_merged;
assign i0 = data_in[(1*IQ_DATA_WIDTH-1):(0*IQ_DATA_WIDTH)];
assign q0 = data_in[(2*IQ_DATA_WIDTH-1):(1*IQ_DATA_WIDTH)];
assign i1 = data_in[(3*IQ_DATA_WIDTH-1):(2*IQ_DATA_WIDTH)];
assign q1 = data_in[(4*IQ_DATA_WIDTH-1):(3*IQ_DATA_WIDTH)];
assign i_merged = i0 + i1;
assign q_merged = q0 + q1;
always @(ant_flag, q_merged, i_merged, data_in) begin
case (ant_flag)
2'b00: begin
data_out[MSB_HALF_IDX:0] = {q_merged, i_merged};
data_out[MSB_IDX:WIDTH_HALF] = {q_merged, i_merged};
end
2'b01: begin
data_out[MSB_HALF_IDX:0] = data_in[MSB_HALF_IDX:0];
data_out[MSB_IDX:WIDTH_HALF] = data_in[MSB_IDX:WIDTH_HALF];
end
2'b10: begin
data_out[MSB_HALF_IDX:0] = data_in[MSB_IDX:WIDTH_HALF];
data_out[MSB_IDX:WIDTH_HALF] = data_in[MSB_HALF_IDX:0];
end
2'b11: begin
data_out[MSB_HALF_IDX:0] = data_in[MSB_HALF_IDX:0];
data_out[MSB_IDX:WIDTH_HALF] = data_in[MSB_IDX:WIDTH_HALF];
end
default: begin
data_out[MSB_HALF_IDX:0] = data_in[MSB_HALF_IDX:0];
data_out[MSB_IDX:WIDTH_HALF] = data_in[MSB_IDX:WIDTH_HALF];
end
endcase
end
endmodule
| 6.539945 |
module tx_intf_pl_to_m_axis #(
parameter integer C_M00_AXIS_TDATA_WIDTH = 64
) (
// to m_axis and PS
output wire start_1trans_to_m_axis,
output wire [(C_M00_AXIS_TDATA_WIDTH-1) : 0] data_to_m_axis,
output wire data_ready_to_m_axis,
input wire fulln_from_m_axis,
// start m_axis trans mode
input wire [1:0] start_1trans_mode,
input wire start_1trans_ext_trigger,
input wire src_sel,
// from wifi rx
input wire tx_start_from_acc,
input wire tx_end_from_acc,
input wire [(C_M00_AXIS_TDATA_WIDTH-1) : 0] data_loopback,
input wire data_loopback_valid
);
assign start_1trans_to_m_axis = start_1trans_to_m_axis_reg;
reg start_1trans_to_m_axis_reg;
always @(start_1trans_mode, tx_start_from_acc, tx_end_from_acc, start_1trans_ext_trigger) begin
case (start_1trans_mode)
2'b00: begin
start_1trans_to_m_axis_reg = tx_end_from_acc;
end
2'b01: begin
start_1trans_to_m_axis_reg = tx_start_from_acc;
end
2'b10: begin
start_1trans_to_m_axis_reg = start_1trans_ext_trigger;
end
2'b11: begin
start_1trans_to_m_axis_reg = start_1trans_ext_trigger;
end
default: begin
start_1trans_to_m_axis_reg = start_1trans_ext_trigger;
end
endcase
end
assign data_to_m_axis = (src_sel == 1'b0) ? data_loopback : data_loopback;
assign data_ready_to_m_axis = (src_sel == 1'b0) ? data_loopback_valid : data_loopback_valid;
endmodule
| 6.968967 |
module tx_lock (
input wire pclk,
input wire rst,
input wire [7:0] data_in,
output reg tx_start,
output reg [7:0] data_out
);
localparam IDLE = 2'b00;
localparam START = 2'b01;
localparam LOCKED = 2'b10;
localparam COUNTER_LIMIT = 28700;
reg [7:0] temp_data;
reg [1:0] state, next_state;
reg [14:0] counter, next_counter;
always @(posedge pclk) begin
if (rst) begin
state <= IDLE;
counter <= 15'b0;
data_out <= 8'b0;
end else begin
state <= next_state;
counter <= next_counter;
data_out <= temp_data;
end
end
always @(state or counter) begin
case (state)
IDLE: begin
next_state = START;
end
START: begin
next_state = LOCKED;
end
LOCKED: begin
if (counter > COUNTER_LIMIT) begin
next_state = IDLE;
end else begin
next_state = LOCKED;
end
end
default: begin
next_state = IDLE;
end
endcase
end
always @* begin
next_counter = counter;
temp_data = data_out;
case (state)
IDLE: begin
tx_start = 1'b0;
next_counter = 15'b0;
end
START: begin
tx_start = 1'b1;
temp_data = data_in;
next_counter = 15'b0;
end
LOCKED: begin
tx_start = 1'b0;
next_counter = counter + 1;
end
default: begin
tx_start = 1'b0;
end
endcase
end
endmodule
| 8.086284 |
module tx_logic (
item_in,
read,
empty,
table_addr,
table_data,
item_out,
n_ena,
n_busy,
s_ena,
s_busy,
e_ena,
e_busy,
w_ena,
w_busy,
l_ena,
l_busy
);
input empty, n_busy, s_busy, e_busy, w_busy, l_busy;
output read, s_ena, n_ena, e_ena, w_ena, l_ena;
input [`PAYLOAD_SIZE+`ADDR_SZ-1:0] item_in;
output [`PAYLOAD_SIZE+`ADDR_SZ-1:0] item_out;
output [`ADDR_SZ-1:0] table_addr;
input [`BITS_DIR-1:0] table_data;
assign table_addr = item_in[`ADDR_SZ-1:0];
assign item_out = item_in;
assign n_ena = !empty & (table_data == `NORTH) & !n_busy;
assign s_ena = !empty & (table_data == `SOUTH) & !s_busy;
assign e_ena = !empty & (table_data == `EAST) & !e_busy;
assign w_ena = !empty & (table_data == `WEST) & !w_busy;
assign l_ena = !empty & (table_data == `LOCAL) & !l_busy;
assign read = n_ena | s_ena | e_ena | w_ena | l_ena;
endmodule
| 6.742217 |
module TX_MAC_TB ();
reg SYS_CLK;
reg SYS_RST;
reg TX_START;
wire TX_BUSY;
wire [7:0] GMII_TXD;
wire GMII_TX_EN;
reg [7:0] CONTROL_IN;
TX_MAC inst_TX_MAC (
.TX_CLK(SYS_CLK),
.SYS_RST(SYS_RST),
.TX_START(TX_START),
.TX_BUSY(TX_BUSY),
.GMII_TXD(GMII_TXD),
.GMII_TX_EN(GMII_TX_EN),
.CONTROL_IN(CONTROL_IN)
);
initial begin
SYS_CLK = 1'b0;
forever #4 SYS_CLK = ~SYS_CLK;
end
initial begin
$dumpfile("TX_MAC.vcd");
$dumpvars(0, TX_MAC_TB);
end
initial begin
SYS_RST = 1'b1;
TX_START = 1'b0;
CONTROL_IN = 8'd00;
#1000 SYS_RST = 1'b0;
wait (TX_BUSY == 1'b0);
#4 TX_START = 1'b1;
#12 TX_START = 1'b0;
wait (TX_BUSY == 1'b1);
$display("TX MAC Started");
CONTROL_IN = 8'd60;
wait (TX_BUSY == 1'b0);
$display("TX MAC Operation Finished!");
#100 $finish;
end
endmodule
| 7.725735 |
module Tx_modifier (
Tx_tick_retreiver,
wen_retreiver,
Tx_tick_Tx,
wen_Tx,
end_address,
address
);
input wen_retreiver;
input Tx_tick_Tx;
input [17:0] address;
input [17:0] end_address;
output wen_Tx;
output Tx_tick_retreiver;
reg mux_out = 0;
//hijack transmit signals when needed
two_way_mux for_wen (
.data0(wen_retreiver),
.data1(0),
.sel(mux_out),
.result(wen_Tx)
);
two_way_mux for_tx_tick (
.data0(Tx_tick_Tx),
.data1(1),
.sel(mux_out),
.result(Tx_tick_retreiver)
);
always @(address) begin
if ((address[17:9] <= end_address[17:9]) & (address[8:0] <= end_address[8:0]))
mux_out <= 0; //if the address is in range maintain normal transmition
else mux_out <= 1; //if address is out of range hijack the 2 wires connecting Tx and retreiver
end
endmodule
| 7.054779 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_module(
CLK,
RST_n,
Tx_En_Sig,
Tx_Data,
Tx_Done_Sig,
Tx_Pin_Out
);
input CLK;
input RST_n;
input Tx_En_Sig;
input [7:0]Tx_Data;
output Tx_Done_Sig;
output Tx_Pin_Out;
wire BPS_CLK;
tx_bps_module U1(
.CLK(CLK),
.RST_n(RST_n),
.Count_Sig(Tx_En_Sig),
.BPS_CLK(BPS_CLK)
);
tx_control_module U2(
.CLK(CLK),
.RST_n(RST_n),
.Tx_En_Sig(Tx_En_Sig),
.Tx_Data(Tx_Data),
.BPS_CLK(BPS_CLK),
.Tx_Done_Sig(Tx_Done_Sig),
.Tx_Pin_Out(Tx_Pin_Out)
);
endmodule
| 7.088073 |
module tx_module_2 #(
parameter BPS = 13'd434
) (
clk,
rst_n,
tx_en_sig,
tx_data,
tx_pin
);
input clk;
input rst_n;
input tx_en_sig;
input [7:0] tx_data;
output reg tx_pin;
/***********************/
/*
//每个bit所占用的clk个数
localparam BPS_50MHz_9600 = 13'd5208; *10 = 52080(16bit)
localparam BPS_50MHz_115200 = 13'd434; *10 = 4340
localparam BPS_12MHz_9600 = 13'd1250; *10 = 12500
localparam BPS_12MHz_115200 = 13'd104; *10 = 1040
*/
/***********************/
reg [15:0] c1; //循环操作--max为一帧数据的clk个数
reg [15:0] x; //控制每bit数据的发送
reg [ 9:0] rData; //完整的一帧数据 1bit start + 8bit data + 1bit stop
reg [ 3:0] index;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
tx_pin <= 1'b1;
c1 <= 16'd0;
x <= 16'd0;
rData <= 10'd0;
index <= 4'd0;
end else if (tx_en_sig) begin
rData <= {
1'b1, tx_data, 1'b0
}; //相当于每个clk都动作(且恒定--即不涉及什么时候开始,什么时候停止)
if(x+1 == c1) //tx_pin依赖rData,延时1个clk
begin
x <= x + BPS;
tx_pin <= rData[index];
index <= index + 1'b1;
end
if(c1 == BPS*10) //共需要BSP*10+1个clk
begin
c1 <= 16'd0;
x <= 16'd0;
index <= 4'd0;
end else c1 <= c1 + 1'b1;
end
end
endmodule
| 7.091302 |
module tx_module_3 #(
parameter BPS = 13'd434
) (
clk,
rst_n,
tx_en_sig,
tx_data,
tx_done,
tx_pin
);
input clk;
input rst_n;
input tx_en_sig;
input [7:0] tx_data;
output reg tx_done;
output reg tx_pin;
/***********************/
/*
//每个bit所占用的clk个数
localparam BPS_50MHz_9600 = 13'd5208; *10 = 52080(16bit)
localparam BPS_50MHz_115200 = 13'd434; *10 = 4340
localparam BPS_12MHz_9600 = 13'd1250; *10 = 12500
localparam BPS_12MHz_115200 = 13'd104; *10 = 1040
*/
/***********************/
reg [15:0] c1; //循环操作--max为一帧数据的clk个数
reg [15:0] x; //控制每bit数据的发送
reg [ 9:0] rData; //完整的一帧数据 1bit start + 8bit data + 1bit stop
reg [ 3:0] index;
reg [ 1:0] i;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
tx_done <= 1'b0;
tx_pin <= 1'b1;
c1 <= 16'd0;
x <= 16'd0;
rData <= 10'd0;
index <= 4'd0;
i <= 2'd0;
end else if (tx_en_sig) begin
case (i)
0: begin
rData <= {
1'b1, tx_data, 1'b0
}; //相当于每个clk都动作(且恒定--即不涉及什么时候开始,什么时候停止)
if(x+1 == c1) //tx_pin依赖rData,延时1个clk
begin
x <= x + BPS;
tx_pin <= rData[index];
index <= index + 1'b1;
end
if(c1 == BPS*10) //共需要BSP*10+1个clk
begin
c1 <= 16'd0;
x <= 16'd0;
index <= 4'd0;
i <= 1;
end else c1 <= c1 + 1'b1;
end
1: begin
tx_done <= 1'b1;
i <= 2;
end
2: begin
tx_done <= 1'b0;
i <= 0;
end
endcase
end
end
endmodule
| 7.993215 |
module tx_module_before #(
parameter BPS_CLK = 13'd433
) (
clk,
rst_n,
tx_en_sig,
tx_data,
tx_done,
tx_pin
);
input clk;
input rst_n;
input tx_en_sig;
input [7:0] tx_data;
output tx_done;
output tx_pin;
/***********************/
/*
parameter BPS_50MHz_9600 = 13'd5207;
parameter BPS_50MHz_115200 = 13'd433;
parameter BPS_12MHz_9600 = 13'd1249;
parameter BPS_12MHz_115200 = 13'd103;
*/
wire tx_bps_clk;
tx_bps_module #(
.BPS(BPS_CLK)
) u1 (
.clk(clk),
.rst_n(rst_n),
.tx_count_sig(tx_en_sig),
.tx_bps_clk(tx_bps_clk)
);
tx_control_module u2 (
.clk(clk),
.rst_n(rst_n),
.tx_en_sig(tx_en_sig),
.tx_data(tx_data),
.tx_bps_clk(tx_bps_clk),
.tx_done(tx_done),
.tx_pin(tx_pin)
);
endmodule
| 6.723499 |
module TX_MUX #(
// RX/TX interface data width
parameter C_DATA_WIDTH = 64,
parameter TCQ = 1,
// TSTRB width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8
) (
input wire clk,
input wire sys_rst,
// AXIS Output
input wire s_axis_tx_tready,
output wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output wire s_axis_tx_tlast,
output wire s_axis_tx_tvalid,
output wire tx_src_dsc,
// AXIS Input 1
input wire s_axis_tx1_req,
output reg s_axis_tx1_ack = 1'b0,
output wire s_axis_tx1_tready,
input wire [C_DATA_WIDTH-1:0] s_axis_tx1_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tx1_tkeep,
input wire s_axis_tx1_tlast,
input wire s_axis_tx1_tvalid,
input wire tx1_src_dsc,
// AXIS Input 2
input wire s_axis_tx2_req,
output reg s_axis_tx2_ack = 1'b0,
output wire s_axis_tx2_tready,
input wire [C_DATA_WIDTH-1:0] s_axis_tx2_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tx2_tkeep,
input wire s_axis_tx2_tlast,
input wire s_axis_tx2_tvalid,
input wire tx2_src_dsc
);
always @(posedge clk) begin
if (sys_rst) begin
s_axis_tx1_ack <= 1'b0;
s_axis_tx2_ack <= 1'b0;
end else begin
case ({
s_axis_tx2_ack, s_axis_tx1_ack
})
2'b00: begin
if (s_axis_tx1_req) s_axis_tx1_ack <= 1'b1;
else if (s_axis_tx2_req) s_axis_tx2_ack <= 1'b1;
else begin
s_axis_tx1_ack <= 1'b0;
s_axis_tx2_ack <= 1'b0;
end
end
2'b01: begin
if (~s_axis_tx1_req) begin
s_axis_tx1_ack <= 1'b0;
if (s_axis_tx2_req) s_axis_tx2_ack <= 1'b1;
end
end
2'b10: begin
if (~s_axis_tx2_req) begin
s_axis_tx2_ack <= 1'b0;
if (s_axis_tx1_req) s_axis_tx1_ack <= 1'b1;
end
end
2'b11: begin
end
endcase
end
end
assign s_axis_tx1_tready = s_axis_tx_tready & s_axis_tx1_ack;
assign s_axis_tx2_tready = s_axis_tx_tready & s_axis_tx2_ack;
assign s_axis_tx_tdata = s_axis_tx2_ack ? s_axis_tx2_tdata : s_axis_tx1_tdata;
assign s_axis_tx_tkeep = s_axis_tx2_ack ? s_axis_tx2_tkeep : s_axis_tx1_tkeep;
assign s_axis_tx_tlast = s_axis_tx2_ack ? s_axis_tx2_tlast : s_axis_tx1_tlast;
assign s_axis_tx_tvalid = s_axis_tx2_ack ? s_axis_tx2_tvalid : s_axis_tx1_tvalid;
assign tx_src_dsc = s_axis_tx2_ack ? tx2_src_dsc : tx1_src_dsc;
endmodule
| 9.010156 |
module Tx_Out (
input CLK_I,
RST_I,
input [31:0] DAT_I,
input CYC_I,
WE_I,
STB_I,
output ACK_O,
output reg [31:0] DAT_O,
output reg CYC_O,
STB_O,
output WE_O,
input ACK_I
);
reg [31:0] Pre[0:319];
//assign {datafile[0], datafile[1], ...} = {16'b0, 16'b0, ...};
initial $readmemh("E:/neelam/Text_File/Pre.txt", Pre);
reg [31:0] idat;
reg ival;
wire out_halt, ena;
reg [8:0] pre_cnt;
reg pre_ena;
reg dat_sym_ena;
assign out_halt = STB_O & (~ACK_I);
assign ena = CYC_I & STB_I & WE_I;
assign ACK_O = ena & (~out_halt) & (dat_sym_ena);
always @(posedge CLK_I) begin
if (RST_I) idat <= 32'd0;
else if (ACK_O) idat <= DAT_I;
end
always @(posedge CLK_I) begin
if (RST_I) ival <= 1'b0;
else if (ena) ival <= 1'b1;
else ival <= 1'b0;
end
reg icyc;
always @(posedge CLK_I) begin
if (RST_I) icyc <= 1'b0;
else icyc <= CYC_I;
end
always @(posedge CLK_I) begin
if (RST_I) CYC_O <= icyc;
else CYC_O <= icyc;
end
always @(posedge CLK_I) begin
if (RST_I) pre_cnt <= 9'd0;
else if (CYC_I & (~icyc)) pre_cnt <= 9'd0;
else if (icyc & (~out_halt) & (~(pre_cnt == 9'd320))) pre_cnt <= pre_cnt + 1'b1;
end
always @(posedge CLK_I) begin
if (RST_I) pre_ena <= 1'b0;
else if (CYC_I & (~icyc)) pre_ena <= 1'b1;
else if (CYC_O & (pre_cnt == 9'd319)) pre_ena <= 1'b0;
end
always @(posedge CLK_I) begin
if (RST_I) dat_sym_ena <= 1'b0;
else if (CYC_I & (~icyc)) dat_sym_ena <= 1'b0;
else if (CYC_O & (pre_cnt == 9'd318)) dat_sym_ena <= 1'b1;
else if (~CYC_O) dat_sym_ena <= 1'b0;
end
always @(posedge CLK_I) begin
if (RST_I) begin
STB_O <= 1'b0;
DAT_O <= 32'b0;
end else if (pre_ena & (~out_halt)) begin
DAT_O <= Pre[pre_cnt];
STB_O <= 1'b1;
end else if (ival & (~out_halt)) begin
DAT_O <= idat;
STB_O <= 1'b1;
end else if (~ival) begin
STB_O <= 1'b0;
end
end
assign WE_O = STB_O;
endmodule
| 7.562738 |
module Tx_outputsel (
input [1:0] STM_ctrl_outputsel
, input Shift_data_bit
, input Parity_data
, output reg outputsel_data_bit
);
parameter Parity = 3;
parameter STOP = 0;
parameter DATA = 2;
parameter START = 1;
always @(*) begin
case (STM_ctrl_outputsel)
STOP: begin
outputsel_data_bit = 1;
end
START: begin
outputsel_data_bit = 0;
end
DATA: begin
outputsel_data_bit = Shift_data_bit;
end
Parity: begin
outputsel_data_bit = Parity_data;
end
endcase
end // always
endmodule
| 7.130672 |
module tx_packer ( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0] usbdata,
// TX Side
input reset,
input txclk,
output reg [31:0] usbdata_final,
output reg WR_final
);
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk) begin
if (bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if (WR_fx2 & ~write_count[8]) write_count <= #1 write_count + 9'd1;
else write_count <= #1 WR_fx2 ? write_count : 9'b0;
end
reg WR_fx2_fixed;
reg [15:0] usbdata_fixed;
always @(posedge usbclk) begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete;
reg [15:0] usbdata_delayed;
reg writing;
wire [31:0] usbdata_packed;
wire WR_packed;
always @(posedge usbclk) begin
if (bus_reset) begin
word_complete <= 0;
writing <= 0;
end else if (WR_fx2_fixed) begin
writing <= 1;
if (word_complete) word_complete <= 0;
else begin
usbdata_delayed <= usbdata_fixed;
word_complete <= 1;
end
end else writing <= 0;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed};
assign WR_packed = word_complete & writing;
/* Make sure data are sync with usbclk */
reg [31:0] usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk) begin
if (WR_packed) usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [31:0] usbdata_tx;
reg WR_tx;
reg WR_1;
reg WR_2;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset) WR_1 <= 0;
else WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset) WR_2 <= 0;
else WR_2 <= WR_1;
always @(posedge txclk) begin
if (reset) WR_tx <= 0;
else WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk) begin
if (reset) WR_final <= 0;
else begin
WR_final <= WR_tx;
if (WR_tx) usbdata_final <= usbdata_tx;
end
end
endmodule
| 6.914362 |
module tx_packet_ctrl_fifo (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
overflow,
prog_full
);
input [63 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [63 : 0] dout;
output empty;
output full;
output overflow;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V4_4 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(64),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex5"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(1),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(13),
.C_PROG_FULL_THRESH_NEGATE_VAL(12),
.C_PROG_FULL_TYPE(1),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.OVERFLOW(overflow),
.PROG_FULL(prog_full),
.CLK(0),
.INT_CLK(0),
.BACKUP(0),
.BACKUP_MARKER(0),
.PROG_EMPTY_THRESH(0),
.PROG_EMPTY_THRESH_ASSERT(0),
.PROG_EMPTY_THRESH_NEGATE(0),
.PROG_FULL_THRESH(0),
.PROG_FULL_THRESH_ASSERT(0),
.PROG_FULL_THRESH_NEGATE(0),
.RD_RST(0),
.SRST(0),
.WR_RST(0),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.PROG_EMPTY(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 6.681531 |
module tx_packet_fifo (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
overflow,
prog_full
);
input [63 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [63 : 0] dout;
output empty;
output full;
output overflow;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V4_4 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(64),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex5"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(1),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1013),
.C_PROG_FULL_THRESH_NEGATE_VAL(1012),
.C_PROG_FULL_TYPE(1),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.OVERFLOW(overflow),
.PROG_FULL(prog_full),
.CLK(0),
.INT_CLK(0),
.BACKUP(0),
.BACKUP_MARKER(0),
.PROG_EMPTY_THRESH(0),
.PROG_EMPTY_THRESH_ASSERT(0),
.PROG_EMPTY_THRESH_NEGATE(0),
.PROG_FULL_THRESH(0),
.PROG_FULL_THRESH_ASSERT(0),
.PROG_FULL_THRESH_NEGATE(0),
.RD_RST(0),
.SRST(0),
.WR_RST(0),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.PROG_EMPTY(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 6.704782 |
module tx_parity_gen (
tx_data_in,
load,
parity_bit
);
input [7:0] tx_data_in;
input load;
output reg parity_bit;
always @(*)
if (load == 0) parity_bit = 1'b0;
else parity_bit = ^(tx_data_in);
endmodule
| 6.510215 |
module tx_pkt_fifo_8192x256 (
reset_,
wrclk,
wren,
datain,
wrfull,
wrusedw,
rdclk,
rden,
dataout,
rdempty,
rdusedw
);
parameter WIDTH = 256, DEPTH = 1024, PTR = 10;
input wire reset_;
input wire wrclk; // Clk for writing data
input wire wren; // request to write
input wire [WIDTH-1 : 0] datain; // Data coming in
output wire wrfull; // indicates fifo is full or not (To avoid overiding)
output wire [PTR -1:0] wrusedw; // number of slots currently in use for writing
input wire rdclk; // Clk for read data
input wire rden; // Request to read from FIFO
output wire [WIDTH-1 : 0] dataout; // Data coming out
output wire rdempty; // indicates fifo is empty or not (to avoid underflow)
output wire [PTR -1 : 0] rdusedw; // number of slots currently in use for reading
asynch_fifo #(
.WIDTH(WIDTH),
.DEPTH(DEPTH),
.PTR (PTR)
) asynch_1024x256 (
.reset_(reset_),
.wrclk(wrclk), // Clk to write data
.wren(wren), // write enable
.datain(datain), // write data
.wrfull(wrfull), // indicates fifo is full or not (To avoid overiding)
.wrempty (), // indicates fifo is empty or not (to avoid underflow)
.wrusedw (wrusedw), // wrusedw -number of locations filled in fifo
.rdclk (rdclk), // i-1, Clk to read data
.rden (rden), // i-1, read enable of data FIFO
.dataout(dataout), // Dataout of data FIFO
.rdfull (), // indicates fifo is full or not (To avoid overiding) (Not used)
.rdempty(rdempty), // indicates fifo is empty or not (to avoid underflow)
.rdusedw(rdusedw), // rdusedw -number of locations filled in fifo (not used )
.dbg()
);
endmodule
| 7.752925 |
module tx_port_buffer_32 #(
parameter C_FIFO_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2 ** clog2(C_FIFO_DEPTH)) + 1)
) (
input RST,
input CLK,
input [ C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data FIFO is full
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "functions.vh"
reg rFifoRdEn = 0, _rFifoRdEn = 0;
reg [C_FIFO_DATA_WIDTH-1:0]
rFifoData = {C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData = {C_FIFO_DATA_WIDTH{1'd0}};
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rFifoData;
// Buffer the input signals that come from outside the tx_port.
always @(posedge CLK) begin
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
end
always @(*) begin
_rFifoRdEn = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(
.C_WIDTH(C_FIFO_DATA_WIDTH),
.C_DEPTH(C_FIFO_DEPTH),
.C_PROVIDE_COUNT(1)
) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Buffer data from the FIFO.
always @(posedge CLK) begin
rFifoData <= #1 _rFifoData;
end
always @(*) begin
_rFifoData = wFifoData;
end
endmodule
| 8.219744 |
module accepts transmitter data from the GMII style
// interface from the attached client MAC. At 1 Gbps, this
// GMII transmitter data will be valid on evey clock cycle
// of the 125MHz reference clock; at 100Mbps, this data
// will be repeated for a ten clock period duration of the
// 125MHz reference clock; at 10Mbps, this data will be
// repeated for a hundred clock period duration of the
// 125MHz reference clock.
//
// This module will sample the input transmitter GMII data
// synchronously to the 125MHz reference clock. This
// sampled data can then be connected direcly to the input
// GMII- style interface of the Ethernet 1000BASE-X PCS/PMA
// or SGMII LogiCORE.
`timescale 1 ps/1 ps
module tx_rate_adapt
(
input reset, // Synchronous reset.
input clk125m, // Reference 125MHz transmitter clock.
input sgmii_clk_en, // Clock enable pulse for the transmitter logic
input [7:0] gmii_txd_in, // Transmit data from client MAC.
input gmii_tx_en_in, // Transmit data valid signal from client MAC.
input gmii_tx_er_in, // Transmit error signal from client MAC.
output reg [7:0] gmii_txd_out, // Transmit data from client MAC.
output reg gmii_tx_en_out, // Transmit data valid signal from client MAC.
output reg gmii_tx_er_out // Transmit error signal from client MAC.
);
// At 1Gbps speeds, sgmii_clk_en is permantly tied to logic 1
// and the input data will be sampled on every clock cycle. At 10Mbs
// and 100Mbps speeds, sgmii_clk_en will be at logic 1 only only one clock
// cycle in ten, or one clock cycle in a hundred, respectively.
// The sampled output GMII transmitter data is sent directly into the
// Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE synchronously to the
// 125MHz reference clock.
always @(posedge clk125m)
begin
if (reset == 1'b1) begin
gmii_txd_out <= 8'b0;
gmii_tx_en_out <= 1'b0;
gmii_tx_er_out <= 1'b0;
end
else if (sgmii_clk_en == 1'b1) begin
gmii_txd_out <= gmii_txd_in;
gmii_tx_en_out <= gmii_tx_en_in;
gmii_tx_er_out <= gmii_tx_er_in;
end
end
endmodule
| 8.196517 |
module tx_rd_addr_synch (
input clk_out,
input reset_n_clk_out,
input clk_in,
input reset_n_clk_in,
input [9:0] commited_rd_addr_in,
output reg [9:0] commited_rd_addr_out
);
// localparam
localparam s0 = 8'b00000000;
localparam s1 = 8'b00000001;
localparam s2 = 8'b00000010;
localparam s3 = 8'b00000100;
localparam s4 = 8'b00001000;
localparam s5 = 8'b00010000;
localparam s6 = 8'b00100000;
localparam s7 = 8'b01000000;
localparam s8 = 8'b10000000;
//-------------------------------------------------------
// Local a
//-------------------------------------------------------
reg [7:0] fsm_a;
reg [9:0] bus_in_last;
reg synch;
reg [9:0] cross;
//-------------------------------------------------------
// Local b
//-------------------------------------------------------
reg synch_reg0;
reg synch_reg1;
reg [9:0] cross_reg0;
////////////////////////////////////////////////
// a
////////////////////////////////////////////////
always @( posedge clk_in or negedge reset_n_clk_in ) begin
if (!reset_n_clk_in ) begin // reset
bus_in_last <= 'b0;
synch <= 1'b0;
fsm_a <= s0;
end
else begin // not reset
case (fsm_a)
s0 : begin
if (bus_in_last != commited_rd_addr_in) begin
cross <= commited_rd_addr_in;
fsm_a <= s1;
end
end
s1 : begin
bus_in_last <= cross;
synch <= 1'b1;
fsm_a <= s2;
end
s2 : begin
synch <= 1'b0;
fsm_a <= s3;
end
s3 : fsm_a <= s4;
s4 : fsm_a <= s5;
s5 : fsm_a <= s6;
s6 : fsm_a <= s0;
default : begin
fsm_a <= s0;
end
endcase
end // not reset
end //always
////////////////////////////////////////////////
// b
////////////////////////////////////////////////
always @( posedge clk_out or negedge reset_n_clk_out ) begin
if (!reset_n_clk_out ) begin // reset
commited_rd_addr_out <= 'b0;
synch_reg0 <= 1'b0;
synch_reg1 <= 1'b0;
end
else begin // not reset
cross_reg0 <= cross;
synch_reg0 <= synch;
synch_reg1 <= synch_reg0;
if (synch_reg1) begin
commited_rd_addr_out <= cross_reg0;
end
end // not reset
end //always
endmodule
| 8.13359 |
module tx_responder #(
parameter BASE = 0
) (
input clk,
input reset,
input clear,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
input ack_or_error,
input packet_consumed,
input [11:0] seqnum,
input [63:0] error_code,
input [31:0] sid,
input [63:0] vita_time,
output [63:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
reg [11:0] seqnum_int;
always @(posedge clk) if (packet_consumed) seqnum_int <= seqnum;
wire trigger_fc, trigger_ctxt;
wire [95:0] msg_data = {
sid[15:0], sid[31:16], (ack_or_error ? error_code : {32'h0, 20'h0, seqnum_int})
};
wire [95:0] ctxt_data;
reg [11:0] reply_seqnum;
wire done;
always @(posedge clk)
if (reset | clear) reply_seqnum <= 12'd0;
else if (done) reply_seqnum <= reply_seqnum + 12'd1;
trigger_context_pkt #(
.BASE(BASE)
) trig (
.clk(clk),
.reset(reset),
.clear(clear),
.set_stb(set_stb),
.set_addr(set_addr),
.set_data(set_data),
.packet_consumed(packet_consumed),
.trigger(trigger_fc)
);
axi_fifo_short #(
.WIDTH(64 + 32)
) ack_queue (
.clk(clk),
.reset(reset),
.clear(clear),
.i_tdata(msg_data),
.i_tvalid(ack_or_error | trigger_fc),
.i_tready(),
.o_tdata(ctxt_data),
.o_tvalid(trigger_ctxt),
.o_tready(done),
.space(),
.occupied()
);
context_packet_gen ack_err_gen (
.clk(clk),
.reset(reset),
.clear(clear),
.trigger(trigger_ctxt),
.seqnum(reply_seqnum),
.sid(ctxt_data[95:64]),
.body(ctxt_data[63:0]),
.vita_time(vita_time),
.done(done),
.o_tdata(o_tdata),
.o_tlast(o_tlast),
.o_tvalid(o_tvalid),
.o_tready(o_tready)
);
endmodule
| 7.880273 |
module tx_rx_controller (
input clk,
input reset,
input [7:0] data_to_tx,
input rx_done_tick,
input [7:0] data_received, // tie to dout port of rx
output reg tx_start, // tie to tx_start port of tx
output reg [7:0] frame_out, // tie to din port of tx
output reg [7:0] data_received_out // Received Data
);
reg [7:0] data_to_tx_last_St;
reg send_tx_start;
always @(posedge clk, posedge reset) begin
if (reset) begin
data_to_tx_last_St <= 8'd0;
frame_out <= 8'd0;
tx_start <= 1'b0;
end else begin
if ((data_to_tx != data_to_tx_last_St)) begin
frame_out <= data_to_tx;
tx_start <= 1'b1;
data_to_tx_last_St <= data_to_tx;
end else begin
tx_start <= 1'b0;
frame_out <= frame_out;
data_to_tx_last_St <= data_to_tx;
end
end
end
always @(posedge clk) begin
if (rx_done_tick) data_received_out = data_received;
else data_received_out = data_received_out; //data_received_out
end
endmodule
| 6.753018 |
module tx_selio_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ports here
output wire txclk,
output wire txclk_div,
output wire [39:0] dout,
output wire reset,
// input wire [9:0] ein,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready,
input wire [23:0] din1,
input wire [15:0] din2,
input wire [31:0] din3
);
// Instantiation of Axi Bus Interface S00_AXI
tx_selio_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) tx_selio_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready),
.txclk(txclk),
.txclk_div(txclk_div),
.dout(dout),
.ein(ein),
.din1(din1),
.din2(din2),
.din3(din3)
);
// Add user logic here
assign reset = ~s00_axi_aresetn;
// User logic ends
endmodule
| 6.575733 |
module UART_Protocal_Tx_stm (
input glb_rstn
, input glb_clk
, input CFG_PROT_ctrl_Txen
, input CFG_PROT_ctrl_empty
, input USR_PROT_ctrl_cts
, input CORE_CFG_r_en
, output reg PROT_CORE_ctrl_Txen
, output reg PROT_CORE_ctrl_empty
, output reg [1:0] PROT_CFG_ctrl_Txsel
, output reg PROT_CFG_ctrl_tx_r_en
, output reg PROT_CFG_ctrl_tx_rst
);
reg [1:0] state;
reg [1:0] next_state;
parameter INIT = 0;
parameter SEND_SLAVE_ADDR = 1;
parameter SEND_DATA = 2;
parameter SEND_STOP_FRAME = 3;
always @(negedge glb_rstn or posedge glb_clk) begin
if (!glb_rstn) state <= INIT;
else begin
state <= next_state;
end
end
always @(*) begin
case (state)
INIT: begin
next_state = (CFG_PROT_ctrl_Txen) ? SEND_SLAVE_ADDR : INIT;
end
SEND_SLAVE_ADDR: begin
next_state = SEND_DATA;
end
SEND_DATA: begin
next_state = (CFG_PROT_ctrl_empty) ? SEND_STOP_FRAME : SEND_DATA;
end
SEND_STOP_FRAME: begin
next_state = (CORE_CFG_r_en) ? INIT : SEND_STOP_FRAME;
end
endcase
end // always
always @(*) begin
case (state)
INIT: begin
PROT_CORE_ctrl_Txen = CFG_PROT_ctrl_Txen;
PROT_CFG_ctrl_Txsel = 0;
PROT_CFG_ctrl_tx_r_en = 0;
PROT_CFG_ctrl_tx_rst = 0;
PROT_CORE_ctrl_empty = 0;
end
SEND_SLAVE_ADDR: begin
PROT_CORE_ctrl_Txen = 1;
PROT_CFG_ctrl_Txsel = 0;
PROT_CFG_ctrl_tx_r_en = 0;
PROT_CFG_ctrl_tx_rst = 0;
PROT_CORE_ctrl_empty = 0;
end
SEND_DATA: begin
PROT_CORE_ctrl_Txen = 1;
PROT_CFG_ctrl_Txsel = 1;
PROT_CFG_ctrl_tx_r_en = CORE_CFG_r_en & !CFG_PROT_ctrl_empty;
PROT_CFG_ctrl_tx_rst = 0;
PROT_CORE_ctrl_empty = 0;
end
SEND_STOP_FRAME: begin
PROT_CORE_ctrl_Txen = 1;
PROT_CFG_ctrl_Txsel = 2;
PROT_CFG_ctrl_tx_r_en = 0;
PROT_CFG_ctrl_tx_rst = CORE_CFG_r_en;
PROT_CORE_ctrl_empty = CORE_CFG_r_en;
end
endcase
end // always
endmodule
| 6.877049 |
module TX_sequence (
input clock,
input reset,
input PB, //PushButton
output reg send16, // Si esta alto, se deben transmitir 16 bits (2 bytes)
input busy, // Si esta alto, la UART se encuentra transmitiendo un dato
output [1:0] stateID // Indica en que estado de la secuencia esta para mostrarlo en los LEDs
);
reg [1:0] next_state, state;
//state encoding
localparam IDLE = 2'd0; // Esperando dato
localparam TX_OPERAND01 = 2'd1; // Transmitiendo el primer operando
localparam TX_OPERAND02 = 2'd2; // Transmitiendo el segundo operando
localparam TX_ALU_CTRL = 2'd3; // Transmitiendo la senal de control para la operacion
assign stateID = state;
// combo logic of FSM
always @(*) begin
//default assignments
next_state = state;
send16 = 1'b1;
case (state)
IDLE: begin
if (PB & ~busy) begin
next_state = TX_OPERAND01;
end
end
TX_OPERAND01: begin
if (PB & ~busy) begin
next_state = TX_OPERAND02;
end
end
TX_OPERAND02: begin
if (PB & ~busy) begin
next_state = TX_ALU_CTRL;
end
end
TX_ALU_CTRL: begin
send16 = 1'b0;
if (~busy) begin
next_state = IDLE;
end
end
endcase
end
//when clock ticks, update the state
always @(posedge clock) begin
if (reset) state <= IDLE;
else state <= next_state;
end
endmodule
| 7.864703 |
module.
// Output a character using RS232 protocol (8N1) and 115200 baud
// Ken Shirriff http://righto.com
module tx_serial(
input clk,
input rst,
input [7:0] char, // Character to output
input send, // High = request a send
output reg out, // Output pin
output busy // High while character is being output
);
//localparam DIVISOR = 13'd868;
localparam DIVISOR = 13'd868; // 108 for 921600 bauds on 100MHz
// Divide 50 MHz by 434 to get approximately 115200 baud (divide by 5208 to get 9600 baud)
//localparam DIVISOR = 13'd434;
//localparam DIVISOR = 13'd217;
//localparam DIVISOR = 13'd108;
reg [12:0] counter;
localparam SPACE = 1'b0, MARK = 1'b1;
reg [3:0] state; // Bit counter
localparam IDLE = 4'd0, START = 4'd1, BIT0 = 4'd2, BIT1 = 4'd3,
BIT2 = 4'd4, BIT3 = 4'd5, BIT4 = 4'd6, BIT5 = 4'd7, BIT6 = 4'd8,
BIT7 = 4'd9, STOP = 4'd10;
// Busy while not in IDLE state
assign busy = (state == IDLE) ? 1'b0 : 1'b1;
reg [7:0] char1;
always @(posedge clk) begin
if (rst) begin
state <= IDLE;
counter <= 0;
end
else if (state == IDLE) begin
// Wait for a send request
if (send == 1) begin
state <= START;
counter <= 0;
char1 <= char;
end
end
else begin
if (counter < DIVISOR - 1) begin
// Keep counting to the end of the bit time
counter <= counter + 1'b1;
end
else begin
// End of bit time. Reset counter and move to next state.
counter <= 0;
if (state != STOP) begin
state <= state + 1'b1;
end
else begin
state <= IDLE;
end
end
end
end
// Output the appropriate level depending on state
always @(*) begin
case (state)
IDLE: out = MARK; // Stop bit is also IDLE
START: out = SPACE;
BIT0: out = char1[0];
BIT1: out = char1[1];
BIT2: out = char1[2];
BIT3: out = char1[3];
BIT4: out = char1[4];
BIT5: out = char1[5];
BIT6: out = char1[6];
BIT7: out = char1[7];
default: out = MARK;
endcase
end
initial begin
state <= IDLE;
counter <= 0;
end
endmodule
| 7.826234 |
module tx_shiftr_reg_n #(
parameter BUS_WIDTH = 8
) (
Clk,
Reset,
ALoad,
DataIn,
SO,
Empty
);
input Clk, Reset, ALoad; // Clock, Reset, and Asynchronous Load inputs
input [BUS_WIDTH-1:0] DataIn; // Data to parallel load
output reg SO = 1'b1; // Serial Out
output reg Empty; // Shift Register Empty Flag
reg [BUS_WIDTH+1:0] tmp; // START Bit + Data + STOP Bit
reg [3:0] counter; // Maximum bits per frame = 10
always @(posedge Clk, posedge ALoad, negedge Reset) begin
if (!Reset) // Active-Low reset
begin
tmp <= 0; // Clear the shift register
SO <= 1'b1; // Clear the output
counter <= (BUS_WIDTH + 4'd1);
Empty <= 1'b1; // Set Empty flag to 1
end else begin
if (ALoad) // Load if Active-High Asynchronous Load asserted and Shift Register is empty
begin
if (Empty) begin
// {STOP bit, MSB -> LSB, START bit}
tmp <= {1'b1, DataIn[7:0], 1'b0}; // Load next set of data into shift register
counter <= (BUS_WIDTH + 4'd1); // Load the counter
Empty <= 1'b0; // Set Empty flag to 0
end
end
else if (counter == 0) // STOP bit has been transmitted if counter = 0
begin
SO = tmp[0]; // Update output to Idle
Empty = 1'b1; // Set Empty flag to 1
end else // Shift right 1 if ALoad is not asserted
begin
SO = tmp[0]; // Output is the end bit of the shift register
tmp = {1'b0, tmp[BUS_WIDTH+1:1]}; // Shift contents of the shift register one to the right
counter = counter - 4'd1; // Decrement the counter
end
end
end
endmodule
| 6.932792 |
module tx_shift_reg (
Clk,
Reset,
DataIn,
TxOut,
Empty
); // 单字节发送，发送下一个字节需要复位此模块
input Clk, Reset; // 时钟、复位
input [7:0] DataIn; // 待发送数据
output reg TxOut; // 串行输出
output reg Empty; // 移位寄存器空标志
reg [7:0] tmp;
reg [3:0] counter; // 计数变量
always @(posedge Clk, negedge Reset) begin
if (!Reset) begin
{tmp, counter, Empty} <= 0; // 复位寄存器
TxOut <= 1'b1;
end else begin
if (counter == 0) begin
tmp <= DataIn[7:0];
TxOut <= 1'b0;
counter <= counter + 1'b1;
end else if (counter < 10) begin
TxOut <= tmp[0];
tmp <= {1'b1, tmp[7:1]};
counter <= counter + 1'b1;
end else begin
Empty <= 1'b1;
end
end
end
endmodule
| 7.005889 |
module tx_sim (
input eth_rstn,
input eth_clkin,
input eth_txen,
input [1:0] eth_txd
);
`include "../rtl/util.vh"
reg crc_rst;
reg crc_vld;
reg [ 7:0] crc_dat;
wire [31:0] crc_code;
wire [31:0] crc_bswap = bswap32(crc_code);
crc32 crc32_inst (
.clk (eth_clkin),
.rst (crc_rst),
.vld (crc_vld),
.data(crc_dat),
.crc (crc_code)
);
reg verbose = 1;
task set_verbose;
input verbose_;
begin
verbose = verbose_;
end
endtask
reg [31:0] test;
task recv;
output [1522 * 8 - 1 : 0] data;
output [10:0] len;
output err;
integer i, b;
reg [ 7:0] byte_buf;
reg [63:0] preamble_buffer;
begin
preamble_buffer = 0;
while (preamble_buffer != 64'hd555555555555555) begin
preamble_buffer = eth_txen ? {eth_txd, preamble_buffer[63:2]} : 0;
@(posedge eth_clkin);
#0.001;
end
if (verbose) $display("TX SOF");
crc_rst = 1;
crc_vld = 0;
i = 0;
b = 0;
while (eth_txen) begin
byte_buf = {eth_txd, byte_buf[7:2]};
b = b + 1;
if (b == 4) begin
if (i >= 4) begin
crc_vld = 1;
crc_dat = data[(i-4)*8+:8];
end
data[i*8+:8] = byte_buf;
b = 0;
if (verbose) $display("TX DATA[%d] = %h", i, byte_buf);
i = i + 1;
end
@(posedge eth_clkin);
#0.001;
crc_rst = 0;
crc_vld = 0;
end
len = i;
err = 0;
if (verbose) begin
$display("TX CRC = %h", data[(i-4)*8+:32]);
$display("TX EXPECTED CRC = %h", crc_bswap);
end
if (b != 0) begin
if (verbose) $display("TX INCOMPLETE TRANSMIT");
err = 1;
end else if (i < 68) begin
if (verbose) $display("TX FRAME TOO SHORT");
err = 1;
end else if (crc_bswap != data[(i-4)*8+:32]) begin
if (verbose) $display("TX CRC FAIL");
err = 1;
end else begin
if (verbose) $display("TX EOF");
end
end
endtask
endmodule
| 7.62948 |
module TX_SM (
input clk,
input reset,
input HOLD_REG_FULL,
input HOLD_REG_EMPTY,
input DATA_WAIT,
output reg [7:0] dataIn,
output reg TX_VALID,
output reg TX_READY
);
reg [40:0] data;
reg flag;
integer i;
reg [7:0] SYNC, PID, EOP;
initial begin
flag = 0;
dataIn = 0;
TX_VALID = 0;
TX_READY = 0;
data = 40'b0110111101101100011011000110010101101000;
SYNC = 8'b00101010;
PID = 8'b01111000;
EOP = 8'b00010000;
end
initial begin
#512 $finish;
end
initial begin
#16 TX_READY = 1;
end
always @(posedge clk) begin
if (reset) begin
TX_READY = 0;
end
if (TX_READY & (!flag)) begin
dataIn = SYNC;
#16 dataIn = PID;
#16 TX_VALID = 1;
flag = 1;
dataIn = 0;
end
if (TX_VALID) begin
if (!DATA_WAIT) begin
dataIn = data[8:0];
data = data >> 8;
#16;
if (data == 0) begin
TX_VALID = 0;
dataIn = EOP;
#16 TX_READY = 0;
flag = 0;
dataIn = 0;
end
end
end
end
endmodule
| 7.444751 |
module recieves a byte from the databus and transmit's it serially
// at the configured baud rate
//////////////////////////////////////////////////////////////////////////////////
module tx_spart(
output txd,
output reg tbr,
input clk,rst,
input iorw,
input brg_full, //goes high once every baud
input [7:0] databus,
input [1:0] ioaddr);
reg [9:0] tx_shift_reg,tx_shift_reg_next;
localparam IDLE = 1'b0;
localparam TRANSMITTING = 1'b1;
reg state, state_next;
//count to 10
reg [3:0] tx_count,tx_count_next;
always @(posedge clk) begin
if (rst == 1'b1) begin
state <= 1'b0;
tx_count <= 4'h0;
tx_shift_reg <= 10'hFFF;
end
else begin
state <= state_next;
tx_count <= tx_count_next;
tx_shift_reg <= tx_shift_reg_next;
end
end
always @(*) begin
//defaults
tx_count_next = tx_count;
tx_shift_reg_next = tx_shift_reg;
case (state)
IDLE: begin
tbr = 1'b1; //ready to transmit again
tx_count_next = 4'd0;
if (ioaddr == 2'b00 && iorw == 1'b0) begin
state_next = TRANSMITTING;
tx_shift_reg_next = {databus,2'b01};
tx_count_next = 4'h0;
end
else begin
//stay in idle state
state_next = IDLE;
end
end
TRANSMITTING: begin
tbr = 1'b0;//busy
if (tx_count == 4'd11) begin
state_next = IDLE;
end
else begin
//remain in state, not done yet.
state_next = TRANSMITTING;
end
if (brg_full == 1'b1)begin
//we've waited a full baud! send out another bit! they'll be so excited.
//1 bit shift right, shifting in 1 to MSB
tx_shift_reg_next = {1'b1,tx_shift_reg[9:1]};
tx_count_next = tx_count + 1;
end
end
endcase
end
assign txd = tx_shift_reg[0];
endmodule
| 7.124804 |
module tx_spart_parity (
output txd,
output reg tbr,
input clk,
rst,
input iorw,
input brg_full, //goes high once every baud
input [7:0] databus,
input [1:0] ioaddr
);
reg [10:0] tx_shift_reg, tx_shift_reg_next;
localparam IDLE = 1'b0;
localparam TRANSMITTING = 1'b1;
reg state, state_next;
//count to 10
reg [3:0] tx_count, tx_count_next;
always @(posedge clk) begin
if (rst == 1'b1) begin
state <= 1'b0;
tx_count <= 4'h0;
tx_shift_reg <= 11'hFFF;
end else begin
state <= state_next;
tx_count <= tx_count_next;
tx_shift_reg <= tx_shift_reg_next;
end
end
always @(*) begin
//defaults
tx_count_next = tx_count;
tx_shift_reg_next = tx_shift_reg;
case (state)
IDLE: begin
tbr = 1'b1; //ready to transmit again
tx_count_next = 4'd0;
if (ioaddr == 2'b00 && iorw == 1'b0) begin
state_next = TRANSMITTING;
// parity bit, data, start bit
tx_shift_reg_next = {^databus[7:0], databus, 2'b01};
tx_count_next = 4'h0;
end else begin
//stay in idle state
state_next = IDLE;
end
end
TRANSMITTING: begin
tbr = 1'b0; //busy
if (tx_count == 4'd12) begin
state_next = IDLE;
end else begin
//remain in state, not done yet.
state_next = TRANSMITTING;
end
if (brg_full == 1'b1) begin
//we've waited a full baud! send out another bit! they'll be so excited.
//1 bit shift right, shifting in 1 to MSB
tx_shift_reg_next = {1'b1, tx_shift_reg[10:1]};
tx_count_next = tx_count + 1;
end
end
endcase
end
assign txd = tx_shift_reg[0];
endmodule
| 8.1995 |
module tx_spart_tb ();
reg clk, rst;
reg iorw;
reg [1:0] ioaddr;
reg [7:0] databus;
brg_spart BRG (
.clk(clk),
.rst(rst),
.ioaddr(ioaddr),
.databus(databus),
.brg_en(brg_en),
.brg_full(brg_full)
);
tx_spart DUT (
.txd(txd),
.tbr(tbr),
.clk(clk),
.rst(rst),
.iorw(iorw),
.brg_full(brg_full),
.databus(databus),
.ioaddr(ioaddr)
);
initial begin
clk = 1'b1;
forever #5 clk = ~clk;
end
initial begin
rst = 1'b1;
iorw = 1'b1; // "read", so TX shouldn't do anything
ioaddr = 2'b00;
#10 rst = 1'b0;
ioaddr = 2'b10;
databus = 8'h05;
#10 ioaddr = 2'b11;
databus = 8'h00;
#10 ioaddr = 2'b00;
#200 databus = 8'h6a; // should TX ...1111| 0| 0101 0110 |111111...
iorw = 1'b0; // begin TX'ing
#10 iorw = 1'b1;
// Since we left iorw as "Write", TX should loop.
@(posedge tbr) #10 databus = 8'hf3; // 0| 1111 0011
#1000 iorw = 1'b0; // Begin TX'ing the new byte
@(posedge tbr);
@(posedge tbr);
$stop;
end
endmodule
| 6.56871 |
module Tx_specific_CC (
input clock,
input [15:0] to_port,
input udp_rx_active,
input [7:0] udp_rx_data,
output reg EER,
output reg internal_CW,
output reg key_reverse,
output reg iambic,
output reg sidetone,
output reg keyer_mode,
output reg keyer_spacing,
output reg break_in,
output reg [7:0] sidetone_level,
output reg [11:0] tone_freq,
output reg [5:0] keyer_speed,
output reg [7:0] keyer_weight,
output reg [9:0] hang,
output reg [7:0] RF_delay,
output reg Line_In,
output reg [4:0] Line_In_Gain,
output reg Mic_boost,
output reg Orion_micPTT_disable,
output reg Orion_tip_ring_select,
output reg MICBIAS_ENABLE,
output reg [4:0] Orion_atten_Tx1,
output reg [4:0] Orion_atten_Tx0,
output reg data_ready,
output HW_reset
);
parameter port = 16'd1026;
localparam IDLE = 1'd0, PROCESS = 1'd1;
reg [31:0] CC_sequence_number;
reg [10:0] byte_number;
reg [31:0] temp_Rx1_frequency;
reg [31:0] temp_Rx2_frequency;
reg [31:0] temp_Tx1_frequency;
reg state;
always @(posedge clock) begin
if (udp_rx_active && to_port == port) // look for to_port = 1026
case (state)
IDLE: begin
data_ready <= 0;
// HW_reset <= 1'b1;
byte_number <= 11'd1; // since byte 0 is received here
CC_sequence_number <= {
CC_sequence_number[31-8:0], udp_rx_data
}; //save MSB of sequence number
state <= PROCESS;
end
PROCESS: begin
case (byte_number) //save balance of sequence number
1, 2, 3: begin
CC_sequence_number <= {CC_sequence_number[31-8:0], udp_rx_data};
// HW_reset <= 1'b1;
end
5: begin
EER <= udp_rx_data[0];
internal_CW <= udp_rx_data[1];
key_reverse <= udp_rx_data[2];
iambic <= udp_rx_data[3];
sidetone <= udp_rx_data[4];
keyer_mode <= udp_rx_data[5];
keyer_spacing <= udp_rx_data[6];
break_in <= udp_rx_data[7];
end
6: sidetone_level <= udp_rx_data;
7: tone_freq[11:8] <= udp_rx_data[3:0];
8: tone_freq[7:0] <= udp_rx_data;
9: keyer_speed[5:0] <= udp_rx_data[5:0];
10: keyer_weight <= udp_rx_data;
11: hang[9:8] <= udp_rx_data[1:0];
12: hang[7:0] <= udp_rx_data;
13: RF_delay <= udp_rx_data;
50: begin
Line_In <= udp_rx_data[0];
Mic_boost <= udp_rx_data[1];
Orion_micPTT_disable <= udp_rx_data[2];
Orion_tip_ring_select <= udp_rx_data[3];
MICBIAS_ENABLE <= udp_rx_data[4];
end
51: Line_In_Gain[4:0] <= udp_rx_data[4:0];
58: begin
Orion_atten_Tx1[4:0] <= udp_rx_data[4:0];
data_ready <= 1'b1;
end
59: begin
Orion_atten_Tx0[4:0] <= udp_rx_data[4:0];
data_ready <= 1'b0;
// HW_reset <= 1'b0;
end
default:
if (byte_number > 11'd59) state <= IDLE; // change this when increasing data size
endcase
byte_number <= byte_number + 11'd1;
end
default: state <= IDLE;
endcase
else state <= IDLE;
end
// inhibit HW_reset if Ethernet data stops
assign HW_reset = (byte_number > 4 && udp_rx_active);
endmodule
| 7.118738 |
module will called by fpga_top_ft600_tx_mass.v or fpga_top_ft232h_tx_mass.v
//--------------------------------------------------------------------------------------------------------
module tx_specified_len (
input wire rstn,
input wire clk,
// AXI-stream slave
output wire i_tready,
input wire i_tvalid,
input wire [ 7:0] i_tdata,
// AXI-stream master
input wire o_tready,
output wire o_tvalid,
output wire [31:0] o_tdata,
output wire [ 3:0] o_tkeep,
output wire o_tlast
);
localparam [2:0] RX_BYTE0 = 3'd0,
RX_BYTE1 = 3'd1,
RX_BYTE2 = 3'd2,
RX_BYTE3 = 3'd3,
TX_DATA = 3'd4;
reg [ 2:0] state = RX_BYTE0;
reg [31:0] length = 0;
always @ (posedge clk or negedge rstn)
if (~rstn) begin
state <= RX_BYTE0;
length <= 0;
end else begin
case (state)
RX_BYTE0 : if (i_tvalid) begin
length[ 7: 0] <= i_tdata;
state <= RX_BYTE1;
end
RX_BYTE1 : if (i_tvalid) begin
length[15: 8] <= i_tdata;
state <= RX_BYTE2;
end
RX_BYTE2 : if (i_tvalid) begin
length[23:16] <= i_tdata;
state <= RX_BYTE3;
end
RX_BYTE3 : if (i_tvalid) begin
length[31:24] <= i_tdata;
state <= TX_DATA;
end
default : // TX_DATA :
if (o_tready) begin
if (length >= 4) begin
length <= length - 4;
end else begin
length <= 0;
state <= RX_BYTE0;
end
end
endcase
end
assign i_tready = (state != TX_DATA);
assign o_tvalid = (state == TX_DATA);
assign o_tdata = {length[7:0] - 8'd4,
length[7:0] - 8'd3,
length[7:0] - 8'd2,
length[7:0] - 8'd1 };
assign o_tkeep = (length>=4) ? 4'b1111 :
(length==3) ? 4'b0111 :
(length==2) ? 4'b0011 :
(length==1) ? 4'b0001 :
/*length==0*/ 4'b0000;
assign o_tlast = (length>=4) ? 1'b0 : 1'b1;
endmodule
| 6.957354 |
module tx_sr (
clk,
n_rst,
data_in,
shift_enable,
load_enable,
data_out
);
input [127:0] data_in;
output [31:0] data_out;
input clk, n_rst, shift_enable, load_enable;
tri clk;
tri n_rst;
tri [127:0] data_in;
tri shift_enable;
tri load_enable;
tri [31:0] data_out;
flexbyte_pts_sr pts (
.clk(clk),
.n_rst(n_rst),
.shift_enable(shift_enable),
.load_enable(load_enable),
.data_in(data_in),
.data_out(data_out)
);
endmodule
| 7.061752 |
module tx_state (
reset,
a_cnt,
code_sel,
a_send,
current_state,
next_state,
current_ifg,
current_q_det,
next_ifg,
next_q_det,
txdata_i,
txcharisk_i,
txdata_o,
txcharisk_o,
link_status_event,
link_status
);
input reset;
input [4:0] a_cnt;
input code_sel;
input [2:0] current_state;
output [2:0] next_state;
input current_ifg, current_q_det;
output next_ifg, next_q_det, a_send;
input [31:0] txdata_i;
input [3:0] txcharisk_i;
output [31:0] txdata_o;
output [3:0] txcharisk_o;
input link_status_event;
input [31:0] link_status;
wire got_tx_data = txdata_i != {4{8'h07}};
function [2:0] nstate;
input [2:0] cstate;
input ifg;
input code_sel;
input [4:0] a_cnt;
input q_det;
input got_tx_data;
input reset;
begin
nstate = `SEND_RANDOM_R;
if (reset) begin
nstate = `SEND_RANDOM_R;
end else if (got_tx_data) begin
nstate = ifg == `IFG_K || a_cnt == 5'b0 ? `SEND_K : `SEND_A;
end else begin
case (cstate)
`SEND_K: begin
nstate = `SEND_RANDOM_R;
end
`SEND_A: begin
nstate = q_det ? `SEND_Q : `SEND_RANDOM_R;
end
`SEND_Q: begin
nstate = `SEND_RANDOM_R;
end
`SEND_RANDOM_R: begin
nstate = a_cnt != 5'b0 && code_sel ? `SEND_RANDOM_R :
a_cnt == 5'b0 ? `SEND_RANDOM_A : `SEND_RANDOM_K ;
end
`SEND_RANDOM_K: begin
nstate = a_cnt == 5'b0 ? `SEND_RANDOM_A : code_sel ? `SEND_RANDOM_R : `SEND_RANDOM_K;
end
`SEND_RANDOM_A: begin
nstate = q_det ? `SEND_RANDOM_Q : code_sel ? `SEND_RANDOM_R : `SEND_RANDOM_K;
end
`SEND_RANDOM_Q: begin
nstate = code_sel ? `SEND_RANDOM_R : `SEND_RANDOM_K;
end
default: begin
nstate = nstate;
end
endcase
end
end
endfunction
function [31:0] idle_convert;
input [31:0] data;
input [3:0] isk;
begin
idle_convert = {
isk[3] && data[31:24] == `XAUI_IDLE_ ? `SYM_K_ : data[31:24],
isk[2] && data[23:16] == `XAUI_IDLE_ ? `SYM_K_ : data[23:16],
isk[1] && data[15:8] == `XAUI_IDLE_ ? `SYM_K_ : data[15:8],
isk[0] && data[7:0] == `XAUI_IDLE_ ? `SYM_K_ : data[7:0]
};
end
endfunction
assign next_state = nstate(
current_state, current_ifg, code_sel, a_cnt, current_q_det, got_tx_data, reset
);
assign next_ifg = (current_state ==`SEND_K || reset) ? `IFG_A : current_state == `SEND_A ? `IFG_K : current_ifg;
assign next_q_det = reset ? 1'b0 :
link_status_event ? 1'b1 :
current_state == `SEND_RANDOM_Q ? 1'b0 :
current_state == `SEND_Q ? 1'b0 :
current_q_det;
assign a_send = reset ? 1'b0 : txdata_o == {4{`SYM_A_}};
assign txdata_o = reset ? {4{`SYM_K_}} : got_tx_data ? idle_convert(
txdata_i, txcharisk_i
) : current_state == `SEND_RANDOM_Q || current_state == `SEND_Q ? link_status :
current_state == `SEND_RANDOM_K || current_state == `SEND_K ? {4{`SYM_K_}} : current_state ==
`SEND_RANDOM_R ? {4{`SYM_R_}} : current_state == `SEND_RANDOM_A ? {4{`SYM_A_}} : {4{`SYM_K_}};
assign txcharisk_o = reset ? {4'b1111} :
got_tx_data ? txcharisk_i :
current_state == `SEND_RANDOM_Q || current_state == `SEND_Q ? 4'b0001 :
4'b1111;
endmodule
| 7.648336 |
module tx_stats_fifo ( /*AUTOARG*/
// Outputs
txsfifo_rdata,
txsfifo_rempty,
// Inputs
clk_xgmii_tx,
reset_xgmii_tx_n,
wb_clk_i,
wb_rst_i,
txsfifo_wdata,
txsfifo_wen
);
input clk_xgmii_tx;
input reset_xgmii_tx_n;
input wb_clk_i;
input wb_rst_i;
input [13:0] txsfifo_wdata;
input txsfifo_wen;
output [13:0] txsfifo_rdata;
output txsfifo_rempty;
generic_fifo #(
.DWIDTH(14),
.AWIDTH(`TX_STAT_FIFO_AWIDTH),
.REGISTER_READ(1),
.EARLY_READ(1),
.CLOCK_CROSSING(1),
.ALMOST_EMPTY_THRESH(7),
.ALMOST_FULL_THRESH(12),
.MEM_TYPE(`MEM_AUTO_SMALL)
) fifo0 (
.wclk(clk_xgmii_tx),
.wrst_n(reset_xgmii_tx_n),
.wen(txsfifo_wen),
.wdata(txsfifo_wdata),
.wfull(),
.walmost_full(),
.rclk(wb_clk_i),
.rrst_n(~wb_rst_i),
.ren(1'b1),
.rdata(txsfifo_rdata),
.rempty(txsfifo_rempty),
.ralmost_empty()
);
endmodule
| 6.984053 |
module TX_Switch #(
parameter REG_WIDTH = 8
) (
//-----------------Input Ports-----------------
input CLK, //ClockSignal
input RESET, //Active high,syn reset
input START, //Start Process
input [REG_WIDTH-1:0] init_delay, // the initial delay from start to pulse
input [REG_WIDTH-1:0] tx_len, // the length of the transmit signal
input [REG_WIDTH-1:0] damp_len, // the length of the transmit signal
//-----------------Output Ports----------------
// Pulsing signals @ pulse freq
output [7:0] TXP,
output [7:0] TXN
);
reg [REG_WIDTH-1:0] init_delay_cnt;
reg [REG_WIDTH-1:0] tx_len_cnt;
reg [REG_WIDTH-1:0] damp_len_cnt;
reg TX_EN;
reg DAMP;
reg [4:0] State;
localparam [4:0] S0 = 5'b00001, S1 = 5'b00010, S2 = 5'b00100, S3 = 5'b01000, S4 = 5'b10000;
//
//State Machine Process
//
always @(posedge CLK, posedge RESET) begin
if (RESET) begin
//Reset Register Assignments
init_delay_cnt <= 6'b000000;
tx_len_cnt <= 4'b0000;
TX_EN <= 1'b0;
DAMP <= 1'b0;
//Reset State Variable
State <= S0;
end else begin
//State Machine operations (actions and transitions)
case (State)
S0: //State 0
begin
TX_EN <= 1'b0;
DAMP <= 1'b0;
init_delay_cnt <= {1'b1, {(REG_WIDTH - 1) {1'b0}}} - init_delay + 2;
tx_len_cnt <= {1'b1, {(REG_WIDTH - 1) {1'b0}}} - tx_len + 1;
damp_len_cnt <= {1'b1, {(REG_WIDTH - 1) {1'b0}}} - damp_len + 1;
//waiting for START to go high
if (START) State <= S1;
end
S1: //State 1
begin
init_delay_cnt <= init_delay_cnt + 1'b1;
if (init_delay_cnt[REG_WIDTH-1]) State <= S2;
end
S2: //State 2
begin
TX_EN = 1'b1;
tx_len_cnt <= tx_len_cnt + 1'b1;
if (tx_len_cnt[REG_WIDTH-1]) State <= S3;
end
S3: //State 3
begin
TX_EN = 1'b0;
DAMP = 1'b1;
damp_len_cnt <= damp_len_cnt + 1'b1;
if (damp_len_cnt[REG_WIDTH-1]) State <= S0;
end
endcase
end
end
wire [7:0] TXPi;
wire [7:0] TXNi;
assign TXPi[0] = TX_EN ? CLK : 1'b0;
assign TXPi[1] = TX_EN ? CLK : 1'b0;
assign TXPi[2] = TX_EN ? CLK : 1'b0;
assign TXPi[3] = TX_EN ? CLK : 1'b0;
assign TXPi[4] = TX_EN ? CLK : 1'b0;
assign TXPi[5] = TX_EN ? CLK : 1'b0;
assign TXPi[6] = TX_EN ? CLK : 1'b0;
assign TXPi[7] = TX_EN ? CLK : 1'b0;
assign TXNi[0] = TX_EN ? ~CLK : 1'b0;
assign TXNi[1] = TX_EN ? ~CLK : 1'b0;
assign TXNi[2] = TX_EN ? ~CLK : 1'b0;
assign TXNi[3] = TX_EN ? ~CLK : 1'b0;
assign TXNi[4] = TX_EN ? ~CLK : 1'b0;
assign TXNi[5] = TX_EN ? ~CLK : 1'b0;
assign TXNi[6] = TX_EN ? ~CLK : 1'b0;
assign TXNi[7] = TX_EN ? ~CLK : 1'b0;
assign TXN = DAMP ? 8'hFF : TXNi;
assign TXP = DAMP ? 8'hFF : TXPi;
endmodule
| 8.636191 |
module TX_Switch_tb;
parameter REG_WIDTH = 8;
parameter timescale_ref = 1000000; // reference scale based on timescale
parameter CLK_RATE_HZ = 20; // in MHz
//setting up clockticks
localparam integer clockticks = (timescale_ref / CLK_RATE_HZ) / 2.0;
//Signals
reg START;
wire TXD1N;
wire TXD1P;
wire TXD2N;
wire TXD2P;
wire TXD3N;
wire TXD3P;
wire TXD4N;
wire TXD4P;
wire TXD5N;
wire TXD5P;
wire TXD6N;
wire TXD6P;
wire TXD7N;
wire TXD7P;
wire TXD8N;
wire TXD8P;
//System Signals
reg CLK;
reg RESET;
reg [REG_WIDTH-1:0] init_delay;
reg [REG_WIDTH-1:0] tx_len;
reg [REG_WIDTH-1:0] damp_len;
TX_Switch uut (
//Signals
.CLK (CLK),
.RESET(RESET),
.START(START),
.init_delay(init_delay),
.tx_len(tx_len),
.damp_len(damp_len),
.TXP({TXD1P, TXD2P, TXD3P, TXD4P, TXD5P, TXD6P, TXD7P, TXD8P}),
.TXN({TXD1N, TXD2N, TXD3N, TXD4N, TXD5N, TXD6N, TXD7N, TXD8N})
);
initial begin
CLK = 1'b1;
RESET = 1'b0;
START = 1'b0;
init_delay = 5;
tx_len = 7;
damp_len = 3;
#(clockticks * 4) RESET = 1'b1;
#(clockticks * 4) RESET = 1'b0;
#(clockticks * 12) START = 1'b1;
#(clockticks * 1) START = 1'b0;
end
always begin
#clockticks CLK = ~CLK;
end
endmodule
| 9.493799 |
module TX_SYNC_GTP
(
output TXENPMAPHASEALIGN,
output TXPMASETPHASE,
output SYNC_DONE,
input USER_CLK,
input RESET
);
//*******************************Register Declarations************************
reg begin_r;
reg phase_align_r;
reg ready_r;
reg [14:0] sync_counter_r;
reg [9:0] wait_before_sync_r;
reg wait_stable_r;
//*******************************Wire Declarations****************************
wire count_512_complete_r;
wire next_phase_align_c;
wire next_ready_c;
wire next_wait_stable_c;
wire sync_count_complete_r;
//*******************************Main Body of Code****************************
//________________________________ State machine __________________________
// This state machine manages the phase alingnment procedure of the GTP.
// The module is held in reset till the usrclk source is stable.In the
// case of buffer bypass where the refclkout is used to clock the usrclks,
// the usrclk stable indication is given the pll_locked signal.
// Once the pll_lock is asserted, state machine goes into the wait_stable_r
// for 512 cycles to allow some time to ensure the pll is stable. After this,
// it goes into the phase_align_r state where the phase alignment procedure is
// executed. This involves asserting the TXENPHASEALIGN and TXPMASETPHASE for
// the recommended number of clock cycles
// State registers
always @(posedge USER_CLK)
if(RESET)
{begin_r,wait_stable_r,phase_align_r,ready_r} <= `DLY 4'b1000;
else
begin
begin_r <= `DLY 1'b0;
wait_stable_r <= `DLY next_wait_stable_c;
phase_align_r <= `DLY next_phase_align_c;
ready_r <= `DLY next_ready_c;
end
// Next state logic
assign next_wait_stable_c = begin_r |
(wait_stable_r & !count_512_complete_r);
assign next_phase_align_c = (wait_stable_r & count_512_complete_r) |
(phase_align_r & !sync_count_complete_r);
assign next_ready_c = (phase_align_r & sync_count_complete_r) |
ready_r;
//_________ Counter for to wait for pll to be stable before sync __________
always @(posedge USER_CLK)
begin
if (!wait_stable_r)
wait_before_sync_r <= `DLY 10'b000000000;
else
wait_before_sync_r <= `DLY wait_before_sync_r + 1'b1;
end
assign count_512_complete_r = wait_before_sync_r[9];
//_______________ Counter for holding SYNC for SYNC_CYCLES ________________
always @(posedge USER_CLK)
begin
if (!phase_align_r)
sync_counter_r <= `DLY 15'b000000000000000;
else
sync_counter_r <= `DLY sync_counter_r + 1'b1;
end
assign sync_count_complete_r = sync_counter_r[12];
//_______________ Assign the phase align ports into the GTP _______________
assign TXENPMAPHASEALIGN = !begin_r;
assign TXPMASETPHASE = phase_align_r;
//_______________________ Assign the sync_done port _______________________
assign SYNC_DONE = ready_r;
endmodule
| 6.580749 |
module tx_tb ();
//this is the testbench for the tx module independently
reg clk, Rst_n, TxData_Valid;
reg [31:0] TxData;
reg Error_Ack, Rx_Ready, Rx_Error;
wire Tx_Ready, Tx_Error, S_Data;
wire Tx_Ready_net, Tx_Error_net, S_Data_net;
tx DUT (
.Clk_s(clk),
.Rst_n(Rst_n),
.TxData_Valid(TxData_Valid),
.TxData(TxData),
.Error_Ack(Error_Ack),
.Rx_Ready(Rx_Ready),
.Rx_Error(Rx_Error), //INPUTS
.Tx_Ready(Tx_Ready),
.Tx_Error(Tx_Error),
.S_Data(S_Data) //OUTPUTS
);
tx_synth netDUT (
.Clk_s(clk),
.Rst_n(Rst_n),
.TxData_Valid(TxData_Valid),
.TxData(TxData),
.Error_Ack(Error_Ack),
.Rx_Ready(Rx_Ready),
.Rx_Error(Rx_Error), //INPUTS
.Tx_Ready(Tx_Ready_net),
.Tx_Error(Tx_Error_net),
.S_Data(S_Data_net) //OUTPUTS
);
reg Tx_Ready_Error, Tx_Error_Error, S_Data_Error, Global_Error;
always @(negedge clk) begin
Tx_Ready_Error = (Tx_Ready != Tx_Ready_net);
Tx_Error_Error = (Tx_Error != Tx_Error_net);
S_Data_Error = (S_Data != S_Data_net);
Global_Error = (Tx_Ready_Error || Tx_Error_Error || S_Data_Error);
end
reg failedTestCase = 1'b0;
/*
reg nextErr = 1'b0;
always @(posedge clk) nextErr = failedTestCase ? 0 : failedTestCase;
always @(posedge clk) failedTestCase = nextErr;
*/
//establish a clk
always #5 clk = !clk;
reg [5:0] count_1 = 6'd0;
initial begin
//start by giving tx a few cycles to 'warm up'
//assert and deassert reset
clk = 1'b0;
Rst_n = 1'b0;
TxData_Valid = 1'b0;
Error_Ack = 1'b0;
Rx_Ready = 1'b0;
Rx_Error = 1'b0;
#10
//release reset
Rst_n = 1'b1;
//now lets have some fun. We will send a signal from the tb core and
//watch it send the message. We will watch each bit and confirm that it
//is the expected operation...
Rx_Ready = 1'b1;
@(negedge clk) TxData = 32'b_1111_0010_0101_0101_1100_1100_1100_1100;
@(negedge clk)
TxData_Valid = 1'b1;//We have now told the Tx Module it can go to town... If Rx is ready it will go...
//Here we should see Tx_Ready Drop //40ns
//if(Tx_Ready != 1'b0) failedTestCase = 1'b1;
@(negedge Tx_Ready)
//hold valid a little after to make sure synth version sees it
@(posedge clk)
@(posedge clk)
TxData_Valid = 1'b0; //when Tx_Ready goes low, TxData_Valid can go down as well...
//We should now see the signal come as 00000
@(negedge S_Data) //when S_Data goes low, the start sequence should start
for (count_1 = 6'd0; count_1 < 6'd5; count_1 = count_1 + 1'b1) begin
@(negedge clk) if (S_Data != 1'b0) failedTestCase = 1'b1;
end
Rx_Ready = 1'b0; //simulate the fact that Rx would have seen the start sequence
//Then as 1111 1111 0101 etc.
for (count_1 = 6'd32; count_1 > 0; count_1 = count_1 - 1'b1) begin
@(negedge clk) if (S_Data != TxData[count_1-1'b1]) failedTestCase = 1'b1;
end
@(negedge clk) if (S_Data != ~^(TxData)) failedTestCase = 1'b1;
//Tx_Ready should go high as soon as the data is transmitted
//(Regardless of error)
@(negedge clk) if (Tx_Ready != 1'b1) failedTestCase = 1'b1;
//After the full signal transmits, the Rx_Error line will stay low or
//go high depending on if there was an error, for the purpose of this
//tb, we will assert the error signal
@(posedge clk) Rx_Error = 1'b1;
Rx_Ready = 1'b1; //Set High, as Rx is done with that packet.
@(posedge clk) Rx_Error = 1'b0; // Deassert after a cycle
//we should now see the Tx_Error go high a cycle later, and then see
//the Error_Ack Signal go high, followed by the Tx_Error signal
//going low
@(posedge clk) if (Tx_Error != 1'b1) failedTestCase = 1'b1;
Error_Ack = 1'b1;
@(posedge clk) #1 if (Tx_Error != 1'b0) failedTestCase = 1'b1;
Error_Ack = 1'b0;
//hold for a bit so we see everything
#20 $stop;
end
endmodule
| 6.93599 |
module tx_t (
input MAIN_PAUSE,
output reg clk,
output reg RESET_L,
output reg PUSH_MAIN,
output reg init,
output reg POP_D0,
output reg POP_D1,
output reg [5:0] DATA_IN_TX,
output reg [4:0] main_fifo_low,
output reg [4:0] main_fifo_high,
output reg [4:0] Vco_low,
output reg [4:0] Vco_high,
output reg [4:0] Vc1_low,
output reg [4:0] Vc1_high,
output reg [4:0] Do_low,
output reg [4:0] Do_high,
output reg [4:0] D1_low,
output reg [4:0] D1_high
);
initial begin
$dumpfile("result_tx.vcd");
$dumpvars;
{clk, RESET_L, PUSH_MAIN, init, POP_D0, POP_D1} <= 0;
{DATA_IN_TX} <= 0;
{main_fifo_high, main_fifo_low, Vco_high, Vco_low, Vc1_high, Vc1_low} <= 0;
{D1_high, D1_low, Do_low, Do_high} <= 0;
@(posedge clk);
RESET_L <= 1;
@(posedge clk);
main_fifo_low <= 'h1;
main_fifo_high <= 'h3;
Vco_low <= 'h3;
Vco_high <= 'hC;
Vc1_low <= 'h3;
Vc1_high <= 'hC;
Do_low <= 'h1;
Do_high <= 'h3;
D1_low <= 'h1;
D1_high <= 'h3;
@(posedge clk);
DATA_IN_TX <= 'b000000;
PUSH_MAIN <= 1;
@(posedge clk);
DATA_IN_TX <= 'b000001;
@(posedge clk);
DATA_IN_TX <= 'b000010;
@(posedge clk);
DATA_IN_TX <= 'b000011;
@(posedge clk);
DATA_IN_TX <= 'b000100;
@(posedge clk);
DATA_IN_TX <= 'b000101;
@(posedge clk);
DATA_IN_TX <= 'b000110;
@(posedge clk);
DATA_IN_TX <= 'b000111;
POP_D0 <= 1;
POP_D1 <= 1;
@(posedge clk);
DATA_IN_TX <= 'b001000;
@(posedge clk);
DATA_IN_TX <= 'b001001;
@(posedge clk);
DATA_IN_TX <= 'b001010;
@(posedge clk);
DATA_IN_TX <= 'b001011;
@(posedge clk);
DATA_IN_TX <= 'b001100;
@(posedge clk);
DATA_IN_TX <= 'b001101;
@(posedge clk);
DATA_IN_TX <= 'b001110;
@(posedge clk);
DATA_IN_TX <= 'b001111;
@(posedge clk);
DATA_IN_TX <= 'b000000;
PUSH_MAIN <= 0;
@(posedge clk); //end algo
repeat (10) @(posedge clk);
POP_D0 <= 0;
POP_D1 <= 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
DATA_IN_TX <= 'b110000;
PUSH_MAIN <= 1;
@(posedge clk);
DATA_IN_TX <= 'b010001;
@(posedge clk);
DATA_IN_TX <= 'b100010;
@(posedge clk);
DATA_IN_TX <= 'b000011;
@(posedge clk);
DATA_IN_TX <= 'b010100;
@(posedge clk);
DATA_IN_TX <= 'b100101;
@(posedge clk);
DATA_IN_TX <= 'b110110;
@(posedge clk);
DATA_IN_TX <= 'b000111;
POP_D0 <= 1;
POP_D1 <= 1;
@(posedge clk);
DATA_IN_TX <= 'b101000;
@(posedge clk);
DATA_IN_TX <= 'b111001;
@(posedge clk);
DATA_IN_TX <= 'b011010;
@(posedge clk);
DATA_IN_TX <= 'b101011;
@(posedge clk);
DATA_IN_TX <= 'b111100;
@(posedge clk);
DATA_IN_TX <= 'b001101;
@(posedge clk);
DATA_IN_TX <= 'b011110;
@(posedge clk);
DATA_IN_TX <= 'b011111;
@(posedge clk);
DATA_IN_TX <= 'b000000;
PUSH_MAIN <= 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
POP_D0 <= 0;
POP_D1 <= 0;
repeat (8) @(posedge clk);
$finish;
end
initial clk <= 0;
always #2 clk <= ~clk;
endmodule
| 7.194042 |
module tx_tb ();
reg clk;
reg rst_n;
reg TxD_start;
reg Enable;
reg [7:0] TxD_data;
wire TxD;
wire TBR;
tx iDUT (
clk,
rst_n,
TxD_start,
Enable,
TxD_data,
TxD,
TBR
);
initial begin
$dumpfile("test_tx.vcd");
$dumpvars(0, iDUT);
clk = 0;
rst_n = 0;
TxD_start = 0;
Enable = 0;
TxD_data = 8'b10101010;
#12;
rst_n = 1;
#3;
TxD_start = 1'b1;
#20;
TxD_start = 1'b0;
#50000;
$stop;
end
always begin
#5;
clk = ~clk;
end
always begin
#25;
Enable = 1;
#5;
Enable = 0;
end
always begin
#475;
$display("TxD = %b", TxD);
$display("TBR = %b", TBR);
#5;
end
endmodule
| 7.939113 |
module top (
input clk,
output Tx
);
wire [7:0] w_data;
wire w_Tx_EN;
wire w_RFN;
UART_Tx #(1250) u1 (
.clk(clk),
.data(w_data),
.Tx_EN(w_Tx_EN),
.Tx(Tx),
.RFN(w_RFN)
);
tx t1 (
.clk (clk),
.Tx_EN(w_Tx_EN),
.RFN (w_RFN),
.data (w_data)
);
endmodule
| 7.233807 |
module UART_Tx #(
parameter CPB = 1250
) // CPB = clocks per bit: 12 MHz / 9600 Baud = 1250
(
input clk,
input [7:0] data,
input Tx_EN,
output Tx,
output RFN // RFN = ready for next (data)
);
// states
localparam START = 0;
localparam TRANSMIT = 1;
localparam IDLE = 2;
// state machine reg
reg [1:0] STATE = IDLE; // initialized state is IDLE
// data reg with start and stop bits
reg [8:0] temp = 9'b000000000;
// output registers
reg r_Tx = 1;
reg r_RFN = 0;
// counting registers
reg [10:0] counter = 0;
reg [3:0] sample = 0;
reg CE;
// counters
always @(posedge clk) begin
if (CE) begin
if (counter < CPB - 1) counter <= counter + 1;
else counter <= 0;
end // if (CE)
else counter <= 0; // if CE low, counter is reset to 0
end // always
always @(posedge clk) begin
if (counter == CPB - 1) begin
if (sample < 9) sample <= sample + 1;
else sample <= 0;
end // if (counter...
end // always
// state machine
always @(posedge clk) begin
case (STATE)
START: begin
temp = {1'b1, data[7:0]}; // data plus stop bit
CE <= 1;
r_Tx <= 0; // send start bit (low)
r_RFN <= 0; // dont load new data
if (counter == CPB - 1) STATE <= TRANSMIT;
else STATE <= START;
end // START
TRANSMIT: begin
if (sample < 9) r_Tx <= temp[sample];
else begin
r_RFN <= 1; // ready for new data
STATE <= IDLE;
CE <= 0;
end // else
end // TRANSMIT
IDLE: begin
if (Tx_EN) STATE <= START;
else r_Tx <= 1;
end // IDLE
default: begin
CE <= 0;
STATE <= IDLE;
end // default
endcase
end // always
assign Tx = r_Tx;
assign RFN = r_RFN;
endmodule
| 7.336003 |
module tx ( // sends data to UART_Tx to be then serialized and sent over UART to terminal
input clk,
output [7:0] data,
output Tx_EN,
input RFN // RFN = ready for next (data)
);
reg [7:0] r_data;
reg r_Tx_EN;
reg [31:0] counter;
always @(posedge clk) begin
if (counter <= 78002) counter <= counter + 1;
else counter <= 0;
end
always @(posedge clk) begin
if (counter == 13000) begin
r_data <= 8'h48;
r_Tx_EN <= 1;
end else if (counter == 13001) r_Tx_EN <= 0;
if (RFN) begin
if (counter == 26000) begin
r_data <= 8'h45;
r_Tx_EN <= 1;
end else if (counter == 26001) r_Tx_EN <= 0;
else if (counter == 39000) begin
r_data <= 8'h4C;
r_Tx_EN <= 1;
end else if (counter == 39001) r_Tx_EN <= 0;
else if (counter == 52000) begin
r_data <= 8'h4C;
r_Tx_EN <= 1;
end else if (counter == 52001) r_Tx_EN <= 0;
else if (counter == 65000) begin
r_data <= 8'h4F;
r_Tx_EN <= 1;
end else if (counter == 65001) r_Tx_EN <= 0;
else if (counter == 78000) begin
r_data <= 8'h20;
r_Tx_EN <= 1;
end else if (counter == 78001) r_Tx_EN <= 0;
end // if RFN
end // always
assign Tx_EN = r_Tx_EN;
assign data = r_data;
endmodule
| 8.35717 |
module: UART_TX
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tx_test;
// Inputs
reg [7:0] RxD_par;
reg RxD_start;
reg RTS;
reg sys_clk;
wire BaudTick;
// Outputs
wire TxD_ser;
BaudGen baudgen (
.sys_clk(sys_clk),
.BaudTick(BaudTick)
);
// Instantiate the Unit Under Test (UUT)
UART_TX uut (
.RxD_par(RxD_par),
.RxD_start(RxD_start),
.RTS(RTS),
.sys_clk(sys_clk),
.BaudTick(BaudTick),
.TxD_ser(TxD_ser)
);
initial begin
// Initialize Inputs
RxD_par = 8'b01010101;
RxD_start = 0;
RTS = 1;
sys_clk = 0;
// Wait 100 ns for global reset to finish
#4000;
#37 RxD_start = 1;
#74 RxD_start = 0;
// Add stimulus here
end
always begin
#18.5 sys_clk <= !sys_clk;
end
endmodule
| 7.984548 |
module tx_testbench ();
//input
reg [7:0] data_o;
reg clk;
reg receive_ack;
//output
wire txd;
wire LEDmind;
uart_tx uarttx (
.data_o(data_o),
.txd(txd),
.clk(clk),
.receive_ack(receive_ack),
.LEDmind(LEDmind)
);
initial begin
#0 clk = 0;
data_o = 0;
receive_ack = 0;
#50 data_o = 'b11111111;
#100 receive_ack = 1;
#10 receive_ack = 0;
#110 data_o = 'b10001100;
#40 receive_ack = 1;
#10 receive_ack = 0;
#110 data_o = 'b11101101;
#40 receive_ack = 1;
#10 receive_ack = 0;
#110 data_o = 'b00001101;
#40 receive_ack = 1;
#10 receive_ack = 0;
end
always #5 clk = !clk;
endmodule
| 7.820584 |
module: can_tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Tx_test_internal;
// Inputs
reg [10:0] address;
reg clk;
reg baud_clk;
reg rst;
reg [63:0] data;
reg send_data;
reg clear_to_tx;
assign rx = tx;
assign bitstuffed_output = tx;
// Outputs
wire tx;
wire can_bitstuff;
wire txing;
// Instantiate the Unit Under Test (UUT)
can_tx uut (
.tx(tx),
.can_bitstuff(can_bitstuff),
.txing(txing),
.rx(rx),
.address(address),
.clk(clk),
.baud_clk(baud_clk),
.rst(rst),
.data(data),
.send_data(send_data),
.bitstuffed_output(bitstuffed_output),
.clear_to_tx(clear_to_tx)
);
initial begin
// Initialize Inputs
address = 11'h28;
clk = 0;
baud_clk = 0;
rst = 1;
data = 43;
send_data = 0;
clear_to_tx = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
#10;
send_data = 1;
clear_to_tx = 1;
#300000 $stop;
// Add stimulus here
end
always #1.25 clk=~clk;
always #1000 baud_clk=~baud_clk;
endmodule
| 8.134321 |
module tx_timer (
input clk,
input rst,
input reg_flush,
input [31:0] reg_tout,
input timer_start,
output reg timer_busy,
output [31:0] timer_cnt
);
reg [25:0] timer;
assign timer_cnt = {6'b0, timer};
always @(posedge clk) begin
if (rst || (timer == reg_tout) || reg_flush) timer <= 'b0;
else if (timer_start) timer <= 'b1;
else if (|timer && (timer < reg_tout)) timer <= 'b1 + timer;
end
always @(posedge clk) begin
if (rst) timer_busy <= 1'b0;
else if (timer_start) timer_busy <= 1'b1;
else if ((timer == reg_tout[25:0]) && |reg_tout[25:0]) timer_busy <= 1'b0;
end
endmodule
| 6.834962 |
module tx_top_v ();
reg [11:0] story_tb;
reg clk, reset;
reg [7:0] dat_i;
reg lchar_i, valid_i;
wire d_o, s_o, ready_o;
tx_top top (
.txClk (clk),
.txReset(reset),
.dat_i (dat_i),
.lchar_i(lchar_i),
.valid_i(valid_i),
.d(d_o),
.s(s_o),
.ready_o(ready_o)
);
`DEFIO(clk, H, L)
`DEFASSERT0(d, o)
`DEFASSERT0(s, o)
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
// Make sure that the S signal is stable between characters.
story_tb <= 12'h000;
{clk, valid_i, lchar_i, dat_i} <= 0;
reset <= 1;
clkL();
clkH();
reset <= 0;
clkL();
clkH();
dat_i <= 8'h02;
lchar_i <= 1;
valid_i <= 1;
clkL();
clkH();
assert_d(0);
assert_s(0);
story_tb <= 12'h001;
valid_i <= 0;
clkL();
clkH(); // Drives Tx pins during this cycle...
story_tb <= 12'hFFF;
clkL();
clkH(); // ... which should appear at D/S now.
assert_d(0);
assert_s(1); // Parity
story_tb <= 12'hFFE;
clkL();
clkH();
assert_d(1);
assert_s(1); // LChar flag
story_tb <= 12'h002;
clkL();
clkH();
assert_d(0);
assert_s(1); // D0a
story_tb <= 12'h003;
clkL();
clkH();
assert_d(1);
assert_s(1); // D1a
story_tb <= 12'h004;
dat_i <= 8'h00;
valid_i <= 1;
lchar_i <= 1;
clkL();
clkH();
assert_d(1);
assert_s(1); // D/S stable
story_tb <= 12'h005;
valid_i <= 0;
lchar_i <= 0;
clkL();
clkH();
clkL();
clkH();
assert_d(1);
assert_s(0); // Parity
story_tb <= 12'h006;
clkL();
clkH();
assert_d(1);
assert_s(1); // LChar flag
story_tb <= 12'h007;
clkL();
clkH();
assert_d(0);
assert_s(1); // D0b
story_tb <= 12'h008;
clkL();
clkH();
assert_d(0);
assert_s(0); // D1b
$display("@I Done.");
$stop;
end
endmodule
| 6.957977 |
module tx_uart #(
parameter DBIT = 8,
parameter NB_STATE = 2,
parameter SB_TICK = 16
) (
input i_clock,
input i_reset,
input i_tx_start,
input i_s_tick,
input [DBIT-1:0] i_data,
output reg o_tx_done_tick,
output o_tx
);
localparam [NB_STATE - 1 : 0] IDLE = 2'b00;
localparam [NB_STATE - 1 : 0] START = 2'b01;
localparam [NB_STATE - 1 : 0] DATA = 2'b10;
localparam [NB_STATE - 1 : 0] STOP = 2'b11;
reg [1:0] state, next_state;
reg [3:0] tick_counter, next_tick_counter;
reg [2:0] data_counter, next_data_counter;
reg [DBIT-1:0] shiftreg, next_shiftreg;
reg tx_reg, tx_next;
always @(posedge i_clock) begin //le saque el posedge reset
if (i_reset) begin
state <= IDLE;
tick_counter <= 0;
data_counter <= 0;
shiftreg <= 0;
tx_reg <= 1'b1;
end else begin
state <= next_state;
tick_counter <= next_tick_counter;
data_counter <= next_data_counter;
shiftreg <= next_shiftreg;
tx_reg <= tx_next;
end
end
always @(*) begin
next_state = state;
o_tx_done_tick = 1'b0;
next_tick_counter = tick_counter;
next_data_counter = data_counter;
next_shiftreg = shiftreg;
tx_next = tx_reg;
case (state)
IDLE: begin
tx_next = 1'b1;
if (i_tx_start) begin
next_state = START;
next_tick_counter = 0;
next_shiftreg = i_data;
end
end
START: begin
tx_next = 1'b0;
if (i_s_tick) begin
if (tick_counter == (SB_TICK - 1)) begin
next_state = DATA;
next_tick_counter = 0;
next_data_counter = 0;
end else begin
next_tick_counter = tick_counter + 1;
end
end
end
DATA: begin
tx_next = shiftreg[0];
if (i_s_tick) begin
if (tick_counter == (SB_TICK - 1)) begin
next_tick_counter = 0;
next_shiftreg = shiftreg >> 1;
if (data_counter == (DBIT - 1)) next_state = STOP;
else begin
next_data_counter = data_counter + 1;
end
end else next_tick_counter = tick_counter + 1;
end
end
STOP: begin
tx_next = 1'b1;
if (i_s_tick) begin
if (tick_counter == 4'b1111) begin
next_state = IDLE;
o_tx_done_tick = 1'b1;
end else begin
next_tick_counter = tick_counter + 1;
end
end
end
endcase
end
assign o_tx = tx_reg;
endmodule
| 7.908163 |
module tx_write_dev_MSN_bram_V_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 63;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "hls_ultra", cascade_height = 1 *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./tx_write_dev_MSN_bram_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
end
end
endmodule
| 8.085225 |
module tx_write_dev_MSN_bram_V (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd63;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
tx_write_dev_MSN_bram_V_ram tx_write_dev_MSN_bram_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 8.085225 |
module tx_write_dev_MSN_V #(
parameter
DataWidth = 64,
AddressWidth = 13,
AddressRange = 8192
) (
input wire clk,
input wire reset,
input wire [AddressWidth-1:0] address0,
input wire ce0,
input wire we0,
input wire [ DataWidth-1:0] d0,
output wire [ DataWidth-1:0] q0
);
//------------------------Local signal-------------------
reg [AddressRange-1:0] written = {AddressRange{1'b0}};
wire [ DataWidth-1:0] q0_ram;
wire [ DataWidth-1:0] q0_rom;
wire q0_sel;
reg [ 0:0] sel0_sr;
//------------------------Instantiation------------------
tx_write_dev_MSN_V_ram tx_write_dev_MSN_V_ram_u (
.clk (clk),
.ce0 (ce0),
.addr0(address0),
.we0 (we0),
.d0 (d0),
.q0 (q0_ram)
);
//------------------------Body---------------------------
assign q0 = q0_sel ? q0_ram : q0_rom;
assign q0_sel = sel0_sr[0];
assign q0_rom = 64'b1000000000000000000000000000000000000000000000000000000000000000;
always @(posedge clk) begin
if (reset) written <= 1'b0;
else begin
if (ce0 & we0) begin
written[address0] <= 1'b1;
end
end
end
always @(posedge clk) begin
if (ce0) begin
sel0_sr[0] <= written[address0];
end
end
endmodule
| 8.085225 |
module tx_write_dev_MSN_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "hls_ultra", cascade_height = 1 *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
endmodule
| 8.085225 |
module tx_write_dev_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 8.085225 |
module tx_write_dev_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 8.085225 |
module tx_write_dev_reset_MSN_V_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 1;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./tx_write_dev_reset_MSN_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
end
end
endmodule
| 8.085225 |
module tx_write_dev_reset_MSN_V (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
tx_write_dev_reset_MSN_V_ram tx_write_dev_reset_MSN_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 8.085225 |
module tx_wr_addr_synch (
input clk_out,
input reset_n_clk_out,
input clk_in,
input reset_n_clk_in,
input [9:0] commited_wr_addr_in,
output reg [9:0] commited_wr_addr_out
);
// localparam
localparam s0 = 8'b00000000;
localparam s1 = 8'b00000001;
localparam s2 = 8'b00000010;
localparam s3 = 8'b00000100;
localparam s4 = 8'b00001000;
localparam s5 = 8'b00010000;
localparam s6 = 8'b00100000;
localparam s7 = 8'b01000000;
localparam s8 = 8'b10000000;
//-------------------------------------------------------
// Local a
//-------------------------------------------------------
reg [7:0] fsm_a;
reg [9:0] bus_in_last;
reg synch;
reg [9:0] cross;
//-------------------------------------------------------
// Local b
//-------------------------------------------------------
reg synch_reg0;
reg synch_reg1;
reg [9:0] cross_reg0;
////////////////////////////////////////////////
// a
////////////////////////////////////////////////
always @( posedge clk_in or negedge reset_n_clk_in ) begin
if (!reset_n_clk_in ) begin // reset
bus_in_last <= 'b0;
synch <= 1'b0;
fsm_a <= s0;
end
else begin // not reset
case (fsm_a)
s0 : begin
if (bus_in_last != commited_wr_addr_in) begin
cross <= commited_wr_addr_in;
fsm_a <= s1;
end
end
s1 : begin
bus_in_last <= cross;
synch <= 1'b1;
fsm_a <= s2;
end
s2 : fsm_a <= s3;
s3 : begin
synch <= 1'b0;
fsm_a <= s4;
end
s4 : fsm_a <= s5;
s5 : fsm_a <= s6;
s6 : fsm_a <= s7;
s7 : fsm_a <= s0;
default : begin
fsm_a <= s0;
end
endcase
end // not reset
end //always
////////////////////////////////////////////////
// b
////////////////////////////////////////////////
always @( posedge clk_out or negedge reset_n_clk_out ) begin
if (!reset_n_clk_out ) begin // reset
commited_wr_addr_out <= 'b0;
synch_reg0 <= 1'b0;
synch_reg1 <= 1'b0;
end
else begin // not reset
cross_reg0 <= cross;
synch_reg0 <= synch;
synch_reg1 <= synch_reg0;
if (synch_reg1) begin
commited_wr_addr_out <= cross_reg0;
end
end // not reset
end //always
endmodule
| 7.981102 |
module TYPEA (
input CLK,
input RESET_N,
input CLKEN,
input TDI,
output TDO,
output reg DATA_OUT,
input DATA_IN,
input CAPTURE_DR,
input UPDATE_DR
);
reg tdoInt;
always @(negedge CLK or negedge RESET_N) begin
if (RESET_N == 1'b0) tdoInt <= 1'b0;
else if (CLK == 1'b0)
if (CLKEN == 1'b1)
if (CAPTURE_DR == 1'b0) tdoInt <= TDI;
else tdoInt <= DATA_IN;
end
assign TDO = tdoInt;
always @(negedge CLK or negedge RESET_N) begin
if (RESET_N == 1'b0) DATA_OUT <= 1'b0;
else if (CLK == 1'b0) if (UPDATE_DR == 1'b1) DATA_OUT <= tdoInt;
end
endmodule
| 7.600886 |
module LockingRRArbiter (
input clock,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input [15:0] io_in_0_bits_RouteID,
input [ 5:0] io_in_0_bits_address,
input [15:0] io_in_0_bits_data,
input [ 1:0] io_in_0_bits_mask,
input io_in_1_valid,
input [15:0] io_in_1_bits_RouteID,
input [ 5:0] io_in_1_bits_address,
input [15:0] io_in_1_bits_data,
input [ 1:0] io_in_1_bits_mask,
input io_out_ready,
output io_out_valid,
output [15:0] io_out_bits_RouteID,
output [ 5:0] io_out_bits_address,
output [15:0] io_out_bits_data,
output [ 1:0] io_out_bits_mask,
output io_chosen
);
wire choice;
wire _GEN_0_valid;
wire _GEN_8;
wire [15:0] _GEN_9;
wire [5:0] _GEN_10;
wire [15:0] _GEN_11;
wire [1:0] _GEN_12;
wire [1:0] _GEN_3_bits_mask;
wire [15:0] _GEN_4_bits_data;
wire [5:0] _GEN_5_bits_address;
wire [15:0] _GEN_6_bits_RouteID;
reg value;
reg [31:0] _RAND_0;
reg _T_62;
reg [31:0] _RAND_1;
wire _T_66;
wire [1:0] _T_71;
wire _T_72;
wire _GEN_15;
wire _GEN_16;
wire _GEN_17;
reg lastGrant;
reg [31:0] _RAND_2;
wire _GEN_18;
wire grantMask_1;
wire validMask_1;
wire _T_83;
wire _T_91;
wire _T_92;
wire _T_93;
wire _GEN_19;
wire _GEN_20;
assign io_in_0_ready = _T_93;
assign io_out_valid = _GEN_0_valid;
assign io_out_bits_RouteID = _GEN_6_bits_RouteID;
assign io_out_bits_address = _GEN_5_bits_address;
assign io_out_bits_data = _GEN_4_bits_data;
assign io_out_bits_mask = _GEN_3_bits_mask;
assign io_chosen = _GEN_17;
assign choice = _GEN_20;
assign _GEN_0_valid = _GEN_8;
assign _GEN_8 = io_chosen ? io_in_1_valid : io_in_0_valid;
assign _GEN_9 = io_chosen ? io_in_1_bits_RouteID : io_in_0_bits_RouteID;
assign _GEN_10 = io_chosen ? io_in_1_bits_address : io_in_0_bits_address;
assign _GEN_11 = io_chosen ? io_in_1_bits_data : io_in_0_bits_data;
assign _GEN_12 = io_chosen ? io_in_1_bits_mask : io_in_0_bits_mask;
assign _GEN_3_bits_mask = _GEN_12;
assign _GEN_4_bits_data = _GEN_11;
assign _GEN_5_bits_address = _GEN_10;
assign _GEN_6_bits_RouteID = _GEN_9;
assign _T_66 = io_out_ready & io_out_valid;
assign _T_71 = value + 1'h1;
assign _T_72 = _T_71[0:0];
assign _GEN_15 = _T_66 ? io_chosen : _T_62;
assign _GEN_16 = _T_66 ? _T_72 : value;
assign _GEN_17 = value ? _T_62 : choice;
assign _GEN_18 = _T_66 ? io_chosen : lastGrant;
assign grantMask_1 = 1'h1 > lastGrant;
assign validMask_1 = io_in_1_valid & grantMask_1;
assign _T_83 = validMask_1 == 1'h0;
assign _T_91 = _T_62 == 1'h0;
assign _T_92 = value ? _T_91 : _T_83;
assign _T_93 = _T_92 & io_out_ready;
assign _GEN_19 = io_in_0_valid ? 1'h0 : 1'h1;
assign _GEN_20 = validMask_1 ? 1'h1 : _GEN_19;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
value = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
_T_62 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
lastGrant = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
value <= 1'h0;
end else begin
if (_T_66) begin
value <= _T_72;
end
end
if (_T_66) begin
_T_62 <= io_chosen;
end
if (_T_66) begin
lastGrant <= io_chosen;
end
end
endmodule
| 7.257641 |
module LockingRRArbiter_1 (
output io_in_0_ready,
input io_in_0_valid,
input io_out_ready,
output io_out_valid
);
assign io_in_0_ready = io_out_ready;
assign io_out_valid = io_in_0_valid;
endmodule
| 7.257641 |
module Demux (
input io_en,
output io_outputs_0_valid
);
wire _T_16;
wire _GEN_3;
assign io_outputs_0_valid = _GEN_3;
assign _T_16 = io_en == 1'h0;
assign _GEN_3 = _T_16 ? 1'h0 : 1'h1;
endmodule
| 7.252853 |
module LockingRRArbiter_2 (
input clock,
output io_in_0_ready,
input io_in_0_valid,
input [15:0] io_in_0_bits_RouteID,
input [15:0] io_in_0_bits_address,
output io_in_1_ready,
input io_in_1_valid,
input [15:0] io_in_1_bits_RouteID,
input [15:0] io_in_1_bits_address,
input io_out_ready,
output io_out_valid,
output [15:0] io_out_bits_RouteID,
output [15:0] io_out_bits_address,
output io_chosen
);
wire choice;
wire _GEN_0_valid;
wire _GEN_6;
wire [15:0] _GEN_7;
wire [15:0] _GEN_8;
wire [15:0] _GEN_3_bits_address;
wire [15:0] _GEN_4_bits_RouteID;
wire _T_60;
reg lastGrant;
reg [31:0] _RAND_0;
wire _GEN_11;
wire grantMask_1;
wire validMask_1;
wire _T_65;
wire _T_69;
wire _T_71;
wire _T_75;
wire _T_76;
wire _T_77;
wire _GEN_12;
wire _GEN_13;
assign io_in_0_ready = _T_76;
assign io_in_1_ready = _T_77;
assign io_out_valid = _GEN_0_valid;
assign io_out_bits_RouteID = _GEN_4_bits_RouteID;
assign io_out_bits_address = _GEN_3_bits_address;
assign io_chosen = choice;
assign choice = _GEN_13;
assign _GEN_0_valid = _GEN_6;
assign _GEN_6 = io_chosen ? io_in_1_valid : io_in_0_valid;
assign _GEN_7 = io_chosen ? io_in_1_bits_RouteID : io_in_0_bits_RouteID;
assign _GEN_8 = io_chosen ? io_in_1_bits_address : io_in_0_bits_address;
assign _GEN_3_bits_address = _GEN_8;
assign _GEN_4_bits_RouteID = _GEN_7;
assign _T_60 = io_out_ready & io_out_valid;
assign _GEN_11 = _T_60 ? io_chosen : lastGrant;
assign grantMask_1 = 1'h1 > lastGrant;
assign validMask_1 = io_in_1_valid & grantMask_1;
assign _T_65 = validMask_1 | io_in_0_valid;
assign _T_69 = validMask_1 == 1'h0;
assign _T_71 = _T_65 == 1'h0;
assign _T_75 = grantMask_1 | _T_71;
assign _T_76 = _T_69 & io_out_ready;
assign _T_77 = _T_75 & io_out_ready;
assign _GEN_12 = io_in_0_valid ? 1'h0 : 1'h1;
assign _GEN_13 = validMask_1 ? 1'h1 : _GEN_12;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
lastGrant = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (_T_60) begin
lastGrant <= io_chosen;
end
end
endmodule
| 7.257641 |
module LockingRRArbiter_3 (
input clock,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input [15:0] io_in_0_bits_addr,
input [ 7:0] io_in_0_bits_tag,
output io_in_1_ready,
input io_in_1_valid,
input [15:0] io_in_1_bits_addr,
input [ 7:0] io_in_1_bits_tag,
input io_out_ready,
output io_out_valid,
output [15:0] io_out_bits_addr,
output [ 7:0] io_out_bits_tag,
output io_chosen
);
wire choice;
wire _GEN_0_valid;
wire _GEN_7;
wire [15:0] _GEN_8;
wire [7:0] _GEN_11;
wire [7:0] _GEN_2_bits_tag;
wire [15:0] _GEN_5_bits_addr;
reg value;
reg [31:0] _RAND_0;
reg _T_62;
reg [31:0] _RAND_1;
wire _T_66;
wire [1:0] _T_71;
wire _T_72;
wire _GEN_13;
wire _GEN_14;
wire _GEN_15;
reg lastGrant;
reg [31:0] _RAND_2;
wire _GEN_16;
wire grantMask_1;
wire validMask_1;
wire _T_79;
wire _T_83;
wire _T_85;
wire _T_89;
wire _T_91;
wire _T_92;
wire _T_93;
wire _T_96;
wire _T_97;
wire _GEN_17;
wire _GEN_18;
assign io_in_0_ready = _T_93;
assign io_in_1_ready = _T_97;
assign io_out_valid = _GEN_0_valid;
assign io_out_bits_addr = _GEN_5_bits_addr;
assign io_out_bits_tag = _GEN_2_bits_tag;
assign io_chosen = _GEN_15;
assign choice = _GEN_18;
assign _GEN_0_valid = _GEN_7;
assign _GEN_7 = io_chosen ? io_in_1_valid : io_in_0_valid;
assign _GEN_8 = io_chosen ? io_in_1_bits_addr : io_in_0_bits_addr;
assign _GEN_11 = io_chosen ? io_in_1_bits_tag : io_in_0_bits_tag;
assign _GEN_2_bits_tag = _GEN_11;
assign _GEN_5_bits_addr = _GEN_8;
assign _T_66 = io_out_ready & io_out_valid;
assign _T_71 = value + 1'h1;
assign _T_72 = _T_71[0:0];
assign _GEN_13 = _T_66 ? io_chosen : _T_62;
assign _GEN_14 = _T_66 ? _T_72 : value;
assign _GEN_15 = value ? _T_62 : choice;
assign _GEN_16 = _T_66 ? io_chosen : lastGrant;
assign grantMask_1 = 1'h1 > lastGrant;
assign validMask_1 = io_in_1_valid & grantMask_1;
assign _T_79 = validMask_1 | io_in_0_valid;
assign _T_83 = validMask_1 == 1'h0;
assign _T_85 = _T_79 == 1'h0;
assign _T_89 = grantMask_1 | _T_85;
assign _T_91 = _T_62 == 1'h0;
assign _T_92 = value ? _T_91 : _T_83;
assign _T_93 = _T_92 & io_out_ready;
assign _T_96 = value ? _T_62 : _T_89;
assign _T_97 = _T_96 & io_out_ready;
assign _GEN_17 = io_in_0_valid ? 1'h0 : 1'h1;
assign _GEN_18 = validMask_1 ? 1'h1 : _GEN_17;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
value = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
_T_62 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
lastGrant = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
value <= 1'h0;
end else begin
if (_T_66) begin
value <= _T_72;
end
end
if (_T_66) begin
_T_62 <= io_chosen;
end
if (_T_66) begin
lastGrant <= io_chosen;
end
end
endmodule
| 7.257641 |
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