code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module two_compliment25 (
data_in,
data_out
);
input [24:0] data_in;
output [24:0] data_out;
wire [24:0] temp;
//Not
assign temp = ~data_in;
//add 1
adder25 add25 (
.A(temp),
.B(25'b1),
.S(data_out),
.Cout()
);
endmodule
| 6.975868 |
module two_compliment10 (
data_in,
data_out
);
input [9:0] data_in;
output [9:0] data_out;
wire [9:0] temp;
//Not
assign temp = ~data_in;
//add 1
adder10 add10 (
.A(temp),
.B(10'b1),
.S(data_out),
.Cout()
);
endmodule
| 6.975868 |
module two_compliment9 (
data_in,
data_out
);
input [8:0] data_in;
output [8:0] data_out;
wire [8:0] temp;
//Not
assign temp = ~data_in;
//add 1
adder9 add9 (
.A(temp),
.B(9'b1),
.S(data_out),
.Cout()
);
endmodule
| 6.975868 |
module two_compliment8 (
data_in,
data_out
);
input [7:0] data_in;
output [7:0] data_out;
wire [7:0] temp;
//Not
assign temp = ~data_in;
//add 1
adder8 add8 (
.A(temp),
.B(8'b1),
.S(data_out),
.Cout()
);
endmodule
| 6.975868 |
module two_compliment5 (
data_in,
data_out
);
input [4:0] data_in;
output [4:0] data_out;
wire [4:0] temp;
//Not
assign temp = ~data_in;
//add 1
adder5 add5 (
.A(temp),
.B(5'b1),
.S(data_out),
.Cout()
);
endmodule
| 6.975868 |
module two_comp_t (
input [27:0] a_m_shift,
input a_s,
output [27:0] z
);
assign z = a_s ? -a_m_shift : a_m_shift; // 2's complement
endmodule
| 7.926771 |
module two_decimal_vals (
input [7:0] val,
output [6:0] seg7_dig0,
output [6:0] seg7_dig1
);
integer storage;
integer dig0;
integer dig1;
reg [3:0] result_dig0;
reg [3:0] result_dig1;
// Create the module to display the 8 bit result
always @(*) begin
storage = (val[0] * 1) + (val[1] * 2) + (val[2] * 4) + (val[3] * 8) + (val[4] * 16) + (val[5] * 32) + (val[6] * 64);
dig0 = storage % 10;
dig1 = ((storage - (storage % 10)) / 10) % 10;
result_dig0 = dig0[3:0];
result_dig1 = dig1[3:0];
end
// Displays
seven_segment ZERO (
result_dig0,
seg7_dig0
);
seven_segment ONE (
result_dig1,
seg7_dig1
);
endmodule
| 6.564228 |
module two_decimal_vals_w_neg (
input [7:0] val,
output [6:0] seg7_neg_sign,
output [6:0] seg7_lsb,
output [6:0] seg7_mid,
output [6:0] seg7_msb
);
reg [3:0] result_one_digit;
reg [3:0] result_ten_digit;
reg [3:0] result_hundreds_digit;
reg result_is_negative;
reg [7:0] twos_comp;
always @(*) begin
twos_comp = -8'b1 * val;
if (val[7] == 1'b1) begin
result_is_negative = 1'b1;
result_one_digit = twos_comp % 8'd10;
result_ten_digit = (twos_comp / 8'd10) % 8'd10;
result_hundreds_digit = twos_comp / 8'd100;
end else begin
result_is_negative = 1'b0;
result_one_digit = val % 8'd10;
result_ten_digit = (val / 8'd10) % 8'd10;
result_hundreds_digit = val / 8'd100;
end
end
/* instantiate the modules for each of the seven seg decoders including the negative one */
seven_segment ones (
result_one_digit,
seg7_lsb
);
seven_segment tens (
result_ten_digit,
seg7_mid
);
seven_segment hundreds (
result_hundreds_digit,
seg7_msb
);
seven_segment_negative negative (
result_is_negative,
seg7_neg_sign
);
endmodule
| 6.564228 |
module two_dff_inv_rst (
clk_i,
rst_i,
d_i,
d0_o,
d1_o
);
input wire clk_i;
input wire rst_i;
input wire d_i;
output reg d0_o;
output reg d1_o;
wire int_rst;
assign int_rst = ~rst_i;
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
d0_o <= 0;
end else begin
d0_o <= d_i;
end
end
always @(posedge clk_i or posedge int_rst) begin
if (int_rst) begin
d1_o <= 0;
end else begin
d1_o <= d_i;
end
end
endmodule
| 7.523038 |
module Two_Digit_Counter (
input clk,
rst,
toggle,
output [6:0] seg_1,
seg_10
);
wire [3:0] bcdout_1, bcdout_10;
wire clk_1hz;
frequencyDivider f (
.rst(rst),
.clkIN(clk),
.clkOUT(clk_1hz)
);
counter c (
.clk(clk_1hz),
.rst(rst),
.toggle(toggle),
.bcd_1(bcdout_1),
.bcd_10(bcdout_10)
);
bcd_7 b1 (
.A (bcdout_1),
.out(seg_1)
);
bcd_7 b10 (
.A (bcdout_10),
.out(seg_10)
);
endmodule
| 7.256582 |
module fht_8x8_core (
rstn,
sclk,
x_valid,
x_data,
fht_2d_valid,
fht_2d_data
);
// Number of input bits
parameter N = 8;
input rstn;
input sclk;
input x_valid;
input [N-1:0] x_data;
output fht_2d_valid;
output [N+5:0] fht_2d_data;
// +++--->>> One-Dimensional Fast Hartley Transform - 1st Stage
// Data input [N-1:0] = N bits
//
wire fht_1d_valid;
wire [N+2:0] fht_1d_data;
fht_1d_x8 #(N) u1_fht_1d_x8_1st (
.rstn(rstn),
.sclk(sclk),
// input data
.x_valid(x_valid),
.x_data (x_data),
// output data
.fht_valid(fht_1d_valid),
.fht_data (fht_1d_data)
);
// +++--->>> Matrix Transposition <<<---+++ \\
wire mem_valid;
wire [N+2:0] mem_data;
mtx_trps_8x8_dpsram #(N + 3) u2_mtx_ts (
.rstn(rstn),
.sclk(sclk),
.inp_valid(fht_1d_valid),
.inp_data (fht_1d_data),
.mem_data (mem_data),
.mem_valid(mem_valid)
);
// +++--->>> One-Dimensional Fast Hartley Transform - 2nd Stage
fht_1d_x8 #(N + 3) u3_fht_1d_x8_2nd (
.rstn(rstn),
.sclk(sclk),
// input data
.x_valid(mem_valid),
.x_data (mem_data),
// output data
.fht_valid(fht_2d_valid),
.fht_data (fht_2d_data)
);
endmodule
| 7.889716 |
module fht_bfly_noFF (
a,
b,
c,
d
);
parameter N = 8;
input [N-1:0] a; // input
input [N-1:0] b; // input
output [N : 0] c; // additive output
output [N : 0] d; // subtractive output
assign c = rca_N(a, b);
assign d = rca_N(a, twos_complement(b));
// +--------------------------------------------------+ \\
// +----------- Function's Description Part ----------+ \\
// +--------------------------------------------------+ \\
// Full Adder
function [1:0] full_adder;
input a, b, ci;
reg co, s;
begin
s = (a ^ b ^ ci);
co = (a & b) | (ci & (a ^ b));
full_adder = {co, s};
end
endfunction
// Half Adder, i.e. without carry in
function [1:0] half_adder;
input a, b;
reg co, s;
begin
s = (a ^ b);
co = (a & b);
half_adder = {co, s};
end
endfunction
// Ripple Carry Adder - rca
// Input vector = N bits
// Output vector = N + 1 bits
function [N:0] rca_N;
// parameter N = 8;
input [N-1:0] a;
input [N-1:0] b;
reg [N-1:0] co, sum;
begin : RCA // RIPPLE CARRY ADDER
integer i;
//for (i = 0; i <= N; i = i + 1)
for (i = 0; i < N; i = i + 1)
if (i == 0) {co[i], sum[i]} = half_adder(a[i], b[i]);
else {co[i], sum[i]} = full_adder(a[i], b[i], co[i-1]);
rca_N[N-1:0] = sum;
// MSB is a sign bit
rca_N[N] = (a[N-1] == b[N-1]) ? co[N-1] : sum[N-1];
end
endfunction
function [N-1:0] twos_complement;
input [N-1:0] a;
reg [N-1:0] ainv;
reg [ N:0] plus1;
begin
ainv = ~a;
plus1 = rca_N(ainv, {{N - 1{1'b0}}, 1'b1});
// pragma coverage block = off
// synopsys translate_off
// The only problem is absolute minumum negative value
if (a == {1'b1, {N - 1{1'b0}}})
$display("--->>> 2's complement ERROR - absolute minimum negative value: %0b\n\t %m", a);
// synopsys translate_on
// pragma coverage block = on
twos_complement = plus1[N-1:0];
end
endfunction
endmodule
| 7.21281 |
module fht_bfly (
rstn,
clk,
valid,
a,
b,
c,
d
);
parameter N = 8;
input rstn;
input clk;
input valid;
input [N-1:0] a; // input
input [N-1:0] b; // input
output [N : 0] c; // additive output
output [N : 0] d; // subtractive output
reg [N-1:0] a_FF;
always @(posedge clk)
if (!rstn) a_FF <= #1 0;
else if (valid) a_FF <= #1 a;
reg [N-1:0] b_FF;
always @(posedge clk)
if (!rstn) b_FF <= #1 0;
else if (valid) b_FF <= #1 b;
assign c = rca_N(a_FF, b_FF);
assign d = rca_N(a_FF, twos_complement(b_FF));
// +--------------------------------------------------+ \\
// +----------- Function's Description Part ----------+ \\
// +--------------------------------------------------+ \\
// Full Adder
function [1:0] full_adder;
input a, b, ci;
reg co, s;
begin
s = (a ^ b ^ ci);
co = (a & b) | (ci & (a ^ b));
full_adder = {co, s};
end
endfunction
// Half Adder, i.e. without carry in
function [1:0] half_adder;
input a, b;
reg co, s;
begin
s = (a ^ b);
co = (a & b);
half_adder = {co, s};
end
endfunction
// Ripple Carry Adder - rca
// Input vector = N bits
// Output vector = N + 1 bits
function [N:0] rca_N;
// parameter N = 8;
input [N-1:0] a;
input [N-1:0] b;
reg [N-1:0] co, sum;
begin : RCA // RIPPLE_CARRY_ADDER
integer i;
//for (i = 0; i <= N; i = i + 1)
for (i = 0; i < N; i = i + 1)
if (i == 0) {co[i], sum[i]} = half_adder(a[i], b[i]);
else {co[i], sum[i]} = full_adder(a[i], b[i], co[i-1]);
rca_N[N-1:0] = sum;
// MSB is a sign bit
rca_N[N] = (a[N-1] == b[N-1]) ? co[N-1] : sum[N-1];
end
endfunction
function [N-1:0] twos_complement;
input [N-1:0] a;
reg [N-1:0] ainv;
reg [ N:0] plus1;
begin
ainv = ~a;
plus1 = rca_N(ainv, {{N - 1{1'b0}}, 1'b1});
// pragma coverage block = off
// synopsys translate_off
// The only problem is absolute minumum negative value
if (a == {1'b1, {N - 1{1'b0}}})
$display("--->>> 2's complement ERROR - absolute minimum negative value: %0b\n\t %m", a);
// synopsys translate_on
// pragma coverage block = on
twos_complement = plus1[N-1:0];
end
endfunction
endmodule
| 7.43346 |
module mtx_trps_8x8_dpsram (
rstn,
sclk,
// Input
inp_valid,
inp_data,
// Output
mem_data,
mem_valid
);
parameter N = 8;
input rstn;
input sclk;
input inp_valid;
input [N-1:0] inp_data;
output [N-1:0] mem_data;
output mem_valid;
reg [6:0] cnt128d_wr; // Write Mode Counter
wire indicator; // 64 words written - Indication(pos. or neg. edge)
reg indicator_1d; // Indication 1 clock delay
wire indicator_pos_edge; // positive edge
wire indicator_neg_edge; // negative edge
reg [6:0] cnt128d_rd; // Read Counter
wire cnt128d_rd_valid_start; // Counter start increment
wire cnt128d_rd_valid_stop; // Counter stop increment
reg cnt128d_rd_valid; // valid time for cnt128d_rd counter
reg mem_valid; // 1 clock delay after reading
// DPSRAM Memory Signal Description
wire [15:0] wr_DATA;
wire [6:0] wr_ADDR;
wire wr_CSN;
wire wr_WEN;
wire [6:0] rd_ADDR;
wire rd_CSN;
`ifdef USE_FPGA_SPSRAM
wire [15:0] rd_DATA;
dpsram_128x16 u_dpsram (
.addra(wr_ADDR),
.addrb(rd_ADDR),
.clka (sclk),
.clkb (sclk),
.dina (wr_DATA),
.dinb ({16{1'b0}}),
.douta( /* OPEN */),
.doutb(rd_DATA),
.ena (wr_CSN),
.enb (rd_CSN),
.wea (wr_WEN),
.web (1'b1)
);
`endif
`ifdef USE_ASIC_SPSRAM
reg [15:0] rd_DATA = 16'd0;
reg [15:0] sram[0:127];
always @(posedge sclk) if (~wr_WEN && ~wr_CSN) sram[wr_ADDR] <= wr_DATA; // Write
always @(posedge sclk) if (1'b1 && ~rd_CSN) rd_DATA <= sram[rd_ADDR]; // Read
`endif
always @(posedge sclk or negedge rstn)
if (!rstn) cnt128d_wr <= #1 0;
else if (inp_valid) cnt128d_wr <= #1 cnt128d_wr + 1;
assign wr_DATA = {{16 - N{1'b0}}, inp_data};
assign wr_ADDR = cnt128d_wr;
assign wr_CSN = ~inp_valid;
assign wr_WEN = ~inp_valid;
// Start Reading After fisrt 64 words had been written
assign indicator = cnt128d_wr[6];
always @(posedge sclk or negedge rstn)
if (!rstn) indicator_1d <= #1 1'b0;
else indicator_1d <= #1 indicator;
assign indicator_pos_edge = indicator & ~indicator_1d;
assign indicator_neg_edge = ~indicator & indicator_1d;
assign cnt128d_rd_valid_start = indicator_pos_edge | indicator_neg_edge;
assign cnt128d_rd_valid_stop = (cnt128d_rd[5:0] == 63) ? 1'b1 : 1'b0;
always @(posedge sclk or negedge rstn)
if (!rstn) cnt128d_rd_valid <= #1 1'b0;
else if (cnt128d_rd_valid_start) cnt128d_rd_valid <= #1 1'b1;
else if (cnt128d_rd_valid_stop) cnt128d_rd_valid <= #1 1'b0;
// Read Mode Counter
always @(posedge sclk or negedge rstn)
if (!rstn) cnt128d_rd <= #1 1'b0;
else if (cnt128d_rd_valid) cnt128d_rd <= #1 cnt128d_rd + 1;
assign rd_ADDR = {cnt128d_rd[6], cnt128d_rd[2:0], cnt128d_rd[5:3]};
assign rd_CSN = ~cnt128d_rd_valid;
// Output
always @(posedge sclk or negedge rstn)
if (!rstn) mem_valid <= #1 1'b0;
else mem_valid <= #1 cnt128d_rd_valid;
assign #1 mem_data = rd_DATA[N-1:0];
// synopsys translate_off
// <<<------------- DUMP Section
/*
// 2D FHT OUTPUT DUMP DATA
parameter MEM_TRPS_DPSRAM_FILE = "./result/mem_trps_dpsram.txt";
integer mem_trps_dpsram_dump;
initial mem_trps_dpsram_dump = $fopen(MEM_TRPS_DPSRAM_FILE);
always @(posedge sclk)
if (mem_valid) $fdisplay(mem_trps_dpsram_dump,"%h",mem_data);
*/
// synopsys translate_on
endmodule
| 6.881801 |
module signed_mult_const_asic (
rstn,
clk,
valid,
a,
p
);
parameter N = 8;
input rstn;
input clk;
input valid;
input [N-1:0] a; // variable - positive/negative
output [N : 0] p; // product output
// FHT constant
//wire [8:0] mult_constant; // always positive
//assign mult_constant = 9'd362;
parameter mult_constant = 9'd362;
reg [N-1:0] a_FF;
always @(posedge clk)
if (!rstn) a_FF <= #1 0;
else if (valid) a_FF <= #1 a;
// Convert into 2's complement if (a_FF) is negative
wire [N-1:0] b;
assign b = a_FF[N-1] ? {~a_FF[N-1:0] + {{N - 1{1'b0}}, 1'b1}} : a_FF[N-1:0];
// Multiply 2 positive numbers
// b[N-2:0] * mult_constant[8:0]
// output result mult_wo_sign
// N-2+1 - number of (b) bits
// 8+1 - number of mult_constant bits
// N-2+1+8+1 - number of bits on the output
// = N+8 = [N+7:0]
wire [N+7:0] mult_wo_sign; // mult without sign
assign mult_wo_sign = b[N-2:0] * mult_constant;
// Divided by 256 - [N+7-8:0] = [N-1:0]
wire [N-1:0] div256; // divided 256
assign div256 = mult_wo_sign >> 8;
assign p = a_FF[N-1] ? {1'b1, {~div256[N-1:0] + {{N - 1{1'b0}}, 1'b1}}} : {1'b0, div256[N-1:0]};
endmodule
| 7.218537 |
module signed_mult_const_fpga (
rstn,
clk,
valid,
a,
p
);
parameter N = 8;
input rstn;
input clk;
input valid;
input signed [N-1:0] a; // variable - positive/negative
output signed [N : 0] p; // product output
// FHT constant
// wire [8:0] mult_constant; // always positive
// assign mult_constant = 9'd362;
//wire signed [17:0] mult_constant; // always positive
//assign mult_constant = {1'b0, 17'd92681};
parameter mult_constant = {1'b0, 17'd92681};
reg signed [N-1:0] a_FF;
always @(posedge clk)
if (!rstn) a_FF <= #1 0;
else if (valid) a_FF <= #1 a;
wire signed [(16+1)+N-1:0] p_tmp = $signed(a_FF) * $signed(mult_constant);
//assign p = p_tmp[(16+1)+N-1:16];// >> 16;
assign p = p_tmp >> 16;
endmodule
| 7.218537 |
module: two_d_filter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module two_d_filter_tb_v;
// Inputs
reg aclr;
reg data_valid_in;
reg clk;
//reg clken;
reg [8:0] coef1_1;
reg [8:0] coef1_2;
reg [8:0] coef1_3;
reg [8:0] coef2_1;
reg [8:0] coef2_2;
reg [8:0] coef2_3;
reg [8:0] coef3_1;
reg [8:0] coef3_2;
reg [8:0] coef3_3;
reg [29:0] data;
//reg result;
// Outputs
wire [29:0] row1_1;
wire [29:0] row1_2;
wire [29:0] row1_3;
wire [29:0] row2_1;
wire [29:0] row2_2;
wire [29:0] row2_3;
wire [29:0] row3_1;
wire [29:0] row3_2;
wire [29:0] row3_3;
wire data_valid_out;
// Instantiate the Unit Under Test (UUT)
two_d_filter uut (
.aclr(aclr),
.data_valid_in(data_valid_in),
.clk(clk),
//.clken(clken),
.coef1_1(coef1_1),
.coef1_2(coef1_2),
.coef1_3(coef1_3),
.coef2_1(coef2_1),
.coef2_2(coef2_2),
.coef2_3(coef2_3),
.coef3_1(coef3_1),
.coef3_2(coef3_2),
.coef3_3(coef3_3),
.data(data),
.row1_1(row1_1),
.row1_2(row1_2),
.row1_3(row1_3),
.row2_1(row2_1),
.row2_2(row2_2),
.row2_3(row2_3),
.row3_1(row3_1),
.row3_2(row3_2),
.row3_3(row3_3),
.data_valid_out(data_valid_out)
//.result(result)
);
parameter p=6;//ʱ
parameter a=12;//ʱ
parameter q=3;//ʱ
parameter v=10;//ʱ
parameter column_size=12;
parameter row_size=16;
//parameter column_size=1280,row_size=1024;
reg [10:0] i,j;
initial begin
// Initialize Inputs
aclr = 0;
data_valid_in = 0;
clk = 0;
//clken = 0;
coef1_1 = 0;
coef1_2 = 0;
coef1_3 = 0;
coef2_1 = 0;
coef2_2 = 0;
coef2_3 = 0;
coef3_1 = 0;
coef3_2 = 0;
coef3_3 = 0;
data = 0;
//data_valid_out = 0;
//result = 0;
// Wait 100 ns for global reset to finish
#100;
aclr = 1;
// Add stimulus here
for(i=1;i<=p;i=i+1)//p=6
begin
# 20;
data_valid_in = 0;
end
for(i=1;i<=row_size/2-1;i=i+1)
begin
for(j=1;j<=a/2;j=j+1)
begin
#20;
data_valid_in = 1;
data=2*j-1+2*a*(i-1);
#20;
data_valid_in = 0;
end
repeat(q)
begin
#20;
data_valid_in = 0;
data=0;
end
end
for(j=1;j<=a/2;j=j+1)
begin
#20;
data_valid_in = 1;
data=2*j-1+2*a*(row_size/2-1);
#20;
data_valid_in = 0;
end
repeat(p)
begin
# 20;
data_valid_in = 0;
data=0;
end
repeat(v)
begin
# 20;
data_valid_in = 0;
data=0;
end//һ֡ͼ
#120
repeat(p)
begin
# 20;
data_valid_in = 0;
data=0;
end
for(i=1;i<=row_size/2-1;i=i+1)
begin
for(j=1;j<=a/2;j=j+1)
begin
#20;
data_valid_in = 1;
data=2*j-1+2*a*(i-1);
#20;
data_valid_in = 0;
end
repeat(q)
begin
#20;
data_valid_in = 0;
data=0;
end
end
end
always #10 clk=~clk;
endmodule
| 6.534878 |
module two_flop_cdc (
input wire i_clk,
input wire i_sig,
output wire o_sig
);
reg [1:0] cdc;
always @(posedge i_clk) begin
cdc[0] <= i_sig;
cdc[1] <= cdc[0];
end
assign o_sig = cdc[1];
endmodule
| 7.25602 |
module D_FF (
Q,
D,
CLK
);
input D, CLK;
output Q;
reg Q, NQ;
initial begin
Q = 0;
NQ = 0;
end
always @(posedge CLK) begin
Q <= D;
NQ <= ~D;
end
endmodule
| 7.013014 |
module two_four_decoder (
input [1:0] x,
output reg [3:0] y
);
always @(x) begin
case (x)
0: y = 4'b0001;
1: y = 4'b0010;
2: y = 4'b0100;
3: y = 4'b1000;
endcase
end
endmodule
| 6.560706 |
module two_ip_tb;
wire t_p, t_q;
reg [1:0] inTest;
gate dut (
.a(inTest[1]),
.b(inTest[0]),
.p(t_p),
.q(t_q)
);
initial begin
$monitor(inTest[0], inTest[1], t_p, t_q);
inTest = 2'b00;
#60 inTest = 2'b01;
#60 inTest = 2'b10;
#60 inTest = 2'b11;
#60 $finish;
end
endmodule
| 6.986443 |
module two_level_branch_predictor (
clk,
reset_n,
input_ip,
output_prediction,
input_taken
);
input clk;
input reset_n;
input [63:0] input_ip;
input [0:0] input_taken;
output [0:0] output_prediction;
reg [0:0] output_reg;
reg [1 : 0] branch_table[0:255];
reg [1 : 0] state;
reg [7:0] prev_index;
reg [7:0] BHSR;
integer i;
// you can add more variables
assign output_prediction = output_reg;
initial begin
BHSR <= 8'b0;
output_reg <= 0;
state <= 2'b00;
prev_index <= 8'b0;
for (i = 0; i < 256; i = i + 1) begin
branch_table[i] = 2'b00;
end
end
always @(*) begin
case (state)
2'b00: output_reg = 0;
2'b01: output_reg = 0;
2'b10: output_reg = 1;
2'b11: output_reg = 1;
endcase
end
always @(negedge reset_n) begin
// reset all state asynchronously
BHSR <= 8'b0;
output_reg <= 0;
state <= 2'b00;
prev_index <= 8'b0;
for (i = 0; i < 256; i = i + 1) begin
branch_table[i] = 2'b00;
end
$display("reset_n activated");
end
always @(posedge clk) begin
state = branch_table[BHSR];
case (branch_table[prev_index])
2'b00: branch_table[prev_index] = input_taken ? 2'b01 : 2'b00;
2'b01: branch_table[prev_index] = input_taken ? 2'b10 : 2'b00;
2'b10: branch_table[prev_index] = input_taken ? 2'b11 : 2'b01;
2'b11: branch_table[prev_index] = input_taken ? 2'b11 : 2'b10;
endcase
prev_index = BHSR;
BHSR = BHSR << 1;
BHSR[0] = input_taken;
end
endmodule
| 7.330718 |
module two_level_CLA #(
parameter WIDTH_0 = 2,
parameter WIDTH_1 = 2,
parameter GROUP_COUNT = 2
) (
input carry_in,
input [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0] x,
input [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0] y,
output [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0] z,
output carry_out
);
wire [GROUP_COUNT * WIDTH_1 - 1 : 0] p_temp, g_temp;
wire [GROUP_COUNT * WIDTH_1 : 0] c_temp;
assign c_temp[0] = carry_in;
generate
genvar i;
genvar j;
for (i = 0; i <= GROUP_COUNT * WIDTH_1 - 1; i = i + 1) begin : stage
carry_lookahead_adder #(
.WIDTH(WIDTH_0)
) i_CLA (
.carry_in (c_temp[i]),
.x (x[(i+1)*WIDTH_0-1 : i*WIDTH_0]),
.y (y[(i+1)*WIDTH_0-1 : i*WIDTH_0]),
.z (z[(i+1)*WIDTH_0-1 : i*WIDTH_0]),
.group_propagate(p_temp[i]),
.group_generate (g_temp[i]),
.carry_out ()
);
end
for (j = 0; j <= GROUP_COUNT - 1; j = j + 1) begin : clg_stage
carry_lookahead_generator #(
.WIDTH(WIDTH_1)
) i_CLG (
.carry_in (c_temp[WIDTH_1*j]),
.generate_in (g_temp[WIDTH_1*(j+1)-1 : WIDTH_1*j]),
.propagate_in (p_temp[WIDTH_1*(j+1)-1 : WIDTH_1*j]),
.carry (c_temp[WIDTH_1*(j+1) : WIDTH_1*j+1]),
.group_propagate(),
.group_generate ()
);
end
endgenerate
assign carry_out = c_temp[GROUP_COUNT*WIDTH_1];
endmodule
| 8.848434 |
module two_mux (
X,
Y,
Z,
CTRL
);
//parameter definitions
parameter N = 32;
input wire [N-1:0] X, Y;
output wire [N-1:0] Z;
input wire CTRL;
//port definitions - customize for different bit widths
assign Z = CTRL ? Y : X;
endmodule
| 8.861062 |
module two_mux_4_to_1 #(
parameter DELAY = 10
) (
input s1_n,
s2_n,
a1,
a0,
d3_1,
d2_1,
d1_1,
d0_1,
d3_2,
d2_2,
d1_2,
d0_2,
output y1,
y2
);
reg y1_reg, y2_reg;
always @(*)
case ({
a1, a0
})
00: begin
y1_reg = d0_1;
y2_reg = d0_2;
end
00: begin
y1_reg = d1_1;
y2_reg = d1_2;
end
00: begin
y1_reg = d2_1;
y2_reg = d2_2;
end
00: begin
y1_reg = d3_1;
y2_reg = d3_2;
end
endcase
assign #DELAY y1 = (s1_n) ? 1'b0 : y1_reg;
assign #DELAY y2 = (s2_n) ? 1'b0 : y2_reg;
endmodule
| 6.679689 |
module two_port ( /*autoport*/
//output
rddata1,
rddata2,
ram_address,
ram_data_o,
ram_wr_n,
ram_rd_n,
dataenable,
//input
rst_n,
clk2x,
address1,
wrdata1,
dataenable1,
rd1,
wr1,
address2,
wrdata2,
dataenable2,
rd2,
wr2,
ram_data_i
);
input wire rst_n;
input wire clk2x;
input wire [31:0] address1;
input wire [31:0] wrdata1;
output reg [31:0] rddata1;
input wire [3:0] dataenable1;
input wire rd1;
input wire wr1;
input wire [31:0] address2;
input wire [31:0] wrdata2;
output reg [31:0] rddata2;
input wire [3:0] dataenable2;
input wire rd2;
input wire wr2;
output reg [31:0] ram_address;
input wire [31:0] ram_data_i;
output wire [31:0] ram_data_o;
output reg ram_wr_n;
output reg ram_rd_n;
output reg [3:0] dataenable;
reg [ 3:0] state;
reg [31:0] wrbuf;
assign ram_data_o = wrbuf;
always @(posedge clk2x or negedge rst_n) begin
if (!rst_n) begin
// reset
state <= 4'b1;
rddata1 <= 32'b0;
ram_wr_n <= 1'b1;
ram_rd_n <= 1'b1;
end else begin
state <= {state[2:0], state[3]};
if (state[0]) begin
ram_address <= address1;
wrbuf <= wrdata1;
ram_wr_n <= ~wr1;
ram_rd_n <= ~rd1;
dataenable <= dataenable1;
end else if (state[1]) begin
ram_address <= address2;
wrbuf <= wrdata2;
rddata1 <= ram_data_i;
ram_wr_n <= ~wr2;
ram_rd_n <= ~rd2;
dataenable <= dataenable2;
end else begin
ram_wr_n <= 1'b1;
ram_rd_n <= 1'b1;
if (state[2]) begin
rddata2 <= ram_data_i;
end
end
end
end
endmodule
| 6.729025 |
module two_port_ram_sclk #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 13
) (
input clk,
// Port A for write
input en_a,
input [ADDR_WIDTH-1:0] addr_a,
input [DATA_WIDTH-1:0] data,
// Port B for read
input en_b,
input [ADDR_WIDTH-1:0] addr_b,
output reg [DATA_WIDTH-1:0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[0:2**ADDR_WIDTH-1];
// Port A for write
always @(posedge clk) begin
if (en_a) begin
ram[addr_a] <= data;
end
end
// Port B for read
always @(posedge clk) begin
if (en_b) begin
q <= ram[addr_b];
end else begin
q <= 0;
end
end
endmodule
| 8.716654 |
module main (
clk
);
input clk;
wire all_shared, is_sharedA, is_sharedB;
wire ND_inA, ND_inB, ndA, ndB;
wire master_outA, master_outB;
wire master_inA, master_inB;
wire inv_outA, inv_outB, invalidate;
wire mem_served;
wire info_availA, info_availB;
wire bus_reqA, bus_reqB;
wire bus_ackA, bus_ackB;
wire [2:0] snoop_typeA, snoop_typeB;
wire [2:0] shared_snoop;
pcache pcacheA (
clk,
shared_snoop,
is_snoop,
master_inA,
ND_inA,
bus_ackA,
all_shared,
mem_served,
invalidate,
inv_outA,
snoop_typeA,
bus_reqA,
master_outA,
is_sharedA,
info_availA
);
pcache pcacheB (
clk,
shared_snoop,
is_snoop,
master_inB,
ND_inB,
bus_ackB,
all_shared,
mem_served,
invalidate,
inv_outB,
snoop_typeB,
bus_reqB,
master_outB,
is_sharedB,
info_availB
);
assign all_shared = (is_sharedA && is_sharedB);
// All the proceesors are in Shared state
assign ND_inA = ndA && !bus_ackA;
assign ND_inB = (master_outA) ? ND_inA : (ndB && !bus_ackB);
// Non deter. B if proc. A is not Master
assign master_inA = 0;
assign master_inB = master_outA;
assign ndA = {0, 1};
assign ndB = {0, 1};
assign mem_served = !(info_availA || info_availB);
// if no proc. has info, Mem supplies
arbiter bus_arbiter (
clk,
bus_reqA,
bus_reqB,
snoop_typeA,
snoop_typeB,
inv_outA,
inv_outB,
bus_ackA,
bus_ackB,
is_snoop,
shared_snoop,
invalidate
);
endmodule
| 7.779865 |
module main (
clk
);
input clk;
wire all_shared, is_sharedA, is_sharedB;
wire ND_inA, ND_inB, ndA, ndB;
wire master_outA, master_outB;
wire master_inA, master_inB;
wire inv_outA, inv_outB, invalidate;
wire mem_served;
wire info_availA, info_availB;
wire bus_reqA, bus_reqB;
wire bus_ackA, bus_ackB;
wire [2:0] snoop_typeA, snoop_typeB;
wire [2:0] shared_snoop;
wire is_snoop;
pcache pcacheA (
clk,
shared_snoop,
is_snoop,
master_inA,
ND_inA,
bus_ackA,
all_shared,
mem_served,
invalidate,
inv_outA,
snoop_typeA,
bus_reqA,
master_outA,
is_sharedA,
info_availA
);
pcache pcacheB (
clk,
shared_snoop,
is_snoop,
master_inB,
ND_inB,
bus_ackB,
all_shared,
mem_served,
invalidate,
inv_outB,
snoop_typeB,
bus_reqB,
master_outB,
is_sharedB,
info_availB
);
assign all_shared = (is_sharedA && is_sharedB);
// All the proceesors are in Shared state
assign ND_inA = ndA && !bus_ackA;
assign ND_inB = (master_outA == 1'b1) ? ND_inA : (ndB & !bus_ackB);
// Non deter. B if proc. A is not Master
assign master_inA = 0;
assign master_inB = master_outA;
assign ndA = {0, 1};
assign ndB = {0, 1};
assign mem_served = !(info_availA || info_availB);
// if no proc. has info, Mem supplies
arbiter bus_arbiter (
clk,
bus_reqA,
bus_reqB,
snoop_typeA,
snoop_typeB,
inv_outA,
inv_outB,
bus_ackA,
bus_ackB,
is_snoop,
shared_snoop,
invalidate
);
endmodule
| 7.779865 |
module two_stage_mult (
input [15:0] a,
input [15:0] b,
output [31:0] out,
input clk
);
logic [31:0] register;
logic [31:0] register2;
always @(posedge clk) begin
register <= a * b;
register2 <= register;
end
assign out = register2;
endmodule
| 7.479731 |
module Two_to_Four_MUX45bit (
R0,
R1,
R2,
R3,
QA,
Q
);
input [45:0] R0; //input for each register that could propogate to the output
input [45:0] R1;
input [45:0] R2;
input [45:0] R3;
input [1:0] QA; //address of the selected register to propogate to the output
output reg [45:0] Q; //output of the mux
always @* begin
case (QA)
2'b00: Q = R0;
2'b01: Q = R1;
2'b10: Q = R2;
2'b11: Q = R3;
endcase
end
endmodule
| 7.552459 |
module two_to_one #(
parameter WORD_LEN = 33
) (
input clk,
arst,
input [2*WORD_LEN-1:0] din,
input din_valid,
output din_ready,
output [WORD_LEN-1:0] dout,
input dout_ready,
output dout_valid
);
reg [1:0] holding; // holding 0..2 words
reg [2*WORD_LEN-1:0] storage;
assign din_ready = (holding == 2'b0) || ((holding == 2'b1) && dout_ready);
assign dout_valid = (|holding);
assign dout = storage[WORD_LEN-1:0];
always @(posedge clk or posedge arst) begin
if (arst) begin
storage <= 0;
holding <= 0;
end else begin
if (din_ready & din_valid) begin
// if we are reloading it goes to 2 blocks available
storage <= din;
holding <= 2'b10;
end else begin
// not reloading
// if the output side is ready lose one block
if (dout_valid & dout_ready) begin
holding <= holding - 1'b1;
storage <= {{(WORD_LEN) {1'b0}}, storage[2*WORD_LEN-1:WORD_LEN]};
end
end
end
end
endmodule
| 7.859118 |
module two_to_one_MUX (
input wire A,
input wire B,
input wire S,
output wire z
// output wire cout
);
//assign z = (A&~S) | (B&S);
assign z = (S == 1'b0) ? A : (S == 1'b1) ? B : 1'bX;
endmodule
| 7.90739 |
module two_to_one_mux_testbench;
reg a, b, s;
wire y;
two_to_one_mux m (
a,
b,
s,
y
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, two_to_one_mux_testbench);
end
initial begin
$monitor(a, b, s, y);
s = 1'b0;
a = 1'b0;
b = 1'b0;
#5 a = 1'b0;
b = 1'b1;
#5 a = 1'b1;
b = 1'b0;
#5 a = 1'b1;
b = 1'b1;
#5 s = 1'b1;
a = 1'b0;
b = 1'b0;
#5 a = 1'b0;
b = 1'b1;
#5 a = 1'b1;
b = 1'b0;
#5 a = 1'b1;
b = 1'b1;
#5;
end
endmodule
| 7.326213 |
module two_wide_double_buf #(
DATA_WIDTH = 8,
ADDR_WIDTH = 6
) (
input i_clk,
input i_resetn,
// to avoid conflicts we write two values at once at sequential addresses
input [DATA_WIDTH-1 : 0] wdata0,
wdata1,
// input [ADDR_WIDTH-1 : 0] waddr,
input wen,
// output wsync, // sync the writer writes
// reading
output [DATA_WIDTH-1 : 0] rdata0,
rdata1,
// output [ADDR_WIDTH-1 : 0] raddr,
output reg rsync // sync the reader reads
);
// create internal signals
// double buffer
reg [DATA_WIDTH-1 : 0] ram_buf[0:1][0 : 2**ADDR_WIDTH - 1];
// output buffers
reg [DATA_WIDTH-1 : 0] reg_rdata0, reg_rdata1;
// internal waddr and raddr
reg [ADDR_WIDTH-1 : 0] waddr, raddr;
// which page of memory to read/write from
reg wpage;
wire rpage;
// ensure that the read and write pages are opposite
assign rpage = ~wpage;
// assign outputs
assign rdata0 = reg_rdata0;
assign rdata1 = reg_rdata1;
// handle wpage
always @(posedge i_clk) begin
if (~i_resetn) begin
wpage <= 0;
end else begin
if (waddr == 2 ** ADDR_WIDTH - 2 && wen) begin
// we're at the last write address and are writing
wpage <= ~wpage;
end
end
end
// handle incrementing waddr
always @(posedge i_clk) begin
if (~i_resetn) begin
// reset raddr
waddr <= 0;
end else begin
if (wen) begin
// should wrap once it's full?
waddr <= waddr + 2;
end
end
end
// handle writing to the ram
integer i;
always @(posedge i_clk) begin
if (~i_resetn) begin
// reset the buffers
for (i = 0; i < 2 ** ADDR_WIDTH; i = i + 1) begin
ram_buf[wpage][i] <= 0;
ram_buf[rpage][i] <= 0;
end
end else begin
if (wen) begin
// write to the buffer if the master enables writes
ram_buf[wpage][waddr+0] <= wdata0;
ram_buf[wpage][waddr+1] <= wdata1;
end
end
end
// handle incrementing raddr
always @(posedge i_clk) begin
if (~i_resetn) begin
// reset raddr
raddr <= 0;
end else begin
if (rsync) begin
// should wrap once full, write once we're ready to write
raddr <= raddr + 2;
end
end
end
// handle rsync
// rsync should go high once we're done
always @(posedge i_clk) begin
if (~i_resetn) begin
rsync <= 0;
end else begin
if (waddr == 2 ** ADDR_WIDTH - 2 && wen && ~rsync) begin
// if rsync is low and we finished writing a block, set high
rsync <= 1;
end else if (raddr == 2 ** ADDR_WIDTH - 2 && rsync && waddr < 2 ** ADDR_WIDTH - 2) begin
// if we're about to finish reading, but not done writing, clear
rsync <= 0;
end else begin
// if we're about to finish writing and rsync is high, stay high
rsync <= rsync;
end
end
end
// handle reading from the ram
always @(posedge i_clk) begin
reg_rdata0 <= ram_buf[rpage][raddr+0];
reg_rdata1 <= ram_buf[rpage][raddr+1];
end
endmodule
| 8.283039 |
module two_complement (
in,
out
);
input wire [7:0] in;
output wire [7:0] out;
assign out = ~in + 8'b00000001;
endmodule
| 7.955961 |
module tx #(
parameter data_width = 8, //数据宽度
parameter test = 2, //偶校验
parameter stop_width = 1
) //结束符宽度1个高电平
(
input tx_clk,
input rst_n,
input [data_width-1:0] data_in,
input enable,
output reg tx_out
);
localparam IDLE = 3'b000;
localparam S1 = 3'b001; //发送低电平
localparam S2 = 3'b010;
localparam S3 = 3'b011;
localparam S4 = 3'b100;
reg [3:0] state, nstate;
reg [3:0] count_data; //输出数据位计数器
reg [1:0] count_stop; //结束符长度计数器
reg check_bit;
//状态机第一段
always @(posedge tx_clk or negedge rst_n)
if (!rst_n) state <= IDLE;
else state <= nstate;
//状态机第二段
always @(*) begin
case (state)
IDLE: nstate = (enable ? S1 : IDLE); //注意enable的时序
S1: nstate = S2;
S2:
nstate = (test == 'b0 && count_data == (data_width - 1)? S4 : count_data == (data_width - 1)? S3 : S2);
S3: nstate = S4;
S4:
nstate = count_stop == (stop_width - 1) ? IDLE : S4; //注意count_data和count_stop的时序
default: nstate = IDLE;
endcase
end
//状态机的输出
always @(*)
case (state)
IDLE: tx_out = 1'b1;
S1: tx_out = 1'b0;
S2: tx_out = data_in[count_data]; //由低位到高位依次输出
S3: tx_out = check_bit;
S4: tx_out = 1'b1;
default: tx_out = 1'b1;
endcase
//S2状态，输出数据位的计数器
always @(posedge tx_clk or negedge rst_n)
if (!rst_n) count_data <= 4'b0000;
else if (count_data < data_width && state == S2) count_data <= count_data + 1'b1;
else count_data <= 4'b0000;
//UART的奇偶校验位的生成
always @(posedge tx_clk or negedge rst_n) begin
if (!rst_n) check_bit <= 1'b0;
else if (state == S2)
case (test)
2'b00: check_bit <= 1'b0;
2'b01: check_bit <= !(^data_in);
2'b10: check_bit <= (^data_in);
default: check_bit <= 1'b0;
endcase
else check_bit <= check_bit;
end
//UART停止位计数器
always @(posedge tx_clk or negedge rst_n) begin
if (!rst_n) count_stop <= 2'b00;
else if (state == S4 && count_stop < stop_width) count_stop <= count_stop + 1'b1;
else count_stop <= 2'b00;
end
endmodule
| 7.70951 |
module tx20_io10 (
input I_clk, // NOT USED
input I_rst_n, // NOT USED
input [1:0] I_sel, // NOT USED
input I_pll_areset,
input I_tx_inclock,
input [9:0] i0_p,
input [9:0] i1_p,
input [9:0] i2_p,
input [9:0] i3_p,
input [9:0] i4_p,
input [9:0] i5_p,
input [9:0] i6_p,
input [9:0] i7_p,
input [9:0] i8_p,
input [9:0] i9_p,
input [9:0] i10_p,
input [9:0] i11_p,
input [9:0] i12_p,
input [9:0] i13_p,
input [9:0] i14_p,
input [9:0] i15_p,
input [9:0] i16_p,
input [9:0] i17_p,
input [9:0] i18_p,
input [9:0] i19_p,
output [19:0] O_tx20_out,
output O_tx_locked,
output O_tx_outclock,
output O_tx_coreclock
);
wire [199:0] tx_in;
`ifdef BOARD_7406
s4_lvds_rx60
`else
s3_lvds_rx60
`endif
lvds_tx20_inst(
.pll_areset (I_pll_areset),
.tx_in (tx_in),
.tx_inclock (I_tx_inclock),
.tx_coreclock (O_tx_coreclock),
.tx_locked (O_tx_locked),
.tx_out (O_tx20_out),
.tx_outclock (O_tx_outclock)
);
assign tx_in[9:0] = i0_p;
assign tx_in[19:10] = i1_p;
assign tx_in[29:20] = i2_p;
assign tx_in[39:30] = i3_p;
assign tx_in[49:40] = i4_p;
assign tx_in[59:50] = i5_p;
assign tx_in[69:60] = i6_p;
assign tx_in[79:70] = i7_p;
assign tx_in[89:80] = i8_p;
assign tx_in[99:90] = i9_p;
assign tx_in[109:100] = i10_p;
assign tx_in[119:110] = i11_p;
assign tx_in[129:120] = i12_p;
assign tx_in[139:130] = i13_p;
assign tx_in[149:140] = i14_p;
assign tx_in[159:150] = i15_p;
assign tx_in[169:160] = i16_p;
assign tx_in[179:170] = i17_p;
assign tx_in[189:180] = i18_p;
assign tx_in[199:190] = i19_p;
endmodule
| 6.847858 |
module tx20_io40 (
input I_clk, // NOT USED
input I_rst_n, // NOT USED
input [1:0] I_sel, // NOT USED
input I_pll_areset,
input I_tx_inclock,
input [9:0] i0_p,
input [9:0] i1_p,
input [9:0] i2_p,
input [9:0] i3_p,
input [9:0] i4_p,
input [9:0] i5_p,
input [9:0] i6_p,
input [9:0] i7_p,
input [9:0] i8_p,
input [9:0] i9_p,
input [9:0] i10_p,
input [9:0] i11_p,
input [9:0] i12_p,
input [9:0] i13_p,
input [9:0] i14_p,
input [9:0] i15_p,
input [9:0] i16_p,
input [9:0] i17_p,
input [9:0] i18_p,
input [9:0] i19_p,
output [19:0] O_tx20_out,
output O_tx_locked,
output O_tx_outclock,
output O_tx_coreclock
);
wire [199:0] tx_in;
wire tx_locked;
generate
begin : L0
genvar i;
for (i=o; i<=19; i = i+1)
begin u
reg_mux_40_10 reg_mux_40_10_inst[i] (
.clk (I_clk),
.rst (I_rst_n),
.sel (I_sel),
.tx_locked (tx_locked),
.i_p (i[i]_p),
.o_p (tx_in[(9+(i*10)):(10*i)]),
);
end // for (i=o; i<=59; i = i+1)
end // block: L0
endgenerate
`ifdef BOARD_7406
s4_lvds_rx60
`else
s3_lvds_rx60
`endif
lvds_tx20_inst(
.pll_areset (I_pll_areset),
.tx_in (tx_in),
.tx_inclock (I_tx_inclock),
.tx_coreclock (O_tx_coreclock),
.tx_locked (tx_locked),
.tx_out (O_tx20_out),
.tx_outclock (O_tx_outclock)
);
assign O_tx_locked = tx_locked;
endmodule
| 7.622132 |
module tx_tb ();
reg stm_clk, stm_rst, stm_en, stm_en_tx;
reg [7:0] stm_data;
reg [4:0] i;
reg [9:0] result;
wire tbr_mon, TxD_mon;
tx tx0 (
.clk(stm_clk),
.rst(stm_rst),
.data(stm_data),
.en(stm_en),
.en_tx(stm_en_tx),
.tbr(tbr_mon),
.TxD(TxD_mon)
);
always #5 stm_clk <= ~stm_clk;
initial begin
stm_clk = 0;
stm_rst = 1;
stm_en = 0;
stm_en_tx = 0;
stm_data = 8'hE3;
result = 10'h000;
repeat (2) begin
@(posedge stm_clk);
end
stm_rst = 0;
stm_en_tx = 1;
@(posedge stm_clk);
stm_en_tx = 0;
repeat (6) begin
@(posedge stm_clk);
end
if (tbr_mon) begin
$display("tbr is not set low");
$stop();
end
while (~tbr_mon) begin
result = {TxD_mon, result[9:1]};
for (i = 0; i < 16; i = i + 1) begin
stm_en = 1;
@(posedge stm_clk);
stm_en = 0;
repeat (5) @(posedge stm_clk);
end
end
// result = {TxD_mon, result[9:1]};
$display("Here is the end result: %h", result);
$stop();
end
endmodule
| 6.93599 |
module tx9_io40 (
input I_clk, // NOT USED
input I_rst_n, // NOT USED
input [1:0] I_sel, // NOT USED
input I_pll_areset,
input I_tx_inclock,
input [39:0] i0_p,
input [39:0] i1_p,
input [39:0] i2_p,
input [39:0] i3_p,
input [39:0] i4_p,
input [39:0] i5_p,
input [39:0] i6_p,
input [39:0] i7_p,
input [39:0] i8_p,
output [8:0] O_tx9_out,
output O_tx_locked,
output O_tx_outclock,
output O_tx_coreclock
);
wire [89:0] tx_in;
wire tx_locked;
reg_mux_40_10 reg_mux_40_10_inst0 (
.clk (I_clk),
.rst (I_rst_n),
.sel (I_sel),
.tx_locked (tx_locked),
.i_p (i0_p),
.o_p (tx_in[9:0])
);
reg_mux_40_10 reg_mux_40_10_inst1 (
.clk (I_clk),
.rst (I_rst_n),
.sel (I_sel),
.tx_locked (tx_locked),
.i_p (i1_p),
.o_p (tx_in[19:10])
);
reg_mux_40_10 reg_mux_40_10_inst2 (
.clk (I_clk),
.rst (I_rst_n),
.sel (I_sel),
.tx_locked (tx_locked),
.i_p (i2_p),
.o_p (tx_in[29:20])
);
reg_mux_40_10 reg_mux_40_10_inst3 (
.clk (I_clk),
.rst (I_rst_n),
.sel (I_sel),
.tx_locked (tx_locked),
.i_p (i3_p),
.o_p (tx_in[39:30])
);
reg_mux_40_10 reg_mux_40_10_inst4 (
.clk (I_clk),
.rst (I_rst_n),
.sel (I_sel),
.tx_locked (tx_locked),
.i_p (i4_p),
.o_p (tx_in[49:40])
);
reg_mux_40_10 reg_mux_40_10_inst5 (
.clk (I_clk),
.rst (I_rst_n),
.sel (I_sel),
.tx_locked (tx_locked),
.i_p (i5_p),
.o_p (tx_in[59:50])
);
reg_mux_40_10 reg_mux_40_10_inst6 (
.clk (I_clk),
.rst (I_rst_n),
.sel (I_sel),
.tx_locked (tx_locked),
.i_p (i6_p),
.o_p (tx_in[69:60])
);
reg_mux_40_10 reg_mux_40_10_inst7 (
.clk (I_clk),
.rst (I_rst_n),
.sel (I_sel),
.tx_locked (tx_locked),
.i_p (i7_p),
.o_p (tx_in[79:70])
);
reg_mux_40_10 reg_mux_40_10_inst8 (
.clk (I_clk),
.rst (I_rst_n),
.sel (I_sel),
.tx_locked (tx_locked),
.i_p (i8_p),
.o_p (tx_in[89:80])
);
//
`ifdef BOARD_7406
s4_lvds_tx9
`else
s3_lvds_tx9
`endif
lvds_tx9_inst(
.pll_areset (I_pll_areset),
.tx_in (tx_in),
.tx_inclock (I_tx_inclock),
.tx_coreclock (O_tx_coreclock),
.tx_locked (tx_locked),
.tx_out (O_tx9_out),
.tx_outclock (O_tx_outclock)
);
assign O_tx_locked = tx_locked;
endmodule
| 6.744913 |
module TXBlock (
CONTROL,
DATA,
RST,
CLK,
STATUS,
LINE_OUT
);
parameter BAUD = 9600;
// states
parameter START = 1;
parameter WAIT = 2;
parameter TxBIT = 3;
// statuses
parameter RDY = 0;
parameter BSY = 255;
// control commands
parameter NOP = 0;
parameter SND = 255;
input [7:0] CONTROL, DATA;
input CLK, RST;
output reg [7:0] STATUS;
output reg LINE_OUT;
reg [7:0] local_data;
reg [3:0] incr;
reg [2:0] state = START;
reg bg_rst;
wire bg_end;
BaudGenerator #(
.BAUD (BAUD),
.SPLIT(0)
) bg (
.RST(bg_rst),
.CLK(CLK),
.OUT(bg_end)
);
always @(posedge CLK) begin
if (RST) begin
LINE_OUT <= 1;
state <= START;
end else begin
case (state)
START: begin
LINE_OUT <= 1;
STATUS <= RDY;
bg_rst <= 1;
state <= WAIT;
end
WAIT: begin
if (CONTROL == SND) begin
bg_rst <= 0;
state <= TxBIT;
LINE_OUT <= 0; // send a start bit
local_data <= DATA;
incr <= 0;
STATUS <= BSY;
end
end
TxBIT: begin
if (bg_end) begin
incr <= incr + 1;
if (incr >= 8) begin
LINE_OUT <= 1; // send a stop bit (longer than normal)
if (incr == 10) begin // will using 1/2 stop bit make a difference?
state <= START;
end
end else begin
LINE_OUT <= local_data[incr];
end
end
end
default: state <= START;
endcase
end
end
endmodule
| 7.917548 |
module: TXBlock
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TXBLockTest;
// Inputs
reg [7:0] CONTROL;
reg [7:0] DATA;
reg CLK;
// Outputs
wire [7:0] STATUS;
wire LINE_OUT;
// Instantiate the Unit Under Test (UUT)
TXBlock uut (
.CONTROL(CONTROL),
.DATA(DATA),
.CLK(CLK),
.STATUS(STATUS),
.LINE_OUT(LINE_OUT)
);
always
begin
CLK = 1;
#5;
CLK = 0;
#5;
end
initial begin
// Initialize Inputs
CONTROL = 0;
DATA = 0;
// Wait 100 ns for global reset to finish
#100;
DATA = 78;
#20;
CONTROL = 255;
#50;
if (STATUS == 255) begin
CONTROL = 0;
end
#2000;
// Add stimulus here
end
endmodule
| 7.383826 |
module txchar (
input wire clk, //-- System clock
input wire rstn, //-- Reset (active low)
output wire tx //-- Serial data output
);
//-- Serial Unit instantation
uart_tx #(
.BAUDRATE(`B115200) //-- Set the baudrate
) TX0 (
.clk(clk),
.rstn(rstn),
.data("A"), //-- Fixed character to transmit (always the same)
.start(1'b1), //-- Start signal always set to 1
.tx(tx)
); //-- Port ready not used
endmodule
| 7.244689 |
module txchar_tb ();
//-- Baudrate for the simulation
localparam BAUDRATE = `B115200;
//-- clock tics needed for sending one serial package
localparam SERIAL_CHAR = (BAUDRATE * 10);
//-- System clock
reg clk = 0;
//-- Transmission line
wire tx;
//-- Reset
reg rstn = 0;
//-- Instantiate the entity the character transmitter
txchar dut (
.clk (clk),
.rstn(rstn),
.tx (tx)
);
//-- Clock generator
always #0.5 clk <= ~clk;
initial begin
//-- File where to store the simulation
$dumpfile("txchar_tb.vcd");
$dumpvars(0, txchar_tb);
//-- Activate reset
#1 rstn <= 0;
//-- Disable the reset. The transmission begins!
#5 rstn <= 1;
//-- Wait for 3 characters and finish
#(SERIAL_CHAR * 3) $display("END of simulation");
$finish;
end
endmodule
| 8.333383 |
module txclkdivide (
reset,
oscclk,
trcal,
dr,
txclk
);
input reset, oscclk, dr;
input [9:0] trcal; // max: 1023
output txclk;
reg txclk;
reg [6:0] counter;
// trcal3 = 3 * trcal
wire [10:0] trcal2;
assign trcal2[10:1] = trcal;
assign trcal2[0] = 1'b0;
wire [11:0] trcal3;
assign trcal3 = trcal2 + trcal;
wire [11:0] dr1numerator;
assign dr1numerator = (11'd75 + trcal3); // max: 12 bits
wire [11:0] dr0numerator;
assign dr0numerator = (11'd4 + trcal); // max: 11 bits
wire [6:0] tempdivider;
assign tempdivider = dr ? ({1'b0, dr1numerator[11:7]}) : (dr0numerator[9:4]); // max dr0 = 64, dr1 = 24 -> 7 bits.
wire [6:0] divider;
assign divider = (tempdivider >= 7'd2) ? tempdivider : 7'd2;
always @(posedge oscclk or posedge reset) begin
if (reset) begin
txclk = 0;
counter = 0;
end else if (counter >= (divider - 1)) begin
txclk = 1;
counter = 0;
end else if (counter == ((divider - 1) >> 1)) begin
counter = counter + 7'd1;
txclk = 0;
end else begin
counter = counter + 7'd1;
end // ~reset
end // always
endmodule
| 6.827871 |
module txclkgenerator #(
parameter B = 9600, // Baud rate del dispositivo
F = 50000000, // Frecuencia del clock de la FPGA
N = 32 // Bits necesarios para el contador, 9 para 9600 y 5 para 115200
) (
input wire clk,
reset,
output wire clk_out
);
//signal declaration
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
// body
// register
always @(posedge clk, posedge reset)
if (reset) r_reg <= 0;
else r_reg <= r_next;
// next-state logic
assign r_next = (r_reg == 16 * 2 * F / (32 * B)) ? 0 : r_reg + 1;
// output logic
assign clk_out = (r_reg > 16 * F / (32 * B)) ? 1'b1 : 0'b0;
endmodule
| 7.021605 |
module tb_TxCore;
parameter PARITY = 1;
parameter CLK_PERIOD = 10; //should be %2
// Inputs
reg [7:0] dataIn;
reg loadDataIn;
reg [12:0] clocksPerBit;
reg stopBit2;
wire oddParity = 0; //if 1, parity bit is such that data+parity have an odd number of 1
wire msbFirst = 0; //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
reg clk;
reg nReset;
// Outputs
wire serialOut;
wire run;
wire full;
wire stopBits;
// Instantiate the Unit Under Test (UUT)
TxCore #(
.PARITY_POLARITY(PARITY)
) uut (
.serialOut(serialOut),
.run(run),
.full(full),
.stopBits(stopBits),
.dataIn(dataIn),
.clocksPerBit(clocksPerBit),
.stopBit2(stopBit2),
.oddParity(oddParity),
.msbFirst(msbFirst),
.loadDataIn(loadDataIn),
.clk(clk),
.nReset(nReset)
);
//test bench signals
reg tbClock;
reg tbBitCounter;
initial begin
tbClock = 0;
tbBitCounter = 0;
// Initialize Inputs
dataIn = 0;
loadDataIn = 0;
clocksPerBit = 8;
stopBit2 = 0;
clk = 0;
nReset = 0;
#(CLK_PERIOD * 10);
nReset = 1;
#(CLK_PERIOD * 10);
// Add stimulus here
dataIn = 8'b1000_0000;
loadDataIn = 1;
wait (full == 1);
wait (full == 0);
//loadDataIn=0;
dataIn = 8'b0111_1111;
//loadDataIn = 1;
wait (full == 1);
wait (full == 0);
loadDataIn = 0;
end
initial begin
// timeout
#10000;
$finish;
end
always #1 tbClock = !tbClock;
always #(CLK_PERIOD / 2) clk = !clk;
endmodule
| 7.702301 |
module TxCycleCtrl (
clk,
mkReady,
txReady,
txStart
);
input clk, mkReady, txReady;
output reg txStart;
parameter [7:0] FreqInMHz = 40;
parameter [15:0] FreqOutHz = 5000;
localparam [15:0] PR = ((1000000 * FreqInMHz) / FreqOutHz) - 1;
reg [15:0] Cnt = 16'h0000;
always @(posedge clk) begin
if (!txReady) txStart <= 1'b0;
if (mkReady) begin
if (Cnt < PR) Cnt <= Cnt + 16'h0001;
else begin
txStart <= 1'b1;
Cnt <= 0;
end
end else begin
end
end
endmodule
| 6.932338 |
module trans_reg (
d_in,
load,
shift,
txd,
clk,
rst
);
input [7:0] d_in;
input load;
input shift;
output txd;
input clk;
input rst;
reg [10:0] t_reg; // transmit register
integer i; // logic variable
// TxD
assign txd = t_reg[0]; // bit 0 is always output to TxD
// shift register
always @(posedge clk or posedge rst)
if (rst) t_reg <= 'h7FF; // ensure TxD is '1' in idle state
else if (load) begin
t_reg[10] <= 1'b1; // stop bit
t_reg[9:2] <= d_in; // byte to be transmitted
t_reg[1] <= 1'b0; // start bit
t_reg[0] <= 1'b1; // line idle
end else if (shift) // serialisation of transmit register
for (i = 1; i <= 10; i = i + 1) t_reg[i-1] <= t_reg[i];
endmodule
| 7.307444 |
module TxData (
input SysClk,
input Reset,
output reg [6:0] HEX7, //
output reg [6:0] HEX6, //
output reg [6:0] HEX5, //
output reg [6:0] HEX4, //
output reg [6:0] HEX3, //
output reg [6:0] HEX2, //
output reg [6:0] HEX1, //
output reg [6:0] HEX0, //
output reg [1:0] Addr,
output reg [7:0] DataOut,
input [7:0] DataIn,
output reg CS_N,
output reg RD_N,
output reg WR_N
);
reg [2:0] c_state;
reg [2:0] n_state;
reg [7:0] CSRegIn;
reg [7:0] tmpDataOut;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b110;
parameter S7 = 3'b111;
parameter LED_None = 7'b0111111; // Display "-"
reg [2:0] counter;
always@ (posedge SysClk) // output logic
begin
if (~Reset) begin
counter <= 3'b000;
HEX0 <= LED_None;
HEX1 <= LED_None;
HEX2 <= LED_None;
HEX3 <= LED_None;
HEX4 <= LED_None;
HEX5 <= LED_None;
HEX6 <= LED_None;
HEX7 <= LED_None;
end else begin
if (c_state == S6) //
begin
case (counter)
3'b000: HEX0 <= tmpDataOut[6:0];
3'b001: HEX1 <= tmpDataOut[6:0];
3'b010: HEX2 <= tmpDataOut[6:0];
3'b011: HEX3 <= tmpDataOut[6:0];
3'b100: HEX4 <= tmpDataOut[6:0];
3'b101: HEX5 <= tmpDataOut[6:0];
3'b110: HEX6 <= tmpDataOut[6:0];
3'b111: HEX7 <= tmpDataOut[6:0];
endcase
counter <= counter + 3'b001;
end
end
end
always@ (posedge SysClk) // output logic
begin
if (~Reset) CSRegIn <= 8'h00;
else begin
if (c_state == S0) CSRegIn <= 8'h0;
else if (c_state == S3) CSRegIn <= DataIn;
end
end
always @(*) begin
if (DataOut == 8'h7A) tmpDataOut <= 8'h41;
else tmpDataOut <= DataOut + 8'h01;
end
always@ (posedge SysClk) // output logic
begin
if (~Reset) begin
CS_N <= 1'b1;
RD_N <= 1'b1;
WR_N <= 1'b1;
DataOut <= 8'h41;
end else begin
if (c_state == S2) // Read status register to check if Tx buffer is empty
begin
CS_N <= 1'b0;
RD_N <= 1'b0;
WR_N <= 1'b1;
Addr <= 2'b01;
end
else if (c_state == S6) // Transmit "tmpDataOut" to TxD
begin
CS_N <= 1'b0;
RD_N <= 1'b1;
WR_N <= 1'b0;
Addr <= 2'b00;
DataOut <= tmpDataOut;
end else begin
CS_N <= 1'b1;
RD_N <= 1'b1;
WR_N <= 1'b1;
end
end
end
always@ (posedge SysClk) // synchronous resettable flop-flops
begin
if (~Reset) c_state <= S0;
else c_state <= n_state;
end
always@(*) // Next state logic
begin
case (c_state)
S0: n_state <= S1;
S1: n_state <= S2;
S2: n_state <= S3;
S3: n_state <= S4;
S4:
if (CSRegIn[3]) n_state <= S6; //UnderRun (Tx Buffer & Tx Reg Empty)
else n_state <= S5;
S5: n_state <= S2;
S6: n_state <= S0;
default: n_state <= S0;
endcase
end
endmodule
| 6.775672 |
module TXDemo (
input Clock,
input Reset,
input start_tx,
input tx_packet_data_rdy_in,
output [15:0] tx_packet_data_out,
output tx_req_out,
input tx_complete_in,
output reg [8:0] Debug_LEDG
);
assign tx_packet_data_out = rom_data[15:0];
assign tx_req_out = state == wait_for_tx_rdy;
parameter waiting = 4'd0, wait_for_tx_rdy = 4'd1, wait_for_complete = 4'd2;
reg [3:0] state;
reg [4:0] rom_index;
wire [17:0] rom_data;
reg [7:0] ncr_reg;
wire [4:0] w_rom_index = (state == wait_for_tx_rdy) & tx_packet_data_rdy_in ? rom_index + 5'd1 : rom_index;
always @(posedge Clock) begin
if (Reset) begin
rom_index <= 5'd0;
state <= waiting;
Debug_LEDG <= 9'b0;
end else begin
case (state)
waiting: begin
// let it overflow to zero for the first tx
rom_index <= 5'h1F;
if (start_tx) begin
state <= wait_for_tx_rdy;
end else begin
state <= waiting;
end
end
wait_for_tx_rdy: begin
if (tx_packet_data_rdy_in) begin
rom_index <= w_rom_index;
end
if (rom_index == 5'd12) begin
state <= wait_for_complete;
end else begin
state <= wait_for_tx_rdy;
end
end
wait_for_complete: begin
if (tx_complete_in) begin
Debug_LEDG <= 9'h1FF;
state <= waiting;
end else begin
state <= wait_for_complete;
end
end
endcase
end
end
enet_init_rom eir (
.address(w_rom_index),
.clock(Clock),
.q(rom_data)
);
endmodule
| 8.179048 |
module TxDWrapper (
input Clock,
input Reset,
input [15:0] Data,
input [1:0] RequestToSend,
output [1:0] DataReceivedOut,
output SDO
);
localparam STATE_Idle = 2'b00, STATE_Wait = 2'b01, STATE_TxDStart = 2'b010;
reg [1:0] CurrentState = STATE_Idle;
reg [1:0] NextState = STATE_Idle;
reg [7:0] TxDBuffer = 8'b0;
reg [7:0] NewTxDValue = 8'b0;
reg [1:0] DataReceived = 2'b0;
reg [1:0] DRNext = 2'b0;
assign DataReceivedOut = DataReceived;
//--------------------------------------------
//Synchronous State Transition
//--------------------------------------------
always @(posedge Clock) begin
if (Reset) begin
CurrentState <= STATE_Idle;
TxDBuffer <= 8'b0;
DataReceived <= 2'b0;
end else begin
CurrentState <= NextState;
TxDBuffer <= NewTxDValue;
DataReceived <= DRNext;
end
end
//------------------------------------------
//Conditional State Transition
//------------------------------------------
always @(*) begin
NextState = CurrentState;
NewTxDValue = TxDBuffer;
DRNext = DataReceived;
case (CurrentState)
STATE_Idle: begin
if (RequestToSend[1]) begin
NewTxDValue = Data[15:8];
NextState = TxDBusy ? STATE_Wait : STATE_TxDStart;
DRNext = 2'b10;
end else if (RequestToSend[0]) begin
NewTxDValue = Data[7:0];
NextState = TxDBusy ? STATE_Wait : STATE_TxDStart;
DRNext = 2'b01;
end
end
STATE_Wait: begin
DRNext = 2'b00;
if (!TxDBusy) NextState = STATE_TxDStart;
end
STATE_TxDStart: begin
DRNext = 2'b00;
NextState = STATE_Idle;
end
endcase
end
assign TxDStart = (CurrentState == STATE_TxDStart);
async_transmitter txd (
.clk(Clock),
.TxD_start(TxDStart),
.TxD_data(TxDBuffer),
.TxD(SDO),
.TxD_busy(TxDBusy)
);
endmodule
| 7.771106 |
module TxFifo (
busClk,
usbClk,
rstSyncToBusClk,
rstSyncToUsbClk,
fifoREn,
fifoEmpty,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataOut
);
//FIFO_DEPTH = ADDR_WIDTH^2
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
input busClk;
input usbClk;
input rstSyncToBusClk;
input rstSyncToUsbClk;
input fifoREn;
output fifoEmpty;
input [2:0] busAddress;
input busWriteEn;
input busStrobe_i;
input busFifoSelect;
input [7:0] busDataIn;
output [7:0] busDataOut;
output [7:0] fifoDataOut;
wire busClk;
wire usbClk;
wire rstSyncToBusClk;
wire rstSyncToUsbClk;
wire fifoREn;
wire fifoEmpty;
wire [2:0] busAddress;
wire busWriteEn;
wire busStrobe_i;
wire busFifoSelect;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
wire [7:0] fifoDataOut;
//internal wires and regs
wire fifoWEn;
wire forceEmptySyncToUsbClk;
wire forceEmptySyncToBusClk;
wire [15:0] numElementsInFifo;
wire fifoFull;
fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo (
.wrClk(busClk),
.rdClk(usbClk),
.rstSyncToWrClk(rstSyncToBusClk),
.rstSyncToRdClk(rstSyncToUsbClk),
.dataIn(busDataIn),
.dataOut(fifoDataOut),
.fifoWEn(fifoWEn),
.fifoREn(fifoREn),
.fifoFull(fifoFull),
.fifoEmpty(fifoEmpty),
.forceEmptySyncToWrClk(forceEmptySyncToBusClk),
.forceEmptySyncToRdClk(forceEmptySyncToUsbClk),
.numElementsInFifo(numElementsInFifo)
);
TxfifoBI u_TxfifoBI (
.address(busAddress),
.writeEn(busWriteEn),
.strobe_i(busStrobe_i),
.busClk(busClk),
.usbClk(usbClk),
.rstSyncToBusClk(rstSyncToBusClk),
.fifoSelect(busFifoSelect),
.busDataIn(busDataIn),
.busDataOut(busDataOut),
.fifoWEn(fifoWEn),
.forceEmptySyncToBusClk(forceEmptySyncToBusClk),
.forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
.numElementsInFifo(numElementsInFifo)
);
endmodule
| 6.747114 |
module txfifo_packet_composer #(
parameter DATA_WIDTH = 64,
parameter LOCAL_FIFO_DEPTH = 256
) (
clock,
aclr,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw
);
function integer log2;
input integer number;
begin
log2 = 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
localparam FIFO_ADDR_WIDTH = log2(LOCAL_FIFO_DEPTH);
input clock;
input aclr;
input [DATA_WIDTH-1:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [DATA_WIDTH-1:0] q;
output [FIFO_ADDR_WIDTH-1:0] usedw;
wire [FIFO_ADDR_WIDTH-1:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [DATA_WIDTH-1:0] sub_wire3;
wire sub_wire4;
wire [FIFO_ADDR_WIDTH-1:0] usedw = sub_wire0[FIFO_ADDR_WIDTH-1:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [DATA_WIDTH-1:0] q = sub_wire3[DATA_WIDTH-1:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock(clock),
.wrreq(wrreq),
.data(data),
.rdreq(rdreq),
.usedw(sub_wire0),
.empty(sub_wire1),
.full(sub_wire2),
.q(sub_wire3),
.almost_full(sub_wire4),
.aclr(aclr),
.sclr()
);
defparam scfifo_component.add_ram_output_register = "OFF", scfifo_component.almost_full_value =
LOCAL_FIFO_DEPTH / 2, scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = LOCAL_FIFO_DEPTH, scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo", scfifo_component.lpm_width = DATA_WIDTH,
scfifo_component.lpm_widthu = FIFO_ADDR_WIDTH, scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON", scfifo_component.use_eab = "ON";
endmodule
| 6.503782 |
module TxFifo_simlib (
busClk,
usbClk,
rstSyncToBusClk,
rstSyncToUsbClk,
fifoREn,
fifoEmpty,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataOut
);
//FIFO_DEPTH = ADDR_WIDTH^2
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
input busClk;
input usbClk;
input rstSyncToBusClk;
input rstSyncToUsbClk;
input fifoREn;
output fifoEmpty;
input [2:0] busAddress;
input busWriteEn;
input busStrobe_i;
input busFifoSelect;
input [7:0] busDataIn;
output [7:0] busDataOut;
output [7:0] fifoDataOut;
wire busClk;
wire usbClk;
wire rstSyncToBusClk;
wire rstSyncToUsbClk;
wire fifoREn;
wire fifoEmpty;
wire [2:0] busAddress;
wire busWriteEn;
wire busStrobe_i;
wire busFifoSelect;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
wire [7:0] fifoDataOut;
//internal wires and regs
wire fifoWEn;
wire forceEmptySyncToUsbClk;
wire forceEmptySyncToBusClk;
wire [15:0] numElementsInFifo;
wire fifoFull;
fifoRTL_simlib #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo (
.wrClk(busClk),
.rdClk(usbClk),
.rstSyncToWrClk(rstSyncToBusClk),
.rstSyncToRdClk(rstSyncToUsbClk),
.dataIn(busDataIn),
.dataOut(fifoDataOut),
.fifoWEn(fifoWEn),
.fifoREn(fifoREn),
.fifoFull(fifoFull),
.fifoEmpty(fifoEmpty),
.forceEmptySyncToWrClk(forceEmptySyncToBusClk),
.forceEmptySyncToRdClk(forceEmptySyncToUsbClk),
.numElementsInFifo(numElementsInFifo)
);
TxfifoBI_simlib u_TxfifoBI (
.address(busAddress),
.writeEn(busWriteEn),
.strobe_i(busStrobe_i),
.busClk(busClk),
.usbClk(usbClk),
.rstSyncToBusClk(rstSyncToBusClk),
.fifoSelect(busFifoSelect),
.busDataIn(busDataIn),
.busDataOut(busDataOut),
.fifoWEn(fifoWEn),
.forceEmptySyncToBusClk(forceEmptySyncToBusClk),
.forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
.numElementsInFifo(numElementsInFifo)
);
endmodule
| 6.616674 |
module TxFsm (
output io_dataOut_valid,
input io_dataOut_ready,
output reg io_dataOut_payload_last,
output [511:0] io_dataOut_payload_fragment_data,
output [ 15:0] io_dataOut_payload_fragment_byteNum,
output [ 63:0] io_dataOut_payload_fragment_tkeep,
input clk,
input reset
);
wire [6:0] _zz_dataCnt_valueNext;
wire [0:0] _zz_dataCnt_valueNext_1;
wire [6:0] _zz_io_dataOut_payload_fragment_data;
reg dataCnt_willIncrement;
wire dataCnt_willClear;
reg [6:0] dataCnt_valueNext;
reg [6:0] dataCnt_value;
wire dataCnt_willOverflowIfInc;
wire dataCnt_willOverflow;
wire io_dataOut_fire;
assign _zz_dataCnt_valueNext_1 = dataCnt_willIncrement;
assign _zz_dataCnt_valueNext = {6'd0, _zz_dataCnt_valueNext_1};
assign _zz_io_dataOut_payload_fragment_data = dataCnt_value;
always @(*) begin
dataCnt_willIncrement = 1'b0;
if (io_dataOut_fire) begin
dataCnt_willIncrement = 1'b1;
end
end
assign dataCnt_willClear = 1'b0;
assign dataCnt_willOverflowIfInc = (dataCnt_value == 7'h63);
assign dataCnt_willOverflow = (dataCnt_willOverflowIfInc && dataCnt_willIncrement);
always @(*) begin
if (dataCnt_willOverflow) begin
dataCnt_valueNext = 7'h0;
end else begin
dataCnt_valueNext = (dataCnt_value + _zz_dataCnt_valueNext);
end
if (dataCnt_willClear) begin
dataCnt_valueNext = 7'h0;
end
end
assign io_dataOut_payload_fragment_byteNum = 16'h0064;
assign io_dataOut_valid = 1'b1;
assign io_dataOut_payload_fragment_data = {505'd0, _zz_io_dataOut_payload_fragment_data};
assign io_dataOut_payload_fragment_tkeep = 64'hffffffffffffffff;
assign io_dataOut_fire = (io_dataOut_valid && io_dataOut_ready);
always @(*) begin
if (dataCnt_willOverflow) begin
io_dataOut_payload_last = 1'b1;
end else begin
io_dataOut_payload_last = 1'b0;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
dataCnt_value <= 7'h0;
end else begin
dataCnt_value <= dataCnt_valueNext;
end
end
endmodule
| 7.118452 |
module txmit (
din,
tbre,
tsre,
rst,
clk16x,
wrn,
sdo
);
output tbre;
output tsre;
output sdo;
input [7:0] din;
input rst;
input clk16x;
input wrn;
reg tbre;
reg tsre;
reg clk1x_enable;
reg [7:0] tsr;
reg [7:0] tbr;
reg parity;
reg [3:0] clkdiv;
wire clk1x;
reg sdo;
reg [3:0] no_bits_sent;
reg wrn1;
reg wrn2;
always @(posedge clk16x or posedge rst) begin
if (rst) begin
wrn1 <= 1'b1;
wrn2 <= 1'b1;
end else begin
wrn1 <= wrn;
wrn2 <= wrn1;
end
end
always @(posedge clk16x or posedge rst) begin
if (rst) begin
tbre <= 1'b0;
clk1x_enable <= 1'b0;
end else if (!wrn1 && wrn2) begin
clk1x_enable <= 1'b1;
tbre <= 1'b1;
end else if (no_bits_sent == 4'b0010) tbre <= 1'b1;
else if (no_bits_sent == 4'b1101) begin
clk1x_enable <= 1'b0;
tbre <= 1'b0;
end
end
always @(negedge wrn or posedge rst) begin
if (rst) tbr = 8'b0;
else tbr = din;
end
always @(posedge clk16x or posedge rst) begin
if (rst) clkdiv = 4'b0;
else if (clk1x_enable) clkdiv = clkdiv + 1;
end
assign clk1x = clkdiv[3];
always @(negedge clk1x or posedge rst)
if (rst) begin
sdo <= 1'b1;
tsre <= 1'b1;
parity <= 1'b1;
tsr <= 8'b0;
end else begin
if (no_bits_sent == 4'b0001) begin
tsr <= tbr;
tsre <= 1'b0;
end else if (no_bits_sent == 4'b0010) begin
sdo <= 1'b0;
end else if ((no_bits_sent >= 4'b0011) && (no_bits_sent <= 4'b1010)) begin
tsr[7:1] <= tsr[6:0];
tsr[0] <= 1'b0;
sdo <= tsr[7];
parity <= parity ^ tsr[7];
end else if (no_bits_sent == 4'b1011) begin
sdo <= parity;
end else if (no_bits_sent == 4'b1100) begin
sdo <= 1'b1;
tsre <= 1'b1;
end
end
always @(posedge clk1x or posedge rst or negedge clk1x_enable)
if (rst) no_bits_sent = 4'b0000;
else if (!clk1x_enable) no_bits_sent = 4'b0000;
else no_bits_sent = no_bits_sent + 1;
endmodule
| 7.535853 |
module TXMOD (
output TX,
input CLK,
input [7:0] data,
input valid,
output ready
);
reg TXReg = 1;
assign TX = TXReg;
reg [10:0] dataStore = 1536; // MSB=1, LSB=0
reg writing = 0;
assign ready = (writing == 0);
reg [13:0] writeClock = 0; // which cycle are we in?
reg [ 3:0] writeBit = 0; // which bit are we writing? (10 bits total)
always @(posedge CLK) begin
if (writing == 0 && valid == 1) begin
writing <= 1;
dataStore[8:1] <= data;
writeClock <= 100;
writeBit <= 0;
TXReg <= dataStore[0];
end else if (writing == 1 && writeClock == 0 && writeBit == 9) begin
// we're done
TXReg <= 1;
writing <= 0;
end else if (writing == 1 && writeClock == 0) begin
// move on to next bit
TXReg <= dataStore[writeBit];
writeBit <= writeBit + 1;
writeClock <= 100;
end else if (writing == 1) begin
TXReg <= dataStore[writeBit];
writeClock <= writeClock - 1;
end else begin
TXReg <= 1;
end
end
endmodule
| 6.749078 |
module txrx_tb ();
//this is the testbench for the tx module independently
reg clk, Rst_n, TxData_Valid;
reg [31:0] TxData;
reg Error_Ack;
wire Rx_Ready_synth, Rx_Error_synth;
wire Rx_Ready, Rx_Error;
wire Tx_Ready_synth, Tx_Error_synth, S_Data_synth;
wire Tx_Ready, Tx_Error, S_Data;
// RX/Core Wires
reg Core_Rcv_Ready = 1'b0;
wire RxData_Valid;
wire [31:0] RxData;
wire RxData_Valid_synth;
wire [31:0] RxData_synth;
tx DUT (
.Clk_s(clk),
.Rst_n(Rst_n),
.TxData_Valid(TxData_Valid),
.TxData(TxData),
.Error_Ack(Error_Ack),
.Rx_Ready(Rx_Ready),
.Rx_Error(Rx_Error), //INPUTS
.Tx_Ready(Tx_Ready),
.Tx_Error(Tx_Error),
.S_Data(S_Data) //OUTPUTS
);
tx_synth txNetDUT (
.Clk_s(clk),
.Rst_n(Rst_n),
.TxData_Valid(TxData_Valid),
.TxData(TxData),
.Error_Ack(Error_Ack),
.Rx_Ready(Rx_Ready),
.Rx_Error(Rx_Error), //INPUTS
.Tx_Ready(Tx_Ready_synth),
.Tx_Error(Tx_Error_synth),
.S_Data(S_Data_synth) //OUTPUTS
);
rx DUTrx (
.Clk_s(clk),
.Rst_n(Rst_n),
.Core_Rcv_Ready(Core_Rcv_Ready),
.S_Data(S_Data), //Inputs
.RxData_Valid(RxData_Valid),
.RxData(RxData),
.Rx_Ready(Rx_Ready),
.Rx_Error(Rx_Error) //Outputs
);
rx_synth DUTrxNet (
.Clk_s(clk),
.Rst_n(Rst_n),
.Core_Rcv_Ready(Core_Rcv_Ready),
.S_Data(S_Data), //Inputs
.RxData_Valid(RxData_Valid_synth),
.RxData(RxData_synth),
.Rx_Ready(Rx_Ready_synth),
.Rx_Error(Rx_Error_synth) //Outputs
);
reg
Rx_Ready_Error,
Rx_Error_Error,
RxData_Error,
RxData_Valid_Error,
Tx_Ready_Error,
Tx_Error_Error,
S_Data_Error;
reg Synth_Error;
always @(negedge clk) begin
Rx_Ready_Error = (Rx_Ready != Rx_Ready_synth);
Rx_Error_Error = (Rx_Error != Rx_Error_synth);
RxData_Error = (RxData != RxData_synth);
RxData_Valid_Error = (RxData_Valid != RxData_Valid_synth);
Tx_Ready_Error = (Tx_Ready != Tx_Ready_synth);
Tx_Error_Error = (Tx_Error != Tx_Error_synth);
S_Data_Error = (S_Data != S_Data_synth);
Synth_Error = (Rx_Ready_Error || Rx_Error_Error || RxData_Error || RxData_Valid_Error || Tx_Ready_Error || Tx_Error_Error || S_Data_Error);
end
reg GlobalErr = 1'b0;
/*
reg nextErr = 1'b0;
always @(posedge clk) nextErr = GlobalErr ? 0 : GlobalErr;
always @(posedge clk) GlobalErr = nextErr;
*/
//establish a clk
always #5 clk = !clk;
reg [5:0] count_1 = 6'd0;
initial begin
//start by giving tx a few cycles to 'warm up'
//assert and deassert reset
clk = 1'b0;
Rst_n = 1'b0;
TxData_Valid = 1'b0;
Error_Ack = 1'b0;
#10
//release reset
Rst_n = 1'b1;
//now lets have some fun. We will send a signal from the tb core and
//watch it send the message. We will watch each bit and confirm that it
//is the expected operation...
#5 TxData = 32'b0000_1100_0001_0101_1100_1100_1100_1100;
#20
TxData_Valid = 1'b1;//We have now told the Tx Module it can go to town... If Rx is ready it will go...
#5
//Here we should see Tx_Ready Drop
if (Tx_Ready != 1'b0)
GlobalErr = 1'b1;
TxData_Valid = 1'b0;
#420 Core_Rcv_Ready = 1'b1;
#10 Core_Rcv_Ready = 1'b0;
#10 $display("Expected RxData:\t%b", TxData);
$display("Actual RxData:\t\t%b", RxData);
#5 TxData = 32'hFFFF_FFFF;
#20
TxData_Valid = 1'b1;//We have now told the Tx Module it can go to town... If Rx is ready it will go...
#5
//Here we should see Tx_Ready Drop
if (Tx_Ready != 1'b0)
GlobalErr = 1'b1;
TxData_Valid = 1'b0;
#420 Core_Rcv_Ready = 1'b1;
#10 Core_Rcv_Ready = 1'b0;
#10 $display("Expected RxData:\t%b", TxData);
$display("Actual RxData:\t\t%b", RxData);
$stop;
end
endmodule
| 7.547806 |
module txrx_tb ();
//this is the testbench for the tx module independently
reg clk, Rst_n, TxData_Valid;
reg [31:0] TxData;
reg Error_Ack;
wire Rx_Ready, Rx_Error;
wire Tx_Ready, Tx_Error, S_Data;
// RX/Core Wires
reg Core_Rcv_Ready = 1'b0;
wire RxData_Valid;
wire [31:0] RxData;
tx DUT (
.Clk_s(clk),
.Rst_n(Rst_n),
.TxData_Valid(TxData_Valid),
.TxData(TxData),
.Error_Ack(Error_Ack),
.Rx_Ready(Rx_Ready),
.Rx_Error(Rx_Error), //INPUTS
.Tx_Ready(Tx_Ready),
.Tx_Error(Tx_Error),
.S_Data(S_Data) //OUTPUTS
);
rx DUTrx (
.Clk_s(clk),
.Rst_n(Rst_n),
.Core_Rcv_Ready(Core_Rcv_Ready),
.S_Data(S_Data), //Inputs
.RxData_Valid(RxData_Valid),
.RxData(RxData),
.Rx_Ready(Rx_Ready),
.Rx_Error(Rx_Error) //Outputs
);
reg GlobalErr = 1'b0;
/*
reg nextErr = 1'b0;
always @(posedge clk) nextErr = GlobalErr ? 0 : GlobalErr;
always @(posedge clk) GlobalErr = nextErr;
*/
//establish a clk
always #5 clk = !clk;
reg [5:0] count_1 = 6'd0;
initial begin
//start by giving tx a few cycles to 'warm up'
//assert and deassert reset
clk = 1'b0;
Rst_n = 1'b0;
TxData_Valid = 1'b0;
Error_Ack = 1'b0;
#10
//release reset
Rst_n = 1'b1;
//now lets have some fun. We will send a signal from the tb core and
//watch it send the message. We will watch each bit and confirm that it
//is the expected operation...
#5 TxData = 32'b0000_1100_0001_0101_1100_1100_1100_1100;
#20
TxData_Valid = 1'b1;//We have now told the Tx Module it can go to town... If Rx is ready it will go...
#5
//Here we should see Tx_Ready Drop
if (Tx_Ready != 1'b0)
GlobalErr = 1'b1;
TxData_Valid = 1'b0;
#420 Core_Rcv_Ready = 1'b1;
#10 Core_Rcv_Ready = 1'b0;
#10 $display("Expected RxData:\t%b", TxData);
$display("Actual RxData:\t\t%b", RxData);
#5 TxData = 32'hFFFF_FFFF;
#20
TxData_Valid = 1'b1;//We have now told the Tx Module it can go to town... If Rx is ready it will go...
#5
//Here we should see Tx_Ready Drop
if (Tx_Ready != 1'b0)
GlobalErr = 1'b1;
TxData_Valid = 1'b0;
#420 Core_Rcv_Ready = 1'b1;
#10 Core_Rcv_Ready = 1'b0;
#10 $display("Expected RxData:\t%b", TxData);
$display("Actual RxData:\t\t%b", RxData);
$stop;
end
endmodule
| 7.547806 |
module txsettings (
reset,
trcal_in,
m_in,
dr_in,
trext_in,
querycomplete,
trcal_out,
m_out,
dr_out,
trext_out
);
input reset, dr_in, trext_in, querycomplete;
input [9:0] trcal_in;
input [1:0] m_in;
output dr_out, trext_out;
output [9:0] trcal_out;
output [1:0] m_out;
reg dr_out, trext_out;
reg [9:0] trcal_out;
reg [1:0] m_out;
always @(posedge querycomplete or posedge reset) begin
if (reset) begin
dr_out <= 0;
trext_out <= 0;
trcal_out <= 0;
m_out <= 0;
end else begin
dr_out <= dr_in;
trext_out <= trext_in;
trcal_out <= trcal_in;
m_out <= m_in;
end
end
endmodule
| 7.689918 |
module txstr #(
parameter BAUDRATE = `B115200
) (
input wire clk, //-- System clock
input wire go, //-- When to transmit the string (pulse)
output wire tx //-- Serial data output
);
//-- Serial Unit instantation
uart_tx #(
.BAUDRATE(BAUDRATE) //-- Set the baudrate
) TX0 (
.clk(clk),
.data(data),
.start(start),
.tx(tx),
.ready(ready)
);
//-- Connecting wires
wire ready;
reg start = 0;
reg [7:0] data = 0;
//-- Multiplexer with the 8-character string to transmit
//-- As it is a long string, it would be a better solution to
//-- store it into a rom memory (it is easier to change the text)
always @*
case (char_count)
8'd0: data <= "H";
8'd1: data <= "o";
8'd2: data <= "l";
8'd3: data <= "a";
8'd4: data <= "!";
8'd5: data <= " ";
8'd6: data <= "S";
8'd7: data <= "o";
8'd8: data <= "y";
8'd9: data <= " ";
8'd10: data <= "t";
8'd11: data <= "u";
8'd12: data <= " ";
8'd13: data <= "I";
8'd14: data <= "c";
8'd15: data <= "e";
8'd16: data <= "z";
8'd17: data <= "u";
8'd18: data <= "m";
8'd19: data <= " ";
8'd20: data <= "A";
8'd21: data <= "l";
8'd22: data <= "h";
8'd23: data <= "a";
8'd24: data <= "m";
8'd25: data <= "b";
8'd26: data <= "r";
8'd27: data <= "a";
8'd28: data <= " ";
8'd29: data <= ":";
8'd30: data <= "-";
8'd31: data <= ")";
default: data <= ".";
endcase
//-- Characters counter
//-- It only counts when the cena control signal is enabled
reg [4:0] char_count = 0;
reg cena = 0; //-- Counter enable
always @(posedge clk) if (cena) char_count = char_count + 1;
//--------------------- CONTROLLER
localparam INI = 0;
localparam TXCAR = 1;
localparam NEXTCAR = 2;
localparam WAIT = 3;
//-- fsm state
reg [1:0] state = INI;
reg [1:0] next_state;
//-- Transition between states
always @(posedge clk) begin
state <= next_state;
end
//-- Control signal generation and next states
always @(*) begin
next_state = state;
start = 0;
cena = 0;
case (state)
//-- Initial state. Start the trasmission
INI: begin
start = 1;
next_state = TXCAR;
end
//-- Wait until one car is transmitted
TXCAR: begin
if (ready) next_state = NEXTCAR;
end
//-- Increment the character counter
//-- Finish when it is the last character
NEXTCAR: begin
cena = 1;
if (char_count == 31) next_state = WAIT;
else next_state = INI;
end
WAIT: begin
if (go) next_state = INI;
end
default: begin
end
endcase
end
endmodule
| 6.937204 |
module txstr_tb ();
//-- Baudrate for the simulation
localparam BAUDRATE = `B115200;
//-- clock tics needed for sending one serial package
localparam SERIAL_CAR = (BAUDRATE * 10);
//-- System clock
reg clk = 1;
//-- Transmission line
wire tx;
//-- Reset
reg rstn = 0;
//-- Instantiate the entity the character transmitter
txstr #(
.BAUDRATE(BAUDRATE)
) dut (
.clk (clk),
.rstn(rstn),
.tx (tx)
);
//-- Clock generator
always #0.5 clk <= ~clk;
initial begin
//-- File where to store the simulation
$dumpfile("txstr_tb.vcd");
$dumpvars(0, txstr_tb);
//-- Activate reset
#1 rstn <= 0;
//-- Disable the reset. The transmission begins!
#3 rstn <= 1;
//-- Wait for 3 characters and finish
#(SERIAL_CAR * 10) $display("END of simulation");
$finish;
end
endmodule
| 7.973423 |
module TXT (
input clk, // Input 25.175 MHz clock, this is a pixel clock for this VGA mode
input reset, // Input async. active low reset signal
output [9:0] pix_x, // The exact X coordinate of a pixel that is currently being drawn
output [9:0] pix_y, // The exact Y coordinate of a pixel that is currently being drawn
output reg [11:0] ascii_address, // Address into memory containing a current character code
input [ 7:0] char_line_data, // Currect character single line data (8 bit at a time)
output reg vga_out, // Final VGA out signal (monochrome)
output reg disp_mem_en, // Enable display memory to read
output reg font_mem_en, // Enable font memory to read
output hsync,
output vsync
);
VGA vga0 (
.clk (clk),
.pixv (pix_x),
.pixh (pix_y),
.hsync(hsync),
.vsync(vsync)
);
reg [ 7:0] line_data; // Current character line data shifter
reg [11:0] xp = 0; // Temp
reg [11:0] yp = 0; // Temp
always @(posedge clk or negedge reset) begin
if (!reset) begin
line_data <= 0; // Do a mandatory reset of all registers
ascii_address <= 0;
disp_mem_en <= 0;
font_mem_en <= 0;
end else begin
ascii_address <= 0;
// The sequence of getting a pixel to display is clocked by pix_x[2:0]
// Font it 16x16 pixels, that is two 8-bit words for each line
case (pix_x[2:0])
// State 1: send the address of a character to pick up onto the
// address bus of the display ROM. Enable both memories
// so the output of the first one propagates to the second one
// and make it output a line of character definition
3'b110: begin
// Calculate the address within the display memory of a current
// character based on the current pixel X and Y coordinates
// There are 40 chars/line, hence multiply Y by 40
xp[11:0] <= {6'd0, pix_x[9:4]};
yp[11:0] <= {6'd0, pix_y[9:4]};
ascii_address[11:0] <= (yp << 5) + (yp << 3) + xp;
//ascii_address[11:0] <= xp + yp * 40;
disp_mem_en <= 1;
font_mem_en <= 1;
end
// State 2: At this time clock the outputs of both memories should have
// stabilized and we can read a line of character definition
3'b111: begin
line_data <= char_line_data;
end
// State 3: This is timed to coencide with pix'000 when a new character
// line is going to be displayed (@always loop below).
// Disable outputs of display and font memories for now
3'b000: begin
font_mem_en <= 0;
disp_mem_en <= 0;
end
endcase
end
end
always @(posedge clk) begin
// Depending on the position of a current character pixel, display individual pixels
// using a buffer that was loaded in a state machine (@always loop above)
case (pix_x[2:0])
3'b000: vga_out <= line_data[7];
3'b001: vga_out <= line_data[6];
3'b010: vga_out <= line_data[5];
3'b011: vga_out <= line_data[4];
3'b100: vga_out <= line_data[3];
3'b101: vga_out <= line_data[2];
3'b110: vga_out <= line_data[1];
3'b111: vga_out <= line_data[0];
endcase
end
endmodule
| 8.046579 |
module which generates video sync impulses
///////////////////////////////////////////////////////////////
module txtd (
// inputs:
input wire pixel_clock,
input wire [15:0]wrdata,
input wire [12:0]wradr,
input wire wren,
// outputs:
output reg hsync,
output reg vsync,
//high-color test video signal
output reg [4:0]r,
output reg [5:0]g,
output reg [4:0]b,
output reg visible
);
// video signal parameters, default 1440x900 60Hz
parameter horz_front_porch = 80;
parameter horz_sync = 152;
parameter horz_back_porch = 232;
parameter horz_addr_time = 1440;
parameter vert_front_porch = 3;
parameter vert_sync = 6;
parameter vert_back_porch = 25;
parameter vert_addr_time = 900;
//variables
reg [11:0]pixel_count = 0;
reg [11:0]line_count = 0;
reg hvisible = 1'b0;
reg vvisible = 1'b0;
reg hfetch = 1'b0;
reg [12:0]scr_addr;
reg [11:0]fnt_addr;
//synchronous process
always @(posedge pixel_clock)
begin
hsync <= (pixel_count >= (horz_addr_time+horz_front_porch) && pixel_count < (horz_addr_time+horz_front_porch+horz_sync) );
if(pixel_count < (horz_addr_time+horz_front_porch+horz_sync+horz_back_porch-1) )
pixel_count <= pixel_count + 1'b1;
else
pixel_count <= 0;
end
always @(posedge hsync)
begin
vsync <= (line_count >= (vert_addr_time+vert_back_porch) && line_count < (vert_addr_time+vert_back_porch+vert_sync) );
if(line_count < (vert_sync+vert_back_porch+vert_addr_time+vert_front_porch -1) )
line_count <= line_count + 1'b1;
else
line_count <= 0;
end
always @*
begin
hfetch = (pixel_count < horz_addr_time-5) || (pixel_count > (horz_addr_time+horz_front_porch+horz_sync+horz_back_porch-6));
hvisible = (pixel_count < horz_addr_time);
vvisible = (line_count < vert_addr_time);
end
always @(posedge pixel_clock)
begin
visible <= hvisible & vvisible;
r <= {rr,rr,3'h0};
g <= {gg,gg,3'h0,visible};
b <= {bb,bb,3'h0};
end
reg [2:0]get_char_line;
always @*
begin
if(pixel_count[10:4]>8'h60)
scr_addr = { line_count[9:4], 7'h00 };
else
scr_addr = { line_count[9:4], pixel_count[10:4] + 1'b1 };
fnt_addr = { scr_char[7:0], line_count[3:0] };
end
reg [15:0]scr_char;
reg [7:0]scr_char_line;
reg [2:0]fcolor;
reg [2:0]bcolor;
reg rr,gg,bb;
reg sbit;
always @*
begin
sbit = scr_char_line[ 3'h7 - pixel_count[3:1] ];
end
always @(posedge pixel_clock)
begin
get_char_line <= { get_char_line[1:0],( pixel_count[3:0]==4'hC ) & vvisible & hfetch} ;
if(get_char_line[0])
scr_char <= scr_data;
if(get_char_line[2])
begin
scr_char_line <= fnt_data;
fcolor <= scr_char[10: 8];
bcolor <= scr_char[14:12];
end
if(visible)
begin
rr <= sbit ? fcolor[2] : bcolor[2];
gg <= sbit ? fcolor[1] : bcolor[1];
bb <= sbit ? fcolor[0] : bcolor[0];
end
else
begin
rr <= 1'b0;
bb <= 1'b0;
gg <= 1'b0;
end
end
//memory work here
wire [7:0]fnt_data;
wire [15:0]scr_data;
rom_font my_rom_font(
.address( fnt_addr ),
.clock( pixel_clock ),
.q( fnt_data )
);
screen_ram my_screen_ram (
.clock( pixel_clock ),
.data( wrdata ),
.rdaddress( scr_addr ),
.wraddress( wradr ),
.wren( wren ),
.q( scr_data )
);
endmodule
| 6.687535 |
module txtest (
input wire clk,
input wire load,
output reg tx
);
parameter BAUD = `B300;
reg [9:0] shifter;
reg load_r;
wire clk_baud;
always @(posedge clk) begin
load_r <= load;
end
always @(posedge clk) begin
if (load_r == 0) shifter <= {"K", 2'b01};
else if (load_r == 1 && clk_baud == 1) shifter <= {1'b1, shifter[9:1]};
end
always @(posedge clk) begin
tx <= (load_r) ? shifter[0] : 1;
end
baudgen #(BAUD) BAUD0 (
.clk(clk),
.clk_ena(load_r),
.clk_out(clk_baud)
);
endmodule
| 7.489425 |
module txtest2 (
input wire clk,
input wire load,
output reg tx
);
parameter BAUD = `B300;
reg [9:0] shifter;
reg load_r;
wire clk_baud;
always @(posedge clk) begin
load_r <= load;
end
always @(posedge clk) begin
if (load_r == 0) shifter <= {"K", 2'b01};
else if (load_r == 1 && clk_baud == 1) shifter <= {shifter[0], shifter[9:1]};
end
always @(posedge clk) begin
tx <= (load_r) ? shifter[0] : 1;
end
baudgen #(BAUD) BAUD0 (
.clk(clk),
.clk_ena(load_r),
.clk_out(clk_baud)
);
endmodule
| 7.654519 |
module txtest2_tb ();
//-- Baudios con los que realizar la simulacion
//-- A 300 baudios, la simulacion tarda mas en realizarse porque los
//-- tiempos son mas largos. A 115200 baudios la simulacion es mucho
//-- mas rapida
localparam BAUD = `B115200;
//-- Tics de reloj para envio de datos a esa velocidad
//-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades
localparam BITRATE = (BAUD << 1);
//-- Tics necesarios para enviar una trama serie completa, mas un bit adicional
localparam FRAME = (BITRATE * 11);
//-- Tiempo entre dos bits enviados
localparam FRAME_WAIT = (BITRATE * 4);
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente
txtest2 #(
.BAUD(BAUD)
) dut (
.clk (clk),
.load(dtr),
.tx (tx)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("txtest2_tb.vcd");
$dumpvars(0, txtest2_tb);
#1 dtr <= 0;
//-- Enviar primer caracter
#FRAME_WAIT dtr <= 1;
#(FRAME * 3) dtr <= 0;
//-- Segundo envio
#FRAME_WAIT dtr <= 1;
#(FRAME * 3) dtr <= 0;
#FRAME_WAIT $display("FIN de la simulacion");
$finish;
end
endmodule
| 7.543185 |
module txtest2 (
input wire clk,
output reg tx
);
parameter BAUD = `B300;
parameter DELAY = `T_250ms;
reg [9:0] shifter;
reg load_r;
wire clk_baud;
wire load;
always @(posedge clk) begin
load_r <= load;
end
always @(posedge clk) begin
if (load_r == 0) shifter <= {"K", 2'b01};
else if (load_r == 1 && clk_baud == 1) shifter <= {1'b1, shifter[9:1]};
end
always @(posedge clk) begin
tx <= (load_r) ? shifter[0] : 1;
end
baudgen #(BAUD) BAUD0 (
.clk(clk),
.clk_ena(load_r),
.clk_out(clk_baud)
);
divider #(DELAY) DIV0 (
.clk_in (clk),
.clk_out(load)
);
endmodule
| 7.654519 |
module txtest2_tb ();
//-- Baudios con los que realizar la simulacion
//-- A 300 baudios, la simulacion tarda mas en realizarse porque los
//-- tiempos son mas largos. A 115200 baudios la simulacion es mucho
//-- mas rapida
localparam BAUD = `B115200;
//-- Tics de reloj para envio de datos a esa velocidad
//-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades
localparam BITRATE = (BAUD << 1);
//-- Tics necesarios para enviar una trama serie completa, mas un bit adicional
localparam FRAME = (BITRATE * 11);
//-- Tiempo entre dos bits enviados
localparam FRAME_WAIT = (BITRATE * 4);
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente
txtest2 #(
.BAUD(BAUD)
) dut (
.clk (clk),
.load(dtr),
.tx (tx)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("txtest2_tb.vcd");
$dumpvars(0, txtest2_tb);
#1 dtr <= 0;
//-- Enviar primer caracter
#FRAME_WAIT dtr <= 1;
#(FRAME * 3) dtr <= 0;
//-- Segundo envio
#FRAME_WAIT dtr <= 1;
#(FRAME * 3) dtr <= 0;
#FRAME_WAIT $display("FIN de la simulacion");
$finish;
end
endmodule
| 7.543185 |
module txtest_tb ();
reg clk = 0;
localparam BAUD = `B115200;
//-- Tics de reloj para envio de datos a esa velocidad
//-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades
localparam BITRATE = (BAUD << 1);
//-- Tics necesarios para enviar una trama serie completa, mas un bit adicional
localparam FRAME = (BITRATE * 11);
//-- Tiempo entre dos bits enviados
localparam FRAME_WAIT = (BITRATE * 4);
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente
txtest #(
.BAUD(BAUD)
) dut (
.clk (clk),
.load(dtr),
.tx (tx)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk <= ~clk;
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("txtest_tb.vcd");
$dumpvars(0, txtest_tb);
#1 dtr <= 0;
//-- Enviar primer caracter
#FRAME_WAIT dtr <= 1;
#FRAME dtr <= 0;
//-- Segundo envio
#FRAME_WAIT dtr <= 1;
#FRAME dtr <= 0;
#FRAME_WAIT $display("FIN de la simulacion");
$finish;
end
endmodule
| 7.949722 |
module TxTop (
clk,
rst,
in_data,
para,
s_num,
d_num,
bd_rate,
start,
out_data,
T1200
);
/////////////////////////////////////////////////////////////////////////////////// inputs / outputs
input clk, rst;
input start;
input [7:0] in_data;
//selectors
input [1:0] para, bd_rate;
input s_num, d_num;
output out_data;
output T1200;
wire T2400, T4800, T9600;
/////////////////////////////////////////////////////////////////////////////////// frqunecy divider instance
freq dut1 (
clk,
rst,
T1200,
T2400,
T4800,
T9600
);
/////////////////////////////////////////////////////////////////////////////////// Tx instance
Tx dut2 (
rst,
in_data,
out_data,
para,
s_num,
d_num,
bd_rate,
T1200,
T2400,
T4800,
T9600,
start
);
endmodule
| 7.031263 |
module txt_col (
for_en,
col_bak,
col_for,
r2,
r1,
r0,
g2,
g1,
g0,
b1,
b0
);
parameter BAK_COL_FILE = "";
parameter FOR_COL_FILE = "";
input for_en;
input [3:0] col_bak;
input [3:0] col_for;
wire [7:0] bak_col;
wire [7:0] for_col;
wire [7:0] col;
assign col = for_en ? for_col : bak_col;
reg [7:0] bak_ram[15:0];
reg [7:0] for_ram[15:0];
/*
assign bak_col = bak_ram[col_bak];
assign for_col = for_ram[col_for];
*/
assign bak_col = {
col_bak[3], col_bak[2], col_bak[2], col_bak[3], col_bak[1], col_bak[1], col_bak[3], col_bak[0]
};
assign for_col = {
col_for[3], col_for[2], col_for[2], col_for[3], col_for[1], col_for[1], col_for[3], col_for[0]
};
output r2, r1, r0, g2, g1, g0, b1, b0;
assign r2 = col[7];
assign r1 = col[6];
assign r0 = col[5];
assign g2 = col[4];
assign g1 = col[3];
assign g0 = col[2];
assign b1 = col[1];
assign b0 = col[0];
initial begin
if (BAK_COL_FILE != "") begin
$readmemh(BAK_COL_FILE, bak_ram);
end
if (FOR_COL_FILE != "") begin
$readmemh(FOR_COL_FILE, for_ram);
end
end
endmodule
| 6.811509 |
module TxUnit (
Clk,
Reset,
Enable,
Load,
TxD,
TRegE,
TBufE,
DataO
);
input Clk; // Clock signal
input Reset; // Reset input
input Enable; // Enable input
input Load; // Load transmit data
output TxD; // RS-232 data output
output TRegE; // Tx register empty
output TBufE; // Tx buffer empty
input [7:0] DataO;
wire Clk;
wire Reset;
wire Enable;
wire Load;
wire TRegE;
wire TBufE;
wire [7:0] DataO;
reg TxD;
//---------------------------------------------------------------------------
// Signals
//---------------------------------------------------------------------------
reg [7:0] TBuff; // transmit buffer
reg [7:0] TReg; // transmit register
reg [3:0] BitCnt; // bit counter
reg tmpTRegE; //
reg tmpTBufE; //
//---------------------------------------------------------------------------
// Implements the Tx unit
//---------------------------------------------------------------------------
always @(posedge Clk) begin : P1
reg tmp_TRegE;
if (Reset == 1'b0) begin
tmpTRegE <= 1'b1;
tmpTBufE <= 1'b1;
TxD <= 1'b1;
BitCnt <= 4'b0000;
end else if (Load == 1'b1) begin
TBuff <= DataO;
tmpTBufE <= 1'b0;
end else if (Enable == 1'b1) begin
if ((tmpTBufE == 1'b0) && (tmpTRegE == 1'b1)) begin
TReg <= TBuff;
tmpTRegE <= 1'b0; // tmp_TRegE := '0';
tmpTBufE <= 1'b1;
// else
// tmp_TRegE := tmpTRegE;
end
if (tmpTRegE == 1'b0) begin
case (BitCnt)
4'b0000: begin
TxD <= 1'b0;
BitCnt <= BitCnt + 4'b0001;
end
4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111, 4'b1000: begin
TxD <= TReg[0];
TReg <= {1'b1, TReg[7:1]};
BitCnt <= BitCnt + 4'b0001;
end
4'b1001: begin
TxD <= 1'b1;
TReg <= {1'b1, TReg[7:1]};
BitCnt <= 4'b0000;
tmpTRegE <= 1'b1;
end
default: begin
end
endcase
end
end
end
assign TRegE = tmpTRegE;
assign TBufE = tmpTBufE;
//=================== End of architecture ====================--
endmodule
| 6.53096 |
module tx_24bits (
input CLK,
input RST,
input [19:0] tx_data,
input tx_vld,
output tx
);
wire clk_800;
CLKDIV_800 gen8bits (
.CLK (CLK),
.RST (RST),
.CLK_O(clk_800)
);
reg [19:0] temp_data = 20'b0;
always @(posedge CLK) begin
if (RST) temp_data <= 20'b0;
else if (tx_vld) temp_data <= tx_data;
else temp_data <= temp_data;
end
reg [7:0] tx_1, tx_2, tx_3;
always @(temp_data) begin
tx_1 = {temp_data[19:13], 1'b0};
tx_2 = {temp_data[12:10], 2'b0, temp_data[9:7]};
tx_3 = {temp_data[6:0], 1'b0};
end
reg tx_flag;
reg [1:0] cnt = 2'b0;
always @(posedge CLK) begin
if (RST) tx_flag <= 0;
else if (tx_vld) tx_flag <= 1;
else if (cnt == 3) tx_flag <= 0;
else tx_flag <= tx_flag;
end
always @(posedge CLK) begin
if (RST) cnt <= 0;
else if (tx_flag) begin
if (clk_800) cnt <= cnt + 1;
else cnt <= cnt;
end else if (cnt == 3 && clk_800) cnt <= 0;
else cnt <= cnt;
end
reg [7:0] snd_data = 8'b11111111;
always @(posedge CLK) begin
if (RST) snd_data <= 8'b0;
else if (clk_800) begin
case (cnt)
0: snd_data <= tx_1;
1: snd_data <= tx_2;
2: snd_data <= tx_3;
3: snd_data <= 8'b11111111;
default: snd_data <= 8'b00000000;
endcase
end else snd_data <= snd_data;
end
bluetooth_tx transmitter (
.CLK(CLK),
.RST(RST),
.tx_data(snd_data),
.tx_vld(clk_800),
.tx(tx)
);
endmodule
| 7.057222 |
module tx_4channel_arbiter #(
parameter NUM_DAT_WORDS = 8,
parameter LOG_DAT_WORDS = 4, // enough bits to represent 0..#dat inclusive
parameter CHANID0 = 8'h0,
parameter CHANID1 = 8'h1,
parameter CHANID2 = 8'h2,
parameter CHANID3 = 8'h3
) (
input clk,
arst,
// four input ports
input [LOG_DAT_WORDS-1:0] num_chan0words_valid,
input [64*NUM_DAT_WORDS-1:0] chan0words,
input chan0sop,
input [3:0] chan0eopbits,
output chan0ready,
input chan0valid,
input [LOG_DAT_WORDS-1:0] num_chan1words_valid,
input [64*NUM_DAT_WORDS-1:0] chan1words,
input chan1sop,
input [3:0] chan1eopbits,
output chan1ready,
input chan1valid,
input [LOG_DAT_WORDS-1:0] num_chan2words_valid,
input [64*NUM_DAT_WORDS-1:0] chan2words,
input chan2sop,
input [3:0] chan2eopbits,
output chan2ready,
input chan2valid,
input [LOG_DAT_WORDS-1:0] num_chan3words_valid,
input [64*NUM_DAT_WORDS-1:0] chan3words,
input chan3sop,
input [3:0] chan3eopbits,
output chan3ready,
input chan3valid,
// output port
output reg [LOG_DAT_WORDS-1:0] num_datwords_valid,
output reg [64*NUM_DAT_WORDS-1:0] datwords,
output reg [7:0] chan,
output reg sop,
output reg [3:0] eopbits,
input ready,
output valid
);
localparam ARB_CHANS = 4;
reg [ARB_CHANS-1:0] qualified_req;
always @(posedge clk or posedge arst) begin
if (arst) begin
qualified_req <= 0;
end else begin
qualified_req[0] <= chan0valid & (|num_chan0words_valid);
qualified_req[1] <= chan1valid & (|num_chan1words_valid);
qualified_req[2] <= chan2valid & (|num_chan2words_valid);
qualified_req[3] <= chan3valid & (|num_chan3words_valid);
end
end
/////////////////////////////////////
// arbiter with rotating fairness
reg [ARB_CHANS-1:0] base, grant;
wire [ARB_CHANS-1:0] grant_w;
reg [1:0] enc_grant;
always @(posedge clk or posedge arst) begin
if (arst) begin
base <= 1;
grant <= 0;
enc_grant <= 0;
end else begin
if (ready) begin
base <= {base[ARB_CHANS-2:0], base[ARB_CHANS-1]};
grant <= grant_w;
enc_grant <= {grant_w[3] | grant_w[2], grant_w[3] | grant_w[1]};
end
end
end
arbiter arb (
.req (qualified_req),
.grant(grant_w),
.base (base)
);
defparam arb.WIDTH = ARB_CHANS;
/////////////////////////////////////
// ready the winner if any
always @(posedge clk or posedge arst) begin
if (arst) begin
num_datwords_valid <= 0;
datwords <= 0;
chan <= 0;
sop <= 0;
eopbits <= 0;
end else begin
if (ready) begin
if (enc_grant == 2'b00) begin
num_datwords_valid <= num_chan0words_valid;
datwords <= chan0words;
sop <= chan0sop;
eopbits <= chan0eopbits;
chan <= CHANID0;
end else if (enc_grant == 2'b01) begin
num_datwords_valid <= num_chan1words_valid;
datwords <= chan1words;
sop <= chan1sop;
eopbits <= chan1eopbits;
chan <= CHANID1;
end else if (enc_grant == 2'b10) begin
num_datwords_valid <= num_chan2words_valid;
datwords <= chan2words;
sop <= chan2sop;
eopbits <= chan2eopbits;
chan <= CHANID2;
end else begin
num_datwords_valid <= num_chan3words_valid;
datwords <= chan3words;
sop <= chan3sop;
eopbits <= chan3eopbits;
chan <= CHANID3;
end
if (~|grant) num_datwords_valid <= 0;
end
end
end
assign chan0ready = grant[0] & ready;
assign chan1ready = grant[1] & ready;
assign chan2ready = grant[2] & ready;
assign chan3ready = grant[3] & ready;
assign valid = |num_datwords_valid;
endmodule
| 7.025033 |
module tx_64b_tb;
parameter VCD_FILE = "tx_tb.vcd";
parameter NUM_LANES = 1;
parameter NUM_LINKS = 1;
parameter OCTETS_PER_FRAME = 4;
parameter FRAMES_PER_MULTIFRAME = 32;
`include "tb_base.v"
reg [NUM_LINKS-1:0] sync = {NUM_LINKS{1'b1}};
reg [31:0] counter = 'h00;
reg [63:0] tx_data = 'h00000000;
wire tx_ready;
wire tx_valid = 1'b1;
wire [NUM_LANES-1:0] cfg_lanes_disable;
wire [NUM_LINKS-1:0] cfg_links_disable;
wire [7:0] cfg_beats_per_multiframe;
wire [7:0] cfg_octets_per_frame;
wire [7:0] cfg_lmfc_offset;
wire cfg_sysref_oneshot;
wire cfg_sysref_disable;
wire cfg_continuous_cgs;
wire cfg_continuous_ilas;
wire cfg_skip_ilas;
wire [7:0] cfg_mframes_per_ilas;
wire cfg_disable_char_replacement;
wire cfg_disable_scrambler;
wire tx_ilas_config_rd;
wire [1:0] tx_ilas_config_addr;
wire [32*NUM_LANES-1:0] tx_ilas_config_data;
always @(posedge clk) begin
if (reset == 1'b1) begin
tx_data <= 'h00000000;
end else if (tx_ready == 1'b1) begin
tx_data <= tx_data + 1'b1;
end
end
/* Generate independent SYNCs
*
* Each SYNC will be asserted/deasserted at different clock edges.
* The assertion/deassertion order: first SYNC[0], ..., last SYNC[NUM_LINKS-1]
*/
always @(posedge clk) begin
counter <= counter + 1'b1;
end
genvar i;
generate
for (i = 1; i <= NUM_LINKS; i = i + 1) begin : SYNC_GENERATOR
always @(posedge clk) begin
if (counter >= (32'h100 | (i << 4)) && counter <= (32'h300 | (i << 4))) begin
sync[i-1] <= 1'b0;
end else begin
sync[i-1] <= 1'b1;
end
end
end
endgenerate
// DUT with static configuration
jesd204_tx_static_config #(
.NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS),
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
) i_cfg (
.clk(clk),
.cfg_lanes_disable(cfg_lanes_disable),
.cfg_links_disable(cfg_links_disable),
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
.cfg_octets_per_frame(cfg_octets_per_frame),
.cfg_lmfc_offset(cfg_lmfc_offset),
.cfg_continuous_cgs(cfg_continuous_cgs),
.cfg_continuous_ilas(cfg_continuous_ilas),
.cfg_skip_ilas(cfg_skip_ilas),
.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
.cfg_disable_char_replacement(cfg_disable_char_replacement),
.cfg_disable_scrambler(cfg_disable_scrambler),
.cfg_sysref_oneshot(cfg_sysref_oneshot),
.cfg_sysref_disable(cfg_sysref_disable),
.ilas_config_rd (tx_ilas_config_rd),
.ilas_config_addr(tx_ilas_config_addr),
.ilas_config_data(tx_ilas_config_data)
);
jesd204_tx #(
.NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS),
.LINK_MODE(2)
) i_tx (
.clk (clk),
.reset(reset),
.cfg_lanes_disable(cfg_lanes_disable),
.cfg_links_disable(cfg_links_disable),
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
.cfg_octets_per_frame(cfg_octets_per_frame),
.cfg_lmfc_offset(cfg_lmfc_offset),
.cfg_continuous_cgs(cfg_continuous_cgs),
.cfg_continuous_ilas(cfg_continuous_ilas),
.cfg_skip_ilas(cfg_skip_ilas),
.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
.cfg_disable_char_replacement(cfg_disable_char_replacement),
.cfg_disable_scrambler(cfg_disable_scrambler),
.cfg_sysref_oneshot(cfg_sysref_oneshot),
.cfg_sysref_disable(cfg_sysref_disable),
.ilas_config_rd (tx_ilas_config_rd),
.ilas_config_addr(tx_ilas_config_addr),
.ilas_config_data(tx_ilas_config_data),
.ctrl_manual_sync_request(1'b0),
.tx_ready(tx_ready),
.tx_valid(tx_valid),
.tx_data ({NUM_LANES{tx_data}}),
.sync (sync),
.sysref(sysref)
);
endmodule
| 7.880524 |
modules to simplify interface
// Note the MSB and LSB sequence
// LSB first for both input and output data
module TX_8B10B_ENC(
input i_clk
,input i_rst_n
//output for 8b/10b encoder
,input [7:0] i_8b_data
,input i_8b_datak
,output [9:0] o_10b_data
);
reg r_disp_store;
wire c_disp_new;
wire [9:0] c_10b_data;
wire [9:0] c_10b_data_lsf;
reg [9:0] r_10b_data;
TXENC8TO10BYTE m_txenc8to10byte(
.i_Tx8B10BUse (1'b1),
.i_DataK (i_8b_datak),
.i_Data (i_8b_data),
.i_TxDisp (r_disp_store),
.o_EncData (c_10b_data),
.o_TxKErr (),
.o_TxDisp (c_disp_new)
);
always@(posedge i_clk or negedge i_rst_n) begin
if (~i_rst_n) begin
r_disp_store <= `DELAY 1'b0;
end
else begin
r_disp_store <= `DELAY c_disp_new;
end
end
always@(posedge i_clk or negedge i_rst_n) begin
if (~i_rst_n) begin
r_10b_data <= `DELAY 10'h0;
end
else begin
r_10b_data <= `DELAY c_10b_data_lsf;
end
end
assign o_10b_data = r_10b_data;
//the output of TXENC8TO10BYTE is MSB first, the following will change to LSB first
genvar i;
generate
for (i=0; i<=9; i=i+1) begin: BIT_SEQ_ADJ
assign c_10b_data_lsf [i] = c_10b_data[9-i];
end
endgenerate
endmodule
| 7.112616 |
module tx_axis_adapter (
input clk_mac,
input rst_n,
output reg tx_vld,
output reg [7:0] tx_dat,
output reg tx_sof,
output reg tx_eof,
input tx_ack,
input [7:0] tx_axis_mac_tdata,
input tx_axis_mac_tvalid,
input tx_axis_mac_tlast,
output tx_axis_mac_tready
);
reg buffer_used;
reg buffer_vld;
reg [7:0] buffer_data;
reg buffer_last;
assign tx_axis_mac_tready = buffer_used || !buffer_vld;
always @(posedge clk_mac) begin
if (!rst_n) begin
buffer_vld <= 0;
end
if (tx_axis_mac_tready) begin
buffer_vld <= tx_axis_mac_tvalid;
buffer_data <= tx_axis_mac_tdata;
buffer_last <= tx_axis_mac_tlast;
end
end
localparam STATE_IDLE = 0;
localparam STATE_DATA = 1;
localparam STATE_EOF = 2;
localparam STATE_ACK_EOF = 3;
reg [1:0] state, next_state;
always @(posedge clk_mac) begin
if (rst_n) state <= next_state;
else state <= STATE_IDLE;
end
reg next_tx_vld;
reg [7:0] next_tx_dat;
reg next_tx_sof;
reg next_tx_eof;
always @(posedge clk_mac) begin
tx_vld <= rst_n && next_tx_vld;
tx_dat <= next_tx_dat;
tx_sof <= next_tx_sof;
tx_eof <= next_tx_eof;
end
always @* begin
next_state = state;
buffer_used = 0;
next_tx_vld = tx_vld;
next_tx_dat = tx_dat;
next_tx_sof = tx_sof;
next_tx_eof = tx_eof;
case (state)
STATE_IDLE: begin
next_tx_vld = 0;
next_tx_eof = 0;
next_tx_sof = 0;
if (buffer_vld) begin
next_state = buffer_last ? STATE_EOF : STATE_DATA;
next_tx_vld = 1;
next_tx_dat = buffer_data;
next_tx_sof = 1;
buffer_used = 1;
end
end
STATE_DATA: begin
if (tx_ack) begin
if (buffer_vld) begin
next_state = buffer_last ? STATE_EOF : STATE_DATA;
next_tx_vld = 1;
next_tx_dat = buffer_data;
next_tx_sof = 0;
next_tx_eof = 0;
buffer_used = 1;
end else next_state = STATE_IDLE;
end
end
STATE_EOF: begin
if (tx_ack) begin
next_tx_vld = 1;
next_tx_sof = 0;
next_tx_eof = 1;
next_state = STATE_ACK_EOF;
end
end
STATE_ACK_EOF: begin
if (tx_ack) begin
next_tx_vld = 0;
next_tx_eof = 0;
next_state = STATE_IDLE;
end
end
endcase
end
endmodule
| 9.052983 |
module tx_band_gen (
input clk,
input rst,
input band_sig,
output reg clk_bps
);
/////////////////////
parameter SYS_RATE = 100000000;
parameter BAND_RATE = 9600;
parameter CNT_BAND = SYS_RATE / BAND_RATE;
///////////////////////////
reg [13:0] cnt_bps;
always @(posedge clk or posedge rst)
if (rst) begin
cnt_bps <= CNT_BAND - 1'b1;
clk_bps <= 1'b0;
end else if (!band_sig) begin
cnt_bps <= CNT_BAND - 1'b1;
clk_bps <= 1'b0;
end else if (cnt_bps == CNT_BAND) begin
cnt_bps <= 14'd0;
clk_bps <= 1'b1;
end else begin
cnt_bps <= cnt_bps + 1'b1;
clk_bps <= 1'b0;
end
endmodule
| 7.079829 |
module tx_baudrate_tick_generator #(
parameter baudrate = 32'd9600,
parameter frequency = 32'd100000000 // in Hz
) (
input wire clk,
input wire reset,
input wire enable,
output reg tick
);
reg [31:0] count;
localparam [31:0] count_threshold = frequency / (baudrate * 2);
initial begin
tick = 1'b0;
count = 31'b0;
end
always @(posedge (clk), posedge (reset), negedge (enable)) begin
if (~enable) begin
count = 0;
tick = 0;
end else if (reset) begin
count = 0;
tick = 0;
end else begin
if (count == count_threshold) begin
count = 0;
tick = 1;
end else begin
count = count + 1;
tick = 0;
end
end
end
endmodule
| 7.205239 |
module stimulus();
// reg CLK,RESET;
// wire TICK;
// tx_baudrate_tick_generator #(.baudrate(32'd9600),.frequency(32'd100000000))
// t1(
// .clk(CLK),
// .tick(TICK),
// .reset(RESET)
// );
// initial begin
// $dumpfile("simulation.vcd");
// $dumpvars(0,
// CLK,
// TICK,
// RESET
// );
// end
// initial begin
// CLK = 1'b0;
// RESET = 1'b0;
// end
// always
// #1 CLK = ~ CLK;
// initial begin
// #20 RESET = 1'b1;
// #10 RESET = 1'b0;
// end
// initial
// #10000 $finish;
// endmodule
| 6.85176 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_bps_module(
CLK,
RST_n,
Count_Sig,
BPS_CLK
);
input CLK;
input RST_n;
input Count_Sig;
output BPS_CLK;
//50MHz
parameter T104US = 13'd5208;
reg [12:0]Count_BPS;
always @(posedge CLK or negedge RST_n) begin
if (!RST_n)
Count_BPS <= 13'd0;
else if (Count_BPS == T104US)
Count_BPS <= 13'd0;
else if (Count_Sig)
Count_BPS <= Count_BPS + 1'b1;
else
Count_BPS <= 13'd0;
end
assign BPS_CLK = (Count_BPS == (T104US>>1)) ? 1'b1: 1'b0;
endmodule
| 7.088073 |
module tx_buffer ( // USB Side
input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input [15:0] usbdata,
input wire WR,
output reg have_space,
output reg tx_underrun,
input clear_status,
// DSP Side
input txclk,
input reset, // standard DSP-side reset
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
input txstrobe,
output wire tx_empty,
output [31:0] debugbus
);
wire [11:0] txfifolevel;
wire [15:0] fifodata;
wire rdreq;
reg [3:0] phase;
wire sop_f, iq_f;
reg sop;
// USB Side of FIFO
reg [15:0] usbdata_reg;
reg wr_reg;
reg [ 8:0] write_count;
always @(posedge usbclk) have_space <= (txfifolevel < (4092 - 256)); // be extra conservative
always @(posedge usbclk) begin
wr_reg <= WR;
usbdata_reg <= usbdata;
end
always @(posedge usbclk)
if (bus_reset) write_count <= 0;
else if (wr_reg) write_count <= write_count + 1;
else write_count <= 0;
always @(posedge usbclk) sop <= WR & ~wr_reg; // Edge detect
// FIFO
fifo_4k_18 txfifo ( // USB Write Side
.data({sop, write_count[0], usbdata_reg}),
.wrreq(wr_reg & ~write_count[8]),
.wrclk(usbclk),
.wrfull(),
.wrempty(),
.wrusedw(txfifolevel),
// DSP Read Side
.q({sop_f, iq_f, fifodata}),
.rdreq(rdreq),
.rdclk(txclk),
.rdfull(),
.rdempty(tx_empty),
.rdusedw(),
// Async, shared
.aclr(reset)
);
// DAC Side of FIFO
always @(posedge txclk)
if (reset) begin
{tx_i_0, tx_q_0, tx_i_1, tx_q_1} <= 64'h0;
phase <= 4'd0;
end else if (phase == channels) begin
if (txstrobe) phase <= 4'd0;
end else if (~tx_empty) begin
case (phase)
4'd0: tx_i_0 <= fifodata;
4'd1: tx_q_0 <= fifodata;
4'd2: tx_i_1 <= fifodata;
4'd3: tx_q_1 <= fifodata;
endcase // case(phase)
phase <= phase + 4'd1;
end
assign rdreq = ((phase != channels) & ~tx_empty);
// Detect Underruns, cross clock domains
reg clear_status_dsp, tx_underrun_dsp;
always @(posedge txclk) clear_status_dsp <= clear_status;
always @(posedge usbclk) tx_underrun <= tx_underrun_dsp;
always @(posedge txclk)
if (reset) tx_underrun_dsp <= 1'b0;
else if (txstrobe & (phase != channels)) tx_underrun_dsp <= 1'b1;
else if (clear_status_dsp) tx_underrun_dsp <= 1'b0;
// TX debug bus
//
// 15:0 txclk domain => TXA [15:0]
// 31:16 usbclk domain => RXA [15:0]
assign debugbus[0] = reset;
assign debugbus[1] = txstrobe;
assign debugbus[2] = rdreq;
assign debugbus[6:3] = phase;
assign debugbus[7] = tx_empty;
assign debugbus[8] = tx_underrun_dsp;
assign debugbus[9] = iq_f;
assign debugbus[10] = sop_f;
assign debugbus[14:11] = 0;
assign debugbus[15] = txclk;
assign debugbus[16] = bus_reset;
assign debugbus[17] = WR;
assign debugbus[18] = wr_reg;
assign debugbus[19] = have_space;
assign debugbus[20] = write_count[8];
assign debugbus[21] = write_count[0];
assign debugbus[22] = sop;
assign debugbus[23] = tx_underrun;
assign debugbus[30:24] = 0;
assign debugbus[31] = usbclk;
endmodule
| 7.163892 |
module tx_chain (
input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
wire [15:0] bb_i, bb_q;
cic_interp cic_interp_i (
.clock(clock),
.reset(reset),
.enable(enable),
.rate(interp_rate),
.strobe_in(interpolator_strobe),
.strobe_out(sample_strobe),
.signal_in(i_in),
.signal_out(bb_i)
);
cic_interp cic_interp_q (
.clock(clock),
.reset(reset),
.enable(enable),
.rate(interp_rate),
.strobe_in(interpolator_strobe),
.strobe_out(sample_strobe),
.signal_in(q_in),
.signal_out(bb_q)
);
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx (
.clk(clock),
.reset(reset),
.enable(enable),
.strobe(sample_strobe),
.freq(freq),
.phase(phase)
);
cordic tx_cordic_0 (
.clock(clock),
.reset(reset),
.enable(sample_strobe),
.xi(bb_i),
.yi(bb_q),
.zi(phase[31:16]),
.xo(i_out),
.yo(q_out),
.zo()
);
`endif
endmodule
| 7.160319 |
module tx_chain_hb (
input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug,
output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe, hb_strobe, interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb (
.clock(clock),
.reset(reset),
.enable(enable),
.strobe_in(interpolator_strobe),
.strobe_out(hb_strobe),
.signal_in_i(i_in),
.signal_in_q(q_in),
.signal_out_i(hb_i_out),
.signal_out_q(hb_q_out),
.debug(debug[12:0])
);
cic_interp cic_interp_i (
.clock(clock),
.reset(reset),
.enable(enable),
.rate(interp_rate),
.strobe_in(hb_strobe),
.strobe_out(sample_strobe),
.signal_in(hb_i_out),
.signal_out(bb_i)
);
cic_interp cic_interp_q (
.clock(clock),
.reset(reset),
.enable(enable),
.rate(interp_rate),
.strobe_in(hb_strobe),
.strobe_out(sample_strobe),
.signal_in(hb_q_out),
.signal_out(bb_q)
);
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx (
.clk(clock),
.reset(reset),
.enable(enable),
.strobe(sample_strobe),
.freq(freq),
.phase(phase)
);
cordic tx_cordic_0 (
.clock(clock),
.reset(reset),
.enable(sample_strobe),
.xi(bb_i),
.yi(bb_q),
.zi(phase[31:16]),
.xo(i_out),
.yo(q_out),
.zo()
);
`endif
endmodule
| 7.397822 |
module TX_CHAR_REPLACE#(
parameter AM_INTERVAL = 64 //should be large than the rx deksew fifo depth
)(
input i_clk
,input i_rst_n
//rs encoded data
,input i_sof_in
,input [31:0] i_data_in
,input [3:0] i_data_valid_in
//output for 8b/10b encoder
,output [31:0] o_data_out
,output [3:0] o_datak_out
,input i_x1_mode
);
reg [31:0] r_data_out;
reg [3:0] r_datak_out;
reg [7:0] r_align_interval_cnt;
reg [1:0] r_sof_byte_cnt;
always@(posedge i_clk or negedge i_rst_n) begin
if (~i_rst_n) begin
//default send K28.5
r_data_out <= `DELAY {4{`CHAR_I}}; //32'hBC_BC_BC_BC;
r_datak_out <= `DELAY 4'hF;
end
else begin
if(i_data_valid_in) begin
if(i_sof_in) begin
if(r_sof_byte_cnt == 2'd0) begin
//|S|
r_data_out <= `DELAY {4{`CHAR_S}}; //32'hFB_FB_FB_FB;
r_datak_out <= `DELAY 4'hF;
end
else if(r_sof_byte_cnt == 2'd1) begin
r_data_out[7:0] <= `DELAY `CHAR_A;
r_datak_out[0] <= `DELAY 1'b1;
end
else if(r_sof_byte_cnt == 2'd2) begin
r_data_out[7:0] <= `DELAY 8'h55;
r_datak_out[0] <= `DELAY 1'b0;
end
else if(r_sof_byte_cnt == 2'd3) begin
r_data_out[7:0] <= `DELAY 8'h00;
r_datak_out[0] <= `DELAY 1'b0;
end
end
else begin
//Data
r_data_out <= `DELAY i_data_in;
r_datak_out <= `DELAY 4'h0;
end
end
else begin
// |A| is not inserted in X1 mode
if((r_align_interval_cnt == 8'h0) && (~i_x1_mode)) begin
//|A|
r_data_out <= `DELAY {4{`CHAR_A}}; //32'h7C_7C_7C_7C;
r_datak_out <= `DELAY 4'hF;
end
else begin
//|I|
r_data_out <= `DELAY {4{`CHAR_I}}; //32'hBC_BC_BC_BC;
r_datak_out <= `DELAY 4'hF;
end
end
end
end
//in x1 mode, lane1/2/3 all send idles
assign o_data_out = i_x1_mode ? { {3{`CHAR_I}}, r_data_out[7:0]} : r_data_out;
assign o_datak_out = i_x1_mode ? {3'b111, r_datak_out[0]} : r_datak_out;
//align interval cnt
always@(posedge i_clk or negedge i_rst_n) begin
if (~i_rst_n) begin
r_align_interval_cnt <= `DELAY AM_INTERVAL;
end
else begin
if(r_align_interval_cnt == 8'd0) begin
//reset the counter to 15 when /A/ is sent
//otherwise, keep it as '0'
if(~i_data_valid_in)
r_align_interval_cnt <= `DELAY AM_INTERVAL;
end
else
r_align_interval_cnt <= `DELAY r_align_interval_cnt - 8'd1;
end
end
//sof count, for x1 only
always@(posedge i_clk or negedge i_rst_n) begin
if (~i_rst_n) begin
r_sof_byte_cnt <= `DELAY 2'd0;
end
else begin
if(~i_x1_mode)
r_sof_byte_cnt <= `DELAY 2'd0;
else if(r_sof_byte_cnt == 2'd0) begin
if((i_data_valid_in && i_sof_in))
r_sof_byte_cnt <= `DELAY 2'd1;
end
else
r_sof_byte_cnt <= `DELAY r_sof_byte_cnt + 2'd1;
end
end
endmodule
| 6.61175 |
module tx_checkCurrentPacket_dev_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 7.081267 |
module tx_checkCurrentPacket_dev_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 7.081267 |
module tx_checkCurrentPacket_dev_regslice_forward #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
localparam W = DataWidth + 1;
wire [W-1:0] cdata;
wire cstop;
wire [W-1:0] idata;
wire istop;
wire [W-1:0] odata;
wire ostop;
tx_checkCurrentPacket_dev_regslice_obuf #(
.W(W)
) regslice_obuf_inst (
.clk (ap_clk),
.reset(ap_rst),
.cdata(idata),
.cstop(istop),
.odata(odata),
.ostop(ostop)
);
assign idata = {vld_in, data_in};
assign ack_in = ~istop;
assign vld_out = odata[W-1];
assign data_out = odata[W-2:0];
assign ostop = ~ack_out;
assign apdone_blk = ((ap_rst == 1'b0) & (1'b0 == ack_out) & (1'b1 == vld_out));
endmodule
| 7.081267 |
module tx_checkCurrentPacket_dev_regslice_forward_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
localparam W = 2;
wire [W-1:0] cdata;
wire cstop;
wire [W-1:0] idata;
wire istop;
wire [W-1:0] odata;
wire ostop;
tx_checkCurrentPacket_dev_regslice_obuf #(
.W(W)
) regslice_obuf_inst (
.clk (ap_clk),
.reset(ap_rst),
.cdata(idata),
.cstop(istop),
.odata(odata),
.ostop(ostop)
);
assign idata = {vld_in, data_in};
assign ack_in = ~istop;
assign vld_out = odata[W-1];
assign data_out = odata[W-2:0];
assign ostop = ~ack_out;
assign apdone_blk = ((ap_rst == 1'b0) & (1'b0 == ack_out) & (1'b1 == vld_out));
endmodule
| 7.081267 |
module tx_checkCurrentPacket_dev_regslice_obuf #(
parameter W = 32
) (
input clk,
input reset,
input [W-1:0] cdata,
output cstop,
output reg [W-1:0] odata,
input ostop
);
// Stop the core when buffer full and output not ready
assign cstop = reset ? 1'b1 : (odata[W-1] & ostop);
always @(posedge clk)
if (reset) odata <= {1'b0, {{W - 1} {1'b0}}};
else if (!cstop) begin // Can we accept more data?
odata <= cdata; // Yes: load the buffer
end
endmodule
| 7.081267 |
module tx_checkTimeout_dev_header_m_axi_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge sclk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge sclk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge sclk) begin
if (reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge sclk) begin
if (reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 6.500458 |
module tx_checkTimeout_dev_header_m_axi_fifo #(
parameter DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
) (
input wire sclk,
input wire reset,
input wire sclk_en,
output reg empty_n,
output reg full_n,
input wire rdreq,
input wire wrreq,
output reg [DATA_BITS-1:0] q,
input wire [DATA_BITS-1:0] data
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
wire push;
wire pop;
wire full_cond;
reg data_vld;
reg [DEPTH_BITS-1:0] pout;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign push = full_n & wrreq;
assign pop = data_vld & (~(empty_n & ~rdreq));
generate
if (DEPTH >= 2) begin
assign full_cond = push && ~pop && pout == DEPTH - 2 && data_vld;
end else begin
assign full_cond = push && ~pop;
end
endgenerate
// q
always @(posedge sclk) begin
if (reset) q <= 0;
else if (sclk_en) begin
if (~(empty_n & ~rdreq)) q <= mem[pout];
end
end
// empty_n
always @(posedge sclk) begin
if (reset) empty_n <= 1'b0;
else if (sclk_en) begin
if (~(empty_n & ~rdreq)) empty_n <= data_vld;
end
end
// data_vld
always @(posedge sclk) begin
if (reset) data_vld <= 1'b0;
else if (sclk_en) begin
if (push) data_vld <= 1'b1;
else if (~push && pop && pout == 1'b0) data_vld <= 1'b0;
end
end
// full_n
always @(posedge sclk) begin
if (reset) full_n <= 1'b1;
else if (sclk_en) begin
if (pop) full_n <= 1'b1;
else if (full_cond) full_n <= 1'b0;
end
end
// pout
always @(posedge sclk) begin
if (reset) pout <= 1'b0;
else if (sclk_en) begin
if (push & ~pop & data_vld) pout <= pout + 1'b1;
else if (~push && pop && pout != 1'b0) pout <= pout - 1'b1;
end
end
integer i;
always @(posedge sclk) begin
if (sclk_en) begin
if (push) begin
for (i = 0; i < DEPTH - 1; i = i + 1) begin
mem[i+1] <= mem[i];
end
mem[0] <= data;
end
end
end
endmodule
| 6.500458 |
module tx_checkTimeout_dev_header_m_axi_buffer #(
parameter MEM_STYLE = "block",
DATA_WIDTH = 32,
ADDR_WIDTH = 5,
DEPTH = 32
) (
// system signal
input wire clk,
input wire reset,
input wire sclk_en,
// write
output wire if_full_n,
input wire if_write_ce,
input wire if_write,
input wire [DATA_WIDTH-1:0] if_din,
// read
output wire if_empty_n,
input wire if_read_ce,
input wire if_read,
output wire [DATA_WIDTH-1:0] if_dout
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
(* ram_style = MEM_STYLE *)
reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
reg [DATA_WIDTH-1:0] q_buf = 1'b0;
reg [ADDR_WIDTH-1:0] waddr = 1'b0;
reg [ADDR_WIDTH-1:0] raddr = 1'b0;
wire [ADDR_WIDTH-1:0] wnext;
wire [ADDR_WIDTH-1:0] rnext;
wire push;
wire pop;
reg [ADDR_WIDTH-1:0] mOutPtr = 1'b0;
reg full_n = 1'b1;
reg empty_n = 1'b0;
reg [DATA_WIDTH-1:0] q_tmp = 1'b0;
reg show_ahead = 1'b0;
reg [DATA_WIDTH-1:0] dout_buf = 1'b0;
reg dout_valid = 1'b0;
//------------------------Instantiation------------------
//------------------------Task and function--------------
//------------------------Body---------------------------
assign if_full_n = full_n;
assign if_empty_n = dout_valid;
assign if_dout = dout_buf;
assign push = full_n & if_write_ce & (if_write === 1'b1);
assign pop = empty_n & if_read_ce & (~dout_valid | if_read);
assign wnext = !push ? waddr : (waddr == DEPTH - 1) ? 1'b0 : waddr + 1'b1;
assign rnext = !pop ? raddr : (raddr == DEPTH - 1) ? 1'b0 : raddr + 1'b1;
// waddr
always @(posedge clk) begin
if (reset == 1'b1) waddr <= 1'b0;
else if (sclk_en) waddr <= wnext;
end
// raddr
always @(posedge clk) begin
if (reset == 1'b1) raddr <= 1'b0;
else if (sclk_en) raddr <= rnext;
end
// mOutPtr
always @(posedge clk) begin
if (reset == 1'b1) mOutPtr <= 1'b0;
else if (sclk_en)
if (push & ~pop) mOutPtr <= mOutPtr + 1'b1;
else if (~push & pop) mOutPtr <= mOutPtr - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1) full_n <= 1'b1;
else if (sclk_en)
if (push & ~pop) full_n <= (mOutPtr != DEPTH - 1);
else if (~push & pop) full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1) empty_n <= 1'b0;
else if (sclk_en)
if (push & ~pop) empty_n <= 1'b1;
else if (~push & pop) empty_n <= (mOutPtr != 1'b1);
end
// mem
always @(posedge clk) begin
if (push) mem[waddr] <= if_din;
end
// q_buf
always @(posedge clk) begin
q_buf <= mem[rnext];
end
// q_tmp
always @(posedge clk) begin
if (reset == 1'b1) q_tmp <= 1'b0;
else if (sclk_en) if (push) q_tmp <= if_din;
end
// show_ahead
always @(posedge clk) begin
if (reset == 1'b1) show_ahead <= 1'b0;
else if (sclk_en)
if (push && mOutPtr == pop) show_ahead <= 1'b1;
else show_ahead <= 1'b0;
end
// dout_buf
always @(posedge clk) begin
if (reset == 1'b1) dout_buf <= 1'b0;
else if (sclk_en) if (pop) dout_buf <= show_ahead ? q_tmp : q_buf;
end
// dout_valid
always @(posedge clk) begin
if (reset == 1'b1) dout_valid <= 1'b0;
else if (sclk_en)
if (pop) dout_valid <= 1'b1;
else if (if_read_ce & if_read) dout_valid <= 1'b0;
end
endmodule
| 6.500458 |
module tx_checkTimeout_dev_header_m_axi_decoder #(
parameter DIN_WIDTH = 3
) (
input wire [ DIN_WIDTH-1:0] din,
output reg [2**DIN_WIDTH-1:0] dout
);
integer i;
always @(din) begin
dout = {2 ** DIN_WIDTH{1'b0}};
for (i = 0; i < din; i = i + 1) dout[i] = 1'b1;
end
endmodule
| 6.500458 |
module tx_checkTimeout_dev_mul_64ns_66ns_129_6_1_Multiplier_0 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [64 - 1 : 0] a;
input [66 - 1 : 0] b;
output [129 - 1 : 0] p;
reg [ 64 - 1 : 0] a_reg0;
reg [ 66 - 1 : 0] b_reg0;
wire [129 - 1 : 0] tmp_product;
reg [129 - 1 : 0] buff0;
reg [129 - 1 : 0] buff1;
reg [129 - 1 : 0] buff2;
reg [129 - 1 : 0] buff3;
assign p = buff3;
assign tmp_product = a_reg0 * b_reg0;
always @(posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
end
end
endmodule
| 6.500458 |
module tx_checkTimeout_dev_mul_64ns_66ns_129_6_1 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
tx_checkTimeout_dev_mul_64ns_66ns_129_6_1_Multiplier_0 tx_checkTimeout_dev_mul_64ns_66ns_129_6_1_Multiplier_0_U(
.clk(clk),
.ce (ce),
.a (din0),
.b (din1),
.p (dout)
);
endmodule
| 6.500458 |
module tx_checkTimeout_dev_mul_65s_67ns_131_6_1_Multiplier_1 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [65 - 1 : 0] a;
input [67 - 1 : 0] b;
output [131 - 1 : 0] p;
reg signed [65 - 1 : 0] a_reg0;
reg [67 - 1 : 0] b_reg0;
wire signed [131 - 1 : 0] tmp_product;
reg signed [131 - 1 : 0] buff0;
reg signed [131 - 1 : 0] buff1;
reg signed [131 - 1 : 0] buff2;
reg signed [131 - 1 : 0] buff3;
assign p = buff3;
assign tmp_product = a_reg0 * $signed({1'b0, b_reg0});
always @(posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
end
end
endmodule
| 6.500458 |
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