code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tm_testbench ();
localparam DATA_WIDTH_IN = 18;
localparam DATA_WIDTH_OUT = 18;
reg signed clk;
reg signed rst_n;
reg signed halt_ctrl;
reg signed [ 5:0] tm64_ctrl;
reg signed [DATA_WIDTH_IN-1:0] din_real;
reg signed [DATA_WIDTH_IN-1:0] din_imag;
always begin
#5 clk = ~clk;
end
initial begin
clk = 1;
rst_n = 1;
halt_ctrl = 0;
tm64_ctrl = 0;
din_real = 0;
din_imag = 0;
#40 rst_n = 0;
#20 rst_n = 1;
#20 halt_ctrl <= 1;
tm64_ctrl <= 27;
din_real <= 10000;
din_imag <= -10000;
#10 tm64_ctrl <= 55;
din_real <= 10000;
din_imag <= -10000;
end
dif_radix2_64p_tm #(
.DATA_WIDTH_IN (18),
.DATA_WIDTH_OUT(18)
) tm (
.clk(clk),
.rst_n(rst_n),
.halt_ctrl(halt_ctrl),
.tm64_ctrl(tm64_ctrl),
.din_real(din_real),
.din_imag(din_imag),
.dout_real(),
.dout_imag()
);
endmodule
| 7.373333 |
module twiddle64_0 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
assign dout_rere = din_real;
assign dout_imim = 0;
assign dout_reim = 0;
assign dout_imre = din_imag;
endmodule
| 7.511271 |
module twiddle64_1 #(
parameter DATA_WIDTH = 14
) (
input signed [DATA_WIDTH-1:0] din_real,
input signed [DATA_WIDTH-1:0] din_imag,
output signed [DATA_WIDTH-1:0] dout_rere,
output signed [DATA_WIDTH-1:0] dout_imim,
output signed [DATA_WIDTH-1:0] dout_reim,
output signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real - (din_real >>> 4);
assign tmp1_rere = tmp0_rere - (tmp0_rere >>> 6);
assign dout_rere = tmp0_rere + (tmp1_rere >>> 4);
assign tmp0_imim = din_imag >>> 4;
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 2);
assign tmp2_imim = tmp1_imim + (tmp1_imim >>> 6);
assign dout_imim = tmp1_imim + (tmp2_imim >>> 2);
assign tmp0_imre = din_imag - (din_imag >>> 4);
assign tmp1_imre = tmp0_imre - (tmp0_imre >>> 6);
assign dout_imre = tmp0_imre + (tmp1_imre >>> 4);
assign tmp0_reim = din_real >>> 4;
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 2);
assign tmp2_reim = tmp1_reim + (tmp1_reim >>> 6);
assign dout_reim = tmp1_reim + (tmp2_reim >>> 2);
endmodule
| 6.918234 |
module twiddle64_2 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real + (din_real >>> 2);
assign tmp1_rere = tmp0_rere - (tmp0_rere >>> 6);
assign dout_rere = din_real - (tmp1_rere >>> 6);
assign tmp0_imim = din_imag >>> 3;
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 4);
assign tmp2_imim = tmp1_imim - (tmp1_imim >>> 4);
assign dout_imim = tmp1_imim + (tmp2_imim >>> 1);
assign tmp0_imre = din_imag + (din_imag >>> 2);
assign tmp1_imre = tmp0_imre - (tmp0_imre >>> 6);
assign dout_imre = din_imag - (tmp1_imre >>> 6);
assign tmp0_reim = din_real >>> 3;
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 4);
assign tmp2_reim = tmp1_reim - (tmp1_reim >>> 4);
assign dout_reim = tmp1_reim + (tmp2_reim >>> 1);
endmodule
| 7.168156 |
module twiddle64_3 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real - (din_real >>> 5);
assign tmp1_rere = tmp0_rere + (tmp0_rere >>> 8);
assign dout_rere = tmp1_rere - (din_real >>> 6);
assign tmp0_imim = din_imag + (din_imag >>> 2);
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 5);
assign dout_imim = (din_imag >>> 2) + (tmp1_imim >>> 5);
assign tmp0_imre = din_imag - (din_imag >>> 5);
assign tmp1_imre = tmp0_imre + (tmp0_imre >>> 8);
assign dout_imre = tmp1_imre - (din_imag >>> 6);
assign tmp0_reim = din_real + (din_real >>> 2);
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 5);
assign dout_reim = (din_real >>> 2) + (tmp1_reim >>> 5);
endmodule
| 7.472133 |
module twiddle64_4 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real - (din_real >>> 3);
assign tmp1_rere = din_real + (tmp0_rere >>> 2);
assign dout_rere = din_real - (tmp1_rere >>> 4);
assign tmp0_imim = din_imag + (din_imag >>> 1);
assign tmp1_imim = tmp0_imim - (tmp0_imim >>> 11);
assign dout_imim = (din_imag >>> 7) + (tmp1_imim >>> 2);
assign tmp0_imre = din_imag - (din_imag >>> 3);
assign tmp1_imre = din_imag + (tmp0_imre >>> 2);
assign dout_imre = din_imag - (tmp1_imre >>> 4);
assign tmp0_reim = din_real + (din_real >>> 1);
assign tmp1_reim = tmp0_reim - (tmp0_reim >>> 11);
assign dout_reim = (din_real >>> 7) + (tmp1_reim >>> 2);
endmodule
| 7.362297 |
module twiddle64_5 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp3_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
wire signed [DATA_WIDTH:0] tmp3_reim;
assign tmp0_rere = din_real + (din_real >>> 7);
assign tmp1_rere = tmp0_rere - (tmp0_rere >>> 3);
assign dout_rere = tmp1_rere + (din_real >>> 14);
assign tmp0_imim = din_imag >>> 1;
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 2);
assign tmp2_imim = tmp1_imim + (tmp1_imim >>> 3);
assign tmp3_imim = (tmp2_imim >>> 6) - tmp1_imim;
assign dout_imim = (tmp3_imim >>> 2) + tmp1_imim;
assign tmp0_imre = din_imag + (din_imag >>> 7);
assign tmp1_imre = tmp0_imre - (tmp0_imre >>> 3);
assign dout_imre = tmp1_imre + (din_imag >>> 14);
assign tmp0_reim = din_real >>> 1;
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 2);
assign tmp2_reim = tmp1_reim + (tmp1_reim >>> 3);
assign tmp3_reim = (tmp2_reim >>> 6) - tmp1_reim;
assign dout_reim = (tmp3_reim >>> 2) + tmp1_reim;
endmodule
| 7.181315 |
module twiddle64_6 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp2_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp2_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real + (din_real >>> 2);
assign tmp1_rere = tmp0_rere - (tmp0_rere >>> 5);
assign tmp2_rere = tmp0_rere + (tmp1_rere >>> 4);
assign dout_rere = (din_real >>> 1) + (tmp2_rere >>> 2);
assign tmp0_imim = din_imag >>> 1;
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 6);
assign tmp2_imim = tmp1_imim - (tmp1_imim >>> 3);
assign dout_imim = tmp0_imim + (tmp2_imim >>> 3);
assign tmp0_imre = din_imag + (din_imag >>> 2);
assign tmp1_imre = tmp0_imre - (tmp0_imre >>> 5);
assign tmp2_imre = tmp0_imre + (tmp1_imre >>> 4);
assign dout_imre = (din_imag >>> 1) + (tmp2_imre >>> 2);
assign tmp0_reim = din_real >>> 1;
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 6);
assign tmp2_reim = tmp1_reim - (tmp1_reim >>> 3);
assign dout_reim = tmp0_reim + (tmp2_reim >>> 3);
endmodule
| 6.972645 |
module twiddle64_7 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real - (din_real >>> 5);
assign tmp1_rere = tmp0_rere - (tmp0_rere >>> 4);
assign dout_rere = din_real - (tmp1_rere >>> 2);
assign tmp0_imim = din_imag + (din_imag >>> 4);
assign tmp1_imim = din_imag + (tmp0_imim >>> 7);
assign tmp2_imim = tmp1_imim + (tmp1_imim >>> 3);
assign dout_imim = tmp2_imim - (din_imag >>> 1);
assign tmp0_imre = din_imag - (din_imag >>> 5);
assign tmp1_imre = tmp0_imre - (tmp0_imre >>> 4);
assign dout_imre = din_imag - (tmp1_imre >>> 2);
assign tmp0_reim = din_real + (din_real >>> 4);
assign tmp1_reim = din_real + (tmp0_reim >>> 7);
assign tmp2_reim = tmp1_reim + (tmp1_reim >>> 3);
assign dout_reim = tmp2_reim - (din_real >>> 1);
endmodule
| 7.309479 |
module twiddle64_8 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp2_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp2_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real + (din_real >>> 6);
assign tmp1_rere = tmp0_rere + (tmp0_rere >>> 8);
assign tmp2_rere = (din_real >>> 4) + (din_real >>> 2);
assign dout_rere = tmp1_rere - tmp2_rere;
assign tmp0_imim = din_imag + (din_imag >>> 6);
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 8);
assign tmp2_imim = (din_imag >>> 4) + (din_imag >>> 2);
assign dout_imim = tmp1_imim - tmp2_imim;
assign tmp0_imre = din_imag + (din_imag >>> 6);
assign tmp1_imre = tmp0_imre + (tmp0_imre >>> 8);
assign tmp2_imre = (din_imag >>> 4) + (din_imag >>> 2);
assign dout_imre = tmp1_imre - tmp2_imre;
assign tmp0_reim = din_real + (din_real >>> 6);
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 8);
assign tmp2_reim = (din_real >>> 4) + (din_real >>> 2);
assign dout_reim = tmp1_reim - tmp2_reim;
endmodule
| 6.980159 |
module twiddle64_part2 #(
parameter DATA_WIDTH = 14,
parameter TWIDDLE = 0
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
input wire signed [ DATA_WIDTH:0] tmp0_rere,
input wire signed [ DATA_WIDTH:0] tmp0_imim,
input wire signed [ DATA_WIDTH:0] tmp0_reim,
input wire signed [ DATA_WIDTH:0] tmp0_imre,
input wire signed [ DATA_WIDTH:0] tmp1_rere,
input wire signed [ DATA_WIDTH:0] tmp1_imim,
input wire signed [ DATA_WIDTH:0] tmp1_reim,
input wire signed [ DATA_WIDTH:0] tmp1_imre,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
generate
case (TWIDDLE)
0: begin : const0
assign dout_rere = tmp1_rere;
assign dout_imim = tmp1_imim;
assign dout_reim = tmp1_reim;
assign dout_imre = tmp1_imre;
end
1: begin : const1
assign dout_rere = tmp0_rere + (tmp1_rere >>> 4);
assign dout_imim = tmp0_imim + (tmp1_imim >>> 2);
assign dout_imre = tmp0_imre + (tmp1_imre >>> 4);
assign dout_reim = tmp0_reim + (tmp1_reim >>> 2);
end
2: begin : const2
assign dout_rere = din_real - (tmp1_rere >>> 6);
assign dout_imim = tmp0_imim + (tmp1_imim >>> 1);
assign dout_imre = din_imag - (tmp1_imre >>> 6);
assign dout_reim = tmp0_reim + (tmp1_reim >>> 1);
end
3: begin : const3
assign dout_rere = tmp1_rere - (din_real >>> 6);
assign dout_imim = (din_imag >>> 2) + (tmp1_imim >>> 5);
assign dout_imre = tmp1_imre - (din_imag >>> 6);
assign dout_reim = (din_real >>> 2) + (tmp1_reim >>> 5);
end
4: begin : const4
assign dout_rere = din_real - (tmp1_rere >>> 4);
assign dout_imim = (din_imag >>> 7) + (tmp1_imim >>> 2);
assign dout_imre = din_imag - (tmp1_imre >>> 4);
assign dout_reim = (din_real >>> 7) + (tmp1_reim >>> 2);
end
5: begin : const5
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign dout_rere = tmp1_rere + (din_real >>> 14);
assign tmp2_imim = (tmp1_imim >>> 6) - tmp0_imim;
assign dout_imim = (tmp2_imim >>> 2) + tmp0_imim;
assign dout_imre = tmp1_imre + (din_imag >>> 14);
assign tmp2_reim = (tmp1_reim >>> 6) - tmp0_reim;
assign dout_reim = (tmp2_reim >>> 2) + tmp0_reim;
end
6: begin : const6
wire signed [DATA_WIDTH:0] tmp2_rere;
wire signed [DATA_WIDTH:0] tmp2_imre;
assign tmp2_rere = tmp0_rere + (tmp1_rere >>> 4);
assign dout_rere = (din_real >>> 1) + (tmp2_rere >>> 2);
assign dout_imim = (din_imag >>> 1) + (tmp1_imim >>> 3);
assign tmp2_imre = tmp0_imre + (tmp1_imre >>> 4);
assign dout_imre = (din_imag >>> 1) + (tmp2_imre >>> 2);
assign dout_reim = (din_real >>> 1) + (tmp1_reim >>> 3);
end
7: begin : const7
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign dout_rere = din_real - (tmp1_rere >>> 2);
assign tmp2_imim = tmp1_imim + (tmp1_imim >>> 3);
assign dout_imim = tmp2_imim - (din_imag >>> 1);
assign dout_imre = din_imag - (tmp1_imre >>> 2);
assign tmp2_reim = tmp1_reim + (tmp1_reim >>> 3);
assign dout_reim = tmp2_reim - (din_real >>> 1);
end
8: begin : const8
wire signed [DATA_WIDTH:0] tmp2_rere;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp2_imre;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp2_rere = (din_real >>> 4) + (din_real >>> 2);
assign dout_rere = tmp1_rere - tmp2_rere;
assign tmp2_imim = (din_imag >>> 4) + (din_imag >>> 2);
assign dout_imim = tmp1_imim - tmp2_imim;
assign tmp2_imre = (din_imag >>> 4) + (din_imag >>> 2);
assign dout_imre = tmp1_imre - tmp2_imre;
assign tmp2_reim = (din_real >>> 4) + (din_real >>> 2);
assign dout_reim = tmp1_reim - tmp2_reim;
end
endcase
endgenerate
endmodule
| 6.796218 |
module TNBUFFX16 (
INP,
ENB,
Z
);
input INP;
input ENB;
output Z;
bufif1 U0 (Z, INP, ENB);
specify
specparam
tdelay_INP_Z_01_0=0.01,
tdelay_INP_Z_10_0=0.01,
tdelay_ENB_Z_Z1_0=0.01,
tdelay_ENB_Z_Z0_0=0.01,
tdelay_ENB_Z_01_0=0.01,
tdelay_ENB_Z_10_0=0.01;
(INP + => Z) = (tdelay_INP_Z_01_0, tdelay_INP_Z_10_0);
(ENB => Z)=(tdelay_ENB_Z_Z1_0, tdelay_ENB_Z_Z0_0, tdelay_ENB_Z_Z1_0, tdelay_ENB_Z_Z1_0, tdelay_ENB_Z_Z0_0, tdelay_ENB_Z_Z0_0);
endspecify
endmodule
| 6.546464 |
module TNBUFFX8 (
INP,
ENB,
Z
);
input INP;
input ENB;
output Z;
bufif1 U0 (Z, INP, ENB);
specify
specparam
tdelay_INP_Z_01_0=0.01,
tdelay_INP_Z_10_0=0.01,
tdelay_ENB_Z_Z1_0=0.01,
tdelay_ENB_Z_Z0_0=0.01,
tdelay_ENB_Z_01_0=0.01,
tdelay_ENB_Z_10_0=0.01;
(INP + => Z) = (tdelay_INP_Z_01_0, tdelay_INP_Z_10_0);
(ENB => Z)=(tdelay_ENB_Z_Z1_0, tdelay_ENB_Z_Z0_0, tdelay_ENB_Z_Z1_0, tdelay_ENB_Z_Z1_0, tdelay_ENB_Z_Z0_0, tdelay_ENB_Z_Z0_0);
endspecify
endmodule
| 6.58734 |
module TNKIIICoreClocks_Cen (
input wire i_clk,
output wire clk_13p4_cen,
output wire clk_13p4,
output wire clk_13p4b_cen,
output wire clk_13p4b,
output wire clk_6p7_cen,
output wire clk_6p7b_cen,
output wire clk_3p35_cen,
output wire clk_3p35b_cen,
output wire clk_4_cen,
output wire clk_4b_cen
);
reg ck_stb1 = 1'b0;
reg ck_stb2 = 1'b0;
reg ck_stb3 = 1'b0;
reg ck_stb4 = 1'b0;
reg ck_stb5 = 1'b0;
reg ck_stb6 = 1'b0;
reg ck_stb7 = 1'b0;
reg ck_stb8 = 1'b0;
//--------- 13.4 MHz ---------
reg [3:0] counter1 = 4'h4; //16'hC000
reg clk_13p4_r = 0;
reg [3:0] counter2 = 4'hC; //16'h4000
reg clk_13p4b_r = 0;
//-------- 6.7 MHz ---------
reg [3:0] counter3 = 4'hE; //16'hE000
reg [3:0] counter4 = 4'h6; //16'h6000
//-------- 3.35 MHz---------
reg [3:0] counter5 = 4'hF; //16'hF000
reg [3:0] counter6 = 4'h7; //16'h7000
//---3---- 4 MHz ------------
reg [15:0] counter7 = 16'd63583;
reg [15:0] counter8 = 16'd30815;
//--------- 13.4 MHz ---------
always @(negedge i_clk) begin
{ck_stb1, counter1} <= counter1 + 4'h4; //13.4MHz
end
assign clk_13p4_cen = ck_stb1;
always @(posedge i_clk)
if (clk_13p4_cen || clk_13p4b_cen) begin
clk_13p4_r <= ~clk_13p4_r;
clk_13p4b_r <= ~clk_13p4b_r;
end
assign clk_13p4 = clk_13p4_r;
assign clk_13p4b = clk_13p4b_r;
always @(negedge i_clk) begin
{ck_stb2, counter2} <= counter2 + 4'h4; //13.4MHz 180degrees shifted
end
assign clk_13p4b_cen = ck_stb2;
//--------- 6.7 MHz ----------
always @(negedge i_clk) begin
{ck_stb3, counter3} <= counter3 + 4'h2; //6.7MHz
end
always @(negedge i_clk) begin
{ck_stb4, counter4} <= counter4 + 4'h2; //6.7MHz 180 degrees shifted
end
assign clk_6p7_cen = ck_stb3;
assign clk_6p7b_cen = ck_stb4;
//--------- 3.35 MHz ---------
always @(negedge i_clk) begin
{ck_stb5, counter5} <= counter5 + 4'h1; //3.35MHz
end
always @(negedge i_clk) begin
{ck_stb6, counter6} <= counter6 + 4'h1; //3.35MHz 180 degrees shifted
end
assign clk_3p35_cen = ck_stb5;
assign clk_3p35b_cen = ck_stb6;
//--------- 4 MHz ------------
always @(negedge i_clk) begin
{ck_stb7, counter7} <= counter7 + 16'd4891; //4MHz
end
always @(negedge i_clk) begin
{ck_stb8, counter8} <= counter8 + 16'd4891; //4MHz 180 degrees shifted
end
assign clk_4_cen = ck_stb7;
assign clk_4b_cen = ck_stb8;
endmodule
| 7.267132 |
module receives scan code, and returns corresponding ASCII code.
module toASCII(
input [7:0]data,
output [7:0]asdata
);
(* ram_init_file = "ascii.mif" *)reg [7:0] toascii [255:0];
assign asdata = toascii[data];
//ROM
endmodule
| 7.18918 |
module TODO (
input reloj,
input resetM,
input Boton_B,
input Boton_R,
input Boton_G,
output [3:0] R,
output [3:0] G,
output [3:0] B,
output H_Sync,
output V_Sync,
output H_Sync2,
output V_Sync2,
output BIT_FUENTE,
output H_ON,
output V_ON,
output R2,
output G2,
output B2
);
wire [9:0] Qv;
wire [9:0] Qh;
counter inst_counter (
.Qh(Qh),
.Qv(Qv),
.H_Sync(H_Sync),
.V_Sync(V_Sync),
.V_ON(V_ON),
.H_ON(H_ON),
.resetM(resetM),
.reloj(reloj),
.H_Sync2(H_Sync2),
.V_Sync2(V_Sync2)
);
Posicion_Mosaicos inst_Mosaico (
.Qv(Qv),
.Qh(Qh),
.resetM(resetM),
.reloj(reloj),
.wire_BIT_FUENTE(BIT_FUENTE)
);
RGB1 inst_RGB1 (
.R(R),
.G(G),
.B(B),
.BotonR(Boton_R),
.BotonG(Boton_G),
.BotonB(Boton_B),
.BIT_FUENTE(BIT_FUENTE),
.H_ON(H_ON),
.V_ON(V_ON),
.R2(R2),
.B2(B2),
.G2(G2)
);
endmodule
| 7.449721 |
module TODO_tb(
);
reg reloj;
reg resetM;
reg Boton_B,Boton_R,Boton_G;
<<<<<<< HEAD
wire H_Sync,H_Sync2,V_Sync,V_Sync2,BIT_FUENTE,H_ON,V_ON,R2,G2,B2;
=======
wire H_Sync,V_Sync,BIT_FUENTE,H_ON,V_ON;
>>>>>>> 577cc9a1689b628be444f2603bb3fba1a29a7b4d
wire [3:0] R;
wire [3:0] G;
wire [3:0] B;
wire [9:0] Qv;
wire [9:0] Qh;
counter inst_counter(
.Qh(Qh),
.Qv(Qv),
.H_Sync(H_Sync),
.V_Sync(V_Sync),
.V_ON(V_ON),
.H_ON(H_ON),
.resetM(resetM),
<<<<<<< HEAD
.reloj(reloj),
.H_Sync2(H_Sync2),
.V_Sync2(V_Sync2)
=======
.reloj(reloj)
>>>>>>> 577cc9a1689b628be444f2603bb3fba1a29a7b4d
);
Posicion_Mosaicos inst_Mosaico(
.Qv(Qv),
.Qh(Qh),
.resetM(resetM),
.reloj(reloj),
.wire_BIT_FUENTE(BIT_FUENTE)
);
RGB1 inst_RGB1(
.R(R),
.G(G),
.B(B),
.BotonR(Boton_R),
.BotonG(Boton_G),
.BotonB(Boton_B),
.BIT_FUENTE(BIT_FUENTE),
.H_ON(H_ON),
<<<<<<< HEAD
.V_ON(V_ON),
.R2(R2),
.B2(B2),
.G2(G2)
=======
.V_ON(V_ON)
>>>>>>> 577cc9a1689b628be444f2603bb3fba1a29a7b4d
);
initial
begin
reloj= 0 ;
resetM = 1;
Boton_R = 1'b0;
Boton_G = 1'b0;
Boton_B = 1'b0;
#100 resetM = 0;
#1000 Boton_R = 1'b1;
#5000 Boton_B = 1'b1;
#19000000 resetM = 1'b1;
end
always
begin
#5 reloj = ~reloj;
end
endmodule
| 7.108934 |
module toe_ack_delay_ack_table_V_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_ack_delay_ack_table_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
end
end
end
endmodule
| 8.242296 |
module toe_ack_delay_ack_table_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
toe_ack_delay_ack_table_V_ram toe_ack_delay_ack_table_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1)
);
endmodule
| 8.242296 |
module toe_ap_rst_if #(
parameter RESET_ACTIVE_LOW = 0
) (
input wire din,
output wire dout
);
assign dout = (RESET_ACTIVE_LOW == 1) ? ~din : din;
endmodule
| 8.492718 |
module toe_free_port_table_freePortTable_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 1;
parameter AWIDTH = 15;
parameter MEM_SIZE = 32768;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_free_port_table_freePortTable_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
end
end
end
endmodule
| 7.440096 |
module toe_free_port_table_freePortTable (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd32768;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
toe_free_port_table_freePortTable_ram toe_free_port_table_freePortTable_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1)
);
endmodule
| 7.440096 |
module toe_m_axis_listen_port_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [7:0] TDATA,
// User signals
input wire [0:0] listenPortRsp_V_din,
output wire listenPortRsp_V_full_n,
input wire listenPortRsp_V_write
);
//------------------------Local signal-------------------
// FIFO
wire [0:0] fifo_read;
wire [0:0] fifo_empty_n;
wire [0:0] listenPortRsp_V_dout;
wire [0:0] listenPortRsp_V_empty_n;
// register slice
wire [0:0] s_valid;
wire [0:0] s_ready;
wire [0:0] s_data;
wire [0:0] m_valid;
wire [0:0] m_ready;
wire [0:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_listen_port_rsp_reg_slice #(
.N(1)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// listenPortRsp_V_fifo
toe_m_axis_listen_port_rsp_fifo #(
.DATA_BITS (1),
.DEPTH_BITS(4)
) listenPortRsp_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(listenPortRsp_V_empty_n),
.full_n (listenPortRsp_V_full_n),
.read (fifo_read),
.write (listenPortRsp_V_write),
.dout (listenPortRsp_V_dout),
.din (listenPortRsp_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TVALID = m_valid;
assign TDATA = m_data[0:0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = fifo_empty_n;
assign m_ready = TREADY;
assign s_data = {listenPortRsp_V_dout};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_read = fifo_empty_n & s_ready;
assign fifo_empty_n = listenPortRsp_V_empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 8.287233 |
module toe_m_axis_listen_port_rsp_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 8.287233 |
module toe_m_axis_listen_port_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.287233 |
module toe_m_axis_notification_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [87:0] TDATA,
// User signals
input wire [80:0] notification_V_din,
output wire notification_V_full_n,
input wire notification_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [80:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [80:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_notification_reg_slice #(
.N(81)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[80:0];
// Register Slice
assign s_valid = notification_V_write;
assign m_ready = TREADY;
assign s_data = notification_V_din;
// User Signal
assign notification_V_full_n = s_ready;
endmodule
| 7.778493 |
module toe_m_axis_notification_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.778493 |
module toe_m_axis_open_conn_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [23:0] TDATA,
// User signals
input wire [16:0] openConnRsp_V_din,
output wire openConnRsp_V_full_n,
input wire openConnRsp_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [16:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [16:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_open_conn_rsp_reg_slice #(
.N(17)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[16:0];
// Register Slice
assign s_valid = openConnRsp_V_write;
assign m_ready = TREADY;
assign s_data = openConnRsp_V_din;
// User Signal
assign openConnRsp_V_full_n = s_ready;
endmodule
| 8.959194 |
module toe_m_axis_open_conn_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.959194 |
module toe_m_axis_rxread_cmd_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [71:0] TDATA,
// User signals
input wire [71:0] rxBufferReadCmd_V_din,
output wire rxBufferReadCmd_V_full_n,
input wire rxBufferReadCmd_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [71:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [71:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_rxread_cmd_reg_slice #(
.N(72)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[71:0];
// Register Slice
assign s_valid = rxBufferReadCmd_V_write;
assign m_ready = TREADY;
assign s_data = rxBufferReadCmd_V_din;
// User Signal
assign rxBufferReadCmd_V_full_n = s_ready;
endmodule
| 8.494329 |
module toe_m_axis_rxread_cmd_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.494329 |
module toe_m_axis_rxwrite_cmd_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [71:0] TDATA,
// User signals
input wire [71:0] rxBufferWriteCmd_V_din,
output wire rxBufferWriteCmd_V_full_n,
input wire rxBufferWriteCmd_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [71:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [71:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_rxwrite_cmd_reg_slice #(
.N(72)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[71:0];
// Register Slice
assign s_valid = rxBufferWriteCmd_V_write;
assign m_ready = TREADY;
assign s_data = rxBufferWriteCmd_V_din;
// User Signal
assign rxBufferWriteCmd_V_full_n = s_ready;
endmodule
| 8.494329 |
module toe_m_axis_rxwrite_cmd_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.494329 |
module toe_m_axis_rxwrite_data_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 8.494329 |
module toe_m_axis_rxwrite_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.494329 |
module toe_m_axis_rx_data_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
output wire [ 7:0] TKEEP,
output wire [ 0:0] TLAST,
// User signals
input wire [63:0] rxDataRsp_V_data_V_din,
output wire rxDataRsp_V_data_V_full_n,
input wire rxDataRsp_V_data_V_write,
input wire [ 7:0] rxDataRsp_V_keep_V_din,
output wire rxDataRsp_V_keep_V_full_n,
input wire rxDataRsp_V_keep_V_write,
input wire [ 0:0] rxDataRsp_V_last_V_din,
output wire rxDataRsp_V_last_V_full_n,
input wire rxDataRsp_V_last_V_write
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_read;
wire [ 0:0] fifo_empty_n;
wire [63:0] rxDataRsp_V_data_V_dout;
wire [ 0:0] rxDataRsp_V_data_V_empty_n;
wire [ 7:0] rxDataRsp_V_keep_V_dout;
wire [ 0:0] rxDataRsp_V_keep_V_empty_n;
wire [ 0:0] rxDataRsp_V_last_V_dout;
wire [ 0:0] rxDataRsp_V_last_V_empty_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [72:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [72:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_rx_data_rsp_reg_slice #(
.N(73)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// rxDataRsp_V_data_V_fifo
toe_m_axis_rx_data_rsp_fifo #(
.DATA_BITS (64),
.DEPTH_BITS(4)
) rxDataRsp_V_data_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(rxDataRsp_V_data_V_empty_n),
.full_n (rxDataRsp_V_data_V_full_n),
.read (fifo_read),
.write (rxDataRsp_V_data_V_write),
.dout (rxDataRsp_V_data_V_dout),
.din (rxDataRsp_V_data_V_din)
);
// rxDataRsp_V_keep_V_fifo
toe_m_axis_rx_data_rsp_fifo #(
.DATA_BITS (8),
.DEPTH_BITS(4)
) rxDataRsp_V_keep_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(rxDataRsp_V_keep_V_empty_n),
.full_n (rxDataRsp_V_keep_V_full_n),
.read (fifo_read),
.write (rxDataRsp_V_keep_V_write),
.dout (rxDataRsp_V_keep_V_dout),
.din (rxDataRsp_V_keep_V_din)
);
// rxDataRsp_V_last_V_fifo
toe_m_axis_rx_data_rsp_fifo #(
.DATA_BITS (1),
.DEPTH_BITS(4)
) rxDataRsp_V_last_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(rxDataRsp_V_last_V_empty_n),
.full_n (rxDataRsp_V_last_V_full_n),
.read (fifo_read),
.write (rxDataRsp_V_last_V_write),
.dout (rxDataRsp_V_last_V_dout),
.din (rxDataRsp_V_last_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TVALID = m_valid;
assign TDATA = m_data[63:0];
assign TKEEP = m_data[71:64];
assign TLAST = m_data[72:72];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = fifo_empty_n;
assign m_ready = TREADY;
assign s_data = {rxDataRsp_V_last_V_dout, rxDataRsp_V_keep_V_dout, rxDataRsp_V_data_V_dout};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_read = fifo_empty_n & s_ready;
assign fifo_empty_n = rxDataRsp_V_data_V_empty_n & rxDataRsp_V_keep_V_empty_n & rxDataRsp_V_last_V_empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 8.494329 |
module toe_m_axis_rx_data_rsp_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 8.494329 |
module toe_m_axis_rx_data_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.494329 |
module toe_m_axis_rx_data_rsp_metadata_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [15:0] TDATA,
// User signals
input wire [15:0] rxDataRspMeta_V_V_din,
output wire rxDataRspMeta_V_V_full_n,
input wire rxDataRspMeta_V_V_write
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_read;
wire [ 0:0] fifo_empty_n;
wire [15:0] rxDataRspMeta_V_V_dout;
wire [ 0:0] rxDataRspMeta_V_V_empty_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [15:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [15:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_rx_data_rsp_metadata_reg_slice #(
.N(16)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// rxDataRspMeta_V_V_fifo
toe_m_axis_rx_data_rsp_metadata_fifo #(
.DATA_BITS (16),
.DEPTH_BITS(4)
) rxDataRspMeta_V_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(rxDataRspMeta_V_V_empty_n),
.full_n (rxDataRspMeta_V_V_full_n),
.read (fifo_read),
.write (rxDataRspMeta_V_V_write),
.dout (rxDataRspMeta_V_V_dout),
.din (rxDataRspMeta_V_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TVALID = m_valid;
assign TDATA = m_data[15:0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = fifo_empty_n;
assign m_ready = TREADY;
assign s_data = {rxDataRspMeta_V_V_dout};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_read = fifo_empty_n & s_ready;
assign fifo_empty_n = rxDataRspMeta_V_V_empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 8.494329 |
module toe_m_axis_rx_data_rsp_metadata_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 8.494329 |
module toe_m_axis_rx_data_rsp_metadata_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.494329 |
module toe_m_axis_session_lup_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [103:0] TDATA,
// User signals
input wire [ 96:0] sessionLookup_req_V_din,
output wire sessionLookup_req_V_full_n,
input wire sessionLookup_req_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [96:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [96:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_session_lup_req_reg_slice #(
.N(97)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[96:0];
// Register Slice
assign s_valid = sessionLookup_req_V_write;
assign m_ready = TREADY;
assign s_data = sessionLookup_req_V_din;
// User Signal
assign sessionLookup_req_V_full_n = s_ready;
endmodule
| 7.910423 |
module toe_m_axis_session_lup_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.910423 |
module toe_m_axis_session_upd_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [111:0] TDATA,
// User signals
input wire [111:0] sessionUpdate_req_V_din,
output wire sessionUpdate_req_V_full_n,
input wire sessionUpdate_req_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [111:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [111:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_session_upd_req_reg_slice #(
.N(112)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[111:0];
// Register Slice
assign s_valid = sessionUpdate_req_V_write;
assign m_ready = TREADY;
assign s_data = sessionUpdate_req_V_din;
// User Signal
assign sessionUpdate_req_V_full_n = s_ready;
endmodule
| 7.910423 |
module toe_m_axis_session_upd_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.910423 |
module toe_m_axis_tcp_data_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
output wire [ 7:0] TKEEP,
output wire [ 0:0] TLAST,
// User signals
input wire [72:0] ipTxData_V_din,
output wire ipTxData_V_full_n,
input wire ipTxData_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [72:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [72:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_tcp_data_reg_slice #(
.N(73)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[63:0];
assign TKEEP = m_data[71:64];
assign TLAST = m_data[72:72];
// Register Slice
assign s_valid = ipTxData_V_write;
assign m_ready = TREADY;
assign s_data = ipTxData_V_din;
// User Signal
assign ipTxData_V_full_n = s_ready;
endmodule
| 7.873669 |
module toe_m_axis_tcp_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.873669 |
module toe_m_axis_txread_cmd_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [71:0] TDATA,
// User signals
input wire [71:0] txBufferReadCmd_V_din,
output wire txBufferReadCmd_V_full_n,
input wire txBufferReadCmd_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [71:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [71:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_txread_cmd_reg_slice #(
.N(72)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[71:0];
// Register Slice
assign s_valid = txBufferReadCmd_V_write;
assign m_ready = TREADY;
assign s_data = txBufferReadCmd_V_din;
// User Signal
assign txBufferReadCmd_V_full_n = s_ready;
endmodule
| 8.66842 |
module toe_m_axis_txread_cmd_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.66842 |
module toe_m_axis_txwrite_cmd_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [71:0] TDATA,
// User signals
input wire [71:0] txBufferWriteCmd_V_din,
output wire txBufferWriteCmd_V_full_n,
input wire txBufferWriteCmd_V_write
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [71:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [71:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_txwrite_cmd_reg_slice #(
.N(72)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TVALID = m_valid;
assign TDATA = m_data[71:0];
// Register Slice
assign s_valid = txBufferWriteCmd_V_write;
assign m_ready = TREADY;
assign s_data = txBufferWriteCmd_V_din;
// User Signal
assign txBufferWriteCmd_V_full_n = s_ready;
endmodule
| 8.66842 |
module toe_m_axis_txwrite_cmd_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.66842 |
module toe_m_axis_txwrite_data_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 8.66842 |
module toe_m_axis_txwrite_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.66842 |
module toe_m_axis_tx_data_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [23:0] TDATA,
// User signals
input wire [16:0] txDataRsp_V_V_din,
output wire txDataRsp_V_V_full_n,
input wire txDataRsp_V_V_write
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_read;
wire [ 0:0] fifo_empty_n;
wire [16:0] txDataRsp_V_V_dout;
wire [ 0:0] txDataRsp_V_V_empty_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [16:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [16:0] m_data;
//------------------------Instantiation------------------
// rs
toe_m_axis_tx_data_rsp_reg_slice #(
.N(17)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// txDataRsp_V_V_fifo
toe_m_axis_tx_data_rsp_fifo #(
.DATA_BITS (17),
.DEPTH_BITS(4)
) txDataRsp_V_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(txDataRsp_V_V_empty_n),
.full_n (txDataRsp_V_V_full_n),
.read (fifo_read),
.write (txDataRsp_V_V_write),
.dout (txDataRsp_V_V_dout),
.din (txDataRsp_V_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TVALID = m_valid;
assign TDATA = m_data[16:0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = fifo_empty_n;
assign m_ready = TREADY;
assign s_data = {txDataRsp_V_V_dout};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_read = fifo_empty_n & s_ready;
assign fifo_empty_n = txDataRsp_V_V_empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 8.66842 |
module toe_m_axis_tx_data_rsp_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 8.66842 |
module toe_m_axis_tx_data_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.66842 |
module toe_probe_timer_probeTimerTable_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 33;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_probe_timer_probeTimerTable_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
end
end
end
endmodule
| 6.885215 |
module toe_probe_timer_probeTimerTable (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd33;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
toe_probe_timer_probeTimerTable_ram toe_probe_timer_probeTimerTable_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1)
);
endmodule
| 6.885215 |
module toe_rx_sar_table_rx_table_appd_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_rx_sar_table_rx_table_appd_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 7.224988 |
module toe_rx_sar_table_rx_table_appd_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
toe_rx_sar_table_rx_table_appd_V_ram toe_rx_sar_table_rx_table_appd_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 7.224988 |
module toe_rx_sar_table_rx_table_recvd_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_rx_sar_table_rx_table_recvd_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 7.224988 |
module toe_rx_sar_table_rx_table_recvd_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
toe_rx_sar_table_rx_table_recvd_V_ram toe_rx_sar_table_rx_table_recvd_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 7.224988 |
module toe_state_table_state_table_1_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 4;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_state_table_state_table_1_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
end
end
end
endmodule
| 7.135654 |
module toe_state_table_state_table_1 (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
toe_state_table_state_table_1_ram toe_state_table_state_table_1_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1)
);
endmodule
| 7.135654 |
module toe_s_axis_close_conn_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] closeConnReq_V_V_dout,
output wire closeConnReq_V_V_empty_n,
input wire closeConnReq_V_V_read
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_write;
wire [ 0:0] fifo_full_n;
wire [15:0] closeConnReq_V_V_din;
wire [ 0:0] closeConnReq_V_V_full_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [15:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [15:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_close_conn_req_reg_slice #(
.N(16)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// closeConnReq_V_V_fifo
toe_s_axis_close_conn_req_fifo #(
.DATA_BITS (16),
.DEPTH_BITS(4)
) closeConnReq_V_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(closeConnReq_V_V_empty_n),
.full_n (closeConnReq_V_V_full_n),
.read (closeConnReq_V_V_read),
.write (fifo_write),
.dout (closeConnReq_V_V_dout),
.din (closeConnReq_V_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TREADY = s_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = TVALID;
assign m_ready = fifo_full_n;
assign s_data = {TDATA[15:0]};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_write = fifo_full_n & m_valid;
assign closeConnReq_V_V_din = m_data[15:0];
assign fifo_full_n = closeConnReq_V_V_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 8.260126 |
module toe_s_axis_close_conn_req_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 8.260126 |
module toe_s_axis_close_conn_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.260126 |
module toe_s_axis_listen_port_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] listenPortReq_V_V_dout,
output wire listenPortReq_V_V_empty_n,
input wire listenPortReq_V_V_read
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_write;
wire [ 0:0] fifo_full_n;
wire [15:0] listenPortReq_V_V_din;
wire [ 0:0] listenPortReq_V_V_full_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [15:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [15:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_listen_port_req_reg_slice #(
.N(16)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// listenPortReq_V_V_fifo
toe_s_axis_listen_port_req_fifo #(
.DATA_BITS (16),
.DEPTH_BITS(4)
) listenPortReq_V_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(listenPortReq_V_V_empty_n),
.full_n (listenPortReq_V_V_full_n),
.read (listenPortReq_V_V_read),
.write (fifo_write),
.dout (listenPortReq_V_V_dout),
.din (listenPortReq_V_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TREADY = s_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = TVALID;
assign m_ready = fifo_full_n;
assign s_data = {TDATA[15:0]};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_write = fifo_full_n & m_valid;
assign listenPortReq_V_V_din = m_data[15:0];
assign fifo_full_n = listenPortReq_V_V_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.814297 |
module toe_s_axis_listen_port_req_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 7.814297 |
module toe_s_axis_listen_port_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.814297 |
module toe_s_axis_open_conn_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [47:0] TDATA,
// User signals
output wire [47:0] openConnReq_V_dout,
output wire openConnReq_V_empty_n,
input wire openConnReq_V_read
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [47:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [47:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_open_conn_req_reg_slice #(
.N(48)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TREADY = s_ready;
// Register Slice
assign s_valid = TVALID;
assign m_ready = openConnReq_V_read;
assign s_data[47:0] = TDATA[47:0];
// User Signal
assign openConnReq_V_empty_n = m_valid;
assign openConnReq_V_dout = m_data;
endmodule
| 8.231243 |
module toe_s_axis_open_conn_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 8.231243 |
module toe_s_axis_rxread_data_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 7.789307 |
module toe_s_axis_rxread_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.789307 |
module toe_s_axis_rxwrite_sts_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [7:0] TDATA,
// User signals
output wire [7:0] rxBufferWriteStatus_V_dout,
output wire rxBufferWriteStatus_V_empty_n,
input wire rxBufferWriteStatus_V_read
);
//------------------------Local signal-------------------
// register slice
wire [0:0] s_valid;
wire [0:0] s_ready;
wire [7:0] s_data;
wire [0:0] m_valid;
wire [0:0] m_ready;
wire [7:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_rxwrite_sts_reg_slice #(
.N(8)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TREADY = s_ready;
// Register Slice
assign s_valid = TVALID;
assign m_ready = rxBufferWriteStatus_V_read;
assign s_data[7:0] = TDATA[7:0];
// User Signal
assign rxBufferWriteStatus_V_empty_n = m_valid;
assign rxBufferWriteStatus_V_dout = m_data;
endmodule
| 7.789307 |
module toe_s_axis_rxwrite_sts_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.789307 |
module toe_s_axis_rx_data_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [31:0] TDATA,
// User signals
output wire [31:0] rxDataReq_V_dout,
output wire rxDataReq_V_empty_n,
input wire rxDataReq_V_read
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [31:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [31:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_rx_data_req_reg_slice #(
.N(32)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TREADY = s_ready;
// Register Slice
assign s_valid = TVALID;
assign m_ready = rxDataReq_V_read;
assign s_data[31:0] = TDATA[31:0];
// User Signal
assign rxDataReq_V_empty_n = m_valid;
assign rxDataReq_V_dout = m_data;
endmodule
| 7.789307 |
module toe_s_axis_rx_data_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.789307 |
module toe_s_axis_session_lup_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] sessionLookup_rsp_V_dout,
output wire sessionLookup_rsp_V_empty_n,
input wire sessionLookup_rsp_V_read
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [15:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [15:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_session_lup_rsp_reg_slice #(
.N(16)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TREADY = s_ready;
// Register Slice
assign s_valid = TVALID;
assign m_ready = sessionLookup_rsp_V_read;
assign s_data[15:0] = TDATA[15:0];
// User Signal
assign sessionLookup_rsp_V_empty_n = m_valid;
assign sessionLookup_rsp_V_dout = m_data;
endmodule
| 7.981393 |
module toe_s_axis_session_lup_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.981393 |
module toe_s_axis_session_upd_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] sessionUpdate_rsp_V_dout,
output wire sessionUpdate_rsp_V_empty_n,
input wire sessionUpdate_rsp_V_read
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [15:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [15:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_session_upd_rsp_reg_slice #(
.N(16)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TREADY = s_ready;
// Register Slice
assign s_valid = TVALID;
assign m_ready = sessionUpdate_rsp_V_read;
assign s_data[15:0] = TDATA[15:0];
// User Signal
assign sessionUpdate_rsp_V_empty_n = m_valid;
assign sessionUpdate_rsp_V_dout = m_data;
endmodule
| 7.981393 |
module toe_s_axis_session_upd_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.981393 |
module toe_s_axis_tcp_data_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [63:0] TDATA,
input wire [ 7:0] TKEEP,
input wire [ 0:0] TLAST,
// User signals
output wire [63:0] ipRxData_V_data_V_dout,
output wire ipRxData_V_data_V_empty_n,
input wire ipRxData_V_data_V_read,
output wire [ 7:0] ipRxData_V_keep_V_dout,
output wire ipRxData_V_keep_V_empty_n,
input wire ipRxData_V_keep_V_read,
output wire [ 0:0] ipRxData_V_last_V_dout,
output wire ipRxData_V_last_V_empty_n,
input wire ipRxData_V_last_V_read
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_write;
wire [ 0:0] fifo_full_n;
wire [63:0] ipRxData_V_data_V_din;
wire [ 0:0] ipRxData_V_data_V_full_n;
wire [ 7:0] ipRxData_V_keep_V_din;
wire [ 0:0] ipRxData_V_keep_V_full_n;
wire [ 0:0] ipRxData_V_last_V_din;
wire [ 0:0] ipRxData_V_last_V_full_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [72:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [72:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_tcp_data_reg_slice #(
.N(73)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// ipRxData_V_data_V_fifo
toe_s_axis_tcp_data_fifo #(
.DATA_BITS (64),
.DEPTH_BITS(4)
) ipRxData_V_data_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(ipRxData_V_data_V_empty_n),
.full_n (ipRxData_V_data_V_full_n),
.read (ipRxData_V_data_V_read),
.write (fifo_write),
.dout (ipRxData_V_data_V_dout),
.din (ipRxData_V_data_V_din)
);
// ipRxData_V_keep_V_fifo
toe_s_axis_tcp_data_fifo #(
.DATA_BITS (8),
.DEPTH_BITS(4)
) ipRxData_V_keep_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(ipRxData_V_keep_V_empty_n),
.full_n (ipRxData_V_keep_V_full_n),
.read (ipRxData_V_keep_V_read),
.write (fifo_write),
.dout (ipRxData_V_keep_V_dout),
.din (ipRxData_V_keep_V_din)
);
// ipRxData_V_last_V_fifo
toe_s_axis_tcp_data_fifo #(
.DATA_BITS (1),
.DEPTH_BITS(4)
) ipRxData_V_last_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(ipRxData_V_last_V_empty_n),
.full_n (ipRxData_V_last_V_full_n),
.read (ipRxData_V_last_V_read),
.write (fifo_write),
.dout (ipRxData_V_last_V_dout),
.din (ipRxData_V_last_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TREADY = s_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = TVALID;
assign m_ready = fifo_full_n;
assign s_data = {TLAST[0:0], TKEEP[7:0], TDATA[63:0]};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_write = fifo_full_n & m_valid;
assign ipRxData_V_data_V_din = m_data[63:0];
assign ipRxData_V_keep_V_din = m_data[71:64];
assign ipRxData_V_last_V_din = m_data[72:72];
assign fifo_full_n = ipRxData_V_data_V_full_n & ipRxData_V_keep_V_full_n & ipRxData_V_last_V_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.593196 |
module toe_s_axis_tcp_data_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 7.593196 |
module toe_s_axis_tcp_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.593196 |
module toe_s_axis_txread_data_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [63:0] TDATA,
input wire [ 7:0] TKEEP,
input wire [ 0:0] TLAST,
// User signals
output wire [72:0] txBufferReadData_V_dout,
output wire txBufferReadData_V_empty_n,
input wire txBufferReadData_V_read
);
//------------------------Local signal-------------------
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [72:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [72:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_txread_data_reg_slice #(
.N(73)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TREADY = s_ready;
// Register Slice
assign s_valid = TVALID;
assign m_ready = txBufferReadData_V_read;
assign s_data[63:0] = TDATA[63:0];
assign s_data[71:64] = TKEEP[7:0];
assign s_data[72:72] = TLAST[0:0];
// User Signal
assign txBufferReadData_V_empty_n = m_valid;
assign txBufferReadData_V_dout = m_data;
endmodule
| 7.971983 |
module toe_s_axis_txread_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.971983 |
module toe_s_axis_txwrite_sts_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [7:0] TDATA,
// User signals
output wire [7:0] txBufferWriteStatus_V_dout,
output wire txBufferWriteStatus_V_empty_n,
input wire txBufferWriteStatus_V_read
);
//------------------------Local signal-------------------
// register slice
wire [0:0] s_valid;
wire [0:0] s_ready;
wire [7:0] s_data;
wire [0:0] m_valid;
wire [0:0] m_ready;
wire [7:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_txwrite_sts_reg_slice #(
.N(8)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
//------------------------Body---------------------------
// AXI4-Stream
assign TREADY = s_ready;
// Register Slice
assign s_valid = TVALID;
assign m_ready = txBufferWriteStatus_V_read;
assign s_data[7:0] = TDATA[7:0];
// User Signal
assign txBufferWriteStatus_V_empty_n = m_valid;
assign txBufferWriteStatus_V_dout = m_data;
endmodule
| 7.971983 |
module toe_s_axis_txwrite_sts_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.971983 |
module toe_s_axis_tx_data_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [63:0] TDATA,
input wire [ 7:0] TKEEP,
input wire [ 0:0] TLAST,
// User signals
output wire [63:0] txDataReq_V_data_V_dout,
output wire txDataReq_V_data_V_empty_n,
input wire txDataReq_V_data_V_read,
output wire [ 7:0] txDataReq_V_keep_V_dout,
output wire txDataReq_V_keep_V_empty_n,
input wire txDataReq_V_keep_V_read,
output wire [ 0:0] txDataReq_V_last_V_dout,
output wire txDataReq_V_last_V_empty_n,
input wire txDataReq_V_last_V_read
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_write;
wire [ 0:0] fifo_full_n;
wire [63:0] txDataReq_V_data_V_din;
wire [ 0:0] txDataReq_V_data_V_full_n;
wire [ 7:0] txDataReq_V_keep_V_din;
wire [ 0:0] txDataReq_V_keep_V_full_n;
wire [ 0:0] txDataReq_V_last_V_din;
wire [ 0:0] txDataReq_V_last_V_full_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [72:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [72:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_tx_data_req_reg_slice #(
.N(73)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// txDataReq_V_data_V_fifo
toe_s_axis_tx_data_req_fifo #(
.DATA_BITS (64),
.DEPTH_BITS(4)
) txDataReq_V_data_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(txDataReq_V_data_V_empty_n),
.full_n (txDataReq_V_data_V_full_n),
.read (txDataReq_V_data_V_read),
.write (fifo_write),
.dout (txDataReq_V_data_V_dout),
.din (txDataReq_V_data_V_din)
);
// txDataReq_V_keep_V_fifo
toe_s_axis_tx_data_req_fifo #(
.DATA_BITS (8),
.DEPTH_BITS(4)
) txDataReq_V_keep_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(txDataReq_V_keep_V_empty_n),
.full_n (txDataReq_V_keep_V_full_n),
.read (txDataReq_V_keep_V_read),
.write (fifo_write),
.dout (txDataReq_V_keep_V_dout),
.din (txDataReq_V_keep_V_din)
);
// txDataReq_V_last_V_fifo
toe_s_axis_tx_data_req_fifo #(
.DATA_BITS (1),
.DEPTH_BITS(4)
) txDataReq_V_last_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(txDataReq_V_last_V_empty_n),
.full_n (txDataReq_V_last_V_full_n),
.read (txDataReq_V_last_V_read),
.write (fifo_write),
.dout (txDataReq_V_last_V_dout),
.din (txDataReq_V_last_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TREADY = s_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = TVALID;
assign m_ready = fifo_full_n;
assign s_data = {TLAST[0:0], TKEEP[7:0], TDATA[63:0]};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_write = fifo_full_n & m_valid;
assign txDataReq_V_data_V_din = m_data[63:0];
assign txDataReq_V_keep_V_din = m_data[71:64];
assign txDataReq_V_last_V_din = m_data[72:72];
assign fifo_full_n = txDataReq_V_data_V_full_n & txDataReq_V_keep_V_full_n & txDataReq_V_last_V_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.971983 |
module toe_s_axis_tx_data_req_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 7.971983 |
module toe_s_axis_tx_data_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.971983 |
module toe_s_axis_tx_data_req_metadata_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] txDataReqMeta_V_V_dout,
output wire txDataReqMeta_V_V_empty_n,
input wire txDataReqMeta_V_V_read
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_write;
wire [ 0:0] fifo_full_n;
wire [15:0] txDataReqMeta_V_V_din;
wire [ 0:0] txDataReqMeta_V_V_full_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [15:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [15:0] m_data;
//------------------------Instantiation------------------
// rs
toe_s_axis_tx_data_req_metadata_reg_slice #(
.N(16)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// txDataReqMeta_V_V_fifo
toe_s_axis_tx_data_req_metadata_fifo #(
.DATA_BITS (16),
.DEPTH_BITS(4)
) txDataReqMeta_V_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(txDataReqMeta_V_V_empty_n),
.full_n (txDataReqMeta_V_V_full_n),
.read (txDataReqMeta_V_V_read),
.write (fifo_write),
.dout (txDataReqMeta_V_V_dout),
.din (txDataReqMeta_V_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TREADY = s_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = TVALID;
assign m_ready = fifo_full_n;
assign s_data = {TDATA[15:0]};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_write = fifo_full_n & m_valid;
assign txDataReqMeta_V_V_din = m_data[15:0];
assign fifo_full_n = txDataReqMeta_V_V_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.971983 |
module toe_s_axis_tx_data_req_metadata_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 7.971983 |
module toe_s_axis_tx_data_req_metadata_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.971983 |
module toe_tx_app_table_app_table_ackd_V_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_tx_app_table_app_table_ackd_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
end
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
q1 <= d1;
end else q1 <= ram[addr1];
end
end
endmodule
| 7.879755 |
module toe_tx_app_table_app_table_ackd_V (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
toe_tx_app_table_app_table_ackd_V_ram toe_tx_app_table_app_table_ackd_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1),
.q1(q1)
);
endmodule
| 7.879755 |
module toe_tx_sar_table_tx_table_app_V_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_tx_sar_table_tx_table_app_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
end
end
end
endmodule
| 7.363764 |
module toe_tx_sar_table_tx_table_app_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
toe_tx_sar_table_tx_table_app_V_ram toe_tx_sar_table_tx_table_app_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1)
);
endmodule
| 7.363764 |
module toe_tx_sar_table_tx_table_cong_window_V_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_tx_sar_table_tx_table_cong_window_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
q1 <= d1;
end else q1 <= ram[addr1];
end
end
endmodule
| 7.363764 |
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