code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module toe_tx_sar_table_tx_table_cong_window_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
toe_tx_sar_table_tx_table_cong_window_V_ram toe_tx_sar_table_tx_table_cong_window_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1),
.q1(q1)
);
endmodule
| 7.363764 |
module toe_tx_sar_table_tx_table_count_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_tx_sar_table_tx_table_count_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 7.363764 |
module toe_tx_sar_table_tx_table_count_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
toe_tx_sar_table_tx_table_count_V_ram toe_tx_sar_table_tx_table_count_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0)
);
endmodule
| 7.363764 |
module toe_tx_sar_table_tx_table_not_ackd_V_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_tx_sar_table_tx_table_not_ackd_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 7.363764 |
module toe_tx_sar_table_tx_table_not_ackd_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
toe_tx_sar_table_tx_table_not_ackd_V_ram toe_tx_sar_table_tx_table_not_ackd_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 7.363764 |
module toe_tx_sar_table_tx_table_recv_window_V_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_tx_sar_table_tx_table_recv_window_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
end
end
end
endmodule
| 7.363764 |
module toe_tx_sar_table_tx_table_recv_window_V (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
toe_tx_sar_table_tx_table_recv_window_V_ram toe_tx_sar_table_tx_table_recv_window_V_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1)
);
endmodule
| 7.363764 |
module toe_tx_sar_table_tx_table_slowstart_threshold_V_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./toe_tx_sar_table_tx_table_slowstart_threshold_V_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
end
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 7.363764 |
module toe_tx_sar_table_tx_table_slowstart_threshold_V (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
toe_tx_sar_table_tx_table_slowstart_threshold_V_ram toe_tx_sar_table_tx_table_slowstart_threshold_V_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 7.363764 |
module DRAM_read (
// global signals
clk,
rst_n,
// axi read address channel
araddr_m_inf, //master
arlen_m_inf, //master
arvalid_m_inf, //master
arready_m_inf, //slave
// axi read data channel
rdata_m_inf, //slave
rlast_m_inf, //slave
rvalid_m_inf, //slave
rready_m_inf, //master
// in valid
in_valid,
curr_addr,
// out valid
out_valid,
counter
);
//================================================================
// Parameter and Integer
//================================================================
parameter ADDR_WIDTH = 32;
parameter DATA_WIDTH = 128;
parameter IDLE = 4'd0;
parameter WAIT_OUTPUT = 4'd1;
parameter RD_HIST = 4'd2;
parameter DONE = 4'd3;
//================================================================
// INPUT AND OUTPUT DECLARATION
//================================================================
// global signals
input clk, rst_n;
// axi read address channel
output reg [ADDR_WIDTH-1:0] araddr_m_inf; //*
output reg [7:0] arlen_m_inf;
output reg arvalid_m_inf;
input wire arready_m_inf;
// axi read data channel
input wire [DATA_WIDTH-1:0] rdata_m_inf;
input wire rlast_m_inf;
input wire rvalid_m_inf;
output wire rready_m_inf;
// in valid
input wire in_valid;
input wire [31:0] curr_addr;
// out valid
output wire out_valid;
output reg [7:0] counter;
//================================================================
// Reg and Wire
//================================================================
reg [3:0] state_cs, state_ns;
wire doneRD;
assign doneRD = counter == 255;
//================================================================
// FSM
//================================================================
always @(posedge clk or negedge rst_n) begin
if (!rst_n) state_cs <= IDLE;
else state_cs <= state_ns;
end
always @(*) begin
case (state_cs)
IDLE: state_ns = arvalid_m_inf ? WAIT_OUTPUT : IDLE;
WAIT_OUTPUT: state_ns = (rready_m_inf && rvalid_m_inf) ? RD_HIST : WAIT_OUTPUT;
RD_HIST: state_ns = doneRD ? DONE : RD_HIST;
DONE: state_ns = IDLE;
default: state_ns = state_cs;
endcase
end
//================================================================
// Design
//================================================================
assign out_valid = (state_ns == RD_HIST || state_cs == RD_HIST);
assign add_address = (counter[3:0] == 15);
// counter
always @(posedge clk or negedge rst_n) begin
if (!rst_n) counter <= 0;
else if (state_ns == IDLE) counter <= 0;
else if (state_ns == RD_HIST) counter <= counter + 1;
end
// axi4
//assign araddr_m_inf = 8'h0001_0000 ;
assign rready_m_inf = 1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) arlen_m_inf <= 0;
else arlen_m_inf <= 255;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) arvalid_m_inf <= 0;
else if (state_cs == IDLE && state_ns == WAIT_OUTPUT) arvalid_m_inf <= arvalid_m_inf;
else if (in_valid) arvalid_m_inf <= 1;
else arvalid_m_inf <= 0;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) araddr_m_inf <= 0;
else araddr_m_inf <= curr_addr;
end
endmodule
| 6.928386 |
module WINDOW_MET_5 (
// global signals
clk,
rst_n,
// input signals
in_valid,
in_data,
curr_mode,
// output signals
out_valid,
out_dist
);
//================================================================
// Parameter and Integer
//================================================================
parameter IDLE = 4'd0;
parameter FILL = 4'd1;
parameter OP = 4'd2;
parameter DONE = 4'd3;
integer i;
//================================================================
// INPUT AND OUTPUT DECLARATION
//================================================================
input clk;
input rst_n;
input in_valid;
input [15:0] in_data;
input [1:0] curr_mode;
output reg out_valid;
output reg [7:0] out_dist;
//================================================================
// Reg and Wire
//================================================================
reg [3:0] state_cs, state_ns;
reg [8:0] counter;
reg [10:0] win_val;
reg [10:0] max_win_val;
reg [4:0] shift_reg[0:3];
wire fill_done;
wire op_done;
assign fill_done = counter == 5;
assign op_done = counter == 256;
//================================================================
// FSM
//================================================================
always @(posedge clk or negedge rst_n) begin
if (!rst_n) state_cs <= IDLE;
else state_cs <= state_ns;
end
always @(*) begin
case (state_cs)
IDLE: state_ns = in_valid ? FILL : IDLE;
FILL: state_ns = fill_done ? OP : FILL;
OP: state_ns = op_done ? DONE : OP;
DONE: state_ns = IDLE;
default: state_ns = state_cs;
endcase
end
//================================================================
// Design
//================================================================
always @(posedge clk or negedge rst_n) begin
if (!rst_n) counter <= 0;
else if (state_ns == IDLE) counter <= 0;
else if (state_ns == FILL || state_ns == OP) counter <= counter + 1;
end
reg [3:0] in_data_reg[0:3];
always @(posedge clk or negedge rst_n) begin
if (!rst_n) for (i = 0; i < 4; i = i + 1) in_data_reg[i] <= 0;
else if (state_ns == FILL || state_ns == OP) begin
in_data_reg[0] <= in_data[3:0];
in_data_reg[1] <= in_data[7:4];
in_data_reg[2] <= in_data[11:8];
in_data_reg[3] <= in_data[15:12];
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) for (i = 0; i < 4; i = i + 1) shift_reg[i] <= 0;
else if (state_ns == IDLE) for (i = 0; i < 4; i = i + 1) shift_reg[i] <= 0;
else if (state_ns == FILL || state_ns == OP) begin
shift_reg[0] <= shift_reg[1];
shift_reg[1] <= shift_reg[2];
shift_reg[2] <= shift_reg[3];
shift_reg[3] <= in_data_reg[0] + in_data_reg[1] + in_data_reg[2] + in_data_reg[3];
end
end
always @(*) begin
if (state_ns == FILL || state_ns == OP) begin
if (curr_mode == 0 || curr_mode == 1)
win_val = shift_reg[0]+shift_reg[2]+in_data_reg[0]+in_data_reg[1]+in_data_reg[2]+in_data_reg[3];
else
win_val = shift_reg[0]+shift_reg[1]*16+shift_reg[2]*9+shift_reg[3]*4+in_data_reg[0]+in_data_reg[1]+in_data_reg[2]+in_data_reg[3];
end else win_val = 0;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) max_win_val <= 0;
else if (state_ns == IDLE) max_win_val <= 0;
else if (state_ns == OP && win_val > max_win_val) max_win_val <= win_val;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) out_dist <= 1;
else if (state_ns == IDLE) out_dist <= 1;
else if (state_ns == OP && win_val > max_win_val) out_dist <= counter - 4;
// to avoid large distribute
else if (state_ns == OP && win_val == max_win_val) out_dist <= (out_dist + counter - 4) / 2;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) out_valid <= 0;
else if (state_ns == IDLE) out_valid <= 0;
else if (state_ns == DONE) out_valid <= 1;
end
endmodule
| 7.860252 |
module tof1021 (
input clk,
input rst,
input rx,
output tx,
output [7:0] seg0,
output [7:0] seg1,
output [7:0] seg2,
output [7:0] seg3,
output [7:0] seg4,
output [7:0] seg5
);
parameter clk_fre = 50_000_000;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire rx_sig;
wire tx_sig;
wire [19:0] data_bcd;
wire [3:0] unit;
wire [3:0] ten;
wire [3:0] hun;
wire [3:0] thou;
wire [3:0] ten_thou;
wire [3:0] hun_thou;
uart_rx #(
.UART_BPS(9600),
.clk_fre (50_000_000)
) rx1 (
.clk(clk),
.rst(rst),
.rx(rx),
.po_data(rx_data),
.po_sig(rx_sig)
);
uart_tx #(
.UART_BPS(9600),
.clk_fre (50_000_000)
) tx1 (
.clk(clk),
.rst(rst),
.pi_data(tx_data),
.pi_sig(tx_sig),
.tx(tx)
);
ascii_control ascii_control_inst (
.clk(clk),
.rst(rst),
.pi_data(rx_data),
.pi_sig(rx_sig),
.data_dis(data_bcd)
);
bcd_8421 bcd1 (
.clk(clk),
.rst(rst_deb),
.data(data_bcd),
.unit(unit),
.ten(ten),
.hun(hun),
.thou(thou),
.ten_thou(ten_thou),
.hun_thou(hun_thou)
);
seven_seg s0 (
.en (1'b1),
.in (unit),
.seg(seg0)
);
seven_seg_dot s1 (
.en (1'b1),
.in (ten),
.seg(seg1)
);
seven_seg s2 (
.en (1'b1),
.in (hun),
.seg(seg2)
);
seven_seg s3 (
.en (1'b1),
.in (thou),
.seg(seg3)
);
seven_seg s4 (
.en (1'b1),
.in (ten_thou),
.seg(seg4)
);
seven_seg s5 (
.en (1'b1),
.in (hun_thou),
.seg(seg5)
);
endmodule
| 6.517097 |
module toffoli_gate (
input a,
b,
c,
output p,
q,
r
);
assign p = a;
assign q = b;
assign r = (a & b) ^ c;
endmodule
| 7.415387 |
module GateToFloat (
input [3:0] _D,
output [3:0] F,
output [1:0] P
);
wire high, low;
power U0 (
high,
low
);
wire [2:0] _P;
wire [3:0] D;
not (D[0], _D[0]);
not (D[1], _D[1]);
not (D[2], _D[2]);
not (D[3], _D[3]);
not (P[0], _P[0]);
not (P[1], _P[1]);
Gate148 U1 (
._S(low),
._I({high, high, high, high, D[3], D[2], D[1], low}),
.Y (_P)
);
Gate153 U2 (
._S1(low),
._S2(low),
.D1 (_D),
.D2 ({_D[2], _D[1], _D[0], low}),
.Y1 (F[3]),
.Y2 (F[2]),
.A (P)
);
Gate153 U3 (
._S1(low),
._S2(low),
.D1 ({_D[1], _D[0], low, low}),
.D2 ({_D[0], low, low, low}),
.Y1 (F[1]),
.Y2 (F[0]),
.A (P)
);
endmodule
| 7.118585 |
module DRAM_read (
// global signals
clk,
rst_n,
// axi read address channel
araddr_m_inf, //master
arlen_m_inf, //master
arvalid_m_inf, //master
arready_m_inf, //slave
// axi read data channel
rdata_m_inf, //slave
rlast_m_inf, //slave
rvalid_m_inf, //slave
rready_m_inf, //master
// in valid
in_valid,
curr_addr,
// out valid
out_valid,
counter
);
//================================================================
// Parameter and Integer
//================================================================
parameter ADDR_WIDTH = 32;
parameter DATA_WIDTH = 128;
parameter IDLE = 4'd0;
parameter WAIT_OUTPUT = 4'd1;
parameter RD_HIST = 4'd2;
parameter DONE = 4'd3;
//================================================================
// INPUT AND OUTPUT DECLARATION
//================================================================
// global signals
input clk, rst_n;
// axi read address channel
output reg [ADDR_WIDTH-1:0] araddr_m_inf; //*
output reg [7:0] arlen_m_inf;
output reg arvalid_m_inf;
input wire arready_m_inf;
// axi read data channel
input wire [DATA_WIDTH-1:0] rdata_m_inf;
input wire rlast_m_inf;
input wire rvalid_m_inf;
output wire rready_m_inf;
// in valid
input wire in_valid;
input wire [31:0] curr_addr;
// out valid
output wire out_valid;
output reg [7:0] counter;
//================================================================
// Reg and Wire
//================================================================
reg [3:0] state_cs, state_ns;
//reg [7:0] counter;
wire doneRD;
assign doneRD = counter == 255;
//================================================================
// FSM
//================================================================
always @(posedge clk or negedge rst_n) begin
if (!rst_n) state_cs <= IDLE;
else state_cs <= state_ns;
end
always @(*) begin
case (state_cs)
IDLE: state_ns = arvalid_m_inf ? WAIT_OUTPUT : IDLE;
WAIT_OUTPUT: state_ns = (rready_m_inf && rvalid_m_inf) ? RD_HIST : WAIT_OUTPUT;
RD_HIST: state_ns = doneRD ? DONE : RD_HIST;
DONE: state_ns = IDLE;
default: state_ns = state_cs;
endcase
end
//================================================================
// Design
//================================================================
assign out_valid = (state_ns == RD_HIST || state_cs == RD_HIST);
assign add_address = (counter[3:0] == 15);
// counter
always @(posedge clk or negedge rst_n) begin
if (!rst_n) counter <= 0;
else if (state_ns == IDLE) counter <= 0;
else if (state_ns == RD_HIST) counter <= counter + 1;
end
// axi4
//assign araddr_m_inf = 8'h0001_0000 ;
assign rready_m_inf = 1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) arlen_m_inf <= 0;
else arlen_m_inf <= 255;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) arvalid_m_inf <= 0;
else if (state_cs == IDLE && state_ns == WAIT_OUTPUT) arvalid_m_inf <= arvalid_m_inf;
else if (in_valid) arvalid_m_inf <= 1;
else arvalid_m_inf <= 0;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) araddr_m_inf <= 0;
else araddr_m_inf <= curr_addr;
end
endmodule
| 6.928386 |
module Together (
output wire [25:0] avm_node_address,
output wire avm_node_read,
input wire [15:0] avm_node_readdata,
input wire avm_node_readdatavalid,
output wire avm_node_write,
output wire [15:0] avm_node_writedata,
output wire [5:0] avm_node_burstcount,
input wire avm_node_waitrequest,
input wire [15:0] avs_config_address,
output wire avs_config_waitrequest,
input wire avs_config_write,
input wire [31:0] avs_config_writedata,
input wire avs_config_read,
output wor [31:0] avs_config_readdata,
output wor avs_config_readdatavalid,
input wire dma_irq,
output wire hps_irq,
input wire CLOCK_50,
input wire reset
);
wire [15:0] asi_var_data;
wire asi_var_ready;
wire asi_var_valid;
wire [95:0] asi_result_data;
wire asi_result_channel;
wire asi_result_ready;
wire asi_result_valid;
wire [127:0] asi_requests_data;
wire asi_requests_channel;
wire asi_requests_ready;
wire asi_requests_valid;
wire mReadValid, cReadValid;
wire [31:0] mReadData, cReadData;
assign avs_config_readdatavalid = mReadValid;
assign avs_config_readdatavalid = cReadValid;
assign avs_config_readdata = mReadData;
assign avs_config_readdata = cReadData;
MemoryAccess m (
.avm_node_address(avm_node_address),
.avm_node_read(avm_node_read),
.avm_node_readdata(avm_node_readdata),
.avm_node_readdatavalid(avm_node_readdatavalid),
.avm_node_write(avm_node_write),
.avm_node_writedata(avm_node_writedata),
.avm_node_burstcount(avm_node_burstcount),
.avm_node_waitrequest(avm_node_waitrequest),
.avs_config_address(avs_config_address),
.avs_config_write(avs_config_write),
.avs_config_writedata(avs_config_writedata),
.avs_config_read(avs_config_read),
.avs_config_readdata(mReadData),
.avs_config_waitrequest(avs_config_waitrequest),
.avs_config_readdatavalid(mReadValid),
.asi_requests_data(asi_requests_data),
.asi_requests_channel(asi_requests_channel),
.asi_requests_ready(asi_requests_ready),
.asi_requests_valid(asi_requests_valid),
.hps_irq(hps_irq),
.dma_irq(dma_irq),
.aso_var_data(asi_var_data),
.aso_var_ready(asi_var_ready),
.aso_var_valid(asi_var_valid),
.aso_result_data(asi_result_data),
.aso_result_ready(asi_result_ready),
.aso_result_valid(asi_result_valid),
.clk(CLOCK_50),
.reset(reset)
);
CoPartial c (
.avs_config_address(avs_config_address),
.avs_config_waitrequest(),
.avs_config_write(avs_config_write),
.avs_config_writedata(avs_config_writedata),
.avs_config_read(avs_config_read),
.avs_config_readdata(cReadData),
.avs_config_readdatavalid(cReadValid),
.avs_co_write(avs_co_write),
.avs_co_writedata(avs_co_writedata),
.avs_co_read(avs_co_read),
.avs_co_readdata(avs_co_readdata),
.avs_co_waitrequest(avs_co_waitrequest),
.avs_co_byteenable(avs_co_byteenable),
.aso_var_data(aso_var_data),
.aso_var_ready(aso_var_ready),
.aso_var_valid(aso_var_valid),
.aso_cache_data(aso_cache_data),
.aso_cache_ready(aso_cache_ready),
.aso_cache_valid(aso_cache_valid),
.asi_result_data(asi_result_data),
.asi_result_channel(asi_result_channel),
.asi_result_ready(asi_result_ready),
.asi_result_valid(asi_result_valid),
.asi_var_data(asi_var_data),
.asi_var_ready(asi_var_ready),
.asi_var_valid(asi_var_valid),
.clk(CLOCK_50),
.reset(reset)
);
endmodule
| 6.863846 |
module toggle #(
parameter TON_us = 50,
parameter TOFF_us = 50,
parameter CLK_FREQ_MHz = 100
) (
input wire clk,
output reg toggle_OUT
);
reg [31:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
if (counter == (TON_us) * CLK_FREQ_MHz) begin
toggle_OUT = 1'b0;
end
if (counter >= ((TON_us + TOFF_us) * CLK_FREQ_MHz)) begin
toggle_OUT = 1'b1;
counter <= 0;
end
end
endmodule
| 7.469767 |
module toggle3pos (
input [1:0] pkgpin, // raw pin input
output reg [1:0] out
);
always @(*)
case (pkgpin)
2'b00: out = 2'b11; // can't happen
2'b01: out = 2'b00; // top
2'b10: out = 2'b10; // bottom
2'b11: out = 2'b01; // center
endcase
endmodule
| 7.559138 |
module ToggleLight #(
parameter integer CLAPS_WIDTH = 16,
parameter integer TOGLITE_ON_VAL = 2,
parameter integer TOGLITE_OFF_VAL = 3
) (
input wire clock,
input wire [CLAPS_WIDTH-1:0] claps_data,
input wire claps_valid,
output reg claps_ready = 0,
output reg toglite_state = 0
);
reg [CLAPS_WIDTH-1:0] claps_buff = 0;
always @(posedge clock)
if (claps_valid == 1 && claps_ready == 1) begin
claps_buff <= claps_data;
claps_ready <= 0;
end else begin
claps_ready <= 1;
end
always @(posedge clock)
if (claps_buff == TOGLITE_ON_VAL) begin
toglite_state <= 1;
end else if (claps_buff == TOGLITE_OFF_VAL) begin
toglite_state <= 0;
end
endmodule
| 7.390661 |
module toggleReg (
q,
d,
clk,
en,
clr
);
input d, clk, en, clr;
output q;
wire w1, w2, w3, w4, w5;
not notty (w1, d);
not notty2 (w3, q);
and and1 (w2, d, w3);
and and2 (w4, w1, q);
or orgate (w5, w2, w4);
dffe_ref regg (
q,
w5,
clk,
1'b1,
clr
);
endmodule
| 6.536433 |
module toggle_detector
#(
parameter width = 1
)(
clk,
reset,
signal,
toggle_flag
);
input clk;
input reset;
input [width-1:0]signal;
output toggle_flag;
reg [width-1:0]signal_delayed;
reg [width-1:0]toggle;
genvar i;
generate
for( i=0; i< width; i=i+1 )
begin: toggle_loop
always @ (posedge clk or posedge reset)
begin
if(reset)
signal_delayed[i] <= 1'b0;
else
signal_delayed[i] <= signal[i] ;
end
end
endgenerate
assign toggle_flag = ((signal[width-1:0] !=
signal_delayed[width-1:0]))? 1'b1 : 1'b0; .
endmodule
| 6.992692 |
module toggle_flipflop (
out,
clock
);
input clock;
output out;
wire d, outBar;
reg reg1;
initial reg1 = 0;
d_flipflop main (
out,
d,
clock
);
not not1 (outBar, out);
or or1 (d, outBar, reg1);
endmodule
| 6.552577 |
module toggle_gen #(
parameter RST_TO_INPUT = 1
) (
input clk,
input rst,
input pulse,
output toggle
);
reg q;
assign toggle = q ^ pulse;
generate
if (RST_TO_INPUT) begin : RST_TO_INPUT_
always @(posedge clk)
if (rst) q <= pulse;
else q <= toggle;
end else begin : RST_TO_ZERO_
always @(posedge clk)
if (rst) q <= 0;
else q <= toggle;
end
endgenerate
endmodule
| 6.557877 |
module toggle_reg (
input wire i_clk,
input wire i_res_n,
input wire i_init_val,
input wire i_pls,
output reg o_sig
);
always @(posedge i_clk or negedge i_res_n) begin
if (~i_res_n) begin
o_sig <= i_init_val;
end else if (i_pls) begin
o_sig <= ~o_sig;
end
end
endmodule
| 8.156894 |
module toggle_simple ( /*AUTOARG*/
// Outputs
dot,
blank,
// Inputs
in,
rstn
);
input in;
output dot;
output blank;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
wire dot;
wire blank, blank_n;
latch U_LATCH_1 (
.i(blank_n),
.q(dot),
.en(in),
.rstn(rstn)
);
latch U_LATCH_2 (
.i(dot),
.q(blank),
.en(!in),
.rstn(rstn)
);
inv U_INV (
.i (blank),
.zn(blank_n)
);
endmodule
| 6.688011 |
module tomasulo (
pc,
clk1,
clk2
);
input [4:0] pc;
input clk1, clk2;
wire [15:0] inst; //This is for getting instruction from ins set
// reg [3:0] rs1,rs2,func,rd;
//These are stage 1 pr
reg [3:0] pr1_rs1, pr1_rs2, pr1_func, pr1_rd;
reg pr2_count;
//These are stage 2 pr
reg [3:0] pr2_rs1, pr2_rs2, pr2_func, pr2_rd;
reg [2:0] pr2_rob_ind;
//These are stage3 that is RS stage
//1st bit and 2nd bit are for add-sub exec unit
//3rd and 4th are for mul-div exec unit
reg [3:0] pr3_exec_b;
reg [7:0] pr3_rs1data[0:3], pr3_rs2data[0:3];
reg [3:0] pr3_func[0:3], pr3_rd[0:3];
reg [2:0] pr3_rob_ind[0:3], pr3_rsindex[0:3];
integer pr3_addcount, pr3_mulcount;
//This is for issue stage
integer add_count, mul_count, bch_count; //These are needed in issue stage
reg [2:0] head_p, tail_p;
//RS coulmns: func,rs1,rs2,rob,rs1b,rs2b,busy,exec_busy
reg [3:0] add_array[0:2][0:7]; //RS add and sub
reg [3:0] mul_array[0:2][0:7]; //RS mul_array
reg [4:0] bch_array[0:1][0:7]; //RS branches
reg [15:0] ls_queue[0:3][0:7]; //Each index should be 16 bits since we wil be storing the data
reg [15:0] regbank[0:15][0:1]; //First column is actual value and second column is ROB
reg [15:0] ROB[0:7][0:2]; //Each index should be 16 bits since we will be storing the data
reg [15:0] memory[0:255]; //Memory
instruction_set k1 (
pc,
clk1,
inst
);
always @(posedge clk2) begin
$display("\nIn fetch stage:");
pr1_func = inst[15:12];
pr1_rs1 = inst[11:8];
pr1_rs2 = inst[7:4];
pr1_rd = inst[3:0];
$display(
"values of pc = %b,values of func = %b,values of rs1 = %b,values of rs2 = %b,values of rd = %b\n\n",
pc, pr1_func, pr1_rs1, pr1_rs2, pr1_rd);
end
issue is1 (
pr1_rs1,
pr1_rs2,
pr1_rd,
pr1_func,
clk1,
clk2
);
endmodule
| 7.710145 |
module tomosulo ();
reg clk1, clk2;
reg [5:0] pc;
reg [6:0] func7, opcode;
reg [4:0] rs1, rs2, rd;
reg [2:0] func3;
reg [11:0] imm;
reg [2:0] inst_type;
reg [5:0] ROB[1:8][0:3];
reg [5:0] arf_rat[1:10][0:3];
reg [5:0] rs_add_sub[0:2][0:6];
reg [5:0] rs_div_mul[0:1][0:6];
reg [4:0] lsb[0:2][0:4];
reg [7:0] memory[0:17]; //memory
reg [31:0] instr_set[1:7];
reg [31:0] temp;
reg [8:0] cycle;
integer i;
initial begin
pc = 1;
clk1 = 0;
clk2 = 0;
instr_set[1] = 32'h00012183;
instr_set[2] = 32'h0241c133;
instr_set[3] = 32'h026280b3;
instr_set[4] = 32'h008381b3;
instr_set[5] = 32'h023080b3;
instr_set[6] = 32'h40508233;
instr_set[7] = 32'h002200b3;
for (i = 0; i < 18; i++) begin
memory[i] = i;
end
cycle = 0;
arf_rat[1][1] = 12;
arf_rat[2][1] = 16;
arf_rat[3][1] = 45;
arf_rat[4][1] = 5;
arf_rat[5][1] = 3;
arf_rat[6][1] = 4;
arf_rat[7][1] = 1;
arf_rat[8][1] = 2;
arf_rat[9][1] = 2;
arf_rat[10][1] = 3;
ROB[1][0] = 6'b000001;
ROB[2][0] = 6'b000010;
ROB[3][0] = 6'b000011;
ROB[4][0] = 6'b000100;
ROB[5][0] = 6'b000101;
ROB[6][0] = 6'b000110;
ROB[7][0] = 6'b000111;
ROB[8][0] = 6'b001000;
for (i = 0; i < 3; i++) begin
rs_add_sub[i][1] = 6'b000000; //busy bit
end
for (i = 0; i < 2; i++) begin
rs_div_mul[i][1] = 6'b000000; //busy bit
end
for (i = 0; i < 3; i++) begin
lsb[i][1] = 5'b00000; //busy bit
end
for (i = 0; i < 10; i++) begin
arf_rat[i][3] = 6'b000000; //busy bit
end
arf_rat[1][2] = 6'b000001; //R1
arf_rat[2][2] = 6'b000010; //R2
arf_rat[3][2] = 6'b000011;
arf_rat[4][2] = 6'b000100;
arf_rat[5][2] = 6'b000101;
arf_rat[6][2] = 6'b000110;
arf_rat[7][2] = 6'b000111;
arf_rat[8][2] = 6'b001000;
arf_rat[9][2] = 6'b001001;
arf_rat[10][2] = 6'b001010; //R10
for (i = 0; i < 3; i++) begin
rs_add_sub[i][3] = 0;
rs_add_sub[i][4] = 0;
lsb[i][4] = 0;
end
for (i = 0; i < 2; i++) begin
rs_div_mul[i][3] = 0;
rs_div_mul[i][4] = 0;
end
end
always #5 clk1 = ~clk1;
always #5 clk2 = ~clk2;
always @(posedge clk1) begin
temp = instr_set[pc];
cycle += 1;
if (pc > 10) $finish;
pc = pc + 1;
end
decode inst1 (
temp,
clk1,
clk2
);
endmodule
| 6.586641 |
module tone (
input clk,
input [31:0] duration, // millis
input [31:0] freq, //hz
output reg tone_out, // pin
output reg done
);
parameter CLK_F = 48; // CLK freq in MHz
reg [ 7:0] prescaler = 0;
reg [31:0] tone_counter = 0;
reg [31:0] time_counter = 0;
reg [31:0] millis = 0;
wire [31:0] period = 1000000 / freq;
always @(posedge clk)
if (duration > 0) begin
if (time_counter == CLK_F * 1000 - 1) begin
millis <= millis + 1;
time_counter <= 0;
end else time_counter <= time_counter + 1;
if (millis < duration) begin
prescaler <= prescaler + 1;
if (prescaler == CLK_F / 2 - 1) begin
prescaler <= 0;
tone_counter <= tone_counter + 1;
if (tone_counter >= period - 1) begin
tone_counter <= 0;
tone_out <= ~tone_out;
end
end
end else begin
tone_out <= 0;
done = 1;
end
end else begin
millis <= 0;
done <= 0;
prescaler <= 0;
time_counter <= 0;
tone_counter <= 0;
end
endmodule
| 8.025425 |
module ToneDecode (
Index,
OTone
);
input [3:0] Index;
output [12:0] OTone;
reg [12:0] OTone;
always @(Index) begin
case (Index)
4'b0000: OTone = 13'd8191;
4'b0001: OTone = 13'd548;
4'b0010: OTone = 13'd1382;
4'b0011: OTone = 13'd2125;
4'b0100: OTone = 13'd2465;
4'b0101: OTone = 13'd3090;
4'b0110: OTone = 13'd3647;
4'b0111: OTone = 13'd4142;
4'b1000: OTone = 13'd4370;
4'b1001: OTone = 13'd4787;
4'b1010: OTone = 13'd5158;
4'b1011: OTone = 13'd5328;
4'b1100: OTone = 13'd5641;
4'b1101: OTone = 13'd5919;
4'b1110: OTone = 13'd6167;
4'b1111: OTone = 13'd6281;
endcase
end
endmodule
| 7.738321 |
module tones (
input wire clk,
output wire ch0,
ch1,
ch2,
ch3
);
//-- Parametro del divisor. Fijarlo a 1Hz
//-- Se define como parametro para poder modificarlo desde el testbench
//-- para hacer pruebas
parameter F0 = `F_1KHz;
parameter F1 = `F_2KHz;
parameter F2 = `F_3KHz;
parameter F3 = `F_4KHz;
//-- Generador de tono 0
divider #(F0) CH0 (
.clk_in (clk),
.clk_out(ch0)
);
//-- Generador de tono 1
divider #(F1) CH1 (
.clk_in (clk),
.clk_out(ch1)
);
//-- Generador de tono 2
divider #(F2) CH2 (
.clk_in (clk),
.clk_out(ch2)
);
//-- Generador de tono 3
divider #(F3) CH3 (
.clk_in (clk),
.clk_out(ch3)
);
endmodule
| 8.083412 |
module ToneTaba (
iclk,
code,
speaker
);
input iclk;
input [4:0] code;
output speaker;
reg [18:0] Tone;
reg [18:0] cnt;
reg clk_temp;
assign speaker = clk_temp;
always @(posedge iclk) begin
case (code)
5'd0: Tone <= 134;
5'd01: Tone <= 494;
5'd02: Tone <= 554;
5'd03: Tone <= 622;
5'd04: Tone <= 659;
5'd05: Tone <= 740;
5'd06: Tone <= 831;
5'd07: Tone <= 932;
5'd11: Tone <= 988;
5'd12: Tone <= 1109;
5'd13: Tone <= 1245;
5'd14: Tone <= 1318;
5'd15: Tone <= 1480;
5'd16: Tone <= 1661;
5'd17: Tone <= 1865;
5'd21: Tone <= 1976;
5'd22: Tone <= 2218;
5'd23: Tone <= 2490;
5'd24: Tone <= 2636;
5'd25: Tone <= 2960;
5'd26: Tone <= 2322;
5'd27: Tone <= 3730;
default: Tone <= 134;
endcase
if (cnt == (50000000 / Tone) / 2 - 1) begin
clk_temp = ~clk_temp;
cnt <= 0;
end else cnt <= cnt + 1;
end
endmodule
| 6.924775 |
module tone_440_rom (
addr,
q
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
input [(ADDR_WIDTH-1):0] addr;
output [(DATA_WIDTH-1):0] q;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
assign q = ram[addr];
initial $readmemh("../../../../i2s_to_wb/scilab/tone_roms/tone_440_at_48000sps_rom.txt", ram);
endmodule
| 7.121599 |
module tone_660_rom (
addr,
q
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
input [(ADDR_WIDTH-1):0] addr;
output [(DATA_WIDTH-1):0] q;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
assign q = ram[addr];
initial $readmemh("../../../../i2s_to_wb/scilab/tone_roms/tone_660_at_48000sps_rom.txt", ram);
endmodule
| 6.913863 |
module tone_gen (
input wire clk_in,
output wire tone
);
parameter freq = 1000;
wire clk_out;
divM #(
.number(freq)
) divider (
.clk_in (clk_in),
.clk_out(clk_out)
);
assign tone = clk_out;
endmodule
| 7.243717 |
module tone_generator (
input output_enable,
input [23:0] tone_switch_period,
input clk,
input rst,
output square_wave_out
);
reg [23:0] clock_counter = 0;
reg wave = 0;
assign square_wave_out = 1'b0;
endmodule
| 7.792384 |
module tone_generator_testbench ();
reg clock;
reg output_enable;
reg rst;
reg [23:0] tone_to_play;
wire sq_wave;
initial clock = 0;
always #(30.3 / 2) clock <= ~clock;
tone_generator piezo_controller (
.clk(clock),
.rst(rst),
.output_enable(output_enable),
.tone_switch_period(tone_to_play),
.square_wave_out(sq_wave)
);
initial begin
tone_to_play = 24'd0;
output_enable = 1'b0;
rst = 1'b0;
@(posedge clock);
rst = 1'b1;
@(posedge clock);
rst = 1'b0;
#(10 * `MS);
output_enable = 1'b1;
tone_to_play = 24'd37500;
#(200 * `MS);
tone_to_play = 24'd42000;
#(200 * `MS);
tone_to_play = 24'd45000;
#(200 * `MS);
tone_to_play = 24'd47000;
#(200 * `MS);
tone_to_play = 24'd50000;
#(200 * `MS);
output_enable = 1'b0;
#(100 * `MS);
$finish();
end
integer file;
initial begin
file = $fopen("output.txt", "w");
forever begin
$fwrite(file, "%h\n", sq_wave);
#(`SAMPLE_PERIOD);
end
end
endmodule
| 7.792384 |
module tone_mapping_divider (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [9:0] denom;
input [17:0] numer;
output [17:0] quotient;
output [9:0] remain;
wire [17:0] sub_wire0;
wire [ 9:0] sub_wire1;
wire [17:0] quotient = sub_wire0[17:0];
wire [ 9:0] remain = sub_wire1[9:0];
lpm_divide LPM_DIVIDE_component (
.clock(clock),
.denom(denom),
.numer(numer),
.quotient(sub_wire0),
.remain(sub_wire1),
.aclr(1'b0),
.clken(1'b1)
);
defparam LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED", LPM_DIVIDE_component.lpm_hint =
"LPM_REMAINDERPOSITIVE=TRUE", LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_pipeline = 18, LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 10, LPM_DIVIDE_component.lpm_widthn = 18;
endmodule
| 7.816099 |
module tone_tester (
input CLK,
output tone_1khz,
output tone_100hz,
output tone_12khz
);
reg [31:0] period_1khz = 1000;
reg [31:0] period_100hz = 10000;
reg [31:0] period_12khz = 80;
tone #(32) t1 (
.CLK(CLK),
.period(period_1khz),
.tone_out(tone_1khz)
);
tone #(32) t2 (
.CLK(CLK),
.period(period_100hz),
.tone_out(tone_100hz)
);
tone #(32) t3 (
.CLK(CLK),
.period(period_12khz),
.tone_out(tone_12khz)
);
endmodule
| 7.340183 |
module decoder_2_4 (
input wire [1:0] in,
output wire [3:0] out
);
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : gen_for_dec_2_4
assign out[i] = (in == i);
end
endgenerate
endmodule
| 7.833664 |
module decoder_4_16 (
input wire [ 3:0] in,
output wire [15:0] out
);
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : gen_for_dec_4_16
assign out[i] = (in == i);
end
endgenerate
endmodule
| 7.408825 |
module decoder_5_32 (
input wire [ 4:0] in,
output wire [31:0] out
);
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : gen_for_dec_5_32
assign out[i] = (in == i);
end
endgenerate
endmodule
| 6.549097 |
module decoder_6_64 (
input wire [ 5:0] in,
output wire [63:0] out
);
genvar i;
generate
for (i = 0; i < 63; i = i + 1) begin : gen_for_dec_6_64
assign out[i] = (in == i);
end
endgenerate
endmodule
| 6.818106 |
module too_slow_char_rom (
input wire [15:0] char_xy,
output reg [ 6:0] char_code // pixels of the character line
);
always @* begin
case (char_xy)
16'h0000: char_code = 7'h54;
16'h0100: char_code = 7'h4f;
16'h0200: char_code = 7'h4f;
16'h0300: char_code = 7'h20;
16'h0400: char_code = 7'h53;
16'h0500: char_code = 7'h4c;
16'h0600: char_code = 7'h4f;
16'h0700: char_code = 7'h57;
16'h0800: char_code = 7'h21;
16'h0900: char_code = 7'h21;
16'h0a00: char_code = 7'h21;
16'h0b00: char_code = 7'h00;
16'h0c00: char_code = 7'h54;
16'h0d00: char_code = 7'h72;
16'h0e00: char_code = 7'h79;
16'h0f00: char_code = 7'h20;
16'h1000: char_code = 7'h61;
16'h1100: char_code = 7'h67;
16'h1200: char_code = 7'h61;
16'h1300: char_code = 7'h69;
16'h1400: char_code = 7'h6e;
16'h1500: char_code = 7'h21;
default: char_code = 0;
endcase
end
endmodule
| 7.059669 |
module top (
input clk,
rst,
input rx,
output tx,
output reg led0,
output reg led1
);
reg startRec;
reg kernelWE;
reg pixelWE;
reg sendWE;
wire calWE;
wire [71:0] kernel;
wire [7:0] Pixel_read;
wire [7:0] Pixel_send;
wire readOne;
wire kernelFinished;
wire calStart;
wire readFinished;
wire sentFlag;
reg [31:0] cal_cnt;
parameter CALSIZE = 32'd1007;
parameter ALLSIZE = 32'd252004;
//调用
//需要修改posedge we or negedge we
//(似乎已经完成)需要修改设置，每一个读取和发送过程都会产生信号延迟，需要将这一部分考虑到
recKernel recKernel (
.clk(clk),
.rst(rst),
.we(kernelWE),
.rx(rx),
.finished(kernelFinished),
.kernel(kernel)
);
recPixel recPixel (
.clk(clk),
.rst(rst),
.we(pixelWE),
.rx(rx),
.readOne(readOne),
.start(calStart),
.finished(readFinished),
.Pixel(Pixel_read)
);
shiftCal shiftCal (
.clk(clk),
.rst(rst),
.we(calWE),
.kernel(kernel),
.data_in(Pixel_read),
.data_out(Pixel_send)
);
send send (
.clk(clk),
.rst(rst),
.we(sendWE),
.tx(tx),
.sentFlag(sentFlag),
.Pixel(Pixel_send)
);
//WE
always @(posedge clk or posedge rst) begin
if (rst) startRec <= 0;
else if (rx != 0 && startRec == 0) startRec = 1;
end
always @(posedge clk or posedge rst) begin
if (rst) kernelWE <= 0;
else if (startRec && kernel == 0) kernelWE <= 1;
else if (kernelFinished == 1) kernelWE <= 0;
end
always @(posedge clk or posedge rst) begin
if (rst) pixelWE <= 0;
else if (kernelFinished == 1 && readFinished != 1) pixelWE <= 1;
end
//每当读入了一个数据，就写入寄存器
assign calWE = readOne && !rst;
//为了避免重复发送，sendWE在发送完一个信号之后就不再发送，除非此时又有了新的输入（即readOne == 1）
//sendFlag不需要通过shiftcal返回，因为整个系统的时延完全是由UART控制的
//所以只需要在输入的数据填满寄存器之后，就可以输出
//输出使能的管理：
//counter
always @(posedge clk or posedge rst) begin
if (rst) cal_cnt <= 0;
else if (readOne) cal_cnt <= cal_cnt + 32'b1;
end
always @(posedge clk or posedge rst) begin
if (rst) sendWE <= 0;
else if (pixelWE) begin
if (cal_cnt >= CALSIZE && cal_cnt <= ALLSIZE) sendWE <= 1;
else sendWE <= 0;
end else sendWE <= 0;
end
always @(posedge clk or posedge rst) begin
if (rst) led0 <= 0;
else if (pixelWE) led0 <= 1;
end
always @(posedge clk or posedge rst) begin
if (rst) led1 <= 0;
else if (calStart) led1 <= 1;
end
endmodule
| 7.233807 |
module top (
input clk,
input rstn,
(* syn_preserve="TRUE" *) input ila_a,
(* syn_preserve="TRUE" *) input ila_b,
(* syn_preserve="TRUE" *) input ila_c
// (* syn_preserve="TRUE" *)input ila_d
);
(* syn_preserve="TRUE" *)wire data_en_o;
(* syn_preserve="TRUE" *)wire [7:0] data_o;
reg spi_clk, mosi, spi_ss;
always @(posedge clk) begin
if (ila_a) spi_clk <= 1;
else spi_clk <= 0;
if (ila_b) mosi <= 1;
else mosi <= 0;
if (ila_c) spi_ss <= 1;
else spi_ss <= 0;
end
spi_slave spi_slave (
//
.clk (clk),
.rstn (rstn),
.spi_clk(ila_a),
.mosi (ila_b),
.spi_ss (ila_c),
.data_en_o(data_en_o),
.data_o (data_o )
);
endmodule
| 7.233807 |
module Top_Module (
input clk, //Clock signal
input [3:0] enable, //Enable signal
input [3:0] angle, //ON/OFF FPGA switch to select angle
input [3:0] clk_trig, //Trigger switch on FPGA for PIPO
output [3:0] pwm //PWM output signal
);
wire [27:0] t [3:0]; //Output from PIPO
wire [27:0] ontime_BUS; //Ontime_bus
//Module instantiations
Angle_to_on_time DUT (
angle,
ontime_BUS
);
PIPO_shift_register I_1 (
clk_trig[0],
ontime_BUS,
t[0]
);
PWM_generator I_2 (
clk,
enable[0],
t[0],
pwm[0]
);
PIPO_shift_register I_3 (
clk_trig[1],
ontime_BUS,
t[1]
);
PWM_generator I_4 (
clk,
enable[1],
t[1],
pwm[1]
);
PIPO_shift_register I_5 (
clk_trig[2],
ontime_BUS,
t[2]
);
PWM_generator I_6 (
clk,
enable[2],
t[2],
pwm[2]
);
PIPO_shift_register I_7 (
clk_trig[3],
ontime_BUS,
t[3]
);
PWM_generator I_8 (
clk,
enable[3],
t[3],
pwm[3]
);
endmodule
| 6.750161 |
module top_design (
// Inputs
input clk,
input rst_btn,
// Outputs
output [1:0] led // Not reg element!
);
// Internal signals
wire rst;
// Invert active-low button
assign rst = ~rst_btn;
// Instantiate the first clock divider module
clock_divider #(
.COUNT_WIDTH(32),
.MAX_COUNT (1500000 - 1)
) div_1 (
.clk(clk),
.rst(rst),
.out(led[0])
);
// Instantiate the second clock divider module
clock_divider div_2 (
.clk(clk),
.rst(rst),
.out(led[1])
);
endmodule
| 7.970167 |
module uart_buttons_rx_0clk_380ecc95 (
clk,
clock_enable,
\global_to_module.uart_rx_mac_word_out ,
\module_to_global.uart_buttons ,
\module_to_global.uart_rx_mac_out_ready
);
wire [3:0] _0_;
wire [3:0] _1_;
reg [3:0] _2_ = 4'h0;
input clk;
wire clk;
input clock_enable;
wire clock_enable;
input [8:0] \global_to_module.uart_rx_mac_word_out ;
wire [8:0] \global_to_module.uart_rx_mac_word_out ;
output [3:0] \module_to_global.uart_buttons ;
wire [3:0] \module_to_global.uart_buttons ;
output \module_to_global.uart_rx_mac_out_ready ;
wire \module_to_global.uart_rx_mac_out_ready ;
wire [3:0] reg_comb_uart_buttons_reg;
wire [3:0] uart_buttons_reg;
wire uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_cond;
wire [3:0] uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_iffalse;
wire [3:0] uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_iftrue;
wire [3:0] uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_return_output;
assign _1_ = clock_enable ? reg_comb_uart_buttons_reg : uart_buttons_reg;
always @(posedge clk) _2_ <= _1_;
mux_uint1_t_uint4_t_uint4_t_0clk_de264c78 uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff (
.cond(uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_cond),
.iffalse(uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_iffalse),
.iftrue(uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_iftrue),
.return_output(_0_)
);
assign uart_buttons_reg = _2_;
assign reg_comb_uart_buttons_reg = uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_return_output;
assign uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_cond = \global_to_module.uart_rx_mac_word_out [8];
assign uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_iftrue = \global_to_module.uart_rx_mac_word_out [3:0];
assign uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_iffalse = uart_buttons_reg;
assign uart_buttons_reg_mux_pipelinec_app_c_l117_c3_d3ff_return_output = _0_;
assign \module_to_global.uart_buttons = uart_buttons_reg;
assign \module_to_global.uart_rx_mac_out_ready = 1'h1;
endmodule
| 7.225107 |
module uart_buttons_tx_0clk_380ecc95 (
clk,
clock_enable,
\global_to_module.frame_clock_rising_edge ,
\global_to_module.frame_clock_falling_edge ,
\global_to_module.buttons ,
\global_to_module.uart_buttons ,
\module_to_global.buttons_or_uart ,
\module_to_global.uart_tx_mac_word_in
);
wire [3:0] _0_;
wire [3:0] _1_;
wire [3:0] _2_;
reg [3:0] _3_ = 4'h0;
wire [3:0] bin_op_or_pipelinec_app_c_l144_c27_0888_left;
wire [3:0] bin_op_or_pipelinec_app_c_l144_c27_0888_return_output;
wire [3:0] bin_op_or_pipelinec_app_c_l144_c27_0888_right;
wire [3:0] buttons_or_uart_reg;
wire buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_cond;
wire [3:0] buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_iffalse;
wire [3:0] buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_iftrue;
wire [3:0] buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_return_output;
input clk;
wire clk;
input clock_enable;
wire clock_enable;
input [3:0] \global_to_module.buttons ;
wire [3:0] \global_to_module.buttons ;
input \global_to_module.frame_clock_falling_edge ;
wire \global_to_module.frame_clock_falling_edge ;
input \global_to_module.frame_clock_rising_edge ;
wire \global_to_module.frame_clock_rising_edge ;
input [3:0] \global_to_module.uart_buttons ;
wire [3:0] \global_to_module.uart_buttons ;
output [3:0] \module_to_global.buttons_or_uart ;
wire [3:0] \module_to_global.buttons_or_uart ;
output [8:0] \module_to_global.uart_tx_mac_word_in ;
wire [8:0] \module_to_global.uart_tx_mac_word_in ;
wire [3:0] reg_comb_buttons_or_uart_reg;
assign _2_ = clock_enable ? reg_comb_buttons_or_uart_reg : buttons_or_uart_reg;
always @(posedge clk) _3_ <= _2_;
bin_op_or_uint4_t_uint4_t_0clk_de264c78 bin_op_or_pipelinec_app_c_l144_c27_0888 (
.left(bin_op_or_pipelinec_app_c_l144_c27_0888_left),
.return_output(_1_),
.right(bin_op_or_pipelinec_app_c_l144_c27_0888_right)
);
mux_uint1_t_uint4_t_uint4_t_0clk_de264c78 buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95 (
.cond(buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_cond),
.iffalse(buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_iffalse),
.iftrue(buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_iftrue),
.return_output(_0_)
);
assign buttons_or_uart_reg = _3_;
assign reg_comb_buttons_or_uart_reg = buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_return_output;
assign buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_cond = \global_to_module.frame_clock_falling_edge ;
assign buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_iftrue = bin_op_or_pipelinec_app_c_l144_c27_0888_return_output;
assign buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_iffalse = buttons_or_uart_reg;
assign buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_7f95_return_output = _0_;
assign bin_op_or_pipelinec_app_c_l144_c27_0888_left = \global_to_module.buttons ;
assign bin_op_or_pipelinec_app_c_l144_c27_0888_right = \global_to_module.uart_buttons ;
assign bin_op_or_pipelinec_app_c_l144_c27_0888_return_output = _1_;
assign \module_to_global.buttons_or_uart = buttons_or_uart_reg;
assign \module_to_global.uart_tx_mac_word_in = {
\global_to_module.frame_clock_rising_edge , 4'h0, buttons_or_uart_reg
};
endmodule
| 7.225107 |
module unary_op_not_uint17_t_0clk_de264c78 (
expr,
return_output
);
wire [16:0] _0_;
wire [50:0] \20110.read_pipe ;
input [16:0] expr;
wire [16:0] expr;
output [16:0] return_output;
wire [16:0] return_output;
assign _0_ = ~expr;
assign \20110.read_pipe = {expr, 34'hzzzzzzzzz};
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint18_t_0clk_de264c78 (
expr,
return_output
);
wire [17:0] _0_;
wire [53:0] \17950.read_pipe ;
input [17:0] expr;
wire [17:0] expr;
output [17:0] return_output;
wire [17:0] return_output;
assign _0_ = ~expr;
assign \17950.read_pipe = {expr, 36'hzzzzzzzzz};
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint1_t_0clk_de264c78 (
expr,
return_output
);
wire _0_;
wire [2:0] \2434.read_pipe ;
input expr;
wire expr;
output return_output;
wire return_output;
assign _0_ = ~expr;
assign \2434.read_pipe = {expr, 2'hz};
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint1_t_1clk_1891d2b1 (
clk,
expr,
return_output
);
wire _0_;
reg [5:0] _1_;
wire [2:0] \11747.read_pipe ;
input clk;
wire clk;
input expr;
wire expr;
wire [5:0] manual_registers;
wire [5:0] manual_registers_r;
output return_output;
wire return_output;
assign _0_ = ~manual_registers_r[5];
always @(posedge clk) _1_ <= manual_registers;
assign manual_registers = {
expr, \11747.read_pipe [1:0], manual_registers_r[5], _0_, manual_registers_r[5]
};
assign manual_registers_r = _1_;
assign \11747.read_pipe = manual_registers_r[5:3];
assign return_output = _0_;
endmodule
| 7.105344 |
module bin_op_neq_float_8_14_t_float_8_14_t_0clk_de264c78 (
left,
right,
return_output
);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
wire [93:0] \20050.read_pipe ;
input [22:0] left;
wire [22:0] left;
output return_output;
wire return_output;
input [22:0] right;
wire [22:0] right;
assign _0_ = left == right;
assign _1_ = 1'h1 & _0_;
assign _2_ = ~_1_;
assign _3_ = _2_ ? 1'h1 : 1'h0;
assign \20050.read_pipe = {left, right, 48'hzzzzzzzzzzzz};
assign return_output = _3_;
endmodule
| 6.532477 |
module fixed_to_float_0clk_419d9cb4 (
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_right;
wire [22:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
wire [21:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs;
output [22:0] return_output;
wire [22:0] return_output;
bin_op_sl_float_8_14_t_int5_t_0clk_e595f783 bin_op_sl_fixed_type_h_l169_c49_8ae1 (
.left(bin_op_sl_fixed_type_h_l169_c49_8ae1_left),
.return_output(_1_),
.right(bin_op_sl_fixed_type_h_l169_c49_8ae1_right)
);
cast_to_float_8_14_t_int22_t_0clk_c85e892e cast_to_float_8_14_t_fixed_type_h_l169_c49_6286 (
.return_output(_0_),
.rhs(cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs)
);
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs = \a.f ;
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output = _0_;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_left = cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_right = 5'h16;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output = _1_;
assign return_output = bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
endmodule
| 7.411582 |
module fixed_to_float_1clk_742dcbff (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_right;
wire [22:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
wire [21:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs;
input clk;
wire clk;
output [22:0] return_output;
wire [22:0] return_output;
bin_op_sl_float_8_14_t_int5_t_1clk_8b4ff545 bin_op_sl_fixed_type_h_l169_c49_8ae1 (
.clk(clk),
.left(bin_op_sl_fixed_type_h_l169_c49_8ae1_left),
.return_output(_1_),
.right(bin_op_sl_fixed_type_h_l169_c49_8ae1_right)
);
cast_to_float_8_14_t_int22_t_0clk_c85e892e cast_to_float_8_14_t_fixed_type_h_l169_c49_6286 (
.return_output(_0_),
.rhs(cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs)
);
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs = \a.f ;
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output = _0_;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_left = cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_right = 5'h16;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output = _1_;
assign return_output = bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
endmodule
| 7.411582 |
module fixed_to_float_1clk_7da43b21 (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_right;
wire [22:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
wire [21:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs;
input clk;
wire clk;
output [22:0] return_output;
wire [22:0] return_output;
bin_op_sl_float_8_14_t_int5_t_1clk_07337a26 bin_op_sl_fixed_type_h_l169_c49_8ae1 (
.clk(clk),
.left(bin_op_sl_fixed_type_h_l169_c49_8ae1_left),
.return_output(_1_),
.right(bin_op_sl_fixed_type_h_l169_c49_8ae1_right)
);
cast_to_float_8_14_t_int22_t_0clk_c85e892e cast_to_float_8_14_t_fixed_type_h_l169_c49_6286 (
.return_output(_0_),
.rhs(cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs)
);
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs = \a.f ;
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output = _0_;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_left = cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_right = 5'h16;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output = _1_;
assign return_output = bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
endmodule
| 7.411582 |
module fixed_to_float_1clk_b5c01c8b (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_right;
wire [22:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
wire [21:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs;
input clk;
wire clk;
output [22:0] return_output;
wire [22:0] return_output;
bin_op_sl_float_8_14_t_int5_t_1clk_0f9dc973 bin_op_sl_fixed_type_h_l169_c49_8ae1 (
.clk(clk),
.left(bin_op_sl_fixed_type_h_l169_c49_8ae1_left),
.return_output(_1_),
.right(bin_op_sl_fixed_type_h_l169_c49_8ae1_right)
);
cast_to_float_8_14_t_int22_t_0clk_c85e892e cast_to_float_8_14_t_fixed_type_h_l169_c49_6286 (
.return_output(_0_),
.rhs(cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs)
);
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs = \a.f ;
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output = _0_;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_left = cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_right = 5'h16;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output = _1_;
assign return_output = bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
endmodule
| 7.411582 |
module fixed_to_float_1clk_d2411c07 (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_right;
wire [22:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
wire [21:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs;
input clk;
wire clk;
output [22:0] return_output;
wire [22:0] return_output;
bin_op_sl_float_8_14_t_int5_t_0clk_e595f783 bin_op_sl_fixed_type_h_l169_c49_8ae1 (
.left(bin_op_sl_fixed_type_h_l169_c49_8ae1_left),
.return_output(_1_),
.right(bin_op_sl_fixed_type_h_l169_c49_8ae1_right)
);
cast_to_float_8_14_t_int22_t_1clk_e9f09518 cast_to_float_8_14_t_fixed_type_h_l169_c49_6286 (
.clk(clk),
.return_output(_0_),
.rhs(cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs)
);
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs = \a.f ;
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output = _0_;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_left = cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_right = 5'h16;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output = _1_;
assign return_output = bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
endmodule
| 7.411582 |
module fixed_to_float_1clk_e40e2927 (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_right;
wire [22:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
wire [21:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs;
input clk;
wire clk;
output [22:0] return_output;
wire [22:0] return_output;
bin_op_sl_float_8_14_t_int5_t_0clk_e595f783 bin_op_sl_fixed_type_h_l169_c49_8ae1 (
.left(bin_op_sl_fixed_type_h_l169_c49_8ae1_left),
.return_output(_1_),
.right(bin_op_sl_fixed_type_h_l169_c49_8ae1_right)
);
cast_to_float_8_14_t_int22_t_1clk_94c4a8b4 cast_to_float_8_14_t_fixed_type_h_l169_c49_6286 (
.clk(clk),
.return_output(_0_),
.rhs(cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs)
);
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs = \a.f ;
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output = _0_;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_left = cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_right = 5'h16;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output = _1_;
assign return_output = bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
endmodule
| 7.411582 |
module fixed_to_float_1clk_e8a081f4 (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_right;
wire [22:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
wire [21:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs;
input clk;
wire clk;
output [22:0] return_output;
wire [22:0] return_output;
bin_op_sl_float_8_14_t_int5_t_1clk_d0201478 bin_op_sl_fixed_type_h_l169_c49_8ae1 (
.clk(clk),
.left(bin_op_sl_fixed_type_h_l169_c49_8ae1_left),
.return_output(_1_),
.right(bin_op_sl_fixed_type_h_l169_c49_8ae1_right)
);
cast_to_float_8_14_t_int22_t_0clk_c85e892e cast_to_float_8_14_t_fixed_type_h_l169_c49_6286 (
.return_output(_0_),
.rhs(cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs)
);
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs = \a.f ;
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output = _0_;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_left = cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_right = 5'h16;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output = _1_;
assign return_output = bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
endmodule
| 7.411582 |
module fixed_to_float_1clk_f1263733 (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_right;
wire [22:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
wire [21:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs;
input clk;
wire clk;
output [22:0] return_output;
wire [22:0] return_output;
bin_op_sl_float_8_14_t_int5_t_1clk_08f2962a bin_op_sl_fixed_type_h_l169_c49_8ae1 (
.clk(clk),
.left(bin_op_sl_fixed_type_h_l169_c49_8ae1_left),
.return_output(_1_),
.right(bin_op_sl_fixed_type_h_l169_c49_8ae1_right)
);
cast_to_float_8_14_t_int22_t_0clk_c85e892e cast_to_float_8_14_t_fixed_type_h_l169_c49_6286 (
.return_output(_0_),
.rhs(cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs)
);
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs = \a.f ;
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output = _0_;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_left = cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_right = 5'h16;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output = _1_;
assign return_output = bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
endmodule
| 7.411582 |
module fixed_to_float_1clk_fc83ae6f (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_right;
wire [22:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
wire [21:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs;
input clk;
wire clk;
output [22:0] return_output;
wire [22:0] return_output;
bin_op_sl_float_8_14_t_int5_t_0clk_e595f783 bin_op_sl_fixed_type_h_l169_c49_8ae1 (
.left(bin_op_sl_fixed_type_h_l169_c49_8ae1_left),
.return_output(_1_),
.right(bin_op_sl_fixed_type_h_l169_c49_8ae1_right)
);
cast_to_float_8_14_t_int22_t_1clk_66b4a0af cast_to_float_8_14_t_fixed_type_h_l169_c49_6286 (
.clk(clk),
.return_output(_0_),
.rhs(cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs)
);
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs = \a.f ;
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output = _0_;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_left = cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_right = 5'h16;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output = _1_;
assign return_output = bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
endmodule
| 7.411582 |
module fixed_to_float_1clk_fd16488b (
clk,
\a.f ,
return_output
);
wire [22:0] _0_;
wire [22:0] _1_;
input [21:0] \a.f ;
wire [21:0] \a.f ;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_left;
wire [22:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
wire [ 4:0] bin_op_sl_fixed_type_h_l169_c49_8ae1_right;
wire [22:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
wire [21:0] cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs;
input clk;
wire clk;
output [22:0] return_output;
wire [22:0] return_output;
bin_op_sl_float_8_14_t_int5_t_0clk_e595f783 bin_op_sl_fixed_type_h_l169_c49_8ae1 (
.left(bin_op_sl_fixed_type_h_l169_c49_8ae1_left),
.return_output(_1_),
.right(bin_op_sl_fixed_type_h_l169_c49_8ae1_right)
);
cast_to_float_8_14_t_int22_t_1clk_791dfefe cast_to_float_8_14_t_fixed_type_h_l169_c49_6286 (
.clk(clk),
.return_output(_0_),
.rhs(cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs)
);
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_rhs = \a.f ;
assign cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output = _0_;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_left = cast_to_float_8_14_t_fixed_type_h_l169_c49_6286_return_output;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_right = 5'h16;
assign bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output = _1_;
assign return_output = bin_op_sl_fixed_type_h_l169_c49_8ae1_return_output;
endmodule
| 7.411582 |
module mux_uint1_t_hit_out_hit_out_0clk_de264c78 (
cond,
\iftrue.dist ,
\iftrue.borderdist ,
\iftrue.hit ,
\iffalse.dist ,
\iffalse.borderdist ,
\iffalse.hit ,
\return_output.dist ,
\return_output.borderdist ,
\return_output.hit
);
wire _0_;
wire [183:0] _1_;
wire [552:0] \12985.read_pipe ;
input cond;
wire cond;
input [22:0] \iffalse.borderdist ;
wire [22:0] \iffalse.borderdist ;
input [22:0] \iffalse.dist ;
wire [22:0] \iffalse.dist ;
input [137:0] \iffalse.hit ;
wire [137:0] \iffalse.hit ;
input [22:0] \iftrue.borderdist ;
wire [22:0] \iftrue.borderdist ;
input [22:0] \iftrue.dist ;
wire [22:0] \iftrue.dist ;
input [137:0] \iftrue.hit ;
wire [137:0] \iftrue.hit ;
output [22:0] \return_output.borderdist ;
wire [22:0] \return_output.borderdist ;
output [22:0] \return_output.dist ;
wire [22:0] \return_output.dist ;
output [137:0] \return_output.hit ;
wire [137:0] \return_output.hit ;
assign _0_ = cond == 1'h1;
assign _1_ = _0_ ? { \iftrue.hit , \iftrue.borderdist , \iftrue.dist } : { \iffalse.hit , \iffalse.borderdist , \iffalse.dist };
assign \12985.read_pipe = {
\iffalse.hit ,
\iffalse.borderdist ,
\iffalse.dist ,
\iftrue.hit ,
\iftrue.borderdist ,
\iftrue.dist ,
cond,
184'hzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
};
assign \return_output.dist = _1_[22:0];
assign \return_output.borderdist = _1_[45:23];
assign \return_output.hit = _1_[183:46];
endmodule
| 7.16061 |
module mux_uint1_t_hit_out_hit_out_1clk_72c91a3c (
clk,
cond,
\iftrue.dist ,
\iftrue.borderdist ,
\iftrue.hit ,
\iffalse.dist ,
\iffalse.borderdist ,
\iffalse.hit ,
\return_output.dist ,
\return_output.borderdist ,
\return_output.hit
);
wire _0_;
wire [183:0] _1_;
reg [1105:0] _2_;
wire [552:0] \32708.read_pipe ;
input clk;
wire clk;
input cond;
wire cond;
input [22:0] \iffalse.borderdist ;
wire [22:0] \iffalse.borderdist ;
input [22:0] \iffalse.dist ;
wire [22:0] \iffalse.dist ;
input [137:0] \iffalse.hit ;
wire [137:0] \iffalse.hit ;
input [22:0] \iftrue.borderdist ;
wire [22:0] \iftrue.borderdist ;
input [22:0] \iftrue.dist ;
wire [22:0] \iftrue.dist ;
input [137:0] \iftrue.hit ;
wire [ 137:0] \iftrue.hit ;
wire [1105:0] manual_registers;
wire [1105:0] manual_registers_r;
output [22:0] \return_output.borderdist ;
wire [22:0] \return_output.borderdist ;
output [22:0] \return_output.dist ;
wire [22:0] \return_output.dist ;
output [137:0] \return_output.hit ;
wire [137:0] \return_output.hit ;
assign _0_ = manual_registers_r[737] == 1'h1;
assign _1_ = _0_ ? manual_registers_r[921:738] : manual_registers_r[1105:922];
always @(posedge clk) _2_ <= manual_registers;
assign manual_registers = {
\iffalse.hit ,
\iffalse.borderdist ,
\iffalse.dist ,
\iftrue.hit ,
\iftrue.borderdist ,
\iftrue.dist ,
cond,
\32708.read_pipe [183:0],
manual_registers_r[1105:737],
_1_
};
assign manual_registers_r = _2_;
assign \32708.read_pipe = manual_registers_r[1105:553];
assign \return_output.dist = _1_[22:0];
assign \return_output.borderdist = _1_[45:23];
assign \return_output.hit = _1_[183:46];
endmodule
| 7.16061 |
module object_coord_to_float3_0clk_06be10dc (
\a.x ,
\a.y ,
\a.z ,
\return_output.x ,
\return_output.y ,
\return_output.z
);
wire [22:0] _0_;
wire [22:0] _1_;
wire [22:0] _2_;
input [21:0] \a.x ;
wire [21:0] \a.x ;
input [21:0] \a.y ;
wire [21:0] \a.y ;
input [21:0] \a.z ;
wire [21:0] \a.z ;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output;
output [22:0] \return_output.x ;
wire [22:0] \return_output.x ;
output [22:0] \return_output.y ;
wire [22:0] \return_output.y ;
output [22:0] \return_output.z ;
wire [22:0] \return_output.z ;
fixed_to_float_0clk_419d9cb4 fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a),
.return_output(_0_)
);
fixed_to_float_0clk_419d9cb4 fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a),
.return_output(_1_)
);
fixed_to_float_0clk_419d9cb4 fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a),
.return_output(_2_)
);
assign fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a = \a.x ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output = _0_;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a = \a.y ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output = _1_;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a = \a.z ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output = _2_;
assign \return_output.x = fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output;
assign \return_output.y = fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output;
assign \return_output.z = fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output;
endmodule
| 7.353216 |
module object_coord_to_float3_1clk_68a9f4f7 (
clk,
\a.x ,
\a.y ,
\a.z ,
\return_output.x ,
\return_output.y ,
\return_output.z
);
wire [22:0] _0_;
wire [22:0] _1_;
wire [22:0] _2_;
input [21:0] \a.x ;
wire [21:0] \a.x ;
input [21:0] \a.y ;
wire [21:0] \a.y ;
input [21:0] \a.z ;
wire [21:0] \a.z ;
input clk;
wire clk;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output;
output [22:0] \return_output.x ;
wire [22:0] \return_output.x ;
output [22:0] \return_output.y ;
wire [22:0] \return_output.y ;
output [22:0] \return_output.z ;
wire [22:0] \return_output.z ;
fixed_to_float_1clk_b5c01c8b fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a),
.clk(clk),
.return_output(_0_)
);
fixed_to_float_1clk_b5c01c8b fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a),
.clk(clk),
.return_output(_1_)
);
fixed_to_float_1clk_b5c01c8b fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a),
.clk(clk),
.return_output(_2_)
);
assign fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a = \a.x ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output = _0_;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a = \a.y ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output = _1_;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a = \a.z ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output = _2_;
assign \return_output.x = fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output;
assign \return_output.y = fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output;
assign \return_output.z = fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output;
endmodule
| 7.353216 |
module object_coord_to_float3_1clk_9710bca3 (
clk,
\a.x ,
\a.y ,
\a.z ,
\return_output.x ,
\return_output.y ,
\return_output.z
);
wire [22:0] _0_;
wire [22:0] _1_;
wire [22:0] _2_;
input [21:0] \a.x ;
wire [21:0] \a.x ;
input [21:0] \a.y ;
wire [21:0] \a.y ;
input [21:0] \a.z ;
wire [21:0] \a.z ;
input clk;
wire clk;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output;
output [22:0] \return_output.x ;
wire [22:0] \return_output.x ;
output [22:0] \return_output.y ;
wire [22:0] \return_output.y ;
output [22:0] \return_output.z ;
wire [22:0] \return_output.z ;
fixed_to_float_1clk_7da43b21 fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a),
.clk(clk),
.return_output(_0_)
);
fixed_to_float_1clk_7da43b21 fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a),
.clk(clk),
.return_output(_1_)
);
fixed_to_float_1clk_7da43b21 fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a),
.clk(clk),
.return_output(_2_)
);
assign fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a = \a.x ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output = _0_;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a = \a.y ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output = _1_;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a = \a.z ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output = _2_;
assign \return_output.x = fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output;
assign \return_output.y = fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output;
assign \return_output.z = fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output;
endmodule
| 7.353216 |
module object_coord_to_float3_1clk_cb94220f (
clk,
\a.x ,
\a.y ,
\a.z ,
\return_output.x ,
\return_output.y ,
\return_output.z
);
wire [22:0] _0_;
wire [22:0] _1_;
wire [22:0] _2_;
input [21:0] \a.x ;
wire [21:0] \a.x ;
input [21:0] \a.y ;
wire [21:0] \a.y ;
input [21:0] \a.z ;
wire [21:0] \a.z ;
input clk;
wire clk;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output;
output [22:0] \return_output.x ;
wire [22:0] \return_output.x ;
output [22:0] \return_output.y ;
wire [22:0] \return_output.y ;
output [22:0] \return_output.z ;
wire [22:0] \return_output.z ;
fixed_to_float_1clk_e40e2927 fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a),
.clk(clk),
.return_output(_0_)
);
fixed_to_float_1clk_e40e2927 fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a),
.clk(clk),
.return_output(_1_)
);
fixed_to_float_1clk_e40e2927 fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a),
.clk(clk),
.return_output(_2_)
);
assign fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a = \a.x ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output = _0_;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a = \a.y ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output = _1_;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a = \a.z ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output = _2_;
assign \return_output.x = fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output;
assign \return_output.y = fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output;
assign \return_output.z = fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output;
endmodule
| 7.353216 |
module object_coord_to_float3_1clk_d9f99e26 (
clk,
\a.x ,
\a.y ,
\a.z ,
\return_output.x ,
\return_output.y ,
\return_output.z
);
wire [22:0] _0_;
wire [22:0] _1_;
wire [22:0] _2_;
input [21:0] \a.x ;
wire [21:0] \a.x ;
input [21:0] \a.y ;
wire [21:0] \a.y ;
input [21:0] \a.z ;
wire [21:0] \a.z ;
input clk;
wire clk;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output;
wire [21:0] fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a;
wire [22:0] fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output;
output [22:0] \return_output.x ;
wire [22:0] \return_output.x ;
output [22:0] \return_output.y ;
wire [22:0] \return_output.y ;
output [22:0] \return_output.z ;
wire [22:0] \return_output.z ;
fixed_to_float_1clk_e8a081f4 fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a),
.clk(clk),
.return_output(_0_)
);
fixed_to_float_1clk_e8a081f4 fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a),
.clk(clk),
.return_output(_1_)
);
fixed_to_float_1clk_e8a081f4 fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e (
.\a.f (fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a),
.clk(clk),
.return_output(_2_)
);
assign fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_a = \a.x ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output = _0_;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_a = \a.y ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output = _1_;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_a = \a.z ;
assign fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output = _2_;
assign \return_output.x = fixed_to_float_tr_pipelinec_gen_c_l76_c15_1adf_return_output;
assign \return_output.y = fixed_to_float_tr_pipelinec_gen_c_l76_c36_a55e_return_output;
assign \return_output.z = fixed_to_float_tr_pipelinec_gen_c_l76_c57_ad2e_return_output;
endmodule
| 7.353216 |
module uart_buttons_rx_0clk_380ecc95 (
clk,
clock_enable,
\global_to_module.uart_rx_mac_word_out ,
\module_to_global.uart_buttons ,
\module_to_global.uart_rx_mac_out_ready
);
wire [3:0] _0_;
wire [3:0] _1_;
reg [3:0] _2_ = 4'h0;
input clk;
wire clk;
input clock_enable;
wire clock_enable;
input [8:0] \global_to_module.uart_rx_mac_word_out ;
wire [8:0] \global_to_module.uart_rx_mac_word_out ;
output [3:0] \module_to_global.uart_buttons ;
wire [3:0] \module_to_global.uart_buttons ;
output \module_to_global.uart_rx_mac_out_ready ;
wire \module_to_global.uart_rx_mac_out_ready ;
wire [3:0] reg_comb_uart_buttons_reg;
wire [3:0] uart_buttons_reg;
wire uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_cond;
wire [3:0] uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_iffalse;
wire [3:0] uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_iftrue;
wire [3:0] uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_return_output;
assign _1_ = clock_enable ? reg_comb_uart_buttons_reg : uart_buttons_reg;
always @(posedge clk) _2_ <= _1_;
mux_uint1_t_uint4_t_uint4_t_0clk_de264c78 uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5 (
.cond(uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_cond),
.iffalse(uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_iffalse),
.iftrue(uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_iftrue),
.return_output(_0_)
);
assign uart_buttons_reg = _2_;
assign reg_comb_uart_buttons_reg = uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_return_output;
assign uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_cond = \global_to_module.uart_rx_mac_word_out [8];
assign uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_iftrue = \global_to_module.uart_rx_mac_word_out [3:0];
assign uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_iffalse = uart_buttons_reg;
assign uart_buttons_reg_mux_pipelinec_app_c_l117_c3_20c5_return_output = _0_;
assign \module_to_global.uart_buttons = uart_buttons_reg;
assign \module_to_global.uart_rx_mac_out_ready = 1'h1;
endmodule
| 7.225107 |
module uart_buttons_tx_0clk_380ecc95 (
clk,
clock_enable,
\global_to_module.frame_clock_rising_edge ,
\global_to_module.frame_clock_falling_edge ,
\global_to_module.buttons ,
\global_to_module.uart_buttons ,
\module_to_global.buttons_or_uart ,
\module_to_global.uart_tx_mac_word_in
);
wire [3:0] _0_;
wire [3:0] _1_;
wire [3:0] _2_;
reg [3:0] _3_ = 4'h0;
wire [3:0] bin_op_or_pipelinec_app_c_l144_c27_f03d_left;
wire [3:0] bin_op_or_pipelinec_app_c_l144_c27_f03d_return_output;
wire [3:0] bin_op_or_pipelinec_app_c_l144_c27_f03d_right;
wire [3:0] buttons_or_uart_reg;
wire buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_cond;
wire [3:0] buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_iffalse;
wire [3:0] buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_iftrue;
wire [3:0] buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_return_output;
input clk;
wire clk;
input clock_enable;
wire clock_enable;
input [3:0] \global_to_module.buttons ;
wire [3:0] \global_to_module.buttons ;
input \global_to_module.frame_clock_falling_edge ;
wire \global_to_module.frame_clock_falling_edge ;
input \global_to_module.frame_clock_rising_edge ;
wire \global_to_module.frame_clock_rising_edge ;
input [3:0] \global_to_module.uart_buttons ;
wire [3:0] \global_to_module.uart_buttons ;
output [3:0] \module_to_global.buttons_or_uart ;
wire [3:0] \module_to_global.buttons_or_uart ;
output [8:0] \module_to_global.uart_tx_mac_word_in ;
wire [8:0] \module_to_global.uart_tx_mac_word_in ;
wire [3:0] reg_comb_buttons_or_uart_reg;
assign _2_ = clock_enable ? reg_comb_buttons_or_uart_reg : buttons_or_uart_reg;
always @(posedge clk) _3_ <= _2_;
bin_op_or_uint4_t_uint4_t_0clk_de264c78 bin_op_or_pipelinec_app_c_l144_c27_f03d (
.left(bin_op_or_pipelinec_app_c_l144_c27_f03d_left),
.return_output(_1_),
.right(bin_op_or_pipelinec_app_c_l144_c27_f03d_right)
);
mux_uint1_t_uint4_t_uint4_t_0clk_de264c78 buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e (
.cond(buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_cond),
.iffalse(buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_iffalse),
.iftrue(buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_iftrue),
.return_output(_0_)
);
assign buttons_or_uart_reg = _3_;
assign reg_comb_buttons_or_uart_reg = buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_return_output;
assign buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_cond = \global_to_module.frame_clock_falling_edge ;
assign buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_iftrue = bin_op_or_pipelinec_app_c_l144_c27_f03d_return_output;
assign buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_iffalse = buttons_or_uart_reg;
assign buttons_or_uart_reg_mux_pipelinec_app_c_l140_c3_490e_return_output = _0_;
assign bin_op_or_pipelinec_app_c_l144_c27_f03d_left = \global_to_module.buttons ;
assign bin_op_or_pipelinec_app_c_l144_c27_f03d_right = \global_to_module.uart_buttons ;
assign bin_op_or_pipelinec_app_c_l144_c27_f03d_return_output = _1_;
assign \module_to_global.buttons_or_uart = buttons_or_uart_reg;
assign \module_to_global.uart_tx_mac_word_in = {
\global_to_module.frame_clock_rising_edge , 4'h0, buttons_or_uart_reg
};
endmodule
| 7.225107 |
module unary_op_not_uint16_t_0clk_de264c78 (
expr,
return_output
);
wire [15:0] _0_;
wire [47:0] \33744.read_pipe ;
input [15:0] expr;
wire [15:0] expr;
output [15:0] return_output;
wire [15:0] return_output;
assign _0_ = ~expr;
assign \33744.read_pipe = {expr, 32'hzzzzzzzz};
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint16_t_1clk_22bc2879 (
clk,
expr,
return_output
);
wire [15:0] _0_;
reg [95:0] _1_;
wire [47:0] \37216.read_pipe ;
input clk;
wire clk;
input [15:0] expr;
wire [15:0] expr;
wire [95:0] manual_registers;
wire [95:0] manual_registers_r;
output [15:0] return_output;
wire [15:0] return_output;
assign _0_ = ~manual_registers_r[95:80];
always @(posedge clk) _1_ <= manual_registers;
assign manual_registers = {
expr, \37216.read_pipe [31:0], manual_registers_r[95:80], _0_, manual_registers_r[95:80]
};
assign manual_registers_r = _1_;
assign \37216.read_pipe = manual_registers_r[95:48];
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint16_t_1clk_41572785 (
clk,
expr,
return_output
);
wire [15:0] _0_;
reg [95:0] _1_;
wire [47:0] \52094.read_pipe ;
input clk;
wire clk;
input [15:0] expr;
wire [15:0] expr;
wire [95:0] manual_registers;
wire [95:0] manual_registers_r;
output [15:0] return_output;
wire [15:0] return_output;
assign _0_ = ~manual_registers_r[95:80];
always @(posedge clk) _1_ <= manual_registers;
assign manual_registers = {
expr, \52094.read_pipe [31:0], manual_registers_r[95:80], _0_, manual_registers_r[95:80]
};
assign manual_registers_r = _1_;
assign \52094.read_pipe = manual_registers_r[95:48];
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint16_t_1clk_dfdfc59e (
clk,
expr,
return_output
);
wire [15:0] _0_;
reg [95:0] _1_;
wire [47:0] \60639.read_pipe ;
input clk;
wire clk;
input [15:0] expr;
wire [15:0] expr;
wire [95:0] manual_registers;
wire [95:0] manual_registers_r;
output [15:0] return_output;
wire [15:0] return_output;
assign _0_ = ~manual_registers_r[95:80];
always @(posedge clk) _1_ <= manual_registers;
assign manual_registers = {
expr, \60639.read_pipe [31:0], manual_registers_r[95:80], _0_, manual_registers_r[95:80]
};
assign manual_registers_r = _1_;
assign \60639.read_pipe = manual_registers_r[95:48];
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint17_t_0clk_de264c78 (
expr,
return_output
);
wire [16:0] _0_;
wire [50:0] \8753.read_pipe ;
input [16:0] expr;
wire [16:0] expr;
output [16:0] return_output;
wire [16:0] return_output;
assign _0_ = ~expr;
assign \8753.read_pipe = {expr, 34'hzzzzzzzzz};
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint1_t_0clk_de264c78 (
expr,
return_output
);
wire _0_;
wire [2:0] \2845.read_pipe ;
input expr;
wire expr;
output return_output;
wire return_output;
assign _0_ = ~expr;
assign \2845.read_pipe = {expr, 2'hz};
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint1_t_1clk_ad90329c (
clk,
expr,
return_output
);
wire _0_;
reg [5:0] _1_;
wire [2:0] \51531.read_pipe ;
input clk;
wire clk;
input expr;
wire expr;
wire [5:0] manual_registers;
wire [5:0] manual_registers_r;
output return_output;
wire return_output;
assign _0_ = ~expr;
always @(posedge clk) _1_ <= manual_registers;
assign manual_registers = {expr, _0_, expr, manual_registers_r[5:3]};
assign manual_registers_r = _1_;
assign \51531.read_pipe = manual_registers_r[5:3];
assign return_output = manual_registers_r[4];
endmodule
| 7.105344 |
module unary_op_not_uint22_t_0clk_de264c78 (
expr,
return_output
);
wire [21:0] _0_;
wire [65:0] \13606.read_pipe ;
input [21:0] expr;
wire [21:0] expr;
output [21:0] return_output;
wire [21:0] return_output;
assign _0_ = ~expr;
assign \13606.read_pipe = {expr, 44'hzzzzzzzzzzz};
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint22_t_1clk_a1ec89d4 (
clk,
expr,
return_output
);
wire [ 21:0] _0_;
reg [131:0] _1_;
wire [ 65:0] \51949.read_pipe ;
input clk;
wire clk;
input [21:0] expr;
wire [ 21:0] expr;
wire [131:0] manual_registers;
wire [131:0] manual_registers_r;
output [21:0] return_output;
wire [21:0] return_output;
assign _0_ = ~manual_registers_r[131:110];
always @(posedge clk) _1_ <= manual_registers;
assign manual_registers = {
expr, \51949.read_pipe [43:0], manual_registers_r[131:110], _0_, manual_registers_r[131:110]
};
assign manual_registers_r = _1_;
assign \51949.read_pipe = manual_registers_r[131:66];
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint23_t_0clk_de264c78 (
expr,
return_output
);
wire [22:0] _0_;
wire [68:0] \33978.read_pipe ;
input [22:0] expr;
wire [22:0] expr;
output [22:0] return_output;
wire [22:0] return_output;
assign _0_ = ~expr;
assign \33978.read_pipe = {expr, 46'hzzzzzzzzzzzz};
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint23_t_1clk_0178b709 (
clk,
expr,
return_output
);
wire [ 22:0] _0_;
reg [137:0] _1_;
wire [ 68:0] \60218.read_pipe ;
input clk;
wire clk;
input [22:0] expr;
wire [ 22:0] expr;
wire [137:0] manual_registers;
wire [137:0] manual_registers_r;
output [22:0] return_output;
wire [22:0] return_output;
assign _0_ = ~manual_registers_r[137:115];
always @(posedge clk) _1_ <= manual_registers;
assign manual_registers = {
expr, \60218.read_pipe [45:0], manual_registers_r[137:115], _0_, manual_registers_r[137:115]
};
assign manual_registers_r = _1_;
assign \60218.read_pipe = manual_registers_r[137:69];
assign return_output = _0_;
endmodule
| 7.105344 |
module unary_op_not_uint23_t_1clk_9c9fdeb0 (
clk,
expr,
return_output
);
wire [ 22:0] _0_;
reg [137:0] _1_;
wire [ 68:0] \52012.read_pipe ;
input clk;
wire clk;
input [22:0] expr;
wire [ 22:0] expr;
wire [137:0] manual_registers;
wire [137:0] manual_registers_r;
output [22:0] return_output;
wire [22:0] return_output;
assign _0_ = ~expr;
always @(posedge clk) _1_ <= manual_registers;
assign manual_registers = {expr, _0_, expr, manual_registers_r[137:69]};
assign manual_registers_r = _1_;
assign \52012.read_pipe = manual_registers_r[137:69];
assign return_output = manual_registers_r[114:92];
endmodule
| 7.105344 |
module top (
input clk16,
input usb_d_p,
input usb_d_n,
output usb_pullup,
output user_led
);
wire sys_clk;
reg sys_rst = 1'd0;
wire clk16_1;
reg [23:0] count = 24'd0;
// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator
// to run the combinatorial process once at the beginning.
// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
assign sys_clk = clk16_1;
assign clk16_1 = clk16;
assign usb_pullup = 1'd0;
assign user_led = count[22];
always @(posedge sys_clk) begin
count <= (count + 1'd1);
if (sys_rst) begin
count <= 24'd0;
end
end
endmodule
| 7.233807 |
module top (
input clk16,
input usb_d_p,
input usb_d_n,
output usb_pullup,
output user_led
);
wire sys_clk;
reg sys_rst = 1'd0;
wire clk16_1;
wire clk16b;
reg [23:0] count = 24'd0;
// Adding a dummy event (using a dummy signal 'dummy_s') to get the simulator
// to run the combinatorial process once at the beginning.
// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
assign clk16_1 = clk16;
assign usb_pullup = 1'd0;
assign user_led = count[22];
always @(posedge sys_clk) begin
count <= (count + 1'd1);
if (sys_rst) begin
count <= 24'd0;
end
end
SB_PLL40_CORE #(
.DIVF(6'd63),
.DIVQ(3'd6),
.DIVR(1'd0),
.FILTER_RANGE(3'd1)
) SB_PLL40_CORE (
.REFERENCECLK(clk16_1),
.RESETB(1'd1),
.PLLOUTCORE(clk16b)
);
SB_GB SB_GB (
.USER_SIGNAL_TO_GLOBAL_BUFFER(clk16b),
.GLOBAL_BUFFER_OUTPUT(sys_clk)
);
endmodule
| 7.233807 |
module top (
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk_125mhz,
input wire rst_125mhz,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;
wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;
uart uart_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(uart_tx_axis_tdata),
.s_axis_tvalid(uart_tx_axis_tvalid),
.s_axis_tready(uart_tx_axis_tready),
// AXI output
.m_axis_tdata(uart_rx_axis_tdata),
.m_axis_tvalid(uart_rx_axis_tvalid),
.m_axis_tready(uart_rx_axis_tready),
// uart
.rxd(uart_txd),
.txd(uart_rxd),
// status
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
// configuration
.prescale(125000000 / (9600 * 8))
);
//assign led = sw;
assign led = uart_tx_axis_tdata;
assign phy_reset_n = ~rst_125mhz;
assign phy_gtx_clk = 1'b0;
assign phy_txd = 8'd0;
assign phy_tx_en = 1'b0;
assign phy_tx_er = 1'b0;
always @(posedge clk_125mhz or posedge rst_125mhz) begin
if (rst_125mhz) begin
uart_tx_axis_tdata <= 0;
uart_tx_axis_tvalid <= 0;
uart_rx_axis_tready <= 0;
end else begin
if (uart_tx_axis_tvalid) begin
// attempting to transmit a byte
// so can't receive one at the moment
uart_rx_axis_tready <= 0;
// if it has been received, then clear the valid flag
if (uart_tx_axis_tready) begin
uart_tx_axis_tvalid <= 0;
end
end else begin
// ready to receive byte
uart_rx_axis_tready <= 1;
if (uart_rx_axis_tvalid) begin
// got one, so make sure it gets the correct ready signal
// (either clear it if it was set or set it if we just got a
// byte out of waiting for the transmitter to send one)
uart_rx_axis_tready <= ~uart_rx_axis_tready;
// send byte back out
uart_tx_axis_tdata <= uart_rx_axis_tdata;
uart_tx_axis_tvalid <= 1;
end
end
end
end
endmodule
| 7.364191 |
module consume_cdc (
sdram_clk,
consume_r_gry,
consume_w_gry,
sdram_rst
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/fifo.py:353" *)
input [2:0] consume_r_gry;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/fifo.py:354" *)
output [2:0] consume_w_gry;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/clks.py:53" *)
input sdram_clk;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/clks.py:53" *)
input sdram_rst;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/cdc.py:89" *)
reg [2:0] stage0 = 3'h0;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/cdc.py:89" *)
wire [2:0] \stage0$next ;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/cdc.py:89" *)
reg [2:0] stage1 = 3'h0;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/cdc.py:89" *)
wire [2:0] \stage1$next ;
always @(posedge sdram_clk) stage0 <= \stage0$next ;
always @(posedge sdram_clk) stage1 <= \stage1$next ;
assign consume_w_gry = stage1;
assign \stage1$next = stage0;
assign \stage0$next = consume_r_gry;
endmodule
| 6.606069 |
module i_button_ffsync (
i_unsync_buttons__fireA,
i_unsync_buttons__fireB,
i_unsync_buttons__up,
i_unsync_buttons__down,
i_unsync_buttons__left,
i_unsync_buttons__right,
i_buttons__pwr,
rst,
clk,
i_unsync_buttons__pwr
);
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/clks.py:52" *)
input clk;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:94" *)
wire i_buttons__down;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:94" *)
wire i_buttons__fireA;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:94" *)
wire i_buttons__fireB;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:94" *)
wire i_buttons__left;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:94" *)
output i_buttons__pwr;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:94" *)
wire i_buttons__right;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:94" *)
wire i_buttons__up;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:67" *)
input i_unsync_buttons__down;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:67" *)
input i_unsync_buttons__fireA;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:67" *)
input i_unsync_buttons__fireB;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:67" *)
input i_unsync_buttons__left;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:67" *)
input i_unsync_buttons__pwr;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:67" *)
input i_unsync_buttons__right;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/upload.py:67" *)
input i_unsync_buttons__up;
(* src = "/home/ubuntu/from_host/x/Documents/git_repos/gateware/amtest/amtest/boards/ulx3s/common/clks.py:52" *)
input rst;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/cdc.py:89" *)
reg [6:0] stage0 = 7'h00;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/cdc.py:89" *)
wire [6:0] \stage0$next ;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/cdc.py:89" *)
reg [6:0] stage1 = 7'h00;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/lib/cdc.py:89" *)
wire [6:0] \stage1$next ;
always @(posedge clk) stage0 <= \stage0$next ;
always @(posedge clk) stage1 <= \stage1$next ;
assign { i_buttons__right, i_buttons__left, i_buttons__down, i_buttons__up, i_buttons__fireB, i_buttons__fireA, i_buttons__pwr } = stage1;
assign \stage1$next = stage0;
assign \stage0$next = {
i_unsync_buttons__right,
i_unsync_buttons__left,
i_unsync_buttons__down,
i_unsync_buttons__up,
i_unsync_buttons__fireB,
i_unsync_buttons__fireA,
i_unsync_buttons__pwr
};
endmodule
| 7.190546 |
module pin_button_pwr_0 (
button_pwr_0__io,
button_pwr_0__i
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/vendor/lattice_ecp5.py:465" *)
wire \$1 ;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
output button_pwr_0__i;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/vendor/lattice_ecp5.py:464" *)
wire button_pwr_0__i_n;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
input button_pwr_0__io;
assign \$1 = ~ (* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/vendor/lattice_ecp5.py:465" *) button_pwr_0__i_n;
IB button_pwr_0_0 (
.I(button_pwr_0__io),
.O(button_pwr_0__i_n)
);
assign button_pwr_0__i = \$1 ;
endmodule
| 7.276041 |
module pin_esp32_spi_0__en (
esp32_spi_0__en__io,
esp32_spi_0__en__o
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
output esp32_spi_0__en__io;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
input esp32_spi_0__en__o;
OB esp32_spi_0__en_0 (
.I(esp32_spi_0__en__o),
.O(esp32_spi_0__en__io)
);
endmodule
| 6.569117 |
module pin_esp32_spi_0__gpio0 (
esp32_spi_0__gpio0__io,
esp32_spi_0__gpio0__o
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/vendor/lattice_ecp5.py:531" *)
wire \$1 ;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
wire esp32_spi_0__gpio0__i;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
inout esp32_spi_0__gpio0__io;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
input esp32_spi_0__gpio0__o;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
wire esp32_spi_0__gpio0__oe;
BB esp32_spi_0__gpio0_0 (
.B(esp32_spi_0__gpio0__io),
.I(esp32_spi_0__gpio0__o),
.O(esp32_spi_0__gpio0__i),
.T(1'h1)
);
assign esp32_spi_0__gpio0__oe = 1'h0;
assign \$1 = 1'h1;
endmodule
| 6.569117 |
module pin_esp32_spi_0__gpio12_cipo (
esp32_spi_0__gpio12_cipo__io
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
output esp32_spi_0__gpio12_cipo__io;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
wire esp32_spi_0__gpio12_cipo__o;
OB esp32_spi_0__gpio12_cipo_0 (
.I(1'h0),
.O(esp32_spi_0__gpio12_cipo__io)
);
assign esp32_spi_0__gpio12_cipo__o = 1'h0;
endmodule
| 6.569117 |
module pin_esp32_spi_0__gpio16_sclk (
esp32_spi_0__gpio16_sclk__io
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
wire esp32_spi_0__gpio16_sclk__i;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
input esp32_spi_0__gpio16_sclk__io;
IB esp32_spi_0__gpio16_sclk_0 (
.I(esp32_spi_0__gpio16_sclk__io),
.O(esp32_spi_0__gpio16_sclk__i)
);
endmodule
| 6.569117 |
module pin_esp32_spi_0__gpio4_copi (
esp32_spi_0__gpio4_copi__io
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
wire esp32_spi_0__gpio4_copi__i;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
input esp32_spi_0__gpio4_copi__io;
IB esp32_spi_0__gpio4_copi_0 (
.I(esp32_spi_0__gpio4_copi__io),
.O(esp32_spi_0__gpio4_copi__i)
);
endmodule
| 6.569117 |
module pin_esp32_spi_0__gpio5_cs (
esp32_spi_0__gpio5_cs__io
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/vendor/lattice_ecp5.py:465" *)
wire \$1 ;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
wire esp32_spi_0__gpio5_cs__i;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/vendor/lattice_ecp5.py:464" *)
wire esp32_spi_0__gpio5_cs__i_n;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
input esp32_spi_0__gpio5_cs__io;
assign \$1 = ~ (* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/vendor/lattice_ecp5.py:465" *) esp32_spi_0__gpio5_cs__i_n;
IB esp32_spi_0__gpio5_cs_0 (
.I(esp32_spi_0__gpio5_cs__io),
.O(esp32_spi_0__gpio5_cs__i_n)
);
assign esp32_spi_0__gpio5_cs__i = \$1 ;
endmodule
| 6.569117 |
module pin_esp32_spi_0__rx (
esp32_spi_0__rx__io,
esp32_spi_0__rx__i
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
output esp32_spi_0__rx__i;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
input esp32_spi_0__rx__io;
IB esp32_spi_0__rx_0 (
.I(esp32_spi_0__rx__io),
.O(esp32_spi_0__rx__i)
);
endmodule
| 6.569117 |
module pin_esp32_spi_0__tx (
esp32_spi_0__tx__io,
esp32_spi_0__tx__o
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
output esp32_spi_0__tx__io;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
input esp32_spi_0__tx__o;
OB esp32_spi_0__tx_0 (
.I(esp32_spi_0__tx__o),
.O(esp32_spi_0__tx__io)
);
endmodule
| 6.569117 |
module pin_uart_0__tx (
uart_0__tx__io,
uart_0__tx__o
);
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:129" *)
output uart_0__tx__io;
(* src = "/home/ubuntu/Documents/venv_fpga/lib/python3.8/site-packages/amaranth/build/res.py:143" *)
input uart_0__tx__o;
OB uart_0__tx_0 (
.I(uart_0__tx__o),
.O(uart_0__tx__io)
);
endmodule
| 6.500531 |
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