code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Queue_3 (
input clk,
input reset,
output io_enq_ready,
input io_enq_valid,
input [1:0] io_enq_bits_resp,
input [4:0] io_enq_bits_id,
input io_enq_bits_user,
input io_deq_ready,
output io_deq_valid,
output [1:0] io_deq_bits_resp,
output [4:0] io_deq_bits_id,
output io_deq_bits_user,
output [1:0] io_count
);
wire [1:0] T0;
wire ptr_diff;
reg R1;
wire T21;
wire T2;
wire T3;
wire do_deq;
reg R4;
wire T22;
wire T5;
wire T6;
wire do_enq;
wire T7;
wire ptr_match;
reg maybe_full;
wire T23;
wire T8;
wire T9;
wire T10;
wire [7:0] T11;
reg [7:0] ram[1:0];
wire [7:0] T12;
wire [7:0] T13;
wire [7:0] T14;
wire [5:0] T15;
wire [4:0] T16;
wire [1:0] T17;
wire T18;
wire empty;
wire T19;
wire T20;
wire full;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
R1 = {1{$random}};
R4 = {1{$random}};
maybe_full = {1{$random}};
for (initvar = 0; initvar < 2; initvar = initvar + 1) ram[initvar] = {1{$random}};
end
// synthesis translate_on
`endif
assign io_count = T0;
assign T0 = {T7, ptr_diff};
assign ptr_diff = R4 - R1;
assign T21 = reset ? 1'h0 : T2;
assign T2 = do_deq ? T3 : R1;
assign T3 = R1 + 1'h1;
assign do_deq = io_deq_ready & io_deq_valid;
assign T22 = reset ? 1'h0 : T5;
assign T5 = do_enq ? T6 : R4;
assign T6 = R4 + 1'h1;
assign do_enq = io_enq_ready & io_enq_valid;
assign T7 = maybe_full & ptr_match;
assign ptr_match = R4 == R1;
assign T23 = reset ? 1'h0 : T8;
assign T8 = T9 ? do_enq : maybe_full;
assign T9 = do_enq != do_deq;
assign io_deq_bits_user = T10;
assign T10 = T11[0];
assign T11 = ram[R1];
assign T13 = T14;
assign T14 = {io_enq_bits_resp, T15};
assign T15 = {io_enq_bits_id, io_enq_bits_user};
assign io_deq_bits_id = T16;
assign T16 = T11[5:1];
assign io_deq_bits_resp = T17;
assign T17 = T11[7:6];
assign io_deq_valid = T18;
assign T18 = empty ^ 1'h1;
assign empty = ptr_match & T19;
assign T19 = maybe_full ^ 1'h1;
assign io_enq_ready = T20;
assign T20 = full ^ 1'h1;
assign full = ptr_match & maybe_full;
always @(posedge clk) begin
if (reset) begin
R1 <= 1'h0;
end else if (do_deq) begin
R1 <= T3;
end
if (reset) begin
R4 <= 1'h0;
end else if (do_enq) begin
R4 <= T6;
end
if (reset) begin
maybe_full <= 1'h0;
end else if (T9) begin
maybe_full <= do_enq;
end
if (do_enq) ram[R4] <= T13;
end
endmodule
| 6.517764 |
module FlowThroughSerializer_1 (
output io_in_ready,
input io_in_valid,
input [1:0] io_in_bits_addr_beat,
input [1:0] io_in_bits_client_xact_id,
input [2:0] io_in_bits_manager_xact_id,
input io_in_bits_is_builtin_type,
input [3:0] io_in_bits_g_type,
input [127:0] io_in_bits_data,
input io_out_ready,
output io_out_valid,
output [1:0] io_out_bits_addr_beat,
output [1:0] io_out_bits_client_xact_id,
output [2:0] io_out_bits_manager_xact_id,
output io_out_bits_is_builtin_type,
output [3:0] io_out_bits_g_type,
output [127:0] io_out_bits_data,
output io_cnt,
output io_done
);
assign io_done = 1'h1;
assign io_cnt = 1'h0;
assign io_out_bits_data = io_in_bits_data;
assign io_out_bits_g_type = io_in_bits_g_type;
assign io_out_bits_is_builtin_type = io_in_bits_is_builtin_type;
assign io_out_bits_manager_xact_id = io_in_bits_manager_xact_id;
assign io_out_bits_client_xact_id = io_in_bits_client_xact_id;
assign io_out_bits_addr_beat = io_in_bits_addr_beat;
assign io_out_valid = io_in_valid;
assign io_in_ready = io_out_ready;
endmodule
| 6.711201 |
module FlowThroughSerializer_0 (
output io_in_ready,
input io_in_valid,
input [1:0] io_in_bits_addr_beat,
input [1:0] io_in_bits_client_xact_id,
input [2:0] io_in_bits_manager_xact_id,
input io_in_bits_is_builtin_type,
input [3:0] io_in_bits_g_type,
input [127:0] io_in_bits_data,
input io_in_bits_manager_id,
input io_out_ready,
output io_out_valid,
output [1:0] io_out_bits_addr_beat,
output [1:0] io_out_bits_client_xact_id,
output [2:0] io_out_bits_manager_xact_id,
output io_out_bits_is_builtin_type,
output [3:0] io_out_bits_g_type,
output [127:0] io_out_bits_data,
output io_out_bits_manager_id,
output io_cnt,
output io_done
);
assign io_done = 1'h1;
assign io_cnt = 1'h0;
assign io_out_bits_manager_id = io_in_bits_manager_id;
assign io_out_bits_data = io_in_bits_data;
assign io_out_bits_g_type = io_in_bits_g_type;
assign io_out_bits_is_builtin_type = io_in_bits_is_builtin_type;
assign io_out_bits_manager_xact_id = io_in_bits_manager_xact_id;
assign io_out_bits_client_xact_id = io_in_bits_client_xact_id;
assign io_out_bits_addr_beat = io_in_bits_addr_beat;
assign io_out_valid = io_in_valid;
assign io_in_ready = io_out_ready;
endmodule
| 6.711201 |
module RecFNToRecFN (
input [32:0] io_in,
input [ 1:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire [4:0] T0;
wire invalidExc;
wire T1;
wire T2;
wire [55:0] outRawFloat_sig;
wire [55:0] T3;
wire [26:0] T4;
wire [26:0] T5;
wire [24:0] T6;
wire [22:0] T7;
wire outRawFloat_isNaN;
wire T8;
wire T9;
wire T10;
wire [8:0] T11;
wire T12;
wire [1:0] T13;
wire [64:0] T14;
wire [63:0] T15;
wire [51:0] T16;
wire [51:0] T17;
wire [11:0] T18;
wire [11:0] T19;
wire [11:0] T20;
wire [11:0] T21;
wire outRawFloat_isInf;
wire T22;
wire T23;
wire T24;
wire T25;
wire [11:0] T26;
wire [11:0] T27;
wire [11:0] T28;
wire T29;
wire outRawFloat_isZero;
wire T30;
wire T31;
wire [2:0] T32;
wire [11:0] T33;
wire [11:0] T34;
wire [11:0] T35;
wire [11:0] T36;
wire [12:0] outRawFloat_sExp;
wire [12:0] T45;
wire [11:0] T37;
wire [11:0] T46;
wire [9:0] T38;
wire [9:0] T39;
wire [9:0] T40;
wire [1:0] T47;
wire T48;
wire T49;
wire T41;
wire T42;
wire outRawFloat_sign;
wire T43;
wire T44;
assign io_exceptionFlags = T0;
assign T0 = {invalidExc, 4'h0};
assign invalidExc = outRawFloat_isNaN & T1;
assign T1 = T2 ^ 1'h1;
assign T2 = outRawFloat_sig[53];
assign outRawFloat_sig = T3;
assign T3 = T4 << 5'h1d;
assign T4 = T5;
assign T5 = {2'h1, T6};
assign T6 = {T7, 2'h0};
assign T7 = io_in[22:0];
assign outRawFloat_isNaN = T8;
assign T8 = T9;
assign T9 = T12 & T10;
assign T10 = T11[6];
assign T11 = io_in[31:23];
assign T12 = T13 == 2'h3;
assign T13 = T11[8:7];
assign io_out = T14;
assign T14 = {T41, T15};
assign T15 = {T18, T16};
assign T16 = outRawFloat_isNaN ? 52'h8000000000000 : T17;
assign T17 = outRawFloat_sig[53:2];
assign T18 = T20 | T19;
assign T19 = outRawFloat_isNaN ? 12'he00 : 12'h0;
assign T20 = T26 | T21;
assign T21 = outRawFloat_isInf ? 12'hc00 : 12'h0;
assign outRawFloat_isInf = T22;
assign T22 = T23;
assign T23 = T12 & T24;
assign T24 = T25 ^ 1'h1;
assign T25 = T11[6];
assign T26 = T33 & T27;
assign T27 = ~T28;
assign T28 = T29 ? 12'h200 : 12'h0;
assign T29 = outRawFloat_isZero | outRawFloat_isInf;
assign outRawFloat_isZero = T30;
assign T30 = T31;
assign T31 = T32 == 3'h0;
assign T32 = T11[8:6];
assign T33 = T36 & T34;
assign T34 = ~T35;
assign T35 = outRawFloat_isZero ? 12'hc00 : 12'h0;
assign T36 = outRawFloat_sExp[11:0];
assign outRawFloat_sExp = T45;
assign T45 = {T49, T37};
assign T37 = T46 + 12'h700;
assign T46 = {T47, T38};
assign T38 = T39;
assign T39 = T40;
assign T40 = {1'h0, T11};
assign T47 = T48 ? 2'h3 : 2'h0;
assign T48 = T38[9];
assign T49 = T37[11];
assign T41 = outRawFloat_sign & T42;
assign T42 = outRawFloat_isNaN ^ 1'h1;
assign outRawFloat_sign = T43;
assign T43 = T44;
assign T44 = io_in[32];
endmodule
| 6.761906 |
module DivSqrtRecF64 (
input clk,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [1:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
wire T0;
wire ds_io_inReady_div;
wire ds_io_inReady_sqrt;
wire ds_io_outValid_div;
wire ds_io_outValid_sqrt;
wire [64:0] ds_io_out;
wire [4:0] ds_io_exceptionFlags;
wire [3:0] ds_io_usingMulAdd;
wire ds_io_latchMulAddA_0;
wire [53:0] ds_io_mulAddA_0;
wire ds_io_latchMulAddB_0;
wire [53:0] ds_io_mulAddB_0;
wire [104:0] ds_io_mulAddC_2;
wire [104:0] mul_io_result_s3;
assign T0 = ds_io_usingMulAdd[0];
assign io_exceptionFlags = ds_io_exceptionFlags;
assign io_out = ds_io_out;
assign io_outValid_sqrt = ds_io_outValid_sqrt;
assign io_outValid_div = ds_io_outValid_div;
assign io_inReady_sqrt = ds_io_inReady_sqrt;
assign io_inReady_div = ds_io_inReady_div;
DivSqrtRecF64_mulAddZ31 ds (
.clk(clk),
.reset(reset),
.io_inReady_div(ds_io_inReady_div),
.io_inReady_sqrt(ds_io_inReady_sqrt),
.io_inValid(io_inValid),
.io_sqrtOp(io_sqrtOp),
.io_a(io_a),
.io_b(io_b),
.io_roundingMode(io_roundingMode),
.io_outValid_div(ds_io_outValid_div),
.io_outValid_sqrt(ds_io_outValid_sqrt),
.io_out(ds_io_out),
.io_exceptionFlags(ds_io_exceptionFlags),
.io_usingMulAdd(ds_io_usingMulAdd),
.io_latchMulAddA_0(ds_io_latchMulAddA_0),
.io_mulAddA_0(ds_io_mulAddA_0),
.io_latchMulAddB_0(ds_io_latchMulAddB_0),
.io_mulAddB_0(ds_io_mulAddB_0),
.io_mulAddC_2(ds_io_mulAddC_2),
.io_mulAddResult_3(mul_io_result_s3)
);
Mul54 mul (
.clk(clk),
.io_val_s0(T0),
.io_latch_a_s0(ds_io_latchMulAddA_0),
.io_a_s0(ds_io_mulAddA_0),
.io_latch_b_s0(ds_io_latchMulAddB_0),
.io_b_s0(ds_io_mulAddB_0),
.io_c_s2(ds_io_mulAddC_2),
.io_result_s3(mul_io_result_s3)
);
endmodule
| 6.793472 |
module DataArray_T9 (
input CLK,
input RST,
input init,
input [7:0] W0A,
input W0E,
input [127:0] W0I,
input [127:0] W0M,
input [7:0] R1A,
input R1E,
output [127:0] R1O
);
`ifndef SYNTHESIS
integer i;
integer j;
always @(posedge CLK) begin
for (i = 0; i < 2; i = i + 64) begin
for (j = 1; j < 64; j = j + 1) begin
if (W0M[i] != W0M[i+j]) begin
$fwrite(32'h80000002, "ASSERTION FAILED: write mask granularity\n");
$finish;
end
end
end
end
`endif
reg [127:0] ram[255:0];
`ifndef SYNTHESIS
integer initvar;
initial begin
#0.002;
for (initvar = 0; initvar < 256; initvar = initvar + 1) ram[initvar] = {4{$random}};
end
`endif
reg [7:0] reg_R1A;
always @(posedge CLK) begin
if (R1E) reg_R1A <= R1A;
if (W0E && W0M[0]) ram[W0A][63:0] <= W0I[63:0];
if (W0E && W0M[64]) ram[W0A][127:64] <= W0I[127:64];
end
assign R1O = ram[reg_R1A];
endmodule
| 6.622475 |
module MetadataArray_T6 (
input CLK,
input RST,
input init,
input [5:0] W0A,
input W0E,
input [87:0] W0I,
input [87:0] W0M,
input [5:0] R1A,
input R1E,
output [87:0] R1O
);
`ifndef SYNTHESIS
integer i;
integer j;
always @(posedge CLK) begin
for (i = 0; i < 4; i = i + 22) begin
for (j = 1; j < 22; j = j + 1) begin
if (W0M[i] != W0M[i+j]) begin
$fwrite(32'h80000002, "ASSERTION FAILED: write mask granularity\n");
$finish;
end
end
end
end
`endif
reg [87:0] ram[63:0];
`ifndef SYNTHESIS
integer initvar;
initial begin
#0.002;
for (initvar = 0; initvar < 64; initvar = initvar + 1) ram[initvar] = {3{$random}};
end
`endif
reg [5:0] reg_R1A;
always @(posedge CLK) begin
if (R1E) reg_R1A <= R1A;
if (W0E && W0M[0]) ram[W0A][21:0] <= W0I[21:0];
if (W0E && W0M[22]) ram[W0A][43:22] <= W0I[43:22];
if (W0E && W0M[44]) ram[W0A][65:44] <= W0I[65:44];
if (W0E && W0M[66]) ram[W0A][87:66] <= W0I[87:66];
end
assign R1O = ram[reg_R1A];
endmodule
| 6.901681 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] D_o;
reg A_sign;
reg B_sign;
reg add_sign;
localparam a_width = MAN+1+2; // width of sum after rounding (_sum)
// addr_width should be less than EXPONENT
localparam addr_width = log(a_width);
`include "misc.v"
`include "DW_lzd_function.inc"
reg [addr_width-1:0] num_zeros;
initial begin
clk = 1'b1;
A_i = 32'h0;
B_i = 32'h0;
#10
A_i = 32'h3e71d0a6; // 0.236147 32'hbedd039c; //0.432688 32'h3e71d0a6; // 0.236147 32'h423c0000; //47
B_i = 32'hbe71d0a5; // 0.236147 32'hbfa6a865; //1.302014 32'h3f2f9e2c; // 0.686007 32'h42380000; //46
//Ai = {1'b1,A_i[MAN-1:0],2'b00};
//Bi = {1'b1,B_i[MAN-1:0],2'b00};
#100
$display("[%t] : A_i: %h, B_i: %h\n", $realtime, A_i, B_i);
$display("[%t] : A_sign:%h, B_sign:%h\n", $realtime, A_sign, B_sign);
$display("[%t] : D_o:%h\n", $realtime, D_o);
$display("[%t] : add_sign:%b\n", $realtime, add_sign);
$finish;
end
fp_adder2#(
.EXPONENT(EXP),
.MANTISSA(MAN)
) fpadder2(
.a1(A_i),
.a2(B_i),
.add_sign(add_sign),
.adder_o(D_o)
);
always #10 clk=~clk;
initial begin
if ($test$plusargs ("dump_all")) begin
`ifdef NCV // Cadence TRN dump
$recordsetup("design=board",
"compress",
"wrapsize=100M",
"version=1",
"run=1");
$recordvars();
`elsif VCS //Synopsys VPD dump
$vcdplusfile("board.vpd");
$vcdpluson;
$vcdplusglitchon;
$vcdplusflush;
`else
// Verilog VC dump
$dumpfile("board.vcd");
$dumpvars(0, board);
`endif
end
end
endmodule
| 6.608387 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] C_i;
reg [EXP+MAN:0] D_o;
reg A_sign;
reg B_sign;
reg C_sign;
localparam a_width = MAN+1+2; // width of sum after rounding (_sum)
// addr_width should be less than EXPONENT
localparam addr_width = log(a_width);
`include "misc.v"
`include "DW_lzd_function.inc"
reg [addr_width-1:0] num_zeros;
initial begin
clk = 1'b1;
A_i = 32'h0;
B_i = 32'h0;
C_i = 32'h0;
#10
A_i = 32'h423c0000; //47 32'h3edd039c; //0.432688 32'h3e71d0a6; // 0.236147
B_i = 32'h42380000; //46 32'h3fa6a865; //1.302014 32'h3f2f9e2c; // 0.686007
C_i = 32'h42840000; //66 32'h3efad8c4; //0.489935 32'hbc81abaa; //-0.015829
//Ai = {1'b1,A_i[MAN-1:0],2'b00};
//Bi = {1'b1,B_i[MAN-1:0],2'b00};
//Ci = {1'b1,C_i[MAN-1:0],2'b00};
#100
$display("[%t] : A_i: %h, B_i: %h C_i: %h\n", $realtime, A_i, B_i, C_i);
$display("[%t] : A_sign:%h, B_sign:%h, C_sign:%h\n", $realtime, A_sign, B_sign, C_sign);
$display("[%t] : D_o:%h\n", $realtime, D_o);
$finish;
end
fp_adder#(
.EXPONENT(EXP),
.MANTISSA(MAN)
) fpadder(
.clk(clk),
.a1(A_i),
.a2(B_i),
.a3(C_i),
.adder_o(D_o)
);
always #10 clk=~clk;
initial begin
if ($test$plusargs ("dump_all")) begin
`ifdef NCV // Cadence TRN dump
$recordsetup("design=board",
"compress",
"wrapsize=100M",
"version=1",
"run=1");
$recordvars();
`elsif VCS //Synopsys VPD dump
$vcdplusfile("board.vpd");
$vcdpluson;
$vcdplusglitchon;
$vcdplusflush;
`else
// Verilog VC dump
$dumpfile("board.vcd");
$dumpvars(0, board);
`endif
end
end
endmodule
| 6.608387 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] C_i;
reg [MAN+2:0] A_o;
reg [MAN+2:0] B_o;
reg [MAN+2:0] C_o;
reg [MAN+2:0] D_o;
reg A_sign;
reg B_sign;
reg C_sign;
initial begin
clk = 1'b1;
A_i = 32'h0;
B_i = 32'h0;
C_i = 32'h0;
#10
A_i = 32'h3e71d0a6;
B_i = 32'h3f2f9e2c;
C_i = 32'hbc81abaa;
//Ai = {1'b1,A_i[MAN-1:0],2'b00};
//Bi = {1'b1,B_i[MAN-1:0],2'b00};
//Ci = {1'b1,C_i[MAN-1:0],2'b00};
//D_o = 26'hff;
#100
$display("[%t] : A_i: %h, B_i: %h C_i: %h\n", $realtime, {1'b1,A_i[MAN-1:0],2'b00}, {1'b1,B_i[MAN-1:0],2'b00}, {1'b1,C_i[MAN-1:0],2'b00});
$display("[%t] : A_o: %h, B_o: %h C_o: %h\n", $realtime, A_o, B_o, C_o);
$display("[%t] : A_sign:%h, B_sign:%h, C_sign:%h\n", $realtime, A_sign, B_sign, C_sign);
$display("[%t] : D_o:%h\n", $realtime, D_o);
$finish;
end
fp_align3#(
.EXPONENT(EXP),
.MANTISSA(MAN)
) align3(
.a1(A_i),
.a2(B_i),
.a3(C_i),
.a1_mantissa(A_o),
.a2_mantissa(B_o),
.a3_mantissa(C_o),
.a1_sign(A_sign),
.a2_sign(B_sign),
.a3_sign(C_sign)
);
fp_rshift#(
.EXPONENT(EXP),
.MANTISSA(MAN)
) rshift(
.val({1'b1,B_i[MAN-1:0]}),
.count(8'h3),
.val_o(D_o)
);
always #10 clk=~clk;
endmodule
| 6.608387 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] C_i;
reg [EXP+MAN:0] D_o;
reg A_sign;
reg B_sign;
reg C_sign;
initial begin
clk = 1'b1;
A_i = 32'h0;
B_i = 32'h0;
C_i = 32'h0;
#10
A_i = 32'h3e6c074f;
B_i = 32'h8f437ebe;
C_i = 32'h3e5c074f;
//D_o = 26'hff;
#100
$display("[%t] : A_i: %h, B_i: %h C_i: %h\n", $realtime, A_i, B_i, C_i);
$display("[%t] : A_sign:%h, B_sign:%h, C_sign:%h\n", $realtime, A_sign, B_sign, C_sign);
$display("[%t] : D_o:%h\n", $realtime, D_o);
$finish;
end
fp_lshift#(
.SHIFTWIDTH(EXP),
.DATAWIDTH(32)
) lshift(
.val(B_i),
.count(8'h3),
.val_o(D_o)
);
always #10 clk=~clk;
endmodule
| 6.608387 |
module
`timescale 1ns/1ps
module top;
reg clk;
reg [31:0] A;
reg [31:0] B;
reg [31:0] C;
localparam EXP = 8;
localparam MAN = 23;
initial begin
clk = 1'b1;
A = 32'h00000000;
B = 32'hbd7b54be;
#100
$display("[%t] : larger one of %h and %h is %h\n", $realtime, A, B, C);
$finish;
end
fp_max#(.EXPONENT(EXP),
.MANTISSA(MAN)
) max(
.a1(A),
.a2(B),
.max_o(C)
);
always #10 clk=~clk;
initial begin
if ($test$plusargs ("dump_all")) begin
`ifdef NCV // Cadence TRN dump
$recordsetup("design=top",
"compress",
"wrapsize=100M",
"version=1",
"run=1");
$recordvars();
`elsif VCS //Synopsys VPD dump
$vcdplusfile("top.vpd");
$vcdpluson;
//$vcdplusglitchon;
//$vcdplusflush;
`else
// Verilog VC dump
$dumpfile("top.vcd");
$dumpvars(0, top);
`endif
end
end
endmodule
| 7.853048 |
module
`timescale 1ns/1ps
module top;
reg clk;
reg [31:0] A;
reg [31:0] B;
reg [31:0] C;
localparam EXP = 8;
localparam MAN = 23;
initial begin
clk = 1'b1;
A = 32'h430260bb;
B = 32'hbd7b54be;
#100
$display("[%t] : %h mul %h is %h\n", $realtime, A, B, C);
$finish;
end
fp_mul2#(.EXPONENT(EXP),
.MANTISSA(MAN)
) mul2(
.A(A),
.B(B),
.C(C)
);
always #10 clk=~clk;
initial begin
if ($test$plusargs ("dump_all")) begin
`ifdef NCV // Cadence TRN dump
$recordsetup("design=board",
"compress",
"wrapsize=100M",
"version=1",
"run=1");
$recordvars();
`elsif VCS //Synopsys VPD dump
$vcdplusfile("board.vpd");
$vcdpluson;
//$vcdplusglitchon;
//$vcdplusflush;
`else
// Verilog VC dump
$dumpfile("board.vcd");
$dumpvars(0, board);
`endif
end
end
endmodule
| 7.853048 |
module
`timescale 1ns/1ps
module top;
reg clk;
reg [31:0] A;
reg [31:0] B;
reg [31:0] C;
localparam EXP = 8;
localparam MAN = 23;
reg [MAN:0] exp_sum; //[(MAN+3)*2-1:0]
initial begin
clk = 1'b1;
//A = 32'h3e6c074f;
//B = 32'h3f437ebe;
A = 32'h430260bb;
B = 32'hbd7b54be;
#100
$display("[%t] : %h mul %h is %h\n", $realtime, A, B, C);
$display("[%t] : exponent sum: %b\n", $realtime, exp_sum);
$finish;
end
fp_mul2#(.EXPONENT(EXP),
.MANTISSA(MAN)
) mul2(
.A(A),
.B(B),
._expOutput(exp_sum),
.C(C)
);
always #10 clk=~clk;
endmodule
| 7.853048 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 12;
reg clk;
reg sum_sign;
reg [MAN+4:0] sum_unsigned;
reg [EXP-1:0] sum_exp;
reg [EXP+MAN:0] sum_o;
localparam a_width = MAN+1+2; // width of sum after rounding (_sum)
// addr_width should be less than EXPONENT
localparam addr_width = log(a_width);
`include "misc.v"
`include "DW_lzd_function.inc"
reg [addr_width-1:0] num_zeros;
initial begin
sum_sign = 1'b0;
sum_unsigned = {MAN+5{1'b0}};
sum_exp = {EXP{1'b0}};
#10
sum_sign = 1'b0;
sum_unsigned = 17'b10; //28'b111 << 25;
sum_exp = 8'd12;
#100
$display("[%t] : sum_sign: %b, sum_unsigned: %h sum_exp: %h\n", $realtime, sum_sign, sum_unsigned, sum_exp);
$display("[%t] : sum_sign: %b, sum_unsigned: %b sum_exp: %b\n", $realtime, sum_sign, sum_unsigned, sum_exp);
$display("[%t] : sum_o:%h, sum_o exp: %h, sum_o unsigned: %h\n", $realtime, sum_o, sum_o[EXP+MAN-1:MAN], {1'b1,sum_o[MAN-1:0]});
$display("[%t] : sum_o:%b, sum_o exp: %b, sum_o unsigned: %b\n", $realtime, sum_o, sum_o[EXP+MAN-1:MAN], {1'b1,sum_o[MAN-1:0]});
$display("[%t] : num_zeros:%b\n", $realtime, num_zeros);
$finish;
end
fp_norm#(
.EXPONENT(EXP),
.MANTISSA(MAN)
) fpnorm(
.sum_sign(sum_sign),
.sum_unsigned(sum_unsigned),
.sum_exp(sum_exp),
.num_zeros(num_zeros),
.sum_o(sum_o)
);
//input wire sum_sign,
//input wire [MANTISSA+4 : 0] sum_unsigned,
//input wire [EXPONENT-1 : 0] sum_exp,
//output reg [MANTISSA+EXPONENT : 0] sum_o
always #10 clk=~clk;
initial begin
if ($test$plusargs ("dump_all")) begin
`ifdef NCV // Cadence TRN dump
$recordsetup("design=board",
"compress",
"wrapsize=100M",
"version=1",
"run=1");
$recordvars();
`elsif VCS //Synopsys VPD dump
$vcdplusfile("board.vpd");
$vcdpluson;
$vcdplusglitchon;
$vcdplusflush;
`else
// Verilog VC dump
$dumpfile("board.vcd");
$dumpvars(0, board);
`endif
end
end
endmodule
| 6.608387 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] C_i;
reg [MAN+2:0] A_o;
reg [MAN+2:0] B_o;
reg [MAN+2:0] C_o;
reg [MAN+2:0] D_o;
reg A_sign;
reg B_sign;
reg C_sign;
initial begin
clk = 1'b1;
A_i = 32'h0;
B_i = 32'h0;
C_i = 32'h0;
#10
A_i = 32'h3e6c074f;
B_i = 32'h8f437ebe;
C_i = 32'h3e5c074f;
//D_o = 26'hff;
#100
$display("[%t] : A_i: %h, B_i: %h C_i: %h\n", $realtime, A_i, B_i, C_i);
$display("[%t] : A_o: %h, B_o: %h C_o: %h\n", $realtime, A_o, B_o, C_o);
$display("[%t] : A_sign:%h, B_sign:%h, C_sign:%h\n", $realtime, A_sign, B_sign, C_sign);
$display("[%t] : D_o:%h\n", $realtime, D_o);
$finish;
end
fp_rshift#(
.EXPONENT(EXP),
.MANTISSA(MAN)
) rshift(
.val({1'b1,B_i[MAN-1:0]}),
.count(8'h3),
.val_o(D_o)
);
always #10 clk=~clk;
endmodule
| 6.608387 |
module
`timescale 1ns/1ps
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] A_i;
reg [EXP+MAN:0] B_i;
reg [EXP+MAN:0] C_i;
reg A_sign;
reg B_sign;
reg C_sign;
reg [MAN+4:0] D_o;
reg D_sign;
initial begin
clk = 1'b1;
A_i = 32'h0;
B_i = 32'h0;
C_i = 32'h0;
#10
A_i = 32'hcfa6a865; // -1.302014
B_i = 32'hbc81abaa; // -0.015829
C_i = 32'hcdc9bbee; // -0.098503
//D_o = 26'hff;
#100
$display("[%t] : A_i: %h, B_i: %h C_i: %h\n", $realtime, A_i, B_i, C_i);
$display("[%t] : A_sign:%b, B_sign:%b, C_sign:%b\n", $realtime, A_i[EXP+MAN], B_i[EXP+MAN], C_i[EXP+MAN]);
$display("[%t] : D_o:%h\n", $realtime, D_o);
$display("[%t] : D_sign:%b\n", $realtime, D_sign);
$finish;
end
fp_sum3#(
.EXPONENT(EXP),
.MANTISSA(MAN)
) sum3(
.a1_mantissa_unsigned({1'b1,A_i[MAN-1:0],2'b0}),
.a2_mantissa_unsigned({1'b1,B_i[MAN-1:0],2'b0}),
.a3_mantissa_unsigned({1'b1,C_i[MAN-1:0],2'b0}),
.a1_sign(A_i[EXP+MAN]),
.a2_sign(B_i[EXP+MAN]),
.a3_sign(C_i[EXP+MAN]),
.sum_unsigned(D_o),
.sum_sign(D_sign)
);
always #10 clk=~clk;
endmodule
| 6.608387 |
module Queue_3 (
input clk,
input reset,
output io_enq_ready,
input io_enq_valid,
input [127:0] io_enq_bits_data,
input io_enq_bits_last,
input [15:0] io_enq_bits_strb,
input io_enq_bits_user,
input io_deq_ready,
output io_deq_valid,
output [127:0] io_deq_bits_data,
output io_deq_bits_last,
output [15:0] io_deq_bits_strb,
output io_deq_bits_user,
output [2:0] io_count
);
wire [2:0] T0;
wire [1:0] ptr_diff;
reg [1:0] R1;
wire [1:0] T23;
wire [1:0] T2;
wire [1:0] T3;
wire do_deq;
reg [1:0] R4;
wire [1:0] T24;
wire [1:0] T5;
wire [1:0] T6;
wire do_enq;
wire T7;
wire ptr_match;
reg maybe_full;
wire T25;
wire T8;
wire T9;
wire T10;
wire [145:0] T11;
reg [145:0] ram[3:0];
wire [145:0] T12;
wire [145:0] T13;
wire [145:0] T14;
wire [16:0] T15;
wire [128:0] T16;
wire [15:0] T17;
wire T18;
wire [127:0] T19;
wire T20;
wire empty;
wire T21;
wire T22;
wire full;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
R1 = {1{$random}};
R4 = {1{$random}};
maybe_full = {1{$random}};
for (initvar = 0; initvar < 4; initvar = initvar + 1) ram[initvar] = {5{$random}};
end
// synthesis translate_on
`endif
assign io_count = T0;
assign T0 = {T7, ptr_diff};
assign ptr_diff = R4 - R1;
assign T23 = reset ? 2'h0 : T2;
assign T2 = do_deq ? T3 : R1;
assign T3 = R1 + 2'h1;
assign do_deq = io_deq_ready & io_deq_valid;
assign T24 = reset ? 2'h0 : T5;
assign T5 = do_enq ? T6 : R4;
assign T6 = R4 + 2'h1;
assign do_enq = io_enq_ready & io_enq_valid;
assign T7 = maybe_full & ptr_match;
assign ptr_match = R4 == R1;
assign T25 = reset ? 1'h0 : T8;
assign T8 = T9 ? do_enq : maybe_full;
assign T9 = do_enq != do_deq;
assign io_deq_bits_user = T10;
assign T10 = T11[1'h0:1'h0];
assign T11 = ram[R1];
assign T13 = T14;
assign T14 = {T16, T15};
assign T15 = {io_enq_bits_strb, io_enq_bits_user};
assign T16 = {io_enq_bits_data, io_enq_bits_last};
assign io_deq_bits_strb = T17;
assign T17 = T11[5'h10:1'h1];
assign io_deq_bits_last = T18;
assign T18 = T11[5'h11:5'h11];
assign io_deq_bits_data = T19;
assign T19 = T11[8'h91:5'h12];
assign io_deq_valid = T20;
assign T20 = empty ^ 1'h1;
assign empty = ptr_match & T21;
assign T21 = maybe_full ^ 1'h1;
assign io_enq_ready = T22;
assign T22 = full ^ 1'h1;
assign full = ptr_match & maybe_full;
always @(posedge clk) begin
if (reset) begin
R1 <= 2'h0;
end else if (do_deq) begin
R1 <= T3;
end
if (reset) begin
R4 <= 2'h0;
end else if (do_enq) begin
R4 <= T6;
end
if (reset) begin
maybe_full <= 1'h0;
end else if (T9) begin
maybe_full <= do_enq;
end
if (do_enq) ram[R4] <= T13;
end
endmodule
| 6.517764 |
module RRArbiter_0 (
input clk,
input reset,
output io_in_1_ready,
input io_in_1_valid,
input io_in_1_bits_rw,
input [11:0] io_in_1_bits_addr,
input [63:0] io_in_1_bits_data,
output io_in_0_ready,
input io_in_0_valid,
input io_in_0_bits_rw,
input [11:0] io_in_0_bits_addr,
input [63:0] io_in_0_bits_data,
input io_out_ready,
output io_out_valid,
output io_out_bits_rw,
output [11:0] io_out_bits_addr,
output [63:0] io_out_bits_data,
output io_chosen
);
wire chosen;
wire choose;
wire T0;
wire T1;
wire T2;
reg last_grant;
wire T27;
wire T3;
wire T4;
wire [63:0] T5;
wire T6;
wire [11:0] T7;
wire T8;
wire T9;
wire T10;
wire T11;
wire T12;
wire T13;
wire T14;
wire T15;
wire T16;
wire T17;
wire T18;
wire T19;
wire T20;
wire T21;
wire T22;
wire T23;
wire T24;
wire T25;
wire T26;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
last_grant = {1{$random}};
end
// synthesis translate_on
`endif
assign io_chosen = chosen;
assign chosen = choose;
assign choose = T1 ? 1'h1 : T0;
assign T0 = io_in_0_valid == 1'h0;
assign T1 = io_in_1_valid & T2;
assign T2 = last_grant < 1'h1;
assign T27 = reset ? 1'h0 : T3;
assign T3 = T4 ? chosen : last_grant;
assign T4 = io_out_ready & io_out_valid;
assign io_out_bits_data = T5;
assign T5 = T6 ? io_in_1_bits_data : io_in_0_bits_data;
assign T6 = chosen;
assign io_out_bits_addr = T7;
assign T7 = T6 ? io_in_1_bits_addr : io_in_0_bits_addr;
assign io_out_bits_rw = T8;
assign T8 = T6 ? io_in_1_bits_rw : io_in_0_bits_rw;
assign io_out_valid = T9;
assign T9 = T6 ? io_in_1_valid : io_in_0_valid;
assign io_in_0_ready = T10;
assign T10 = T11 & io_out_ready;
assign T11 = T18 | T12;
assign T12 = T13 ^ 1'h1;
assign T13 = T16 | T14;
assign T14 = io_in_1_valid & T15;
assign T15 = last_grant < 1'h1;
assign T16 = io_in_0_valid & T17;
assign T17 = last_grant < 1'h0;
assign T18 = last_grant < 1'h0;
assign io_in_1_ready = T19;
assign T19 = T20 & io_out_ready;
assign T20 = T24 | T21;
assign T21 = T22 ^ 1'h1;
assign T22 = T23 | io_in_0_valid;
assign T23 = T16 | T14;
assign T24 = T26 & T25;
assign T25 = last_grant < 1'h1;
assign T26 = T16 ^ 1'h1;
always @(posedge clk) begin
if (reset) begin
last_grant <= 1'h0;
end else if (T4) begin
last_grant <= chosen;
end
end
endmodule
| 6.876771 |
module FlowThroughSerializer (
output io_in_ready,
input io_in_valid,
input [1:0] io_in_bits_addr_beat,
input [1:0] io_in_bits_client_xact_id,
input [3:0] io_in_bits_manager_xact_id,
input io_in_bits_is_builtin_type,
input [3:0] io_in_bits_g_type,
input [127:0] io_in_bits_data,
input io_out_ready,
output io_out_valid,
output [1:0] io_out_bits_addr_beat,
output [1:0] io_out_bits_client_xact_id,
output [3:0] io_out_bits_manager_xact_id,
output io_out_bits_is_builtin_type,
output [3:0] io_out_bits_g_type,
output [127:0] io_out_bits_data,
output io_cnt,
output io_done
);
assign io_done = 1'h1;
assign io_cnt = 1'h0;
assign io_out_bits_data = io_in_bits_data;
assign io_out_bits_g_type = io_in_bits_g_type;
assign io_out_bits_is_builtin_type = io_in_bits_is_builtin_type;
assign io_out_bits_manager_xact_id = io_in_bits_manager_xact_id;
assign io_out_bits_client_xact_id = io_in_bits_client_xact_id;
assign io_out_bits_addr_beat = io_in_bits_addr_beat;
assign io_out_valid = io_in_valid;
assign io_in_ready = io_out_ready;
endmodule
| 6.711201 |
module RecFNToRecFN (
input [32:0] io_in,
input [ 1:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire [4:0] T0;
wire invalidExc;
wire T1;
wire T2;
wire [55:0] outRawFloat_sig;
wire [55:0] T3;
wire [26:0] T4;
wire [26:0] T5;
wire [24:0] T6;
wire [22:0] T7;
wire [1:0] T8;
wire T9;
wire T10;
wire [2:0] T11;
wire [8:0] T12;
wire outRawFloat_isNaN;
wire T13;
wire T14;
wire T15;
wire T16;
wire [1:0] T17;
wire [64:0] T18;
wire [63:0] T19;
wire [51:0] T20;
wire [51:0] T21;
wire [11:0] T22;
wire [11:0] T23;
wire [11:0] T24;
wire [11:0] T25;
wire outRawFloat_isInf;
wire T26;
wire T27;
wire T28;
wire T29;
wire [11:0] T30;
wire [11:0] T31;
wire [11:0] T32;
wire T33;
wire outRawFloat_isZero;
wire T34;
wire [11:0] T35;
wire [11:0] T36;
wire [11:0] T37;
wire [11:0] T38;
wire [12:0] outRawFloat_sExp;
wire [13:0] T39;
wire [12:0] T47;
wire [9:0] T40;
wire [9:0] T41;
wire [9:0] T42;
wire [2:0] T48;
wire T49;
wire T43;
wire T44;
wire outRawFloat_sign;
wire T45;
wire T46;
assign io_exceptionFlags = T0;
assign T0 = {invalidExc, 4'h0};
assign invalidExc = outRawFloat_isNaN & T1;
assign T1 = T2 ^ 1'h1;
assign T2 = outRawFloat_sig[6'h35:6'h35];
assign outRawFloat_sig = T3;
assign T3 = T4 << 5'h1d;
assign T4 = T5;
assign T5 = {T8, T6};
assign T6 = {T7, 2'h0};
assign T7 = io_in[5'h16:1'h0];
assign T8 = {1'h0, T9};
assign T9 = T10 ^ 1'h1;
assign T10 = T11 == 3'h0;
assign T11 = T12[4'h8:3'h6];
assign T12 = io_in[5'h1f:5'h17];
assign outRawFloat_isNaN = T13;
assign T13 = T14;
assign T14 = T16 & T15;
assign T15 = T12[3'h6:3'h6];
assign T16 = T17 == 2'h3;
assign T17 = T12[4'h8:3'h7];
assign io_out = T18;
assign T18 = {T43, T19};
assign T19 = {T22, T20};
assign T20 = outRawFloat_isNaN ? 52'h8000000000000 : T21;
assign T21 = outRawFloat_sig[6'h35:2'h2];
assign T22 = T24 | T23;
assign T23 = outRawFloat_isNaN ? 12'he00 : 12'h0;
assign T24 = T30 | T25;
assign T25 = outRawFloat_isInf ? 12'hc00 : 12'h0;
assign outRawFloat_isInf = T26;
assign T26 = T27;
assign T27 = T16 & T28;
assign T28 = T29 ^ 1'h1;
assign T29 = T12[3'h6:3'h6];
assign T30 = T35 & T31;
assign T31 = ~T32;
assign T32 = T33 ? 12'h200 : 12'h0;
assign T33 = outRawFloat_isZero | outRawFloat_isInf;
assign outRawFloat_isZero = T34;
assign T34 = T10;
assign T35 = T38 & T36;
assign T36 = ~T37;
assign T37 = outRawFloat_isZero ? 12'hc00 : 12'h0;
assign T38 = outRawFloat_sExp[4'hb:1'h0];
assign outRawFloat_sExp = T39;
assign T39 = T47 + 13'h700;
assign T47 = {T48, T40};
assign T40 = T41;
assign T41 = T42;
assign T42 = {1'h0, T12};
assign T48 = T49 ? 3'h7 : 3'h0;
assign T49 = T40[4'h9:4'h9];
assign T43 = outRawFloat_sign & T44;
assign T44 = outRawFloat_isNaN ^ 1'h1;
assign outRawFloat_sign = T45;
assign T45 = T46;
assign T46 = io_in[6'h20:6'h20];
endmodule
| 6.761906 |
module DivSqrtRecF64 (
input clk,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [1:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
wire T0;
wire ds_io_inReady_div;
wire ds_io_inReady_sqrt;
wire ds_io_outValid_div;
wire ds_io_outValid_sqrt;
wire [64:0] ds_io_out;
wire [4:0] ds_io_exceptionFlags;
wire [3:0] ds_io_usingMulAdd;
wire ds_io_latchMulAddA_0;
wire [53:0] ds_io_mulAddA_0;
wire ds_io_latchMulAddB_0;
wire [53:0] ds_io_mulAddB_0;
wire [104:0] ds_io_mulAddC_2;
wire [104:0] mul_io_result_s3;
assign T0 = ds_io_usingMulAdd[1'h0:1'h0];
assign io_exceptionFlags = ds_io_exceptionFlags;
assign io_out = ds_io_out;
assign io_outValid_sqrt = ds_io_outValid_sqrt;
assign io_outValid_div = ds_io_outValid_div;
assign io_inReady_sqrt = ds_io_inReady_sqrt;
assign io_inReady_div = ds_io_inReady_div;
DivSqrtRecF64_mulAddZ31 ds (
.clk(clk),
.reset(reset),
.io_inReady_div(ds_io_inReady_div),
.io_inReady_sqrt(ds_io_inReady_sqrt),
.io_inValid(io_inValid),
.io_sqrtOp(io_sqrtOp),
.io_a(io_a),
.io_b(io_b),
.io_roundingMode(io_roundingMode),
.io_outValid_div(ds_io_outValid_div),
.io_outValid_sqrt(ds_io_outValid_sqrt),
.io_out(ds_io_out),
.io_exceptionFlags(ds_io_exceptionFlags),
.io_usingMulAdd(ds_io_usingMulAdd),
.io_latchMulAddA_0(ds_io_latchMulAddA_0),
.io_mulAddA_0(ds_io_mulAddA_0),
.io_latchMulAddB_0(ds_io_latchMulAddB_0),
.io_mulAddB_0(ds_io_mulAddB_0),
.io_mulAddC_2(ds_io_mulAddC_2),
.io_mulAddResult_3(mul_io_result_s3)
);
Mul54 mul (
.clk(clk),
.io_val_s0(T0),
.io_latch_a_s0(ds_io_latchMulAddA_0),
.io_a_s0(ds_io_mulAddA_0),
.io_latch_b_s0(ds_io_latchMulAddB_0),
.io_b_s0(ds_io_mulAddB_0),
.io_c_s2(ds_io_mulAddC_2),
.io_result_s3(mul_io_result_s3)
);
endmodule
| 6.793472 |
module DataArray_T9 (
input CLK,
input RST,
input init,
input [7:0] W0A,
input W0E,
input [127:0] W0I,
input [127:0] W0M,
input [7:0] R1A,
input R1E,
output [127:0] R1O
);
`ifndef SYNTHESIS
integer i;
integer j;
always @(posedge CLK) begin
for (i = 0; i < 2; i = i + 64) begin
for (j = 1; j < 64; j = j + 1) begin
if (W0M[i] != W0M[i+j]) begin
$fwrite(32'h80000002, "ASSERTION FAILED: write mask granularity\n");
$finish;
end
end
end
end
`endif
reg [127:0] ram[255:0];
`ifndef SYNTHESIS
integer initvar;
initial begin
#0.002;
for (initvar = 0; initvar < 256; initvar = initvar + 1) ram[initvar] = {4{$random}};
end
`endif
reg [7:0] reg_R1A;
always @(posedge CLK) begin
if (R1E) reg_R1A <= R1A;
if (W0E && W0M[0]) ram[W0A][63:0] <= W0I[63:0];
if (W0E && W0M[64]) ram[W0A][127:64] <= W0I[127:64];
end
assign R1O = ram[reg_R1A];
endmodule
| 6.622475 |
module MetadataArray_tag_arr (
input CLK,
input RST,
input init,
input [5:0] W0A,
input W0E,
input [87:0] W0I,
input [87:0] W0M,
input [5:0] R1A,
input R1E,
output [87:0] R1O
);
`ifndef SYNTHESIS
integer i;
integer j;
always @(posedge CLK) begin
for (i = 0; i < 4; i = i + 22) begin
for (j = 1; j < 22; j = j + 1) begin
if (W0M[i] != W0M[i+j]) begin
$fwrite(32'h80000002, "ASSERTION FAILED: write mask granularity\n");
$finish;
end
end
end
end
`endif
reg [87:0] ram[63:0];
`ifndef SYNTHESIS
integer initvar;
initial begin
#0.002;
for (initvar = 0; initvar < 64; initvar = initvar + 1) ram[initvar] = {3{$random}};
end
`endif
reg [5:0] reg_R1A;
always @(posedge CLK) begin
if (R1E) reg_R1A <= R1A;
if (W0E && W0M[0]) ram[W0A][21:0] <= W0I[21:0];
if (W0E && W0M[22]) ram[W0A][43:22] <= W0I[43:22];
if (W0E && W0M[44]) ram[W0A][65:44] <= W0I[65:44];
if (W0E && W0M[66]) ram[W0A][87:66] <= W0I[87:66];
end
assign R1O = ram[reg_R1A];
endmodule
| 6.901681 |
module HellaQueue_0 (
input clk,
input reset,
output io_enq_ready,
input io_enq_valid,
input [127:0] io_enq_bits_data,
input io_deq_ready,
output io_deq_valid,
output [127:0] io_deq_bits_data
//output[4:0] io_count
);
wire fq_io_enq_ready;
wire fq_io_deq_valid;
wire [127:0] fq_io_deq_bits_data;
wire Queue_io_enq_ready;
wire Queue_io_deq_valid;
wire [127:0] Queue_io_deq_bits_data;
`ifndef SYNTHESIS
// synthesis translate_off
// assign io_count = {1{$random}};
// synthesis translate_on
`endif
assign io_deq_bits_data = Queue_io_deq_bits_data;
assign io_deq_valid = Queue_io_deq_valid;
assign io_enq_ready = fq_io_enq_ready;
HellaFlowQueue_0 fq (
.clk(clk),
.reset(reset),
.io_enq_ready(fq_io_enq_ready),
.io_enq_valid(io_enq_valid),
.io_enq_bits_data(io_enq_bits_data),
.io_deq_ready(Queue_io_enq_ready),
.io_deq_valid(fq_io_deq_valid),
.io_deq_bits_data(fq_io_deq_bits_data)
//.io_count( )
);
Queue_15 Queue (
.clk(clk),
.reset(reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(fq_io_deq_valid),
.io_enq_bits_data(fq_io_deq_bits_data),
.io_deq_ready(io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_data(Queue_io_deq_bits_data)
//.io_count( )
);
endmodule
| 6.761208 |
module FlowThroughSerializer (
output io_in_ready,
input io_in_valid,
input [1:0] io_in_bits_addr_beat,
input [127:0] io_in_bits_data,
input [6:0] io_in_bits_client_xact_id,
input [2:0] io_in_bits_manager_xact_id,
input io_in_bits_is_builtin_type,
input [3:0] io_in_bits_g_type,
input io_out_ready,
output io_out_valid,
output [1:0] io_out_bits_addr_beat,
output [127:0] io_out_bits_data,
output [6:0] io_out_bits_client_xact_id,
output [2:0] io_out_bits_manager_xact_id,
output io_out_bits_is_builtin_type,
output [3:0] io_out_bits_g_type,
output io_cnt,
output io_done
);
assign io_done = 1'h1;
assign io_cnt = 1'h0;
assign io_out_bits_g_type = io_in_bits_g_type;
assign io_out_bits_is_builtin_type = io_in_bits_is_builtin_type;
assign io_out_bits_manager_xact_id = io_in_bits_manager_xact_id;
assign io_out_bits_client_xact_id = io_in_bits_client_xact_id;
assign io_out_bits_data = io_in_bits_data;
assign io_out_bits_addr_beat = io_in_bits_addr_beat;
assign io_out_valid = io_in_valid;
assign io_in_ready = io_out_ready;
endmodule
| 6.711201 |
module LockingArbiter_0 (
input clk,
input reset,
output io_in_1_ready,
input io_in_1_valid,
input [25:0] io_in_1_bits_addr_block,
input [6:0] io_in_1_bits_client_xact_id,
input [1:0] io_in_1_bits_addr_beat,
input [127:0] io_in_1_bits_data,
input [2:0] io_in_1_bits_r_type,
input io_in_1_bits_voluntary,
output io_in_0_ready,
input io_in_0_valid,
input [25:0] io_in_0_bits_addr_block,
input [6:0] io_in_0_bits_client_xact_id,
input [1:0] io_in_0_bits_addr_beat,
input [127:0] io_in_0_bits_data,
input [2:0] io_in_0_bits_r_type,
input io_in_0_bits_voluntary,
input io_out_ready,
output io_out_valid,
output [25:0] io_out_bits_addr_block,
output [6:0] io_out_bits_client_xact_id,
output [1:0] io_out_bits_addr_beat,
output [127:0] io_out_bits_data,
output [2:0] io_out_bits_r_type,
output io_out_bits_voluntary,
output io_chosen
);
wire chosen;
wire T0;
wire choose;
reg lockIdx;
wire T35;
wire T1;
wire T2;
wire T3;
wire T4;
wire T5;
wire T6;
wire T7;
wire T8;
wire T9;
wire T10;
wire T11;
wire T12;
reg locked;
wire T36;
wire T13;
wire T14;
wire T15;
wire T16;
wire [1:0] T17;
reg [1:0] R18;
wire [1:0] T37;
wire [1:0] T19;
wire T20;
wire T21;
wire [2:0] T22;
wire [127:0] T23;
wire [1:0] T24;
wire [6:0] T25;
wire [25:0] T26;
wire T27;
wire T28;
wire T29;
wire T30;
wire T31;
wire T32;
wire T33;
wire T34;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
lockIdx = {1{$random}};
locked = {1{$random}};
R18 = {1{$random}};
end
// synthesis translate_on
`endif
assign io_chosen = chosen;
assign chosen = T0;
assign T0 = locked ? lockIdx : choose;
assign choose = io_in_0_valid == 1'h0;
assign T35 = reset ? 1'h1 : T1;
assign T1 = T4 ? T2 : lockIdx;
assign T2 = T3 == 1'h0;
assign T3 = io_in_0_ready & io_in_0_valid;
assign T4 = T6 & T5;
assign T5 = locked ^ 1'h1;
assign T6 = T12 & T7;
assign T7 = T9 | T8;
assign T8 = 3'h2 == io_out_bits_r_type;
assign T9 = T11 | T10;
assign T10 = 3'h1 == io_out_bits_r_type;
assign T11 = 3'h0 == io_out_bits_r_type;
assign T12 = io_out_ready & io_out_valid;
assign T36 = reset ? 1'h0 : T13;
assign T13 = T15 ? 1'h0 : T14;
assign T14 = T4 ? 1'h1 : locked;
assign T15 = T12 & T16;
assign T16 = T17 == 2'h0;
assign T17 = R18 + 2'h1;
assign T37 = reset ? 2'h0 : T19;
assign T19 = T6 ? T17 : R18;
assign io_out_bits_voluntary = T20;
assign T20 = T21 ? io_in_1_bits_voluntary : io_in_0_bits_voluntary;
assign T21 = chosen;
assign io_out_bits_r_type = T22;
assign T22 = T21 ? io_in_1_bits_r_type : io_in_0_bits_r_type;
assign io_out_bits_data = T23;
assign T23 = T21 ? io_in_1_bits_data : io_in_0_bits_data;
assign io_out_bits_addr_beat = T24;
assign T24 = T21 ? io_in_1_bits_addr_beat : io_in_0_bits_addr_beat;
assign io_out_bits_client_xact_id = T25;
assign T25 = T21 ? io_in_1_bits_client_xact_id : io_in_0_bits_client_xact_id;
assign io_out_bits_addr_block = T26;
assign T26 = T21 ? io_in_1_bits_addr_block : io_in_0_bits_addr_block;
assign io_out_valid = T27;
assign T27 = T21 ? io_in_1_valid : io_in_0_valid;
assign io_in_0_ready = T28;
assign T28 = T29 & io_out_ready;
assign T29 = locked ? T30 : 1'h1;
assign T30 = lockIdx == 1'h0;
assign io_in_1_ready = T31;
assign T31 = T32 & io_out_ready;
assign T32 = locked ? T34 : T33;
assign T33 = io_in_0_valid ^ 1'h1;
assign T34 = lockIdx == 1'h1;
always @(posedge clk) begin
if (reset) begin
lockIdx <= 1'h1;
end else if (T4) begin
lockIdx <= T2;
end
if (reset) begin
locked <= 1'h0;
end else if (T15) begin
locked <= 1'h0;
end else if (T4) begin
locked <= 1'h1;
end
if (reset) begin
R18 <= 2'h0;
end else if (T6) begin
R18 <= T17;
end
end
endmodule
| 8.44302 |
module divSqrtRecodedFloat64 (
input clk,
input reset,
output io_inReady_div,
output io_inReady_sqrt,
input io_inValid,
input io_sqrtOp,
input [64:0] io_a,
input [64:0] io_b,
input [1:0] io_roundingMode,
output io_outValid_div,
output io_outValid_sqrt,
output [64:0] io_out,
output [4:0] io_exceptionFlags
);
wire T0;
wire ds_io_inReady_div;
wire ds_io_inReady_sqrt;
wire ds_io_outValid_div;
wire ds_io_outValid_sqrt;
wire [64:0] ds_io_out;
wire [4:0] ds_io_exceptionFlags;
wire [3:0] ds_io_usingMulAdd;
wire ds_io_latchMulAddA_0;
wire [53:0] ds_io_mulAddA_0;
wire ds_io_latchMulAddB_0;
wire [53:0] ds_io_mulAddB_0;
wire [104:0] ds_io_mulAddC_2;
wire [104:0] mul_io_result_s3;
assign T0 = ds_io_usingMulAdd[1'h0:1'h0];
assign io_exceptionFlags = ds_io_exceptionFlags;
assign io_out = ds_io_out;
assign io_outValid_sqrt = ds_io_outValid_sqrt;
assign io_outValid_div = ds_io_outValid_div;
assign io_inReady_sqrt = ds_io_inReady_sqrt;
assign io_inReady_div = ds_io_inReady_div;
divSqrtRecodedFloat64_mulAddZ31 ds (
.clk(clk),
.reset(reset),
.io_inReady_div(ds_io_inReady_div),
.io_inReady_sqrt(ds_io_inReady_sqrt),
.io_inValid(io_inValid),
.io_sqrtOp(io_sqrtOp),
.io_a(io_a),
.io_b(io_b),
.io_roundingMode(io_roundingMode),
.io_outValid_div(ds_io_outValid_div),
.io_outValid_sqrt(ds_io_outValid_sqrt),
.io_out(ds_io_out),
.io_exceptionFlags(ds_io_exceptionFlags),
.io_usingMulAdd(ds_io_usingMulAdd),
.io_latchMulAddA_0(ds_io_latchMulAddA_0),
.io_mulAddA_0(ds_io_mulAddA_0),
.io_latchMulAddB_0(ds_io_latchMulAddB_0),
.io_mulAddB_0(ds_io_mulAddB_0),
.io_mulAddC_2(ds_io_mulAddC_2),
.io_mulAddResult_3(mul_io_result_s3)
);
mul54 mul (
.clk(clk),
.io_val_s0(T0),
.io_latch_a_s0(ds_io_latchMulAddA_0),
.io_a_s0(ds_io_mulAddA_0),
.io_latch_b_s0(ds_io_latchMulAddB_0),
.io_b_s0(ds_io_mulAddB_0),
.io_c_s2(ds_io_mulAddC_2),
.io_result_s3(mul_io_result_s3)
);
endmodule
| 6.548765 |
module MetadataArray_T1 (
input CLK,
input RST,
input init,
input [5:0] W0A,
input W0E,
input [87:0] W0I,
input [87:0] W0M,
input [5:0] R1A,
input R1E,
output [87:0] R1O
);
`ifndef SYNTHESIS
integer i;
integer j;
always @(posedge CLK) begin
for (i = 0; i < 4; i = i + 22) begin
for (j = 1; j < 22; j = j + 1) begin
if (W0M[i] != W0M[i+j]) begin
$fwrite(32'h80000002, "ASSERTION FAILED: write mask granularity\n");
$finish;
end
end
end
end
`endif
reg [87:0] ram[63:0];
`ifndef SYNTHESIS
integer initvar;
initial begin
#0.002;
for (initvar = 0; initvar < 64; initvar = initvar + 1) ram[initvar] = {3{$random}};
end
`endif
reg [5:0] reg_R1A;
always @(posedge CLK) begin
if (R1E) reg_R1A <= R1A;
if (W0E && W0M[0]) ram[W0A][21:0] <= W0I[21:0];
if (W0E && W0M[22]) ram[W0A][43:22] <= W0I[43:22];
if (W0E && W0M[44]) ram[W0A][65:44] <= W0I[65:44];
if (W0E && W0M[66]) ram[W0A][87:66] <= W0I[87:66];
end
assign R1O = ram[reg_R1A];
endmodule
| 6.901681 |
module HackBox (
input [63:0] io_in_0,
input [63:0] io_in_1,
input [63:0] io_in_2,
output [63:0] io_out
);
assign out = in_0 + (in_1 * in_2);
endmodule
| 6.993909 |
module proc_control (
input wire clk,
input wire rst_n,
output reg on_3mul,
output reg on_align3,
output reg on_sum3,
output reg on_bias
);
localparam ON_MUL = 3'h1;
localparam ON_ALIGN = 3'h2;
localparam ON_SUM = 3'h3;
localparam ON_BIAS = 3'h4;
reg [2:0] _state;
reg [2:0] _next_state;
always @(posedge clk) begin
_state <= _next_state;
end
always @(_state or rst_n) begin
if (rst_n) begin
_next_state = ON_MUL;
case (_state)
ON_MUL: _next_state = ON_ALIGN;
ON_ALIGN: _next_state = ON_SUM;
ON_SUM: _next_state = ON_BIAS;
ON_BIAS: _next_state = ON_MUL;
endcase
end else begin
_next_state = ON_MUL;
end
end
always @(_state or rst_n) begin
on_3mul = 1'b0;
on_align3 = 1'b0;
on_sum3 = 1'b0;
on_bias = 1'b0;
if (rst_n) begin
case (_state)
ON_MUL: on_3mul = 1'b1;
ON_ALIGN: on_align3 = 1'b1;
ON_SUM: on_sum3 = 1'b1;
ON_BIAS: on_bias = 1'b1;
endcase
end
end
endmodule
| 8.057958 |
module
`timescale 1ns/1ps
`define NULL 0
module top;
localparam EXP = 8;
localparam MAN = 23;
reg clk;
reg [EXP+MAN:0] ker1;
reg [EXP+MAN:0] ker2;
reg [EXP+MAN:0] ker3;
reg [EXP+MAN:0] data1;
reg [EXP+MAN:0] data2;
reg [EXP+MAN:0] data3;
reg [EXP+MAN:0] bias;
reg [EXP+MAN:0] result;
reg rst_n; // start processing
reg done;
wire on_3mul;
wire on_align3;
wire on_sum3;
wire on_bias;
initial begin
clk = 1'b1;
data1 = 32'h0;
data2 = 32'h0;
data3 = 32'h0;
ker1 = 32'h0;
ker2 = 32'h0;
ker3 = 32'h0;
bias = 32'h0;
#10
data1 = 32'hc42d7f86; //32'h42f9a7ad;
data2 = 32'hc42670c5; //32'h42fb7b8d;
data3 = 32'hc399b024; //32'h430260bb;
ker1 = 32'h3edbe391;
ker2 = 32'h3ebf3711;
ker3 = 32'hbd7b54be;
bias = 32'h3f3bfafa;
//bias = 32'h42ba9bc8;
#100
$display("[%t] : data1: %h, data2: %h data3: %h\n", $realtime, data1, data2, data3);
$display("[%t] : ker1:%h, ker2:%h, ker3:%h\n", $realtime, ker1, ker2, ker3);
$display("[%t] : bias:%h\n", $realtime, bias);
$display("[%t] : result:%h\n", $realtime, result);
$finish;
end
always #10 clk=~clk;
pe_array1x3#(
.EXPONENT(EXP),
.MANTISSA(MAN)
) pe(
.pe_ker3_i({ker1,ker2,ker3}),
.pe_bias_i(bias),
.pe_data3_i({data1,data2,data3}),
.clk(clk),
.pe_on_3mul_pe_en(1'b1),//on_3mul),
.pe_on_align3(1'b1),//on_align3),
.pe_on_sum3(1'b1),//on_sum3),
.pe_on_bias(1'b1),//on_bias),
.pe_data_o(result)
);
proc_control ctrl(
.clk(clk),
.rst_n(rst_n),
.on_3mul(on_3mul),
.on_align3(on_align3),
.on_sum3(on_sum3),
.on_bias(on_bias)
);
initial begin
if ($test$plusargs ("dump_all")) begin
`ifdef NCV // Cadence TRN dump
$recordsetup("design=board",
"compress",
"wrapsize=100M",
"version=1",
"run=1");
$recordvars();
`elsif VCS //Synopsys VPD dump
$vcdplusfile("board.vpd");
$vcdpluson;
$vcdplusglitchon;
$vcdplusflush;
`else
// Verilog VC dump
$dumpfile("board.vcd");
$dumpvars(0, board);
`endif
end
end
endmodule
| 6.608387 |
module proc_control (
input wire clk,
input wire rst_n,
output reg on_3mul,
output reg on_align3,
output reg on_sum3,
output reg on_bias
);
localparam ON_MUL = 3'h1;
localparam ON_ALIGN = 3'h2;
localparam ON_SUM = 3'h3;
localparam ON_BIAS = 3'h4;
reg [2:0] _state;
reg [2:0] _next_state;
always @(posedge clk) begin
_state <= _next_state;
end
always @(_state or rst_n) begin
if (rst_n) begin
_next_state = ON_MUL;
case (_state)
ON_MUL: _next_state = ON_ALIGN;
ON_ALIGN: _next_state = ON_SUM;
ON_SUM: _next_state = ON_BIAS;
ON_BIAS: _next_state = ON_MUL;
endcase
end else begin
_next_state = ON_MUL;
end
end
always @(_state or rst_n) begin
on_3mul = 1'b0;
on_align3 = 1'b0;
on_sum3 = 1'b0;
on_bias = 1'b0;
if (rst_n) begin
case (_state)
ON_MUL: on_3mul = 1'b1;
ON_ALIGN: on_align3 = 1'b1;
ON_SUM: on_sum3 = 1'b1;
ON_BIAS: on_bias = 1'b1;
endcase
end
end
endmodule
| 8.057958 |
module prga_simple_buf (
input wire [0:0] C,
input wire [0:0] D,
output reg [0:0] Q
);
always @(posedge C) begin
Q <= D;
end
endmodule
| 7.13912 |
module prga_simple_bufr (
input wire [0:0] C,
input wire [0:0] R,
input wire [0:0] D,
output reg [0:0] Q
);
always @(posedge C) begin
if (R) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 7.13912 |
module iob (
input wire [0:0] outpad
, output wire [0:0] inpad
, input wire [0:0] ipin
, output wire [0:0] opin
, output wire [0:0] oe
, input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [0:0] prog_din
, output wire [0:0] prog_dout
, output wire [0:0] prog_we_o
);
wire [0:0] _io__inpad;
wire [0:0] _io__opin;
wire [0:0] _io__oe;
wire [0:0] _i_buf_prog_rst_l0__Q;
wire [0:0] _i_buf_prog_done_l0__Q;
wire [0:0] _i_scanchain_head__prog_dout;
wire [0:0] _i_scanchain_head__prog_we_o;
wire [0:0] _i_prog_data_io__prog_dout;
wire [1:0] _i_prog_data_io__prog_data;
wire [0:0] _i_scanchain_tail__prog_dout;
wire [0:0] _i_scanchain_tail__prog_we_o;
iopad io (
.outpad(outpad)
, .inpad(_io__inpad)
, .ipin(ipin)
, .opin(_io__opin)
, .oe(_io__oe)
, .prog_done(_i_buf_prog_done_l0__Q)
, .prog_data(_i_prog_data_io__prog_data)
);
prga_simple_buf i_buf_prog_rst_l0 (
.C(prog_clk)
, .D(prog_rst)
, .Q(_i_buf_prog_rst_l0__Q)
);
prga_simple_bufr i_buf_prog_done_l0 (
.C(prog_clk)
, .R(_i_buf_prog_rst_l0__Q)
, .D(prog_done)
, .Q(_i_buf_prog_done_l0__Q)
);
scanchain_delim i_scanchain_head (
.prog_clk (prog_clk)
, .prog_rst (_i_buf_prog_rst_l0__Q)
, .prog_done(_i_buf_prog_done_l0__Q)
, .prog_we (prog_we)
, .prog_din (prog_din)
, .prog_dout(_i_scanchain_head__prog_dout)
, .prog_we_o(_i_scanchain_head__prog_we_o)
);
scanchain_data_d2 i_prog_data_io (
.prog_clk (prog_clk)
, .prog_rst (_i_buf_prog_rst_l0__Q)
, .prog_done(_i_buf_prog_done_l0__Q)
, .prog_we (_i_scanchain_head__prog_we_o)
, .prog_din (_i_scanchain_head__prog_dout)
, .prog_dout(_i_prog_data_io__prog_dout)
, .prog_data(_i_prog_data_io__prog_data)
);
scanchain_delim i_scanchain_tail (
.prog_clk (prog_clk)
, .prog_rst (_i_buf_prog_rst_l0__Q)
, .prog_done(_i_buf_prog_done_l0__Q)
, .prog_we (_i_scanchain_head__prog_we_o)
, .prog_din (_i_prog_data_io__prog_dout)
, .prog_dout(_i_scanchain_tail__prog_dout)
, .prog_we_o(_i_scanchain_tail__prog_we_o)
);
assign inpad = _io__inpad;
assign opin = _io__opin;
assign oe = _io__oe;
assign prog_dout = _i_scanchain_tail__prog_dout;
assign prog_we_o = _i_scanchain_tail__prog_we_o;
endmodule
| 6.616918 |
module scanchain_delim (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [0:0] prog_we_o
, output reg [1 - 1:0] prog_dout
);
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_we_o <= 1'b0;
prog_dout <= 1'b0;
end else if (~prog_done && prog_we) begin
prog_we_o <= 1'b1;
prog_dout <= prog_din;
end else begin
prog_we_o <= 1'b0;
end
end
endmodule
| 7.198827 |
module scanchain_data_d2 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [2 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 2;
localparam CHAIN_WIDTH = 1;
wire [CHAIN_BITCOUNT + CHAIN_WIDTH - 1:0] prog_data_next;
assign prog_data_next = {prog_data, prog_din};
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_data <= {CHAIN_BITCOUNT{1'b0}};
end else if (~prog_done && prog_we) begin
prog_data <= prog_data_next[0+:CHAIN_BITCOUNT];
end
end
assign prog_dout = prog_data_next[CHAIN_BITCOUNT+:CHAIN_WIDTH];
endmodule
| 7.770095 |
module scanchain_data_d1 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [1 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 1;
localparam CHAIN_WIDTH = 1;
wire [CHAIN_BITCOUNT + CHAIN_WIDTH - 1:0] prog_data_next;
assign prog_data_next = {prog_data, prog_din};
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_data <= {CHAIN_BITCOUNT{1'b0}};
end else if (~prog_done && prog_we) begin
prog_data <= prog_data_next[0+:CHAIN_BITCOUNT];
end
end
assign prog_dout = prog_data_next[CHAIN_BITCOUNT+:CHAIN_WIDTH];
endmodule
| 7.770095 |
module sw4 (
input wire [3:0] i
, output reg [0:0] o
, input wire [0:0] prog_done
, input wire [2:0] prog_data
);
always @* begin
if (~prog_done) begin
o = 1'b0;
end else begin
o = 1'b0; // if ``prog_data == 0`` or ``prog_data`` out of bound, output 0
case (prog_data)
3'd1: o = i[0];
3'd2: o = i[1];
3'd3: o = i[2];
3'd4: o = i[3];
endcase
end
end
endmodule
| 6.587067 |
module scanchain_data_d3 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [3 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 3;
localparam CHAIN_WIDTH = 1;
wire [CHAIN_BITCOUNT + CHAIN_WIDTH - 1:0] prog_data_next;
assign prog_data_next = {prog_data, prog_din};
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_data <= {CHAIN_BITCOUNT{1'b0}};
end else if (~prog_done && prog_we) begin
prog_data <= prog_data_next[0+:CHAIN_BITCOUNT];
end
end
assign prog_dout = prog_data_next[CHAIN_BITCOUNT+:CHAIN_WIDTH];
endmodule
| 7.770095 |
module iopad (
input wire [0:0] outpad
, output reg [0:0] inpad
, input wire [0:0] ipin
, output reg [0:0] opin
, output reg [0:0] oe
, input wire [0:0] prog_done // programming
, input wire [1:0] prog_data // mode:
// - 00: disabled
// - 01: input mode
// - 10: output mode
);
localparam MODE_INPUT = 2'h1, MODE_OUTPUT = 2'h2;
always @* begin
inpad = 1'b0;
opin = 1'b0;
oe = 1'b0;
if (prog_done) begin
case (prog_data)
MODE_INPUT: begin
inpad = ipin;
end
MODE_OUTPUT: begin
opin = outpad;
oe = 1'b1;
end
endcase
end
end
endmodule
| 7.272753 |
module scanchain_data_d4 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [4 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 4;
localparam CHAIN_WIDTH = 1;
wire [CHAIN_BITCOUNT + CHAIN_WIDTH - 1:0] prog_data_next;
assign prog_data_next = {prog_data, prog_din};
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_data <= {CHAIN_BITCOUNT{1'b0}};
end else if (~prog_done && prog_we) begin
prog_data <= prog_data_next[0+:CHAIN_BITCOUNT];
end
end
assign prog_dout = prog_data_next[CHAIN_BITCOUNT+:CHAIN_WIDTH];
endmodule
| 7.770095 |
modules/top.v"
`timescale 1us/1ns
module top_tb ();
// 10 MHz clock
reg clk = 1;
always #0.05 clk = ~clk;
reg rst;
wire [1:0] r,g,b;
top_m top (
.clk(clk),
.rst(rst),
.r(r), .g(g), .b(b)
);
initial begin
$dumpfile( "dump.vcd" );
$dumpvars( 0, top );
//\\ =========================== \\//
rst = 1;
#1
rst = 0;
#16582
//\\ =========================== \\//
$finish;
end
endmodule
| 7.284158 |
module Top #(
parameter INSTRUCTION_FILE_NAME = "default_instr_file"
) (
clk,
rst
);
`include "Parameters.vh"
input clk;
input rst;
/* Signal wires between different modules */
// Between datapath and instruction memory
wire [XLEN - 1 : 0] PC;
wire [XLEN - 1 : 0] instruction;
// Between instruction decoder to datapath and control unit
wire [6 : 0] opcode;
wire [2 : 0] funct3;
wire funct7;
wire [4 : 0] srcRegister1;
wire [4 : 0] srcRegister2;
wire [4 : 0] desRegister;
wire [24 : 0] imm;
// Between control unit and datapath
wire PCSrc;
wire resultSrc;
wire memWrite;
wire [2 : 0] ALUControl;
wire ALUSrc;
wire [1 : 0] immSrc;
wire regWrite;
wire zero;
// Between datapath and data memory
wire [XLEN - 1 : 0] ALUResult;
wire [XLEN - 1 : 0] readData;
wire [XLEN - 1 : 0] writeData;
/* Module definitions */
//----------------------------------------------------------------
// Instruction Memory
//----------------------------------------------------------------
InstructionMem #(
.INSTRUCTION_FILE_NAME(INSTRUCTION_FILE_NAME)
) iMem (
.instruction(instruction),
.address(PC)
);
//----------------------------------------------------------------
// Instruction Decode Unit
//----------------------------------------------------------------
// The instruction decoder gets instruction from instruction
// memory and decode it, then pass instruction segments to data
// path & control path
//----------------------------------------------------------------
InstructionDecoder instDecoder (
.instruction(instruction),
// To control unit
.opcode(opcode),
.funct3(funct3),
.funct7(funct7),
// To register file
.srcRegister1(srcRegister1),
.srcRegister2(srcRegister2),
.desRegister (desRegister),
.imm(imm)
);
//----------------------------------------------------------------
// Control Unit
//----------------------------------------------------------------
ControlUnit controlUnit (
// Control signals to datapath
.PCSrc(PCSrc),
.resultSrc(resultSrc),
.memWrite(memWrite),
.ALUControl(ALUControl),
.ALUSrc(ALUSrc),
.immSrc(immSrc),
.regWrite(regWrite),
.opcode(opcode),
.funct3(funct3),
.funct7(funct7),
.zero (zero)
);
//----------------------------------------------------------------
// Data Path
//----------------------------------------------------------------
DataPath dataPath (
.PC(PC),
.ALUResult(ALUResult),
.writeData(writeData),
.zero(zero),
.srcRegister1(srcRegister1),
.srcRegister2(srcRegister2),
.desRegister(desRegister),
.readData(readData),
.imm(imm),
.clk(clk),
.rst(rst),
.PCSrc(PCSrc),
.regWrite(regWrite),
.immSrc(immSrc),
.ALUSrc(ALUSrc),
.ALUControl(ALUControl),
.memWrite(memWrite),
.resultSrc(resultSrc)
);
//----------------------------------------------------------------
// Data Memory
//----------------------------------------------------------------
DataMem dataMem (
.readData(readData),
.clk(clk),
.address(ALUResult),
.writeData(writeData),
.writeEnable(memWrite),
.readEnable(1'b1)
);
endmodule
| 8.750164 |
module top0 (
input i_clk_sys50m,
input i_red,
output [6:0] o_num,
output [7:0] o_sel,
output o_sdram_clk,
inout [15:0] io_sdram_data,
output [1:0] o_sdram_ba,
output [12:0] o_sdram_addr,
output o_sdram_ras,
output o_sdram_cas,
output o_sdram_we,
output o_sdram_cke,
output o_sdram_cs,
output o_sdram_udqm,
output o_sdram_ldqm
);
wire clk, clk_red_1us, clk_num_1ms, clk_500ms;
wire intr, rd_ef;
wire [15:0] nouse1, rd_data, get_data;
wire [7:0] nouse2, data;
reg int0, int1, int2, wr_req, cls_raddr;
reg [15:0] wr_data;
reg [5:0] rdcnt, wrcnt;
assign o_sdram_udqm = 1'b0;
assign o_sdram_ldqm = 1'b0;
pll100m pll_inst (
.inclk0(i_clk_sys50m),
.c0(clk),
.c1(o_sdram_clk),
.locked()
);
wire [7:0] state1, state2;
wire [20:0] waddr, raddr;
reg [6:0] cc;
initial begin
cc = 0;
rdcnt = 0;
wrcnt = 0;
wr_req = 1;
cls_raddr = 0;
wr_data = 1;
end
always @(posedge clk) begin
end
sdramfifo sdramfifo_inst (
.i_clk(clk),
.i_rst_n(1'b1),
.i_wr(wr_req),
.i_rd(1'b1),
.i_wr_data(wr_data),
.o_rd_data(rd_data),
.o_cach_full(),
.o_rd_ef(rd_ef),
.o_rd_done(),
.io_sdram_data(io_sdram_data),
.o_sdram_ba(o_sdram_ba),
.o_sdram_addr(o_sdram_addr),
.o_sdram_ras(o_sdram_ras),
.o_sdram_cas(o_sdram_cas),
.o_sdram_we(o_sdram_we),
.o_sdram_cke(o_sdram_cke),
.o_sdram_cs(o_sdram_cs),
//.state1(state1),
//.state2(state2),
//.waddr(waddr),
//.raddr(raddr),
.i_cls_raddr(cls_raddr)
);
wire [31:0] result;
reg [7:0] rstate1, rstate2;
reg chg;
always @(posedge clk) begin
{int0, int1, int2} <= {intr, int0, int1};
if (int1 & !int2) begin
//wr_data <= 16'd1;
//wr_req <= 1'b1;
cls_raddr <= 1'b1;
end else cls_raddr <= 0;
/*if(wr_req)
begin
cc <= cc+1'b1;
wr_req <= (cc==7'd127) ? 1'b0 : 1'b1;
wr_data <= wr_data + 1'b1;
end
else
cc <= 0;*/
cc <= (cc == 7'd127) ? cc : cc + 1'b1;
wr_req <= (cc == 7'd127) ? 1'b0 : 1'b1;
if (wr_req) wr_data[6:0] <= wr_data[6:0] + 1'b1;
end
DIVCLK #(50) divclk0 (
i_clk_sys50m,
clk_red_1us
);
DIVCLK #(50000) divclk1 (
i_clk_sys50m,
clk_num_1ms
);
DIVCLK #(10000000) divclk2 (
i_clk_sys50m,
clk_500ms
);
RED_RECV red (
clk_red_1us,
i_red,
{nouse1, data, nouse2},
intr
);
wire empty;
fifo #(8, 16) i0 (
.wclk (clk),
.rclk (clk_500ms),
.rst (1'b1),
.rreq (1'b1),
.wreq (rd_ef),
.wdata(rd_data), //({rstate1,rstate2}),
.rdata(get_data),
.empty(empty)
);
always @(posedge clk_500ms) rdcnt <= !empty ? rdcnt + 1'b1 : rdcnt;
always @(posedge clk) wrcnt <= rd_ef ? wrcnt + 1'b1 : wrcnt;
assign result = //wr_data[15:8] * 1000000 + wr_data[7:0] * 10000 +
rdcnt * 1000000 + wrcnt * 10000 + get_data[15:8] * 100 + get_data[7:0];
//waddr[12:0]*10000 + raddr[12:0];
NUMSHOW show (
clk_num_1ms,
result,
o_num,
o_sel
);
endmodule
| 6.685 |
module top (
input d,
clk,
output reg q
);
wire u;
wire s;
assign u = s;
assign u = d;
assign u = clk;
always @(posedge clk) q <= u;
endmodule
| 7.233807 |
module top10 #(
parameter DATA_WIDTH = 16,
NUM_WORDS = 16
) (
input clk,
input rst,
input enable,
input [DATA_WIDTH*NUM_WORDS-1:0] array_in,
output [DATA_WIDTH*10-1:0] array_out,
output [6*10-1:0] id_out,
output reg sorted
);
integer j, k, l, m;
// integer x;
// always @(*)begin
// if(enable)begin
// $display($time,"--------------");
// for(x=0;x<NUM_WORDS ;x=x+1)begin
// $display("in%d=%d id=%d",x,array[x],ID[x]);
// end
// end
// end
reg [DATA_WIDTH-1:0] array[NUM_WORDS-1:0];
reg [5:0] ID[NUM_WORDS-1:0];
always @(*) begin
if (enable) begin
l = 0;
for (j = 0; j < NUM_WORDS; j = j + 1) begin
for (k = 0; k < DATA_WIDTH; k = k + 1) begin
array[j][k] = array_in[l];
l = l + 1;
end
end
end
end
reg [6:0] p, head, max, n;
always @(posedge clk or posedge rst) begin
if (rst) begin
p <= NUM_WORDS - 1;
head <= 0;
max <= NUM_WORDS - 1;
sorted = 1'b0;
for (n = 0; n < NUM_WORDS; n = n + 1) begin
ID[n] <= n;
//$display($time,"ID[n]=%d",ID[n]);
end
end else if (enable) begin
if (head < 10) begin
if (p > head) begin
if (array[p] > array[max]) begin
max <= p;
end
p <= p - 1;
end else begin
if (array[head] < array[max]) begin
array[head] <= array[max];
array[max] <= array[head];
end
p <= NUM_WORDS - 1;
head <= head + 1;
max <= NUM_WORDS - 1;
array[head] <= array[max];
array[max] <= array[head];
ID[head] <= ID[max];
ID[max] <= ID[head];
end
end else begin
sorted = 1'b1;
end
end
end
generate
genvar i;
for (i = 0; i < 10; i = i + 1) begin
assign array_out[i*DATA_WIDTH+:DATA_WIDTH] = array[i];
assign id_out[i*6+:6] = ID[i];
end
endgenerate
endmodule
| 6.604105 |
module Top2 (
Clk,
Reset,
v0_OUT,
v1_OUT,
PC_OUT,
MIN_OUT,
test1,
test2,
test3
);
input Clk, Reset;
wire [31:0] v0_A, v1_A, PCValue_A, MIN_A,
v0_B, v1_B, PCValue_B, MIN_B,
v0_C, v1_C, PCValue_C, MIN_C,
v0_D, v1_D, PCValue_D, MIN_D,
v1_final, v0_final, MIN_final;
output reg [31:0] v0_OUT, v1_OUT, MIN_OUT, PC_OUT, test1, test2, test3;
Top DatapathA (
Clk,
Reset,
v1_A,
v0_A,
PCValue_A,
MIN_A
);
TopB DatapathB (
Clk,
Reset,
v1_B,
v0_B,
PCValue_B,
MIN_B
);
TopC DatapathC (
Clk,
Reset,
v1_C,
v0_C,
PCValue_C,
MIN_C
);
TopD DatapathD (
Clk,
Reset,
v1_D,
v0_D,
PCValue_D,
MIN_D
);
THE_BIGGER_SAD The_Bigger_Sad (
v1_A,
v0_A,
MIN_A,
v1_B,
v0_B,
MIN_B,
v1_C,
v0_C,
MIN_C,
v1_D,
v0_D,
MIN_D,
v1_final,
v0_final,
MIN_final
);
always @(*) begin
v0_OUT <= v0_final;
v1_OUT <= v1_final;
MIN_OUT <= MIN_final;
PC_OUT <= PCValue_D;
test1 <= PCValue_A;
test2 <= PCValue_B;
test3 <= PCValue_C;
end
endmodule
| 6.629108 |
module Top3 (
Clk,
Reset,
out7,
en_out
);
input Clk, Reset;
wire Clk_f;
output [6:0] out7;
output [7:0] en_out;
wire [31:0] v1_final, v0_final;
ClkDiv clkdiv (
Clk,
Reset,
Clk_f
);
Top2 FourCoreSystem (
Clk_f,
Reset,
v0_final,
v1_final
);
Two4DigitDisplay TwoDD (
Clk,
v1_final[15:0],
v0_final[15:0],
out7,
en_out
);
endmodule
| 7.702056 |
module top4digit7seg (
input clk,
rst,
input [3:0] dig0,
dig1,
dig2,
dig3,
output [6:0] abcdefg,
output en0,
en1,
en2,
en3 //reg???
);
wire [1:0] sel;
wire nclk;
wire [3:0] ssmout;
//BE FAMILIAR WITH THE DATASHEET OF A 4 DIGIT 7-SEG LED BEFORE PROCEEDING//
SevenSegMux SevenSegMux (
.out(ssmout),
.a (dig0),
.b (dig1),
.c (dig2), //MUXes digit inputs to encoders.
.d (dig3),
.sel(sel)
);
SevenSegEnc SevenSegEnc (
.Disp(abcdefg), //BCD to 7seg encoder
.BCD (ssmout)
);
Selector Selector (
.o0 (en0),
.o1 (en1), //feeds an 1 at every digit's anode consequently
.o2 (en2),
.o3 (en3),
.sel(sel)
);
counttofour counttofour (
.clk(nclk),
.rst(rst), // a counter up to 4 that feeds all select inputs
.cnt(sel)
);
foursegclk foursegclk (
.clk(clk), //clk generator for muxing digits. Correct clock value was found via experimenting
.rst(rst),
.nclk(nclk)
);
endmodule
| 7.057612 |
module topaudio (
input clock,
input miso,
output adconv,
output ready,
output sck,
output mosi,
output daccs,
output dacclr,
output spissb,
output sf_ce0,
output fpgainitb,
output ampcs,
output ampshdn
);
wire clockslow; //fredivider1
wire enablegain, enableadc, enabledac; //controlador1
wire mosigain, sckgain; //gain1
wire [0:11] datosinterno; //adc1
wire sckadc;
wire mosidac, sckdac; //dac1
assign mosi = mosidac | mosigain;
assign sck = (sckgain | sckadc | sckdac);
fredivider fredivider1 (
.clk(clock),
.clk_out(clockslow) //interno
);
controlador controlador1 (
.clock(clockslow),
.enablegain(enablegain), //interno
.enableadc(enableadc), //interno
.enabledac(enabledac), //interno
.spissb(spissb),
.sf_ce0(sf_ce0),
.fpgainitb(fpgainitb)
);
ganancia gain1 (
.clock(clockslow),
.clockenable(enablegain),
.mosi(mosigain), //interno
.sck(sckgain), //interno
.ampcs(ampcs),
.ampshdn(ampshdn)
);
adc adc1 (
.clock(clockslow),
.clockenable(enableadc),
.miso(miso),
.adconv(adconv),
.ready(ready),
.sck(sckadc), //interno
.datos(datosinterno) //interno
);
dac dac1 (
.clock(clockslow),
.clockenable(enabledac),
.datos(datosinterno),
.mosi(mosidac), //interno
.daccs(daccs),
.sck(sckdac), //interno
.dacclr(dacclr)
);
endmodule
| 7.355552 |
module topaudiotest;
// Inputs
reg clock;
reg miso;
// Outputs
wire adconv;
wire ready;
wire sck;
wire mosi;
wire daccs;
wire dacclr;
wire spissb;
wire sf_ce0;
wire fpgainitb;
wire ampcs;
wire ampshdn;
// Instantiate the Unit Under Test (UUT)
topaudio uut (
.clock(clock),
.miso(miso),
.adconv(adconv),
.ready(ready),
.sck(sck),
.mosi(mosi),
.daccs(daccs),
.dacclr(dacclr),
.spissb(spissb),
.sf_ce0(sf_ce0),
.fpgainitb(fpgainitb),
.ampcs(ampcs),
.ampshdn(ampshdn)
);
initial begin
clock = 0;
miso = 0;
#100;
repeat (2500 * 10 ** 3) begin
clock = ~clock;
#50;
end
end
initial begin
clock = 0;
miso = 0;
#100;
repeat (1250 * 10 ** 2) begin
miso = ~miso;
#1000;
end
end
endmodule
| 7.695563 |
module TopAvoidObstacle (
input clk,
input nCR_Avoid,
input left, //
input right, //Ҽ
input Echo_Signal,
output Trig_Signal,
output [1:0] AvoidSignal
);
wire clk_1m;
wire clk_seg;
wire [19:0] dis; // زߵƽʱus
wire CLK_1s;
Divider50MHzAvoid A0 (
.CLK_50M(clk),
.nCLR(nCR_Avoid),
.CLK_1HzOut(clk_1m)
); //chaoshengbo
defparam A0.N = 26, A0.CLK_Freq = 50000000, A0.OUT_Freq = 100000;
Divider50MHzAvoid A1 (
.CLK_50M(clk),
.nCLR(nCR_Avoid),
.CLK_1HzOut(clk_seg)
); //chaoshengbo
defparam A1.N = 26, A1.CLK_Freq = 50000000, A1.OUT_Freq = 2400;
Divider50MHzAvoid A2 (
.CLK_50M(clk),
.nCLR(nCR_Avoid),
.CLK_1HzOut(CLK_1s)
); //chaoshengbo
defparam A2.N = 26, A2.CLK_Freq = 50000000, A2.OUT_Freq = 1;
TrigSignal TS (
.clk_1m(clk_1m),
.rst(nCR_Avoid),
.trig(Trig_Signal)
); //right
PosCounter PC (
.clk_1m(clk_1m),
.rst(nCR_Avoid),
.echo(Echo_Signal),
.dis_count(dis)
);
AvoidGoing AG (
.clk(clk),
.CLK_1s(CLK_1s),
.nCR(nCR_Avoid),
.left(left),
.right(right),
.dis(dis),
.AvoidSignal(AvoidSignal)
);
//SEG_57lut SEG(.CLK(clk_seg), .det_counter(dis[15:0]), .dig(seg[6:0]), .light(light[3:0]));
endmodule
| 6.678003 |
module TopBottom (
x1,
x2,
z1,
z2p,
aL,
zL,
b
);
input [1:0] x1, x2; //Pin
input [1:0] b; //1 digit of y
input [1:0] aL; //input of LSD
output [1:0] z1;
output z2p;
output [1:0] zL; //output of LSD
//---- MSD Slice -------------------------------------------------------
//---- LUT1 ----
wire L1out;
assign L1out = x2[1] ^ (~x2[0]);
//---- LUT2 ----
wire L2outO6, L2outO5;
assign L2outO6 = ~(x1[1] ^ (~x1[0]));
assign L2outO5 = x1[1] ^ (~x1[0]);
//---- LUT3 ----
wire L3out;
assign L3out = x1[1] & (~x1[0]);
//---- allocate input of slice ----
wire [3:0] DI;
wire [3:0] S;
wire CYINIT;
wire CI;
assign DI = {1'b0, 1'b0, L2outO5, x2[1]};
assign S = {1'b0, 1'b0, L2outO6, L1out};
assign CYINIT = 1'b0;
assign CI = 1'b0;
//CARRY4: Fast Carry Logic Component Virtex-6
wire [3:0] CO, O;
CARRY4 CARRY4_inst_MSD (
.CO(CO), // 4-bit carry out
.O(O), // 4-bit carry chain XOR data out
.CI(CI), // 1-bit carry cascade input
.CYINIT(CYINIT), // 1-bit carry initialization
.DI(DI), // 4-bit carry-MUX data in
.S(S) // 4-bit carry-MUX select input
);
//---- allocate output of slice ----
assign {z1, z2p} = {L3out, ~CO[1], O[1]}; //--real results but need 1 extra LUT
//---- LSD Slice -------------------------------------------------------
// see logbook P135
//assign zL[1] = ~(xL[1]^(~xL[0])^((aL[1]&b[1]&(~b[0])) | ((~aL[1])&(~b[1])&b[0]))) | ((xL[1]^(~xL[0])^(aL[1]))&aL[0]);
//assign zL[0] = (xL[1]^(~xL[0])^aL[1]) ^ (~aL[0]);
//assign zL[1] = (((aL[1]&b[1]&(~b[0])) | ((~aL[1])&(~b[1])&b[0]))) | (~aL[1] & aL[0]);
//assign zL[0] = aL[1] ^ aL[0];
/*wire [1:0] yL;
wire [1:0] temp_zL;
assign yL[1] = ~((aL[1]&b[1]&(~b[0])) | ((~aL[1])&(~b[1])&b[0]));
assign yL[0] = ~((aL[0]&b[1]&(~b[0])) | ((~aL[0])&(~b[1])&b[0]));
assign temp_zL = yL[1] + yL[0];
assign zL[1] = ~temp_zL[1];
assign zL[0] = temp_zL[0];
*/
lsd_slice lsd (
.xL(aL),
.y (b),
.zL(zL)
);
endmodule
| 7.068883 |
module topControl (
input [6:0] opcode,
input [3:0] func,
output branch,
memRead,
memToReg,
memWrite,
ALUSrc,
regWrite,
output [3:0] operation
);
wire [1:0] ALUOp;
controlUnit cu (
opcode,
branch,
memRead,
memToReg,
memWrite,
ALUSrc,
regWrite,
ALUOp
);
ALUControl ac (
ALUOp,
func,
operation
);
endmodule
| 8.29194 |
module topCost (
input clk,
input rst,
input set, //预置信号
input [2:0] initcost, //起步价
input [2:0] percost, //单价
input [2:0] addmail, //加费里程
input [15:0] distence,
output [6:0] seg0,
output [6:0] seg1,
output [6:0] seg2,
output [6:0] seg3
);
wire [15:0] fare;
//计费模块
cost a1 (
clk, //时钟信号
rst, //车停止信号
set, //预置信号
initcost, //起步价
percost, //单价
addmail, //加费里程
distence, //行程
fare //车费
);
//费用显示模块
displayCost displayCost (
clk, //时钟信号
rst, //停止信号
fare, //车费
seg0, //HEX0
seg1, //HEX1
seg2, //HEX2
seg3
);
endmodule
| 6.829222 |
module topcount (
input clk,
reset,
direction,
output reg seg_1,
seg_2,
seg_3,
seg_4,
seg_5,
seg_6,
seg_7,
seg_8,
seg_9,
seg_10,
seg_11,
seg_12,
seg_13,
seg_14,
seg_15,
seg_16,
output LOCK,
output [7:0] count3t,
output [3:0] count2t
);
wire [3:0] countt;
wire [3:0] count2t;
wire [7:0] count3t;
reg directionR;
wire CLKOP, clk_1Hz, CLKOK;
wire seg1, seg2, seg3, seg4, seg5, seg6, seg7,
seg8,seg9, seg10,seg11,seg12,seg13,seg14,seg15,seg16;
my_pll my_pll_inst (
.CLK (clk),
.CLKOK(CLKOK),
.CLKOP(CLKOP),
.LOCK (LOCK)
);
clockDivider clockDivider_inst (
CLKOK,
clk_1Hz
);
count8 counter1 (
CLKOK,
reset,
directionR,
count3t
);
count4 counter2 (
clk,
directionR,
reset,
count2t
);
count4 counter3 (
clk_1Hz,
directionR,
reset,
countt
);
LEDtest my_LEDtest (
direction,
seg1,
seg2,
seg3,
seg4,
seg5,
seg6,
seg7,
seg8,
seg9,
seg10,
seg11,
seg12,
seg13,
seg14,
seg15,
seg16,
countt
);
always @(posedge clk_1Hz) begin
directionR = direction;
seg_1 = seg1;
seg_2 = seg2;
seg_3 = seg3;
seg_4 = seg4;
seg_5 = seg5;
seg_6 = seg6;
seg_7 = seg7;
seg_8 = seg8;
seg_9 = seg9;
seg_10 = seg10;
seg_11 = seg11;
seg_12 = seg12;
seg_13 = seg13;
seg_14 = seg14;
seg_15 = seg15;
seg_16 = seg16;
end
endmodule
| 6.583833 |
module TopCountWorkpieces (
input clk,
nCR,
detector,
output [3:0] Light,
output [6:0] seg
);
wire CLK_Light;
wire fall;
wire [15:0] det_counter;
Divider50MHz U0 (
.CLK_50M(clk),
.nCLR(nCR),
.CLK_1HzOut(CLK_Light)
);
defparam U0.N = 26, U0.CLK_Freq = 50000000, U0.OUT_Freq = 2400;
EdgeDetect E0 (
.clk(CLK_Light),
.nCR(nCR),
.button(detector),
.fall(fall)
);
Test T0 (
.detector(fall),
.nCR(nCR),
.det_counter(det_counter[15:0])
);
SEG_57lut U1 (
.CLK(CLK_Light),
.det_counter(det_counter[15:0]),
.dig(seg[6:0]),
.light(Light[3:0])
);
endmodule
| 7.506983 |
module topcpu (
input clk_in,
input reset,
output [7:0] o_seg,
output [7:0] o_sel,
input miso,
output cs,
output mosi,
output spiclk,
output initfinish,
output writefinish,
output readfinish,
/************************/
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_n,
inout [1:0] ddr2_dqs_p,
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output ddr2_ck_p,
output ddr2_ck_n,
output ddr2_cke,
output ddr2_cs_n,
output [1:0] ddr2_dm,
output ddr2_odt
/************tempLook********/
);
wire cpu_stall;
wire [31:0] reg28;
wire [31:0] inst;
wire [31:0] realpc;
reg div_clk = 0;
reg [40:0] clk_cnt = 0;
always @(posedge clk_in or posedge reset) begin
if (reset) begin
div_clk <= 0;
end else if (clk_cnt == 0) begin
div_clk <= ~div_clk;
clk_cnt <= 200000;
end else begin
clk_cnt <= clk_cnt - 1;
end
end
sccomp_dataflow cpu (
div_clk,
reset,
inst,
cpu_stall,
realpc, //pc=realpc>>2
reg28
);
seg7x16 seg (
clk_in,
reset,
1'b1,
reg28,
o_seg,
o_sel
);
wire [31:0] pc;
assign pc = realpc >> 2;
wire ishit;
assign cpu_stall = ~ishit;
ddrandsd threemem (
clk_in,
reset,
miso,
cs,
mosi,
spiclk,
initfinish,
writefinish,
readfinish,
ddr2_dq,
ddr2_dqs_n,
ddr2_dqs_p,
ddr2_addr,
ddr2_ba,
ddr2_ras_n,
ddr2_cas_n,
ddr2_we_n,
ddr2_ck_p,
ddr2_ck_n,
ddr2_cke,
ddr2_cs_n,
ddr2_dm,
ddr2_odt,
ishit,
pc[7:0],
inst
);
endmodule
| 7.267667 |
module mb8_top (
mx1,
my1,
CLK,
RST,
sum1,
carry1,
mx2,
my2
);
parameter WIDTH = 8;
input wire [WIDTH-1:0] mx1;
input wire [WIDTH-1:0] my1;
input wire CLK;
input wire RST;
output wire [(2*WIDTH)-1:0] sum1;
output wire [(2*WIDTH)-1:0] carry1;
output reg [WIDTH-1:0] mx2;
output reg [WIDTH-1:0] my2;
wire [WIDTH-1:0] mx_reg;
wire [WIDTH-1:0] my_reg;
always@ (posedge CLK) // or negedge RST)
begin
mx2 <= mx_reg;
my2 <= my_reg;
end
mb8_td uut (
.mx1(mx1),
.my1(my1),
.CLK(CLK),
.RST(RST),
.sum1(sum1),
.carry1(carry1),
.mx_reg(mx_reg),
.my_reg(my_reg)
);
endmodule
| 6.835868 |
module TopDesign (
input clk,
input [2:0] PathDectSignal,
input En_Tracing,
input SpeedControl,
input nCR,
input detector,
input another,
input nCR_Avoid,
input Echo_Signal,
output [3:0] Led_Direction,
output Speed_Wheel_1,
Speed_Wheel_2,
output [1:0] Control_Wheel_1,
output [1:0] Control_Wheel_2,
output [3:0] Light,
output [6:0] seg,
output Trig_Signal
);
wire [1:0] AvoidSignal;
TopTracing Top0 (
clk,
SpeedControl,
En_Tracing,
PathDectSignal,
nCR_Avoid,
AvoidSignal,
Led_Direction,
Speed_Wheel_1,
Speed_Wheel_2,
Control_Wheel_1,
Control_Wheel_2
);
TopCountWorkpieces Top1 (
clk,
nCR,
detector,
Light,
seg
);
TopAvoidObstacle Top2 (
clk,
nCR_Avoid,
detector,
another,
Echo_Signal,
Trig_Signal,
AvoidSignal
);
endmodule
| 7.796766 |
module topedoMux (
data0,
data1,
data2,
data3,
data4,
data5,
data6,
data7,
sel,
result
);
input data0;
input data1;
input data2;
input data3;
input data4;
input data5;
input data6;
input data7;
input [2:0] sel;
output result;
wire [0:0] sub_wire0;
wire sub_wire10 = data7;
wire sub_wire9 = data6;
wire sub_wire8 = data5;
wire sub_wire7 = data4;
wire sub_wire6 = data3;
wire sub_wire5 = data2;
wire sub_wire4 = data1;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire result = sub_wire1;
wire sub_wire2 = data0;
wire [7:0] sub_wire3 = {
sub_wire10, sub_wire9, sub_wire8, sub_wire7, sub_wire6, sub_wire5, sub_wire4, sub_wire2
};
lpm_mux LPM_MUX_component (
.data(sub_wire3),
.sel(sel),
.result(sub_wire0)
// synopsys translate_off
, .aclr(),
.clken(),
.clock()
// synopsys translate_on
);
defparam LPM_MUX_component.lpm_size = 8, LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 1, LPM_MUX_component.lpm_widths = 3;
endmodule
| 6.532598 |
module TopLayer (
rst,
CLK,
mem_addr,
dis_mode,
swi_halt,
swi_freq,
seg,
an
);
input rst;
input CLK;
input [3:0] mem_addr;
input [2:0] dis_mode;
input swi_halt;
input swi_freq;
output [7:0] seg; //߶ʾ
output [7:0] an; //Ƭѡź
wire clk, clk_dis;
wire [31:0] mem_dis;
//
wire jump;
wire branch;
wire return1;
wire RegDst1;
wire jal;
wire RegDin1;
wire shift;
wire AluB1;
wire syscall;
wire RegWrite;
wire [3:0] ALUOP;
wire DMWrite;
wire [3:0] mode;
wire bat;
//Ĵļ
wire [31:0] regin;
wire [4:0] rW;
wire [4:0] rA, rB;
wire [31:0] reg1, reg2;
//ָ
wire [31:0] instru;
wire [4:0] rd, rs, rt;
wire [5:0] op, func;
wire [25:0] ins26;
wire [15:0] ins16;
wire [ 4:0] shamt;
//չ
wire [31:0] ins16_32;
wire [31:0] ins;
//npc
wire [31:0] pcout, pc4, pc;
//
wire [15:0] total, uncon, con, con_suc;
//alu
wire [31:0] aluX, aluY;
wire equal;
wire [31:0] aluR;
//ݴ洢
wire [31:0] DMout;
//display
wire [31:0] SyscallOut;
;
wire halt;
halt _halt (
.syscall(syscall),
.equal(equal),
.swi_halt(swi_halt),
.halt(halt)
);
display2 _display2 (
.Mode(dis_mode),
.Pc(pc[17:2]),
.SysCallOut(SyscallOut),
.Total(total),
.Uncon(uncon),
.Con(con),
.Con_suc(con_suc),
.clk_N(clk_dis),
.seg(seg),
.an(an),
.MemDisPlay(mem_dis)
);
divider #(100000) divider_dis (
.clk(CLK),
.parameterN(1),
.clk_N(clk_dis)
);
SwitchFreq _swifreq (
.select(swi_freq),
.clk(clk),
.CLK(CLK)
);
controller _controller (
.op(op),
.func(func),
.alur(aluR),
.equal(equal),
.jump(jump),
.branch(branch),
.ret(return1),
.RegDst1(RegDst1),
.jal(jal),
.RegDin1(RegDin1),
.shift(shift),
.ALUOP(ALUOP),
.syscall(syscall),
.RegWrite(RegWrite),
.sw(DMWrite),
.mode(mode),
.bat(bat),
.AluB1(AluB1)
);
regfile _regfile (
.clk(clk),
.rA (rA),
.rB (rB),
.w (regin),
.rw (rW),
.WE (RegWrite),
.A (reg1),
.B (reg2)
);
instruDecoder _instruDecoder (
.instru(instru),
.op(op),
.rs(rs),
.rt(rt),
.rd(rd),
.shamt(shamt),
.func(func)
, .ins16(ins16),
.ins26(ins26)
);
ALU _alu (
.X(aluX),
.Y(aluY),
.S(ALUOP),
.Result1(aluR),
.Equal(equal)
);
npc _npc (
.jump(jump),
.ret(return1),
.branch(branch),
.imm26(ins26),
.c16_32(ins16_32),
.reg1(reg1),
.pc4(pc4),
.pcout(pcout)
);
pc _pc (
.clk(clk),
.rst(rst),
.halt(halt),
.pcout(pcout),
.pc(pc),
.pc4(pc4)
);
counter _counter (
.clk(clk),
.rst(rst),
.branch(branch),
.bat(bat),
.jump(jump),
.return1(return1),
.total(total),
.uncon(uncon),
.con(con),
.con_suc(con_suc)
, .halt(halt)
);
display _display (
.clk(clk),
.rst(rst),
.syscall(syscall),
.equal(equal),
.reg2(reg2),
.syscallout(SyscallOut)
);
RegFileRead _regfileread (
.jal(jal),
.RegDst1(RegDst1),
.syscall(syscall),
.rd(rd),
.rs(rs),
.rt(rt),
.rW(rW),
.rA(rA),
.rB(rB)
);
RegFileWrite _regfilewrite (
.RegDin1(RegDin1),
.jal(jal),
.aluR(aluR),
.DMout(DMout),
.pc4(pc4),
.RegW_out(regin)
);
RegFiletoALU _regfiletoalu (
.A(reg1),
.B(reg2),
.ins(ins),
.AluB_1(AluB1),
.shift(shift),
.syscall(syscall),
.aluX(aluX),
.aluY(aluY)
);
extend _entend (
._16 (ins16),
.sha (shamt),
.out1 (ins16_32),
.out2 (ins),
.shift(shift)
);
IM _IM (
.pc (pc),
.data(instru)
);
DM _DM (
.clk(clk),
.we(DMWrite),
.addr(aluR),
.Din(reg2),
.mode(mode),
.Dout(DMout),
.visin(mem_addr),
.visout(mem_dis)
);
endmodule
| 6.720977 |
module toplayici_33 (
input [32:0] islec0_i,
input [32:0] islec1_i,
output [32:0] toplam_o
);
toplayici utt (
.islec0_i(islec0_i[32:1]),
.islec1_i(islec1_i[32:1]),
.carry_i (islec0_i[0] && islec1_i[0]),
.toplam_o({toplam_o[32:1]})
);
assign toplam_o[0] = islec0_i[0] ^ islec1_i[0];
endmodule
| 6.893337 |
module TopLevelDec (
input start,
read,
clk,
rst,
output ready,
done,
output [6:0] out0,
out1,
out2,
out3
);
reg [17:0] q;
reg [ 2:0] usedw;
ExpAcc acc (
.done(done),
.start(start),
.clk(clk),
.rst(rst),
.read(read),
.ready(ready),
.q(q),
.usedw(usedw)
);
HexDisplay hx0 (
{1'b0, usedw},
out0
);
assign out1 = 7'b000_1001;
wire [3:0] frac;
assign frac = q[15:12] <= 4'd1 ? 4'd0 :
q[15:12] <= 4'd3 ? 4'd1 :
q[15:12] <= 4'd4 ? 4'd2 :
q[15:12] <= 4'd6 ? 4'd3 :
q[15:12] <= 4'd7 ? 4'd4 :
q[15:12] <= 4'd9 ? 4'd5 :
q[15:12] <= 4'd11 ? 4'd6 :
q[15:12] <= 4'd12 ? 4'd7 :
q[15:12] <= 4'd14 ? 4'd8 : 4'd9;
HexDisplay hx2 (
frac,
out2
);
HexDisplay hx3 (
{2'b00, q[17:16]},
out3
);
endmodule
| 7.118355 |
module TopLevelDesign (
input CLK,
input RST,
input [7:0] SWITCHES,
output IR_LED
);
//////////////////////////////////////////////////////////////////////////////////
//Interconnecting wires
//Processor Buses
wire [7:0] data_bus;
wire [7:0] addr_bus;
wire bus_we;
//ROM Buses
wire [7:0] rom_addr;
wire [7:0] rom_data;
//Interrupts
wire [1:0] interrupt;
wire [1:0] interrupt_ack;
//////////////////////////////////////////////////////////////////////////////////
//Instantiate IR Transmitter Module
IRWrapper IR0 (
.CLK(CLK),
.RST(RST),
.ADDR_IN(addr_bus),
.BUS_WE(bus_we),
.DATA_IN(data_bus),
.IR_LED(IR_LED)
);
//Instantiate Timer Module
Timer T0 (
.CLK(CLK),
.RST(RST),
.BUS_ADDR(addr_bus),
.BUS_DATA(data_bus),
.BUS_WE(bus_we),
.BUS_INTERRUPT_ACK(interrupt_ack[1]),
.BUS_INTERRUPT_RAISE(interrupt[1])
);
//Instantiate RAM
RAM RAM0 (
.CLK(CLK),
.BUS_DATA(data_bus),
.BUS_ADDR(addr_bus),
.BUS_WE(bus_we)
);
//Instantiate ROM
ROM ROM0 (
.CLK (CLK),
.DATA(rom_data),
.ADDR(rom_addr)
);
//Instantiate Microprocessor
CPU CPU0 (
.CLK(CLK),
.RESET(RST),
.BUS_DATA(data_bus),
.BUS_ADDR(addr_bus),
.BUS_WE(bus_we),
.ROM_ADDRESS(rom_addr),
.ROM_DATA(rom_data),
.BUS_INTERRUPTS_RAISE(interrupt),
.BUS_INTERRUPTS_ACK(interrupt_ack)
);
//Instantiate Switch Module
Switches SW0 (
.CLK(CLK),
.RST(RST),
.BUS_ADDR(addr_bus),
.SWITCH_VALUE(SWITCHES),
.BUS_DATA(data_bus)
);
endmodule
| 7.384458 |
module toplevelfinal (
input clk,
reset,
output [9:0] sprite_x,
output [8:0] sprite_y,
output [4:0] sprite_sel,
output sprite_attr,
sprite_pos,
sprite_vis,
bck_ch_active,
output font_ch_active,
font_clr,
font_en,
output [10:0] font_addr,
output [3:0] font_data,
output [1:0] bck,
input [1:0] interrupts,
output [4:0] audioVol,
output [3:0] audioSel,
output audioEn,
input gun_data,
input [7:0] controller_data,
output cnt_int,
output [3:0] PCD
);
parameter D_MEM = "data.txt";
parameter I_MEM = "hour.txt";
parameter D_W = 8;
parameter I_W = 10;
parameter IA1 = 32'h00000020; //IO interrupt[0] assigned above
parameter IA2 = 32'h00000020; //IO interrupt[1] assigned above
parameter IA3 = 32'h00000009; //counter0
parameter IA4 = 32'h00000009; //counter1
wire [31:0] instr_addr;
wire [31:0] mem_addr;
wire [31:0] mem_data;
wire [31:0] instr_data;
wire [31:0] wr_data;
wire [D_W-1:0] data_addr_in;
wire [I_W-1:0] instr_addr_in;
wire stallMem;
mips #(IA1, IA2, IA3, IA4) proc (
clk,
reset,
instr_addr,
instr_data,
wr_en,
mem_addr,
wr_data,
mem_data,
instr_ack,
mem_ack,
sprite_x,
sprite_y,
sprite_sel,
sprite_attr,
sprite_pos,
sprite_vis,
bck_ch_active,
font_ch_active,
font_clr,
font_en,
font_addr,
font_data,
bck,
interrupts,
audioVol,
audioSel,
audioEn,
stallMem,
gun_data,
controller_data,
cnt_int,
PCD
);
assign data_addr_in = mem_addr[D_W-1:0];
assign instr_addr_in = instr_addr[I_W-1:0];
memoryfinal #(D_W, D_MEM) data (
clk,
wr_en,
data_addr_in,
wr_data,
mem_data,
mem_ack,
1'b0
);
memoryfinal #(I_W, I_MEM) instr (
clk,
1'b0,
instr_addr_in,
32'h0000,
instr_data,
instr_ack,
stallMem
);
endmodule
| 7.749115 |
module TopLevelHex (
input start,
read,
clk,
rst,
output ready,
done,
output [6:0] out0,
out1,
out2,
out3
);
reg [17:0] q;
ExpAcc acc (
.done(done),
.start(start),
.clk(clk),
.rst(rst),
.read(read),
.ready(ready),
.q(q)
);
HexDisplay hx0 (
q[7:4],
out0
);
HexDisplay hx1 (
q[11:8],
out1
);
HexDisplay hx2 (
q[15:12],
out2
);
HexDisplay hx3 (
{2'b00, q[17:16]},
out3
);
endmodule
| 7.156546 |
module topLevelPiston (
CLOCK_50, // On Board 50 MHz
SW,
KEY, // On Board Keys
// The ports below are for the VGA output.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [7:0] VGA_R; // VGA Red[7:0]
output [7:0] VGA_G; // VGA Green[7:0]
output [7:0] VGA_B; // VGA Blue[7:0]
wire resetn = KEY[0];
wire [2:0] temperature = SW[2:0];
wire [2:0] mode = SW[7:5];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [8:0] x;
wire [7:0] y;
wire writeEn;
vga_adapter VGA (
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "320x240"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "background.mif";
main mySeqCkt (
.clk(CLOCK_50),
.Reset_nFSM(resetn),
.temperature(temperature),
.xComp(SW[3]),
.yComp(SW[4]),
.go(~KEY[1]),
.xPos(x),
.yPos(y),
.colorOut(colour),
.plot(writeEn),
.Incr(~KEY[2]),
.Decr(~KEY[3]),
.compress(SW[9]),
.expand(SW[8]),
.mode(mode)
);
endmodule
| 8.743876 |
module TopLevelModule (
clk,
reset,
reset_check,
h_sync,
v_sync,
red,
blue,
green,
PS2_CLK,
PS2_DATA,
state,
crash_en,
car_on,
road_on
);
input clk;
input reset;
output reset_check;
output h_sync;
output v_sync;
output [3:0] red;
output [3:0] blue;
output [3:0] green;
input PS2_CLK;
input PS2_DATA;
output [2:0] state;
output crash_en;
output car_on;
output road_on;
wire PS2_CLK;
wire PS2_CLK_IBUF;
wire PS2_DATA;
wire PS2_DATA_IBUF;
wire [3:0] blue;
wire car_on;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire crash_en;
wire [3:0] green;
wire [0:0] green_OBUF;
wire h_sync;
wire inkey_n_0;
wire [3:0] red;
wire reset;
wire reset_check;
wire reset_check_OBUF;
wire road_on;
wire [2:0] state;
wire [0:0] state_OBUF;
wire v_sync;
IBUF PS2_CLK_IBUF_inst (
.I(PS2_CLK),
.O(PS2_CLK_IBUF)
);
IBUF PS2_DATA_IBUF_inst (
.I(PS2_DATA),
.O(PS2_DATA_IBUF)
);
OBUF \blue_OBUF[0]_inst (
.I(green_OBUF),
.O(blue[0])
);
OBUF \blue_OBUF[1]_inst (
.I(green_OBUF),
.O(blue[1])
);
OBUF \blue_OBUF[2]_inst (
.I(green_OBUF),
.O(blue[2])
);
OBUF \blue_OBUF[3]_inst (
.I(green_OBUF),
.O(blue[3])
);
OBUF car_on_OBUF_inst (
.I(1'b0),
.O(car_on)
);
BUFG clk_IBUF_BUFG_inst (
.I(clk_IBUF),
.O(clk_IBUF_BUFG)
);
IBUF clk_IBUF_inst (
.I(clk),
.O(clk_IBUF)
);
OBUF crash_en_OBUF_inst (
.I(1'b0),
.O(crash_en)
);
game_state game_states (
.CLK(clk_IBUF_BUFG),
.\FSM_sequential_state_reg[0]_0 (inkey_n_0),
.state_OBUF(state_OBUF)
);
OBUF \green_OBUF[0]_inst (
.I(green_OBUF),
.O(green[0])
);
OBUF \green_OBUF[1]_inst (
.I(green_OBUF),
.O(green[1])
);
OBUF \green_OBUF[2]_inst (
.I(green_OBUF),
.O(green[2])
);
OBUF \green_OBUF[3]_inst (
.I(green_OBUF),
.O(green[3])
);
OBUF h_sync_OBUF_inst (
.I(1'b1),
.O(h_sync)
);
keyboard inkey (
.AR(reset_check_OBUF),
.CLK(clk_IBUF_BUFG),
.D(PS2_CLK_IBUF),
.\b_reg_reg[10] (PS2_DATA_IBUF),
.key_relese_reg_0(inkey_n_0),
.state_OBUF(state_OBUF)
);
pixel_gen pixel_generator (
.CLK(clk_IBUF_BUFG),
.Q (green_OBUF)
);
OBUF \red_OBUF[0]_inst (
.I(1'b1),
.O(red[0])
);
OBUF \red_OBUF[1]_inst (
.I(green_OBUF),
.O(red[1])
);
OBUF \red_OBUF[2]_inst (
.I(green_OBUF),
.O(red[2])
);
OBUF \red_OBUF[3]_inst (
.I(green_OBUF),
.O(red[3])
);
IBUF reset_IBUF_inst (
.I(reset),
.O(reset_check_OBUF)
);
OBUF reset_check_OBUF_inst (
.I(reset_check_OBUF),
.O(reset_check)
);
OBUF road_on_OBUF_inst (
.I(1'b0),
.O(road_on)
);
OBUF \state_OBUF[0]_inst (
.I(state_OBUF),
.O(state[0])
);
OBUF \state_OBUF[1]_inst (
.I(1'b0),
.O(state[1])
);
OBUF \state_OBUF[2]_inst (
.I(1'b0),
.O(state[2])
);
OBUF v_sync_OBUF_inst (
.I(1'b1),
.O(v_sync)
);
endmodule
| 7.42032 |
module game_state (
state_OBUF,
\FSM_sequential_state_reg[0]_0 ,
CLK
);
output [0:0] state_OBUF;
input \FSM_sequential_state_reg[0]_0 ;
input CLK;
wire CLK;
wire \FSM_sequential_state_reg[0]_0 ;
wire [0:0] state_OBUF;
(* FSM_ENCODED_STATES = "iSTATE:10,iSTATE0:01,iSTATE1:00,iSTATE2:11" *)
FDRE #(
.INIT(1'b0)
) \FSM_sequential_state_reg[0] (
.C (CLK),
.CE(1'b1),
.D (\FSM_sequential_state_reg[0]_0 ),
.Q (state_OBUF),
.R (1'b0)
);
endmodule
| 7.12042 |
module: QuickSilverNEO
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TopLevelTest;
// Inputs
reg clk;
// Outputs
wire [2:0] vgaRed;
wire [2:0] vgaGreen;
wire [1:0] vgaBlue;
wire Hsync;
wire Vsync;
// Instantiate the Unit Under Test (UUT)
QuickSilverNEO uut (
.clk(clk),
.vgaRed(vgaRed),
.vgaGreen(vgaGreen),
.vgaBlue(vgaBlue),
.Hsync(Hsync),
.Vsync(Vsync)
);
always begin
#10 clk = ~clk;
end
initial begin
// Initialize Inputs
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.435384 |
module topLevelVendingMachine (
input c,
u, // Botao 1, 2,
input cima,
baixo,
enter, // Botao 3,4,5
input clock,
reset, // 50 MHz Clock
output [9:0] led, // Led
output sucesso, // Parametro para afirmar se funcionou ou nao
output pizza,
burguer,
torta,
soda // saidas da maquina
);
wire [5:0] saldo, gasto;
wire [10:0] balance_option;
wire [ 3:0] menu_option;
assign oVGA_R = 10'd0;
assign oVGA_G = 10'd0;
assign oVGA_B = 10'd0;
controle_de_saldo cds (
.c(c),
.u(u),
.clock(clock),
.reset(reset),
.gastoIn(gasto),
.sucesso(sucesso),
.led(led),
.saldoOut(saldo),
.balance_option(balance_option)
);
menu main (
.cima(cima),
.baixo(baixo),
.enter(enter),
.clock(clock),
.reset(reset),
.saldoIn(saldo),
.pizza(pizza),
.burguer(burguer),
.torta(torta),
.soda(soda),
.gastoOut(gasto),
.menu_option(menu_option)
);
endmodule
| 6.833642 |
module toplevel_apo_5_nodes (
clk,
out_data,
sw_on,
sw_sel_data,
sw_sel_router,
key_inc,
key_dec,
hex_data,
hex_router
);
input clk;
input sw_on;
input sw_sel_data;
input sw_sel_router;
input key_inc;
input key_dec;
output wire [127:0] out_data;
output wire [6:0] hex_data;
output wire [6:0] hex_router;
wire [`N2-1:0] out_router1;
wire [`N2-1:0] out_router2;
wire [`N2-1:0] out_router3;
wire [`N2-1:0] out_router4;
wire [`N2-1:0] out_router5;
wire[`N2-1:0] r_minR[0:`N_COUNT];// размерности элементов из массива количеством
wire [`N2-1:0] r_maxR[0:`N_COUNT];
wire [`N2-1:0] r_minL[0:`N_COUNT];
wire [`N2-1:0] r_maxL[0:`N_COUNT];
select_data_5 sel (
.clk(clk),
.sw_on(sw_on),
.sw_sel_data(sw_sel_data),
.sw_sel_router(sw_sel_router),
.key_inc(key_inc),
.key_dec(key_dec),
.out_router1(out_router1),
.out_router2(out_router2),
.out_router3(out_router3),
.out_router4(out_router4),
.out_router5(out_router5),
.hex_data(hex_data),
.hex_router(hex_router)
);
apo_router_5_nodes r1 (
.clk(clk),
.router_name(3'b000),
.in_free(out_router1),
.in_r1R(r_minL[1]),
.in_r2R(r_maxL[2]),
.in_r1L(r_minR[4]),
.in_r2L(r_maxR[3]),
.out_r1R(r_minR[0]),
.out_r2R(r_maxR[0]),
.out_r1L(r_minL[0]),
.out_r2L(r_maxL[0]),
.out_data(out_data[0])
);
apo_router_5_nodes r2 (
.clk(clk),
.router_name(3'b001),
.in_free(out_router2),
.in_r1R(r_minL[2]),
.in_r2R(r_maxL[3]),
.in_r1L(r_minR[0]),
.in_r2L(r_maxR[4]),
.out_r1R(r_minR[1]),
.out_r2R(r_maxR[1]),
.out_r1L(r_minL[1]),
.out_r2L(r_maxL[1]),
.out_data(out_data[1])
);
apo_router_5_nodes r3 (
.clk(clk),
.router_name(3'b010),
.in_free(out_router3),
.in_r1R(r_minL[3]),
.in_r2R(r_maxL[4]),
.in_r1L(r_minR[1]),
.in_r2L(r_maxR[0]),
.out_r1R(r_minR[2]),
.out_r2R(r_maxR[2]),
.out_r1L(r_minL[2]),
.out_r2L(r_maxL[2]),
.out_data(out_data[2])
);
apo_router_5_nodes r4 (
.clk(clk),
.router_name(3'b011),
.in_free(out_router4),
.in_r1R(r_minL[4]),
.in_r2R(r_maxL[0]),
.in_r1L(r_minR[2]),
.in_r2L(r_maxR[1]),
.out_r1R(r_minR[3]),
.out_r2R(r_maxR[3]),
.out_r1L(r_minL[3]),
.out_r2L(r_maxL[3]),
.out_data(out_data[3])
);
apo_router_5_nodes r5 (
.clk(clk),
.router_name(3'b100),
.in_free(out_router5),
.in_r1R(r_minL[0]),
.in_r2R(r_maxL[1]),
.in_r1L(r_minR[3]),
.in_r2L(r_maxR[2]),
.out_r1R(r_minR[4]),
.out_r2R(r_maxR[4]),
.out_r1L(r_minL[4]),
.out_r2L(r_maxL[4]),
.out_data(out_data[4])
);
endmodule
| 7.129722 |
module toplevel_apo_9_nodes (
clk,
out_data,
sw_on,
sw_sel_data,
sw_sel_router,
key_inc,
key_dec,
hex_data,
hex_router
);
input clk;
input sw_on;
input sw_sel_data;
input sw_sel_router;
input key_inc;
input key_dec;
output wire [127:0] out_data;
output wire [6:0] hex_data;
output wire [6:0] hex_router;
wire [`N2-1:0] out_router1;
wire [`N2-1:0] out_router2;
wire [`N2-1:0] out_router3;
wire [`N2-1:0] out_router4;
wire [`N2-1:0] out_router5;
wire [`N2-1:0] out_router6;
wire [`N2-1:0] out_router7;
wire [`N2-1:0] out_router8;
wire [`N2-1:0] out_router9;
wire[`N2-1:0] r_minR[0:`N_COUNT];// размерности элементов из массива количеством
wire [`N2-1:0] r_maxR[0:`N_COUNT];
wire [`N2-1:0] r_minL[0:`N_COUNT];
wire [`N2-1:0] r_maxL[0:`N_COUNT];
select_data_9 sel (
.clk(clk),
.sw_on(sw_on),
.sw_sel_data(sw_sel_data),
.sw_sel_router(sw_sel_router),
.key_inc(key_inc),
.key_dec(key_dec),
.out_router1(out_router1),
.out_router2(out_router2),
.out_router3(out_router3),
.out_router4(out_router4),
.out_router5(out_router5),
.out_router6(out_router6),
.out_router7(out_router7),
.out_router8(out_router8),
.out_router9(out_router9),
.hex_data(hex_data),
.hex_router(hex_router)
);
apo_router_9_nodes r1 (
.clk(clk),
.router_name(4'b0000),
.in_free(out_router1),
.in_r1R(r_minL[2]),
.in_r2R(r_maxL[3]),
.in_r1L(r_minR[7]),
.in_r2L(r_maxR[6]),
.out_r1R(r_minR[0]),
.out_r2R(r_maxR[0]),
.out_r1L(r_minL[0]),
.out_r2L(r_maxL[0]),
.out_data(out_data[0])
);
apo_router_9_nodes r2 (
.clk(clk),
.router_name(4'b0001),
.in_free(out_router2),
.in_r1R(r_minL[3]),
.in_r2R(r_maxL[4]),
.in_r1L(r_minR[8]),
.in_r2L(r_maxR[7]),
.out_r1R(r_minR[1]),
.out_r2R(r_maxR[1]),
.out_r1L(r_minL[1]),
.out_r2L(r_maxL[1]),
.out_data(out_data[1])
);
apo_router_9_nodes r3 (
.clk(clk),
.router_name(4'b0010),
.in_free(out_router3),
.in_r1R(r_minL[4]),
.in_r2R(r_maxL[5]),
.in_r1L(r_minR[0]),
.in_r2L(r_maxR[8]),
.out_r1R(r_minR[2]),
.out_r2R(r_maxR[2]),
.out_r1L(r_minL[2]),
.out_r2L(r_maxL[2]),
.out_data(out_data[2])
);
apo_router_9_nodes r4 (
.clk(clk),
.router_name(4'b0011),
.in_free(out_router4),
.in_r1R(r_minL[5]),
.in_r2R(r_maxL[6]),
.in_r1L(r_minR[1]),
.in_r2L(r_maxR[0]),
.out_r1R(r_minR[3]),
.out_r2R(r_maxR[3]),
.out_r1L(r_minL[3]),
.out_r2L(r_maxL[3]),
.out_data(out_data[3])
);
apo_router_9_nodes r5 (
.clk(clk),
.router_name(4'b0100),
.in_free(out_router5),
.in_r1R(r_minL[6]),
.in_r2R(r_maxL[7]),
.in_r1L(r_minR[2]),
.in_r2L(r_maxR[1]),
.out_r1R(r_minR[4]),
.out_r2R(r_maxR[4]),
.out_r1L(r_minL[4]),
.out_r2L(r_maxL[4]),
.out_data(out_data[4])
);
apo_router_9_nodes r6 (
.clk(clk),
.router_name(4'b0101),
.in_free(out_router6),
.in_r1R(r_minL[7]),
.in_r2R(r_maxL[8]),
.in_r1L(r_minR[3]),
.in_r2L(r_maxR[2]),
.out_r1R(r_minR[5]),
.out_r2R(r_maxR[5]),
.out_r1L(r_minL[5]),
.out_r2L(r_maxL[5]),
.out_data(out_data[5])
);
apo_router_9_nodes r7 (
.clk(clk),
.router_name(4'b0110),
.in_free(out_router7),
.in_r1R(r_minL[8]),
.in_r2R(r_maxL[0]),
.in_r1L(r_minR[4]),
.in_r2L(r_maxR[3]),
.out_r1R(r_minR[6]),
.out_r2R(r_maxR[6]),
.out_r1L(r_minL[6]),
.out_r2L(r_maxL[6]),
.out_data(out_data[6])
);
apo_router_9_nodes r8 (
.clk(clk),
.router_name(4'b0111),
.in_free(out_router8),
.in_r1R(r_minL[0]),
.in_r2R(r_maxL[1]),
.in_r1L(r_minR[5]),
.in_r2L(r_maxR[4]),
.out_r1R(r_minR[7]),
.out_r2R(r_maxR[7]),
.out_r1L(r_minL[7]),
.out_r2L(r_maxL[7]),
.out_data(out_data[7])
);
apo_router_9_nodes r9 (
.clk(clk),
.router_name(4'b1000),
.in_free(out_router9),
.in_r1R(r_minL[1]),
.in_r2R(r_maxL[2]),
.in_r1L(r_minR[6]),
.in_r2L(r_maxR[5]),
.out_r1R(r_minR[8]),
.out_r2R(r_maxR[8]),
.out_r1L(r_minL[8]),
.out_r2L(r_maxL[8]),
.out_data(out_data[8])
);
endmodule
| 7.129722 |
module integrate_system (
input clk,
rst,
adjust,
end_cal,
start,
input [3:0] n,
input [15:0] InFreq,
input [15:0] frac,
input [1:0] ui,
output valid,
done
);
fer_mul_toplevel fre (
clk,
rst,
adjust,
end_cal,
n,
InFreq,
valid,
out
);
exp_wrapper ex (
out,
rst,
start,
frac,
ui,
n,
done
);
endmodule
| 6.973707 |
module integrateTB ();
reg clk, rst, adjust, end_cal, start;
reg [ 3:0] n;
reg [15:0] InFreq;
reg [15:0] frac;
reg [ 1:0] ui;
wire valid, done;
integrate_system cpu (
clk,
rst,
adjust,
end_cal,
start,
n,
InFreq,
frac,
ui,
valid,
done
);
initial begin
clk = 1'b1;
rst = 1'b0;
ui = 2'b00;
frac = 16'b0000001010001111; //0.01
InFreq = 16'd2500; //200 kHz
n = 4'b1001;
#7 start = 1'b0;
end
always #3 clk = ~clk; //162 MHz
initial begin
adjust = 1'b0;
#7 adjust = 1'b1;
#100000 start = 1;
#1000 start = 1'b0;
#10000000 end_cal = 1'b1;
end
/*initial begin
clk = 1'b1;
rst = 1'b0;
ui = 2'b00;
frac = 16'b0000001010001111;//0.01
InFreq = 16'd2500;//200 kHz
n = 4'b0111;
#255 start = 1'b0;
end
always #125 clk = ~clk;//25 MHz
initial begin
adjust = 1'b0;
#255 adjust = 1'b1;
#100000
#255 start = 1;
#100 start = 1'b0;
#1000000 end_cal = 1'b1;
end*/
endmodule
| 7.443204 |
module TopLevel_evt_sync #(
parameter SIZE = 65,
parameter DATA_WIDTH = 65,
parameter FIFO_DEPTH = 6,
parameter TOTAL_CLUSTERS = 17,
parameter TOTAL_OUTPUT_BOARDS = 4,
parameter BOARD_ID = 0
) (
input wire clock,
input wire reset_n,
input wire [SIZE-1:0] input_data[TOTAL_CLUSTERS],
output wire [SIZE-1:0] output_data[TOTAL_OUTPUT_BOARDS]
);
// connections between input Spy+FIFO and EventSync
wire evt_sync_input_wren[TOTAL_CLUSTERS];
wire [DATA_WIDTH-1:0] evt_sync_input_data[TOTAL_CLUSTERS];
wire evt_sync_input_read_request[TOTAL_CLUSTERS];
wire evt_sync_input_almost_full [TOTAL_CLUSTERS]; // dantrim: does EvtSync input need this almost_full flag if it is just *pulling* data from the input fifos?
wire evt_sync_input_empty[TOTAL_CLUSTERS];
// connections between output Spy+FIFO and EventSync
wire [DATA_WIDTH-1:0] evt_sync_output_data[TOTAL_OUTPUT_BOARDS];
wire evt_sync_output_write_enable[TOTAL_OUTPUT_BOARDS];
wire evt_sync_output_almost_full[TOTAL_OUTPUT_BOARDS];
//
// Input buffers
//
generate
for (genvar i = 0; i < TOTAL_CLUSTERS; i++) begin : input_spybuffers
SpyBuffer #(
.DATA_WIDTH(SIZE - 1),
.FC_FIFO_WIDTH(FIFO_DEPTH)
) spybuffer (
.rclock(clock),
.wclock(clock),
.rreset(reset_n),
.wreset(reset_n),
.write_data(input_data[i]),
.read_data(evt_sync_input_data[i]),
.read_enable(evt_sync_input_read_request[i]),
.write_enable(evt_sync_input_wren[i]),
.almost_full(evt_sync_input_almost_full[i]),
.empty(evt_sync_input_empty[i])
);
end
endgenerate
//
// EventSync block
//
event_sync #(
.DATA_WIDTH(DATA_WIDTH),
.TOTAL_CLUSTERS(TOTAL_CLUSTERS),
.TOTAL_OUTPUT_BOARDS(TOTAL_OUTPUT_BOARDS),
.FIFO_DEPTH_BITS(FIFO_DEPTH),
.BOARD_ID(BOARD_ID)
) event_sync_inst (
.es_clk(clock),
.es_rst_n(reset_n),
.es_srst_n(reset_n),
.cluster_data(evt_sync_input_data),
.cluster_req(evt_sync_input_read_request),
.cluster_almost_full(evt_sync_input_almost_full),
.cluster_empty(evt_sync_input_empty),
.output_board_event(evt_sync_output_data),
.output_board_wren(evt_sync_output_write_enable),
.output_board_almost_full(evt_sync_output_almost_full)
);
//
// Output buffers
//
generate
for (genvar i = 0; i < TOTAL_OUTPUT_BOARDS; i++) begin : output_spybuffers
SpyBuffer #(
.DATA_WIDTH(SIZE - 1),
.FC_FIFO_WIDTH(FIFO_DEPTH)
) spybuffer (
.rclock(clock),
.wclock(clock),
.rreset(reset_n),
.wreset(reset_n),
.read_data(output_data[i]),
.write_data(evt_sync_output_data[i]),
.write_enable(evt_sync_output_write_enable[i]),
.almost_full(evt_sync_output_almost_full[i])
);
end
endgenerate
endmodule
| 6.652922 |
module cpu_test ();
reg clk;
reg reset;
// Clock generation
initial clk = 0;
always #10 clk = !clk;
// Instantiate CPU
dsp dsp (.clk(clk));
initial begin
$readmemb("./assemble/machine_code_short.dat", dsp.InstrMem.mem, 0);
$readmemb("./assemble/data_mem.dat", dsp.DataMem.mem, 0);
$display("$mem %b", dsp.InstrMem.mem[0]);
$dumpfile("dspTopLevel.vcd");
$dumpvars();
// Assert reset pulse
reset = 0;
#10;
reset = 1;
#10;
reset = 0;
#10;
#82450;
$display("----------------------------------------");
$display("TEST Complete");
$display("----------------------------------------");
#2000 $finish();
end
endmodule
| 7.39269 |
module toplevel_pl (
output reg [7:0] JA,
output reg [7:0] JB,
inout [7:0] JC,
inout [7:0] JD,
output reg [7:0] led,
input [7:0] sw,
input BTNL,
input BTNR,
input BTNU,
input BTND,
input BTNC,
input GCLK
);
wire clk;
clk_div cdiv (
.clk_in(GCLK),
.clk_out(clk),
.div(8'd15)
);
reg [7:0] sw_reg;
wire [7:0] digit_data;
wire [4:0] digit_select;
always @(posedge GCLK) begin
sw_reg <= sw;
led <= sw;
JA <= digit_data;
JB <= {
3'd0, digit_select[4], digit_select[0], digit_select[1], digit_select[2], digit_select[3]
};
end
digital_display_4(
.data({16'h1234}),
.format_select(BTNC), // 0 = hex, 1 = decimal
.digit(digit_data),
.select(digit_select[3:0]),
.clk(clk)
);
endmodule
| 8.02994 |
module toplevel_primerLoopback #(
parameter LEN_DATA_BLOCK = 64,
parameter LEN_CTRL_BLOCK = 8,
parameter LEN_CODED_BLOCK = 66,
parameter TX_NMODULES = 2,
parameter RX_NMODULES = 2
) (
input i_clock,
input i_reset,
input i_enable_frameGenerator,
input i_enable_frameChecker, //al frame checker hay que habilitarlo 10 ciclos de clock dsp (por el delay)
input [TX_NMODULES-1 : 0] i_enable_tx,
input [RX_NMODULES-1 : 0] i_enable_rx,
output wire [LEN_DATA_BLOCK-1 : 0] o_rx_raw_data,
output wire [LEN_CTRL_BLOCK-1 : 0] o_rx_raw_ctrl
);
wire [ LEN_DATA_BLOCK-1 : 0] encoder_data_input;
wire [ LEN_CTRL_BLOCK-1 : 0] encoder_ctrl_input;
wire [LEN_CODED_BLOCK-1 : 0] scrambled_data;
wire match_data;
wire match_ctrl;
top_level_frameGenerator #(
.LEN_DATA_BLOCK(LEN_DATA_BLOCK),
.LEN_CTRL_BLOCK(LEN_CTRL_BLOCK)
) u_top_level_frameGenerator (
.i_clock (i_clock),
.i_reset (i_reset),
.i_enable (i_enable_frameGenerator),
.o_tx_data(encoder_data_input),
.o_tx_ctrl(encoder_ctrl_input)
);
tx_modules #() u_tx_modules (
.i_clock(i_clock),
.i_reset(i_reset),
.i_tx_data(encoder_data_input),
.i_tx_ctrl(encoder_ctrl_input),
.i_enable(i_enable_tx),
.o_scrambled_data(scrambled_data)
);
rx_modules #() u_rx_modules (
.i_clock(i_clock),
.i_reset(i_reset),
.i_enable(i_enable_rx),
.i_scrambled_data(scrambled_data),
.o_rx_raw_data(o_rx_raw_data),
.o_rx_raw_ctrl(o_rx_raw_ctrl)
);
frameChecker #() u_frameChecker (
.i_clock(i_clock),
.i_reset(i_reset),
.i_enable(i_enable_frameChecker),
.i_tx_data(encoder_data_input),
.i_tx_ctrl(encoder_ctrl_input),
.i_rx_raw_data(o_rx_raw_data),
.i_rx_raw_ctrl(o_rx_raw_ctrl),
.o_match_data(match_data),
.o_match_ctrl(match_ctrl)
);
endmodule
| 7.781586 |
module cpu_test ();
reg clk;
reg reset;
// Clock generation
initial clk = 0;
always #10 clk = !clk;
// Instantiate CPU
dsp dsp (.clk(clk));
initial begin
$readmemb("./assemble/machine_code_full.dat", dsp.InstrMem.mem, 0);
$readmemb("./assemble/data_mem.dat", dsp.DataMem.mem, 0);
$display("$mem %b", dsp.InstrMem.mem[0]);
$dumpfile("dspTopLevel.vcd");
$dumpvars();
// Assert reset pulse
reset = 0;
#10;
reset = 1;
#10;
reset = 0;
#10;
#82450;
$display("----------------------------------------");
$display("TEST Complete");
$display("----------------------------------------");
#2000 $finish();
end
endmodule
| 7.39269 |
module TopLevel_sim ();
reg clkin, btnU, btnD, btnL, btnR;
reg [15:0] sw;
wire Hsync, Vsync;
wire [3:0] vgaRed, vgaBlue, vgaGreen;
TopLevel UUT (
.clkin(clkin),
.btnU(btnU),
.btnD(btnD),
.btnL(btnL),
.btnR(btnR),
.sw(sw),
.Hsync(Hsync),
.Vsync(Vsync),
.vgaRed(vgaRed),
.vgaBlue(vgaBlue),
.vgaGreen(vgaGreen)
);
parameter PERIOD = 10;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 2;
initial // Clock process for clkin
begin
#OFFSET clkin = 1'b1;
forever begin
#(PERIOD - (PERIOD * DUTY_CYCLE)) clkin = ~clkin;
end
end
initial begin
btnU = 1'b0;
btnD = 1'b0;
btnR = 1'b0;
btnL = 1'b0;
sw[15:0] = 1'b0;
#1000;
sw[1] = 1'b1;
#100;
sw[1] = 1'b0;
#100;
end
endmodule
| 6.553764 |
module TopLevel_sw_switcher #(
parameter SIZE = 65,
parameter DATA_WIDTH = 65,
parameter FIFO_DEPTH = 6,
parameter TOTAL_INPUTS = 2,
parameter TOTAL_OUTPUTS = 2
) (
input wire clock,
input wire reset_n,
input wire [SIZE-1:0] input_data[TOTAL_INPUTS],
output wire [SIZE-1:0] output_data[TOTAL_OUTPUTS]
);
wire [SIZE-1:0] input_data_out[ TOTAL_INPUTS];
wire [SIZE-1:0] output_data_in[TOTAL_OUTPUTS];
//
// input buffers
//
generate
for (genvar i = 0; i < TOTAL_INPUTS; i++) begin : input_spybuffers
SpyBuffer #(
.DATA_WIDTH(SIZE - 1),
.FC_FIFO_WIDTH(FIFO_DEPTH)
) spybuffer (
.rclock(clock),
.wclock(clock),
.rreset(reset_n),
.wreset(reset_n)
);
end
endgenerate
//
// output buffers
generate
for (genvar i = 0; i < TOTAL_OUTPUTS; i++) begin : output_spybuffers
SpyBuffer #(
.DATA_WIDTH(SIZE - 1),
.FC_FIFO_WIDTH(FIFO_DEPTH)
) spybuffer (
.rclock(clock),
.wclock(clock),
.rreset(reset_n),
.wreset(reset_n)
);
end
endgenerate
endmodule
| 9.244739 |
module TopLevel_tb ();
reg clk;
reg rst;
TopLevel #(
.ROM_ADDR (10),
.DATA_BITS(32),
.MEM_ADDR (10),
.PC_ADDR (10)
) //Rom的地?线长、PC的数据位?
toplevel (
.clk(clk),
.btnL(rst),
.seg(), // segment driver signals, ordered { a, b, ..., g, dp }
.dp(),
.an() // place enable signals, active on LOW
);
initial begin
clk <= 0;
rst <= 1;
#20000 rst <= 0;
end
always begin
#5 clk <= ~clk;
end
endmodule
| 6.705295 |
module toplevel_test;
// Inputs
// UART
reg RST = 1;
reg CLK = 0;
reg RXD = 1;
//CAMERA
reg PIXCLK = 1;
reg FRAME_VALID = 0;
reg LINE_VALID = 0;
reg [9:0] DATA_IN = 0;
// Outputs
wire TXD;
wire CAM_SYSCLK = CLK;
// Instantiate the Unit Under Test (UUT)
topmodule #(2, 3) uut (
.RST(RST),
.CLK(CLK),
.UART_RXD(RXD),
.UART_TXD(TXD),
.CAM_PIXCLK(PIXCLK),
.CAM_FRAME_VALID(FRAME_VALID),
.CAM_LINE_VALID(LINE_VALID),
.CAM_DATA(DATA_IN)
);
wire [7:0] DECODED;
wire DECODED_READY;
uart_receive uut1 (
.RST(RST),
.CLK(CLK),
.RXD(TXD),
.DATA(DECODED),
.RXD_READY(DECODED_READY)
);
initial begin
// Wait for global reset to finish
#1000;
RST = 0;
#3000;
//...STOP, START, 1, 0, 1, 0, 1, 0, 1, 0, STOP...
RXD = 0;
#1000;
RXD = 0;
#1000;
RXD = 1;
#1000;
RXD = 0;
#1000;
RXD = 1;
#1000;
RXD = 0;
#1000;
RXD = 1;
#1000;
RXD = 0;
#1000;
RXD = 1;
#1000;
RXD = 1;
#1000;
end
initial begin
// Initialize Inputs
LINE_VALID = 1;
FRAME_VALID = 1;
DATA_IN = 0;
// Test ignoring of random already ongoing frame
#1852;
#1852;
#1852;
forever begin
LINE_VALID = 0;
FRAME_VALID = 0;
#37.04;
FRAME_VALID = 1;
#37.04;
LINE_VALID = 1;
DATA_IN = 11 << 2;
#37.04;
LINE_VALID = 1;
DATA_IN = 12 << 2;
#37.04;
LINE_VALID = 0;
#37.04;
LINE_VALID = 1;
DATA_IN = 21 << 2;
#37.04;
LINE_VALID = 1;
DATA_IN = 22 << 2;
#37.04;
LINE_VALID = 0;
#37.04;
LINE_VALID = 1;
DATA_IN = 31 << 2;
#37.04;
LINE_VALID = 1;
DATA_IN = 32 << 2;
#37.04;
end
end
always #18.52 CLK <= ~CLK;
always #18.52 PIXCLK <= ~PIXCLK;
initial #100000 $finish;
endmodule
| 7.105914 |
module TopLevel_tb ();
parameter ADDRESS_SIZE = 32;
parameter TRAINING_DATA_SIZE = 4100000;
parameter INSTRUCTION_INDEX_SIZE = $clog2(TRAINING_DATA_SIZE);
parameter GHL = 22;
parameter WS = 5;
parameter LS = 128;
parameter LS_INDEX_SIZE = $clog2(LS);
reg Clk, Rst;
wire BranchPrediction;
wire PredictionCorrect;
wire [INSTRUCTION_INDEX_SIZE - 1:0] CorrectlyPredicted, TotalBranches;
reg [INSTRUCTION_INDEX_SIZE - 1:0] temp_branch = 32'h00;
TopLevel#(ADDRESS_SIZE, TRAINING_DATA_SIZE, INSTRUCTION_INDEX_SIZE, GHL, WS, LS, LS_INDEX_SIZE)
TopLevel_0(
Clk,
Rst,
BranchPrediction,
PredictionCorrect,
CorrectlyPredicted,
TotalBranches
);
initial begin
Clk <= 1'b0;
forever #1 Clk <= ~Clk;
end
initial begin
Rst <= 0;
#100 Rst <= 1;
end
always @(TotalBranches) begin
if (TotalBranches % 32'd100000 == 32'd000000) begin
$display("The hit rate is%d ,%d, %d", CorrectlyPredicted, TotalBranches,
CorrectlyPredicted - temp_branch);
//$display("The hit rate is%d",(CorrectlyPredicted-temp_branch)/100000);
temp_branch <= CorrectlyPredicted;
end
end
endmodule
| 6.705295 |
module topLevel_wrapper (
CLK100MHZ,
ck_io,
ck_rst,
led,
trigger,
uart_rxd_out,
uart_txd_in
);
input CLK100MHZ;
input [3:0] ck_io;
input ck_rst;
output [3:0] led;
input trigger;
output uart_rxd_out;
input uart_txd_in;
wire CLK100MHZ;
wire [3:0] ck_io;
wire ck_rst;
wire [3:0] led;
wire trigger;
wire uart_rxd_out;
wire uart_txd_in;
topLevel topLevel_i (
.CLK100MHZ(CLK100MHZ),
.ck_io(ck_io),
.ck_rst(ck_rst),
.led(led),
.trigger(trigger),
.uart_rxd_out(uart_rxd_out),
.uart_txd_in(uart_txd_in)
);
endmodule
| 8.516765 |
module Toplv (
input en,
input clk,
input rst,
output [7:0] AN,
output [1:7] seg
);
wire [25:0] dispSel;
wire [ 3:0] wmod6;
wire [ 3:0] wmod10;
wire [ 3:0] wmux;
progcnt #(
.N (26),
.MAX(67108863)
) main (
.clk(clk),
.rst(rst),
.en(1),
.count(dispSel)
);
progcnt #(
.N (4),
.MAX(9)
) mod10 (
.clk(dispSel[25]),
.rst(rst),
.en(en),
.count(wmod10)
);
progcnt #(
.N (4),
.MAX(5)
) mod6 (
.clk(dispSel[25]),
.rst(rst),
.en(en && wmod10 == 9),
.count(wmod6)
);
mux mux (
.mod6 (wmod6),
.mod10(wmod10),
.sel (dispSel[16]),
.out (wmux)
);
bin2seg seg7 (
.ca (1),
.bin(wmux),
.seg(seg)
);
assign AN[7] = 1;
assign AN[6] = 1;
assign AN[5] = 1;
assign AN[4] = 1;
assign AN[3] = 1;
assign AN[2] = 1;
assign AN[1] = ~dispSel[16];
assign AN[0] = dispSel[16];
endmodule
| 6.858588 |
module toplevel_STACK (
input clk,
rst
);
wire [2:0] opcode, ALUOP;
wire PCSrc, pc_write, pc_write_con, mem_sel, Mem_read, Mem_write,
IR_write, stack_sel, load_A, A_sel, B_sel, push, pop, tos, ALUZero;
datapath dp (
clk,
rst,
PCSrc,
pc_write,
pc_write_con,
ALUZero,
mem_sel,
Mem_read,
Mem_write,
IR_write,
stack_sel,
load_A,
A_sel,
B_sel,
push,
pop,
tos,
ALUOP,
ALUZero,
opcode
);
controller cont (
clk,
rst,
opcode,
ALUZero,
PCSrc,
pc_write,
pc_write_con,
mem_sel,
Mem_read,
Mem_write,
IR_write,
stack_sel,
load_A,
A_sel,
B_sel,
push,
pop,
tos,
ALUOP
);
endmodule
| 6.893419 |
module AtomALU (
input [63:0] io_src1,
input [63:0] io_src2,
input [ 6:0] io_func,
input io_isWordOp,
output [63:0] io_result
);
wire isAdderSub = ~io_func[6]; // @[LSU.scala 184:20]
wire [63:0] _T_2 = isAdderSub ? 64'hffffffffffffffff : 64'h0; // @[Bitwise.scala 72:12]
wire [63:0] _T_3 = io_src2 ^ _T_2; // @[LSU.scala 185:33]
wire [64:0] _T_4 = io_src1 + _T_3; // @[LSU.scala 185:24]
wire [64:0] _GEN_0 = {{64'd0}, isAdderSub}; // @[LSU.scala 185:60]
wire [64:0] adderRes = _T_4 + _GEN_0; // @[LSU.scala 185:60]
wire [63:0] xorRes = io_src1 ^ io_src2; // @[LSU.scala 186:21]
wire sltu = ~adderRes[64]; // @[LSU.scala 187:14]
wire slt = xorRes[63] ^ sltu; // @[LSU.scala 188:28]
wire [63:0] _T_9 = io_src1 & io_src2; // @[LSU.scala 194:32]
wire [63:0] _T_10 = io_src1 | io_src2; // @[LSU.scala 195:32]
wire [63:0] _T_12 = slt ? io_src1 : io_src2; // @[LSU.scala 196:29]
wire [63:0] _T_14 = slt ? io_src2 : io_src1; // @[LSU.scala 197:29]
wire [63:0] _T_16 = sltu ? io_src1 : io_src2; // @[LSU.scala 198:29]
wire [63:0] _T_18 = sltu ? io_src2 : io_src1; // @[LSU.scala 199:29]
wire _T_19 = 6'h22 == io_func[5:0]; // @[Mux.scala 80:60]
wire [64:0] _T_20 = _T_19 ? {{1'd0}, io_src2} : adderRes; // @[Mux.scala 80:57]
wire _T_21 = 6'h24 == io_func[5:0]; // @[Mux.scala 80:60]
wire [64:0] _T_22 = _T_21 ? {{1'd0}, xorRes} : _T_20; // @[Mux.scala 80:57]
wire _T_23 = 6'h25 == io_func[5:0]; // @[Mux.scala 80:60]
wire [64:0] _T_24 = _T_23 ? {{1'd0}, _T_9} : _T_22; // @[Mux.scala 80:57]
wire _T_25 = 6'h26 == io_func[5:0]; // @[Mux.scala 80:60]
wire [64:0] _T_26 = _T_25 ? {{1'd0}, _T_10} : _T_24; // @[Mux.scala 80:57]
wire _T_27 = 6'h37 == io_func[5:0]; // @[Mux.scala 80:60]
wire [64:0] _T_28 = _T_27 ? {{1'd0}, _T_12} : _T_26; // @[Mux.scala 80:57]
wire _T_29 = 6'h30 == io_func[5:0]; // @[Mux.scala 80:60]
wire [64:0] _T_30 = _T_29 ? {{1'd0}, _T_14} : _T_28; // @[Mux.scala 80:57]
wire _T_31 = 6'h31 == io_func[5:0]; // @[Mux.scala 80:60]
wire [64:0] _T_32 = _T_31 ? {{1'd0}, _T_16} : _T_30; // @[Mux.scala 80:57]
wire _T_33 = 6'h32 == io_func[5:0]; // @[Mux.scala 80:60]
wire [64:0] res = _T_33 ? {{1'd0}, _T_18} : _T_32; // @[Mux.scala 80:57]
wire [31:0] _T_37 = res[31] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [63:0] _T_38 = {_T_37, res[31:0]}; // @[Cat.scala 29:58]
assign io_result = io_isWordOp ? _T_38 : res[63:0]; // @[LSU.scala 202:13]
endmodule
| 7.306711 |
module MOU (
input io_in_valid,
input [ 6:0] io_in_bits_func,
input [38:0] io_cfIn_pc,
output [38:0] io_redirect_target,
output io_redirect_valid,
output flushICache_0,
output flushTLB_0
);
wire _T_2 = io_in_bits_func == 7'h1; // @[MOU.scala 52:36]
wire flushICache = io_in_valid & _T_2; // @[MOU.scala 52:27]
wire _T_12 = io_in_bits_func == 7'h2; // @[MOU.scala 56:33]
wire flushTLB = io_in_valid & _T_12; // @[MOU.scala 56:24]
assign io_redirect_target = io_cfIn_pc + 39'h4; // @[MOU.scala 49:22]
assign io_redirect_valid = io_in_valid; // @[MOU.scala 50:21]
assign flushICache_0 = flushICache;
assign flushTLB_0 = flushTLB;
endmodule
| 7.890495 |
module LockingArbiter (
input clock,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input [31:0] io_in_0_bits_addr,
input [ 3:0] io_in_0_bits_cmd,
input [ 7:0] io_in_0_bits_wmask,
input [63:0] io_in_0_bits_wdata,
output io_in_1_ready,
input io_in_1_valid,
input [31:0] io_in_1_bits_addr,
input [ 2:0] io_in_1_bits_size,
input [ 3:0] io_in_1_bits_cmd,
input [ 7:0] io_in_1_bits_wmask,
input [63:0] io_in_1_bits_wdata,
input io_out_ready,
output io_out_valid,
output [31:0] io_out_bits_addr,
output [ 2:0] io_out_bits_size,
output [ 3:0] io_out_bits_cmd,
output [ 7:0] io_out_bits_wmask,
output [63:0] io_out_bits_wdata,
output io_chosen
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [2:0] value; // @[Counter.scala 29:33]
reg _T; // @[Arbiter.scala 46:22]
wire _T_1 = value != 3'h0; // @[Arbiter.scala 47:34]
wire _T_4 = io_out_bits_cmd[0] & io_out_bits_cmd[1]; // @[Crossbar.scala 100:62]
wire _T_5 = io_out_ready & io_out_valid; // @[Decoupled.scala 40:37]
wire _T_6 = _T_5 & _T_4; // @[Arbiter.scala 50:25]
wire [2:0] _T_9 = value + 3'h1; // @[Counter.scala 39:22]
wire choice = io_in_0_valid ? 1'h0 : 1'h1; // @[Arbiter.scala 88:27]
wire _T_10 = ~io_in_0_valid; // @[Arbiter.scala 31:78]
wire _T_11 = ~_T; // @[Arbiter.scala 57:39]
wire _T_12 = _T_1 ? _T_11 : 1'h1; // @[Arbiter.scala 57:22]
wire _T_15 = _T_1 ? _T : _T_10; // @[Arbiter.scala 57:22]
assign io_in_0_ready = _T_12 & io_out_ready; // @[Arbiter.scala 57:16]
assign io_in_1_ready = _T_15 & io_out_ready; // @[Arbiter.scala 57:16]
assign io_out_valid = io_chosen ? io_in_1_valid : io_in_0_valid; // @[Arbiter.scala 41:16]
assign io_out_bits_addr = io_chosen ? io_in_1_bits_addr : io_in_0_bits_addr; // @[Arbiter.scala 42:15]
assign io_out_bits_size = io_chosen ? io_in_1_bits_size : 3'h3; // @[Arbiter.scala 42:15]
assign io_out_bits_cmd = io_chosen ? io_in_1_bits_cmd : io_in_0_bits_cmd; // @[Arbiter.scala 42:15]
assign io_out_bits_wmask = io_chosen ? io_in_1_bits_wmask : io_in_0_bits_wmask; // @[Arbiter.scala 42:15]
assign io_out_bits_wdata = io_chosen ? io_in_1_bits_wdata : io_in_0_bits_wdata; // @[Arbiter.scala 42:15]
assign io_chosen = _T_1 ? _T : choice; // @[Arbiter.scala 40:13 Arbiter.scala 55:31]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
value = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
_T = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
value <= 3'h0;
end else if (_T_6) begin
value <= _T_9;
end
if (_T_6) begin
_T <= io_chosen;
end
end
endmodule
| 8.44302 |
module SimpleBusAddressMapper (
output io_in_req_ready,
input io_in_req_valid,
input [31:0] io_in_req_bits_addr,
input [ 3:0] io_in_req_bits_cmd,
input [63:0] io_in_req_bits_wdata,
output io_in_resp_valid,
output [ 3:0] io_in_resp_bits_cmd,
output [63:0] io_in_resp_bits_rdata,
input io_out_req_ready,
output io_out_req_valid,
output [31:0] io_out_req_bits_addr,
output [ 3:0] io_out_req_bits_cmd,
output [63:0] io_out_req_bits_wdata,
input io_out_resp_valid,
input [ 3:0] io_out_resp_bits_cmd,
input [63:0] io_out_resp_bits_rdata
);
assign io_in_req_ready = io_out_req_ready; // @[AddressMapper.scala 31:10]
assign io_in_resp_valid = io_out_resp_valid; // @[AddressMapper.scala 31:10]
assign io_in_resp_bits_cmd = io_out_resp_bits_cmd; // @[AddressMapper.scala 31:10]
assign io_in_resp_bits_rdata = io_out_resp_bits_rdata; // @[AddressMapper.scala 31:10]
assign io_out_req_valid = io_in_req_valid; // @[AddressMapper.scala 31:10]
assign io_out_req_bits_addr = {
4'h1, io_in_req_bits_addr[27:0]
}; // @[AddressMapper.scala 31:10 AddressMapper.scala 34:26]
assign io_out_req_bits_cmd = io_in_req_bits_cmd; // @[AddressMapper.scala 31:10]
assign io_out_req_bits_wdata = io_in_req_bits_wdata; // @[AddressMapper.scala 31:10]
endmodule
| 6.846243 |
module of the design. It instantiates the
// 'gpif_interface' in it.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Include File
`include "params.v"
module topmod
(
input rst_i,
input clk_i,
// FX3 Interface
// Input Ports
input flaga_i,
input flagb_i,
// Inout Ports
inout [31:0] sldata_io,
// Output Ports
output slclk_o,
output slrd_o,
output sloe_o,
output slwr_o,
output slcs_o,
output pktend_o,
output [ 1:0] sladdr_o
);
// --------------------------------
//
// Local Variables
//
// --------------------------------
wire sl_clk;
wire rstn_slclk;
wire sloe_gen;
wire fx3_clk_o;
wire [31:0] gpif_data_i;
wire [31:0] gpif_data_o;
// Generate Variable
genvar gi;
// --------------------------------
//
// Generate Block
//
// --------------------------------
generate
for ( gi = 0; gi < 32 ; gi = gi + 1)
begin
BB buf7 (.I(gpif_data_o[gi]), .T(sloe_gen), .O(gpif_data_i[gi]), .B(sldata_io[gi]));
end
endgenerate
// --------------------------------
//
// Assignments
//
// --------------------------------
// CS
assign slcs_o = 1'd0;
// Packet End
assign pktend_o = 1'd1;
// Clock to FX3
assign fx3_clk_o = sl_clk;
// --------------------------------
//
// PLL
//
// --------------------------------
pll
pll
(
.pll_ip_CLKI (clk_i), // Reference Clock
.pll_ip_CLKOP (sl_clk) // 100 MHz Out Clock
);
// --------------------------------
//
// Reset Bridge
//
// --------------------------------
rstn_bridge
rstn_bridge
(
.rstn_i (rst_i),
.clk_i (sl_clk),
.rstn_o (rstn_slclk)
);
// --------------------------------
//
// Output Clock Buffer
//
// --------------------------------
OB i_OB_FX_CLOCK ( .I( fx3_clk_o ), .O( slclk_o ) );
// --------------------------------
//
// GPIF Interface Instance
//
// --------------------------------
gpif_interface
gpif_interface
(
.rstn_i (rstn_slclk),
.clk_i (sl_clk),
.en_i (1'd1),
// Slfifo interface signals
.flaga_i (flaga_i),
.flagb_i (flagb_i),
.data_i (gpif_data_i),
.sloe_gen_o (sloe_gen),
.slrd_o (slrd_o),
.sloe_o (sloe_o),
.slwr_o (slwr_o),
.sladdr_o (sladdr_o),
.data_o (gpif_data_o)
);
endmodule
| 8.52834 |
module jtrclr (
input clk,
button,
output button_n
);
reg [3:0] cnt;
always @(posedge clk) begin
if (button == 1'b0) cnt <= 4'h0;
else if (cnt < 4'h8) cnt <= cnt + 4'b1;
end
assign button_n = cnt[3];
endmodule
| 6.815102 |
module signal_edge (
input clk,
button,
output button_edge
);
reg button_r1, button_r2;
always @(posedge clk) begin
button_r1 <= button;
end
always @(posedge clk) begin
button_r2 <= button_r1;
end
assign button_edge = button_r1 & (~button_r2);
endmodule
| 6.590149 |
module for VGA and CPU implementation
// Feature CPU, Timer and VGA blocks
// Instruction in CPU modify colour register in VGA_Wrapper module
// once a second via an interrupt from the Timer
//
// Dependencies: input clock CLK of 50MHz
// Modules: RAM, ROM, CPU, Timer and VGA_Wrapper
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module TopModule1(
CLK,
RESET,
COLOUR_OUT,
HS_OUT,
VS_OUT
);
input CLK;
input RESET;
output [7:0] COLOUR_OUT;
output HS_OUT;
output VS_OUT;
wire [7:0] ROM_DATA;
wire [7:0] ROM_ADDR;
wire [7:0] RAM_BUS_DATA;
wire [7:0] RAM_BUS_ADDR;
wire RAM_BUS_WE;
wire Timer_IRQ;
wire Timer_IRQ_Ack;
wire Mouse_IRQ_Ack; // not connected, used for output bus on CPU
RAM ram0(.CLK(CLK),
.BUS_DATA(RAM_BUS_DATA),
.BUS_ADDR(RAM_BUS_ADDR),
.BUS_WE(RAM_BUS_WE)
);
ROM rom0(.CLK(CLK),
.DATA(ROM_DATA),
.ADDR(ROM_ADDR)
);
CPU cpu0(.CLK(CLK),
.RESET(RESET),
.BUS_DATA(RAM_BUS_DATA),
.BUS_ADDR(RAM_BUS_ADDR),
.BUS_WE(RAM_BUS_WE),
.ROM_ADDRESS(ROM_ADDR),
.ROM_DATA(ROM_DATA),
.BUS_INTERRUPTS_RAISE({Timer_IRQ, 1'b0}),
.BUS_INTERRUPTS_ACK({Timer_IRQ_Ack,Mouse_IRQ_Ack})
);
VGA_Wrapper vga(.CLK(CLK),
.RESET(RESET),
.BUS_ADDR(RAM_BUS_ADDR),
.BUS_DATA(RAM_BUS_DATA),
.BUS_WE(RAM_BUS_WE),
.COLOUR_OUT(COLOUR_OUT),
.HS_OUT(HS_OUT),
.VS_OUT(VS_OUT)
);
Timer timer0(.CLK(CLK),
.RST(RESET),
.BUS_ADDR(RAM_BUS_ADDR),
.BUS_DATA(RAM_BUS_DATA),
.BUS_WE(RAM_BUS_WE),
.BUS_INTERRUPT_ACK(Timer_IRQ_Ack),
.BUS_INTERRUPT_RAISE(Timer_IRQ)
);
endmodule
| 8.679063 |
module: TopModule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TopModule1_tb;
// Inputs
reg CLK;
reg RESET;
reg [1:0] IQR_RAISE;
// Outputs
wire [1:0] IRQ_ACK;
// Instantiate the Unit Under Test (UUT)
TopModule1 uut (
.CLK(CLK),
.RESET(RESET),
.IQR_RAISE(IQR_RAISE),
.IRQ_ACK(IRQ_ACK)
);
initial begin
// Initialize Inputs
CLK = 0;
forever #10 CLK = ~CLK;
end
initial begin
// Initialize Inputs
RESET = 1;
IQR_RAISE = 0;
#30;
RESET = 0;
#30;
//IQR_RAISE = 1; // trigger handler @ 0xFF addr
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.864778 |
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