code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module frame_counter (
input clk,
resetn,
enable,
input [2:0] color_in,
output frame_enable,
output [2:0] color_out
);
reg [3:0] count;
always @(posedge clk) begin
if (!resetn) count <= 4'b0000;
else if (enable == 1'b1) begin
if (count == 4'b1111) count <= 4'b0000;
else count <= count + 1'b1;
end
end
assign frame_enable = (count == 4'b1111) ? 1 : 0;
assign color_out = (count == 4'b1111) ? 3'b000 : color_in;
endmodule
| 6.859338 |
module x_counter (
input resetn,
enable,
direction,
output reg [7:0] x_pos
);
always @(negedge enable, negedge resetn) begin
if (!resetn) x_pos <= 8'd60;
else begin
if (direction) x_pos <= x_pos + 1'b1;
else x_pos <= x_pos - 1'b1;
end
end
endmodule
| 6.671091 |
module y_counter (
input resetn,
enable,
direction,
output reg [6:0] y_pos
);
always @(negedge enable, negedge resetn) begin
if (!resetn) y_pos <= 7'd60;
else begin
if (direction) y_pos <= y_pos + 2'd2;
else y_pos <= y_pos - 2'd2;
end
end
endmodule
| 6.612318 |
module r_v (
input clk,
resetn,
input [6:0] y,
output reg direction
);
always @(posedge clk) begin
if (!resetn) direction <= 0;
else begin
if (direction) begin
if (y + 3 > 7'd107) direction <= 1'b0;
else direction <= 1'b1;
end else begin
if (y - 3 < 7'd12) direction <= 1'b1;
else direction <= 1'b0;
end
end
end
endmodule
| 6.703342 |
module draw (
input clk,
enable,
resetn,
ld_color,
input [7:0] x_in,
input [6:0] y_in,
input [2:0] color_in,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
reg [7:0] x;
reg [6:0] y;
reg [2:0] color;
//reset or load
always @(posedge clk) begin
if (!resetn) begin
x <= 8'b0;
y <= 7'b0;
color <= 3'b0;
end else begin
x <= x_in;
y <= y_in;
if (ld_color) color <= color_in;
end
end
//2x2 pixel block
reg [1:0] counter;
always @(posedge clk) begin
if (!resetn) counter <= 2'b00;
else if (counter == 2'b11) counter <= 2'b00;
else counter <= counter + 1'b1;
end
assign x_out = x + counter[0];
assign y_out = y + counter[1];
assign color_out = color;
// 4x4 pixel block
// reg [3:0] counter;
// always @(posedge clk) begin
// if (!resetn)
// counter <= 4'b0000;
// else if (counter == 4'b1111)
// counter <= 4'b0000;
// else
// counter <= counter + 1'b1;
// end
// assign x_out = x + counter[1:0];
// assign y_out = y + counter[3:2];
// assign color_out = color;
// 1x1 pixel block
// assign x_out = x;
// assign y_out = y;
// assign color_out = color;
endmodule
| 7.396902 |
module process (
input clk,
enable,
resetn,
ld_color,
input [2:0] color_in,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
wire [ 7:0] x_pos;
wire [ 6:0] y_pos;
wire [19:0] count0;
wire [ 3:0] count1;
wire x_direction, y_direction;
wire [2:0] color;
wire delay_enable;
wire frame_enable;
delay_counter d_c (
.clk(clk),
.resetn(resetn),
.enable(enable),
.delay_enable(delay_enable)
);
frame_counter f_c (
.clk(clk),
.resetn(resetn),
.enable(delay_enable),
.color_in(color_in),
.frame_enable(frame_enable),
.color_out(color)
);
x_counter x_c (
.resetn(resetn),
.enable(frame_enable),
.x_pos(x_pos),
.direction(x_direction)
);
y_counter y_c (
.resetn(resetn),
.enable(frame_enable),
.y_pos(y_pos),
.direction(y_direction)
);
r_h register_h (
.clk(clk),
.resetn(resetn),
.x(x_pos),
.direction(x_direction)
);
r_v register_v (
.clk(clk),
.resetn(resetn),
.y(y_pos),
.direction(y_direction)
);
draw data (
.clk(clk),
.enable(enable),
.resetn(resetn),
.ld_color(ld_color),
.x_in(x_pos),
.y_in(y_pos),
.color_in(color),
.x_out(x_out),
.y_out(y_out),
.color_out(color_out)
);
endmodule
| 6.540992 |
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = (~(in1 ^ in2)) ^ in3;
endmodule
| 7.203305 |
module top_module (
input [1:0] A,
input [1:0] B,
output z
);
assign z = (~(A[0] ^ B[0])) & (~(A[1] ^ B[1]));
endmodule
| 7.203305 |
module Two2OneMux #(
parameter Width = 24
) (
input wire [Width-1:0] din0,
input wire [Width-1:0] din1,
input wire sel,
output wire [Width-1:0] dout
);
assign dout = sel ? din1 : din0;
endmodule
| 7.929578 |
module includes a 2-1 SNN(simplest).
//
// Dependencies: Based on synapses, neurons.
//
// Revision:
// Revision 0.01 - File Created
// 0.1 - Synthesis failed because of limited LUTs. We will try to find a LUT-redundent board for snn.
// Additional Comments: This file is just a test file, which doesn't include true SNN for application.
//
//////////////////////////////////////////////////////////////////////////////////
module two2one_snn(
input clk,
input rst,
input en
);
wire output_spikes;
wire [23 : 0] synapses_results1;
wire [23 : 0] synapses_results2;
wire [23 : 0] after_sum;
reg weights_en;
always@(posedge clk) begin
if(rst) weights_en <= 1'b0;
else if (en) weights_en <= en;
end
wire en_for_initweights;
assign en_for_initweights = weights_en ^ en;
synapse syn1 (
.clk(clk), .rst(rst), .en(en),
.weights_w(16'sd2000),.write_enable(en_for_initweights),.pre_spiking(1'b1), //input_spikes[j]
.spking_value(synapses_results1),.update_en(output_spikes),
.learning_rate(16'h0148)
);
synapse syn2 (
.clk(clk), .rst(rst), .en(en),
.weights_w(16'sd2000),.write_enable(en_for_initweights),.pre_spiking(1'b1), //input_spikes[j]
.spking_value(synapses_results2),.update_en(output_spikes),
.learning_rate(16'h0148)
);
assign after_sum = synapses_results1 + synapses_results2;
exc_neuron exc (
clk,rst,en,after_sum,1'b0,output_spikes
);
endmodule
| 6.588012 |
module Two4DigitDisplay (
Clk,
NumberA,
NumberB,
out7,
en_out
);
parameter NUM_WIDTH = 16;
input Clk;
input [15:0] NumberA;
input [15:0] NumberB;
output [6:0] out7; //seg a, b, ... g
output reg [7:0] en_out;
reg [3:0] in4;
// Use for Structural assignment method
wire [3:0] firstdigitA;
wire [3:0] seconddigitA;
wire [3:0] thirddigitA;
wire [3:0] forthdigitA;
wire [3:0] firstdigitB;
wire [3:0] seconddigitB;
wire [3:0] thirddigitB;
wire [3:0] forthdigitB;
/* // Uncomment for Procedural assignment method
wire [3:0] firstdigitA;
wire [3:0] seconddigitA;
wire [3:0] thirddigitA;
wire [3:0] forthdigitA;
wire [3:0] firstdigitB;
wire [3:0] seconddigitB;
wire [3:0] thirddigitB;
wire [3:0] forthdigitB;*/
//--------- --------- --------- --------- //
//-- to use the module SevenSegment
SevenSegment m1 (
in4,
out7
);
//--------- --------- --------- --------- //
//-- divider counter for ~95.3Hz refresh rate (with 100MHz main clock)
reg [19:0] cnt = 19'd0;
always @(posedge Clk) begin
cnt <= cnt + 1;
end
//-- Structural design of digits
//-- Separating bits of number to display in hex format
assign firstdigitA = NumberA[3:0];
assign seconddigitA = NumberA[7:4];
assign thirddigitA = NumberA[11:8];
assign forthdigitA = NumberA[15:12];
assign firstdigitB = NumberB[3:0];
assign seconddigitB = NumberB[7:4];
assign thirddigitB = NumberB[11:8];
assign forthdigitB = NumberB[15:12];
// Procedural assignment alternative
//-- to seperate each decimal digit for display
/*always @(NumberA) begin
if (NumberA < 65535)
begin
firstdigitA <= NumberA%16;
seconddigitA <= (NumberA/16)%16;
thirddigitA <= (NumberA/256)%16;
forthdigitA <= NumberA/4096;
end
else
begin
firstdigitA <= 4'b1111;
seconddigitA <= 4'b1111;
thirddigitA <= 4'b1111;
forthdigitA <= 4'b1111;
end
end
always @(NumberB) begin
if (NumberB < 65535)
begin
firstdigitB <= NumberB%16;
seconddigitB <= (NumberB/16)%16;
thirddigitB <= (NumberB/256)%16;
forthdigitB <= NumberB/4096;
end
else
begin
firstdigitB <= 4'b1111;
seconddigitB <= 4'b1111;
thirddigitB <= 4'b1111;
forthdigitB <= 4'b1111;
end
end */
//-- to display the number in the appropriate 7-segment digit
always @(cnt) begin
case (cnt[19:17]) //100MHz/(2^20) = 95.3 Hz
3'b000: begin
en_out <= 8'b11111110;
in4 <= firstdigitA;
end
3'b001: begin
en_out <= 8'b11111101;
in4 <= seconddigitA;
end
3'b010: begin
en_out <= 8'b11111011;
in4 <= thirddigitA;
end
3'b011: begin
en_out <= 8'b11110111;
in4 <= forthdigitA;
end
3'b100: begin
en_out <= 8'b11101111;
in4 <= firstdigitB;
end
3'b101: begin
en_out <= 8'b11011111;
in4 <= seconddigitB;
end
3'b110: begin
en_out <= 8'b10111111;
in4 <= thirddigitB;
end
3'b111: begin
en_out <= 8'b01111111;
in4 <= forthdigitB;
end
default: begin
en_out <= 8'b11111111;
in4 <= 4'b1111;
end
endcase
end
endmodule
| 7.958996 |
module TWOadder (
input [31:0] A,
B,
input clk,
rst,
output [31:0] W,
output [31:0] AA,
BB,
output reg [7:0] Aadd,
Badd,
output [1:0] gout,
output cout
);
reg cin, en1, en2, en3, en4;
wire coutadd, en;
wire [7:0] S;
assign en = cout;
always @(*) begin
case (gout)
2'b00: Aadd <= AA[7:0];
2'b01: Aadd <= AA[15:8];
2'b10: Aadd <= AA[23:16];
2'b11: Aadd <= AA[31:24];
default Aadd <= 8'b0;
endcase
case (gout)
2'b00: Badd <= BB[7:0];
2'b01: Badd <= BB[15:8];
2'b10: Badd <= BB[23:16];
2'b11: Badd <= BB[31:24];
default Badd <= 8'b0;
endcase
case (gout)
2'b00: begin
en1 = 1;
en2 = 0;
en3 = 0;
en4 = 0;
end
2'b01: en1 <= 0 && en2 <= 1 && en3 <= 0 && en4 <= 0;
2'b10: en1 <= 0 && en2 <= 0 && en3 <= 1 && en4 <= 0;
2'b11: en1 <= 0 && en2 <= 0 && en3 <= 0 && en4 <= 1;
default begin
Aadd <= 8'b0;
en1 <= 0;
end
endcase
if (rst) cin <= 1'b0;
else cin <= coutadd;
end
genvar j;
generate
for (j = 0; j <= 31; j = j + 8) begin : row
regmaster Num1 (
A[j+7:j],
clk,
rst,
en,
AA[j+7:j]
);
end
endgenerate
genvar i;
generate
for (i = 0; i <= 31; i = i + 8)
regmaster Num1 (
B[i+7:i],
clk,
rst,
en,
BB[i+7:i]
);
endgenerate
ONEadder Num2 (
Aadd,
Badd,
cin,
rst,
S,
coutadd
);
regmaster Num3 (
S,
clk,
rst,
en1,
W[7:0]
);
regmaster Num4 (
S,
clk,
rst,
en2,
W[15:8]
);
regmaster Num5 (
S,
clk,
rst,
en3,
W[23:16]
);
regmaster Num6 (
S,
clk,
rst,
en4,
W[31:24]
);
TWOcounter Num7 (
clk,
rst,
gout,
cout
);
endmodule
| 6.832364 |
module makes up the leaves of the leading zero detecting tree generated by lzdetector
//given its short length, it should probably simply be incorparted into lzdetector in the length==2 case
module twobitlzd(
output wire p,
output wire v,
input wire a,
input wire b
);
assign p = (!a)&b;
assign v = a|b;
endmodule
| 7.27518 |
module twoBitMuti (
input [1:0] A,
input [1:0] B,
output [3:0] PRO
);
assign PRO[3] = B[1] & B[0] & A[1] & A[0];
assign PRO[2] = A[1] & B[1] & (~A[0] | ~B[0]);
assign PRO[1] = A[1] & B[1] & (A[0] ^ B[0]) | ~B[1] & B[0] & A[1] | ~A[1] & A[0] & B[1];
assign PRO[0] = A[0] & B[0];
endmodule
| 7.072617 |
module TwoBitSaturationPredictor (
input clk,
input reset_n,
input [`WORD_SIZE-1:0] PC,
input JumpResolved,
BranchResolved,
BranchTaken,
input [`WORD_SIZE-1:0] ResolvedJumpPC,
ResolvedBranchPC,
input [`WORD_SIZE-1:0] ActualJumpTarget,
ActualBranchTarget,
output [`WORD_SIZE-1:0] Prediction
);
/*
[Two Bit Saturation branch predictor module]
Functionality:
8 bit tag
8 bit BTB index
2 bit BHT saturation counter
Only branch and jump instructions are stored in the BTB.
Inputs:
PC : Address of the current instruction. We should predict its outcome.
BranchTaken : Whether the resolved branch was taken
ResolvedJumpPC : address of the jump instruction resolved this cycle (ID stage)
ResolvedBranchPC : address of the branch instruction resolved this cycle (EX stage)
ActualJumpTarget : The actual destination of the jump instruction resolved this cycle.
ActualBranchTarget: The actual destination of the branch instruction resolved this cycle.
Outputs:
Prediction : Predicted nextPC of the current instruction.
*/
integer i;
reg [`WORD_SIZE-1:0] BTB[`BTB_SIZE-1:0];
reg [7:0] TagTable[`BTB_SIZE-1:0];
reg [1:0] Counter[`BTB_SIZE-1:0];
wire PredictTaken;
// Store the last two prediction history
reg [1:0] PredictionHistory;
always @(posedge clk) begin
if (!reset_n) begin // Synchronous active-low reset
for (i = 0; i < `BTB_SIZE; i = i + 1) begin
BTB[i] <= 0;
TagTable[i] <= 8'hff;
Counter[i] <= 1;
end
PredictionHistory <= 2'b00;
end else begin // Prediction history shift register
PredictionHistory <= {PredictionHistory[1], PredictTaken};
end
end
// Branch prediction logic
assign PredictTaken = (TagTable[PC[`IDX_SIZE-1:0]] == PC[`WORD_SIZE-1:`IDX_SIZE]) && (Counter[PC[`IDX_SIZE-1:0]] >= 2);
assign Prediction = PredictTaken ? BTB[PC[`IDX_SIZE-1:0]] : PC + 1;
// Updating predictor based on the actual outcome of control instructions
always @(negedge clk) begin
if (BranchResolved) begin // In EX stage
if (BranchTaken) begin // Branch taken
if (Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] != 3) begin
Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] <= Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] + 1;
end
end else begin // Branch not taken
if (Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] != 0) begin
Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] <= Counter[ResolvedBranchPC[`IDX_SIZE-1:0]] - 1;
end
end
TagTable[ResolvedBranchPC[`IDX_SIZE-1:0]] <= ResolvedBranchPC[`WORD_SIZE-1:`IDX_SIZE];
BTB[ResolvedBranchPC[`IDX_SIZE-1:0]] <= ActualBranchTarget;
end
if (JumpResolved) begin
// If there was a branch resolution in the EX stage, its prediction should have been correct to ensure the execution of the jump in the ID stage.
// Or else, no branch resolution in the EX stage.
if ((BranchResolved && (BranchTaken == PredictionHistory[1])) || !BranchResolved) begin
if (Counter[ResolvedJumpPC[`IDX_SIZE-1:0]] != 3) begin
Counter[ResolvedJumpPC[`IDX_SIZE-1:0]] <= Counter[ResolvedJumpPC[`IDX_SIZE-1:0]] + 1;
end
TagTable[ResolvedJumpPC[`IDX_SIZE-1:0]] <= ResolvedJumpPC[`WORD_SIZE-1:`IDX_SIZE];
BTB[ResolvedJumpPC[`IDX_SIZE-1:0]] <= ActualJumpTarget;
end
end
end
endmodule
| 9.538702 |
module TwoBitShift (
output data_out,
input data_in
);
assign data_out = data_in << 2;
endmodule
| 8.44379 |
module twobitshifter (
inp,
out
);
input [31:0] inp;
output reg [31:0] out;
always @(inp) out = inp * 4;
endmodule
| 6.578081 |
module top_module (
input [1:0] A,
input [1:0] B,
output z
);
assign z = A == B;
endmodule
| 7.203305 |
module represents a two by one mux.
**********************************************************************/
`timescale 1ns / 1ps
module twobyoneMUX(
input [31:0] A, [31:0] B, input S, output [31:0] c
);
genvar i;
generate
for(i=0; i<32; i=i+1)begin: myblock
mux_2x1 mux(A[i] , B[i] , S, c[i]);
end
endgenerate
endmodule
| 7.311982 |
module
// Find additive inverse
//
// License: MIT
//
////////////////////////////////////////////////////////////////////////
`default_nettype None
`timescale 1ns/1ps
module twoComplementer #(parameter N = 4) (output wire[N-1:0] twoComp, input[N-1:0] in);
wire[N:0] total;
assign total = ~in+1;
assign twoComp = total[N-1:0];
endmodule
| 7.423624 |
module TwoDigitDisplay (
Clk,
Number,
out7,
en_out
);
input Clk;
input [6:0] Number;
output [6:0] out7; //seg a, b, ... g
output reg [7:0] en_out;
reg [3:0] in4;
reg [3:0] firstdigit;
reg [3:0] seconddigit;
//--------- --------- --------- --------- //
//-- to use the module SevenSegment
SevenSegment m1 (
in4,
out7
);
//--------- --------- --------- --------- //
//-- divider counter for ~95.3Hz refresh rate (with 100MHz main clock)
reg [19:0] cnt;
always @(posedge Clk) begin
cnt <= cnt + 1;
end
//-- to seperate each decimal digit for display
always @(Number) begin
if (Number < 100) begin
firstdigit <= Number % 10;
seconddigit <= Number / 10;
end else begin
firstdigit <= 4'b1111;
seconddigit <= 4'b1111;
end
end
//-- to display the number in the appropriate 7-segment digit
always @(cnt) begin
case (cnt[19:17]) //100MHz/(2^20) = 95.3 Hz
3'b000: begin
en_out <= 8'b11111110;
in4 <= firstdigit;
end
3'b001: begin
en_out <= 8'b11111101;
in4 <= seconddigit;
end
//can be used if need to display more than 2 digits
//3'b010: begin en_out <= 8'b11111011;
//3'b011: begin en_out <= 8'b11110111;
//3'b100: begin en_out <= 8'b11101111;
//3'b101: begin en_out <= 8'b11011111;
//3'b110: begin en_out <= 8'b10111111;
//3'b111: begin en_out <= 8'b01111111;
default: begin
en_out <= 8'b11111111;
in4 <= 4'b1111;
end
endcase
end
endmodule
| 8.113622 |
module twodigits (
data,
leds
);
input [6:0] data;
output [13:0] leds;
reg [3:0] digit0, digit1;
initial begin
digit0 = 0;
digit1 = 0;
end
sevenseg led0 (
digit0,
leds[6:0]
);
sevenseg led1 (
digit1,
leds[13:7]
);
always @(data) begin
digit1 = data / 10;
digit0 = data - data / 10 * 10;
end
endmodule
| 6.602591 |
module twoDint_counter32A;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("twoDint_counter32A.vcd");
$dumpvars(0, twoDint_counter32A);
end
////// test bench
//////////////////////////////
////// circuit under test
wire [32:0] carrycomp;
wire [31:0] sumcomp;
wire [1:0] sum[31:0];
wire [1:0] carry[32:0];
genvar i;
// 4 stage pipeline
THnotN u0 (
carry[0][1],
carrycomp[0],
init
); // auto produce carryin
assign carry[0][0] = 1'b0; // auto produce carryin
// two D digit pipelined counter
for (i = 0; i < 32; i = i + 1) begin
twoDint_counter_ringA ci (
sum[i][1:0],
sumcomp[i],
carry[i+1][1:0],
carrycomp[i+1],
carry[i][1:0],
carrycomp[i],
init
);
TH12 u3 (
sumcomp[i],
sum[i][1],
sum[i][0]
); // auto consume sum
end
TH12 u33 (
carrycomp[32],
carry[32][0],
carry[32][1]
); // auto consume carryout
////// circuit under test
//////////////////////////////
////// test bench
wire [63:0] displaysum;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
assign displaysum[2*k+1] = sum[k][1];
assign displaysum[2*k] = sum[k][0];
end
endmodule
| 6.630717 |
module twoDint_counter32C;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("twoDint_counter32C.vcd");
$dumpvars(0, twoDint_counter32C);
end
////// test bench
//////////////////////////////
////// circuit under test
wire [32:0] carrycomp;
wire [31:0] sumcomp;
wire [1:0] sum[31:0];
wire [1:0] carry[32:0];
genvar i;
// 4 stage pipeline
THnotN u0 (
carry[0][1],
carrycomp[0],
init
); // auto produce carryin
assign carry[0][0] = 1'b0; // auto produce carryin
// two D digit pipelined counter
for (i = 0; i < 32; i = i + 1) begin
twoDint_counter_ringC ci (
sum[i][1:0],
sumcomp[i],
carry[i+1][1:0],
carrycomp[i+1],
carry[i][1:0],
carrycomp[i],
init
);
TH12 u3 (
sumcomp[i],
sum[i][1],
sum[i][0]
); // auto consume sum
end
TH12 u33 (
carrycomp[32],
carry[32][0],
carry[32][1]
); // auto consume carryout
////// circuit under test
//////////////////////////////
////// test bench
wire [63:0] displaysum;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
assign displaysum[2*k+1] = sum[k][1];
assign displaysum[2*k] = sum[k][0];
end
endmodule
| 6.630717 |
module twoDint_counter_ringA (
output wire [1:0] sum,
input sumCOMP,
output wire [1:0] carryout,
input carryoutCOMP,
input [1:0] carryin,
output carryinCOMP,
input init
);
wire [1:0] A;
wire [1:0] B;
wire [1:0] C;
wire [1:0] D;
wire ACOMP, BCOMP, CCOMP, DCOMP, CCOMP2;
// 4 stage ring with halfadder
Pipecomponent2N u1 (
B,
BCOMP,
A,
ACOMP,
init
);
halfadd u2 (
C,
CCOMP2,
carryout,
carryoutCOMP,
B,
BCOMP,
carryin,
carryinCOMP,
init
);
TH22 u5 (
CCOMP2,
CCOMP,
sumCOMP
);
assign sum = C;
Pipecomponent2 u3 (
D,
DCOMP,
C,
CCOMP,
init
);
Pipecomponent2D u4 (
A,
ACOMP,
D,
DCOMP,
init
);
endmodule
| 6.630717 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module twoDint_counter_ringC (
output wire [1:0] sum,
input sumCOMP,
output wire [1:0] carryout,
input carryoutCOMP,
input [1:0] carryin,
output carryinCOMP,
input init
);
wire [1:0] A;
wire [1:0] B;
wire [1:0] C;
wire [1:0] D;
wire ACOMP, BCOMP, CCOMP, DCOMP, CCOMP2;
// 4 stage ring with halfadder
Pipecomponent2N u1 (
B,
BCOMP,
A,
ACOMP,
init
);
halfadd u2 (
C,
CCOMP2,
carryout,
carryoutCOMP,
B,
BCOMP,
carryin,
carryinCOMP,
init
);
TH22 u5 (
CCOMP2,
CCOMP,
sumCOMP
);
assign sum = C;
Pipecomponent2 u3 (
D,
DCOMP,
C,
CCOMP,
init
);
Pipecomponent2D u4 (
A,
ACOMP,
D,
DCOMP,
init
);
endmodule
| 6.630717 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module twoD_counter32A;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("twoD_counter32A.vcd");
$dumpvars(0, twoD_counter32A);
end
////// test bench
//////////////////////////////
////// circuit under test
wire [32:0] carrycomp;
wire [31:0] sumcomp;
wire [1:0] sum[31:0];
wire [1:0] carry[32:0];
genvar i;
// 4 stage pipeline
THnotN u0 (
carry[0][1],
carrycomp[0],
init
); // auto produce carryin
assign carry[0][0] = 1'b0; // auto produce carryin
// two D digit pipelined counter
for (i = 0; i < 32; i = i + 1) begin
twoD_counter_ringA ci (
sum[i][1:0],
sumcomp[i],
carry[i+1][1:0],
carrycomp[i+1],
carry[i][1:0],
carrycomp[i],
init
);
TH12 u3 (
sumcomp[i],
sum[i][1],
sum[i][0]
); // auto consume sum
end
TH12 u33 (
carrycomp[32],
carry[32][0],
carry[32][1]
); // auto consume carryout
////// circuit under test
//////////////////////////////
////// test bench
wire [63:0] displaysum;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
assign displaysum[2*k+1] = sum[k][1];
assign displaysum[2*k] = sum[k][0];
end
endmodule
| 6.636592 |
module twoD_counter32B;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("twoD_counter32B.vcd");
$dumpvars(0, twoD_counter32B);
end
////// test bench
//////////////////////////////
////// circuit under test
wire [32:0] countcomp;
wire [31:0] sumcomp;
wire [1:0] sum[31:0];
wire [1:0] carry[32:0];
genvar i;
// 4 stage pipeline
THnotN u0 (
carry[0][1],
countcomp[0],
init
); // auto produce carryin
assign carry[0][0] = 1'b0; // auto produce carryin
// two D digit pipelined counter
for (i = 0; i < 32; i = i + 1) begin
twoD_counter_ringB ci (
sum[i][1:0],
carry[i+1][1:0],
sumcomp[i],
countcomp[i+1],
carry[i][1:0],
countcomp[i],
init
);
TH12 u3 (
sumcomp[i],
sum[i][1],
sum[i][0]
); // auto consume sum
end
TH12 u33 (
countcomp[32],
carry[32][0],
carry[32][1]
); // auto consume carryout
////// circuit under test
//////////////////////////////
////// test bench
wire [63:0] displaysum;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
assign displaysum[2*k+1] = sum[k][1];
assign displaysum[2*k] = sum[k][0];
end
endmodule
| 6.636592 |
module twoD_counter32C;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("twoD_counter32C.vcd");
$dumpvars(0, twoD_counter32C);
end
////// test bench
//////////////////////////////
////// circuit under test
wire [32:0] carrycomp;
wire [31:0] sumcomp;
wire [1:0] sum[31:0];
wire [1:0] carry[32:0];
genvar i;
// 4 stage pipeline
THnotN u0 (
carry[0][1],
carrycomp[0],
init
); // auto produce carryin
assign carry[0][0] = 1'b0; // auto produce carryin
// two D digit pipelined counter
for (i = 0; i < 32; i = i + 1) begin
twoD_counter_ringC ci (
sum[i][1:0],
sumcomp[i],
carry[i+1][1:0],
carrycomp[i+1],
carry[i][1:0],
carrycomp[i],
init
);
TH12 u3 (
sumcomp[i],
sum[i][1],
sum[i][0]
); // auto consume sum
end
TH12 u33 (
carrycomp[32],
carry[32][0],
carry[32][1]
); // auto consume carryout
////// circuit under test
//////////////////////////////
////// test bench
wire [63:0] displaysum;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
assign displaysum[2*k+1] = sum[k][1];
assign displaysum[2*k] = sum[k][0];
end
endmodule
| 6.636592 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 (
ACOMP,
Z[0],
Z[1]
);
endmodule
| 7.182889 |
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = ~(in1 ^ in2) ^ in3;
endmodule
| 7.203305 |
module BitTwoInOneSelector32Bit (
input [31:0] ZeroInput,
input [31:0] OneInput,
input Control,
output reg [31:0] DataOutput
);
always @(Control or ZeroInput or OneInput) begin
DataOutput = (Control == 1) ? OneInput : ZeroInput;
end
endmodule
| 7.803437 |
module TwoInOneSelector5Bit (
input [4:0] ZeroInput,
input [4:0] OneInput,
input Control,
output reg [4:0] DataOutput
);
always @(Control or ZeroInput or OneInput) begin
DataOutput = (Control == 1) ? OneInput : ZeroInput;
end
endmodule
| 6.849886 |
module twoMultAdd (
W,
X,
U,
h,
b,
out
);
// incoming data signed and fixed width
parameter DATA_WIDTH = 16;
parameter FRACT_WIDTH = 8;
input signed [DATA_WIDTH-1:0] W, X, U, h, b;
output wire [DATA_WIDTH-1:0] out;
// internal regs/wires
wire [DATA_WIDTH+FRACT_WIDTH-1:0] p1, p2;
// behavior: out = W*X + U*h + b
assign p1 = (W * X) >> FRACT_WIDTH;
assign p2 = (U * h) >> FRACT_WIDTH;
assign out = p1 + p2 + b;
endmodule
| 8.381371 |
module twoniv (
output z,
input a,
input sys_clk
);
/*reg r_z = 1'b0;
assign z = r_z;
always @(posedge sys_clk)
begin
r_z <= a;
end*/
assign z = a;
endmodule
| 7.033744 |
module twoPortMem (
writeAddress,
writeClk,
writeEnable,
writeData,
readAddress,
readClk,
readEnable,
readData);
//user defined
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
parameter writeMask = 1;
//Auto-calculated, user dont touch
localparam addressWidth =$clog2(addresses);
input [addressWidth-1:0] writeAddress;
input writeClk;
input [writeMask-1:0] writeEnable;
input [width-1:0] writeData;
input [addressWidth-1:0] readAddress;
input readClk;
input readEnable;
output [width-1:0] readData;
generate
if((addresses==0)&&(width==0))
begin
initial
begin
$display("FAIL!! :%m:Parameters, addresses and width can not be set to 0");
$stop;
end
end
`include "scriptGeneratedListOfVendorTwoPortMems.vh"
else
begin
twoPortMemSim #(.addresses (addresses),
.width (width),
.muxFactor (muxFactor),
.writeMask (writeMask)
) mem (.writeAddress(writeAddress),
.writeClk(writeClk),
.writeEnable(writeEnable),
.writeData(writeData),
.readAddress(readAddress),
.readClk(readClk),
.readEnable(readEnable),
.readData(readData));
end
endgenerate
endmodule
| 9.238624 |
module twoPortMemSim (
writeAddress,
writeClk,
writeEnable,
writeData,
readAddress,
readClk,
readEnable,
readData
);
//user defined
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
parameter writeMask = 1;
//Auto-calculated, user dont touch
localparam addressWidth = $clog2(addresses);
input [addressWidth-1:0] writeAddress;
input writeClk;
input [writeMask-1:0] writeEnable;
input [width-1:0] writeData;
input [addressWidth-1:0] readAddress;
input readClk;
input readEnable;
output [width-1:0] readData;
reg [width-1:0] mem [addresses-1:0];
reg [width-1:0] readData;
integer i;
initial begin
$display("%m : simulation model of memory");
end
always @(posedge writeClk) begin
if (writeEnable != 0) begin
if (writeMask == 1) begin
mem[writeAddress] <= writeData;
end else begin
for (i = 0; i < writeMask; i = i + 1)
if (writeEnable[i] == 1) mem[writeAddress][i] <= writeData[i];
end
end
end
always @(posedge writeClk) begin
if (readEnable) begin
readData <= mem[readAddress];
end
end
endmodule
| 9.26883 |
module TwoPort_SRAM (
CLKA,
CENA,
AA,
QA,
CLKB,
CENB,
WENB,
AB,
DB
);
//parameters
parameter ADDR_BITS = 13;
parameter MEM_SIZE = 8192;
input CLKA, CLKB;
input CENA, CENB;
input WENB;
input [ADDR_BITS-1:0] AA, AB;
input [`INTERNAL_BITS-1:0] DB;
output [`INTERNAL_BITS-1:0] QA;
reg [`INTERNAL_BITS-1:0] Memory[0:MEM_SIZE-1];
reg [`INTERNAL_BITS-1:0] QA;
//Port A read only
always @(posedge CLKA) begin
if (CENA) QA <= Memory[AA];
else;
end
//Port B write only
always @(posedge CLKB) begin
if (CENB) begin
if (WENB) Memory[AB] <= DB;
else;
end else;
end
endmodule
| 7.376651 |
module TwoPort_SRAM_tb;
//parameters
parameter ADDR_BITS = 13;
//inputs
reg CLK;
reg CENA, CENB;
reg WENB;
reg [ADDR_BITS-1:0] AA, AB;
reg [`INTERNAL_BITS-1:0] DB;
//outputs
wire [`INTERNAL_BITS-1:0] QA;
TwoPort_SRAM TS (
.CLKA(CLK),
.CLKB(CLK),
.CENA(CENA),
.CENB(CENB),
.WENB(WENB),
.AA (AA),
.AB (AB),
.DB (DB),
.QA (QA)
);
initial CLK = 0;
always #(`CYCLE / 2) CLK = ~CLK;
integer i;
initial begin
for (i = 0; i < 100; i = i + 1) TS.Memory[i] = i;
CENA = 1;
CENB = 1;
WENB = 0;
AA = 0;
AB = 0;
DB = 0;
//read test
for (i = 0; i < 100; i = i + 1) #(`CYCLE) AA = i;
//write test
for (i = 0; i < 100; i = i + 1) begin
#(`CYCLE) AB = i;
DB = 100 - i;
WENB = 1;
end
//read test
#(`CYCLE) WENB = 0;
for (i = 0; i < 100; i = i + 1) #(`CYCLE) AA = i;
#(`CYCLE) $finish;
end
initial begin
`ifdef FSDB
$fsdbDumpfile("TwoPort_SRAM.fsdb");
$fsdbDumpvars(0, TS, "+struct");
`endif
end
endmodule
| 6.767807 |
module my_reg (
input clka,
input clkb,
input a_d,
b_d,
output reg a_q,
b_q
);
initial a_q = 0;
always @(posedge clka) a_q <= a_d;
//cover property ((a_q == 1) && (a_d == 0));
always @(negedge clkb) b_q <= b_d;
endmodule
| 7.230814 |
module TwosComplement #(
parameter N = 8
) (
input [N-1:0] A,
output [N-1:0] O
);
ADD #(
.N(N)
) ADD (
.A (~A),
.B ({N{1'b0}}),
.CI(1'b1),
.S (O),
.CO()
);
endmodule
| 8.45255 |
module complement_16bit (
a,
a_complement
);
input [15:0] a;
output wire [15:0] a_complement;
assign a_complement = {1'b1, 16'b0} - a;
endmodule
| 7.32668 |
module complement_19bit (
a,
a_complement
);
input [18:0] a;
output wire [18:0] a_complement;
assign a_complement = {1'b1, 19'b0} - a;
endmodule
| 6.582878 |
module complement_9bit (
a,
a_complement
);
input [8:0] a;
output wire [9:0] a_complement;
assign a_complement = {1'b1, 9'b0} - {1'b0, a};
endmodule
| 6.889491 |
module twoscompliment (
clk,
reset,
a,
out
);
parameter width = 32;
input clk, reset;
input [width-1:0] a;
output reg [width-1:0] out;
//reg [width-1:0] y;
always @(posedge clk) begin
if (reset) out = 32'b0;
else out = (~a) + 1;
end
//assign out =y;
endmodule
| 7.505089 |
module twoseconds (
input clk,
input rst,
input [11:0] ad, //from adc
input flag, //from adc
output reg convert, //to adc
output reg [11:0] num //to seg
);
parameter cnt_top = 21'd1999999;
//parameter cnt_top=21'd1000;
//generate 2s period
reg [20:0] cnt;
always @(posedge clk or posedge rst) begin
if (rst) cnt <= 0;
else if (cnt == cnt_top) cnt <= 0;
else cnt <= cnt + 21'b1;
end
//flag catch and read permission
reg flag_catch;
reg read_permission;
always @(posedge clk or posedge rst) begin
if (rst) flag_catch <= 0;
else flag_catch <= flag;
end
always @(posedge clk or posedge rst) begin
if (rst) read_permission <= 0;
else if (flag_catch != flag && flag) read_permission <= 1;
else read_permission <= 0;
end
//convert
reg [4:0] convert_cnt;
always @(posedge clk or posedge rst) begin
if (rst) begin
convert_cnt <= 5'b0;
end else if (convert_cnt != 5'b11111) convert_cnt <= convert_cnt + 5'b1;
else convert_cnt <= 0;
end
always @(*) begin
if (convert_cnt == 5'b11111) convert = 1;
else convert = 0;
end
//num temp from adc and one_num_flag
reg [3:0] num_temp;
reg [1:0] one_num_flag;
always @(posedge clk or posedge rst) begin
if (rst) begin
num_temp <= 4'b0;
one_num_flag <= 2'b0;
end else if (read_permission) begin
num_temp <= {num_temp[2:0], ad[0]};
if (one_num_flag == 2'b11) one_num_flag <= 2'b00;
else one_num_flag <= one_num_flag + 2'b1;
end
end
//write_permission and num_temp_3
reg [11:0] num_temp_3;
reg write_permission;
reg [1:0] one_num_flag_catch;
always @(posedge clk or posedge rst) begin
if (rst) one_num_flag_catch <= 2'b0;
else one_num_flag_catch <= one_num_flag;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
write_permission <= 0;
end else begin
if (one_num_flag_catch == 2'b11 && one_num_flag == 2'b00) write_permission <= 1;
else write_permission <= 0;
end
end
always @(posedge clk or posedge rst) begin
if (rst) num_temp_3 <= 12'b0;
else if (write_permission && num_temp <= 4'd9)
num_temp_3[11:0] <= {num_temp_3[7:0], num_temp[3:0]};
end
//num print
always @(posedge clk or posedge rst) begin
if (rst) num = 12'b0;
else begin
if (cnt == cnt_top) num[11:0] <= num_temp_3[11:0];
end
end
endmodule
| 7.297404 |
module twoComp (
in,
out
);
input [4:0] in;
wire [4:0] semiOUT;
output [4:0] out;
assign semiOUT = ~in;
bit4Adder(
semiOUT, 5'b00001, out
);
endmodule
| 7.614959 |
module bit4Adder (
in1,
in2,
out
);
input [4:0] in1;
input [4:0] in2;
output [4:0] out;
wire c12, c23, c34, c45;
wire useless;
//assign out=5'b11111;
fullAdder bit1 (
in1[0],
in2[0],
1'b0,
out[0],
c12
);
fullAdder bit2 (
in1[1],
in2[1],
c12,
out[1],
c23
);
fullAdder bit3 (
in1[2],
in2[2],
c23,
out[2],
c34
);
fullAdder bit4 (
in1[3],
in2[3],
c34,
out[3],
c45
);
fullAdder bit5 (
in1[4],
in2[4],
c45,
out[4],
useless
);
endmodule
| 7.261018 |
module definition
module twos_complement_converter( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg state;
reg outp;
//total number of states = 2
parameter S0 = 0, S1 = 1;
always @( posedge clk, posedge rst ) begin
//start state is S0
if( rst ) begin
state <= S0;
outp <= 0;
end
else begin
case( state )
S0: begin
if( inp ) begin
state <= S1;
outp <= 1;
end
else begin
state <= S0;
outp <= 0;
end
end
S1: begin
if( inp ) begin
state <= S1;
outp <= 0;
end
else begin
state <= S1;
outp <= 1;
end
end
endcase
end
end
endmodule
| 6.923011 |
module twos_Compliment (
input [31 : 0] in,
output [31 : 0] out
);
assign out = (~in + 1);
endmodule
| 7.383534 |
module test;
// Registers
reg clk;
reg en;
reg [7:0] A;
wire [7:0] Output; // The read data
wire ready;
// Initialize varibles
initial begin
#1 en = 0;
A = 8'd12;
clk = 0;
#2 en = 1;
#10 en = 0;
#15 $finish;
end
// Monitoring the output
always @(clk) begin
if ($time % 2 != 0) begin
$display("\ntime=%8d\ten=%d\tclk=%d", $time, en, clk);
end
end
// Some module
// Calling the module
twos_compliment TWO (
.clk(clk),
.en(en),
.A(A),
.ready(ready),
.Output(Output)
);
//For the clock
always begin
#1 clk = !clk;
end
endmodule
| 6.888292 |
module twos_to_sign_mag (
in,
out,
sign
);
input [11:0] in;
output [11:0] out;
output sign;
assign sign = in[11];
assign out = (in[11] == 1) ? ~in + 1'b1 : in;
endmodule
| 7.573 |
module TwoToFourDecoder (
input a,
input b,
output q0,
output q1,
output q2,
output q3
);
and (q0, ~a, ~b);
and (q1, ~a, b);
and (q2, a, ~b);
and (q3, a, b);
endmodule
| 7.158165 |
module TwoToOne (
input select,
input [31:0] A,
input [31:0] B,
output wire [31:0] out
);
assign out = (select == 1) ? B : A;
endmodule
| 8.033965 |
module TwoToOneMux #(
parameter integer RV_BIT_NUM_TWO = `RV_BIT_NUM_TWO)
(
input [`MUX_WIDTH_TWO-1:0] sel,
input [(RV_BIT_NUM_TWO*`MUX_OPTION_TWO)-1 : 0] d,
output reg [RV_BIT_NUM_TWO-1:0]q);
always@(*) begin
case( sel )
`muxcasetwo(`MUX_WIDTH_TWO'd0,0)
`muxcasetwo(`MUX_WIDTH_TWO'd1,1)
default: q = `RV_BIT_NUM_TWO'd0;
endcase
end
endmodule
| 7.193575 |
module mux2_to_1 (
out,
i0,
i1,
s0
);
output out;
input i0, i1, s0;
reg out;
wire i0, i1, s0;
always @(s0 or i0 or i1) begin
if (s0 == 0) out = i0;
else out = i1;
end
endmodule
| 6.888021 |
module twoway_16bit_mux (
in0,
in1,
sel,
out
);
input sel;
input [15:0] in0, in1;
output reg [15:0] out;
always @(*)
case (sel)
'd0: out = in0;
default out = in1;
endcase
endmodule
| 7.014625 |
module enc4to2 (
ENCout,
FLAG,
ENCin,
EN
);
// Declaration of the input-output
input [3:0] ENCin;
input EN;
output reg [1:0] ENCout;
output FLAG;
assign FLAG = ENCin >= 1 ? 1 : 0;
always @(ENCin) begin
if (EN == 0)
casex (ENCin)
4'b1xxx: ENCout = 3;
4'b01xx: ENCout = 2;
4'b001x: ENCout = 1;
4'b0001: ENCout = 0;
default: begin
ENCout = 2'bxx;
end
endcase
else ENCout = 0;
end
endmodule
| 6.844155 |
module dec2to4 (
DECout,
DECin,
EN
);
// declarations of inputs, outputs, & registers;
input [1:0] DECin;
input EN;
integer i = 0;
output reg [3:0] DECout;
always @(DECin or EN) begin
for (i = 0; i <= 3; i = i + 1)
if ((DECin == i) && (EN)) DECout[i] = 1;
else DECout[i] = 0;
end
endmodule
| 7.443137 |
module twowire_dtm_connect_monitor (
input wire dck,
input wire drst_n,
input wire di_q,
input wire [3:0] mdropaddr,
output wire connect_now,
input wire connected
);
localparam LFSR_TAPS = 6'h30;
localparam LFSR_INIT = 6'h29;
reg [5:0] lfsr;
wire lfsr_out = lfsr[5];
reg seq_restart;
always @(posedge dck or negedge drst_n) begin
if (!drst_n) begin
lfsr <= LFSR_INIT;
end else if (seq_restart) begin
lfsr <= LFSR_INIT;
end else begin
lfsr <= {lfsr[4:0], ^(lfsr & LFSR_TAPS)};
end
end
// Connect sequence consists of:
// - Some number of zeroes from the host that doesn't appear elsewhere in the
// sequence (sync/preamble) which basically clears this sequence counter
// - 64 bits of LFSR output, starting and ending with a `1` bit
// - 72 ones, which can't appear in regular TWD traffic
// - 4-bit target address, followed by its bitwise complement
reg [7:0] seq_ctr;
always @(*) begin
seq_restart = 1'b0;
if (connected) begin
seq_restart = 1'b1;
end else if (~|seq_ctr[7:6]) begin
// Bits 0..63: match LFSR output
seq_restart = di_q != lfsr_out;
end else if (~&{seq_ctr[7], seq_ctr[3]}) begin
// Bits 64..135: all ones
seq_restart = !di_q;
end else begin
// Bits 136..143: address followed by complement of address
seq_restart = (di_q ^ seq_ctr[2]) != mdropaddr[~seq_ctr[1:0]];
end
end
always @(posedge dck or negedge drst_n) begin
if (!drst_n) begin
seq_ctr <= 8'h00;
end else if (seq_restart) begin
seq_ctr <= 8'h00;
end else begin
seq_ctr <= seq_ctr + 8'h01;
end
end
assign connect_now = seq_ctr == 8'h8f && di_q == !mdropaddr[0];
endmodule
| 7.429738 |
module twowire_dtm_io_flops (
input wire dck,
input wire drst_n,
input wire do,
output wire do_q,
input wire doe,
output wire doe_q,
input wire di,
output wire di_q
);
`TWOWIRE_REG_KEEP_ATTR reg do_reg;
`TWOWIRE_REG_KEEP_ATTR reg doe_reg;
`TWOWIRE_REG_KEEP_ATTR reg di_reg;
always @ (posedge dck or negedge drst_n) begin
if (!drst_n) begin
do_reg <= 1'b0;
doe_reg <= 1'b0;
di_reg <= 1'b0;
end else begin
do_reg <= do;
doe_reg <= doe;
di_reg <= di;
end
end
assign do_q = do_reg;
assign doe_q = doe_reg;
assign di_q = di_reg;
endmodule
| 7.231774 |
module twox1_32bit (
In0,
In1,
Sel,
out
);
input [31:0] In0, In1;
input Sel;
output [31:0] out;
reg [31:0] out;
always @(In0 or In1 or Sel) begin
case (Sel)
0: out <= In0;
1: out <= In1;
default: out <= 32'hxxxxxxxx;
endcase
end
endmodule
| 7.109293 |
module twoxfourdec (
En,
Inp,
Outp
);
input En;
input [1:0] Inp;
output [3:0] Outp;
reg [3:0] Out;
always @(En or Inp) begin
if (~En) Out <= 4'b1111;
else begin
case (Inp)
2'b00: Out <= 4'b0111;
2'b01: Out <= 4'b1011;
2'b10: Out <= 4'b1101;
2'b11: Out <= 4'b1110;
default: Out <= 4'b0000;
endcase
end
end
assign Outp = Out;
endmodule
| 7.595136 |
module: twoxfourdec
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module twoxfourdec_test;
// Inputs
reg En;
reg [1:0] Inp;
// Outputs
wire [3:0] Outp;
// Instantiate the Unit Under Test (UUT)
twoxfourdec uut (
.En(En),
.Inp(Inp),
.Outp(Outp)
);
initial begin
En = 0;
Inp = 0;
#30;
En = 1;
Inp = 0;
#30;
En = 1;
Inp = 1;
#30;
En = 1;
Inp = 2;
#30;
En = 1;
Inp = 3;
#30;
En = 0;
Inp = 3;
#30;
end
endmodule
| 7.326359 |
module TwoXOneMUX (
input A,
B,
S,
output C
);
assign C = S ? B : A;
//always @(*)
//begin
// C = (A & ~S )|(S & B);
// end
endmodule
| 7.48674 |
module two_1_mux (
data1,
data0,
sel,
outputdata
);
input [15:0] data0;
input [15:0] data1;
input sel;
output [15:0] outputdata;
reg [15:0] outputdata;
always @(sel or data1 or data0) begin
case (sel)
1'b0: begin
outputdata <= data0;
end
1'b1: begin
outputdata <= data1;
end
endcase
end
endmodule
| 7.223511 |
module two_4_input_and_gate #(
parameter DELAY = 10
) (
input wire a1,
b1,
c1,
d1,
a2,
b2,
c2,
d2,
output wire y1,
y2
);
and #DELAY (y1, a1, b1, c1, d1);
and #DELAY (y2, a2, b2, c2, d2);
endmodule
| 7.860282 |
module two_4_input_nand_gate #(
parameter DELAY = 10
) (
input wire a1,
b1,
c1,
d1,
a2,
b2,
c2,
d2,
output wire y1,
y2
);
nand #DELAY (y1, a1, b1, c1, d1);
nand #DELAY (y2, a2, b2, c2, d2);
endmodule
| 8.040559 |
module two_bit (
A0,
A1,
B0,
B1,
S0,
S1,
S2,
C2
);
input A0, A1, B1, B0;
output S0, S1, S2, C2;
wire C1;
assign S0 = A0 & B0;
assign S1 = (A0 & B1) ^ (A1 & B0);
assign C1 = (A0 & B1) & (A1 & B0);
assign S2 = C1 ^ (A1 & B1);
assign C2 = C1 & (A1 & B1);
endmodule
| 7.01638 |
module half_adder (
S,
C,
X,
Y
);
input X, Y;
output S, C;
xor a1 (S, X, Y);
and a2 (C, X, Y);
endmodule
| 6.966406 |
module two_bit_adder (
A,
B,
Cin,
Sum,
Carry
);
input [1:0] A, B;
input Cin;
output [1:0] Sum;
output Carry;
wire C1, C2, C3, C4, S0, S1;
half_adder h1 (
S0,
C0,
A[0],
B[0]
);
half_adder h2 (
Sum[0],
C1,
Cin,
S0
);
or o1 (C2, C1, C0);
half_adder h3 (
S1,
C3,
A[1],
B[1]
);
half_adder h4 (
Sum[1],
C4,
C2,
S1
);
or o2 (Carry, C3, C4);
endmodule
| 6.650749 |
module two_bit_adder_dataflow;
//`include "two_bit_adder.v"
reg [1:0] A, B;
reg Cin;
wire [1:0] Sum;
wire Carry;
two_bit_adder DUT (
A,
B,
Cin,
Sum,
Carry
);
initial begin
$dumpfile("two_bit_adder_dataflow.vcd");
$dumpvars();
end
initial begin
A = 2'b00;
B = 2'b00;
Cin = 1'b0;
#30 A = 2'b00;
B = 2'b01;
Cin = 1'b0;
#30 A = 2'b00;
B = 2'b10;
Cin = 1'b0;
#30 A = 2'b00;
B = 2'b11;
Cin = 1'b0;
#30 A = 2'b01;
B = 2'b00;
Cin = 1'b0;
#30 A = 2'b01;
B = 2'b01;
Cin = 1'b0;
#30 A = 2'b01;
B = 2'b10;
Cin = 1'b0;
#30 A = 2'b01;
B = 2'b11;
Cin = 1'b0;
#30 A = 2'b10;
B = 2'b00;
Cin = 1'b0;
#30 A = 2'b10;
B = 2'b01;
Cin = 1'b0;
#30 A = 2'b10;
B = 2'b10;
Cin = 1'b0;
#30 A = 2'b10;
B = 2'b11;
Cin = 1'b0;
#30 A = 2'b11;
B = 2'b00;
Cin = 1'b0;
#30 A = 2'b11;
B = 2'b01;
Cin = 1'b0;
#30 A = 2'b11;
B = 2'b10;
Cin = 1'b0;
#30 A = 2'b11;
B = 2'b11;
Cin = 1'b0;
#30 A = 2'b00;
B = 2'b00;
Cin = 1'b1;
#30 A = 2'b00;
B = 2'b01;
Cin = 1'b1;
#30 A = 2'b00;
B = 2'b10;
Cin = 1'b1;
#30 A = 2'b00;
B = 2'b11;
Cin = 1'b1;
#30 A = 2'b01;
B = 2'b00;
Cin = 1'b1;
#30 A = 2'b01;
B = 2'b01;
Cin = 1'b1;
#30 A = 2'b01;
B = 2'b10;
Cin = 1'b1;
#30 A = 2'b01;
B = 2'b11;
Cin = 1'b1;
#30 A = 2'b10;
B = 2'b00;
Cin = 1'b1;
#30 A = 2'b10;
B = 2'b01;
Cin = 1'b1;
#30 A = 2'b10;
B = 2'b10;
Cin = 1'b1;
#30 A = 2'b10;
B = 2'b11;
Cin = 1'b1;
#30 A = 2'b11;
B = 2'b00;
Cin = 1'b1;
#30 A = 2'b11;
B = 2'b01;
Cin = 1'b1;
#30 A = 2'b11;
B = 2'b10;
Cin = 1'b1;
#30 A = 2'b11;
B = 2'b11;
Cin = 1'b1;
end
initial begin
$monitor(" time=%0d A=%2b B=%2b Cin=%b Sum=%2b Carry=%b", $time, A, B, Cin, Sum, Carry);
end
endmodule
| 6.650749 |
module half_adder (
S,
C,
X,
Y
);
input X, Y;
output S, C;
xor a1 (S, X, Y);
and a2 (C, X, Y);
endmodule
| 6.966406 |
module two_bit_adder (
A,
B,
Cin,
Sum,
Carry
);
input [1:0] A, B;
input Cin;
output [1:0] Sum;
output Carry;
wire C1, C2, C3, C4, S0, S1;
half_adder h1 (
S0,
C0,
A[0],
B[0]
);
half_adder h2 (
Sum[0],
C1,
Cin,
S0
);
or o1 (C2, C1, C0);
half_adder h3 (
S1,
C3,
A[1],
B[1]
);
half_adder h4 (
Sum[1],
C4,
C2,
S1
);
or o2 (Carry, C3, C4);
endmodule
| 6.650749 |
module two_bit_adder_tb;
//`include "two_bit_adder.v"
reg [1:0] A, B;
reg Cin;
wire [1:0] Sum;
wire Carry;
two_bit_adder DUT (
A,
B,
Cin,
Sum,
Carry
);
initial begin
$dumpfile("two_bit_adder_tb.vcd");
$dumpvars();
end
initial begin
A = 2'b00;
B = 2'b00;
Cin = 1'b0;
#30 A = 2'b00;
B = 2'b01;
Cin = 1'b0;
#30 A = 2'b00;
B = 2'b10;
Cin = 1'b0;
#30 A = 2'b00;
B = 2'b11;
Cin = 1'b0;
#30 A = 2'b01;
B = 2'b00;
Cin = 1'b0;
#30 A = 2'b01;
B = 2'b01;
Cin = 1'b0;
#30 A = 2'b01;
B = 2'b10;
Cin = 1'b0;
#30 A = 2'b01;
B = 2'b11;
Cin = 1'b0;
#30 A = 2'b10;
B = 2'b00;
Cin = 1'b0;
#30 A = 2'b10;
B = 2'b01;
Cin = 1'b0;
#30 A = 2'b10;
B = 2'b10;
Cin = 1'b0;
#30 A = 2'b10;
B = 2'b11;
Cin = 1'b0;
#30 A = 2'b11;
B = 2'b00;
Cin = 1'b0;
#30 A = 2'b11;
B = 2'b01;
Cin = 1'b0;
#30 A = 2'b11;
B = 2'b10;
Cin = 1'b0;
#30 A = 2'b11;
B = 2'b11;
Cin = 1'b0;
#30 A = 2'b00;
B = 2'b00;
Cin = 1'b1;
#30 A = 2'b00;
B = 2'b01;
Cin = 1'b1;
#30 A = 2'b00;
B = 2'b10;
Cin = 1'b1;
#30 A = 2'b00;
B = 2'b11;
Cin = 1'b1;
#30 A = 2'b01;
B = 2'b00;
Cin = 1'b1;
#30 A = 2'b01;
B = 2'b01;
Cin = 1'b1;
#30 A = 2'b01;
B = 2'b10;
Cin = 1'b1;
#30 A = 2'b01;
B = 2'b11;
Cin = 1'b1;
#30 A = 2'b10;
B = 2'b00;
Cin = 1'b1;
#30 A = 2'b10;
B = 2'b01;
Cin = 1'b1;
#30 A = 2'b10;
B = 2'b10;
Cin = 1'b1;
#30 A = 2'b10;
B = 2'b11;
Cin = 1'b1;
#30 A = 2'b11;
B = 2'b00;
Cin = 1'b1;
#30 A = 2'b11;
B = 2'b01;
Cin = 1'b1;
#30 A = 2'b11;
B = 2'b10;
Cin = 1'b1;
#30 A = 2'b11;
B = 2'b11;
Cin = 1'b1;
end
initial begin
$monitor(" time=%0d A=%2b B=%2b Cin=%b Sum=%2b Carry=%b", $time, A, B, Cin, Sum, Carry);
end
endmodule
| 6.650749 |
module: two_bit_adder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module two_bit_adder_top;
// Inputs
reg [1:0] x;
reg [1:0] y;
// Outputs
wire [1:0] z;
wire carry;
// Instantiate the Unit Under Test (UUT)
two_bit_adder uut (
.x(x),
.y(y),
.z(z),
.carry(carry)
);
always@(z, carry) begin
$display("$time = %d, %b + %b = %b, carry = %b\n", $time, x, y, z, carry);
end
initial begin
x = 2'b00; y = 2'b00;
#5
x = 2'b01; y = 2'b00;
#5
x = 2'b10; y = 2'b00;
#5
x = 2'b00; y = 2'b11;
#5
x = 2'b01; y = 2'b01;
#5
x = 2'b10; y = 2'b10;
#5
$finish;
end
endmodule
| 7.237769 |
module d_flipflop (
input CLK,
input R,
input D,
output Q
);
reg Q, Qc;
initial begin
Q = 0;
Qc = 0;
end
always @(posedge CLK) begin
Q <= D;
Qc <= ~D;
if (R) begin
Q <= 0;
Qc <= 1;
end
end
endmodule
| 7.276171 |
module two_bit_comp (
input wire [1:0] x,
y,
output wire answer
);
wire p0, p1, p2, p3;
assign p0 = (~x[1] & ~y[1]) & (~x[0] & ~y[0]);
assign p1 = (~x[1] & ~y[1]) & (x[0] & y[0]);
assign p2 = (x[1] & y[1]) & (~x[0] & ~y[0]);
assign p3 = (x[1] & y[1]) & (x[0] & y[0]);
assign answer = p0 | p1 | p2 | p3;
endmodule
| 7.799052 |
module two_bit_comp2 (
input wire [1:0] x,
y,
output wire answer
);
wire p0, p1;
comp circuit1 (
x[1],
y[1],
p0
);
comp circuit2 (
x[0],
y[0],
p1
);
assign answer = p0 & p1;
endmodule
| 9.006145 |
module two_bit_comp2 (
input wire [1:0] x,
y,
output wire answer
);
assign answer = x == y;
endmodule
| 9.006145 |
module Two_Bit_Comparator (
input [1:0] A, //2-bit INPUT A
input [1:0] B, //2-bit INPUT B
output A_Greater, //OUTPUT BIT A>B
output Equal, //OUTPUT BIT A=B
output B_Greater //OUTPUT BIT A<B
);
////////////////////////WRITE YOUR CODE FROM HERE////////////////////
assign A_Greater = A[1] & ~B[1] | A[0] & ~B[1] & ~B[0] | A[1] & A[0] & ~B[0];
assign Equal = (~A[0] & ~B[0] | A[0] & B[0]) & (~A[1] & ~B[1] | A[1] & B[1]);
assign B_Greater = ~A[1] & B[1] | ~A[0] & B[1] & B[0] | ~A[1] & ~A[0] & B[0];
////////////////////////YOUR CODE ENDS HERE//////////////////////////
endmodule
| 7.18956 |
module two_bit_comp_tb;
reg [1:0] x;
reg [1:0] y;
wire answer;
two_bit_comp2 circuit1 (
x,
y,
answer
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0, two_bit_comp_tb);
x = 2'b00;
y = 2'b00;
#20;
x = 2'b00;
y = 2'b01;
#20;
x = 2'b01;
y = 2'b00;
#20;
x = 2'b11;
y = 2'b11;
#40;
end
initial begin
$monitor("x=%d, y=%d, z=%d", x, y, answer);
end
endmodule
| 6.983096 |
module two_bit_down (
CLOCK_50, //50 MHZ clock
KEY, // reset
SW,
Hex0_value,
Hex1_value,
Hex0,
Hex1
);
input CLOCK_50; //50 MHZ clock
input [0:0] KEY; // reset
input [9:9] SW;
input [3:0] Hex0_value, Hex1_value;
output [0:6] Hex0;
output [0:6] Hex1;
reg [2:0] state;
reg [3:0] counter; // for HEX0
reg [3:0] counter2; // for HEX1
reg [3:0] cycles;
wire clock_oneHz;
Lab4B_modified oneHzClock (
CLOCK_50,
KEY,
clock_oneHz
);
BCD_decoder_modified seven_seg1 (
counter,
Hex0
);
BCD_decoder_modified seven_seg2 (
counter2,
Hex1
);
always @(posedge clock_oneHz, negedge KEY)
if (~KEY) //reset
begin
counter <= 4'd0;
counter2 <= 4'd0;
end else // no reset
if (counter == 4'd0) // 9 to 0
if (counter2 == 4'd0) begin
counter <= Hex0_value;
counter2 <= Hex1_value;
end else begin
counter2 <= counter2 - 1'd1;
counter <= counter;
end
else begin
counter <= counter - 1'd1;
counter2 <= counter2;
end
endmodule
| 7.199636 |
module two_by_one_mux (
input [3:0] in0,
input [3:0] in1,
input selector,
output [3:0] Y
);
assign Y = (selector == 0) ? in0 : in1;
endmodule
| 6.590245 |
module two_complementer (
input inp,
input clk,
input reset,
output reg out
);
reg state;
always @(posedge clk, posedge reset) begin
if (reset) state <= 0;
else begin
case (state)
0: begin
if (inp == 0) begin
state <= 0;
out <= 0;
end else begin
state <= 1;
out <= 1;
end
end
1: begin
if (inp == 0) begin
state <= 1;
out <= 1;
end else begin
state <= 1;
out <= 0;
end
end
endcase
end
end
endmodule
| 7.955961 |
module: two_complementer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module two_complementer_tb;
// Inputs
reg inp;
reg clk;
reg reset;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
two_complementer uut (
.inp(inp),
.clk(clk),
.reset(reset),
.out(out)
);
// Initialize Inputs
reg [15:0]sequence;
reg [15:0]output_seq;
integer i;
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
inp = 0;
assign sequence = 16'b0101011101110010;
i=0;
// Wait 100 ns for global reset to finish
#5;
reset =0;
for( i = 0; i <= 15; i = i + 1)
begin
inp = sequence[i];
clk = 1;
#2;
clk = 0;
#2;
output_seq[i] = out;
$display(" Input = ", inp, ", Output = ", out);
end
end
endmodule
| 7.282119 |
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