code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TopmodulePS2 #(
parameter clk_freq = 50000000
) (
input sys_rst,
input sys_clk,
input [7:0] csr_di, //datainput
input csr_we, //control status register write enable
inout ps2_clk,
inout ps2_data,
output irq,
output rx_avail,
output [7:0] kcode,
output tx_busy,
output [4:0] rx_bitcount
);
wire state_transmit;
wire state_receive;
wire ps2_clk_out;
wire ps2_data_out1;
wire ps2_clk_2;
wire we_reg;
ps2 ps2 (
.sys_rst(sys_rst),
.sys_clk(sys_clk),
.csr_di(csr_di), //datainpu
.csr_we(csr_we), //control status register write enable
.ps2_clk_out(ps2_clk_out),
.ps2_data_out1(ps2_data_out1),
.ps2_clk_2(ps2_clk_2),
.state_receive(state_receive),
.state_transmit(state_transmit),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.we_reg(we_reg),
.kcode(kcode),
.rx_avail(rx_avail),
.irq(irq),
.rx_bitcount(rx_bitcount)
);
CTRLps2 #(
.clk_freq(clk_freq)
) CTRLps2 (
.sys_rst(sys_rst),
.sys_clk(sys_clk),
.we_reg(we_reg),
.rx_bitcount(rx_bitcount),
.ps2_clk_out(ps2_clk_out),
.ps2_clk_2(ps2_clk_2),
.ps2_data_out1(ps2_data_out1),
.tx_busy(tx_busy),
.state_receive(state_receive),
.state_transmit(state_transmit)
);
endmodule
| 7.401869 |
module TopModuleS (
CLOCK_50,
VGA_VS,
VGA_HS,
VGA_CLK,
COLOR,
led1,
swa,
swb,
swc,
swd,
swe,
swf,
swg
);
input CLOCK_50;
output reg [7:0] led1;
output VGA_HS, VGA_VS;
output reg VGA_CLK = 0;
output wire [7:0] COLOR;
input swa, swb, swc, swd, swe, swf, swg;
reg [7:0] color_i;
wire READY;
wire [9:0] pos_H, pos_V;
reg [7:0] baris [0:9999];
reg [7:0] cengiz[0:9999];
reg [7:0] emre [0:9999];
reg [7:0] fail [0:9999];
reg [7:0] vural [0:9999];
reg [7:0] tomak [0:9999];
reg [7:0] zafer [0:9999];
initial begin
$readmemh("baris.txt", baris);
$readmemh("cengiz.txt", cengiz);
$readmemh("emre.txt", emre);
$readmemh("fail.txt", fail);
$readmemh("vural.txt", vural);
$readmemh("tomak.txt", tomak);
$readmemh("zafer.txt", zafer);
end
always @(posedge CLOCK_50) begin
VGA_CLK = ~VGA_CLK;
end
VGA_SyncS SYNC (
.vga_CLK(VGA_CLK),
.VSync(VGA_VS),
.HSync(VGA_HS),
.vga_Ready(READY),
.pos_H(pos_H),
.pos_V(pos_V)
);
always @(posedge VGA_CLK) begin
if (pos_H >= 150 && pos_H < 250 && pos_V >= 100 && pos_V < 200 && swa) begin
color_i <= baris[{(pos_H-150)*100+pos_V-100}];
end else if (pos_H >= 300 && pos_H < 450 && pos_V >= 100 && pos_V < 200 && swb) begin
color_i <= cengiz[{(pos_H-300)*100+pos_V-100}];
end else if (pos_H >= 500 && pos_H < 600 && pos_V >= 100 && pos_V < 200 && swc) begin
color_i <= emre[{(pos_H-500)*100+pos_V-100}];
end else if (pos_H >= 650 && pos_H < 800 && pos_V >= 100 && pos_V < 200 && swd) begin
color_i <= fail[{(pos_H-650)*100+pos_V-100}];
end else if (pos_H >= 200 && pos_H < 300 && pos_V >= 300 && pos_V < 400 && swe) begin
color_i <= vural[{(pos_H-200)*100+pos_V-300}];
end else if (pos_H >= 400 && pos_H < 500 && pos_V >= 300 && pos_V < 400 && swf) begin
color_i <= zafer[{(pos_H-400)*100+pos_V-300}];
end else if (pos_H >= 600 && pos_H < 700 && pos_V >= 300 && pos_V < 400 && swg) begin
color_i <= tomak[{(pos_H-600)*100+pos_V-300}];
end else begin
color_i <= 8'h0;
end
end
assign COLOR = READY ? color_i : 8'h0;
endmodule
| 6.690679 |
module ModWithNestedClk (
input reset,
input io_inClk,
output io_bbOutClk_0,
output io_bbOutClk_1,
output io_bbOutClk_2,
output io_clkDivOut_0,
output io_clkDivOut_1,
output io_clkDivOut_2
);
wire bb_outClk_0; // @[ClkGenSpec.scala 63:18]
wire bb_outClk_1; // @[ClkGenSpec.scala 63:18]
wire bb_outClk_2; // @[ClkGenSpec.scala 63:18]
wire bb_inClk; // @[ClkGenSpec.scala 63:18]
wire clkDiv_io_reset; // @[ClkGenSpec.scala 66:22]
wire clkDiv_io_inClk; // @[ClkGenSpec.scala 66:22]
wire clkDiv_io_outClks_3; // @[ClkGenSpec.scala 66:22]
wire clkDiv_io_outClks_1; // @[ClkGenSpec.scala 66:22]
wire clkDiv_io_outClks_0; // @[ClkGenSpec.scala 66:22]
FakeBBClk bb ( // @[ClkGenSpec.scala 63:18]
.outClk_0(bb_outClk_0),
.outClk_1(bb_outClk_1),
.outClk_2(bb_outClk_2),
.inClk(bb_inClk)
);
SEClkDivider clkDiv ( // @[ClkGenSpec.scala 66:22]
.io_reset(clkDiv_io_reset),
.io_inClk(clkDiv_io_inClk),
.io_outClks_3(clkDiv_io_outClks_3),
.io_outClks_1(clkDiv_io_outClks_1),
.io_outClks_0(clkDiv_io_outClks_0)
);
assign io_bbOutClk_0 = bb_outClk_0; // @[ClkGenSpec.scala 65:15]
assign io_bbOutClk_1 = bb_outClk_1; // @[ClkGenSpec.scala 65:15]
assign io_bbOutClk_2 = bb_outClk_2; // @[ClkGenSpec.scala 65:15]
assign io_clkDivOut_0 = clkDiv_io_outClks_0; // @[ClkGenSpec.scala 69:72]
assign io_clkDivOut_1 = clkDiv_io_outClks_1; // @[ClkGenSpec.scala 69:72]
assign io_clkDivOut_2 = clkDiv_io_outClks_3; // @[ClkGenSpec.scala 69:72]
assign bb_inClk = io_inClk; // @[ClkGenSpec.scala 64:15]
assign clkDiv_io_reset = reset; // @[ClkGenSpec.scala 67:19]
assign clkDiv_io_inClk = io_inClk; // @[ClkGenSpec.scala 68:19]
endmodule
| 6.895733 |
module ModWithNestedClk_1 (
input reset,
input io_inClk,
output io_bbOutClk_0,
output io_bbOutClk_1,
output io_bbOutClk_2,
output io_clkDivOut_0,
output io_clkDivOut_1,
output io_clkDivOut_2
);
wire bb_outClk_0; // @[ClkGenSpec.scala 63:18]
wire bb_outClk_1; // @[ClkGenSpec.scala 63:18]
wire bb_outClk_2; // @[ClkGenSpec.scala 63:18]
wire bb_inClk; // @[ClkGenSpec.scala 63:18]
wire clkDiv_io_reset; // @[ClkGenSpec.scala 66:22]
wire clkDiv_io_inClk; // @[ClkGenSpec.scala 66:22]
wire clkDiv_io_outClks_3; // @[ClkGenSpec.scala 66:22]
wire clkDiv_io_outClks_1; // @[ClkGenSpec.scala 66:22]
wire clkDiv_io_outClks_0; // @[ClkGenSpec.scala 66:22]
FakeBBClk bb ( // @[ClkGenSpec.scala 63:18]
.outClk_0(bb_outClk_0),
.outClk_1(bb_outClk_1),
.outClk_2(bb_outClk_2),
.inClk(bb_inClk)
);
SEClkDivider_1 clkDiv ( // @[ClkGenSpec.scala 66:22]
.io_reset(clkDiv_io_reset),
.io_inClk(clkDiv_io_inClk),
.io_outClks_3(clkDiv_io_outClks_3),
.io_outClks_1(clkDiv_io_outClks_1),
.io_outClks_0(clkDiv_io_outClks_0)
);
assign io_bbOutClk_0 = bb_outClk_0; // @[ClkGenSpec.scala 65:15]
assign io_bbOutClk_1 = bb_outClk_1; // @[ClkGenSpec.scala 65:15]
assign io_bbOutClk_2 = bb_outClk_2; // @[ClkGenSpec.scala 65:15]
assign io_clkDivOut_0 = clkDiv_io_outClks_0; // @[ClkGenSpec.scala 69:72]
assign io_clkDivOut_1 = clkDiv_io_outClks_1; // @[ClkGenSpec.scala 69:72]
assign io_clkDivOut_2 = clkDiv_io_outClks_3; // @[ClkGenSpec.scala 69:72]
assign bb_inClk = io_inClk; // @[ClkGenSpec.scala 64:15]
assign clkDiv_io_reset = reset; // @[ClkGenSpec.scala 67:19]
assign clkDiv_io_inClk = io_inClk; // @[ClkGenSpec.scala 68:19]
endmodule
| 6.895733 |
module TopModule_tb;
// Inputs
reg clk;
reg rst;
// Outputs
wire instruction_bit;
wire alu_result_bit;
wire jump_offset_bit;
wire pc_bit;
// Instantiate the Unit Under Test (UUT)
TopModule uut (
.clk(clk),
.rst(rst),
.instruction_bit(instruction_bit),
.alu_result_bit(alu_result_bit),
.jump_offset_bit(jump_offset_bit),
.pc_bit(pc_bit)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
// this file has the required changes for post-route simulation but due to
// the misinformation of the clock port os Spartan3, only behavioral simulation was run
// Wait 100 ps for global reset to finish
#1;
// Add stimulus here
// Add stimulus here
rst = 1;
#2 rst = 0;
end
always begin
#1 clk = ~clk;
end
endmodule
| 8.900291 |
module top (
input clk,
reset,
output [31:0] writedata,
adr,
output memwrite
);
wire [31:0] readdata;
// microprocessor (control & datapath)
mips mips (
clk,
reset,
adr,
writedata,
memwrite,
readdata
);
// memory
mem mem (
clk,
memwrite,
adr,
writedata,
readdata
);
endmodule
| 7.233807 |
module TopMultiplier (
x_in,
y_in,
result_out
);
input [15:0] x_in, y_in;
output [31:0] result_out;
// internal connections
wire [15:0] pp0, pp1, pp2, pp3, pp4, pp5, pp6, pp7, pp8, pp9, pp10, pp11, pp12, pp13, pp14, pp15;
wire [31:0] opa, opb;
wire [15:0] sign;
//wire [15: 0] sign_compensate;
wire [31:0] sign_compensate;
wire [31:0] res_tmp;
// generate PP
Booth_Classic booth (
.M(x_in),
.R(y_in),
.pp0(pp0),
.pp1(pp1),
.pp2(pp2),
.pp3(pp3),
.pp4(pp4),
.pp5(pp5),
.pp6(pp6),
.pp7(pp7),
.pp8(pp8),
.pp9(pp9),
.pp10(pp10),
.pp11(pp11),
.pp12(pp12),
.pp13(pp13),
.pp14(pp14),
.pp15(pp15),
.S(sign)
);
// wallace tree
WallaceTree16X16 wallace (
.pp0 (pp0),
.pp1 (pp1),
.pp2 (pp2),
.pp3 (pp3),
.pp4 (pp4),
.pp5 (pp5),
.pp6 (pp6),
.pp7 (pp7),
.pp8 (pp8),
.pp9 (pp9),
.pp10(pp10),
.pp11(pp11),
.pp12(pp12),
.pp13(pp13),
.pp14(pp14),
.pp15(pp15),
.opa (opa),
.opb (opb)
);
// calculate the sign bit compensate
//CS_Adder32 signcomp (
// .a( {~sign, 16'b0} ),
// .b( {15'b0, 1'b1, 16'b0} ),
// .cin( 1'b0 ),
// .sum( sign_compensate ),
// .cout()
// );
//// temporary result
//CS_Adder32 resulttemp (
// .a( opa ),
// .b( opb ),
// .cin( 1'b0 ),
// .sum( res_tmp ),
// .cout()
// );
//// final result
//CS_Adder32 result (
// .a( res_tmp ),
// .b( sign_compensate ),
// .cin( 1'b0 ),
// .sum( result_out),
// .cout()
// );
prefixadder32 signcomp (
.A ({~sign, 16'b0}),
.B ({15'b0, 1'b1, 16'b0}),
.Cin(1'b0),
.Sum(sign_compensate)
);
// temporary result
prefixadder32 resulttemp (
.A (opa),
.B (opb),
.Cin(1'b0),
.Sum(res_tmp)
);
// final result
prefixadder32 result (
.A (res_tmp),
.B (sign_compensate),
.Cin(1'b0),
.Sum(result_out)
);
endmodule
| 7.182111 |
module topnbit_verification (
result,
clk,
c_in,
a,
b,
ALOP
);
parameter W = 32;
input [2:0] ALOP;
input clk;
input [W-1:0] a, b;
input c_in;
output [W:0] result;
wire [W-1:0] sum_to_reg;
assign {result} = //verifies each function
(ALOP == 3'b000) ? {a}:
(ALOP == 3'b001) ? {~a}:
(ALOP == 3'b011) ? {a&b}:
(ALOP == 3'b100) ? {a|b}:
(ALOP == 3'b101) ? {a-b}:
(ALOP == 3'b110) ? a+b+c_in:
0;
endmodule
| 7.745191 |
module VizModC ( // @[:@3.2]
input [15:0] io_in, // @[:@6.4]
output [15:0] io_out // @[:@6.4]
);
assign io_out = io_in;
endmodule
| 9.030593 |
module VizModA ( // @[:@13.2]
input [31:0] io_in, // @[:@16.4]
output [15:0] io_out // @[:@16.4]
);
wire [15:0] modC_io_in; // @[VisualizerSpec.scala 40:20:@21.4]
wire [15:0] modC_io_out; // @[VisualizerSpec.scala 40:20:@21.4]
VizModC modC ( // @[VisualizerSpec.scala 40:20:@21.4]
.io_in (modC_io_in),
.io_out(modC_io_out)
);
assign io_out = modC_io_out;
assign modC_io_in = io_in[15:0];
endmodule
| 8.095252 |
module VizModC (
input [15:0] io_in,
output [15:0] io_out
);
assign io_out = io_in; // @[VisualizerSpec.scala 25:10]
endmodule
| 8.61491 |
module VizModA (
input [31:0] io_in,
output [15:0] io_out
);
wire [15:0] modC_io_in; // @[VisualizerSpec.scala 40:20]
wire [15:0] modC_io_out; // @[VisualizerSpec.scala 40:20]
VizModC modC ( // @[VisualizerSpec.scala 40:20]
.io_in (modC_io_in),
.io_out(modC_io_out)
);
assign io_out = modC_io_out; // @[VisualizerSpec.scala 42:10]
assign modC_io_in = io_in[15:0]; // @[VisualizerSpec.scala 41:14]
endmodule
| 8.589487 |
module topology_module #(
parameter PORT_SIZE = 37 + 2,
parameter PORTS_NUM = 4,
parameter NODES_NUM = 2,
`ifdef MESH_2D
parameter H_SIZE = 2
`else
`ifdef CIRCULANT_2
parameter S0 = 1,
parameter S1 = 2
`else
`ifdef TORUS
parameter H_SIZE = 2
`endif // TORUS
`endif // CIRCULANT_2
`endif // MESH
) (
input [NODES_NUM*PORTS_NUM*PORT_SIZE-1:0] data_i,
output [NODES_NUM*PORTS_NUM*PORT_SIZE-1:0] data_o
);
`ifdef MESH_2D
mesh_2d #(
.PORT_SIZE(PORT_SIZE),
.NODES_NUM(NODES_NUM),
.H_SIZE(H_SIZE)
) connector (
data_i,
data_o
);
`else
`ifdef CIRCULANT_2
circulant_2 #(
.PORT_SIZE(PORT_SIZE),
.NODES_NUM(NODES_NUM),
.S0(S0),
.S1(S1)
) connector (
data_i,
data_o
);
`else
`ifdef TORUS
torus #(
.PORT_SIZE(PORT_SIZE),
.NODES_NUM(NODES_NUM),
.H_SIZE(H_SIZE)
) connector (
data_i,
data_o
);
`endif // TORUS
`endif // CIRCULANT_2
`endif // MESH
endmodule
| 7.862427 |
module toppest (
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
input wire [ 3:0] sw, // four switches, [0] right [1] left [2] down [3] up
output wire VGA_HS_O, // horizontal sync output
output wire VGA_VS_O, // vertical sync output
output wire [ 3:0] VGA_R, // 4-bit VGA red output
output wire [ 3:0] VGA_G, // 4-bit VGA green output
output wire [ 3:0] VGA_B, // 4-bit VGA blue output
output wire [15:0] LED // 16 led for debug
);
reg LEDs[15:0];
// localparam one_second = 25'b101111010111100001000000;
localparam one_second = 25'b10111101011110000100000;
// generate a 25 MHz pixel strobe and an 1Hz impulse
reg [15:0] cnt;
reg [24:0] count;
reg G_move_clk;
reg pix_stb;
always @(posedge CLK) begin
{pix_stb, cnt} <= cnt + 16'h4000; // divide by 4: (2^16)/4 = 0x4000
count <= count + 1;
if (count == one_second) begin
G_move_clk <= 1;
end else begin
G_move_clk <= 0;
end
if (G_move_clk) LEDs[0] <= ~LEDs[0];
end
wire [3:0] head_pos_x;
wire [3:0] head_pos_y;
wire [3:0] tail_pos_x;
wire [3:0] tail_pos_y;
wire [3:0] apple_pos_x;
wire [3:0] apple_pos_y;
wire [1:0] state;
// map memory
localparam G_MAP_WIDTH = 14;
localparam G_MAP_HEIGHT = 14;
localparam G_MAP_DEPTH = G_MAP_WIDTH * G_MAP_HEIGHT;
localparam G_MAP_A_WIDTH = 8; // 2 ^ 5 > 5 x 5
localparam G_MAP_D_WIDTH = 2;
// 00 lime green 01 glass green 10 white 11 black
// game module
Game game (
.clk (CLK),
.move_clk (G_move_clk),
.rst (RST_BTN),
.sw (sw),
.o_head_pos_x (head_pos_x),
.o_head_pos_y (head_pos_y),
.o_tail_pos_x (tail_pos_x),
.o_tail_pos_y (tail_pos_y),
.o_apple_pos_x(apple_pos_x),
.o_apple_pos_y(apple_pos_y),
.game_state (state),
.o_LED (LED)
);
// graphic module
top #(
.MAP_WIDTH (G_MAP_WIDTH),
.MAP_HEIGHT (G_MAP_HEIGHT),
.MAP_DEPTH (G_MAP_DEPTH),
.MAP_A_WIDTH(G_MAP_A_WIDTH),
.MAP_D_WIDTH(G_MAP_D_WIDTH)
) graphics (
.M_CLK (CLK),
.M_pix_stb (pix_stb),
.M_RST_BTN (RST_BTN),
// .M_move_clk (G_move_clk),
.i_head_pos_x (head_pos_x),
.i_head_pos_y (head_pos_y),
.i_tail_pos_x (tail_pos_x),
.i_tail_pos_y (tail_pos_y),
.i_apple_pos_x(apple_pos_x),
.i_apple_pos_y(apple_pos_y),
.i_game_state (state),
.M_VGA_HS_O (VGA_HS_O),
.M_VGA_VS_O (VGA_VS_O),
.M_VGA_R (VGA_R),
.M_VGA_G (VGA_G),
.M_VGA_B (VGA_B),
.LED (LED)
);
/*
always @ (posedge CLK)
begin
assign LED [0] = move_clk;
end
*/
assign LED[0] = LEDs[0];
endmodule
| 7.883028 |
module PC_PCArthmetic (
clk,
startingPC,
address,
signExtend,
unconditionalBranchFlag,
branchFlag,
zeroFlag
);
input clk;
input [31:0] signExtend; //sign extended insturction
input unconditionalBranchFlag; //flag from controller
input branchFlag; //flag from controller
input zeroFlag; // flag from ALU
output reg [31:0] address; //address of current instruction
input [31:0] startingPC;
reg [31:0] nextPC, pcPlus4;
reg pcplus4, select, andResult, orResult;
reg [31:0] branchPC;
initial begin
select = 0;
nextPC = startingPC;
pcPlus4 = startingPC + 4;
end
always @(posedge clk) begin
address = (select == 1) ? branchPC : pcPlus4;
pcPlus4 = address + 4;
end
always @(signExtend) begin
branchPC = address + signExtend;
end
always @(zeroFlag, branchFlag, unconditionalBranchFlag) begin
andResult = zeroFlag & branchFlag;
orResult = andResult | unconditionalBranchFlag;
select = orResult;
end
endmodule
| 7.379809 |
module instructionCache (
output reg [31:0] data,
output reg missFlag,
input [31:0] PC,
input [31:0] inputData,
input writeData
); //inputData and writeData would be used if we had an imperfect cache that would go to a lower level and get more data to load into this iCache. Here we include but ignore it.
reg [31:0] memoryAddress[0:15];
reg [31:0] memoryData[0:15]; //could be expanded, but here we just use 16
reg [6:0] i;
always @(PC, inputData) begin : search
for (i = 0; i < 16; i = i + 1) begin //how many lines there are
if (PC == memoryAddress[i]) begin
data = memoryData[i];
missFlag = 0;
disable search;
end //if PC==
end //for
//if you reach here, you didn't find it
data = 0;
missFlag = 1;
end //always
initial begin
memoryAddress[0] = 32'h00001000;
memoryData[0] = 32'h91002294; //ADDI R20, R20, #8
memoryAddress[1] = 32'h00001004;
memoryData[1] = 32'hB20000E3; //ORRI R3, R7, #0
memoryAddress[2] = 32'h00001008;
memoryData[2] = 32'hD1000333; //SUBI R19, R25, #0
memoryAddress[3] = 32'h0000100C;
memoryData[3] = 32'h910006D6; //ADDI X22, X22, #1
memoryAddress[4] = 32'h00001010;
memoryData[4] = 32'hEA001028; //EORR R4, R1, R0
memoryAddress[5] = 32'h00001014;
memoryData[5] = 32'hF8400281; //LDUR R1 [R20, #0]
//memoryAddress[5] = 32'h00001014; memoryData[5] = 32'hCB000165;//SUB R5, R11, R0
//memoryAddress[6] = 32'h00001018; memoryData[6] = 32'hF85F4284; //LDUR R4, [R20 #-12]
/*memoryAddress[6] = 32'h00001018; memoryData[6] = 32'h17FFFFFA; //B #3FFFFFA (-6)
memoryAddress[7] = 32'h0000101C; memoryData[7] = 32'h17FFFFFA;
memoryAddress[8] = 32'h00001020; memoryData[8] = 32'h17FFFFFA;
memoryAddress[9] = 32'h00001024; memoryData[9] = 32'h17FFFFFA;
memoryAddress[10] = 32'h00001028; memoryData[10] = 32'h17FFFFFA;
memoryAddress[11] = 32'h0000102C; memoryData[11] = 32'h17FFFFFA;
memoryAddress[12] = 32'h00001030; memoryData[12] = 32'h17FFFFFA;
memoryAddress[13] = 32'h00001034; memoryData[13] = 32'h17FFFFFA;
memoryAddress[14] = 32'h00001038; memoryData[14] = 32'h17FFFFFA;
memoryAddress[15] = 32'h0000103C; memoryData[15] = 32'h17FFFFFA;*/
end
endmodule
| 6.897004 |
module ALU (
input1,
input2,
result,
zero,
ALUControl
);
input [31:0] input1, input2;
input [3:0] ALUControl;
output reg [31:0] result;
output reg zero;
always @(input1, input2) begin
case (ALUControl)
//CBZ
4'b0111: begin
if (input1 == 0) begin
result = 32'bx;
zero = 1'b1;
end else begin
result = 32'bx;
zero = 1'b0;
end
end
//ADD, LDUR, STUR
4'b0010: begin
result = input1 + input2;
zero = (result == 0) ? 1'b1 : 1'b0;
end
//SUB
4'b1010: begin
result = input1 - input2;
zero = (result == 0) ? 1'b1 : 1'b0;
end
//AND
4'b0110: begin
result = input1 & input2;
zero = (result == 0) ? 1'b1 : 1'b0;
end
//ORR
4'b0100: begin
result = input1 | input2;
zero = (result == 0) ? 1'b1 : 1'b0;
end
//EOR
4'b1001: begin
result = input1 ^ input2;
zero = (result == 0) ? 1'b1 : 1'b0;
end
//NOR
4'b0101: begin
result = ~(input1 | input2);
zero = (result == 0) ? 1'b1 : 1'b0;
end
//NAND
4'b1100: begin
result = ~(input1 & input2);
zero = (result == 0) ? 1'b1 : 1'b0;
end
//MOV
4'b1101: begin
result = input1; //only one input to ALU, dont care about input2, pass along input 1 to data memory
zero = (result == 0) ? 1'b1 : 1'b0;
end
endcase
end
endmodule
| 7.960621 |
module multiplexer64_32 (
option1,
option2,
out,
select
);
input [31:0] option1, option2;
input select;
output reg [31:0] out;
always @(select, option1, option2) begin
if (select) begin
out = option2;
end else begin
out = option1;
end
end
endmodule
| 7.246896 |
module fetchDecodeReg (
input enable,
input [31:0] thisPCAddressIN,
input [31:0] in,
output reg [31:0] out,
output reg [31:0] thisPCAddressOUT
);
always @(enable) begin
if (enable) begin
out = in;
end
end
endmodule
| 7.450352 |
module DecodeExecuteReg (
input enable,
input [31:0] i1,
input [31:0] i2,
input [31:0] i3,
input i4,
input i5,
input i6,
input i7,
input [4:0] i8,
output reg [31:0] o1,
output reg [31:0] o2,
output reg [31:0] o3,
output reg o4,
output reg o5,
output reg o6,
output reg o7,
output reg [4:0] o8
);
always @(enable) begin
if (enable) begin
o1 = i1;
o2 = i2;
o3 = i3;
o4 = i4;
o5 = i5;
o6 = i6;
o7 = i7;
o8 = i8;
end
end
endmodule
| 6.856126 |
module ExecuteMemoryReg (
input enable,
input [31:0] ALUresultIN,
input [31:0] readdata2IN,
output reg [31:0] ALUresultOUT,
output reg [31:0] readdata2OUT,
input memWriteIN,
output reg memWriteOUT,
input memToRegIN,
output reg memToRegOUT,
input [4:0] writeRegIN,
output reg [4:0] writeRegOUT
);
always @(enable) begin
if (enable) begin
ALUresultOUT = ALUresultIN;
readdata2OUT = readdata2IN;
memWriteOUT = memWriteIN;
memToRegOUT = memToRegIN;
writeRegOUT = writeRegIN;
end
end
endmodule
| 7.836619 |
module MemoryWriteBackReg (
input enable,
input [31:0] readDataIN,
output reg [31:0] readDataOUT,
input [31:0] aluResultIN,
output reg [31:0] aluResultOUT,
input [4:0] destinationRegIN,
output reg [4:0] destinationRegOUT,
input memToRegIN,
output reg memToRegOUT,
input [4:0] writeRegIN,
output reg [4:0] writeRegOUT
);
always @(enable) begin
if (enable) begin
readDataOUT = readDataIN;
aluResultOUT = aluResultIN;
destinationRegOUT = destinationRegIN;
memToRegOUT = memToRegIN;
writeRegOUT = writeRegIN;
end
end
endmodule
| 7.077478 |
module topPlaca (
input CLK_28,
input [17:0] SW,
input [3:0] KEY,
output [17:0] LEDR,
output [7:0] LEDG,
output [7:0] HEX0_D,
output [7:0] HEX1_D,
output [7:0] HEX2_D,
output [7:0] HEX3_D,
output [7:0] HEX4_D,
output [7:0] HEX5_D,
output [7:0] HEX6_D,
output [7:0] HEX7_D,
output teste
);
localparam STEP = 0, AUTO = 1;
wire clk, clkCPU, btStep, btRst, swModo, swDisplay;
wire [7:0] enderecoMemoria, pOUTPUT, pINPUT;
wire [15:0] dadoMemoria;
assign clkCPU = swModo == 1'b0 ? clk : btStep; // seleciona entre o clock automático ou manual
assign pINPUT = SW[7:0];
assign LEDG[0] = clk;
assign LEDG[1] = btStep;
assign LEDG[2] = btRst;
//divClk dvck(.clk_in(CLK_28), .divisor(26'h0), .clk_out(clk)); // remover comentario para simular
divClk dvck (
.clk_in (CLK_28),
.divisor(26'h6ACFC0),
.clk_out(clk)
); // clock de 1 segundo - comentar para simular
//pulse pRst(.clk(CLK_28), .chave(KEY[0]), .tempo(26'h1), .sinal(btRst)); // remover comentario para simular
pulse pRst (
.clk (CLK_28),
.chave(KEY[0]),
.tempo(26'h1AB3F00),
.sinal(btRst)
); // comentar para simular
debounce dbModo (
.clk (CLK_28),
.chave(SW[17]),
.sinal(swModo)
);
debounce dbDisplay (
.clk (CLK_28),
.chave(SW[16]),
.sinal(swDisplay)
);
pulse pStep (
.clk (CLK_28),
.chave(KEY[3]),
.tempo(26'hD59F80),
.sinal(btStep)
);
processador processador (
.clk(clkCPU),
.rst(btRst),
.pINPUT(pINPUT),
.dadoMemoria(dadoMemoria),
.enderecoMemoria(enderecoMemoria),
.pOUTPUT(pOUTPUT)
);
display7seg display0 (
.dp (1),
.dado(dadoMemoria[3:0]),
.leds(HEX0_D)
);
display7seg display1 (
.dp (1),
.dado(dadoMemoria[7:4]),
.leds(HEX1_D)
);
display7seg display2 (
.dp (1),
.dado(dadoMemoria[11:8]),
.leds(HEX2_D)
);
display7seg display3 (
.dp (1),
.dado(dadoMemoria[15:12]),
.leds(HEX3_D)
);
display7seg display4 (
.dp (1),
.dado(enderecoMemoria[3:0]),
.leds(HEX4_D)
);
display7seg display5 (
.dp (1),
.dado(enderecoMemoria[7:4]),
.leds(HEX5_D)
);
display7seg display6 (
.dp (1),
.dado(pOUTPUT[3:0]),
.leds(HEX6_D)
);
display7seg display7 (
.dp (1),
.dado(pOUTPUT[7:4]),
.leds(HEX7_D)
);
assign LEDR = SW;
endmodule
| 6.873084 |
module top (
input extClk,
rst,
output [7:0] port
);
// Wires and regs
wire invClk;
wire clk;
wire hlt;
wire [9:0] instAddr;
wire [40:0] ctrlUnitInstIn;
wire [2:0] waddr, raddr1, raddr2;
wire [3:0] aluOpSel;
wire sto;
wire [31:0] imm;
wire [31:0] db1, db2;
wire [31:0] aluRes;
reg [31:0] aluOp2;
wire aluSrcSel2;
wire carry, sign, zero;
wire [2:0] flagsOut;
wire memAddrSel, stk, ramWen, ld, resAddr;
wire [10:0] memAddr;
reg [31:0] ldMuxOut;
wire [31:0] ramData;
reg [10:0] memMuxAddrOut;
wire [10:0] stkTop;
wire pushPop;
wire jmp;
wire progCtrjmp;
reg [31:0] progCtrMuxOut;
wire [3:0] jmpType;
wire [9:0] jmpLoc;
wire [31:0] resultExt;
wire ctrlUnitMul;
wire clkEn;
// Modules
ctr ProgCtr (
.clk(clk),
.rst(rst),
.en(1'b1),
.dir(1'b1),
.ctrOut(instAddr),
.jmp(progCtrjmp),
.jmpLoc(aluRes[9:0])
);
ctr #(
.width(11)
) stkCtr (
.clk(~clk),
.rst(rst),
.en(stk),
.dir(pushPop),
.ctrOut(stkTop),
.jmp(1'b0),
.jmpLoc(11'h00)
);
irom instRom (
.addr(instAddr),
.data(ctrlUnitInstIn)
);
ctrl ctrl (
.inst(ctrlUnitInstIn),
.rst(rst),
.waddr(waddr),
.raddr1(raddr1),
.raddr2(raddr2),
.aluOpSel(aluOpSel),
.aluOp2(aluSrcSel2),
.imm(imm),
.sto(sto),
.memAddrSel(memAddrSel),
.memAddr(memAddr),
.stk(stk),
.ramWen(ramWen),
.resAddr(resAddr),
.ld(ld),
.pushPop(pushPop),
.jmp(jmp),
.jmpType(jmpType),
.mul(ctrlUnitMul),
.hlt(hlt)
);
regFile regFile (
.waddr(waddr),
.raddr1(raddr1),
.raddr2(raddr2),
.clk(invClk),
.rst(rst),
.sto(sto),
.databus1(db1),
.databus2(db2),
.dataIn(ldMuxOut),
.mul(ctrlUnitMul),
.dataInExt(resultExt),
.port(port)
);
ALU ALU (
.a(db1),
.b(aluOp2),
.opSel(aluOpSel),
.carryFlag(carry),
.signFlag(sign),
.zeroFlag(zero),
.result(aluRes),
.resultExt(resultExt)
);
jmpCtrl jmpCtrl (
.carry(carry),
.sign(sign),
.zero(zero),
.op(jmpType),
.jmpWake(jmp),
.jmp(progCtrjmp)
);
ram ram (
.dataIn(aluRes),
.addr(memMuxAddrOut),
.wen(ramWen),
.clk(clk),
.rst(rst),
.data(ramData)
);
assign clk = ~hlt && extClk;
assign invClk = ~clk;
// MUXes
always @(*) begin
// ALU OP MUX
case (aluSrcSel2)
1'b0: aluOp2 = db2;
1'b1: aluOp2 = imm;
default: aluOp2 = db2;
endcase
// LOAD MUX
case (ld)
0: ldMuxOut = aluRes;
1: ldMuxOut = ramData;
default: ldMuxOut = aluRes;
endcase
// MEM MUX
case (memAddrSel)
1'b0: memMuxAddrOut = memAddr;
1'b1: memMuxAddrOut = stkTop;
default: memMuxAddrOut = memAddr;
endcase
end
endmodule
| 7.233807 |
module RAM_IN (
pix_val,
indx,
wren
);
input [9:0] indx;
output [15:0] pix_val;
output reg wren;
reg [15:0] pix_val;
reg [15:0] in_ram [839:0];
always @(indx) begin
pix_val = in_ram[indx];
wren = pix_val[0];
end
initial begin
$readmemb("EvilSnowman.txt", in_ram);
end
endmodule
| 6.865802 |
module toprobertsons (
input clk,
reset,
input [ 7:0] multiplier, // 8-bit data input to multiplier unit
input [ 7:0] multiplicand, // 8-bit data input to multiplier unit
output [15:0] product, // 16-bit data output of multiplier unit
output done // flag to signal multiplication is complete to testbench
);
// instantiate Robertson's Multiplier
robsmult mult (
clk,
reset,
multiplier,
multiplicand,
product,
done
);
// instantiate signed multipler (used for testing testbench)
//signed_mult mult(product, clk, multiplier, multiplicand);
endmodule
| 6.8185 |
module tops (
input wire clk,
rst,
output wire jump,
branch,
alusrc,
memwrite,
regwrite,
regdst,
memtoreg,
output [2:0] alu_control,
output wire [6:0] seg,
output wire [7:0] ans
);
wire [31:0] pcaddr;
integer cnt; //count
reg clk_1hz;
always @(posedge clk) begin
if (cnt == 32'd100000000) begin
cnt <= 1'b0;
clk_1hz <= ~clk_1hz;
end else cnt <= cnt + 1'b1;
end
top top (
.clk(clk_1hz),
.rst(rst),
.jump(jump),
.branch(branch),
.alusrc(alusrc),
.memwrite(memwrite),
.regwrite(regwrite),
.regdst(regdst),
.memtoreg(memtoreg),
.alu_control(alu_control),
.instr(pcaddr)
);
display display (
.clk(clk),
.rst(rst),
.s (pcaddr),
.seg(seg),
.ans(ans)
);
endmodule
| 6.611875 |
module TopSchematic2(
input_DECa,
input_DECb,
input_DECc,
input_FAa,
input_FAb,
input_FAc,
input_FSa,
input_FSb,
input_FSc,
input_HAa,
input_HAb,
input_COUNTclk,
input_COUNTrst,
input_PISOclk,
input_SIPO,
input_SIPOclk,
input_clkin,
input_BCD,
input_ENC,
input_PENC,
input_PISO,
output_FAs,
output_FAco,
output_FSborrow,
output_FSdiff,
output_HAs,
output_HAco,
output_PISO,
output_clkq,
input_BCDb,
input_BCDc,
output_COUNT,
output_DEC,
output_ENC,
output_PENC,
output_SIPO
);
input wire input_DECa;
input wire input_DECb;
input wire input_DECc;
input wire input_FAa;
input wire input_FAb;
input wire input_FAc;
input wire input_FSa;
input wire input_FSb;
input wire input_FSc;
input wire input_HAa;
input wire input_HAb;
input wire input_COUNTclk;
input wire input_COUNTrst;
input wire input_PISOclk;
input wire input_SIPO;
input wire input_SIPOclk;
input wire input_clkin;
input wire [3:0] input_BCD;
input wire [7:0] input_ENC;
input wire [7:0] input_PENC;
input wire [3:0] input_PISO;
output wire output_FAs;
output wire output_FAco;
output wire output_FSborrow;
output wire output_FSdiff;
output wire output_HAs;
output wire output_HAco;
output wire output_PISO;
output wire output_clkq;
output wire [6:0] input_BCDb;
output wire [6:0] input_BCDc;
output wire [3:0] output_COUNT;
output wire [3:0] output_DEC;
output wire [2:0] output_ENC;
output wire [2:0] output_PENC;
output wire [3:0] output_SIPO;
bcd b2v_inst(
.a(input_BCD),
.b(input_BCDb),
.c(input_BCDc));
clockN b2v_inst1(
.clk(input_clkin),
.q(output_clkq));
decoder24 b2v_inst16(
.a(input_DECa),
.b(input_DECb),
.e(input_DECc),
.c(output_DEC));
encoder83 b2v_inst18(
.i(input_ENC),
.o(output_ENC));
fa b2v_inst19(
.a(input_FAa),
.b(input_FAb),
.ci(input_FAc),
.s(output_FAs),
.co(output_FAco));
priority b2v_inst2(
.sel(input_PENC),
.code(output_PENC));
full_subtractor b2v_inst22(
.a(input_FSa),
.b(input_FSb),
.c(input_FSc),
.diff(output_FSdiff),
.borrow(output_FSborrow));
piso1 b2v_inst25(
.clk(input_PISOclk),
.sin(input_PISO),
.sout(output_PISO));
sipo b2v_inst26(
.sin(input_SIPO),
.clk(input_SIPOclk),
.sout(output_SIPO));
up_counter b2v_inst30(
.clk(input_COUNTclk),
.reset(input_COUNTrst),
.counter(output_COUNT));
ha b2v_inst31(
.a(input_HAa),
.b(input_HAb),
.s(output_HAs),
.co(output_HAco));
endmodule
| 7.29016 |
module topsd (
input clk,
input reset,
input sd_miso,
output sd_cs,
output sd_mosi,
output sd_clk,
// output led,
// output [7:0]o_seg,
// output [7:0]o_sel,
output init_done,
output write_finish,
output read_finish,
input [8:0] raddr,
output [7:0] rdata
);
assign write_finish = 1'b1;
//wire init_done;
wire write_start;
wire [31:0] write_addr;
wire [15:0] write_data;
wire write_busy;
wire write_request;
wire read_start;
wire read_enable;
wire [31:0] read_addr;
wire [15:0] read_data;
wire read_error;
wire [8:0] ram_addr;
//SD
data_gen u_data_gen (
clk,
reset,
init_done,
write_busy,
write_request,
write_start,
write_addr,
write_data,
read_enable,
read_data,
read_start,
read_addr,
read_error,
ram_addr
);
//SDģ
sd_ctrl_top u_sd_ctrl_top (
clk,
reset,
//SDӿ
sd_miso,
sd_clk,
sd_cs,
sd_mosi,
//дSDӿ
write_start,
write_addr,
write_data,
write_busy,
write_request,
//SDӿ
read_start,
read_addr,
read_enable,
read_data,
//ʼ
init_done,
read_finish
);
////ledʾ
//led_alarm u_led_alarm(
// clk,
// reset,
// read_error,
// led
// );
//wire [31:0]rdata;
////7
//seg7x16 seg(
// clk,
// reset,
// rdata,
// o_seg,
// o_sel
//);
//ram
sd_ram ram (
clk,
read_enable,
ram_addr,
read_data,
raddr,
rdata
);
endmodule
| 6.726821 |
module TopSDD (
input clk,
input rst
);
reg [ 7:0] oled_x_dc;
reg [ 7:0] oled_y_data;
reg [15:0] oled_rgb;
reg oled_strobe;
reg oled_setpixel_raw8tx;
wire oled_cs;
wire oled_mosi;
wire oled_sck;
wire oled_dc;
wire oled_rst;
wire oled_vccen;
wire oled_pmoden;
wire oled_ready;
wire oled_valid;
always @(*) begin
oled_strobe = 1'b1;
oled_setpixel_raw8tx = 1'b0;
end
sdd1331_gen_pattern ssd_clk (
.clk(clk),
.out_hcnt(oled_x_dc),
.out_vcnt(oled_y_data),
.rgb(oled_rgb),
.rst(rst)
);
oled_ssd1331 oled_ssd1331_i (
.clk(clk),
.resetn(~rst),
.oled_rst(oled_rst),
.strobe(oled_strobe),
.setpixel_raw8tx(oled_setpixel_raw8tx),
.x_dc(oled_x_dc),
.y_data(oled_y_data),
.rgb(oled_rgb),
.ready(oled_ready),
.valid(oled_valid),
.spi_cs(oled_cs),
.spi_dc(oled_dc),
.spi_mosi(oled_mosi),
.spi_sck(oled_sck),
.vccen(oled_vccen),
.pmoden(oled_pmoden)
);
`ifdef COCOTB_SIM
`ifndef SCANNED
`define SCANNED
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, TopSDD);
#1;
end
`endif
`endif
endmodule
| 7.135786 |
module topServo (
input clk_i,
output reg srv_o
);
reg reset;
rst_gen rst_inst (
.clk_i(clk_i),
.rst_i(1'b0),
.rst_o(reset)
);
SimpleServo sso (
.clk_i(clk_i),
.rst_i(reset),
.en_i(1'b1),
.position_i(8'hFF),
.srv_o(srv_o)
);
endmodule
| 6.837843 |
module topset (
clk,
rst,
start,
Done,
SEG,
AN
);
input clk, rst, start;
output Done;
output [7:0] SEG;
output [7:0] AN;
wire clk_N1, clk_N2;
wire [31:0] sum_out;
wire ld_sum, ld_next;
wire sum_sel, next_sel;
wire a_sel;
wire next_zero;
divider Divider1 (
.clk(clk),
.frequency(1),
.clk_N(clk_N1)
);
divider Divider2 (
.clk(clk),
.frequency(2000),
.clk_N(clk_N2)
);
show_numbers SHOW (
.clk(clk_N2),
.sum_out(sum_out),
.AN(AN),
.SEG(SEG)
);
fsm_controller FSM1 (
.clk(clk_N1),
.rst(rst),
.start(start),
.next_zero(next_zero),
.ld_sum(ld_sum),
.ld_next(ld_next),
.sum_sel(sum_sel),
.next_sel(next_sel),
.a_sel(a_sel),
.done(Done)
);
data_path_top DST1 (
.clk(clk_N1),
.rst(rst),
.ld_sum(ld_sum),
.ld_next(ld_next),
.sum_sel(sum_sel),
.next_sel(next_sel),
.a_sel(a_sel),
.next_zero(next_zero),
.sum_out(sum_out)
);
endmodule
| 7.127837 |
module TopStateMachine (
input clk,
input btnUDLR,
input btnC,
input WinDetect,
input LossDetect,
output reset,
output btnCenable,
output btnUDLRenable,
output TimerEnable,
output flashSlug,
output flashBorder,
output [3:0] state
);
wire [3:0] Q;
wire [3:0] D;
TopStateMachineLogic TopStateMachineLogic (
.clk(clk),
.btnUDLR(btnUDLR),
.btnC(btnC),
.WinDetect(WinDetect),
.LossDetect(LossDetect),
.Q(Q),
.reset(reset),
.btnCenable(btnCenable),
.btnUDLRenable(btnUDLRenable),
.TimerEnable(TimerEnable),
.flashSlug(flashSlug),
.flashBorder(flashBorder),
.D(D)
);
FDRE #(
.INIT(1'b1)
) Q0_FF (
.C (clk),
.CE(1'b1),
.D (D[0]),
.Q (Q[0])
);
FDRE #(
.INIT(1'b0)
) Q1_FF (
.C (clk),
.CE(1'b1),
.D (D[1]),
.Q (Q[1])
);
FDRE #(
.INIT(1'b0)
) Q2_FF (
.C (clk),
.CE(1'b1),
.D (D[2]),
.Q (Q[2])
);
FDRE #(
.INIT(1'b0)
) Q3_FF (
.C (clk),
.CE(1'b1),
.D (D[3]),
.Q (Q[3])
);
assign state[0] = Q[0];
assign state[1] = Q[1];
assign state[2] = Q[2];
assign state[3] = Q[3];
endmodule
| 6.500673 |
module TopStateMachineLogic (
input clk,
input btnUDLR,
input btnC,
input WinDetect,
input LossDetect,
input [3:0] Q,
output reset,
output btnCenable,
output btnUDLRenable,
output TimerEnable,
output flashSlug,
output flashBorder,
output [3:0] D
);
assign D[0] = (Q[0] & ~WinDetect & ~LossDetect & ~btnC & ~btnUDLR) | (Q[0] & ~WinDetect & ~LossDetect & btnC) | (Q[2] & btnC) |
(Q[3] & btnC) | (Q[0] & ~WinDetect & LossDetect) | (Q[0] & WinDetect & LossDetect) | (Q[0] & WinDetect & ~LossDetect);
assign D[1] = (Q[0] & ~WinDetect & ~LossDetect & ~btnC & btnUDLR) | (Q[1] & ~WinDetect & ~LossDetect);
assign D[2] = (Q[1] & ~WinDetect & LossDetect) | (Q[2] & ~btnC);
assign D[3] = (Q[1] & WinDetect & ~LossDetect) | (Q[3] & ~btnC);
assign reset = Q[0];
assign btnCenable = ~Q[1];
assign btnUDLRenable = Q[0] | Q[1];
assign TimerEnable = Q[1];
assign flashSlug = Q[2];
assign flashBorder = Q[3];
endmodule
| 6.500673 |
module TopSystem(
input clk
,input PS2Clk
,input PS2Data
,output Hsync
,output Vsync
,output [3:0] vgaRed
,output [3:0] vgaGreen
,output [3:0] vgaBlue
,output [6:0] seg
,output [3:0] an
,output dp
);
wire [15:0] key;
/*--Keyboard--*/
kb_top keyboard_handler(
.clk(clk),
.PS2Clk(PS2Clk),
.PS2Data(PS2Data),
.keycodev(key)
);
wire [2:0] state;
wire reset;
wire [6:0] hpMonster,hpPlayer;
wire [9:0] xPlayer,yPlayer;
wire [59:0] pos; //bullet pos
wire [1:0] pugType;
wire [1:0] milkStatus;
wire endFlag;
/*-Seven segment display-*/
sevenSeg segDisp(
.clk(clk),
.num({2'b00,pugType,key[11:0]}),
.seg(seg),
.an(an),
.dp(dp)
);
/*--logic--*/
game_logic logic(
.clk(clk),
.key(key),
.state(state),
.pugType(pugType),
.reset(reset),
.xPlayer(xPlayer),
.yPlayer(yPlayer),
.hpPlayer(hpPlayer),
.hpMonster(hpMonster),
.pos(pos),
.milkStatus(milkStatus)
);
/*--vga--*/
vga image_handler(
.clk(clk),
.reset(reset),
.screen_state(state),
.xPlayer(xPlayer),
.yPlayer(yPlayer),
.hpPlayer(hpPlayer),
.hpMonster(hpMonster),
.pos(pos),
.pugType(pugType),
.milkStatus(milkStatus),
.Hsync(Hsync),
.Vsync(Vsync),
.vgaRed(vgaRed),
.vgaGreen(vgaGreen),
.vgaBlue(vgaBlue)
);
endmodule
| 7.655706 |
module toptb ();
reg HCLK;
reg HRESETn = 0;
wire [31:0] pwdata, prdata, paddr;
wire [2:0] psel;
wire pwrite, penable;
wire [31:0] pwdatao, prdatao, paddro;
wire [2:0] pselo;
wire pwriteo, penableo;
wire [1:0] Hresp;
wire hwrite;
parameter cycle = 10;
ahbmaster MASTER (
.HCLK(HCLK),
.HRESETn(HRESETn),
.HWRITE(hwrite),
.HREADYin(BRIDGETOP.HREADYin),
.HADDR(BRIDGETOP.HADDR),
.HWDATA(BRIDGETOP.HWDATA),
.HRDATA(BRIDGETOP.HRDATA),
.HRESP(Hresp),
.HREADYout(BRIDGETOP.HREADYout),
.HTRANS(BRIDGETOP.HTRANS)
);
bridgetop BRIDGETOP (
.HCLK(HCLK),
.HRESETn(HRESETn),
.HADDR(MASTER.HADDR),
.HWDATA(MASTER.HWDATA),
.HWRITE(MASTER.HWRITE),
.HTRANS(MASTER.HTRANS),
.HREADYin(MASTER.HREADYin),
.HREADYout(MASTER.HREADYout),
.HRDATA(MASTER.HRDATA),
.HRESP(Hresp),
.PENABLE(penable),
.PWRITE(pwrite),
.PSEL(psel),
.PWDATA(pwdata),
.PRDATA(prdatao),
.PADDR(paddr)
);
apbif APBINTERFACE (
.PENABLEin(penable),
.PWRITEin(pwrite),
.PSELin(psel),
.PADDRin(paddr),
.PWDATAin(pwdata),
.PENABLE(penableo),
.PWRITE(pwriteo),
.PSEL(pselo),
.PADDR(paddro),
.PWDATA(pwdatao),
.PRDATA(prdatao)
);
//testing
//clock generation
always begin
#5;
HCLK = 1'b1;
#5;
HCLK = ~HCLK;
end
//reset task
task rst();
begin
HRESETn = 1'b0;
#5;
HRESETn = 1'b1;
end
endtask
initial begin
#20;
rst();
MASTER.singleread();
#100 $finish();
end
endmodule
| 6.637427 |
module topteset ();
reg clk_p;
reg clk_n;
// reg en;
reg start;
reg stop;
reg enable;
reg reset;
// reg t;
wire [39:0] TDC_out;
wire valid;
wire out;
integer f, j;
real i;
TOP test (
.clk_p(clk_p),
.clk_n(clk_n),
.start(start),
.stop(stop),
.reset_button(reset),
.enable(enable),
.tx(out)
);
// fine_tdc test (
// .trigger (start),
// .clock (clk_p),
// .latched_output (out)
// );
initial begin
clk_p = 1'b1;
forever #2.5 clk_p = ~clk_p;
end
initial begin
clk_n = 1'b0;
start = 1'b0;
stop = 1'b0;
forever #2.5 clk_n = ~clk_n;
end
// initial begin
// forever #100000 start = ~start;
// end
// initial begin
// #100
// forever #100000 stop = ~stop;
// end
initial begin
#10 enable = 0;
start = 0;
stop = 0;
reset = 0;
#500 reset = 1;
#30 reset = 0;
#394.75
for (j = 1; j < 500; j = j + 1) begin
#200 start = 1;
#j stop = 1;
#15 stop = 0;
start = 0;
end
// for (i = 0.01; i<1; i=i+0.05) begin
// #50
// #i
// start = 1;
// #5
// stop = 1;
// #15
// stop = 0;
// start = 0;
// end
// end
// always @(posedge valid) begin
// f = $fopen("output.txt","a");
// $fwrite(f,"%b\n",TDC_out);
// $fclose(f);
end
endmodule
| 6.549927 |
module TopTracing (
input clk,
input SpeedControl,
input En_Tracing,
input [2:0] PathDectSignal,
input nCR_Avoid,
input [1:0] AvoidSignal,
output [3:0] Led_Direction,
output Speed_Wheel_1,
Speed_Wheel_2,
output [1:0] Control_Wheel_1,
output [1:0] Control_Wheel_2
);
PWM Trace0 (
clk,
SpeedControl,
pwm_250,
pwm_220,
pwm_150,
pwm_0
);
TraceRoute Trace1 (
clk,
En_Tracing,
nCR_Avoid,
AvoidSignal,
PathDectSignal,
pwm_250,
pwm_220,
pwm_150,
pwm_0,
Led_Direction,
Speed_Wheel_1,
Speed_Wheel_2,
Control_Wheel_1,
Control_Wheel_2
);
endmodule
| 6.502608 |
module topUnit (
input clk,
input rst
);
wire [7:0] instrCode, pcIn, pcOut, immOut, pc_EX_WB, immOut_EX_WB;
wire branch, branch_EX_WB, branch_ID_EX;
wire [7:0] pc_ID_EX;
wire [7:0] jmpAddr;
wire flush;
assign flush = branch;
assign pcIn = branch ? (jmpAddr) : (pcOut + 1);
// assign pcIn = pcOut + 1;
//Instruction fetch
pc programCounter (
clk,
rst,
pcIn,
pcOut
);
instrMem IM (
clk,
rst,
pcOut,
instrCode
);
wire [7:0] instrCode_IF_ID, pc_IF_ID;
// IF-ID pipeline
IF_ID_pipeline ifid (
clk,
rst,
flush,
instrCode,
pcOut,
instrCode_IF_ID,
pc_IF_ID
);
//Instruction decode
wire [1:0] opcode, immSel;
wire [2:0] readReg1, readReg2, writeReg;
wire regWrite, immToReg, aluControl, regWrite_EX_WB;
wire [7:0] readData1, readData2, writeData_EX_WB;
wire [2:0] rd_EX_WB;
assign opcode = instrCode_IF_ID[7:6];
assign readReg2 = instrCode_IF_ID[2:0];
assign readReg1 = instrCode_IF_ID[5:3];
assign writeReg = instrCode_IF_ID[5:3];
registerFile regBank (
clk,
rst,
readReg1,
readReg2,
rd_EX_WB,
regWrite_EX_WB,
readData1,
readData2,
writeData_EX_WB
);
controlUnit ctrlSignal (
opcode,
immSel,
aluControl,
regWrite,
immToReg,
branch
);
immGen imm (
instrCode_IF_ID,
immSel,
immOut
);
assign jmpAddr = pc_IF_ID + immOut;
wire aluControl_ID_EX;
wire [2:0] rd_ID_EX, rs1_ID_EX, rs2_ID_EX;
wire regWrite_ID_EX;
wire immToReg_ID_EX;
wire [7:0] immOut_ID_EX, data1_ID_EX, data2_ID_EX;
wire [1:0] opcode_ID_EX;
//ID-EX pipeline
ID_EX_pipeline idex (
clk,
rst,
aluControl,
readData1,
readData2,
jmpAddr,
writeReg,
readReg1,
readReg2,
regWrite,
branch,
immToReg,
immOut,
opcode,
aluControl_ID_EX,
data1_ID_EX,
data2_ID_EX,
pc_ID_EX,
rd_ID_EX,
rs1_ID_EX,
rs2_ID_EX,
regWrite_ID_EX,
branch_ID_EX,
immToReg_ID_EX,
immOut_ID_EX,
opcode_ID_EX
);
// Execute
wire [7:0] aluResult;
wire [7:0] aluIn1, aluIn2;
//forwarding
wire [2:0] forward;
wire [7:0] aluResult_EX_WB;
wire [1:0] opcode_EX_WB;
forwardingUnit fwd (
rs1_ID_EX,
rs2_ID_EX,
rd_EX_WB,
data1_ID_EX,
data2_ID_EX,
aluResult_EX_WB,
immOut_EX_WB,
regWrite_EX_WB,
opcode_EX_WB,
forward,
aluIn1,
aluIn2
);
ALU ex (
aluControl_ID_EX,
aluIn1,
aluIn2,
aluResult
);
wire immToReg_EX_WB;
// EX-WB stage
EX_WB_pipeline exwb (
clk,
rst,
pc_ID_EX,
aluResult,
immOut_ID_EX,
branch_ID_EX,
regWrite_ID_EX,
immToReg_ID_EX,
rd_ID_EX,
opcode_ID_EX,
pc_EX_WB,
aluResult_EX_WB,
immOut_EX_WB,
branch_EX_WB,
regWrite_EX_WB,
immToReg_EX_WB,
rd_EX_WB,
opcode_EX_WB
);
//Writeback
assign writeData_EX_WB = immToReg_EX_WB ? immOut_EX_WB : aluResult_EX_WB;
endmodule
| 7.501513 |
module PC_PCArthmetic (
clk,
startingPC,
address,
signExtend,
unconditionalBranchFlag,
branchFlag,
zeroFlag
);
input clk;
input [31:0] signExtend; //sign extended insturction
input unconditionalBranchFlag; //flag from controller
input branchFlag; //flag from controller
input zeroFlag; // flag from ALU
output reg [31:0] address; //address of current instruction
input [31:0] startingPC;
reg [31:0] nextPC, pcPlus4;
reg pcplus4, select, andResult, orResult;
reg [61:0] branchPC;
initial begin
select = 0;
nextPC = startingPC;
pcPlus4 = startingPC + 4;
end
always @(posedge clk) begin
address = (select == 1) ? branchPC : pcPlus4;
pcPlus4 = address + 4;
end
always @(signExtend) begin
branchPC = address + signExtend;
end
always @(zeroFlag, branchFlag, unconditionalBranchFlag) begin
andResult = zeroFlag & branchFlag;
orResult = andResult | unconditionalBranchFlag;
select = orResult;
end
endmodule
| 7.379809 |
module instructionCache (
output reg [31:0] data,
output reg missFlag,
input [31:0] PC,
input [31:0] inputData,
input writeData
); //inputData and writeData would be used if we had an imperfect cache that would go to a lower level and get more data to load into this iCache. Here we include but ignore it.
reg [31:0] memoryAddress[0:15];
reg [31:0] memoryData[0:15]; //could be expanded, but here we just use 16
reg [6:0] i;
always @(PC, inputData) begin : search
for (i = 0; i < 16; i = i + 1) begin //how many lines there are
if (PC == memoryAddress[i]) begin
data = memoryData[i];
missFlag = 0;
disable search;
end //if PC==
end //for
//if you reach here, you didn't find it
data = 0;
missFlag = 1;
end //always
initial begin
memoryAddress[0] = 32'h00001000;
memoryData[0] = 32'hF8400281; //LDUR R1 [R20, #0]
memoryAddress[1] = 32'h00001004;
memoryData[1] = 32'h8B010022; // ADD R2, R1, R1
memoryAddress[2] = 32'h00001008;
memoryData[2] = 32'hD1000333; //SUBI R19, R25, #0
memoryAddress[3] = 32'h0000100C;
memoryData[3] = 32'hB40000E3; //CBZ R3, #7
memoryAddress[4] = 32'h00001010;
memoryData[4] = 32'h91002294; //ADDI R20, R20, #8
memoryAddress[5] = 32'h00001014;
memoryData[5] = 32'hF81F4281; //STUR R1, [R20 #-12]
//memoryAddress[6] = 32'h00001018; memoryData[6] = 32'hF85F4284; //LDUR R4, [R20 #-12]
memoryAddress[6] = 32'h00001018;
memoryData[6] = 32'h17FFFFFA; //B #3FFFFFA (-6)
memoryAddress[7] = 32'h0000101C;
memoryData[7] = 32'h17FFFFFA;
memoryAddress[8] = 32'h00001020;
memoryData[8] = 32'h17FFFFFA;
memoryAddress[9] = 32'h00001024;
memoryData[9] = 32'h17FFFFFA;
memoryAddress[10] = 32'h00001028;
memoryData[10] = 32'h17FFFFFA;
memoryAddress[11] = 32'h0000102C;
memoryData[11] = 32'h17FFFFFA;
memoryAddress[12] = 32'h00001030;
memoryData[12] = 32'h17FFFFFA;
memoryAddress[13] = 32'h00001034;
memoryData[13] = 32'h17FFFFFA;
memoryAddress[14] = 32'h00001038;
memoryData[14] = 32'h17FFFFFA;
memoryAddress[15] = 32'h0000103C;
memoryData[15] = 32'h17FFFFFA;
end
endmodule
| 6.897004 |
module ALU (
input1,
input2,
result,
zero,
ALUControl
);
input [31:0] input1, input2;
input [3:0] ALUControl;
output reg [31:0] result;
output reg zero;
always @(input1, input2) begin
case (ALUControl)
//CBZ
4'b0111: begin
if (input1 == 0) begin
result = 32'bx;
zero = 1'b1;
end else begin
result = 32'bx;
zero = 1'b0;
end
end
//ADD, LDUR, STUR
4'b0010: begin
result = input1 + input2;
zero = (result == 0) ? 1'b1 : 1'b0;
end
//SUB
4'b1010: begin
result = input1 - input2;
zero = (result == 0) ? 1'b1 : 1'b0;
end
//AND
4'b0110: begin
result = input1 & input2;
zero = (result == 0) ? 1'b1 : 1'b0;
end
//ORR
4'b0100: begin
result = input1 | input2;
zero = (result == 0) ? 1'b1 : 1'b0;
end
//EOR
4'b1001: begin
result = input1 ^ input2;
zero = (result == 0) ? 1'b1 : 1'b0;
end
//NOR
4'b0101: begin
result = ~(input1 | input2);
zero = (result == 0) ? 1'b1 : 1'b0;
end
//NAND
4'b1100: begin
result = ~(input1 & input2);
zero = (result == 0) ? 1'b1 : 1'b0;
end
//MOV
4'b1101: begin
result = input1; //only one input to ALU, dont care about input2, pass along input 1 to data memory
zero = (result == 0) ? 1'b1 : 1'b0;
end
endcase
end
endmodule
| 7.960621 |
module multiplexer64_32 (
option1,
option2,
out,
select
);
input [31:0] option1, option2;
input select;
output reg [31:0] out;
always @(select, option1, option2) begin
if (select) begin
out = option2;
end else begin
out = option1;
end
end
endmodule
| 7.246896 |
module TopWrapper (
// inputs
input CLK,
input RESET,
input [7:0] SWITCHES,
//inouts
inout CLK_MOUSE,
inout DATA_MOUSE,
//outputs
output [7:0] StatusLED,
output [3:0] SEG_SELECT,
output [7:0] DEC_OUT,
output [7:0] COLOUR_OUT,
output HS_OUT,
output VS_OUT,
output IR_LED
);
//////////////////////////////////////////////////////////////////////////////////
//Interconnecting wires
//
//ROM buses
wire [7:0] ROM_DATA;
wire [7:0] ROM_ADDR;
//Processor buses
wire [7:0] BUS_DATA;
wire [7:0] BUS_ADDR;
wire BUS_WE;
//Interrupts
wire [1:0] BUS_INTERRUPTS_RAISE;
wire [1:0] BUS_INTERRUPTS_ACK;
//////////////////////////////////////////////////////////////////////////////////
//Instantiating peripherals
//
//Instantiate RAM
RAM RAM (
.CLK(CLK),
.BUS_DATA(BUS_DATA),
.BUS_ADDR(BUS_ADDR),
.BUS_WE(BUS_WE)
);
//Instantiate ROM
ROM ROM (
.CLK (CLK),
.DATA(ROM_DATA),
.ADDR(ROM_ADDR)
);
//Instantiate CPU
CPU CPU (
.CLK(CLK),
.RESET(RESET),
.BUS_DATA(BUS_DATA),
.BUS_ADDR(BUS_ADDR),
.BUS_WE(BUS_WE),
.ROM_ADDRESS(ROM_ADDR),
.ROM_DATA(ROM_DATA),
.BUS_INTERRUPTS_RAISE(BUS_INTERRUPTS_RAISE),
.BUS_INTERRUPTS_ACK(BUS_INTERRUPTS_ACK)
);
//Instantiate VGA peripheral
VGA_Wrapper VGA (
.CLK(CLK),
.RESET(RESET),
.BUS_ADDR(BUS_ADDR),
.BUS_DATA(BUS_DATA),
.BUS_WE(BUS_WE),
.COLOUR_OUT(COLOUR_OUT),
.HS_OUT(HS_OUT),
.VS_OUT(VS_OUT)
);
//Instantiate IR peripheral
IRWrapper IR (
.CLK(CLK),
.RST(RESET),
.DATA_IN(BUS_DATA),
.ADDR_IN(BUS_ADDR),
.BUS_WE(BUS_WE),
// .COLOUR_SEL(COLOUR_SEL),
.IR_LED(IR_LED)
);
//Instantiate MOUSE peripheral
MouseTransceiver MOUSE (
.CLK_MOUSE(CLK_MOUSE),
.DATA_MOUSE(DATA_MOUSE),
.CLK(CLK),
.RESET(RESET),
.BUS_DATA(BUS_DATA),
.BUS_ADDR(BUS_ADDR),
.BUS_WE(BUS_WE),
.BUS_INTERRUPT_ACK(BUS_INTERRUPTS_ACK[0]),
.BUS_INTERRUPT_RAISE(BUS_INTERRUPTS_RAISE[0])
);
//Instantiate TIMER peripheral
Timer TIMER (
.CLK(CLK),
.RST(RESET),
.BUS_ADDR(BUS_ADDR),
.BUS_DATA(BUS_DATA),
.BUS_WE(BUS_WE),
.BUS_INTERRUPT_ACK(BUS_INTERRUPTS_ACK[1]),
.BUS_INTERRUPT_RAISE(BUS_INTERRUPTS_RAISE[1])
);
//Instantiate SEG7 peripheral
Seg7Wrapper SEG7 (
.CLK(CLK),
.RESET(RESET),
.BUS_WE(BUS_WE),
.BUS_DATA(BUS_DATA),
.BUS_ADDR(BUS_ADDR),
.SEG_SELECT(SEG_SELECT),
.DEC_OUT(DEC_OUT)
);
//Instantiate LED peripheral
StatusLED LED (
.CLK(CLK),
.RESET(RESET),
.BUS_DATA(BUS_DATA),
.BUS_ADDR(BUS_ADDR),
.BUS_WE(BUS_WE),
.StatusLED(StatusLED)
);
//Instantiate SWITCHES
Switches SW (
.CLK(CLK),
.RST(RESET),
.BUS_DATA(BUS_DATA),
.BUS_ADDR(BUS_ADDR),
.BUS_WE(BUS_WE),
.SWITCH_VALUE(SWITCHES)
);
endmodule
| 6.717782 |
module mux (
sel,
res
);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res) begin
case (sel)
3'b000: res = 8'b00000001;
3'b001: res = 8'b00000010;
3'b010: res = 8'b00000100;
3'b011: res = 8'b00001000;
3'b100: res = 8'b00010000;
3'b101: res = 8'b00100000;
3'b110: res = 8'b01000000;
default: res = 8'b10000000;
endcase
end
endmodule
| 7.856429 |
module top_1000 (
input clk,
input rst_n,
input [7:0] data_in,
output [3:0] decision,
output finish
);
wire signed [11:0] conv_out_1, conv_out_2, conv_out_3;
wire signed [11:0] conv2_out_1, conv2_out_2, conv2_out_3;
wire signed [11:0] max_value_1, max_value_2, max_value_3;
wire signed [11:0] max2_value_1, max2_value_2, max2_value_3;
wire signed [11:0] fc_out_data;
wire valid_out_1, valid_out_2, valid_out_3, valid_out_4, valid_out_5;
// Module Instantiation
conv1_layer conv1_layer (
.clk(clk),
.rst_n(rst_n),
.data_in(data_in),
.conv_out_1(conv_out_1),
.conv_out_2(conv_out_2),
.conv_out_3(conv_out_3),
.valid_out_conv(valid_out_1)
);
maxpool_relu #(
.CONV_BIT(12),
.HALF_WIDTH(12),
.HALF_HEIGHT(12),
.HALF_WIDTH_BIT(4)
) maxpool_relu_1 (
.clk(clk),
.rst_n(rst_n),
.valid_in(valid_out_1),
.conv_out_1(conv_out_1),
.conv_out_2(conv_out_2),
.conv_out_3(conv_out_3),
.max_value_1(max_value_1),
.max_value_2(max_value_2),
.max_value_3(max_value_3),
.valid_out_relu(valid_out_2)
);
conv2_layer conv2_layer (
.clk(clk),
.rst_n(rst_n),
.valid_in(valid_out_2),
.max_value_1(max_value_1),
.max_value_2(max_value_2),
.max_value_3(max_value_3),
.conv2_out_1(conv2_out_1),
.conv2_out_2(conv2_out_2),
.conv2_out_3(conv2_out_3),
.valid_out_conv2(valid_out_3)
);
maxpool_relu #(
.CONV_BIT(12),
.HALF_WIDTH(4),
.HALF_HEIGHT(4),
.HALF_WIDTH_BIT(3)
) maxpool_relu_2 (
.clk(clk),
.rst_n(rst_n),
.valid_in(valid_out_3),
.conv_out_1(conv2_out_1),
.conv_out_2(conv2_out_2),
.conv_out_3(conv2_out_3),
.max_value_1(max2_value_1),
.max_value_2(max2_value_2),
.max_value_3(max2_value_3),
.valid_out_relu(valid_out_4)
);
fully_connected #(
.INPUT_NUM (48),
.OUTPUT_NUM(10),
.DATA_BITS (8)
) fully_connected (
.clk(clk),
.rst_n(rst_n),
.valid_in(valid_out_4),
.data_in_1(max2_value_1),
.data_in_2(max2_value_2),
.data_in_3(max2_value_3),
.data_out(fc_out_data),
.valid_out_fc(valid_out_5)
);
comparator comparator (
.clk(clk),
.rst_n(rst_n),
.valid_in(valid_out_5),
.data_in(fc_out_data),
.decision(decision),
.valid_out(finish)
);
endmodule
| 6.737425 |
module top8_1step_CLA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
processing_block_8_1step processing_block_8_1step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CLA16 CLA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.479229 |
module top8_1step_RCA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
processing_block_8_1step processing_block_8_1step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
RCA16 RCA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.090952 |
module top8_1step_CSelA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
processing_block_8_1step processing_block_8_1step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CSelA16 CSelA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 7.915499 |
module top8_1step_CSkipA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
processing_block_8_1step processing_block_8_1step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CSkipA16 CSkipA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 7.915499 |
module top8_1step_KSA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
processing_block_8_1step processing_block_8_1step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
KSA16 KSA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 7.797858 |
module top8_1step_CLA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P(p)
);
processing_block_8_1step processing_block_8_1step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CLA16 CLA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.479229 |
module top8_1step_RCA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P(p)
);
processing_block_8_1step processing_block_8_1step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
RCA16 RCA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.090952 |
module top8_1step_CSelA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P(p)
);
processing_block_8_1step processing_block_8_1step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CSelA16 CSelA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 7.915499 |
module top8_1step_CSkipA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P(p)
);
processing_block_8_1step processing_block_8_1step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CSkipA16 CSkipA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 7.915499 |
module top8_1step_KSA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P(p)
);
processing_block_8_1step processing_block_8_1step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
KSA16 KSA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 7.797858 |
module top16_1step_CLA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_1step processing_block_16_1step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CLA32 CLA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 6.897723 |
module top16_1step_RCA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_1step processing_block_16_1step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
RCA32 RCA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.289314 |
module top16_1step_CSelA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_1step processing_block_16_1step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSelA32 CSelA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 6.897723 |
module top16_1step_CSkipA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_1step processing_block_16_1step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSkipA32 CSkipA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 6.897723 |
module top16_1step_KSA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_1step processing_block_16_1step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
KSA32 KSA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 6.855856 |
module top16_1step_CLA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_1step processing_block_16_1step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CLA32 CLA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 6.897723 |
module top16_1step_RCA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_1step processing_block_16_1step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
RCA32 RCA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.289314 |
module top16_1step_CSelA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_1step processing_block_16_1step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSelA32 CSelA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 6.897723 |
module top16_1step_CSkipA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_1step processing_block_16_1step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSkipA32 CSkipA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 6.897723 |
module top16_1step_KSA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_1step processing_block_16_1step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
KSA32 KSA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 6.855856 |
module top (
input [7:0] i,
output o
);
always @*
case (i[6:3])
4: o <= i[0];
3: o <= i[2];
7: o <= i[3];
default: o <= 1'b0;
endcase
endmodule
| 7.233807 |
module Top_2048 (
input wire clk,
input wire PS2KeyboardClk,
input wire PS2KeyboardData,
input wire [4:0] btn,
output wire Hsync,
output wire Vsync,
output wire [2:0] vgaRed,
output wire [2:0] vgaGreen,
output wire [2:0] vgaBlue
);
wire clk25;
wire [7:0] data;
wire win;
wire isEnd;
wire [63:0] map;
wire vidon;
wire [9:0] hc;
wire [9:0] vc;
wire [15:0] addrNumber;
wire [15:0] addrTitle;
wire info_number;
wire info_title;
wire [7:0] info_win;
wire [7:0] info_end;
wire clk_100ms;
wire [15:0] xkey;
clkdiv U0 (
.clk100(clk),
.clk25 (clk25)
);
vga_640x480 U1 (
.clk(clk25),
.Hsync(Hsync),
.Vsync(Vsync),
.hc(hc),
.vc(vc),
.vidon(vidon)
);
vga_display U2 (
.clk(clk25),
.vidon(vidon),
.data(data),
.vgaRed(vgaRed),
.vgaGreen(vgaGreen),
.vgaBlue(vgaBlue)
);
control U3 (
.clk(clk25),
.vidon(vidon),
.hc(hc),
.vc(vc),
.win(win),
.isEnd(isEnd),
.map(map),
.data(data),
.addrNumber(addrNumber),
.addrTitle(addrTitle),
.info_number(info_number),
.info_title(info_title),
.info_win(info_win),
.info_end(info_end)
);
number U4 (
.addra(addrNumber),
.clka (clk25),
.douta(info_number)
);
title U5 (
.addra(addrTitle),
.clka (clk25),
.douta(info_title)
);
move_event U6 (
.clk (clk_100ms),
.btn (btn),
.xkey (xkey),
.win (win),
.isEnd(isEnd),
.map (map)
);
clkdiv_100ms U7 (
.clk(clk),
.clk_100ms(clk_100ms)
);
keyboard U8 (
.clk25(clk25),
.PS2C (PS2KeyboardClk),
.PS2D (PS2KeyboardData),
.xkey (xkey)
);
endmodule
| 7.877243 |
module top8_2step_CLA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
processing_block_8_2step processing_block_8_2step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CLA16 CLA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.828885 |
module top8_2step_RCA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
processing_block_8_2step processing_block_8_2step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
RCA16 RCA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.164733 |
module top8_2step_CSelA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
processing_block_8_2step processing_block_8_2step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CSelA16 CSelA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.199148 |
module top8_2step_CSkipA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
processing_block_8_2step processing_block_8_2step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CSkipA16 CSkipA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.199148 |
module top8_2step_KSA16 (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8 generate_partial_products_8 (
.x(x),
.y(y),
.P(p)
);
processing_block_8_2step processing_block_8_2step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
KSA16 KSA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 7.841116 |
module top8_2step_CLA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P(p)
);
processing_block_8_2step processing_block_8_2step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CLA16 CLA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.828885 |
module top8_2step_RCA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P(p)
);
processing_block_8_2step processing_block_8_2step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
RCA16 RCA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.164733 |
module top8_2step_CSelA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P(p)
);
processing_block_8_2step processing_block_8_2step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CSelA16 CSelA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.199148 |
module top8_2step_CSkipA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P(p)
);
processing_block_8_2step processing_block_8_2step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
CSkipA16 CSkipA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 8.199148 |
module top8_2step_KSA16_trunc (
input [ 7:0] x,
input [ 7:0] y,
output [16:0] prod
);
wire p[7:0][7:0];
wire [15:0] PRE1;
wire [15:0] PRE2;
assign PRE1[15] = 1'b0;
assign PRE2[15] = 1'b0;
generate_partial_products_8_trunc generate_partial_products_8_trunc (
.x(x),
.y(y),
.P(p)
);
processing_block_8_2step processing_block_8_2step (
.p(p),
.out1(PRE1[14:0]),
.out2(PRE2[14:0])
);
KSA16 KSA16 (
.sum(prod[15:0]),
.cout(prod[16]),
.a(PRE1),
.b(PRE2)
); //CLA16 RCA16 CSelA16 CSkipA16 KSA16
endmodule
| 7.841116 |
module top16_2step_CLA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_2step processing_block_16_2step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CLA32 CLA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.320932 |
module top16_2step_RCA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_2step processing_block_16_2step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
RCA32 RCA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.496826 |
module top16_2step_CSelA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_2step processing_block_16_2step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSelA32 CSelA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.320932 |
module top16_2step_CSkipA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_2step processing_block_16_2step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSkipA32 CSkipA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.320932 |
module top16_2step_KSA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_2step processing_block_16_2step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
KSA32 KSA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 6.952091 |
module top16_2step_CLA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_2step processing_block_16_2step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CLA32 CLA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.320932 |
module top16_2step_RCA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_2step processing_block_16_2step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
RCA32 RCA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.496826 |
module top16_2step_CSelA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_2step processing_block_16_2step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSelA32 CSelA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.320932 |
module top16_2step_CSkipA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_2step processing_block_16_2step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSkipA32 CSkipA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.320932 |
module top16_2step_KSA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_2step processing_block_16_2step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
KSA32 KSA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 6.952091 |
module mux (
sel,
res
);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel) begin
case (sel)
3'b000: res = 8'b00000001;
// unused decoder output
3'b001: res = 8'bxxxxxxxx;
3'b010: res = 8'b00000100;
3'b011: res = 8'b00001000;
3'b100: res = 8'b00010000;
3'b101: res = 8'b00100000;
3'b110: res = 8'b01000000;
default: res = 8'b10000000;
endcase
end
endmodule
| 7.856429 |
module top16_3step_CLA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_3step processing_block_16_3step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CLA32 CLA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.41128 |
module top16_3step_RCA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_3step processing_block_16_3step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
RCA32 RCA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.817139 |
module top16_3step_CSelA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_3step processing_block_16_3step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSelA32 CSelA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.41128 |
module top16_3step_CSkipA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_3step processing_block_16_3step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSkipA32 CSkipA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.41128 |
module top16_3step_KSA32 (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16 generate_partial_products_16 (
.x(x),
.y(y),
.p(p)
);
processing_block_16_3step processing_block_16_3step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
KSA32 KSA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.122312 |
module top16_3step_CLA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_3step processing_block_16_3step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CLA32 CLA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.41128 |
module top16_3step_RCA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_3step processing_block_16_3step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
RCA32 RCA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.817139 |
module top16_3step_CSelA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_3step processing_block_16_3step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSelA32 CSelA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.41128 |
module top16_3step_CSkipA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_3step processing_block_16_3step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
CSkipA32 CSkipA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.41128 |
module top16_3step_KSA32_trunc (
input [15:0] x,
input [15:0] y,
output [32:0] prod
);
wire p[15:0][15:0];
wire [31:0] PRE1;
wire [31:0] PRE2;
assign PRE1[31] = 1'b0;
assign PRE2[31] = 1'b0;
generate_partial_products_16_trunc generate_partial_products_16_trunc (
.x(x),
.y(y),
.p(p)
);
processing_block_16_3step processing_block_16_3step (
.p(p),
.out1(PRE1[30:0]),
.out2(PRE2[30:0])
);
KSA32 KSA32 (
.sum(prod[31:0]),
.cout(prod[32]),
.a(PRE1),
.b(PRE2)
); //CLA32 RCA32 CSelA32 CSkipA32 KSA32
endmodule
| 7.122312 |
module mux (
sel,
res
);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res) begin
case (sel)
3'b000: res = 8'b00000001;
3'b001: res = 8'b00000010;
3'b010: res = 8'b00000100;
3'b011: res = 8'b00001000;
3'b100: res = 8'b00010000;
3'b101: res = 8'b00100000;
// 110 and 111 selector values are unused
default: res = 8'bxxxxxxxx;
endcase
end
endmodule
| 7.856429 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.