code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top (
input clk,
input a,
output b
);
dff u_dff (
.clk(clk),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module dffcp (
input d,
clk,
pre,
clr,
output reg q
);
always @(posedge clk)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
| 6.577005 |
module top (
input clk,
input a,
input c,
output b
);
dffcp u_dffcp (
.clk(clk),
.clr(c),
.pre(1'b1),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module dffcp (
input d,
clk,
pre,
clr,
output reg q
);
always @(posedge clk, posedge pre, posedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
| 6.577005 |
module top (
input clk,
input a,
output b
);
dffcp u_dffcp (
.clk(clk),
.clr(1'b0),
.pre(1'b1),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module top (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
| 7.233807 |
module dffr (
input d,
clk,
rst,
output reg q
);
always @(posedge clk)
if (rst) q <= 1'b0;
else q <= d;
endmodule
| 7.053895 |
module top (
input clk,
input a,
output b
);
dffr u_dffr (
.clk(clk),
.rst(1'b1),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module dffsr (
input d,
clk,
pre,
clr,
output reg q
);
always @(posedge clk, posedge pre, negedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
| 6.804969 |
module top (
input clk,
input a,
output b
);
dffsr u_dffsr (
.clk(clk),
.clr(1'b1),
.pre(1'b1),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module dff (
clk,
d,
q
);
input clk;
input d;
output reg q;
always @(posedge clk) q <= d;
endmodule
| 6.824043 |
module top (
input clk,
input a,
output b
);
dff u_dff (
.clk(clk),
.d (1'b0),
.q (b)
);
endmodule
| 7.233807 |
module top_diannao_node_vMAX (
clk, // Main clock
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_op, // Average or MAX op select line (avg = 0, max - 1)
i_nbout, // feedback input from NBout
i_load,
o_to_edram
);
parameter N = 16;
parameter Tn = 1;
parameter Ti = 16;
parameter ADDR_WIDTH = 6;
parameter N_OPS = 1;
//----------- Input Ports ---------------//
input clk, clk2;
// i_inputs is a vector of Tn (16) values, 16-bits each
input [((N*Ti) - 1):0] i_inputs;
// i_synapses is a matrix of Tn x Tn (16x16=256) values, 16-bits each (Row-major).
input [((N*Tn*Ti) - 1):0] i_synapses;
input i_nbout_nfu2_nfu3;
input i_load;
input [N_OPS-1:0] i_op; // Average or MAX op select line (avg = 0, max - 1)
input [((N*Tn) - 1):0] i_nbout;
//----------- Output Ports ---------------//
output [((N*Tn) - 1):0] o_to_edram;
//----------- Internal Signals --------------//
// Wires
wire [((N*Tn*Ti) - 1):0] nfu1_out;
wire [ (N*Tn) - 1 : 0] nfu2_out;
// Registers
// NBin register for current inputs
//reg [ (N*Tn) - 1 : 0 ] nb_in_reg;
// SB register for current synapses
//reg [((N*TnxTn) - 1):0] sb_reg;
// Main pipeline registers
reg [((N*Ti*Tn) - 1):0] nfu1_nfu2_pipe_reg;
reg [ (N*Tn) - 1 : 0] nfu2_nfu3_pipe_reg;
//------------- Code Start -----------------//
// Depending on current state, either write NFU-2 partial sum
// or NFU-3 final results to NBout
//assign o_to_edram = nfu3_out_reg;
assign o_to_edram = nfu2_nfu3_pipe_reg;
//--------------------------------------------------//
//-------------- Main Pipeline Stages --------------//
//--------------------------------------------------//
// NFU-1 (3 internal pipeline stages)
// FIXME: Still need to verify that this is automatically pipelining
nfu_1_pipe_slice n1 (
clk,
i_inputs, //
i_synapses, // sb_reg
nfu1_out // o_results
);
// NFU-2 (2 internal pipeline stages)
nfu_2_pipe_vMAX_slice n2 (
clk,
nfu1_nfu2_pipe_reg, //i_nfu1_out
nfu2_nfu3_pipe_reg, //i_nbout
i_op,
nfu2_out // o_nfu2_out
);
// Main pipeline regs (NFU1/NFU2 + NFU2/NFU3)
always @(posedge clk) begin
// Load the inputs from the SRAMs to the internal registers
// NOTE: Removing the initial load registers... With the NBin/NBout and pipeline regs
// this should be able to figure out some timing stuff.
//nb_in_reg <= i_inputs; // Now in nbin_out
//sb_reg <= i_synapses;
nfu1_nfu2_pipe_reg <= nfu1_out;
if (i_load) nfu2_nfu3_pipe_reg <= nfu2_out;
else nfu2_nfu3_pipe_reg <= i_nbout;
end
//--------------------------------------------------//
//--------------------------------------------------//
//--------------------------------------------------//
endmodule
| 7.347611 |
module top_diannao_node_vMAX (
clk, // Main clock
reset, // Reset
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_nbout, // Input from NBOut
i_sigmoid_coef, // Coefficient values to store in sigmoid RAM
i_load_sigmoid_coef, // Control signal to store sigmoid coefficients
i_op, // Average or MAX op select line (avg = 0, max - 1)
i_first_cycle,
i_precision,
o_to_nbout
);
parameter N = 16;
parameter Tn = 16;
parameter TnxTn = Tn*Tn;
parameter Tw = 16;
parameter ADDR_WIDTH = 6;
parameter N_OPS = 1;
//----------- Input Ports ---------------//
input clk;
input reset;
// i_inputs is a vector of Tn (16) values, 16-bits each
input [((N*Tn) - 1):0] i_inputs;
// i_synapses is a matrix of Tn x Tn (16x16=256) values, 16-bits each (Row-major).
input [((N*TnxTn) - 1):0] i_synapses;
input[(N*Tn*Tw)-1:0] i_nbout;
input [((2*N)-1):0] i_sigmoid_coef; // 16-bit Ai and Bi = 32-bits
input i_load_sigmoid_coef;
input [N_OPS-1:0] i_op; // Average or MAX op select line (avg = 0, max - 1)
input i_first_cycle;
input [4:0] i_precision;
//----------- Output Ports ---------------//
output [((N*Tn) - 1):0] o_to_nbout;
//----------- Internal Signals --------------//
// Wires
wire [(N*Tw*Tn)-1:0] nfu1_2_serial_out;
wire [(N*Tw*Tn)-1:0 mux_to_nbout;
//------------- Code Start -----------------//
assign o_to_nbout = mux_to_nbout;
//--------------------------------------------------//
//-------------- Main Pipeline Stages --------------//
//--------------------------------------------------//
// NFU_1_2_serial_pipe
nfu_1_2_serial_pipe (
clk,
reset,
i_first_cycle,
i_precision,
i_inputs,
i_synapses,
i_nbout,
nfu1_2_serial_out
);
mux_16_to_1_v2 MUX16_1 (
i_mux_sel,
nfu1_2_serial_out,
mux_to_nbout;
);
//--------------------------------------------------//
//--------------------------------------------------//
//--------------------------------------------------//
endmodule
| 7.347611 |
module top_diannao_node_vMAX_no_nfu3 (
clk, // Main clock
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_nbout,
i_op,
o_to_nbout
);
parameter N = 16;
parameter Tn = 16;
parameter TnxTn = Tn * Tn;
//----------- Input Ports ---------------//
input clk;
input i_op;
// i_inputs is a vector of Tn (16) values, 16-bits each
input [((N*Tn) - 1):0] i_inputs;
input [((N*Tn) - 1):0] i_nbout;
// i_synapses is a matrix of Tn x Tn (16x16=256) values, 16-bits each (Row-major).
input [((N*TnxTn) - 1):0] i_synapses;
//----------- Output Ports ---------------//
output [((N*Tn) - 1):0] o_to_nbout;
//----------- Internal Signals --------------//
// Wires
wire [((N*TnxTn) - 1):0] nfu1_out;
wire [ (N*Tn) - 1 : 0] nfu2_out;
// Main pipeline registers
reg [((N*TnxTn) - 1):0] nfu1_nfu2_pipe_reg;
reg [ ((N*Tn) - 1):0] i_inputs_reg;
reg [ ((N*Tn) - 1):0] i_nbout_reg;
reg [((N*TnxTn) - 1):0] i_synapses_reg;
reg i_op_reg;
reg [ ((N*Tn) - 1):0] nfu2_out_reg;
//------------- Code Start -----------------//
// Depending on current state, either write NFU-2 partial sum
// or NFU-3 final results to NBout
assign o_to_nbout = nfu2_out_reg;
//--------------------------------------------------//
//-------------- Main Pipeline Stages --------------//
//--------------------------------------------------//
// NFU-1 (3 internal pipeline stages)
// FIXME: Still need to verify that this is automatically pipelining
nfu_1_pipe n1 (
clk,
i_inputs_reg,
i_synapses_reg,
nfu1_out
);
// NFU-2 (2 internal pipeline stages)
nfu_2_pipe_vMAX n2 (
clk,
nfu1_nfu2_pipe_reg,
i_nbout_reg,
i_op_reg,
nfu2_out
);
// Main pipeline regs (NFU1/NFU2 + NFU2/NFU3)
always @(posedge clk) begin
// Load the inputs from the SRAMs to the internal registers
nfu1_nfu2_pipe_reg <= nfu1_out;
i_inputs_reg <= i_inputs;
i_synapses_reg <= i_synapses;
i_nbout_reg <= i_nbout;
i_op_reg <= i_op;
nfu2_out_reg <= nfu2_out;
end
//--------------------------------------------------//
//--------------------------------------------------//
//--------------------------------------------------//
endmodule
| 7.347611 |
module max_short (
input [15:0] x,
input [15:0] y,
output [15:0] z
);
assign z = (y > x) ? y : x;
endmodule
| 7.08246 |
module max_byte (
input [7:0] x,
input [7:0] y,
output [7:0] z
);
assign z = (y > x) ? y : x;
endmodule
| 7.597222 |
module fiveminusmax0 (
input [3:0] i,
output [3:0] o
);
wire [4:0] fiveminus;
assign fiveminus = 5'd5 - {1'b0, i};
assign o = (!fiveminus[4]) ? fiveminus[3:0] : 4'b0;
endmodule
| 7.754056 |
module unitfull (
input [1:0] select_ms,
input [7:0] Hmm,
input [7:0] Hmc,
input [7:0] Hcm,
input [7:0] Ecm,
input [7:0] Fmc,
output [7:0] Hcc,
output [7:0] Ecc,
output [7:0] Fcc
);
/*
Hcc = max( Hmm + ms, Ecc, Fcc)
Ecc = max( Hcm - 6, Ecm - 1)
Fcc = max( Hmc - 6, Fmc - 1)
*/
wire [7:0] Hcc0;
wire [7:0] Ecc0;
wire [7:0] Ecc1;
wire [7:0] Fcc0;
wire [7:0] Fcc1;
wire [7:0] ms;
assign ms = (select_ms == 2'b00) ? -8'd4 : ((select_ms == 2'b01) ? -8'd1 : 8'd1);
assign Hcc0 = Hmm + ms;
assign Ecc0 = Hcm - 8'd6;
assign Ecc1 = Ecm - 8'd1;
assign Fcc0 = Hmc - 8'd6;
assign Fcc1 = Fmc - 8'd1;
wire [7:0] Ecc_max_Fcc;
assign Ecc_max_Fcc = (Ecc > Fcc) ? Ecc : Fcc;
assign Hcc = (Hcc0 > Ecc_max_Fcc) ? Hcc0 : Ecc_max_Fcc;
assign Ecc = (Ecc0 > Ecc1) ? Ecc0 : Ecc1;
assign Fcc = (Fcc0 > Fcc1) ? Fcc0 : Fcc1;
endmodule
| 6.805252 |
module top (
input USER_CLOCK,
output [3:0] z
);
wire clk;
clockdrv clockdrv ( // Clock in ports
.CLK_IN1 (USER_CLOCK), // IN
// Clock out ports
.CLK_OUT1(clk)
); // OUT
reg [41:0] state;
assign z = state[27:24];
always @(posedge clk) begin
state = state + 1;
end
//wire [15:0] short1;
//wire [15:0] short0;
//assign { short1, short0} = state;
//wire [15:0] short_max;
//max_short max_short( .x(short0), .y(short1), .z(short_max));
wire [3:0] L;
wire [3:0] U;
wire [3:0] Y;
wire [3:0] Z;
wire [3:0] Lp;
wire [3:0] Up;
wire [3:0] Yp;
wire [3:0] Zp;
wire [1:0] select_ms;
unit unit (
.select_ms(select_ms),
.L(L),
.U(U),
.Y(Y),
.Z(Z),
.Lp(Lp),
.Up(Up),
.Yp(Yp),
.Zp(Zp)
);
//wire [7:0] Hmm;
//wire [7:0] Hmc;
//wire [7:0] Hcm;
//wire [7:0] Ecm;
//wire [7:0] Fmc;
//wire [7:0] Hcc;
//wire [7:0] Ecc;
//wire [7:0] Fcc;
//unitfull unit( .select_ms(select_ms), .Hmm(Hmm), .Hmc(Hmc), .Hcm(Hcm), .Ecm(Ecm), .Fmc(Fmc), .Hcc(Hcc), .Ecc(Ecc), .Fcc(Fcc));
//wire [7:0] byte1;
//wire [7:0] byte0;
//assign {byte1, byte0} = state[15:0];
//wire [7:0] byte_max;
//max_byte max_byte( .x(byte0), .y(byte1), .z(byte_max));
//wire [3:0] nibble2;
//wire [3:0] nibble1;
//wire [3:0] nibble0;
//assign nibble2 = 4'd5;
//assign {nibble1,nibble0} = state[7:0];
//wire [3:0] nibble_max;
// wire [3:0] yy;
//max_nibble max_nibble( .x(nibble0), .y(nibble1), .z(nibble_max));
// assign yy = ( y > nibble2) ? y : nibble2;
wire [35:0] CONTROL0;
wire [35:0] CONTROL1;
wire [31:0] combout0;
wire [31:0] combout1;
wire [31:0] combin0;
wire [31:0] combin1;
assign {select_ms, L, U, Y, Z} = combin0[17:0];
assign combout0 = {16'b0, Lp, Up, Yp, Zp};
assign combout1 = 32'b0;
//assign {Hmc,Hcm,Ecm,Fmc} = combin0;
//assign {select_ms,Hmm} = combin1[9:0];
//assign combout0 = { 8'b0, Hcc, Ecc, Fcc};
//assign combout1 = 32'b0;
//assign {select_ms,Hmm,Hmc,Hcm,Ecm,Fmc} = state[41:0];
//wire [31:0] trig0;
//assign trig0 = { L, U, Y, Z, Lp, Up, Yp, Zp};
//assign trig0 = { 8'b0, Hcc, Ecc, Fcc};
icon2 icon2 (
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
);
vio vio0 (
.CONTROL (CONTROL0), // INOUT BUS [35:0]
.ASYNC_IN (combout0), // IN BUS [31:0]
.ASYNC_OUT(combin0) // OUT BUS [31:0]
);
vio vio1 (
.CONTROL (CONTROL1), // INOUT BUS [35:0]
.ASYNC_IN (combout1), // IN BUS [31:0]
.ASYNC_OUT(combin1) // OUT BUS [31:0]
);
endmodule
| 7.233807 |
module top_dip (
in,
out,
clk
);
parameter N = 128;
parameter M = 8;
input clk;
input [M:0] in;
output reg [M:0] out;
reg [M:0] image_in[N-1:0][N-1:0];
reg [M:0] image_in2[N+1:0][N+1:0];
reg [M:0] image_out[N-1:0][N-1:0];
reg [2:0] prc = 0;
reg [2:0] prc1 = 0;
reg load = 1;
integer i = 0;
integer j = 0;
// image loading
always @(posedge clk) begin
if (load == 1) begin
if ((i < N) && ~(i == N - 1 && j == N)) begin
if (j < N) begin
image_in[i][j] = in;
//$display("image[%d][%d]: %d",i,j,in);
j = j + 1;
end else begin
j = 0;
image_in[i+1][0] = in;
i = i + 1;
//$display("image[%d][%d]: %d",i,j,in);
j = j + 1;
end
end else begin
j = 0;
i = 0;
prc = 1;
load = 0;
end
end
end
// padding
integer i1, i2, j1;
always @(prc) begin
if (prc == 1) begin
for (i1 = 0; i1 < N; i1 = i1 + 1)
for (j1 = 0; j1 < N; j1 = j1 + 1) begin
image_in2[i1+1][j1+1] = image_in[i1][j1];
end
for (i2 = 0; i2 < N + 2; i2 = i2 + 1) begin
image_in2[i2][0] = 0;
image_in2[i2][N+1] = 0;
image_in2[0][i2] = 0;
image_in2[N+1][i2] = 0;
end
//$display("%d", prc);
prc1 = 2;
//$display("%d", prc);
end
end
//real multiply = 0.111111 ;
integer i3, j3, c3, d3;
reg [2*M-1:0] sum;
wire [ M-1:0] factor = 8'b0001_1100;
always @(prc1) begin
if (prc1 == 2) begin
for (i3 = 0; i3 < N; i3 = i3 + 1) begin
for (j3 = 0; j3 < N; j3 = j3 + 1) begin
sum = 0;
for (c3 = 0; c3 < 3; c3 = c3 + 1) begin
for (d3 = 0; d3 < 3; d3 = d3 + 1) begin
sum = sum + image_in2[c3+i3][d3+j3];
end
end
sum = sum * factor;
image_out[i3][j3] = sum >> 8;
#2 out = sum >> 8;
end
//$writememh("output_v1.txt",);
end
//prc = 3;
end
end
endmodule
| 6.781053 |
module top_direct_send (
input clk,
input rst,
input RsRx, // Connect to RX pin
output [7:0] Rx_data, // Received data
output RsTx // Connect to TX pin
);
parameter CLK_RATE = 9600000;
parameter BAUD_RATE = 9600;
parameter SAMPLE_RATE = 10;
wire clk_9_6M;
wire uart_clk;
wire sample_clk;
wire sampler_data_out;
wire tx_ready; // tx_ready signifies the availability of TX buffer
wire rx_ready; // when signal == 1, signifies that one byte of data is received
wire [7:0] data; // Received data
reg tx_start; // start to send data when this bit is set to 1
assign Rx_data = data;
receiver_sampler sampler ( // Error checking logic
.rst(rst),
.sample_clk(sample_clk),
.rx_clk(uart_clk),
.RsRx(RsRx),
.data_bit(sampler_data_out)
);
receiver receiver ( // Receiver
.data_in(sampler_data_out),
//.data_in(RsRx),
.rx_clk(uart_clk),
.reset(rst),
.signal(rx_ready),
.data_out(data)
);
transmitter transmitter ( // Transmitter
.data_in(data),
.tx_clk(uart_clk),
.reset(rst),
.start(tx_start),
.data_out(RsTx),
.tx_ready(tx_ready)
);
clk_divide // Clock generator for TX and RX
#(
.CLK_RATE(CLK_RATE),
.BAUD_RATE(BAUD_RATE),
.SAMPLE_RATE(SAMPLE_RATE)
) clk_div (
.clk(clk_9_6M),
.rst(rst),
.clk_uart(uart_clk),
.clk_sampling(sample_clk)
);
PLL_9_6M PLL (
.clk_in(clk),
.clk_out_9_6M(clk_9_6M),
.rst(rst)
);
always @(rx_ready, tx_ready) begin
if (tx_ready && rx_ready) // start to send one byte of data after you received one
tx_start <= 1'b1;
else tx_start <= 1'b0;
end
endmodule
| 7.103126 |
module top_display (
input clk,
input [3:0] thousand,
input [3:0] hund,
input [3:0] ten,
input [3:0] unit,
output [6:0] LED_out,
output dp,
output [3:0] Anode_activate
);
wire [3:0] digit;
wire [1:0] anode;
anode_controller ac1 (
clk,
Anode_activate,
anode
);
cathode_controller cc1 (
anode,
thousand,
hund,
ten,
unit,
digit,
dp
);
display d1 (
digit,
LED_out
);
endmodule
| 7.295151 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
assign {cout, A} = cin % y / x;
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin, (* init = 1'h0 *)
output reg A,
output cout
);
parameter X = 1;
wire o;
initial A = 0;
initial cout = 0;
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle u_mid (
.x(x),
.o(o)
);
u_rtl inst_u_rtl (
.x(x),
.o(o)
);
endmodule
| 7.233807 |
module middle (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 6.553865 |
module u_rtl (
input x,
input y,
output o
);
initial o = 0;
assign o = x / 0;
endmodule
| 6.750051 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
wire pow, p, n;
assign {cout, A} = cin % y / x;
assign pow = y ** x;
assign p = +x;
assign n = -x;
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
assign cout = x / y * cin;
endmodule
| 7.233807 |
module top_div_test (
clk,
rst
);
input clk, rst;
wire clk_div;
div_clock test (
clk,
rst,
clk_div
);
endmodule
| 6.687377 |
module top_double_ram_sy (
clk,
rst,
cs,
din_a_0,
addr_a_0,
dout_a,
we_a,
oe_a,
din_b_0,
addr_b_0,
dout_b,
we_b,
oe_b,
rst_clk,
load
);
parameter DATA_WIDTH = 3;
parameter ADDR_WIDTH = 3;
parameter RAM_DEPTH = DATA_WIDTH;
input clk, rst, cs;
input [ADDR_WIDTH-1:0] addr_a_0, addr_b_0;
input [DATA_WIDTH-1:0] din_a_0, din_b_0;
output [DATA_WIDTH-1:0] dout_a, dout_b;
input we_a, oe_a, we_b, oe_b;
input rst_clk;
input load;
wire rst_o, cs_o, rst_clk_o, load_o; //
wire clk_div;
div_clock my_div_clk (
clk,
rst_clk,
clk_div
);
debounce mydebounce (
clk,
cs,
rst,
rst_clk,
load,
cs_o,
rst_o,
rst_clk_o,
load_o
);
fpga_double_ram_sy my_double_ram_sy (
clk,
rst_o,
cs_o,
din_a_0,
addr_a_0,
dout_a,
we_a,
oe_a,
din_b_0,
addr_b_0,
dout_b,
we_b,
oe_b,
load_o
);
endmodule
| 6.762889 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'DPO_AUTO_EXPR_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/DPO_AUTO_EXPR_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data_a );
$dumpvars( 0, dut0.din_data_b );
$dumpvars( 0, dut0.din_data_c );
$dumpvars( 0, dut0.din_data_d );
$dumpvars( 0, dut0.din_data_e );
$dumpvars( 0, dut0.din_data_f );
$dumpvars( 0, dut0.din_data_g );
$dumpvars( 0, dut0.din_data_h );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/DPO_AUTO_EXPR_V/sim_DPO_AUTO_EXPR_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'DPO_AUTO_OP_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/DPO_AUTO_OP_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data_a );
$dumpvars( 0, dut0.din_data_b );
$dumpvars( 0, dut0.din_data_c );
$dumpvars( 0, dut0.din_data_d );
$dumpvars( 0, dut0.din_data_e );
$dumpvars( 0, dut0.din_data_f );
$dumpvars( 0, dut0.din_data_g );
$dumpvars( 0, dut0.din_data_h );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/DPO_AUTO_OP_V/sim_DPO_AUTO_OP_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'DPO_INLINE_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/DPO_INLINE_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data_a );
$dumpvars( 0, dut0.din_data_b );
$dumpvars( 0, dut0.din_data_c );
$dumpvars( 0, dut0.din_data_d );
$dumpvars( 0, dut0.din_data_e );
$dumpvars( 0, dut0.din_data_f );
$dumpvars( 0, dut0.din_data_g );
$dumpvars( 0, dut0.din_data_h );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/DPO_INLINE_V/sim_DPO_INLINE_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module top
(
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
endmodule
| 7.039434 |
module top #(
parameter AW = 2,
BW = 2,
AREG = 1,
BREG = 1,
PREG = 1
) (
input clk,
CEA,
CEB,
CEP,
input [AW-1:0] A,
input [BW-1:0] B, (* keep *)
output reg [AW+BW-1:0] P
);
(* keep *)reg [AW-1:0] Ar;
(* keep *)reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end else always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end else always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end else always @* P <= Ar * Br;
endgenerate
endmodule
| 7.964012 |
module
module top_dual_fifo #
(
parameter AWIDTH = 3,
parameter DWIDTH = 16
)
(
input arst_n, // asynchronous reset
input wclk, // writing circuit's clock
input wdv, // data valid signal. Writing circuit must assert this signa to have the data registered
input [DWIDTH-1:0] wdata, // data to be written by the writing circuit
output wfull, // FIFO full indicator for the writing circuit
input rclk, // reading circuit's clock
input rrq, // data request signal. Reading circuit must assert this to indicate that it can accept the data on the data bus
output [DWIDTH-1:0] rdata, // data to be read by the reading circuit
output rempty, // FIFO empty indicator for the reading circuit
output rdv // data valid signal. Reading circuit can safely register the data on the data bus
);
// internal nets
wire [AWIDTH:0] rgray;
wire [AWIDTH:0] wgray;
wire [AWIDTH-1:0] waddr;
wire [AWIDTH-1:0] raddr;
wire wen;
wire ren;
// Write logic
wlogic #(.AWIDTH(AWIDTH))
wlogic
(
.wclk (wclk ),
.arst_n (arst_n ),
.wdv (wdv ),
.rgray (rgray ),
.wgray (wgray ),
.waddr (waddr ),
.wfull (wfull ),
.wen (wen )
);
// Read logic
rlogic #(.AWIDTH(AWIDTH))
rlogic
(
.rclk (rclk ),
.arst_n (arst_n ),
.rrq (rrq ),
.wgray (wgray ),
.rgray (rgray ),
.raddr (raddr ),
.rempty (rempty ),
.ren (ren )
);
// Dual-port block RAM for FIFO buffer
dualport_ram #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH)
)
dualport_ram
(
.arst_n (arst_n ),
.wclk (wclk ),
.wen (wen ),
.waddr (waddr ),
.wdata (wdata ),
.rclk (rclk ),
.raddr (raddr ),
.rdata (rdata ),
.ren (ren ),
.rdv (rdv )
);
endmodule
| 7.700374 |
module Mem1D (
input clock,
input [ 3:0] io_w_addr,
input [31:0] io_w_data,
input io_w_en,
input [ 3:0] io_r_addr,
output [31:0] io_output_data
);
reg [31:0] _T_14[0:15];
reg [31:0] _RAND_0;
wire [31:0] _T_14__T_17_data;
wire [3:0] _T_14__T_17_addr;
wire [31:0] _T_14__T_16_data;
wire [3:0] _T_14__T_16_addr;
wire _T_14__T_16_mask;
wire _T_14__T_16_en;
assign _T_14__T_17_addr = io_r_addr;
assign _T_14__T_17_data = _T_14[_T_14__T_17_addr];
assign _T_14__T_16_data = io_w_data;
assign _T_14__T_16_addr = io_w_addr;
assign _T_14__T_16_mask = io_w_en;
assign _T_14__T_16_en = io_w_en;
assign io_output_data = _T_14__T_17_data;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
_RAND_0 = {1{$random}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 16; initvar = initvar + 1) _T_14[initvar] = _RAND_0[31:0];
`endif // RANDOMIZE_MEM_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (_T_14__T_16_en & _T_14__T_16_mask) begin
_T_14[_T_14__T_16_addr] <= _T_14__T_16_data;
end
end
endmodule
| 7.084095 |
module MemND (
input clock,
input [ 3:0] io_w_addr_0,
input [31:0] io_w_data,
input io_w_en,
input io_wMask,
input [ 3:0] io_r_addr_0,
output [31:0] io_output_data
);
wire m_clock;
wire [3:0] m_io_w_addr;
wire [31:0] m_io_w_data;
wire m_io_w_en;
wire [3:0] m_io_r_addr;
wire [31:0] m_io_output_data;
wire [4:0] _T_17;
wire [4:0] _T_19;
wire _T_20;
Mem1D m (
.clock(m_clock),
.io_w_addr(m_io_w_addr),
.io_w_data(m_io_w_data),
.io_w_en(m_io_w_en),
.io_r_addr(m_io_r_addr),
.io_output_data(m_io_output_data)
);
assign _T_17 = io_w_addr_0 * 4'h1;
assign _T_19 = io_r_addr_0 * 4'h1;
assign _T_20 = io_w_en & io_wMask;
assign io_output_data = m_io_output_data;
assign m_io_w_addr = _T_17[3:0];
assign m_io_w_data = io_w_data;
assign m_io_w_en = _T_20;
assign m_io_r_addr = _T_19[3:0];
assign m_clock = clock;
endmodule
| 6.691417 |
module MuxVec (
input [63:0] io_ins_0_0_addr,
input io_ins_0_0_isWr,
input [15:0] io_ins_0_0_size,
input [63:0] io_ins_1_0_addr,
input io_ins_1_0_isWr,
input [15:0] io_ins_1_0_size,
input io_sel,
output [63:0] io_out_0_addr,
output io_out_0_isWr,
output [15:0] io_out_0_size
);
wire [15:0] _GEN_0_0_size;
wire [63:0] _GEN_4;
wire _GEN_5;
wire [15:0] _GEN_7;
wire _GEN_2_0_isWr;
wire [63:0] _GEN_3_0_addr;
assign _GEN_4 = io_sel ? io_ins_1_0_addr : io_ins_0_0_addr;
assign _GEN_5 = io_sel ? io_ins_1_0_isWr : io_ins_0_0_isWr;
assign _GEN_7 = io_sel ? io_ins_1_0_size : io_ins_0_0_size;
assign io_out_0_addr = _GEN_3_0_addr;
assign io_out_0_isWr = _GEN_2_0_isWr;
assign io_out_0_size = _GEN_0_0_size;
assign _GEN_0_0_size = _GEN_7;
assign _GEN_2_0_isWr = _GEN_5;
assign _GEN_3_0_addr = _GEN_4;
endmodule
| 7.323123 |
module Depulser (
input clock,
input reset,
input io_in,
input io_rst,
output io_out
);
wire r_clock;
wire r_reset;
wire r_io_in;
wire r_io_init;
wire r_io_out;
wire r_io_enable;
wire _T_6;
wire _T_8;
FF_11 r (
.clock(r_clock),
.reset(r_reset),
.io_in(r_io_in),
.io_init(r_io_init),
.io_out(r_io_out),
.io_enable(r_io_enable)
);
assign _T_6 = io_rst ? 1'h0 : io_in;
assign _T_8 = io_in | io_rst;
assign io_out = r_io_out;
assign r_io_in = _T_6;
assign r_io_init = 1'h0;
assign r_io_enable = _T_8;
assign r_clock = clock;
assign r_reset = reset;
endmodule
| 6.621304 |
module CounterCore (
input clock,
input reset,
output [9:0] io_out,
output [9:0] io_next,
input io_enable,
output io_done,
input [9:0] io_config_max
);
wire counter_clock;
wire counter_reset;
wire [9:0] counter_io_max;
wire [9:0] counter_io_out;
wire [9:0] counter_io_next;
wire counter_io_enable;
wire counter_io_done;
wire depulser_clock;
wire depulser_reset;
wire depulser_io_in;
wire depulser_io_rst;
wire depulser_io_out;
Counter_2 counter (
.clock(counter_clock),
.reset(counter_reset),
.io_max(counter_io_max),
.io_out(counter_io_out),
.io_next(counter_io_next),
.io_enable(counter_io_enable),
.io_done(counter_io_done)
);
Depulser depulser (
.clock (depulser_clock),
.reset (depulser_reset),
.io_in (depulser_io_in),
.io_rst(depulser_io_rst),
.io_out(depulser_io_out)
);
assign io_out = counter_io_out;
assign io_next = counter_io_next;
assign io_done = counter_io_done;
assign counter_io_max = io_config_max;
assign counter_io_enable = io_enable;
assign counter_clock = clock;
assign counter_reset = reset;
assign depulser_io_in = counter_io_done;
assign depulser_io_rst = 1'h0;
assign depulser_clock = clock;
assign depulser_reset = reset;
endmodule
| 6.834422 |
module CounterChainCore (
input clock,
input reset,
output [9:0] io_out_0,
output [9:0] io_out_1,
output [9:0] io_next_1,
input io_enable_0,
output io_done_0
);
wire counters_0_clock;
wire counters_0_reset;
wire [9:0] counters_0_io_out;
wire [9:0] counters_0_io_next;
wire counters_0_io_enable;
wire counters_0_io_done;
wire [9:0] counters_0_io_config_max;
wire counters_1_clock;
wire counters_1_reset;
wire [9:0] counters_1_io_out;
wire [9:0] counters_1_io_next;
wire counters_1_io_enable;
wire counters_1_io_done;
wire [9:0] counters_1_io_config_max;
wire _T_69;
CounterCore counters_0 (
.clock(counters_0_clock),
.reset(counters_0_reset),
.io_out(counters_0_io_out),
.io_next(counters_0_io_next),
.io_enable(counters_0_io_enable),
.io_done(counters_0_io_done),
.io_config_max(counters_0_io_config_max)
);
CounterCore counters_1 (
.clock(counters_1_clock),
.reset(counters_1_reset),
.io_out(counters_1_io_out),
.io_next(counters_1_io_next),
.io_enable(counters_1_io_enable),
.io_done(counters_1_io_done),
.io_config_max(counters_1_io_config_max)
);
assign _T_69 = counters_0_io_done;
assign io_out_0 = counters_0_io_out;
assign io_out_1 = counters_1_io_out;
assign io_next_1 = counters_1_io_next;
assign io_done_0 = counters_0_io_done;
assign counters_0_io_enable = io_enable_0;
assign counters_0_io_config_max = 10'h1;
assign counters_0_clock = clock;
assign counters_0_reset = reset;
assign counters_1_io_enable = _T_69;
assign counters_1_io_config_max = 10'h200;
assign counters_1_clock = clock;
assign counters_1_reset = reset;
endmodule
| 6.629693 |
module MuxN_1 (
input [63:0] io_ins_0_addr,
input io_ins_0_isWr,
input [15:0] io_ins_0_size,
output [63:0] io_out_addr,
output io_out_isWr,
output [15:0] io_out_size
);
assign io_out_addr = io_ins_0_addr;
assign io_out_isWr = io_ins_0_isWr;
assign io_out_size = io_ins_0_size;
endmodule
| 7.832446 |
module MuxN_3 (
input io_ins_0,
output io_out
);
assign io_out = io_ins_0;
endmodule
| 7.122897 |
module MuxN_4 (
input io_ins_0_valid,
input [31:0] io_ins_0_bits_wdata_0,
input [31:0] io_ins_0_bits_wdata_1,
input [31:0] io_ins_0_bits_wdata_2,
input [31:0] io_ins_0_bits_wdata_3,
input [31:0] io_ins_0_bits_wdata_4,
input [31:0] io_ins_0_bits_wdata_5,
input [31:0] io_ins_0_bits_wdata_6,
input [31:0] io_ins_0_bits_wdata_7,
input [31:0] io_ins_0_bits_wdata_8,
input [31:0] io_ins_0_bits_wdata_9,
input [31:0] io_ins_0_bits_wdata_10,
input [31:0] io_ins_0_bits_wdata_11,
input [31:0] io_ins_0_bits_wdata_12,
input [31:0] io_ins_0_bits_wdata_13,
input [31:0] io_ins_0_bits_wdata_14,
input [31:0] io_ins_0_bits_wdata_15,
input io_ins_0_bits_wlast,
output io_out_valid,
output [31:0] io_out_bits_wdata_0,
output [31:0] io_out_bits_wdata_1,
output [31:0] io_out_bits_wdata_2,
output [31:0] io_out_bits_wdata_3,
output [31:0] io_out_bits_wdata_4,
output [31:0] io_out_bits_wdata_5,
output [31:0] io_out_bits_wdata_6,
output [31:0] io_out_bits_wdata_7,
output [31:0] io_out_bits_wdata_8,
output [31:0] io_out_bits_wdata_9,
output [31:0] io_out_bits_wdata_10,
output [31:0] io_out_bits_wdata_11,
output [31:0] io_out_bits_wdata_12,
output [31:0] io_out_bits_wdata_13,
output [31:0] io_out_bits_wdata_14,
output [31:0] io_out_bits_wdata_15,
output io_out_bits_wlast
);
assign io_out_valid = io_ins_0_valid;
assign io_out_bits_wdata_0 = io_ins_0_bits_wdata_0;
assign io_out_bits_wdata_1 = io_ins_0_bits_wdata_1;
assign io_out_bits_wdata_2 = io_ins_0_bits_wdata_2;
assign io_out_bits_wdata_3 = io_ins_0_bits_wdata_3;
assign io_out_bits_wdata_4 = io_ins_0_bits_wdata_4;
assign io_out_bits_wdata_5 = io_ins_0_bits_wdata_5;
assign io_out_bits_wdata_6 = io_ins_0_bits_wdata_6;
assign io_out_bits_wdata_7 = io_ins_0_bits_wdata_7;
assign io_out_bits_wdata_8 = io_ins_0_bits_wdata_8;
assign io_out_bits_wdata_9 = io_ins_0_bits_wdata_9;
assign io_out_bits_wdata_10 = io_ins_0_bits_wdata_10;
assign io_out_bits_wdata_11 = io_ins_0_bits_wdata_11;
assign io_out_bits_wdata_12 = io_ins_0_bits_wdata_12;
assign io_out_bits_wdata_13 = io_ins_0_bits_wdata_13;
assign io_out_bits_wdata_14 = io_ins_0_bits_wdata_14;
assign io_out_bits_wdata_15 = io_ins_0_bits_wdata_15;
assign io_out_bits_wlast = io_ins_0_bits_wlast;
endmodule
| 7.574965 |
module MuxN_5 (
input io_ins_0,
input io_ins_1,
input io_sel,
output io_out
);
wire _GEN_0;
wire _GEN_1;
assign _GEN_1 = io_sel ? io_ins_1 : io_ins_0;
assign io_out = _GEN_0;
assign _GEN_0 = _GEN_1;
endmodule
| 7.48046 |
module MuxN_6 (
input io_ins_0_valid,
input [63:0] io_ins_0_bits_addr,
input [31:0] io_ins_0_bits_size,
input io_ins_0_bits_isWr,
input [31:0] io_ins_0_bits_tag,
input [31:0] io_ins_0_bits_streamId,
input io_ins_1_valid,
input [63:0] io_ins_1_bits_addr,
input [31:0] io_ins_1_bits_size,
input io_ins_1_bits_isWr,
input [31:0] io_ins_1_bits_tag,
input [31:0] io_ins_1_bits_streamId,
input io_sel,
output io_out_valid,
output [63:0] io_out_bits_addr,
output [31:0] io_out_bits_size,
output io_out_bits_isWr,
output [31:0] io_out_bits_tag,
output [31:0] io_out_bits_streamId
);
wire _GEN_9;
wire [63:0] _GEN_10;
wire [31:0] _GEN_11;
wire _GEN_13;
wire [31:0] _GEN_15;
wire [31:0] _GEN_16;
wire [31:0] _GEN_1_bits_streamId;
wire [31:0] _GEN_2_bits_tag;
wire _GEN_4_bits_isWr;
wire [31:0] _GEN_6_bits_size;
wire [63:0] _GEN_7_bits_addr;
wire _GEN_8_valid;
assign _GEN_9 = io_sel ? io_ins_1_valid : io_ins_0_valid;
assign _GEN_10 = io_sel ? io_ins_1_bits_addr : io_ins_0_bits_addr;
assign _GEN_11 = io_sel ? io_ins_1_bits_size : io_ins_0_bits_size;
assign _GEN_13 = io_sel ? io_ins_1_bits_isWr : io_ins_0_bits_isWr;
assign _GEN_15 = io_sel ? io_ins_1_bits_tag : io_ins_0_bits_tag;
assign _GEN_16 = io_sel ? io_ins_1_bits_streamId : io_ins_0_bits_streamId;
assign io_out_valid = _GEN_8_valid;
assign io_out_bits_addr = _GEN_7_bits_addr;
assign io_out_bits_size = _GEN_6_bits_size;
assign io_out_bits_isWr = _GEN_4_bits_isWr;
assign io_out_bits_tag = _GEN_2_bits_tag;
assign io_out_bits_streamId = _GEN_1_bits_streamId;
assign _GEN_1_bits_streamId = _GEN_16;
assign _GEN_2_bits_tag = _GEN_15;
assign _GEN_4_bits_isWr = _GEN_13;
assign _GEN_6_bits_size = _GEN_11;
assign _GEN_7_bits_addr = _GEN_10;
assign _GEN_8_valid = _GEN_9;
endmodule
| 7.54457 |
module CounterChainCore_4 (
input clock,
input reset,
output [5:0] io_out_0,
output [5:0] io_out_1,
output [5:0] io_next_0,
output [5:0] io_next_1,
input io_enable_0,
input io_enable_1,
input io_config_chain_0
);
wire counters_0_clock;
wire counters_0_reset;
wire [5:0] counters_0_io_out;
wire [5:0] counters_0_io_next;
wire counters_0_io_enable;
wire counters_0_io_done;
wire [5:0] counters_0_io_config_max;
wire counters_1_clock;
wire counters_1_reset;
wire [5:0] counters_1_io_out;
wire [5:0] counters_1_io_next;
wire counters_1_io_enable;
wire counters_1_io_done;
wire [5:0] counters_1_io_config_max;
wire _T_69;
CounterCore_8 counters_0 (
.clock(counters_0_clock),
.reset(counters_0_reset),
.io_out(counters_0_io_out),
.io_next(counters_0_io_next),
.io_enable(counters_0_io_enable),
.io_done(counters_0_io_done),
.io_config_max(counters_0_io_config_max)
);
CounterCore_8 counters_1 (
.clock(counters_1_clock),
.reset(counters_1_reset),
.io_out(counters_1_io_out),
.io_next(counters_1_io_next),
.io_enable(counters_1_io_enable),
.io_done(counters_1_io_done),
.io_config_max(counters_1_io_config_max)
);
assign _T_69 = io_config_chain_0 ? counters_0_io_done : io_enable_1;
assign io_out_0 = counters_0_io_out;
assign io_out_1 = counters_1_io_out;
assign io_next_0 = counters_0_io_next;
assign io_next_1 = counters_1_io_next;
assign counters_0_io_enable = io_enable_0;
assign counters_0_io_config_max = 6'h10;
assign counters_0_clock = clock;
assign counters_0_reset = reset;
assign counters_1_io_enable = _T_69;
assign counters_1_io_config_max = 6'h20;
assign counters_1_clock = clock;
assign counters_1_reset = reset;
endmodule
| 6.629693 |
module MuxN_14 (
input [31:0] io_ins_0,
output [31:0] io_out
);
wire [31:0] _GEN_0;
assign io_out = _GEN_0;
assign _GEN_0 = io_ins_0;
endmodule
| 8.213776 |
module top_dynamic (
input wire sys_clk,
input wire sys_rst_n,
output wire stcp,
output wire shcp,
output wire ds,
output wire oe
);
wire [19:0] data;
wire [5:0] point;
wire sign;
wire seg_en;
data_gen data_gen_inst (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.data (data),
.point (point),
.sign (sign),
.seg_en(seg_en)
);
dynamic_combine dynamic_combine_inst (
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.sign(sign),
.seg_en(seg_en),
.data(data),
.point(point),
.shcp(shcp),
.stcp(stcp),
.oe (oe),
.ds (ds)
);
endmodule
| 8.75978 |
module top_ecc (
clk,
reset,
inst,
ctrl,
sel,
data_out
);
input clk;
input reset;
input [2:0] inst;
input [2:0] ctrl;
input [1:0] sel;
output [7:0] data_out;
wire clk;
wire reset;
wire [2:0] inst;
wire [2:0] ctrl;
wire [1:0] sel;
wire [7:0] data_out;
wire [31:0] data_out1;
wire [31:0] data_in;
wire [7:0] a0;
wire [7:0] a1;
wire [7:0] a2;
wire [7:0] a3;
wire [7:0] b0;
wire [7:0] b1;
wire [7:0] b2;
wire [7:0] b3;
wire [7:0] c0;
wire [7:0] c1;
wire [7:0] c2;
wire [7:0] c3;
wire [7:0] c4;
reg [4:0] count;
reg [4:0] temp;
reg [7:0] a0_temp;
reg [7:0] a1_temp;
reg [7:0] a2_temp;
reg [7:0] a3_temp;
reg [7:0] b0_temp;
reg [7:0] b1_temp;
reg [7:0] b2_temp;
reg [7:0] b3_temp;
reg [7:0] x_in;
reg [7:0] y_in;
wire [7:0] x_out1;
wire [7:0] y_out1;
wire [7:0] x_out2;
wire [7:0] y_out2;
reg valid;
assign data_in = 32'h12345678;
assign a0 = a0_temp;
assign a1 = a1_temp;
assign a2 = a2_temp;
assign a3 = a3_temp;
assign b0 = b0_temp;
assign b1 = b1_temp;
assign b2 = b2_temp;
assign b3 = b3_temp;
control ct1 (
clk,
reset,
ctrl,
data_in,
data_out1,
x_in,
y_in,
x_out1,
y_out1,
x_out2,
y_out2,
s0,
valid
);
ecc ct2 (
clk,
reset,
inst,
a0,
a1,
a2,
a3,
8'd0,
b0,
b1,
b2,
b3,
8'd0,
c0,
c1,
c2,
c3,
c4
);
always @(posedge clk) begin
if (reset) count <= 0;
else if (count == 31) count <= 31;
else count <= count + 1;
end
always @(posedge clk) begin
if (reset == 1) begin
valid <= 0;
temp <= 0;
end else if (s0 == 1 && temp == 0) begin
a0_temp <= x_out1;
b0_temp <= y_out1;
a1_temp <= x_out2;
b1_temp <= y_out2;
temp <= 1;
end else if (s0 == 1 && temp == 1) begin
a2_temp <= x_out1;
b2_temp <= y_out1;
a3_temp <= x_out2;
b3_temp <= y_out2;
temp <= 0;
end else if (count == 11) begin
valid <= 1;
x_in <= c0;
y_in <= c1;
end else if (count == 12) begin
valid <= 1;
x_in <= c2;
y_in <= c3;
end else begin
valid <= 0;
end
end
assign data_out = ( sel == 2'b00 ) ? data_out1[7:0] :
( sel == 2'b01 ) ? data_out1[15:8] :
( sel == 2'b10 ) ? data_out1[23:16] :
( sel == 2'b11 ) ? data_out1[31:24] : 8'd0;
endmodule
| 6.502333 |
module top_edge_preseving_filter (
clk,
rst_n,
en,
done
);
input clk, rst_n, en;
output done;
wire done_mem;
wire [7:0] cl_pixel; // data is filted
wire wr; // signal write into mem2
wire rd, act; // signal read from mem1
wire [7:0] sw_pixel_1,sw_pixel_2,sw_pixel_3,sw_pixel_4,sw_pixel_5,sw_pixel_6,sw_pixel_7,sw_pixel_8,sw_pixel_9;
controller control (
clk,
en,
rst_n,
act,
rd
);
memory mem (
clk,
rst_n,
rd,
wr,
done_mem,
cl_pixel,
sw_pixel_1,
sw_pixel_2,
sw_pixel_3,
sw_pixel_4,
sw_pixel_5,
sw_pixel_6,
sw_pixel_7,
sw_pixel_8,
sw_pixel_9
);
filter fil (
clk,
rst_n,
cl_pixel,
act,
wr,
sw_pixel_1,
sw_pixel_2,
sw_pixel_3,
sw_pixel_4,
sw_pixel_5,
sw_pixel_6,
sw_pixel_7,
sw_pixel_8,
sw_pixel_9
);
assign done = done_mem;
endmodule
| 7.33061 |
module top_elf2_v1 (
output reg [2:0] led_n
);
`include "macros/direction.vh"
reg [2:0] int_rst_cnt = 0;
wire osc_clk;
wire clk = osc_clk;
always @(posedge clk) begin
if (int_rst_cnt != 3'b111) int_rst_cnt <= int_rst_cnt + 1;
end
wire int_rst_n = int_rst_cnt == 3'b111;
wire rst_n = int_rst_n;
wire i_req;
wire [15:0] i_addr;
wire i_ack;
wire [7:0] i_rdata;
wire d_req;
wire d_dir;
wire [7:0] d_addr;
wire [7:0] d_wdata;
wire d_ack;
wire [7:0] d_rdata;
wire io_req;
wire io_dir;
wire [7:0] io_wdata;
reg io_ack;
reg [7:0] io_rdata;
EF2_PHY_OSCDIV osc (
.rstn (1'b1),
.stdby(1'b0),
.div (7'd10),
.clko (osc_clk)
);
bfcpu cpu (
.clk (clk),
.rst_n(rst_n),
.i_req (i_req),
.i_addr (i_addr),
.i_ack (i_ack),
.i_rdata(i_rdata),
.d_req (d_req),
.d_dir (d_dir),
.d_addr (d_addr),
.d_wdata(d_wdata),
.d_ack (d_ack),
.d_rdata(d_rdata),
.io_req (io_req),
.io_dir (io_dir),
.io_wdata(io_wdata),
.io_ack (io_ack),
.io_rdata(io_rdata)
);
i_mem_elf2_v1 im (
.clk(clk),
.i_req (i_req),
.i_addr (i_addr),
.i_ack (i_ack),
.i_rdata(i_rdata)
);
d_mem_elf2_v1 dm (
.clk(clk),
.d_req (d_req),
.d_dir (d_dir),
.d_addr (d_addr),
.d_wdata(d_wdata),
.d_ack (d_ack),
.d_rdata(d_rdata)
);
always @(posedge clk) begin
if (!rst_n) begin
led_n <= 3'b111;
io_ack <= 0;
end else begin
if (io_req) begin
io_ack <= 1;
if (io_dir == `DIRECTION_WRITE) led_n <= ~io_wdata[2:0];
else io_rdata <= {5'b0, ~led_n};
end else begin
io_ack <= 0;
end
end
end
endmodule
| 6.748837 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
typedef enum {
red,
blue,
green
} e_color;
endmodule
| 7.233807 |
module dut (
input fast_clk,
slow_clk,
input [3:0] waddr,
raddr,
input [3:0] wdata,
input wen,
output [3:0] rdata
);
reg [3:0] mem[0:15];
reg [3:0] raddr_reg;
always @(posedge fast_clk) begin
if (wen) mem[waddr] <= wdata;
end
always @(posedge slow_clk) raddr_reg <= raddr;
assign rdata = mem[raddr_reg];
endmodule
| 7.120761 |
module fsm (
clock,
reset,
req,
gnt
);
input clock, reset;
inout [1:0] req;
output [1:0] gnt;
wire clock, reset;
wire [1:0] req;
reg [1:0] gnt;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101, GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @(posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case (state)
IDLE:
if (req[0] == 1'b1) begin
state <= #1 GNT0;
gnt[0] <= 1;
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0:
if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1:
if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2:
if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default: state <= #1 IDLE;
endcase
end
endmodule
| 7.229634 |
module fsm2 (
clock,
reset,
req,
gnt
);
input clock, reset;
inout [1:0] req;
output [1:0] gnt;
wire clock, reset;
wire [1:0] req;
reg [1:0] gnt;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101, GNT3 = 3'b111;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @(posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt[0] <= 0;
gnt[1] <= 0;
end else
case (state)
IDLE:
if (req[0] == 1'b1) begin
state <= #1 GNT0;
gnt[0] <= 1;
end else if (req[1] == 1'b1) begin
gnt[1] <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0:
if (gnt[1] == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt[1] <= 0;
state <= #1 IDLE;
end
GNT1:
if (req[1] == 1'b1) begin
state <= #1 GNT2;
gnt[1] <= req[1];
end
GNT2:
if (gnt[0] == 1'b1) begin
state <= #1 GNT1;
gnt[1] <= req[1];
end
default: state <= #1 IDLE;
endcase
end
endmodule
| 6.534312 |
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
wire [1:0] g;
wire [1:0] r;
fsm u_fsm (
.clock(clk),
.reset(rst),
.req (r),
.gnt (g)
);
assign g0 = g[0];
assign g1 = g[1];
assign r[0] = a;
assign r[1] = b;
endmodule
| 7.233807 |
module top (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 7.233807 |
module top (
input [7:0] x,
input [7:0] y,
input cin,
output reg [7:0] A,
output [7:0] cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle #(7) u_mid (
.x(x),
.o(o),
.y(1'b0)
);
middle #(0) u_mid2 (
.x(x),
.o(o)
);
`else
assign {cout, A} = cin - y * x;
`endif
endmodule
| 7.233807 |
module middle (
x,
y,
o
);
parameter u = 7;
input [u:0] x;
input [u:0] y;
output [u:0] o;
assign o = x + y;
endmodule
| 6.553865 |
module top (
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle u_mid (
.x(x),
.o(o),
.y(1'b0)
);
u_rtl inst_u_rtl (
.x(x),
.o(o)
);
`else
assign {cout, A} = cin - y * x;
`endif
endmodule
| 7.233807 |
module middle (
input x,
input y,
output o
);
wire w;
assign o = x + y;
endmodule
| 6.553865 |
module u_rtl (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 6.750051 |
module top_example_adder #(
parameter integer C_AXIS_TDATA_WIDTH = 512, // Data width of both input and output data
parameter integer C_ADDER_BIT_WIDTH = 32
) (
input wire aclk,
input wire aresetn,
input wire [C_ADDER_BIT_WIDTH-1:0] ctrl_constant,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire [ C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep,
input wire s_axis_tlast,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire [ C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep,
output wire m_axis_tlast
);
localparam integer LP_NUM_LOOPS = C_AXIS_TDATA_WIDTH / C_ADDER_BIT_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Variables
/////////////////////////////////////////////////////////////////////////////
integer i;
reg [ C_ADDER_BIT_WIDTH-1:0] constant_in;
reg [C_AXIS_TDATA_WIDTH-1:0] data_out;
reg areset = 1'b0;
/////////////////////////////////////////////////////////////////////////////
// Adder Logic
/////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset <= ~aresetn;
end
// Register constant, should be set before stream.
always @(posedge aclk) begin
constant_in <= ctrl_constant;
end
// Adder function
always @(*) begin
for (i = 0; i < LP_NUM_LOOPS; i = i + 1) begin
data_out[i*C_ADDER_BIT_WIDTH+:C_ADDER_BIT_WIDTH] = s_axis_tdata[C_ADDER_BIT_WIDTH*i+:C_ADDER_BIT_WIDTH] + constant_in;
end
end
assign m_axis_tdata = data_out;
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tready;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tlast = s_axis_tlast;
endmodule
| 8.220099 |
module top_fc #(
parameter integer C_S00_AXIS_TDATA_WIDTH = 32
) (
input wire CLK,
input wire RESETN,
/// For AXIS protocol
output wire S_AXIS_TREADY,
input wire [ C_S00_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
input wire [(C_S00_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TKEEP,
input wire S_AXIS_TUSER,
input wire S_AXIS_TLAST,
input wire S_AXIS_TVALID,
input wire M_AXIS_TREADY,
output wire M_AXIS_TUSER,
output wire [ C_S00_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
output wire [(C_S00_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TKEEP,
output wire M_AXIS_TLAST,
output wire M_AXIS_TVALID,
/// For APB protocol
input wire [31:0] PADDR,
input wire PENABLE,
input wire PSEL,
input wire PWRITE,
input wire [31:0] PWDATA,
output wire [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR
);
// For FC control path
wire fc_start;
wire fc_done;
wire [31:0] clk_counter;
wire [31:0] max_index;
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
wire [20:0] receive_size;
wire [2:0] receiveCommand;
wire feature_receive_done;
wire bias_receive_done;
wire weight_receive_done;
clk_counter_fc u_clk_counter (
.clk(CLK),
.rstn(RESETN),
.start(fc_start),
.done(fc_done),
.clk_counter(clk_counter)
);
apb_fc u_apb_fc (
.PCLK(CLK),
.PRESETB(RESETN),
.PADDR({16'd0, PADDR[15:0]}),
.PSEL(PSEL),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PWDATA(PWDATA),
.fc_done(fc_done),
.clk_counter(clk_counter),
.max_index(max_index),
.PRDATA(PRDATA),
.receive_size(receive_size),
.receiveCommand(receiveCommand),
.feature_receive_done(feature_receive_done),
.bias_receive_done(bias_receive_done),
.weight_receive_done(weight_receive_done)
);
fc_module u_fc (
.clk(CLK),
.rstn(RESETN),
.S_AXIS_TREADY(S_AXIS_TREADY),
.S_AXIS_TDATA(S_AXIS_TDATA),
.S_AXIS_TKEEP(S_AXIS_TKEEP),
.S_AXIS_TUSER(S_AXIS_TUSER),
.S_AXIS_TLAST(S_AXIS_TLAST),
.S_AXIS_TVALID(S_AXIS_TVALID),
.M_AXIS_TREADY(M_AXIS_TREADY),
.M_AXIS_TUSER(M_AXIS_TUSER),
.M_AXIS_TDATA(M_AXIS_TDATA),
.M_AXIS_TKEEP(M_AXIS_TKEEP),
.M_AXIS_TLAST(M_AXIS_TLAST),
.M_AXIS_TVALID(M_AXIS_TVALID),
.max_index(max_index),
.fc_done(fc_done),
.receive_size(receive_size),
.receiveCommand(receiveCommand),
.feature_receive_done(feature_receive_done),
.bias_receive_done(bias_receive_done),
.weight_receive_done(weight_receive_done)
);
endmodule
| 7.137185 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDCE ff (
.C (clk),
.CE (ce),
.CLR(sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top (
input clk,
ce,
sr,
d,
output q
);
/*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
cliff didn't have constrained, also got annoyed
he is using slightly later version
ERROR: [Place 30-1008] Instance roi/ffs[0].genblk1.genblk1.ff
has an inverted D pin which is unsupported in the UltraScale and UltraScale+ architectures.
which is fine except...he's using 7 series
and now...
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-488] Failed to commit 1 instances:
ff with block Id: 4 (FF) at SLICE_X0Y104
ERROR: [Place 30-99] Placer failed with error: 'failed to commit all instances'
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b1,
failed with same message
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b0,
built!
diff design_fdce.segd design_fdce_inv.segd
> tag CLBLL_L.SLICEL_X0.CLKINV
expected
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b0,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer stopped due to earlier errors.
Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
*/
(*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b0,
LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH
*)
FDCE ff (
.C (clk),
.CE (ce),
.CLR(sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDPE ff (
.C (clk),
.CE (ce),
.PRE(sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDRE ff (
.C (clk),
.CE(ce),
.R (sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDSE ff (
.C (clk),
.CE(ce),
.S (sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top_fetch #(
parameter PC_DATA_WIDTH = 20,
parameter INSTRUCTION_WIDTH = 32,
parameter PC_INITIAL_ADDRESS = 20'h0
) (
input clk, // CPU core clock
input rst_n, // CPU core reset active low
input en,
input stall, // Indicates a stall insertion on the datapath
// input flush, // Force flush in pipeline registers
// input [INSTRUCTION_WIDTH-1:0] inst_mem_data_in, // SRAM input data
input select_new_pc_in, // Signal used for branch not taken
input [PC_DATA_WIDTH-1:0] new_pc_in, // New value of Program Counter
// output reg [PC_DATA_WIDTH-1:0] new_pc_out, // Updated value of the Program Counter
output [PC_DATA_WIDTH-1:0] pc_out, // Value of the Program Counter
// output reg [INSTRUCTION_WIDTH-1:0] instruction_reg_out, // CPU core fetched instruction
output [PC_DATA_WIDTH-1:0] inst_mem_addr_out, // Instruction SRAM address bus
input boot_mode
);
reg [PC_DATA_WIDTH-1:0] pc;
reg [PC_DATA_WIDTH-1:0] pc_mux_data;
reg [PC_DATA_WIDTH-1:0] pc_adder_data;
// -------------------------------------------------------------
// Multiplex to select new PC value
// -------------------------------------------------------------
always @(*) begin
case (select_new_pc_in)
0: pc_mux_data = pc_adder_data;
1: pc_mux_data = new_pc_in;
endcase
end
// -------------------------------------------------------------
// Program Counter adder
// -------------------------------------------------------------
always @(*) begin
pc_adder_data = pc + 20'd4;
end
// -------------------------------------------------------------
// Program Counter regireg [FUNCTION_WIDTH-1:0] inst_function,ster
// -------------------------------------------------------------
assign inst_mem_addr_out = pc;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
pc <= PC_INITIAL_ADDRESS;
end else if (boot_mode) begin
pc <= PC_INITIAL_ADDRESS;
end else if ((!stall) & en) begin
pc <= pc_mux_data;
end
end
assign pc_out = pc;
// -------------------------------------------------------------
// Pipeline Registers
// The if_id pipe needs only this
// ++TODO: Plance this procedure into a module.
// -------------------------------------------------------------
// always@(posedge clk or negedge rst_n)begin
// if(!rst_n) begin
// new_pc_out <= 0;
// instruction_reg_out <= 0;
// end else if(!stall)begin
// new_pc_out <= pc;
// if(flush)begin
// instruction_reg_out <= 0;
// end
// else begin
// instruction_reg_out <= inst_mem_data_in;
// end
// end
// end
endmodule
| 8.327742 |
module adff (
d,
clk,
clr,
q
);
input d, clk, clr;
(* init = 1'h0 *)
output reg q;
initial begin
q = 0;
end
always @(posedge clk, posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.095675 |
module adff (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.089232 |
module adffn (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
| 7.422273 |
module dffe (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
| 7.085902 |
module dffsr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge pre, posedge clr)
if (clr) q <= 1'b0;
else if (pre) q <= 1'b1;
else q <= d;
endmodule
| 6.804969 |
module ndffnsnr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(negedge clk, negedge pre, negedge clr)
if (!clr) q <= 1'b0;
else if (!pre) q <= 1'b1;
else q <= d;
endmodule
| 7.273757 |
module top (
input clk,
input clr,
input pre,
input a,
output b,
b1,
b2,
b3,
b4
);
dffsr u_dffsr (
.clk(clk),
.clr(clr),
.pre(pre),
.d (a),
.q (b)
);
ndffnsnr u_ndffnsnr (
.clk(clk),
.clr(clr),
.pre(pre),
.d (a),
.q (b1)
);
adff u_adff (
.clk(clk),
.clr(clr),
.d (a),
.q (b2)
);
adffn u_adffn (
.clk(clk),
.clr(clr),
.d (a),
.q (b3)
);
dffe u_dffe (
.clk(clk),
.en (clr),
.d (a),
.q (b4)
);
endmodule
| 7.233807 |
module top_FFT
(
input IN_PLLClock,Reset,
`ifndef NO_DAI
//For DAI
input BCK,LRCK,SData,
`endif
//For SRAM
output nWE,nOE,
inout [14:0] SRAMIO,
output [17:0] SRAMAddr,
//For LCDs
output DotClock,VS,HS,
output [14:0] L_RGB, R_RGB
//Debug Pin
`ifndef SIM
,
output [1:0] LED
`endif
);
////////////////////////////////////////////////////
// Instansiation
localparam bw_data = `BW_DATA; //DAI出力ビット幅
localparam bw_fftdata = `BW_FFTDATA; //FFT入力ビット幅
localparam bw_fftp = `BW_FFTPOINT; //FFT要素数 2^x
localparam bw_dpram = `BW_FFTPOINT+1;
`ifdef SIM
pdo_PLL pll(.Clock(PLLClock),.Reset(Reset));
`else //Synthesys
PLL pll (.CLK(IN_PLLClock), .CLKOP(PLLClock) ,.CLKOS(Clock));
LED_Flicker #(.bw_cntr(26)) cntr0(PLLClock,Reset,LED[0]);
LED_Flicker #(.bw_cntr(24)) cntr1(IN_PLLClock,Reset,LED[1]);
`endif
// 1/4 Clock Divider
CLKDIVB clock_div (.RST(Reset),.CLKI(IN_PLLClock),.RELEASE(1'b1),
.CDIV4(DotClock));
//CLKOP = 64MHz
//CLOKOS = IN_PLLClock スルー
`ifdef NO_DAI
pdo_Cacher #(
.bw_dpram(bw_dpram),
.bw_data(bw_data))
pdo_cacher (
.Clock(PLLClock),
.Reset(Reset),
.DPRAMAddr(DPRAMAddr),
.RAM_Q(RAM_Q)
);
`else
//波形保存
Cacher #(
.bw_dpram(bw_dpram),
.bw_data(bw_data))
cacher (
.Clock(PLLClock),
.Reset(Reset),
.BCK(BCK),
.LRCK(LRCK),
.SData(SData),
.DPRAMAddr(DPRAMAddr),
.RAM_Q(RAM_Q)
);
`endif
wire [bw_fftp:0] DPRAMAddr;
wire [bw_data-1:0] RAM_Q;
//スペクトル化
Spectolizer2 #(
.bw_fftp(bw_fftp),
.bw_data(bw_data),
.bw_fftdata(bw_fftdata))
top_sl (
.Clock(PLLClock), //i
.Reset(Reset), //i
//For Cacher
.RAM_Q(RAM_Q), //i
.DPRAMAddr(DPRAMAddr), //i
//For VRAMControl
.SWClockEn(SWClockEn), //i
.StartLoader(StartLoader), //i
.Color(Color), //o
.Screen(Screen), //o
.X(X), //o
.Y(Y) //o
);
wire [8:0] X;
wire [6:0] Y;
wire [14:0] Color;
//VRAM Control
VRAMCtrl vramcont
(
.Clock(PLLClock),
.Reset(Reset),
.DotClock(DotClock),
//For Spectol Writer
.Screen(Screen),
.WrAdr_X(X), //i
.WrAdr_Y(Y), //i
.WriteData(Color), //i
.SWClockEn(SWClockEn), //o
//For SRAM
.nWE(nWE), //o
.nOE(nOE), //o
.Address(SRAMAddr), //o
.IO(SRAMIO), //io
.R_RGB(R_RGB) , //o
.L_RGB(L_RGB), //o
.VS(VS), //o
.HS(HS), //o
.StartLoader(StartLoader) //o
);
defparam vramcont.hs_offset_minus = 1;
endmodule
| 6.678605 |
module top_FFT
(
input Clock,Reset,
//For DAI
input BCK,LRCK,SData,
//For SRAM
output nWE,
inout [14:0] SRAMIO,
output [17:0] SRAMAddr,
//For LCDs
output DotClock,VS,HS,
output [14:0] L_RGB, R_RGB
);
////////////////////////////////////////////////////
// Instansiation
// 1/4 Clock Divider
CLKDIVB clock_div (.RST(Reset),.CLKI(Clock),.RELEASE(1'b1),
.CDIV4(DotClock));
//PLL
`ifdef `SIMULATION
pdo_PLL pll(PLLClock);
`else
PLL pll (.CLK(Clock), .CLKOP(PLLClock), .LOCK());
`endif
localparam bw_romaddr = 6;
//波形保存
Cacher #(.bw_romaddr(bw_romaddr))
cacher (
.Clock(PLLClock),
.Reset(Reset),
.BCK(BCK),
.LRCK(LRCK),
.SData(SData),
.DPRAMAddr(DPRAMAddr),
.DataL(DataL),
.DataR(DataR)
);
wire [bw_romaddr-1:0] DPRAMAddr;
wire [8:0] DataL,DataR;
//スペクトル化
Spectolizer #(.bw_romaddr(bw_romaddr))
top_sl (
.Clock(PLLClock), //i
.Reset(Reset), //i
//For Cacher
.DataR(DataR), //i
.DataL(DataL), //i
.DPRAMAddr(DPRAMAddr), //i
//For VRAMControl
.SWClockEn(SWClockEn), //i
.StartLoader(StartLoader), //i
.Color(Color), //o
.Screen(Screen), //o
.X(X), //o
.Y(Y) //o
);
wire [8:0] X;
wire [6:0] Y;
wire [14:0] Color;
//VRAM Control
VRAMCtrl vramcont
(
.Clock(PLLClock),
.DotClock(DotClock),
.Reset(Reset),
.X(X),
.Y(Y),
.WriteData(Color),
.SWClockEn(SWClockEn),
.nWE(nWE),
.Address(SRAMAddr),
.IO(SRAMIO),
.R_RGB(R_RGB) ,
.L_RGB(L_RGB),
.VS(VS),
.HS(HS),
.StartLoader(StartLoader)
);
endmodule
| 6.678605 |
module adff (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.089232 |
module adffn (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
| 7.422273 |
module dffe (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
| 7.085902 |
module dffsr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge pre, posedge clr)
if (clr) q <= 1'b0;
else if (pre) q <= 1'b1;
else q <= d;
endmodule
| 6.804969 |
module ndffnsnr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(negedge clk, negedge pre, negedge clr)
if (!clr) q <= 1'b0;
else if (!pre) q <= 1'b1;
else q <= d;
endmodule
| 7.273757 |
module top (
input clk,
input clr,
input pre,
input a,
output b,
b1,
b2,
b3,
b4
);
dffsr u_dffsr (
.clk(clk),
.clr(clr),
.pre(pre),
.d (a),
.q (b)
);
ndffnsnr u_ndffnsnr (
.clk(clk),
.clr(clr),
.pre(pre),
.d (a),
.q (b1)
);
adff u_adff (
.clk(clk),
.clr(clr),
.d (a),
.q (b2)
);
adffn u_adffn (
.clk(clk),
.clr(clr),
.d (a),
.q (b3)
);
dffe u_dffe (
.clk(clk),
.en (clr),
.d (a),
.q (b4)
);
endmodule
| 7.233807 |
module top_FIFO (
input clk_125M,
input reset,
input read,
input write,
input [3:0] din,
output full,
output empty,
output almost_empty,
output almost_full,
output [3:0] data_count,
output [3:0] dout
);
wire clk_5M, clk_200H, clk_pulse;
clk_wiz_0 in1 (
.clk_out1(clk_5M),
.clk_in1 (clk_125M)
);
clk_divider #(
.div_value(12499)
) in2 (
.clk_in(clk_5M),
.divided_clk(clk_200H)
);
clk_pulse in3 (
.clk_200H(clk_200H),
.inp_0(read),
.inp_1(write),
.clk_pulse(clk_pulse)
);
fifo_generator_0 your_in4 (
.clk (clk_pulse), // input wire clk
.srst (reset), // input wire srst
.din (din), // input wire [3 : 0] din
.wr_en (write), // input wire wr_en
.rd_en (read), // input wire rd_en
.dout (dout), // output wire [3 : 0] dout
.full (full), // output wire full
.almost_full (almost_full), // output wire almost_full
.empty (empty), // output wire empty
.almost_empty(almost_empty), // output wire almost_empty
.data_count (data_count) // output wire [3 : 0] data_count
);
ila_0 in5 (
.clk (clk_125M), // input wire clk
.probe0(din), // input wire [3:0] probe0
.probe1(dout), // input wire [3:0] probe1
.probe2(data_count), // input wire [3:0] probe2
.probe3(read), // input wire [0:0] probe3
.probe4(write), // input wire [0:0] probe4
.probe5(reset), // input wire [0:0] probe5
.probe6(full), // input wire [0:0] probe6
.probe7(almost_full), // input wire [0:0] probe7
.probe8(empty), // input wire [0:0] probe8
.probe9(almost_empty) // input wire [0:0] probe9
);
endmodule
| 6.705486 |
module errors_prompt (
input [3:0] errors,
input clock,
output reg errors_go
);
localparam S_WAIT = 4'd0, S_PROMPT = 4'd1;
reg [3:0] current_state = S_WAIT;
reg [3:0] next_state;
always @(*) begin : state_table
case (current_state)
S_WAIT: next_state = (errors == 4'b0) ? S_WAIT : S_PROMPT;
S_PROMPT: next_state = S_WAIT;
endcase
end
always @(posedge clock) begin
current_state <= next_state;
end
always @(*) begin
errors_go = 1'b0;
case (current_state)
S_PROMPT: errors_go <= 1'b1;
endcase
end
endmodule
| 8.192581 |
module top_fir_lpf (
input wire sclk,
input wire rst_n,
output wire [20:0] lpf_wave
);
wire [7:0] o_wave;
wire lpf_wave_v;
wire [1:0] lpf_wave_ast_source_error;
wire ast_sink_ready;
dds_1M_10M dds_1M_10M_instance (
.sclk (sclk),
.rst_n (rst_n),
.o_wave(o_wave)
);
fir_lpf fir_lpf_instance (
.clk (sclk), // clk.clk
.reset_n (rst_n), // rst.reset_n
.coeff_in_clk (sclk), // coeff_clock.clk
.coeff_in_areset (rst_n), // coeff_reset.reset_n
.ast_sink_data (o_wave), // avalon_streaming_sink.data
.ast_sink_ready (ast_sink_ready), // .ready
.ast_sink_valid (1'b1), // .valid
.ast_sink_error (2'b00), // .error
.ast_source_data (lpf_wave), // avalon_streaming_source.data
.ast_source_ready(1'b1), // .ready
.ast_source_valid(lpf_wave_v), // .valid
.ast_source_error(lpf_wave_ast_source_error) // .error
);
endmodule
| 8.025532 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'FLAT_UNROLL_ALL_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/FLAT_UNROLL_ALL_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/FLAT_UNROLL_ALL_V/sim_FLAT_UNROLL_ALL_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'FLAT_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/FLAT_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/FLAT_V/sim_FLAT_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module top_fnd_display (
input i_clk,
i_reset,
input [7:0] i_data,
output [7:0] o_fndData,
output [3:0] o_fndSelect
);
wire [1:0] w_cnt_2bit;
wire w_1khz;
wire [3:0] w_digit_0, w_digit_1, w_digit_2, w_digit_3, w_data;
clockDivider #(
.MAX_COUNT(50_000)
) clkDiv_1khz (
.i_clk (i_clk),
.i_reset(i_reset),
.o_clk (w_1khz)
);
counter_2bit(
.i_clk(w_1khz), .i_reset(i_reset), .o_cnt(w_cnt_2bit)
); decoder_2x4(
.i_sel(w_cnt_2bit), .o_sel(o_fndSelect)
); digit_divider(
.i_data(i_data),
.o_digit_0(w_digit_0),
.o_digit_1(w_digit_1),
.o_digit_2(w_digit_2),
.o_digit_3(w_digit_3)
); mux_4x1(
.i_sel(w_cnt_2bit),
.i_a(w_digit_0),
.i_b(w_digit_1),
.i_c(w_digit_2),
.i_d(w_digit_3),
.o_y(w_data)
); fnd_decoder(
.i_data(w_data), .o_fndFont(o_fndData)
);
endmodule
| 6.544602 |
module top_top_formal_verification_random_tb;
// ----- Default clock port is added here since benchmark does not contain one -------
reg [0:0] clk;
// ----- Shared inputs -------
reg [0:0] a;
reg [0:0] b;
// ----- FPGA fabric outputs -------
wire [0:0] out:c_gfpga;
`ifdef AUTOCHECKED_SIMULATION
// ----- Benchmark outputs -------
wire [0:0] out:c_bench;
// ----- Output vectors checking flags -------
reg [0:0] out:c_flag;
`endif
// ----- Error counter -------
integer nb_error= 0;
// ----- FPGA fabric instanciation -------
top_top_formal_verification FPGA_DUT(
.a_fm(a),
.b_fm(b),
.out:c_fm(out:c_gfpga) );
// ----- End FPGA Fabric Instanication -------
`ifdef AUTOCHECKED_SIMULATION
// ----- Reference Benchmark Instanication -------
top REF_DUT(
.a(a),
.b(b),
.c(out:c_bench) );
// ----- End reference Benchmark Instanication -------
`endif
// ----- Clock Initialization -------
initial begin
clk[0] <= 1'b0;
while(1) begin
#0.4159859701
clk[0] <= !clk[0];
end
end
// ----- Input Initialization -------
initial begin
a <= 1'b0;
b <= 1'b0;
out:c_flag[0] <= 1'b0;
end
// ----- Input Stimulus -------
always@(negedge clk[0]) begin
a <= $random;
b <= $random;
end
`ifdef AUTOCHECKED_SIMULATION
// ----- Begin checking output vectors -------
// ----- Skip the first falling edge of clock, it is for initialization -------
reg [0:0] sim_start;
always@(negedge clk[0]) begin
if (1'b1 == sim_start[0]) begin
sim_start[0] <= ~sim_start[0];
end else begin
if(!(out:c_gfpga === out:c_bench) && !(out:c_bench === 1'bx)) begin
out:c_flag <= 1'b1;
end else begin
out:c_flag<= 1'b0;
end
end
end
always@(posedge out:c_flag) begin
if(out:c_flag) begin
nb_error = nb_error + 1;
$display("Mismatch on out:c_gfpga at time = %t", $realtime);
end
end
`endif
`ifdef ICARUS_SIMULATOR
// ----- Begin Icarus requirement -------
initial begin
$dumpfile("top_formal.vcd");
$dumpvars(1, top_top_formal_verification_random_tb);
end
`endif
// ----- END Icarus requirement -------
initial begin
sim_start[0] <= 1'b1;
$timeformat(-9, 2, "ns", 20);
$display("Simulation start");
// ----- Can be changed by the user for his/her need -------
#332
if(nb_error == 0) begin
$display("Simulation Succeed");
end else begin
$display("Simulation Failed with %d error(s)", nb_error);
end
$finish;
end
endmodule
| 7.093103 |
module TOP_for_debug #(
parameter BYTE = 8,
parameter DWORD = 32,
parameter ADDR = 5,
parameter NB_MEM_DEPTH = 8,
parameter RB_ADDR = 5,
parameter NB_STATE = 10
) (
input i_clock,
input i_reset,
input i_clock_reset,
input i_rx_done,
input i_tx_done,
input [BYTE-1:0] i_rx_data,
output o_halt,
output [NB_STATE-1:0] o_state,
output [ BYTE-1:0] o_tx_data,
output o_tx_start
);
wire clk_wiz;
clk_wiz_0 clk_wizard (
.clk_out1(clk_wiz),
.reset(i_clock_reset),
.locked(),
.clk_in1(i_clock)
);
wire step_flag;
wire halt;
wire mem_enable;
wire read_memory_data_from_du;
wire mem_read_enable;
wire [ DWORD-1:0] mem_data;
wire [ ADDR-1:0] mem_addr;
wire rb_enable;
wire rb_read_enable;
wire [ DWORD-1:0] rb_data;
wire [ RB_ADDR-1:0] rb_addr;
wire im_enable;
wire im_write_enable;
wire im_read_enable;
wire [ BYTE-1:0] im_addr;
wire [ BYTE-1:0] im_data;
wire unit_control_enable;
wire pc_enable;
wire [ DWORD-1:0] pc;
wire [NB_STATE-1:0] state;
wire PIPELINE_enable;
debug_unit debug_unit (
.i_clock(clk_wiz), // 50 MHz
.i_reset(i_reset),
.i_halt(halt),
.i_rx_done(i_rx_done),
.i_tx_done(i_tx_done),
.i_rx_data(i_rx_data),
.i_pc_value(pc),
.i_mem_data(mem_data),
.i_bank_reg_data(rb_data),
.o_instru_mem_data(im_data),
.o_instru_mem_addr(im_addr),
.o_rb_addr(rb_addr),
.o_mem_data_addr(mem_addr),
.o_tx_data(o_tx_data),
.o_tx_start(o_tx_start),
.o_instru_mem_write_enable(im_write_enable),
.o_instru_mem_read_enable(im_read_enable),
.o_instru_mem_enable(im_enable),
.o_rb_read_enable(rb_read_enable),
.o_rb_enable(rb_enable),
.o_mem_data_enable(mem_enable),
.o_mem_data_read_enable(mem_read_enable),
.o_mem_data_debug_unit(read_memory_data_from_du),
.o_unit_control_enable(unit_control_enable),
.o_pc_enable(pc_enable),
.o_state(state),
.o_pipeline_enable(PIPELINE_enable)
);
PIPELINE PIPELINE (
.i_clock(clk_wiz), // 50 MHz
.i_pc_enable(pc_enable),
.i_pc_reset(i_reset),
.i_read_enable(im_read_enable),
.i_ID_reset(i_reset),
.i_reset_forward_stall(i_reset),
.i_pipeline_enable(PIPELINE_enable),
.i_MEM_debug_unit_flag(read_memory_data_from_du),
.i_instru_mem_enable(im_enable),
.i_instru_mem_write_enable(im_write_enable),
.i_instru_mem_data(im_data),
.i_instru_mem_addr(im_addr),
.i_bank_register_enable(rb_enable),
.i_bank_register_read_enable(rb_read_enable),
.i_bank_register_addr(rb_addr),
.i_mem_data_enable(mem_enable),
.i_mem_data_read_enable(mem_read_enable),
.i_mem_data_read_addr(mem_addr),
.i_unit_control_enable(unit_control_enable),
.o_halt(halt),
.o_bank_register_data(rb_data),
.o_mem_data_data(mem_data),
.o_last_pc(pc)
);
assign o_state = state;
assign o_halt = halt;
endmodule
| 6.899901 |
module top_for_testing (
result_wire,
result,
finished_wire,
rx_data,
rx_ready,
clk,
rst
);
output [63:0] result_wire;
output [7:0] result;
output finished_wire;
input [7:0] rx_data;
input rx_ready, clk, rst;
wire MEM_we, data_collection_finish, collect_finish_display;
wire [13:0] MEM_wr_sel;
wire [7:0] MEM_wr_data;
wire finished_wire;
Data_collect // Collect all the data from PC by UART
//#(.NUM_DATA(NUM_DATA))
Data_collect (
.clk(clk),
.rst(rst),
.data_input(rx_data),
.data_ready(rx_ready),
.calced(finished_wire),
.MEM_write_enable(MEM_we),
.MEM_write_addr(MEM_wr_sel),
.MEM_write_data(MEM_wr_data),
.finish(data_collection_finish),
.collect_finish_display(collect_finish_display)
);
predictor ml_proto (
result_wire,
finished_wire,
MEM_we,
MEM_wr_sel,
MEM_wr_data,
collect_finish_display,
clk,
rst
);
endmodule
| 7.235732 |
module top_fpga (
input wire PCLK,
input wire PRESETn,
input wire PSEL,
input wire PENABLE,
input wire PWrite,
input wire [3:0] button,
inout i2c_sda,
inout i2c_scl,
output PREADY,
output [2:0] ADDRE,
output [7:0] DATA
);
//////change PADDR,PWDATA,length,frequency here //////
localparam [15:0] FREQ = 15'd24999; //7;//24999;
localparam [6:0] slave_address = 7'b101_0111; //7'd87;
localparam [31:0] data_sent = 32'habcd_ef98;
localparam [1:0] length = 3;
///////////////////////////////////////
wire rw;
wire ready;
wire enable;
reg clk = 1;
reg [1:0] bytcount = 0;
reg [6:0] PADDR = 0;
reg [31:0] PWDATA = 0;
reg [15:0] ccount = 0;
reg [1:0] I = 0;
assign rw = ~PWrite;
assign PREADY = ready;
assign enable = PSEL & PENABLE;
always @(*) begin
case (button)
4'b0000: I <= 2'b00;
4'b0001: I <= 2'b00;
4'b0010: I <= 2'b01;
4'b0100: I <= 2'b10;
4'b1000: I <= 2'b11;
default: I <= 2'b00;
endcase
end
always @(posedge PCLK) begin
if (PRESETn) begin
PADDR <= slave_address;
PWDATA <= data_sent;
bytcount <= length;
end
end
always @(posedge PCLK) begin
if (PRESETn) begin
if (ccount == FREQ) begin
clk <= ~clk;
ccount <= 0;
end else ccount <= ccount + 1'b1;
end else begin
ccount <= 0;
clk <= 1;
end
end
i2c_mast mast (
//from apb
.clk(clk),
.rst(PRESETn),
.enable(enable),
.rw(rw),
.bytcount(bytcount),
.addr(PADDR),
.Din(PWDATA),
//to apb
.ready(ready),
//.rdata(PRDATA),
//to slave
.i2c_sda(i2c_sda),
.i2c_scl(i2c_scl),
//top
.DATA(DATA),
.ADDRE(ADDRE),
.I(I)
);
endmodule
| 8.279586 |
module: top_fpga
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_fpga_tb;
// Inputs
reg PCLK;
reg PRESETn;
reg PSEL;
reg PENABLE;
reg PWrite;
reg [1:0] I;
// Outputs
wire PREADY;
wire [2:0] ADDRE;
wire [7:0] DATA;
// Bidirs
wire i2c_sda;
wire i2c_scl;
pullup(i2c_sda);
pullup(i2c_scl);
// Instantiate the Unit Under Test (UUT)
top_fpga uut (
.PCLK(PCLK),
.PRESETn(PRESETn),
.PSEL(PSEL),
.PENABLE(PENABLE),
.PWrite(PWrite),
.i2c_sda(i2c_sda),
.i2c_scl(i2c_scl),
.PREADY(PREADY),
.ADDRE(ADDRE),
.DATA(DATA)
);
always #5 PCLK <= ~PCLK;
initial begin
// Initialize Inputs
PCLK = 1;
PRESETn = 0;
PSEL = 0;
PENABLE = 0;
PWrite = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
PRESETn = 1;
PSEL = 1;
PENABLE = 1;
PWrite = 1;
end
reg sl_sda = 1'bz;
reg sl_scl = 1'bz;
assign i2c_sda = sl_sda;
assign i2c_scl = sl_scl;
initial begin
I = 0;
#6010 I = 0;
#3040 I = 1;
#2900 I = 2;
#2900 I = 3;
end
initial begin
sl_sda = 1'bz;
#3050 sl_sda = 1'b0;
#240 sl_sda = 1'bz;
#2720 sl_sda = 1'b0;
#160 sl_sda = 1'bz;
#2720 sl_sda = 1'b0;
#160 sl_sda = 1'bz;
#2720 sl_sda = 1'b0;
#160 sl_sda = 1'bz;
#2720 sl_sda = 1'b0;
#160 sl_sda = 1'bz;
end
// initial begin
// #6170 sl_scl = 1'b0;
// #400 sl_scl = 1'bz;
// end
endmodule
| 7.092709 |
module: top_fpu_add
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_fpu_add_tb;
// Inputs
reg clk;
reg up_button;
reg [8:1] sw;
// Outputs
wire [3:0] leds_l;
wire [3:0] leds_r;
wire serial1_tx;
// Instantiate the Unit Under Test (UUT)
top_fpu_add uut (
.clk(clk),
.up_button(up_button),
.sw(sw),
.leds_l(leds_l),
.leds_r(leds_r),
.serial1_tx(serial1_tx)
);
initial begin
// Initialize Inputs
clk = 0;
up_button = 1'b1;
sw = 0;
repeat(4)
#10 clk = ~clk;
up_button = 1'b0;
forever
#10 clk = ~clk;
end
initial begin
#20000;
$finish;
end
endmodule
| 7.455915 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.