code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock, reset, req_0, req_1;
output gnt_0, gnt_1;
wire clock, reset, req_0, req_1;
reg gnt_0, gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @(posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case (state)
IDLE:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1:
if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2:
if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default: state <= #1 IDLE;
endcase
end
endmodule
| 7.229634 |
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm (
.clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1)
);
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout, A} = cin + y + x;
`else
assign {cout, A} = cin - y * x;
`endif
endmodule
| 7.233807 |
module top_Game (
input wire CLK100MHZ,
input wire vauxp2,
input wire vauxn2,
input wire vauxp3,
input wire vauxn3,
input wire vauxp10,
input wire vauxn10,
input wire vauxp11,
input wire vauxn11,
input wire vp_in,
input wire vn_in,
input wire [3:0] sw,
output wire [15:0] LED_top,
output wire [7:0] an_top_ADC,
output wire dp_top_ADC,
output wire [6:0] seg_top_ADC,
input wire RST_BTN,
input wire BTNC,
output wire vga_hs_top, // horizontal sync
output wire vga_vs_top, // vertical sync
output wire [3:0] vga_r_top, // red channels
output wire [3:0] vga_g_top, // green channels
output wire [3:0] vga_b_top // blue channels
);
wire [11:0] decimal_reg_in_top;
wire [1:0] BTN_LR; //control button for game, transferred from the analog signal.
wire [6:0] seg_top;
wire an_top;
wire [15:0] LED;
wire [3:0] Speed;
top_XADC top_ADC (
.CLK100MHZ(CLK100MHZ),
.vauxp2(vauxp2),
.vauxn2(vauxn2),
.vauxp3(vauxp3),
.vauxn3(vauxn3),
.vauxp10(vauxp10),
.vauxn10(vauxn10),
.vauxp11(vauxp11),
.vauxn11(vauxn11),
.vp_in(vp_in),
.vn_in(vn_in),
.sw(sw),
.LED(LED),
.an(an_top_ADC),
.dp(dp_top_ADC),
.seg(seg_top_ADC),
.decimal_reg_in(decimal_reg_in_top)
);
top_pong top_Pong (
.CLK(CLK100MHZ), // 100 Mhz clock
.RST_BTN(RST_BTN), // reset button
.BTN_LR(BTN_LR), // left and right buttons
.Speed(Speed), //Step size of movement
.BTNC(BTNC), // mode change button
.VGA_HS(vga_hs_top), // horizontal sync
.VGA_VS(vga_vs_top), // vertical sync
.VGA_R(vga_r_top), // red channels
.VGA_G(vga_g_top), // green channels
.VGA_B(vga_b_top), // blue channels
.seg(seg_top), // 7-segment segments
.AN(an_top) // 7-segment anodes
);
analog2game ag (
.CLK100MHZ(CLK100MHZ), //
.analog_in(decimal_reg_in_top), //from adc, 16 bit input
.SW_direction(sw[3:2]),
.Speed(Speed),
.BTN_LR(BTN_LR) //out to game top module
);
assign LED_top[0] = BTN_LR[0];
assign LED_top[1] = BTN_LR[1];
assign LED_top[2] = sw[2];
assign LED_top[3] = sw[3];
endmodule
| 7.733288 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
parameter u = 0;
genvar index;
generate
for (index = 0; index < 8; index = index + 1) begin : gen_code_label
end
endgenerate
genvar index;
generate
case (u)
0: begin
end
1: begin
end
2: begin
end
3: begin
end
endcase
endgenerate
// reg angle;
// case (index)
// //Create the case statement
// 1 :
// begin
// generate
// genvar caseIndex;
// for (caseIndex = 0; caseIndex < 1024; caseIndex=caseIndex+1)
// begin
// caseIndex: angle = 2*pi*caseIndex/1024;
// end
// endgenerate
// end
// endcase
endmodule
| 7.233807 |
module Top_GLB #(
parameter FIFO_DATA_WIDTH = 8,
parameter PE_SIZE = 16,
parameter integer MEM0_DEPTH = 896,
parameter integer MEM1_DEPTH = 896,
parameter integer MEM0_ADDR_WIDTH = 7,
parameter integer MEM1_ADDR_WIDTH = 7,
parameter integer MEM0_DATA_WIDTH = 128,
parameter integer MEM1_DATA_WIDTH = 128,
parameter integer WEIGHT_ROW_NUM = 70, // 64 + 6
parameter integer WEIGHT_COL_NUM = 294 // 288 + 6
) (
input clk,
input rst_n,
input en,
output wire mem0_ce0,
output wire mem0_we0,
output wire [MEM0_ADDR_WIDTH-1:0] mem0_addr0,
input wire [MEM0_DATA_WIDTH-1:0] mem0_q0_i,
output wire mem1_ce0,
output wire mem1_we0,
output wire [MEM1_ADDR_WIDTH-1:0] mem1_addr0,
input wire [MEM1_DATA_WIDTH-1:0] mem1_q0_i,
output wire [MEM0_DATA_WIDTH-1:0] mem0_q0_o,
output wire mem0_q0_vaild,
output [MEM1_DATA_WIDTH-1:0] rdata_o,
output [PE_SIZE-1:0] weight_en_col_o,
output wire sa_data_mover_en
);
wire wren_o;
// wire mem1_ce0;
// wire mem1_we0;
// wire mem0_ce0;
// wire mem0_we0;
// wire [MEM0_ADDR_WIDTH-1:0] mem0_addr0;
// wire [MEM1_ADDR_WIDTH-1:0] mem1_addr0;
// wire [MEM0_DATA_WIDTH-1:0] mem0_q0_i;
// wire [MEM1_DATA_WIDTH-1:0] mem1_q0_i;
wire [MEM1_DATA_WIDTH-1:0] mem1_q0_o;
wire rden_o;
Conv_Data_mover_v2 #(
.MEM0_DEPTH(MEM0_DEPTH),
.MEM1_DEPTH(MEM1_DEPTH),
.MEM0_ADDR_WIDTH(MEM0_ADDR_WIDTH),
.MEM1_ADDR_WIDTH(MEM1_ADDR_WIDTH),
.MEM0_DATA_WIDTH(MEM0_DATA_WIDTH),
.MEM1_DATA_WIDTH(MEM1_DATA_WIDTH),
.PE_SIZE(PE_SIZE),
.WEIGHT_ROW_NUM(WEIGHT_ROW_NUM), // 64 + 6
.WEIGHT_COL_NUM(WEIGHT_COL_NUM) // 288 + 6
) Conv_data_mover (
.clk(clk),
.rst_n(rst_n),
.en(en),
.mem0_q0_i (mem0_q0_i),
.mem0_addr0(mem0_addr0),
.mem0_ce0 (mem0_ce0),
.mem0_we0 (mem0_we0),
.mem1_q0_i(mem1_q0_i),
.mem1_addr0(mem1_addr0),
.mem1_ce0(mem1_ce0),
.mem1_we0(mem1_we0),
.mem0_q0_o(mem0_q0_o),
.mem1_q0_o(mem1_q0_o),
.wren_o(wren_o),
.mem0_q0_vaild(mem0_q0_vaild),
.rden_o(rden_o),
.sa_data_mover_en(sa_data_mover_en)
);
GLB #(
.FIFO_DATA_WIDTH(FIFO_DATA_WIDTH),
.PE_SIZE(PE_SIZE)
) GLB (
.clk(clk),
.rst_n(rst_n),
.wren_i(wren_o),
.rden_i(rden_o),
.full_o (),
.empty_o(),
.wdata_i(mem1_q0_o),
.rdata_o(rdata_o),
.weight_en_col_o(weight_en_col_o)
);
endmodule
| 7.492739 |
module is to test a RPi driving
* input and displaying those input on
* LEDs.
*
* Author : Brandon Bloodget
*
*****************************
*/
// Force error when implicit net has no type.
`default_nettype none
module top_gpio_out
(
input wire clk_100mhz,
input wire reset_n,
// rpi parallel bus
input wire bus_clk,
inout wire [7:0] bus_data,
input wire bus_rnw, // rpi/master perspective
output wire [3:0] led_out,
output wire led0_r, // indicates reset pressed
output wire led0_g, // indicates match
output wire led1_r // indicates not match
);
assign led_out[3:0] = bus_data[3:0];
assign led0_r = ~reset_n;
assign led0_g = 0;
assign led1_r = 0;
endmodule
| 6.512913 |
module gp_dff (
input d,
input clk,
clr,
output reg q
);
wire nq;
GP_DFF u_gp_dffr (
d,
clk,
nq
);
GP_INV u_gp_inv (
nq,
q
);
endmodule
| 6.624889 |
module gp_dffr (
input d,
input clk,
clr,
output reg q
);
wire nq;
GP_DFFR u_gp_dffr (
d,
clk,
clr,
nq
);
GP_INV u_gp_inv (
nq,
q
);
endmodule
| 6.809361 |
module gp_latchs (
input d,
input clk,
clr,
output reg q
);
wire nq;
GP_DLATCHS u_gp_dffs (
d,
clk,
clr,
nq
);
GP_INV u_gp_inv (
nq,
q
);
endmodule
| 6.847366 |
module top_greedy_snake (
input clk,
input rst,
input left,
input right,
input up,
input down,
input [14:0] sw,
output [15:0] led,
output hsync,
output vsync,
output [11:0] color_out,
output [7:0] seg_out,
output [3:0] sel
);
wire left_key_press;
wire right_key_press;
wire up_key_press;
wire down_key_press;
wire [1:0] snake;
wire [9:0] x_pos;
wire [9:0] y_pos;
wire [5:0] apple_x;
wire [4:0] apple_y;
wire [5:0] head_x;
wire [5:0] head_y;
wire add_cube;
wire [1:0] game_status;
wire hit_wall;
wire hit_body;
wire die_flash;
wire restart;
wire [6:0] cube_num;
wire reward_protected;
wire reward_slowly;
wire reward_grade;
wire speedRecover;
wire rst_n;
assign rst_n = ~rst;
wire clk_4Hz;
wire [11:0] VGA_reward;
clock u_clock (
.clk(clk),
.clk_4Hz(clk_4Hz),
.clk_8Hz(),
.clk_2Hz()
);
game_status_control u_game_status_control (
.clk(clk),
.rst(rst_n),
.key1_press(left_key_press),
.key2_press(right_key_press),
.key3_press(up_key_press),
.key4_press(down_key_press),
.game_status(game_status),
.hit_wall(hit_wall),
.hit_body(hit_body),
.die_flash(die_flash),
.restart(restart)
);
apple_generator u_apple_generator (
.clk(clk),
.rst(rst_n),
.apple_x(apple_x),
.apple_y(apple_y),
.head_x(head_x),
.head_y(head_y),
.add_cube(add_cube)
);
snake_moving u_snake_moving (
.clk(clk),
.rst(rst_n),
.left_press(left_key_press),
.right_press(right_key_press),
.up_press(up_key_press),
.down_press(down_key_press),
.snake(snake),
.x_pos(x_pos),
.reward_protected(reward_protected),
.reward_slowly(reward_slowly),
.y_pos(y_pos),
.head_x(head_x),
.head_y(head_y),
.add_cube(add_cube),
.game_status(game_status),
.speedRecover(speedRecover),
.cube_num(cube_num),
.hit_body(hit_body),
.hit_wall(hit_wall),
.die_flash(die_flash)
);
vga_control u_vga_control (
.clk(clk),
.rst(rst),
.hsync(hsync),
.vsync(vsync),
.snake(snake),
.color_out(color_out),
.game_status(game_status),
.x_pos(x_pos),
.y_pos(y_pos),
.apple_x(apple_x),
.apple_y(apple_y),
.VGA_reward(VGA_reward)
);
buttons u_buttons (
.clk(clk),
.rst(rst_n),
.left(left),
.right(right),
.up(up),
.down(down),
.left_key_press(left_key_press),
.right_key_press(right_key_press),
.up_key_press(up_key_press),
.down_key_press(down_key_press)
);
seg_display u_seg_display (
.clk(clk),
.rst(rst_n),
.add_cube(add_cube),
.game_status(game_status),
.reward_grade(reward_grade),
.seg_out(seg_out),
.sel(sel)
);
reward_logic u_reward_logic (
.clk (clk),
.clk_4Hz (clk_4Hz),
.game_status (game_status),
.head_x (head_x),
.head_y (head_y),
.sw (sw),
.VGA_xpos ({1'b0, x_pos}),
.VGA_ypos ({1'b0, y_pos}),
.speedRecover (speedRecover),
.reward_protected(reward_protected),
.reward_grade (reward_grade),
.reward_slowly (reward_slowly),
.VGA_data_reward (VGA_reward)
);
endmodule
| 7.712426 |
module top_gy_26 (
input flag_gy26,
input clk,
input rst,
input data_rx,
output RX232,
output [9:0] jiaodu
);
Top_uart_tx_gy_26 a (
.flag_gy26(flag_gy26),
.clk(clk),
.rst(rst),
.RX232(RX232),
.over_all(over_all),
.over_rx(over_rx)
);
top_uart_rx_gy_26 b (
.clk(clk),
.rst(rst),
.data_rx(data_rx),
.jiaodu(jiaodu)
);
endmodule
| 6.544141 |
module top_HW3_test;
reg [3:0] A;
reg [3:0] B;
reg Scan_CLK;
reg [7:0] BCI;
reg CLK;
wire [2:1] COM;
wire [6:0] SEG;
top_HW3 DUT (
.A(A),
.B(B),
.Scan_CLK(Scan_CLK),
.BCI(BCI),
.CLK(CLK),
.COM(COM),
.SEG(SEG)
);
initial begin
A = 0;
B = 0;
Scan_CLK = 0;
BCI = 0;
CLK = 0;
end
always #500000 Scan_CLK = ~Scan_CLK;
always #500 CLK = ~CLK;
initial begin
A = 5;
B = 3;
BCI = 2;
#2500000;
A = 2;
B = 8;
BCI = 240;
#2500000;
A = 4;
B = 7;
BCI = 145;
$stop;
end
endmodule
| 6.609323 |
module top_hash_table_URAM (
input clk,
input reset,
input [31:0] key_in,
input [7:0] en_in,
output [64-1:0] rd_xor_result
);
parameter NUM_MUL = 1;
parameter NUM_RD = 16;
parameter NUM_WR = 8;
parameter VALUE_WIDTH = 31;
parameter KEY_WIDTH = 32;
parameter INDEX_WIDTH = 15;
parameter DATA_WIDTH = 64;
reg [NUM_RD*32-1:0] key;
reg [NUM_WR*31-1:0] value;
reg [2*NUM_WR-1:0] opt;
reg [NUM_WR-1:0] en;
reg [10:0] count;
wire [NUM_RD*64-1:0] rd_out_all_update_reg;
hash_table_16_URAM #(NUM_MUL, NUM_RD, NUM_WR, VALUE_WIDTH, KEY_WIDTH, INDEX_WIDTH, DATA_WIDTH) hash_table_16_my (
clk,
reset,
key,
value,
opt,
en,
rd_out_all_update_reg
);
xor_all_URAM #(NUM_RD, DATA_WIDTH) xor_all_u0 (
rd_out_all_update_reg,
rd_xor_result
);
/*
genvar j;
generate
for(j = 0; j < NUM_RD; j = j+1) begin
assign rd_out[j] = rd_out_all_update_reg[j*64+j+32];
end
endgenerate */
integer i;
always @(posedge clk) begin
if (reset) begin
count <= 0;
end else begin
key[count[0]*32+:32] <= key_in;
value[count[2]*31+:31] <= key_in[30:0];
en <= en_in;
for (i = 0; i < NUM_RD; i = i + 1) begin
key[i*32+19] <= en_in[i];
end
for (i = 0; i < NUM_WR; i = i + 1) begin
opt[i*2+:2] <= key_in[i*2+:2];
end
end
end
endmodule
| 6.780764 |
module (Everything that will be synthesized)
//
// Author: Manoja & Yash
// Date: 14th March 2018
//
// Description:
// ------------
// Encapsulates the interface and the design, by instantiating them here. And so port connections are made here
//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module top_hdl; //pragma attribute top_hdl parition_module_xrtl
logic clk;
//Intantiate Interface+BFM
ibuffer ib(clk);
//Intantiate DUT
buffer DUT(ib);
// Free running clock
// tbx clkgen
initial
begin
clk = 0;
forever begin
#10 clk = ~clk;
end
end
endmodule
| 6.755072 |
module top_hex_demo (
input wire clk_25mhz,
input wire [6:0] btn,
output wire [7:0] led,
output wire oled_csn,
output wire oled_clk,
output wire oled_mosi,
output wire oled_dc,
output wire oled_resn
);
parameter C_color_bits = 16;
assign led = 0;
reg [127:0] R_display; // something to display
always @(posedge clk_25mhz) begin
R_display[0] <= btn[0];
R_display[4] <= btn[1];
R_display[8] <= btn[2];
R_display[12] <= btn[3];
R_display[16] <= btn[4];
R_display[20] <= btn[5];
R_display[24] <= btn[6];
R_display[127:64] <= R_display[127:64] + 1; // shown in next OLED row
end
wire [6:0] x;
wire [7:0] y;
wire next_pixel;
wire [C_color_bits-1:0] color;
hex_decoder #(
.C_data_len (128),
.C_font_file ("oled_font.mem"),
.C_color_bits(C_color_bits)
) hex_decoder_inst (
.clk(clk_25mhz),
.en(1'b1),
.data(R_display),
.x(x),
.y(y),
.next_pixel(next_pixel),
.color(color)
);
localparam C_init_file = "st7789_init.mem";
oled_video #(
.C_init_file(C_init_file),
.C_init_size(36)
) oled_video_inst (
.clk(clk_25mhz),
.x(x),
.y(y),
.next_pixel(next_pixel),
.color(color),
.oled_csn(oled_csn),
.oled_clk(oled_clk),
.oled_mosi(oled_mosi),
.oled_dc(oled_dc),
.oled_resn(oled_resn)
);
endmodule
| 6.849367 |
module top (
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o_mid, o_rtl;
always @(posedge cin) A <= o_mid;
middle u_mid (
.x(x),
.y(o_rtl),
.o(o_mid)
);
u_rtl inst_u_rtl (
.x(o_mid),
.y(y),
.o(o_rtl)
);
endmodule
| 7.233807 |
module middle (
input x,
input y,
output o
);
wire o1, o2;
assign o1 = x & o2;
assign o2 = y & o1;
assign o = o1;
endmodule
| 6.553865 |
module u_rtl (
input x,
input y,
output o
);
wire o1, o2;
assign o1 = x & o2;
assign o2 = y & o1;
assign o = o1;
endmodule
| 6.750051 |
module top_hourseg (
rst,
inclk,
seg1,
seg10
);
input rst, inclk;
output wire [6:0] seg1, seg10;
wire [5:0] sec_val;
hour_cnt counter (
rst,
inclk,
sec_val
);
hour_conv converter (
rst,
sec_val,
seg1,
seg10
);
endmodule
| 7.343025 |
module top_HW3 (
input [3:0] A,
B,
input Scan_CLK,
output [2:1] COM,
output [6:0] SEG,
input [7:0] BCI,
input CLK
);
wire [2:1] COM_w;
wire ENA;
MUX_DISP MD1 (
.A(A),
.B(B),
.clk(Scan_CLK),
.com_1(COM_w[1]),
.com_2(COM_w[2]),
.seg_A(SEG[0]),
.seg_B(SEG[1]),
.seg_C(SEG[2]),
.seg_D(SEG[3]),
.seg_E(SEG[4]),
.seg_F(SEG[5]),
.seg_G(SEG[6])
);
PWM PW1 (
.CLK(CLK),
.BCI(BCI),
.OUT(ENA)
);
assign COM = ENA ? COM_w : 2'b11;
endmodule
| 7.525633 |
module that will instantiate and connect our DUT (lcd_controller) the ICON, VIO , ILA cores
For more information refer to this tutorial (Search in docs if link is broken)
http://www.stanford.edu/~phartke/chipscope_tutorial.pdf
http://www.stanford.edu/class/ee183/handouts.shtml
*/
module top_hw_testbench(
input clk,
output hw_lcd_e,
output hw_lcd_rs,
output hw_lcd_rw,
output [3:0] hw_lcd_nibble,
output hw_strata_flash_disable
);
// Declare some wires to connect the components
wire rst;
wire rs_in,strobe_in;
wire[7:0] data_in, period_clk_ns;
wire [3:0] lcd_nibble;
wire lcd_e,lcd_rs,lcd_rw,disable_flash,done;
// Declare the ICON wires
wire [35: 0] control0;
wire [35: 0] control1;
// Declare VIO wires
wire [18: 0] async_out;
// Declare ILA wires
wire trig_0;
wire [16:0] data;
// Declare clock DCM multiplier (3)
wire clock3x, clock1x, clockbuf;
// Instantiate our Device under test
lcd_controller DUT (
rst,
clock1x,
rs_in,
data_in,
strobe_in,
period_clk_ns,
lcd_e,
lcd_nibble,
lcd_rs,
lcd_rw,
disable_flash,
done
);
// Instantiate the module of clock multiplier
corePLL instance_name (
.CLKIN_IN(clk),
.CLKFX_OUT(clock3x),
.CLKIN_IBUFG_OUT(clockbuf),
.CLK0_OUT(clock1x)
);
coreICON integratedController (
.CONTROL0(control0), // INOUT BUS [35:0]
.CONTROL1(control1)
); // INOUT BUS [35:0]
coreILA integratedLogicAnalyser (
.CONTROL(control0), // INOUT BUS [35:0]
.CLK(clock3x), // IN
.DATA(data), // DATA [16:0];
.TRIG0(trig_0)
); // IN BUS [0:0]
coreVIO VIO_inst
(
.CONTROL(control1), // INOUT BUS [35:0]
.CLK(clock1x),// clock1x clock3x
.SYNC_OUT(async_out) // The clock must be inverted on the core to garantee a good sample point.
//.ASYNC_OUT(async_out)
); // IN BUS [18:0]
assign trig_0 = lcd_e;
assign {rst, rs_in, data_in, strobe_in, period_clk_ns} = async_out;
assign data = {7'd1,lcd_e, lcd_nibble[3:0], lcd_rs, lcd_rw, disable_flash, done, strobe_in};
// Send all interest output to outside
assign hw_lcd_e = lcd_e;
assign hw_lcd_rs = lcd_rs;
assign hw_lcd_rw = lcd_rw;
assign hw_lcd_nibble = lcd_nibble;
assign hw_strata_flash_disable = disable_flash;
endmodule
| 7.707616 |
module top_hx8k (
clk_in,
reset_n_in,
// Global data
sck0_in,
sdi0_in,
cs0_n_in,
// Daisy data
sck1_in,
sdi1_in,
sdo1_out,
cs1_n_in,
// READY flags
ready_n_od_out,
// Indicator LED
status_led_n_out
);
localparam POOL_SIZE = 2;
localparam POOL_SIZE_LOG2 = 1;
localparam BASE_TARGET = `TARGET;
// 12 MHz ~ 30 MHz
localparam PLL_DIVR = 4'b0000;
localparam PLL_DIVF = 7'b1001111;
localparam PLL_DIVQ = 3'b101;
// Multiply input clock signal using SB_PLL40_CORE
wire g_clk;
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(PLL_DIVR),
.DIVF(PLL_DIVF),
.DIVQ(PLL_DIVQ),
.FILTER_RANGE(3'b001)
) pll (
.LOCK(),
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clk_in),
//.PLLOUTCORE(g_clk)
.PLLOUTGLOBAL(g_clk)
);
// Inputs and Outputs
input wire clk_in;
input wire reset_n_in;
input wire sck0_in;
input wire sdi0_in;
input wire cs0_n_in;
input wire sck1_in;
input wire sdi1_in;
output wire sdo1_out;
input wire cs1_n_in;
output wire ready_n_od_out;
output wire status_led_n_out;
top #(
.POOL_SIZE(POOL_SIZE),
.POOL_SIZE_LOG2(POOL_SIZE_LOG2),
.BASE_TARGET(BASE_TARGET)
) u (
g_clk,
reset_n_in,
// Global data
sck0_in,
sdi0_in,
cs0_n_in,
// Daisy data
sck1_in,
sdi1_in,
sdo1_out,
cs1_n_in,
// Success flags
ready_n_od_out,
// Indicators
status_led_n_out
);
endmodule
| 6.779626 |
module top (
input [8:0] a,
input [8:0] b,
output [8:0] o1,
output [2:0] o2,
input [2:0] c,
input [2:0] d,
output [2:0] o3,
output [2:0] o4,
input s
);
assign o1 = (s ? 0 : a + b);
assign o2 = (s ? a : a - b);
assign o3 = (s ? 4'b1111 : d + c);
assign o4 = (s ? d : c - d);
endmodule
| 7.233807 |
module top_icecream_v1 (
input clk,
output [2:0] led_n
);
`include "macros/direction.vh"
reg [2:0] int_rst_cnt = 0;
wire pll_locked;
wire new_clk;
always @(posedge new_clk) begin
if (int_rst_cnt != 3'b111 && pll_locked) int_rst_cnt <= int_rst_cnt + 1;
end
wire int_rst_n = int_rst_cnt == 3'b111;
wire rst_n = int_rst_n;
reg [2:0] led;
wire i_req;
wire [15:0] i_addr;
wire i_ack;
wire [7:0] i_rdata;
wire d_req;
wire d_dir;
wire [7:0] d_addr;
wire [7:0] d_wdata;
wire d_ack;
wire [7:0] d_rdata;
wire io_req;
wire io_dir;
wire [7:0] io_wdata;
reg io_ack;
reg [7:0] io_rdata;
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0100), // DIVR = 4
.DIVF(7'b0111111), // DIVF = 63
.DIVQ(3'b101), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1)
) pll (
.LOCK(pll_locked),
.RESETB(1'b1),
.BYPASS(1'b0),
.REFERENCECLK(clk),
.PLLOUTCORE(new_clk)
);
bfcpu cpu (
.clk (new_clk),
.rst_n(rst_n),
.i_req (i_req),
.i_addr (i_addr),
.i_ack (i_ack),
.i_rdata(i_rdata),
.d_req (d_req),
.d_dir (d_dir),
.d_addr (d_addr),
.d_wdata(d_wdata),
.d_ack (d_ack),
.d_rdata(d_rdata),
.io_req (io_req),
.io_dir (io_dir),
.io_wdata(io_wdata),
.io_ack (io_ack),
.io_rdata(io_rdata)
);
i_mem_icecream_v1 im (
.clk(new_clk),
.i_req (i_req),
.i_addr (i_addr),
.i_ack (i_ack),
.i_rdata(i_rdata)
);
d_mem_icecream_v1 dm (
.clk(new_clk),
.d_req (d_req),
.d_dir (d_dir),
.d_addr (d_addr),
.d_wdata(d_wdata),
.d_ack (d_ack),
.d_rdata(d_rdata)
);
always @(posedge new_clk) begin
if (!rst_n) begin
led <= 3'b000;
io_ack <= 0;
end else begin
if (io_req) begin
io_ack <= 1;
if (io_dir == `DIRECTION_WRITE) led <= io_wdata[2:0];
else io_rdata <= {5'b0, led};
end else begin
io_ack <= 0;
end
end
end
SB_RGBA_DRV #(
.RGB0_CURRENT("0b000001"),
.RGB1_CURRENT("0b000001"),
.RGB2_CURRENT("0b000001")
) rgb_driver (
.RGBLEDEN(1),
.CURREN(1),
.RGB0PWM(led[0]),
.RGB1PWM(led[1]),
.RGB2PWM(led[2]),
.RGB0(led_n[0]),
.RGB1(led_n[1]),
.RGB2(led_n[2])
);
endmodule
| 6.740302 |
module top (
input en,
input a,
output b
);
tribuf u_tri (
.en(en),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'II1_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/II1_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data_a );
$dumpvars( 0, dut0.din_data_b );
$dumpvars( 0, dut0.din_data_c );
$dumpvars( 0, dut0.din_data_d );
$dumpvars( 0, dut0.din_data_e );
$dumpvars( 0, dut0.din_data_f );
$dumpvars( 0, dut0.din_data_g );
$dumpvars( 0, dut0.din_data_h );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/II1_V/sim_II1_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'II2_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/II2_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data_a );
$dumpvars( 0, dut0.din_data_b );
$dumpvars( 0, dut0.din_data_c );
$dumpvars( 0, dut0.din_data_d );
$dumpvars( 0, dut0.din_data_e );
$dumpvars( 0, dut0.din_data_f );
$dumpvars( 0, dut0.din_data_g );
$dumpvars( 0, dut0.din_data_h );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/II2_V/sim_II2_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'II3_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/II3_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data_a );
$dumpvars( 0, dut0.din_data_b );
$dumpvars( 0, dut0.din_data_c );
$dumpvars( 0, dut0.din_data_d );
$dumpvars( 0, dut0.din_data_e );
$dumpvars( 0, dut0.din_data_f );
$dumpvars( 0, dut0.din_data_g );
$dumpvars( 0, dut0.din_data_h );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/II3_V/sim_II3_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module top_iic (
input sys_clk,
input sys_rst_n,
output scl,
inout sda
);
parameter SLAVE_ADDRESS = 7'b1010_000; // the address of slave
parameter SYSTEM_CLK = 26'd50_000_000; // system clock
parameter IIC_CLK = 26'd250_000; // IIC clock
parameter DIV_FREQ_FACTOR = SYSTEM_CLK / IIC_CLK / 2; // the factor of dividing system clock
parameter ADDR_WIDTH = 1'b1; //1: 16bit address ; 0:8 bit address
wire start;
wire ctrl_w0_r1;
wire [15:0] addr;
wire [ 7:0] data_write;
wire flag_done;
wire [ 7:0] data_read;
e2prom_ctrl inst_e2prom_ctrl (
.sys_clk (sys_clk),
.sys_rst_n(sys_rst_n),
.flag_done(flag_done),
.data_read(data_read),
.start (start),
.ctrl_w0_r1(ctrl_w0_r1),
.addr (addr),
.data_write(data_write)
);
i2c_drive #(
.SLAVE_ADDRESS (SLAVE_ADDRESS),
.SYSTEM_CLK (SYSTEM_CLK),
.IIC_CLK (IIC_CLK),
.DIV_FREQ_FACTOR(DIV_FREQ_FACTOR),
.ADDR_WIDTH (ADDR_WIDTH)
) inst_i2c_drive (
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.start (start),
.ctrl_w0_r1(ctrl_w0_r1),
.addr (addr),
.data_write(data_write),
.scl (scl),
.sda (sda),
.flag_done(flag_done),
.data_read(data_read)
);
endmodule
| 7.648227 |
module top_impl (
input wire btn,
input wire gclk,
input wire rst,
input wire [7:0] led_sel,
output wire [11:0] led
);
wire clk;
dejitter dejitter (
.clk(gclk),
.btn(btn),
.btn_out(clk)
);
top top (
.clk(clk),
.gclk(gclk),
.rst(rst),
.led_sel(led_sel),
.led(led)
);
endmodule
| 7.77974 |
module top_infrared_rcv (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号，低电平有效
input wire infrared_in, //红外接收信号
output wire stcp, //输出数据存储寄时钟
output wire shcp, //移位寄存器的时钟输入
output wire ds, //串行数据输入
output wire oe, //输出使能信号
output wire led //led灯控制信号
);
//********************************************************************//
//******************** Parameter And Internal Signal *****************//
//********************************************************************//
//wire define
wire repeat_en; //重复码使能信号
wire [19:0] data; //接收的控制码
//********************************************************************//
//**************************** Main Code *****************************//
//********************************************************************//
//-------------infrared_rcv_inst--------------
infrared_rcv infrared_rcv_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n (sys_rst_n), //复位信号，低有效
.infrared_in(infrared_in), //红外接受信号
.repeat_en(repeat_en), //重复码使能信号
.data (data) //接收的控制码
);
//-------------led_ctrl_inst--------------
led_ctrl led_ctrl_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号，低有效
.repeat_en(repeat_en), //重复码使能信号
.led(led)
);
//-------------seg_595_dynamic_inst--------------
seg_595_dynamic seg_595_dynamic_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号，低有效
.data (data), //数码管要显示的值
.point (6'd0), //小数点显示,高电平有效
.seg_en (1'b1), //数码管使能信号，高电平有效
.sign (1'b0), //符号位，高电平显示负号
.stcp(stcp), //输出数据存储寄时钟
.shcp(shcp), //移位寄存器的时钟输入
.ds (ds), //串行数据输入
.oe (oe) //输出使能信号
);
endmodule
| 6.548302 |
module top (
input x,
input y,
input cin,
output reg A,
output reg cout,
output reg B,
C
);
reg ASSERT = 1;
initial begin
begin
A = 0;
cout = 0;
end
end
assign A = y + cin;
assign cout = y + A;
always @* assert (ASSERT);
assign {B, C} = {cout, A} <<< 1;
endmodule
| 7.233807 |
module gpio (
input clk,
input wire out_en,
input wire in_sig,
output wire out_sig
);
localparam INPUT = 0;
localparam OUTPUT = 1;
always @(posedge clk) begin
if (out_en == 0) begin
out_sig <= in_sig;
end
end
endmodule
| 7.858288 |
module top_inout
(
input wire CLK_16MHZ,
input wire PIN_1, // out_en
input wire PIN_2, // in_sig
inout wire PIN_3, // bi-directional pin
output reg PIN_4, // out_sig
);
localparam INPUT = 0;
localparam OUTPUT = 1;
wire out_en = PIN_1;
wire in_sig;
reg out_sig;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) io_block_instance (
.PACKAGE_PIN(PIN_3),
.OUTPUT_ENABLE(out_en),
.D_OUT_0(out_sig),
.D_IN_0(in_sig)
);
gpio gpio_inst
(
.clk(CLK_16MHZ),
.out_en(out_en),
.in_sig(in_sig),
.out_sig(out_sig)
);
endmodule
| 8.090067 |
module top (
input [7:0] data_a,
data_b,
input [6:1] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clka,
clkb,
inout reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[0:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @(posedge clka) begin
if (we_a) begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b) begin
q_a <= ram[addr_a];
end
end
// Port B
always @(posedge clkb) begin
if (we_b) begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b) begin
q_b <= ram[addr_b];
end
end
endmodule
| 7.233807 |
module mux2 (
S,
A,
B,
Y
);
input S;
input A, B;
output reg Y;
always @(*) Y = (S) ? B : A;
endmodule
| 7.562788 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
assign {cout, A} = ~(cin + y + x);
endmodule
| 7.233807 |
module adff (
input [3:0] d,
input clk,
clr,
output reg [3:0] q
);
initial begin
q = 4'b0000;
end
always @(posedge clk, posedge clr)
if (clr) q <= 4'b0110;
else q <= d;
endmodule
| 7.089232 |
module top (
input clk,
input clr,
input pre,
input [3:0] a,
output [3:0] b
);
adff u_adff (
.clk(~clk),
.clr(~clr),
.d (~a),
.q (b)
);
endmodule
| 7.233807 |
module top (
input rx,
output tx,
output sync
);
wire clk;
SB_HFOSC #(
.CLKHF_DIV("0b10")
) u_SB_HFOSC (
.CLKHFPU(1),
.CLKHFEN(1),
.CLKHF (clk)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
isbc8010 machine (
.clk(clk),
.reset(~resetn),
.rx(rx),
.tx(tx),
.sync(sync)
);
endmodule
| 7.233807 |
module top_jacobi (
input clk,
input rst_n,
output wire [31:0] quotient_out
);
wire start_r;
wire [31:0] divisor_r;
wire [31:0] dividend_r;
wire [31:0] quotient_out_o;
wire complete_o;
assign quotient_out = quotient_out_o;
jacobi j1 (
.clk(clk),
.rst_n(rst_n),
.start_r(start_r),
.divisor_r(divisor_r),
.dividend_r(dividend_r),
.quotient_out_o(quotient_out_o),
.complete_o(complete_o)
);
Fixed_Point_Divider_Top int8_16 (
.dividend(dividend_r), //input [23:0] dividend
.divisor(divisor_r), //input [23:0] divisor
.start(start_r), //input start
.clk(clk), //input clk
.quotient_out(quotient_out_o), //output [23:0] quotient_out
.complete(complete_o) //output complete
);
endmodule
| 7.530116 |
module top_jump;
reg [31:0] inst = 32'b0000000001000000000000111101111;
reg clk, reset;
top U_TOP (
clk,
reset,
inst
);
initial begin
clk = 0;
reset = 0;
$dumpfile("top_jump.vcd");
$dumpvars(0, top_jump);
end
always #5 clk = !clk;
initial begin
reset = 1;
#5 reset = 0;
inst = 32'b0000001101000000000000111101111;
#25 inst = 32'b0000000001000000000000100010011;
#25 inst = 32'b0000000001000000000000110010011;
#90 $finish;
end
endmodule
| 6.687464 |
module top_key (
clk_50Mhz,
kin,
kclk,
keyout,
idle
);
input clk_50Mhz, kclk, kin;
output wire [7:0] keyout;
output wire idle;
ps2key keyboard0 (
.clk50(clk_50Mhz),
.kin (kin),
.kclk (kclk),
.code (keyout),
.idle (idle)
);
endmodule
| 7.372615 |
module top_keyexp (
//input
input wire clk,
input wire rst_n,
input wire [127:0] key_in,
input wire start_in,
input wire en_de,
input wire [3:0] round_in,
//output
output wire [127:0] key_out,
output wire ready_out
);
//internal wires
wire [7:0] sbox_in;
wire [7:0] sbox_out;
wire ce, re;
keyexp aes_keyexp (
.clk (clk),
.rst_n (rst_n),
.key_in (key_in),
.sbox_out (sbox_out),
.round_in (round_in),
.key_out (key_out),
.sbox_in (sbox_in),
.sbox_en_de_in(),
.ce (ce),
.re (re),
.ready_out (ready_out),
.start_in (start_in),
.en_de (en_de)
);
sbox_rom aes_sbox2 (
.clk (clk),
.addr (sbox_in),
.chip_en (ce),
.read_en (re),
.data (sbox_out)
);
endmodule
| 8.606554 |
module top_key_demo (
input CLK100MHZ,
input PS2_CLK,
input PS2_DATA,
// output [6:0]SEG,
// output [7:0]AN,
// output DP,
output UART_TXD,
output [7:0] short_code,
input reset
);
reg CLK50MHZ = 0;
wire [31:0] keycode;
always @(posedge (CLK100MHZ)) begin
CLK50MHZ <= ~CLK50MHZ;
end
PS2Receiver keyboard (
.clk(CLK50MHZ),
.kclk(PS2_CLK),
.kdata(PS2_DATA),
.keycodeout(keycode[31:0]),
.reset(reset)
);
// wire [7:0] short_code;
assign short_code = keycode[7:0];
/*
always @(posedge CLK100MHZ) begin
if (~reset) begin
short_code = 8'd0;
end else begin
short_code = keycode[7:0];
end
end */
/*
seg7decimal sevenSeg (
.x(keycode[31:0]),
.clk(CLK100MHZ),
.seg(SEG[6:0]),
.an(AN[7:0]),
.dp(DP)
);
*/
endmodule
| 6.855509 |
module latsr (
input d,
clk,
pre,
clr,
output reg q
);
always @(*)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.011 |
module top (
input clk,
input a,
output b
);
latsr u_latsr (
.clk(clk),
.clr(1'b1),
.pre(1'b1),
.d (a),
.q (b)
);
endmodule
| 7.233807 |
module alatn (
input d,
en,
clr,
output reg q
);
initial begin
q = 0;
end
always @(*)
if (!clr) q <= 1'b0;
else if (!en) q <= d;
endmodule
| 7.499248 |
module latsr (
input d,
en,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(*)
if (clr) q <= 1'b0;
else if (pre) q <= 1'b1;
else if (en) q <= d;
endmodule
| 7.011 |
module nlatsr (
input d,
en,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(*)
if (!clr) q <= 1'b0;
else if (!pre) q <= 1'b1;
else if (!en) q <= d;
endmodule
| 7.387062 |
module top (
input en,
input clr,
input pre,
input a,
output b,
b1,
b2,
b3
);
latsr u_latsr (
.en (en),
.clr(clr),
.pre(pre),
.d (a),
.q (b)
);
nlatsr u_nlatsr (
.en (en),
.clr(clr),
.pre(pre),
.d (a),
.q (b1)
);
alat u_alat (
.en (en),
.clr(clr),
.d (a),
.q (b2)
);
alatn u_alatn (
.en (en),
.clr(clr),
.d (a),
.q (b3)
);
endmodule
| 7.233807 |
module top_layer (
clk,
start,
dram_in,
iram_in_ext,
data_out,
addr_ext,
mem_write_data_ext,
mem_write_ins,
read_en_ext,
data_in_ext,
iram_in,
addr_ins,
addr_out,
state,
control_out,
ir_out,
read_en,
data_out_proc,
pc_addr,
addr_out_proc,
bus_out
);
input start, mem_write_ins, clk; // start the process
input [1:0] read_en_ext;
input [15:0] iram_in_ext, addr_ext;
input [15:0] data_in_ext;
input mem_write_data_ext;
output wire [15:0] bus_out;
output reg [8:0] addr_ins;
output reg [15:0] data_out; // data memory write output (data_bus <= input :: memory <= output)
output reg [15:0] addr_out;
output wire [15:0] iram_in;
output wire [15:0] dram_in; // data memory read output (data_bus <= output :: memory <= input)
output wire [5:0] state;
output wire [15:0] ir_out;
output wire [15:0] data_out_proc, pc_addr;
output wire [22:0] control_out;
output reg [1:0] read_en;
reg mem_write_data_proc;
reg mem_write_data;
reg read_en_data, read_en_ir;
output wire [15:0] addr_out_proc;
// clock clock(clk); //clock module
Processor Processor (
clk,
dram_in,
data_out_proc,
iram_in,
state,
ir_out,
bus_out,
addr_out_proc,
control_out,
pc_addr
);
state_machine state_machine (
clk,
start,
ir_out,
state
);
always @(posedge clk) begin
read_en <= control_out[11:10];
mem_write_data_proc <= control_out[12];
//data memmory
if (mem_write_data_proc == 1 && mem_write_data_ext == 0) begin
mem_write_data = 1;
data_out <= bus_out;
addr_out <= addr_out_proc;
end
if (mem_write_data_proc == 0 && mem_write_data_ext == 1) begin
mem_write_data = 1;
data_out <= data_in_ext;
addr_out <= addr_ext;
end
if (mem_write_ins == 1) begin
addr_ins = addr_ext;
end
// !instruction memory
if (read_en_ext[0] == 0 && read_en[0] == 1) begin
read_en_ir = 1;
addr_ins = addr_out_proc;
end
if (read_en_ext[0] == 1 && read_en[0] == 0) begin
read_en_ir = 1;
addr_ins = addr_ext;
end
// !data memory
if (read_en_ext[1] == 1 && read_en[1] == 0) begin
read_en_data <= 1;
addr_out <= addr_ext;
end
if (read_en_ext[1] == 0 && read_en[1] == 1) begin
read_en_data <= 1;
addr_out <= addr_out_proc;
end
end
memory_ip memory_ip_data ( // instantiate data memory
.address(addr_out), // input [8:0] address_sig
.clock(clk), // input clock_sig
.data(data_out), // input [15:0] data_sig
.rden(read_en_data), // input rden_sig
.wren(mem_write_data), // input wren_sig
.q(dram_in) // output [15:0] q_sig
);
memory_ip memory_ip_inst ( // instantiate instruction memory
.address(addr_ins), // input [8:0] address_sig
.clock(clk), // input clock_sig
.data(iram_in_ext), // input [15:0] data_sig
.rden(read_en_ir), // input rden_sig
.wren(mem_write_ins), // input wren_sig
.q(iram_in) // output [15:0] q_sig
);
endmodule
| 6.56185 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
//Keep inverter off
LDCE_1 ff (
.G (clk),
.GE (ce),
.CLR(sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top (
input clk,
ce,
sr,
d,
output q
);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
//Keep inverter off
LDPE_1 ff (
.G (clk),
.GE (ce),
.PRE(sr),
.D (d),
.Q (q)
);
endmodule
| 7.233807 |
module top_LEDs (
input clock,
input reset,
input [3:0] hex0,
input [3:0] hex1,
input [3:0] hex2,
input [3:0] hex3,
output reg [3:0] enable,
output [7:0] dispcode, // ߶ܵ
output light
);
wire clk_sys;
wire [1:0] count;
wire [3:0] hex_num;
assign light = clk_sys;
clk_div clk_div (
.clk(clock),
.clk_sys(clk_sys)
);
Counter4 Counter4 (
.clk (clk_sys),
.reset(reset),
.count(count)
);
Hex_To_7Seg Hex_To_7Seg (
.hex(hex_num),
.dispcode(dispcode)
);
Mux4_4bits Mux4_4bits (
.choice(count),
.in0(hex0),
.in1(hex1),
.in2(hex2),
.in3(hex3),
.out(hex_num)
);
always @(count) begin
case (count)
2'b00: enable = 4'b1110;
2'b01: enable = 4'b1101;
2'b10: enable = 4'b1011;
2'b11: enable = 4'b0111;
endcase
end
endmodule
| 7.768587 |
module top_level ();
parameter cycle = 10;
reg hclk;
reg hresetn;
wire hready_out;
wire [1:0] hresp;
wire [31:0] hrdata;
wire hwrite, hready_in;
wire [1:0] htrans;
wire [31:0] haddr, hwdata;
wire pwrite, penable;
wire [2:0] psel;
wire [31:0] paddr, pwdata;
wire pwrite_out, penable_out;
wire [2:0] psel_out;
wire [31:0] paddr_out, pwdata_out, prdata;
ahb_master DUT1 (
.hclk(hclk),
.hresetn(hresetn),
.hrdata(hrdata),
.hresp(hresp),
.hready_out(hready_out),
.hwrite(hwrite),
.hready_in(hready_in),
.htrans(htrans),
.haddr(haddr),
.hwdata(hwdata)
);
bridge_top DUT2 (
.hclk(hclk),
.hresetn(hresetn),
.hwrite(hwrite),
.hready_in(hready_in),
.htrans(htrans),
.hwdata(hwdata),
.haddr(haddr),
.pwrite(pwrite),
.penable(penable),
.psel(psel),
.paddr(paddr),
.pwdata(pwdata),
.prdata(prdata),
.hrdata(hrdata),
.hresp(hresp),
.hready_out(hready_out)
);
apb_interface DUT3 (
.pwrite(pwrite),
.penable(penable),
.psel(psel),
.paddr(paddr),
.pwdata(pwdata),
.pwrite_out(pwrite_out),
.penable_out(penable_out),
.psel_out(psel_out),
.paddr_out(paddr_out),
.pwdata_out(pwdata_out),
.prdata(prdata)
);
initial begin
hclk = 0;
forever #(cycle / 2) hclk = ~hclk;
end
initial begin
hresetn = 1;
#cycle;
hresetn = 0;
end
endmodule
| 6.813051 |
module top_level (
CLOCK_50,
SW,
HEX0,
HEX1,
HEX2,
LEDR
); // Defines the top_level for the timer circuit
input wire CLOCK_50; // Declares input hardware 50MHz Clock
input wire [2:0] SW; //Declares 3 input switches
output [2:0] LEDR; //Declares 3 output LEDR wires
assign LEDR[2:0] = SW[2:0]; // Assigns the 3 LEDRS to the 3 switches
wire Reset; // Declares the Reset wire
wire Direction; // Declares the Direction wire
wire Hold; // Declares the Hold wire
assign Reset = SW[2]; //Assign Reset wire to switch 2
assign Direction = SW[1]; //Assign Direction wire switch 1
assign Hold = SW[0]; //Assign Hold wire to switch 0
output wire [6:0] HEX0; //defines output wires for HEX0 display.
output wire [6:0] HEX1; //defines output wires for HEX1 display.
output wire [6:0] HEX2; //defines output wires for HEX2 display.
wire c1, c2, c3, c4, c5, c6, c7; //Declare intermediate clock wires
wire [3:0] A0; //Declare 3 bit Data A0 wire
wire [3:0] A1; //Declare 3 bit Data A1 wire
wire [3:0] A2; //Declare 3 bit Data A2 wire
//Instantiate the divider modules and cascade outputs to get correct clock frequency
divide_by_5 inst0 (
CLOCK_50,
c1
); // Instantiate the divide_by_5 module, output 10MHz
divide_by_10 inst1 (
c1,
c2
); //Instantiate the divide_by_10 module #1 output 1MHz
divide_by_10 inst2 (
c2,
c3
); //Instantiate the divide_by_10 module #2 output 0.1MHZ
divide_by_10 inst3 (
c3,
c4
); //Instantiate the divide_by_10 module #3 output 0.01MHz
divide_by_10 inst4 (
c4,
c5
); //Instantiate the divide_by_10 module #4 output 1KHz
divide_by_10 inst5 (
c5,
c6
); //Instantiate the divide_by_10 module #5 output 0.1KHz
divide_by_10 inst6 (
c6,
c7
); //Instantiate the divide_by_10 module #6 output 0.1HZ
wire Overflow0, Overflow1, Overflow2; //Declare the Overflow wires to feed into succesive counter modules
decimal_counter inst9 (
A0,
Overflow0,
c7,
Reset,
Direction,
Hold
); //Instantiate the decimal_counter module
decimal_counter inst10 (
A1,
Overflow1,
Overflow0,
Reset,
Direction,
Hold
); //Instantiate the decimal_counter module
hex_counter inst11 (
A2,
Overflow2,
Overflow1,
Reset,
Direction,
Hold
); //Instantiate the hex_counter module
hex_7seg_bitwise inst12 (
A0,
HEX0
); //Instantiate the hex_7seg_bitwise for HEX display 0
hex_7seg_bitwise inst13 (
A1,
HEX1
); //Instantiate the hex_7seg_bitwise for HEX display 1
hex_7seg_bitwise inst14 (
A2,
HEX2
); //Instantiate the hex_7seg_bitwise for HEX display 2
endmodule
| 7.454809 |
module top_level_4_1 (
HEX0,
SW,
LEDR
); //declares module
input wire [5:0] SW; //data and selection input
output wire [5:0] LEDR; //outputs 6 wires for LEDR
output wire [6:0] HEX0; //outputs 7 wires for our HEX display
assign LEDR[5:0] = SW[5:0]; //assigns LEDRs to switches
wire m; //defines a wire m
wire [3:0] X; //defines 4 wires X
//assign {A, B, C, D} = {3’b000, m};
Four_to_1_1_bit_mux(
m, SW[3:0], SW[5:4]
); //calls 4 to 1, 1 bit multiplexer, takes in m, and multiple switches
assign X = {3'b000, m}; //concatenates the X wires
hex_7seg_bitwise(
X, HEX0
); //calls hex_7seg_bitwise
endmodule
| 8.979461 |
module top_level (
input CLK,
input [3:0] BUTTON,
output TX
);
wire rst;
wire clkin1, clk_100, clk_10;
wire [63:0] tx_reg;
wire tx_en, tx_dv;
wire [7:0] temp;
//Input Clk buffer
IBUF clkin1_buf (
.O(clkin1),
.I(CLK)
);
//Clk Divider - MMCM
CLK_DIV #(
.MULTI(6.0)
) clk_div (
.clkin1(clkin1),
.rst(rst),
.clk_out_10(clk_10)
);
//Button Debouncer
DEBOUNCER #(
.DELAY(8)
) db (
.clk(clkin1),
.IN (BUTTON[0]),
.OUT(rst)
);
//Output Serial Data
UART_CTRL uart_ctrl (
.clk(clk_10),
.rst(rst),
.tx_reg(tx_reg),
.tx_en(tx_en),
.tx_busy(tx_dv),
.tx(TX)
);
//RRAM controler
RRAM_CTRL #(
.g_RRAM_INV (5), //1,3,5,7
.g_RRAM_CELLS(64)
) rram_ctrl (
.clk(clk_10),
.rst(rst),
.tx_dv(tx_dv),
.tx_en(tx_en),
.tx_reg(tx_reg)
);
endmodule
| 7.454809 |
module top_level (
input CLK,
input [3:0] BUTTON,
output TX
);
wire rst;
wire clkin1, clk_100, clk_10;
wire [63:0] tx_reg;
wire tx_en, tx_dv;
wire [7:0] temp;
//Input Clk buffer
IBUF clkin1_buf (
.O(clkin1),
.I(CLK)
);
//Clk Divider - MMCM
CLK_DIV #(
.MULTI(6.0)
) clk_div (
.clkin1(clkin1),
.rst(rst),
.clk_out_10(clk_10)
);
//Button Debouncer
DEBOUNCER #(
.DELAY(8)
) db (
.clk(clkin1),
.IN (BUTTON[0]),
.OUT(rst)
);
//Output Serial Data
UART_CTRL uart_ctrl (
.clk(clk_10),
.rst(rst),
.tx_reg(tx_reg),
.tx_en(tx_en),
.tx_busy(tx_dv),
.tx(TX)
);
//RRAM controler
RRAM_CTRL #(
.g_RRAM_INV (5), //1,3,5,7
.g_RRAM_CELLS(50)
) rram_ctrl (
.clk(clk_10),
.rst(rst),
.tx_dv(tx_dv),
.tx_en(tx_en),
.tx_reg(tx_reg)
);
endmodule
| 7.454809 |
module clock_divider (
HCLK,
n_RST,
PRE,
tim_clk,
DFT_in,
DFT_sdi,
DFT_sen,
DFT_sdo
);
input HCLK, n_RST, DFT_in, DFT_sdi, DFT_sen;
input [2:0] PRE;
output tim_clk, DFT_sdo;
wire HCLK, n_RST, DFT_in, DFT_sdi, DFT_sen;
wire [2:0] PRE;
wire tim_clk, DFT_sdo;
wire clkdiv2, clkdiv4, clkdiv8, clkdiv16, clkdiv32, clkdiv64, logic_0_1_net, logic_0_2_net;
wire logic_0_3_net, logic_0_4_net, logic_0_5_net, logic_0_6_net, logic_0_7_net, n_0, n_1, n_2;
wire n_3, n_4, n_5, n_6, n_7, n_8, n_9, n_10;
wire n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18;
wire n_19, n_20, n_21, n_22, n_23, n_24, n_25, n_26;
wire n_27, n_28, n_29, n_30, n_31, n_32, n_33, n_34;
wire n_35, n_36;
nor2_1x g60 (
.A(n_32),
.B(DFT_in),
.X(n_34)
);
nor2_1x g61 (
.A(n_33),
.B(DFT_in),
.X(n_35)
);
nor2_1x g62 (
.A(n_31),
.B(DFT_in),
.X(n_36)
);
inv_1x g63 (
.A(PRE[1]),
.X(n_33)
);
inv_1x g64 (
.A(PRE[0]),
.X(n_32)
);
inv_1x g65 (
.A(PRE[2]),
.X(n_31)
);
ao21_1x g222 (
.A(n_29),
.B(n_35),
.C(n_30),
.X(tim_clk)
);
nor2_1x g223 (
.A(n_28),
.B(n_35),
.X(n_30)
);
ao21_1x g224 (
.A(n_24),
.B(n_36),
.C(n_27),
.X(n_29)
);
aoi21_1x g225 (
.A(n_25),
.B(n_34),
.C(n_26),
.X(n_28)
);
aoi21_1x g226 (
.A(n_23),
.B(n_19),
.C(n_36),
.X(n_27)
);
aoi21_1x g227 (
.A(n_18),
.B(n_20),
.C(n_34),
.X(n_26)
);
ao21_1x g228 (
.A(clkdiv32),
.B(n_36),
.C(n_21),
.X(n_25)
);
ao21_1x g229 (
.A(DFT_sdo),
.B(n_34),
.C(n_22),
.X(n_24)
);
nand2_1x g230 (
.A(clkdiv4),
.B(n_16),
.X(n_23)
);
and2_1x g231 (
.A(clkdiv64),
.B(n_16),
.X(n_22)
);
and2_1x g232 (
.A(clkdiv2),
.B(n_17),
.X(n_21)
);
nand2_1x g233 (
.A(n_17),
.B(HCLK),
.X(n_20)
);
nand2_1x g234 (
.A(clkdiv8),
.B(n_34),
.X(n_19)
);
nand2_1x g235 (
.A(clkdiv16),
.B(n_36),
.X(n_18)
);
inv_1x g236 (
.A(n_36),
.X(n_17)
);
inv_1x g237 (
.A(n_34),
.X(n_16)
);
sdffrq_1x clkdiv4_reg (
.RN (n_RST),
.CLK(n_15),
.D (n_7),
.SDI(clkdiv2),
.SEN(DFT_sen),
.Q (clkdiv4)
);
sdffrq_1x clkdiv8_reg (
.RN (n_RST),
.CLK(n_14),
.D (n_6),
.SDI(clkdiv4),
.SEN(DFT_sen),
.Q (clkdiv8)
);
sdffrq_1x clkdiv16_reg (
.RN (n_RST),
.CLK(n_13),
.D (n_5),
.SDI(clkdiv8),
.SEN(DFT_sen),
.Q (clkdiv16)
);
sdffrq_1x clkdiv128_reg (
.RN (n_RST),
.CLK(n_10),
.D (n_2),
.SDI(clkdiv64),
.SEN(DFT_sen),
.Q (DFT_sdo)
);
sdffrq_1x clkdiv64_reg (
.RN (n_RST),
.CLK(n_11),
.D (n_3),
.SDI(clkdiv32),
.SEN(DFT_sen),
.Q (clkdiv64)
);
sdffrq_1x clkdiv32_reg (
.RN (n_RST),
.CLK(n_12),
.D (n_1),
.SDI(clkdiv16),
.SEN(DFT_sen),
.Q (clkdiv32)
);
ao21_1x g125 (
.A(clkdiv2),
.B(n_0),
.C(n_9),
.X(n_15)
);
oai21_1x g126 (
.A(n_7),
.B(DFT_in),
.C(n_8),
.X(n_14)
);
oai21_1x g127 (
.A(n_6),
.B(DFT_in),
.C(n_8),
.X(n_13)
);
oai21_1x g128 (
.A(n_5),
.B(DFT_in),
.C(n_8),
.X(n_12)
);
oai21_1x g129 (
.A(n_1),
.B(DFT_in),
.C(n_8),
.X(n_11)
);
oai21_1x g130 (
.A(n_3),
.B(DFT_in),
.C(n_8),
.X(n_10)
);
sdffrq_1x clkdiv2_reg (
.RN (n_RST),
.CLK(HCLK),
.D (n_4),
.SDI(DFT_sdi),
.SEN(DFT_sen),
.Q (clkdiv2)
);
inv_1x g132 (
.A(n_8),
.X(n_9)
);
nand2_1x g133 (
.A(DFT_in),
.B(HCLK),
.X(n_8)
);
inv_1x g134 (
.A(clkdiv4),
.X(n_7)
);
inv_1x g135 (
.A(clkdiv8),
.X(n_6)
);
inv_1x g136 (
.A(clkdiv16),
.X(n_5)
);
inv_1x g137 (
.A(clkdiv2),
.X(n_4)
);
inv_1x g138 (
.A(clkdiv64),
.X(n_3)
);
inv_1x g139 (
.A(DFT_sdo),
.X(n_2)
);
inv_1x g140 (
.A(clkdiv32),
.X(n_1)
);
inv_1x g141 (
.A(DFT_in),
.X(n_0)
);
tielo_1x tie_0_cell (.X(logic_0_1_net));
tielo_1x tie_0_cell1 (.X(logic_0_2_net));
tielo_1x tie_0_cell2 (.X(logic_0_3_net));
tielo_1x tie_0_cell3 (.X(logic_0_4_net));
tielo_1x tie_0_cell4 (.X(logic_0_5_net));
tielo_1x tie_0_cell5 (.X(logic_0_6_net));
tielo_1x tie_0_cell6 (.X(logic_0_7_net));
endmodule
| 6.818038 |
module top_level_crossbar (
clock,
reset,
req_1m,
cmd_1m,
req_2m,
cmd_2m,
wdata_1m,
wdata_2m,
addr_1m,
addr_2m
);
parameter CLK_HALF_PERIOD = 5;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
input wire clock, reset, req_1m, cmd_1m, req_2m, cmd_2m;
input wire [DATA_WIDTH-1:0] wdata_1m, wdata_2m;
input wire [ADDR_WIDTH-1:0] addr_1m, addr_2m;
// линии соединения автоматов
wire req_1m_1s, ack_1m_1s, cmd_1m_1s,
req_2m_1s, ack_2m_1s, cmd_2m_1s,
req_1m_2s, ack_1m_2s, cmd_1m_2s,
req_2m_2s, ack_2m_2s, cmd_2m_2s;
wire [DATA_WIDTH-1:0] wdata_1m_1s, rdata_1m_1s,
wdata_2m_1s, rdata_2m_1s,
wdata_1m_2s, rdata_1m_2s,
wdata_2m_2s, rdata_2m_2s;
wire [ADDR_WIDTH-1:0] addr_1m_1s, addr_2m_1s, addr_1m_2s, addr_2m_2s;
fsm_master_1 #(DATA_WIDTH, ADDR_WIDTH) dut1master (
.clock(clock),
.reset(reset),
.req_m(req_1m),
.cmd_m (cmd_1m), // признак операции Мастера 1: 0 - чтение, 1 - запись
.addr_m(addr_1m), // адрес запроса от Мастера 1
.wdata_m(wdata_1m), // данные на запись от Мастера 1
.ack_1s (ack_1m_1s), // сигнал - подтрверждение операции от Слэйва 1
.ack_2s (ack_1m_2s), // сигнал - подтрверждение операции от Слэйва 2
.rdata_1s(rdata_1m_1s), // данные, выдаваемые в Мастер 1
.rdata_2s(rdata_1m_2s), // данные, выдаваемые в Мастер 2
// выходы
.cmd_1s(cmd_1m_1s),
.cmd_2s(cmd_1m_2s),
.req_1s(req_1m_1s), // запрос транзакции в Слэйв 1
.req_2s(req_1m_2s), // запрос транзакции от Слэйв 2
.addr_1s(addr_1m_1s),
.addr_2s(addr_1m_2s),
.wdata_1s(wdata_1m_1s),
.wdata_2s(wdata_1m_2s)
);
fsm_master_1 #(DATA_WIDTH, ADDR_WIDTH) dut2master (
.clock(clock),
.reset(reset),
.req_m(req_2m),
.cmd_m (cmd_2m), // признак операции Мастера 1: 0 - чтение, 1 - запись
.addr_m(addr_2m), // адрес запроса от Мастера 1
.wdata_m(wdata_2m), // данные на запись от Мастера 1
.ack_1s (ack_2m_1s), // сигнал - подтрверждение операции от Слэйва 1
.ack_2s (ack_2m_2s), // сигнал - подтрверждение операции от Слэйва 2
.rdata_1s(rdata_2m_1s), // данные, выдаваемые в Мастер 1
.rdata_2s(rdata_2m_2s), // данные, выдаваемые в Мастер 2
// выходы
.cmd_1s(cmd_2m_1s),
.cmd_2s(cmd_2m_2s),
.req_1s(req_2m_1s), // запрос транзакции в Слэйв 1
.req_2s(req_2m_2s), // запрос транзакции от Слэйв 2
.addr_1s(addr_2m_1s),
.addr_2s(addr_2m_2s),
.wdata_1s(wdata_2m_1s),
.wdata_2s(wdata_2m_2s)
);
fsm_slave_1 #(DATA_WIDTH, ADDR_WIDTH) dut1slave (
.clock(clock),
.reset(reset),
.req_1m(req_1m_1s),
.req_2m(req_2m_1s),
.addr_1m(addr_1m_1s),
.addr_2m(addr_2m_1s),
.wdata_1m(wdata_1m_1s),
.wdata_2m(wdata_2m_1s),
.cmd_1m(cmd_1m_1s),
.cmd_2m(cmd_2m_1s),
.ack_1m(ack_1m_1s),
.ack_2m(ack_2m_1s),
.rdata_1m(rdata_1m_1s),
.rdata_2m(rdata_2m_1s)
);
fsm_slave_1 #(DATA_WIDTH, ADDR_WIDTH) dut2slave (
.clock(clock),
.reset(reset),
.req_1m(req_1m_2s),
.req_2m(req_2m_2s),
.addr_1m(addr_1m_2s),
.addr_2m(addr_2m_2s),
.wdata_1m(wdata_1m_2s),
.wdata_2m(wdata_2m_2s),
.cmd_1m(cmd_1m_2s),
.cmd_2m(cmd_2m_2s),
.ack_1m(ack_1m_2s),
.ack_2m(ack_2m_2s),
.rdata_1m(rdata_1m_2s),
.rdata_2m(rdata_2m_2s)
);
endmodule
| 8.030036 |
module Top_level_design (
i_clk,
data_in_1,
data_in_2,
start,
p_STATE,
o_reg_Q,
o_reg_R,
o_reg_B,
Count_out,
done
);
input i_clk;
input [`WIDTH1-1:0] data_in_1; ////divisor B ///
//input rst_n ;
input start;
input [`WIDTH1-1:0] data_in_2; ///dividened Q///
output [`WIDTH1-1:0] o_reg_B;
output [`WIDTH1-1:0] o_reg_R;
output [`WIDTH1-1:0] o_reg_Q;
output [`WIDTH3-1:0] p_STATE;
wire R_out, add_enable, load_b, load_r, load_q, clr_nn;
wire enable_q, done, shift_en_q, clr_Reg_r, clr_ADD, clr_d, z_cnt, load_cnt;
output [`WIDTH4-1:0] Count_out;
output done;
DATAPATH DU (
i_clk,
clr_d,
clr_nn,
shift_en_q,
enable_q,
enable_r,
data_in_1,
data_in_2,
o_reg_B,
o_reg_R,
o_reg_Q,
load_b,
load_cnt,
load_r,
load_q,
add_enable,
R_out,
clr_ADD,
clr_Reg_r,
z_cnt,
Count_out
);
CONTROLLER CU (
i_clk,
clr_d,
start,
load_r,
load_b,
load_q,
R_out,
enable_r,
enable_q,
p_STATE,
add_enable,
done,
shift_en_q,
clr_ADD,
clr_Reg_r,
load_cnt,
z_cnt,
clr_nn
);
endmodule
| 7.501161 |
module Top_level_design_tb ();
reg i_clk;
reg [`WID_1-1:0] data_in_1; ////divisor B ///
//reg rst_n ;
reg start;
reg [`WID_1-1:0] data_in_2; ///dividened Q///
wire [`WID_1-1:0] o_reg_B;
wire [`WID_1-1:0] o_reg_R;
wire [`WID_1-1:0] o_reg_Q;
wire [`WID_3-1:0] Count_out;
wire [`WID_2-1:0] p_STATE;
wire done;
Top_level_design DUT (
i_clk,
data_in_1,
data_in_2,
start,
p_STATE,
o_reg_Q,
o_reg_R,
o_reg_B,
Count_out,
done
);
initial begin
i_clk = 1'b0;
start = 1'b1;
// rst_n = 1'b1 ;
//start = 1'b0 ;
end
always #5 i_clk = ~i_clk;
initial begin
//#1 rst_n = 1'b0 ;
#1 start = 1'b1;
#2 data_in_1 = 4'b0010;
#1 data_in_2 = 4'b1111;
#300 $stop;
end
endmodule
| 7.501161 |
module top_level_D_latch_try_2 (
SW,
LEDR
); //Defines Module
input wire [1:0] SW; //Definess input wire bus for 2 swithces
output wire [3:0] LEDR; //Defines output wire bus for 4 LEDRS
D_latch_try_2(
SW[1], SW[0], LEDR[2], LEDR[3]
); //Instantiates the D Latch module
assign LEDR[1:0] = SW[1:0]; //Assigns LEDRS[1:0] to SW[1:0]
endmodule
| 6.662342 |
module top_level_frameGenerator #(
parameter LEN_DATA_BLOCK = 64,
parameter LEN_CTRL_BLOCK = 8
) (
input i_clock,
input i_reset,
input i_enable,
output wire [LEN_DATA_BLOCK-1 : 0] o_tx_data,
output wire [LEN_CTRL_BLOCK-1 : 0] o_tx_ctrl
);
//Registros y parametros para parametrizacion y generacion de ruido
localparam LEN_GNG = 16;
localparam NB_TERM = 3;
localparam NB_DATA = 8;
localparam NB_IDLE = 5;
wire noise_enable;
wire noise_valid;
wire [LEN_GNG-1:0] noise_data;
wire [NB_TERM-1:0] nterm;
wire [NB_DATA-1:0] ndata;
wire [NB_IDLE-1:0] nidle;
assign noise_enable = 1'b1;
assign nterm = noise_data[LEN_GNG-8 -: NB_TERM]; //3 bits mas significativos para establecer el numero de terminate
assign ndata = (noise_data[LEN_GNG-4 -: NB_DATA] > 8'b1100100) ?
8'b11000110 : noise_data[LEN_GNG-4 -: NB_DATA]; //8 bits siguientes para data
assign nidle = noise_data[LEN_GNG-8-:NB_IDLE]; //6 bits menos significativos para idle
//Registros y parametros para el generador de frames
wire frameGenerator_enb;
assign frameGenerator_enb = (noise_valid == 1'b1) ? 1'b1 : 1'b0;
frameGenerator #() u_frameGenerator (
.i_clock (i_clock),
.i_reset (i_reset),
.i_enable (frameGenerator_enb),
.i_ndata (ndata),
.i_nidle (nidle),
.i_nterm (nterm),
.o_tx_data(o_tx_data),
.o_tx_ctrl(o_tx_ctrl)
);
gng #() u_GaussianNoiseGenerator (
.clk(i_clock),
.rstn(~i_reset),
.ce(noise_enable),
.valid_out(noise_valid),
.data_out(noise_data)
);
endmodule
| 7.64203 |
module top_level_gated_sr_latch (
SW,
LEDR
); //declares module
input wire [2:0] SW; //defines input wires for Switches
output wire [4:0] LEDR; //defines output wires for LEDRs
gated_sr_latch(
SW[1], SW[0], SW[2], LEDR[3], LEDR[4]
); //instantiates gated_sr_latch
assign LEDR[2:0] = SW[2:0]; //assigns LEDRs to Switches
endmodule
| 8.006669 |
modules
//
/////////////////////////////////////////////////////////////////////////////////////////
module top_level_integration(
// Outputs
output reg [25:0] addr_to_L2,
output reg [1:0] command_to_L2,
input mode,
// Inputs
input Clock,
input clear,
input [3:0] n,
input [31:0] address_in,
input Finish);
// For statistics module
wire [31:0] data_hit;
wire [31:0] data_miss;
wire [31:0] data_reads;
wire [31:0] data_writes;
wire [31:0] instr_hit;
wire [31:0] instr_miss;
wire [31:0] instr_reads;
// Commands from tracefile
parameter Reset = 4'd8;
parameter Invalidate = 4'd3;
parameter Read = 4'd0;
parameter Write = 4'd1;
parameter Instruction_Fetch = 4'd2;
parameter Print = 4'd9;
parameter Snoop =4'd4;
// Communication between L1 and L2 caches
wire [1:0] l2_i_cmd, l2_d_cmd;
wire [25:0] l2_i_add, l2_d_add;
// signals from file to caches
wire [31:0] i_add, d_add;
assign i_add = address_in;
assign d_add = address_in;
//Mux the commands accordingly to L2 cache
always @(n)
begin
if(n == Instruction_Fetch)
begin
addr_to_L2 = l2_i_add;
command_to_L2 = l2_i_cmd;
end
else
begin
addr_to_L2 = l2_d_add;
command_to_L2 = l2_d_cmd;
end
end
data_cache data_cache (
.n(n),
.address_in(address_in),
.Clock(Clock),
.addr_to_L2(l2_d_add),
.command_to_L2(l2_d_cmd),
.hit(data_hit),
.miss(data_miss),
.reads(data_reads),
.writes(data_writes),
.mode(mode));
instruction_cache instr_cache (
.Clock(Clock),
.n(n),
.address_in(address_in),
.addr_to_L2(l2_i_add),
.command_to_L2(l2_i_cmd),
.hit(instr_hit),
.miss(instr_miss),
.reads(instr_reads),
.mode(mode));
statistics stats(
.print(Finish),
.ins_reads(instr_reads),
.ins_hit(instr_hit),
.ins_miss(instr_miss),
.data_reads(data_reads),
.data_writes(data_writes),
.data_hit(data_hit),
.data_miss(data_miss)
);
endmodule
| 7.33426 |
module top_level_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input [7:0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk) begin
if (fifo_wr) $write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.712905 |
module top_level_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
);
output fifo_FF;
output [7:0] r_dat;
output wfifo_empty;
output [5:0] wfifo_used;
input clk;
input fifo_clear;
input [7:0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [7:0] r_dat;
wire wfifo_empty;
wire [5:0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
top_level_jtag_uart_0_sim_scfifo_w the_top_level_jtag_uart_0_sim_scfifo_w (
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty(wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.712905 |
module top_level_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [31:0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7:0] fifo_rdata;
wire new_rom;
wire [31:0] num_bytes;
wire [ 6:0] rfifo_entries;
wire rfifo_full;
wire [ 5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n) begin
if (rst_n == 0) begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end else begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d) bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom) bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
| 6.712905 |
module top_level_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
);
output fifo_EF;
output [7:0] fifo_rdata;
output rfifo_full;
output [5:0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [7:0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [7:0] fifo_rdata;
wire rfifo_full;
wire [5:0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
top_level_jtag_uart_0_sim_scfifo_r the_top_level_jtag_uart_0_sim_scfifo_r (
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata(fifo_rdata),
.rfifo_full(rfifo_full),
.rfifo_used(rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
| 6.712905 |
module
module top_level_module (testmode,sysclk,modeControl,resetb,Hex0,Hex1,Hex2,Hex3,LEDR);
input [1:0] testmode;
input sysclk,modeControl,resetb;
output [6:0] Hex0,Hex1,Hex2,Hex3;
output LEDR;
wire sigIn,sigOut,sig1Hz,enable,reset,lock;
wire [15:0] count;
wire [3:0] out0,out1,out2,out3;
assign LEDR=(modeControl)?1'b1:1'b0;
signalInput si(.sysclk(sysclk),.resetb(resetb),.testmode(testmode),.sigIn(sigIn));
Frequence_range fr(.modeControl(modeControl),.sigIn(sigIn),.sigOut(sigOut));
signal_1Hz s_1(.sysclk(sysclk),.sig1Hz(sig1Hz));
Control c(.signal_1Hz(sig1Hz),.enable(enable),.reset(reset),.lock(lock));
Decimal_counter dc(.sigIn(sigOut),.enable(enable),.reset(reset),.count(count));
Latch_16bits l(.count(count),.lock(lock),.out0(out0),.out1(out1),.out2(out2),.out3(out3));
Decoding_diplay dd(.out0(out0),.out1(out1),.out2(out2),.out3(out3),.Hex0(Hex0),.Hex1(Hex1),.Hex2(Hex2),.Hex3(Hex3));
endmodule
| 7.252875 |
module top_level_mux2_1 (
input choice0,
input choice1,
input selection_bit,
output selected_output
);
assign selected_output = selection_bit ? choice1 : choice0;
endmodule
| 7.760832 |
module top_level_pipeline_cpu ();
wire clk;
Pipelined_CPU Pipelined_CPU (
.clk (clk),
.clk10(clk),
.stall(0),
.clk12(clk),
.clk13(clk),
.clk14(clk),
.clk16(clk),
.clk17(clk),
.clk18(clk),
.clk19(clk)
);
Clock b2v_inst1 (.clk(clk));
endmodule
| 7.858017 |
module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
module top_level_Pixel_Buffer (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
// Bi-Directional
SRAM_DQ,
// Outputs
readdata,
readdatavalid,
SRAM_ADDR,
SRAM_LB_N,
SRAM_UB_N,
SRAM_CE_N,
SRAM_OE_N,
SRAM_WE_N
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [17: 0] address;
input [ 1: 0] byteenable;
input read;
input write;
input [15: 0] writedata;
// Bi-Directional
inout [15: 0] SRAM_DQ; // SRAM Data bus 16 Bits
// Outputs
output reg [15: 0] readdata;
output reg readdatavalid;
output reg [17: 0] SRAM_ADDR; // SRAM Address bus 18 Bits
output reg SRAM_LB_N; // SRAM Low-byte Data Mask
output reg SRAM_UB_N; // SRAM High-byte Data Mask
output reg SRAM_CE_N; // SRAM Chip chipselect
output reg SRAM_OE_N; // SRAM Output chipselect
output reg SRAM_WE_N; // SRAM Write chipselect
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg is_read;
reg is_write;
reg [15: 0] writedata_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
readdata <= SRAM_DQ;
readdatavalid <= is_read;
SRAM_ADDR <= address;
SRAM_LB_N <= ~(byteenable[0] & (read | write));
SRAM_UB_N <= ~(byteenable[1] & (read | write));
SRAM_CE_N <= ~(read | write);
SRAM_OE_N <= ~read;
SRAM_WE_N <= ~write;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
is_read <= 1'b0;
else
is_read <= read;
end
always @(posedge clk)
begin
if (reset)
is_write <= 1'b0;
else
is_write <= write;
end
always @(posedge clk)
begin
writedata_reg <= writedata;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign SRAM_DQ = (is_write) ? writedata_reg : 16'hzzzz;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
| 7.349016 |
module top_level_p_data (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [ 7:0] data_out;
wire [ 7:0] out_port;
wire [ 7:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.871021 |
module top_level_p_input (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [1:0] in_port;
input reset_n;
wire clk_en;
wire [ 1:0] data_in;
wire [ 1:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.55246 |
module top_level_p_signal (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [1:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [ 1:0] data_out;
wire [ 1:0] out_port;
wire [ 1:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[1 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 7.163024 |
module top_level (
input clk_100mhz_in,
inout [7:0] IO_P9,
output [7:0] IO_P8,
inout [7:0] IO_P7,
output [7:0] LED,
input [5:0] Switch,
output [7:0] SevenSegment,
output [2:0] SevenSegmentEnable
);
wire clk_sample;
wire clk_100mhz;
wire clk_7seg_scan;
wire rst;
wire rx_in;
wire rx_d_out_valid;
wire rx_reframe;
wire [7:0] rx_d_out;
wire fast_blink;
wire fifo_below_min;
wire clk_external;
wire [7:0] fifo_d_out;
reg rx_in_s;
reg clk_external_s;
reg clk_external_s_prev;
reg reframe_led;
reg data_led;
reg [7:0] last_rx_data;
// IO Outputs
assign rst = ~Switch[5];
assign LED[7:6] = {reframe_led, data_led};
assign LED[5:0] = 6'b0;
assign IO_P9 = {clk_recovered, {7{1'bZ}}};
assign IO_P8 = fifo_d_out;
assign IO_P7 = {1'bZ, ~fifo_below_min, {6{1'bZ}}};
// IO Inputs
assign rx_in = IO_P9[5];
assign clk_external = IO_P7[5];
pll_sample_clk pll_s (
.RESET(rst),
.CLK_IN1(clk_100mhz_in),
.CLK_OUT1(clk_sample),
.CLK_OUT2(clk_100mhz)
);
rx rx (
.clk_x8(clk_sample),
.rst(rst),
.d_in(rx_in_s),
.clk_recovered(clk_recovered),
.d_out(rx_d_out),
.d_out_valid(rx_d_out_valid),
.reframe(rx_reframe)
);
// The FIFO must be continuously clocked on the read side to ensure
// the DREQ signal is updated. The rising edge of the "clock" from the Pi
// is then synchronously detected and used as a write enable pulse.
rx_fifo fifo (
.rst(rst),
.wr_clk(clk_sample),
.rd_clk(clk_100mhz),
.din(rx_d_out),
.wr_en(rx_d_out_valid),
.rd_en(clk_external_s && !clk_external_s_prev),
.dout(fifo_d_out),
.full(),
.empty(),
.prog_empty(fifo_below_min)
);
blinky #(
.width(24)
) blink1 (
.clk(clk_sample),
.rst(rst),
.out(fast_blink)
);
blinky #(
.width(18)
) blink2 (
.clk(clk_sample),
.rst(rst),
.out(clk_7seg_scan)
);
sevenseg_controller sseg_ctrl (
.clk_scan(clk_7seg_scan),
.rst(rst),
.value({4'b0, last_rx_data}),
.sevenseg_enables(SevenSegmentEnable),
.sevenseg_segments(SevenSegment)
);
always @(posedge clk_sample or posedge rst) begin
if (rst) begin
rx_in_s <= 0;
last_rx_data <= 0;
end else begin
rx_in_s <= rx_in;
if (rx_d_out_valid) begin
last_rx_data <= rx_d_out;
data_led <= fast_blink;
reframe_led <= 0;
end else if (rx_reframe) begin
data_led <= 0;
reframe_led <= fast_blink;
end
end
end
always @(posedge rst or posedge clk_100mhz) begin
if (rst) begin
{clk_external_s, clk_external_s_prev} <= 2'b0;
end else begin
clk_external_s <= clk_external;
clk_external_s_prev <= clk_external_s;
end
end
endmodule
| 7.454809 |
module to the Digilent S7 board.
* Inputs and outputs are defined in the XDC Master Constraint File
* provided by Xilinx.
*
* Dependencies:
*
* Revision:
* Revision 0.01 - File Created
* Additional Comments:
*
*/
module top_level_serial(
input enable,
input ck_io26,
input ck_io27,
input ck_io28,
input ck_io29,
input ck_io30,
input ck_io31,
input ck_io32,
input ck_io33,
output ck_io34,
output ck_io35,
output ck_io36,
output ck_io37,
output ck_io38,
output ck_io39,
output ck_io40,
output ck_io41,
input clk,
input orred,
input ck_io0,
output ck_io8
);
(* dont_touch = "yes" *) wire [7:0] challenge;
(* dont_touch = "yes" *) wire [7:0] response;
(* dont_touch = "yes" *) wire [31:0] enables;
(* dont_touch = "yes" *) wire done;
assign challenge = {ck_io26, ck_io27, ck_io28, ck_io29, ck_io30, ck_io31, ck_io32, ck_io33};
assign response = {ck_io34, ck_io35, ck_io36, ck_io37, ck_io38, ck_io39, ck_io40, ck_io41};
assign enables = {32{enable}};
assign ck_io8 = orred | done;
(* dont_touch = "yes" *) puf_serial serial_scheme(enables, challenge, response, done, clk, ck_io0); // ck_io0 is computer_ack for reset
endmodule
| 6.862602 |
module top_level_sr_latch (
SW,
LEDR
); //declares module
input wire [1:0] SW; //defines input wires for Switches
output wire [3:0] LEDR; //defines output wires for LEDRs
sr_latch(
SW[1], SW[0], LEDR[2], LEDR[3]
); //instantiates sr_latch
assign LEDR[1:0] = SW[1:0]; //assigns LEDRs to Switches
endmodule
| 7.644832 |
module top_level_tb ();
reg stm_clk, stm_rst, stm_wrt_tx, stm_rd_rx, stm_sel_low, stm_sel_high;
reg [1:0] stm_br_cfg;
reg [7:0] stm_tx_data, stm_baud_data_in;
reg [15:0] baud_rate_data;
wire tbr_mon, txd_mon, rx_in, tx_rx_en, tb_rda_mon;
wire [7:0] final_data_mon;
reg [2:0] i;
reg [3:0] flags;
top_level top0 (
.clk (stm_clk), // 100mhz clock
.rst (stm_rst), // Asynchronous reset, tied to dip switch 0
.txd (txd_mon), // RS232 Transmit Data
.rxd (rx_in), // RS232 Recieve Data
.br_cfg(stm_br_cfg) // Baud Rate Configuration, Tied to dip switches 2 and 3
);
baud_rate_gen baud_tb0 (
.clk(stm_clk),
.rst(stm_rst),
.en(tx_rx_en),
.data(stm_baud_data_in),
.sel_low(stm_sel_low),
.sel_high(stm_sel_high)
);
tx tx_tb0 (
.clk(stm_clk),
.rst(stm_rst),
.data(stm_tx_data),
.en(tx_rx_en),
.en_tx(stm_wrt_tx),
.tbr(tbr_mon),
.TxD(rx_in)
);
rx rx_tb0 (
.clk(stm_clk),
.rst(stm_rst),
.RxD(txd_mon),
.Baud(tx_rx_en),
.RxD_data(final_data_mon),
.RDA(tb_rda_mon),
.rd_rx(stm_rd_rx)
);
/*
always
case(i[1:0])
2'b00 : baud_rate_data = 16'h12c0;
2'b01 : baud_rate_data = 16'h2580;
2'b10 : baud_rate_data = 16'h4b00;
2'b11 : baud_rate_data = 16'h9600;
endcase
*/
always #5 stm_clk <= ~stm_clk;
initial begin
flags = 4'hf;
for (i = 0; i < 4; i = i + 1) begin
stm_clk = 0;
stm_rst = 1;
stm_br_cfg = i[1:0];
// Baud Init
stm_baud_data_in = (i[1:0] == 2'b00) ? 8'hc0 : (i[1:0] == 2'b01) ? 8'h80 : 8'h00;
stm_sel_low = 1;
stm_sel_high = 0;
// TX Init
stm_tx_data = 8'h40;
stm_wrt_tx = 0;
// RX Init
stm_rd_rx = 0;
// Load Low Buffer
@(posedge stm_clk);
stm_rst = 0;
$display("Low Buffer Loading...");
// Load High Buffer
@(posedge stm_clk);
$display("High Buffer Loading...");
stm_sel_low = 0;
stm_sel_high = 1;
stm_baud_data_in = (i[1:0] == 2'b00) ? 8'h12 :
(i[1:0] == 2'b01) ? 8'h25 :
(i[1:0] == 2'b10) ? 8'h4b : 8'h96;
// Send Data (Ready to Receive)
@(posedge stm_clk);
stm_sel_high = 0;
$display("Sending data...");
// Start sending spart data
stm_wrt_tx = 1;
@(posedge stm_clk);
stm_wrt_tx = 0;
$display("Waiting for receive signal...");
@(posedge tb_rda_mon);
@(posedge stm_clk);
if (final_data_mon != stm_tx_data) begin
flags = (i[1:0] == 2'b00) ? flags & 4'b1110 :
(i[1:0] == 2'b01) ? flags & 4'b1101 :
(i[1:0] == 2'b10) ? flags & 4'b1011 : flags & 4'b0111;
end
end
if (&flags) $display("All tests passed!");
else $display("Some tests failed, check flags: %h", flags);
$stop();
/*
if(final_data_mon != stm_tx_data)
$display("An error occured");
else
$display("Test passed!");
$finish();
*/
end
endmodule
| 8.61882 |
module top_level (
input clk_100mhz,
input clk_12mhz,
input rx_in,
output tx_out,
output clk_recovered,
output [7:0] LED,
input [5:0] Switch,
input [7:0] DPSwitch,
output [7:0] SevenSegment,
output [2:0] SevenSegmentEnable
);
wire clk_sample;
wire clk_bit_tx;
wire rst;
wire scan_clk_7seg;
reg rx_in_s;
wire [7:0] rx_d_out;
reg [7:0] rx_d_out_s;
wire rx_d_out_valid;
wire rx_reframe;
reg reframe_led;
reg data_led;
wire fast_blink;
assign rst = ~Switch[5];
assign LED[6:5] = {reframe_led, data_led};
assign LED[4:0] = 4'b0;
pll_tx_clk pll_t (
.RESET(rst),
.CLK_IN1(clk_12mhz),
.CLK_OUT1(clk_bit_tx)
);
pll_sample_clk pll_s (
.RESET(rst),
.CLK_IN1(clk_100mhz),
.CLK_OUT1(clk_sample)
);
rx rx (
.clk_x8(clk_sample),
.rst(rst),
.d_in(rx_in_s),
.clk_recovered(clk_recovered),
.d_out(rx_d_out),
.d_out_valid(rx_d_out_valid),
.reframe(rx_reframe)
);
tx tx (
.clk_bit(clk_bit_tx),
.rst(rst),
.prbs_on(1'b0),
.d_in(DPSwitch),
// Push switch to idle
.d_in_valid(~Switch[4]),
.out(tx_out)
);
blinky #(
.width(18)
) blink1 (
.clk(clk_sample),
.rst(rst),
.out(scan_clk_7seg)
);
blinky #(
.width(24)
) blink2 (
.clk(clk_sample),
.rst(rst),
.out(fast_blink)
);
// Output
sevenseg_controller sseg_ctrl (
.clk_scan(scan_clk_7seg),
.rst(rst),
.value(rx_d_out_s),
.sevenseg_enables(SevenSegmentEnable),
.sevenseg_segments(SevenSegment)
);
always @(posedge clk_sample or posedge rst) begin
if (rst) begin
rx_d_out_s <= 0;
rx_in_s <= 0;
end else begin
rx_in_s <= rx_in;
if (rx_d_out_valid) begin
rx_d_out_s <= rx_d_out;
data_led <= fast_blink;
reframe_led <= 0;
end else if (rx_reframe) begin
data_led <= 0;
reframe_led <= fast_blink;
end
end
end
endmodule
| 7.454809 |
module topLevel_top (
input c,
u, // Botao 1, 2,
input cima,
baixo,
enter, // Botao 3,4,5
input clock,
reset, // 50 MHz Clock
output [9:0] led, // Led
output [3:0] ledTeste,
output sucesso, // Parametro para afirmar se funcionou ou nao
output pizza,
burguer,
torta,
soda // saidas da maquina
);
wire [5:0] saldo, gasto;
controle_de_saldo cds (
.c(c),
.u(u),
.clock(clock),
.reset(reset),
.gastoIn(gasto),
.sucesso(sucesso),
.led(led),
.saldoOut(saldo)
);
menu main (
.cima(cima),
.baixo(baixo),
.enter(enter),
.clock(clock),
.reset(reset),
.saldoIn(saldo),
.pizza(pizza),
.burguer(burguer),
.torta(torta),
.soda(soda),
.gastoOut(gasto),
.ledTeste(ledTeste)
);
endmodule
| 7.191273 |
module top_level_tx (
input clk_100mhz_in,
inout [9:0] IO_P2,
output [0:0] IO_P3,
output [7:0] LED,
input [3:0] Switch
);
wire clk_bit;
wire clk_100mhz;
wire rst;
wire [7:0] tx_d_in;
wire [7:0] fifo_d_in;
wire fifo_empty;
wire fifo_full;
wire fifo_read_enable;
wire prbs_on;
wire led_mode;
wire prbs_toggle_switch;
wire tx_idle;
wire tx_out;
wire fast_blink;
reg data_led;
reg idle_led;
reg prbs_led;
reg clk_external_s;
reg clk_external_s_prev;
reg [7:0] leds;
assign IO_P2 = {~fifo_full, {9{1'bZ}}};
assign IO_P3 = tx_out;
//assign LED = {data_led, idle_led, prbs_led, 5'b0};
assign LED = leds;
assign rst = ~Switch[3];
assign prbs_toggle_switch = ~Switch[2];
assign fifo_d_in = IO_P2[7:0];
assign clk_external = IO_P2[8];
pll_tx_clk pll_t (
.RESET(rst),
.CLK_IN1(clk_100mhz_in),
.CLK_OUT1(clk_bit),
.CLK_OUT2(clk_100mhz)
);
tx inst_tx (
.clk_bit (clk_bit),
.rst (rst),
.d_in (tx_d_in),
.d_in_valid (~fifo_empty),
.prbs_on (prbs_on),
.out (tx_out),
.read_enable(fifo_read_enable),
.idle (tx_idle)
);
// The FIFO must be continuously clocked on the write side to ensure
// the "full" signal is updated. The rising edge of the "clock" from the Pi
// is then synchronously detected and used as a write enable pulse.
tx_fifo fifo (
.rst(rst),
.wr_clk(clk_100mhz),
.rd_clk(clk_bit),
.din(fifo_d_in),
.wr_en(clk_external_s && !clk_external_s_prev),
.rd_en(fifo_read_enable),
.dout(tx_d_in),
.full(),
.prog_full(fifo_full),
.empty(fifo_empty)
);
blinky #(
.width(21)
) blink (
.clk(clk_bit),
.rst(rst),
.out(fast_blink)
);
debounce_toggle prbs_toggle (
.clk(clk_bit),
.rst(rst),
.button(prbs_toggle_switch),
.out(prbs_on)
);
debounce_toggle led_toggle (
.clk(clk_bit),
.rst(rst),
.button(~Switch[1]),
.out(led_mode)
);
always @(posedge rst or posedge clk_bit) begin
if (rst) begin
{data_led, idle_led, prbs_led} <= 3'b0;
end else if (led_mode == 0) begin
if (prbs_on) begin
leds <= {1'b0, 1'b0, fast_blink, 5'b0};
end else if (tx_idle) begin
leds <= {1'b0, fast_blink, 1'b0, 5'b0};
end else begin
leds <= {fast_blink, 1'b0, 1'b0, 5'b0};
end
end else if (fifo_read_enable) begin
leds <= tx_d_in;
end
end
always @(posedge rst or posedge clk_100mhz) begin
if (rst) begin
{clk_external_s, clk_external_s_prev} <= 2'b0;
end else begin
clk_external_s <= clk_external;
clk_external_s_prev <= clk_external_s;
end
end
endmodule
| 6.64078 |
module top_level_ukf (
input wr_rst,
input wr_enable,
input [127:0] write_data,
input reset,
fast_clock,
slow_clock
);
wire [31:0] rd_data_diag, rd_data_l1, rd_data_l2, rd_data_l3, rd_data_l4;
wire empty_l1, empty_l2, empty_l3, empty_l4, empty_diag, fifo_wre_lower, fifo_wre_diag;
wire start, stop_pipeline, fifo_rde_diag, data_in_diag;
wire [3:0] matrix_size_out;
wire data_in_1, data_in_2, data_in_3, data_in_4;
wire finish;
assign running = 1'b1; //rever
assign parallel_units = 4'b0100;
assign read_diag = fifo_rde_diag || data_in_diag;
fifo_interface fifo_interface1 (
.wr_rst(wr_rst),
.wr_clk(slow_clock),
.wr_en_d(fifo_wre_diag),
.wr_en_l(fifo_wre_lower),
.wr_data_l(write_data),
.wr_data_diag(write_data),
.rd_rst(reset),
.rd_clk(fast_clock),
.rd_en_l1 (data_in_1),
.rd_en_l2 (data_in_2),
.rd_en_l3 (data_in_3),
.rd_en_l4 (data_in_4),
.rd_en_diag(read_diag),
.rd_data_l1 (rd_data_l1),
.rd_data_l2 (rd_data_l2),
.rd_data_l3 (rd_data_l3),
.rd_data_l4 (rd_data_l4),
.rd_data_diag(rd_data_diag), //.full_l1(finish),
//output reg full_l1(),full_l2,full_l3,full_l4,full_diag,
.empty_l1 (empty_l1),
.empty_l2 (empty_l2),
.empty_l3 (empty_l3),
.empty_l4 (empty_l4),
.empty_diag(empty_diag)
);
ukf_fifo_control ukf_fifo_control1 (
.fifo_out_diag(write_data), //verificar tamanho
.matrix_size_out(matrix_size_out),
.stop_pipeline (stop_pipeline),
.fifo_wre_diag (fifo_wre_diag),
.fifo_wre_lower (fifo_wre_lower),
.fifo_rde_diag(fifo_rde_diag),
.start_begin (start),
.wr_enable(wr_enable),
.empty_l1(empty_l1),
.empty_l2(empty_l2),
.empty_l3(empty_l3),
.empty_l4(empty_l4),
.empty_diag(empty_diag),
.running(running),
.fast_clock(fast_clock),
.slow_clock(slow_clock),
.finish(finish),
.rst(reset)
);
ukf ukf1 (
.clock(fast_clock),
.reset(reset),
.start(start),
.diag(rd_data_diag),
.lower1(rd_data_l1),
.lower2(rd_data_l2),
.lower3(rd_data_l3),
.lower4(rd_data_l4),
.matrix_size(matrix_size_out),
.parallel_units(parallel_units),
.data_in_1(data_in_1),
.data_in_2(data_in_2),
.data_in_3(data_in_3),
.data_in_4(data_in_4),
.data_in_diag(data_in_diag),
.finish(finish),
.stop_pipeline(stop_pipeline)
/*lower1_available,
lower2_available,
lower3_available,
lower4_available,
diag_out,
lower1_out,
lower2_out,
lower3_out,
lower4_out*/
);
endmodule
| 6.698517 |
modules or verilog. So as the top level, there are 6 inputs
and one output. Since I am using sturctural verilog and so I used wires.
*****************************************************************************************************************/
//module name and port lists
module top_level_USR( clk_100MHz, rst, D_in, M, SI, D, Q);
//inputs
input clk_100MHz, rst, D_in, SI;
input [1:0] M;
input [3:0] D;
//outputs
output[3:0] Q;
//name wires to connect clk_500hz, one shot and shift reg
wire w0,w1;
//clk_500hz( clk_in, rst, clk_out);
clk_500hz clk_500hz ( clk_100MHz, rst, w0);
//one_shot (clk, D_in, rst, D_out);
one_shot one_shot (w0, D_in, rst, w1);
//shift_reg4( D, clk, Q, M, SI, rst );
shift_reg4 shift_reg4( D, w1, Q, M, SI, rst );
endmodule
| 7.398612 |
module top_level (
input clk_p,
input clk_n,
input [4:0] BUTTON,
output TX
);
wire rst;
wire clkin1, clk_100, clk_10;
wire [63:0] tx_reg;
wire tx_en, tx_dv;
wire [7:0] temp;
//Input Clk buffer
IBUFGDS clkin1_buf (
.O (clkin1),
.I (clk_p),
.IB(clk_n)
);
//Clk Divider - MMCM
CLK_DIV #(
.MULTI(3.0)
) clk_div (
.clkin1(clkin1),
.rst(rst),
.clk_out_10(clk_10)
);
//Button Debouncer
DEBOUNCER #(
.DELAY(8)
) db (
.clk(clkin1),
.IN (BUTTON[0]),
.OUT(rst)
);
//Output Serial Data
UART_CTRL uart_ctrl (
.clk(clk_10),
.rst(rst),
.tx_reg(tx_reg),
.tx_en(tx_en),
.tx_busy(tx_dv),
.tx(TX)
);
//RRAM controler
RRAM_CTRL #(
.g_RRAM_INV (5), //1,3,5,7
.g_RRAM_CELLS(64)
) rram_ctrl (
.clk(clk_10),
.rst(rst),
.tx_dv(tx_dv),
.tx_en(tx_en),
.tx_reg(tx_reg)
);
endmodule
| 7.454809 |
module Top_Life #(
parameter N = 25
) (
input clk,
input nrst,
output out0
);
reg [(N*N)-1:0] seeds;
wire [(N*N)-1:0] cells;
assign out0 = cells[0];
GameOfLife #(
.N(N)
) itsmylife (
.clk (clk),
.nrst (nrst),
.seeds(seeds),
.cells(cells)
);
always @(posedge clk)
if (nrst == 0)
seeds <= 64'b01000000_00100000_11100000_00000000_00000000_00000000_00000000_00000000;
endmodule
| 7.113357 |
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1'bZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(en),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module top (
input x,
input y,
input z,
output A,
output B
);
wire A1, B1, A2, B2;
assign A1 = x & A2;
assign A2 = A1 & y;
assign A = ~A2;
endmodule
| 7.233807 |
module top_loopback (
// UART USB ports
input sys_clk_p, // 200 MHZ on SP605
input sys_clk_n, // 200 MHZ on SP605
output CTS, // I am ready to receive data
input RTS, // USB Clear to send
output TX, // Output to USB
input RX, // Input to USB
output [3:0] leds
);
wire bsys_clk; //Buffered clock
UART_LOOPBACK loopback (
// UART USB ports
.sys_clk(bsys_clk), // 200 MHZ on SP605
.CTS(CTS), // I am ready to receive data
.RTS(RTS), // USB Clear to send
.TX(TX), // Output to USB
.RX(RX), // Input to USB
.leds(leds)
);
/*
IBUFG ibufg(
.I(sys_clk),
.O(bsys_clk)
);
*/
IBUFGDS ibufgds (
.I (sys_clk_p),
.IB(sys_clk_n),
.O (bsys_clk)
);
endmodule
| 7.488194 |
module top_lora_tx (
input clk,
input rst_n,
input send_en,
input [7:0] data_rx,
output RX232,
output over_rx
);
wire bps_start_1;
bps_set_lora u_bps_set_lora (
.clk(clk),
.rst_n(rst_n),
.bps_start(bps_start_1),
.bps_clk(bps_clk)
);
uart_tx_lora u_uart_tx_lora (
.clk(clk),
.bps_clk(bps_clk),
.send_en(send_en),
.rst_n(rst_n),
.data_rx(data_rx),
.RX232(RX232),
.over_rx(over_rx),
.bps_start(bps_start_1)
);
endmodule
| 6.527265 |
module lpc_7seg (
RST, // Active Low (From PCI bus)
DISP_SEL,
DISP_LED,
LPC_CLK,
LFRAME,
LAD,
LAD_OE
);
input RST;
output [3:0] DISP_SEL;
output [6:0] DISP_LED;
input LPC_CLK;
input LFRAME;
inout [3:0] LAD;
output LAD_OE;
wire [2:0] dma_chan_i = 3'b000;
wire dma_tc_i = 1'b0;
wire [3:0] lad_i;
wire [3:0] lad_o;
wire periph_lad_oe;
assign LAD = (periph_lad_oe ? lad_o : 4'bzzzz);
assign LAD_OE = periph_lad_oe;
wire [24:0] wb_adr_o;
wire [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
wire [ 3:0] wb_sel_o;
wire wb_we_o;
wire wb_stb_o;
wire wb_cyc_o;
wire wb_ack_i;
wire wb_rty_i;
wire wb_err_i;
wire wb_int_i;
// Instantiate the module
wb_lpc_periph lpc_periph (
.clk_i(LPC_CLK),
.nrst_i(RST),
.wbm_adr_o(wb_adr_o),
.wbm_dat_o(wb_dat_o),
.wbm_dat_i(wb_dat_i),
.wbm_sel_o(wb_sel_o),
.wbm_tga_o(wb_tga_o),
.wbm_we_o(wb_we_o),
.wbm_stb_o(wb_stb_o),
.wbm_cyc_o(wb_cyc_o),
.wbm_ack_i(wb_ack_i),
.wbm_err_i(wb_err_i),
.dma_chan_o(dma_chan_i),
.dma_tc_o(dma_tc_i),
.lframe_i(~LFRAME),
.lad_i(LAD),
.lad_o(lad_o),
.lad_oe(periph_lad_oe)
);
// Instantiate the 7-Segment module
wb_7seg seven_seg0 (
.clk_i(LPC_CLK),
.nrst_i(RST),
.wb_adr_i(wb_adr_o),
.wb_dat_o(wb_dat_i),
.wb_dat_i(wb_dat_o),
.wb_sel_i(wb_sel_o),
.wb_we_i(wb_we_o),
.wb_stb_i(wb_stb_o),
.wb_cyc_i(wb_cyc_o),
.wb_ack_o(wb_ack_i),
.wb_err_o(wb_err_i),
.wb_int_o(wb_int_i),
.DISP_SEL(DISP_SEL),
.DISP_LED(DISP_LED)
);
endmodule
| 6.66142 |
module top_LPC_FPGA_AlgorithmRun (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 7.640876 |
module top_LPC_FPGA_AlgorithmStart (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 7.640876 |
module top_LPC_FPGA (
algorithm_run_export,
avmm_master_control_rm_fixed_location,
avmm_master_control_rm_read_base,
avmm_master_control_rm_read_length,
avmm_master_control_rm_go,
avmm_master_control_rm_done,
avmm_master_control_wm_fixed_location,
avmm_master_control_wm_write_base,
avmm_master_control_wm_write_length,
avmm_master_control_wm_go,
avmm_master_control_wm_done,
clk_clk,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_dm,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
oct_rzqin,
read_master_control_fixed_location,
read_master_control_read_base,
read_master_control_read_length,
read_master_control_go,
read_master_control_done,
read_master_control_early_done,
read_master_stream_read_buffer,
read_master_stream_buffer_output_data,
read_master_stream_data_available,
status_local_init_done,
status_local_cal_success,
status_local_cal_fail,
write_master_control_fixed_location,
write_master_control_write_base,
write_master_control_write_length,
write_master_control_go,
write_master_control_done,
write_master_stream_write_buffer,
write_master_stream_buffer_input_data,
write_master_stream_buffer_full
);
output algorithm_run_export;
output avmm_master_control_rm_fixed_location;
output [31:0] avmm_master_control_rm_read_base;
output [31:0] avmm_master_control_rm_read_length;
output avmm_master_control_rm_go;
input avmm_master_control_rm_done;
output avmm_master_control_wm_fixed_location;
output [31:0] avmm_master_control_wm_write_base;
output [31:0] avmm_master_control_wm_write_length;
output avmm_master_control_wm_go;
input avmm_master_control_wm_done;
input clk_clk;
output [12:0] memory_mem_a;
output [2:0] memory_mem_ba;
output [0:0] memory_mem_ck;
output [0:0] memory_mem_ck_n;
output [0:0] memory_mem_cke;
output [0:0] memory_mem_cs_n;
output [1:0] memory_mem_dm;
output [0:0] memory_mem_ras_n;
output [0:0] memory_mem_cas_n;
output [0:0] memory_mem_we_n;
output memory_mem_reset_n;
inout [15:0] memory_mem_dq;
inout [1:0] memory_mem_dqs;
inout [1:0] memory_mem_dqs_n;
output [0:0] memory_mem_odt;
input oct_rzqin;
input read_master_control_fixed_location;
input [31:0] read_master_control_read_base;
input [31:0] read_master_control_read_length;
input read_master_control_go;
output read_master_control_done;
output read_master_control_early_done;
input read_master_stream_read_buffer;
output [15:0] read_master_stream_buffer_output_data;
output read_master_stream_data_available;
output status_local_init_done;
output status_local_cal_success;
output status_local_cal_fail;
input write_master_control_fixed_location;
input [31:0] write_master_control_write_base;
input [31:0] write_master_control_write_length;
input write_master_control_go;
output write_master_control_done;
input write_master_stream_write_buffer;
input [15:0] write_master_stream_buffer_input_data;
output write_master_stream_buffer_full;
endmodule
| 6.960641 |
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