code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module priority (sel, code);
input [7:0] sel;
output [2:0] code;
reg [2:0] code;
always @(sel)
begin
if (sel[0]) code <= 3'b000;
else if (sel[1]) code <= 3'b001;
else if (sel[2]) code <= 3'b010;
else if (sel[3]) code <= 3'b011;
else if (sel[4]) code <= 3'b100;
else if (sel[5]) code <= 3'b101;
else if (sel[6]) code <= 3'b110;
else if (sel[7]) code <= 3'b111;
else code <= 3'bxxx;
end
endmodule
| 6.563494 |
module lshift (
DI,
SEL,
SO
);
input [7:0] DI;
input [1:0] SEL;
output [7:0] SO;
reg [7:0] SO;
always @(DI or SEL) begin
case (SEL)
2'b00: SO <= DI;
2'b01: SO <= DI << 1;
2'b10: SO <= DI << 3;
default: SO <= DI << 2;
endcase
end
endmodule
| 7.328798 |
module top_ADC (
input rst,
input clkp,
input clkn,
input vp,
input vn
);
wire clk200;
wire dwe, den;
wire busy, drdy, eoc, eos, jtaglocked;
wire [4:0] channel;
wire [6:0] daddr;
wire [15:0] dout, din;
wire rd, wr, valid;
wire [6:0] addr;
wire [15:0] data_out, data_in;
//---------------------------------------------------------
IBUFGDS #(
.DIFF_TERM ("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD ("DEFAULT") // Specify the input I/O standard
) buf200 (
.O (clk200),
.I (clkp),
.IB(clkn)
);
//---------------------------------------------------------
fsm_ADC fsm_adcUUT (
// User Interface
.clk (clk200),
.rst (rst),
.rd (rd),
.wr (wr),
.addr (addr),
.data_in (data_in),
.data_out (data_out),
.valid (valid),
// XADC ports
.jtaglocked(),
.busy (busy),
.drdy (drdy),
.eoc (eoc),
.eos (eos),
.channel (channel),
.dout (dout),
.dwe (dwe),
.den (den),
.daddr (daddr),
.din (din)
);
//---------------------------------------------------------
xadc_wiz_0 ADC_12bit (
.daddr_in (daddr),
.dclk_in (clk200),
.den_in (den),
.di_in (din),
.dwe_in (dwe),
.reset_in (0),
.busy_out (busy),
.channel_out (channel),
.do_out (dout),
.drdy_out (drdy),
.eoc_out (eoc),
.eos_out (eos),
.ot_out (),
.alarm_out (),
.vp_in (vp),
.vn_in (vn)
);
//------------------- Chipscope --------------------------------------
vio_0 vioUUT (
.clk (clk200), // input wire clk
.probe_in0 (valid), // input wire [0 : 0] probe_in0
.probe_in1 (data_out), // input wire [15 : 0] probe_in1
.probe_out0(wr), // output wire [1 : 0] probe_out0
.probe_out1(rd), // output wire [1 : 0] probe_out0
.probe_out2(addr), // output wire [6 : 0] probe_out1
.probe_out3(data_in) // output wire [15 : 0] probe_out2
);
endmodule
| 6.788568 |
module top_adder (
input [2:0] A,
input [2:0] B,
output [3:0] Sum
);
wire c1, c2;
fullAdder ins1 (
.A(A[0]),
.B(B[0]),
.C(1'b0),
.Sum(Sum[0]),
.Carry(c1)
);
fullAdder ins2 (
.A(A[1]),
.B(B[1]),
.C(c1),
.Sum(Sum[1]),
.Carry(c2)
);
fullAdder ins3 (
.A(A[2]),
.B(B[2]),
.C(c2),
.Sum(Sum[2]),
.Carry(Sum[3])
);
endmodule
| 6.535744 |
module dffs (
input d,
clk,
pre,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, negedge pre)
if (!pre) q <= 1'b1;
else q <= d;
endmodule
| 7.692708 |
module dffr (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
| 7.053895 |
module top_all (
clk,
miso,
mosi,
sck,
cs,
rstn
);
input clk, mosi, sck, cs, rstn;
output miso;
wire [13:0] buffer_2, buffer_3, reff, dn;
s2p s2p_0 (
.mosi(mosi),
.sck(sck),
.cs(cs),
.rstn(rstn),
.clk(clk),
.buffer_2(buffer_2),
.buffer_3(buffer_3),
.reff(reff),
.head_flag(head_flag)
);
p2s p2s_0 (
.sck(sck),
.head_flag(head_flag),
.cs(cs),
.rstn(rstn),
.clk(clk),
.in_p2s(dn),
.miso(miso)
);
alog_top alog_top (
.rstn(rstn),
.clk(clk),
.buffer_2(buffer_2),
.buffer_3(buffer_3),
.reff(reff),
.head_flag(head_flag),
.dout(dn)
);
endmodule
| 6.536052 |
module top (
input clk_25mhz,
input ftdi_txd,
output ftdi_rxd,
output [3:0] led
);
reg [5:0] reset_cnt;
wire resetn = &reset_cnt;
always @(posedge clk_25mhz) begin
reset_cnt <= reset_cnt + !resetn;
end
altair machine (
.clk(clk_25mhz),
.reset(~resetn),
.rx(ftdi_txd),
.tx(ftdi_rxd),
.led(led)
);
endmodule
| 7.233807 |
module mux2 (
S,
A,
B,
Y,
Y1
);
input S;
input A, B;
output reg Y, Y1;
always_ff @(*) Y = (S) ? B : A;
always_latch Y1 = (~S) ? B : A;
endmodule
| 7.562788 |
module top (
input [1:0] x,
input [1:0] y,
input [1:0] z,
input clk,
input A,
output reg B
);
initial begin
B = 0;
end
always @(posedge clk) begin
if (x || y && z) B <= A & z;
if (x || y && !z) B <= A | x;
end
endmodule
| 7.233807 |
module top_arch (
output wire [15:0] out,
output wire En,
input [7:0] data1,
data2,
data3,
data4,
data5,
data6,
data7,
input reset,
clk,
load
);
wire [7:0] I, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16;
wire out0,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15;
shift_reg1 M1 (
P16,
P1,
P2,
data1,
reset,
clk,
load
);
shift_reg2 M2 (
P15,
P3,
data2,
reset,
clk,
load
);
shift_reg3 M3 (
P14,
P4,
data3,
reset,
clk,
load
);
shift_reg4 M4 (
I,
P13,
P5,
En,
data4,
reset,
clk,
load
);
shift_reg3 M5 (
P12,
P6,
data5,
reset,
clk,
load
);
shift_reg2 M6 (
P11,
P7,
data6,
reset,
clk,
load
);
shift_reg1 M7 (
P10,
P9,
P8,
data7,
reset,
clk,
load
);
com C1 (
out0,
I,
P1
);
com C2 (
out1,
I,
P2
);
com C3 (
out2,
I,
P3
);
com C4 (
out3,
I,
P4
);
com C5 (
out4,
I,
P5
);
com C6 (
out5,
I,
P6
);
com C7 (
out6,
I,
P7
);
com C8 (
out7,
I,
P8
);
com C9 (
out8,
I,
P9
);
com C10 (
out9,
I,
P10
);
com C11 (
out10,
I,
P11
);
com C12 (
out11,
I,
P12
);
com C13 (
out12,
I,
P13
);
com C14 (
out13,
I,
P14
);
com C15 (
out14,
I,
P15
);
com C16 (
out15,
I,
P16
);
count S1 (
out,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7,
out8,
out9,
out10,
out11,
out12,
out13,
out14,
out15
);
endmodule
| 7.921453 |
module middle (
input x,
input y,
output o
);
assign o = x + y;
endmodule
| 6.553865 |
module top (
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
always @(posedge cin) A <= o;
assign cout = cin ? y : x;
middle u_mid1 (
.x(x),
.A(o),
.y(1'b0)
);
middle u_mid2 (
.x(x),
.A(o),
.y(1'b1)
);
middle u_mid3 (
.x(x),
.A(o),
.y(1'bX)
);
middle u_mid4 (
.x(x),
.A(o),
.y(1'bX)
);
endmodule
| 7.233807 |
module adff (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
| 7.089232 |
module adffn (
input d,
clk,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
| 7.422273 |
module dffe (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
| 7.085902 |
module dffsr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk, posedge pre, posedge clr)
if (clr) q <= 1'b0;
else if (pre) q <= 1'b1;
else q <= d;
endmodule
| 6.804969 |
module ndffnsnr (
input d,
clk,
pre,
clr,
output reg q
);
initial begin
q = 0;
end
always @(negedge clk, negedge pre, negedge clr)
if (!clr) q <= 1'b0;
else if (!pre) q <= 1'b1;
else q <= d;
endmodule
| 7.273757 |
module top (
input clk,
input clr,
input pre,
input a,
output b,
b1,
b2,
b3,
b4
);
dffsr u_dffsr (
.clk(clk),
.clr(1'b1),
.pre(pre),
.d (1'b0),
.q (b)
);
ndffnsnr u_ndffnsnr (
.clk(clk),
.clr(clr),
.pre(1'b0),
.d (1'b0),
.q (b1)
);
adff u_adff (
.clk(clk),
.clr(1'b1),
.d (1'b0),
.q (b2)
);
adffn u_adffn (
.clk(clk),
.clr(1'b1),
.d (a),
.q (b3)
);
dffe u_dffe (
.clk(clk),
.en (clr),
.d (1'b0),
.q (b4)
);
endmodule
| 7.233807 |
module top_async_fifo #(
parameter DATAIN_WIDTH = 10'd16, //input data's width, must equel to RAM's width
parameter DATAOUT_WIDTH = 10'd32 //output data's width
) (
input w_clk,
r_clk,
input w_rst,
r_rst,
input w_en,
r_en,
input [DATAIN_WIDTH-1:0] data_write,
output flag_full,
output flag_empty,
output [DATAOUT_WIDTH-1:0] data_read
);
localparam FIFO_WIDTH = DATAIN_WIDTH; //define the width of RAM, must equel to input data's width
localparam FIFO_DEPTH = 8 * DATAIN_WIDTH; //define the depth of RAM
localparam FIFO_WIDTH_BIT = $clog2(FIFO_WIDTH); //get bits of RAM's width, though function clog2
localparam FIFO_DEPTH_BIT = $clog2(FIFO_DEPTH); //get bits of RAM's depth
wire [FIFO_DEPTH_BIT-1:0] write_addr, read_addr;
wire [FIFO_DEPTH_BIT:0] write_addr_gray, read_addr_gray;
wire [FIFO_DEPTH_BIT:0] write_addr_gray_sync, read_addr_gray_sync;
ram #(
.DATAIN_WIDTH (DATAIN_WIDTH),
.DATAOUT_WIDTH (DATAOUT_WIDTH),
.FIFO_WIDTH (FIFO_WIDTH),
.FIFO_WIDTH_BIT(FIFO_WIDTH_BIT),
.FIFO_DEPTH (FIFO_DEPTH),
.FIFO_DEPTH_BIT(FIFO_DEPTH_BIT)
) inst_ram (
.w_clk (w_clk), //input
.r_clk (r_clk),
.w_rst (w_rst),
.r_rst (r_rst),
.w_en (w_en),
.r_en (r_en),
.flag_full (flag_full),
.flag_empty(flag_empty),
.write_addr(write_addr),
.read_addr (read_addr),
.data_write(data_write),
.data_read(data_read) //output
);
write_full #(
.FIFO_DEPTH_BIT(FIFO_DEPTH_BIT)
) inst_write_full (
.w_clk (w_clk), //input
.w_rst (w_rst),
.w_en (w_en),
.read_addr_gray_sync(read_addr_gray_sync),
.write_addr_gray (write_addr_gray),
.write_addr(write_addr), //output
.flag_full (flag_full)
);
read_empty #(
.DATAIN_WIDTH (DATAIN_WIDTH),
.DATAOUT_WIDTH (DATAOUT_WIDTH),
.FIFO_DEPTH_BIT(FIFO_DEPTH_BIT)
) inst_read_empty (
.r_clk (r_clk), //input
.r_rst (r_rst),
.r_en (r_en),
.write_addr_gray_sync(write_addr_gray_sync),
.read_addr_gray (read_addr_gray),
.read_addr (read_addr), //output
.flag_empty(flag_empty)
);
sync_addr_gray #(
.FIFO_DEPTH_BIT(FIFO_DEPTH_BIT)
) inst_sync_addr_gray (
.w_clk (w_clk), //input
.r_clk (r_clk),
.w_rst (w_rst),
.r_rst (r_rst),
.write_addr_gray(write_addr_gray),
.read_addr_gray (read_addr_gray),
.write_addr_gray_sync(write_addr_gray_sync), //output
.read_addr_gray_sync (read_addr_gray_sync)
);
endmodule
| 8.11541 |
module mux2 (
S,
A,
B,
Y
);
input S;
input A, B;
output reg Y;
always @(*) Y = (S) ? B : A;
endmodule
| 7.562788 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
task automatic do_things;
input [31:0] number_of_things;
reg [31:0] tmp_thing;
endtask
endmodule
| 7.233807 |
module top_a_e115fb (
input clk,
input ext_rst_n,
output reg [3:0] led_n
);
`include "macros/direction.vh"
reg [2:0] int_rst_cnt = 0;
always @(posedge clk) begin
if (int_rst_cnt != 3'b111) int_rst_cnt <= int_rst_cnt + 1;
end
wire int_rst_n = int_rst_cnt == 3'b111;
wire rst_n = int_rst_n & ext_rst_n;
wire i_req;
wire [15:0] i_addr;
wire i_ack;
wire [7:0] i_rdata;
wire d_req;
wire d_dir;
wire [7:0] d_addr;
wire [7:0] d_wdata;
wire d_ack;
wire [7:0] d_rdata;
wire io_req;
wire io_dir;
wire [7:0] io_wdata;
reg io_ack;
reg [7:0] io_rdata;
bfcpu cpu (
.clk (clk),
.rst_n(rst_n),
.i_req (i_req),
.i_addr (i_addr),
.i_ack (i_ack),
.i_rdata(i_rdata),
.d_req (d_req),
.d_dir (d_dir),
.d_addr (d_addr),
.d_wdata(d_wdata),
.d_ack (d_ack),
.d_rdata(d_rdata),
.io_req (io_req),
.io_dir (io_dir),
.io_wdata(io_wdata),
.io_ack (io_ack),
.io_rdata(io_rdata)
);
i_mem_a_e115fb im (
.clk(clk),
.i_req (i_req),
.i_addr (i_addr),
.i_ack (i_ack),
.i_rdata(i_rdata)
);
d_mem_a_e115fb dm (
.clk(clk),
.d_req (d_req),
.d_dir (d_dir),
.d_addr (d_addr),
.d_wdata(d_wdata),
.d_ack (d_ack),
.d_rdata(d_rdata)
);
always @(posedge clk) begin
if (!rst_n) begin
led_n <= 4'b1111;
io_ack <= 0;
end else begin
if (io_req) begin
io_ack <= 1;
if (io_dir == `DIRECTION_WRITE) led_n <= ~io_wdata[3:0];
else io_rdata <= {4'b0, ~led_n};
end else begin
io_ack <= 0;
end
end
end
endmodule
| 7.328185 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'BASIC_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
fir_cosim fir0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/BASIC_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
`ifdef ioConfig_PIN
$dumpvars( 0, fir0.clk );
$dumpvars( 0, fir0.rst );
$dumpvars( 0, fir0.coeffs_table_0 );
$dumpvars( 0, fir0.coeffs_table_1 );
$dumpvars( 0, fir0.coeffs_table_2 );
$dumpvars( 0, fir0.coeffs_table_3 );
$dumpvars( 0, fir0.coeffs_table_4 );
$dumpvars( 0, fir0.coeffs_table_5 );
$dumpvars( 0, fir0.coeffs_table_6 );
$dumpvars( 0, fir0.coeffs_table_7 );
$dumpvars( 0, fir0.din_busy );
$dumpvars( 0, fir0.din_vld );
$dumpvars( 0, fir0.din_data );
$dumpvars( 0, fir0.dout_busy );
$dumpvars( 0, fir0.dout_vld );
$dumpvars( 0, fir0.dout_data );
`endif
$dumpvars( 4, fir0.fir0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/BASIC_V/sim_BASIC_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module top (
input [15:0] data,
input [2:0] load, //{opcode,y,x}
input clk,
input reset,
output [3:0] anode,
output [6:0] seg,
output [15:0] leds_out
);
wire [15:0] alu_out;
wire [15:0] display_out;
assign leds_out = alu_out;
assign display_out = alu_out;
top_data_alu alu (
.data(data),
//.push(push),
.reset(reset),
.load(load),
.alu_out(alu_out)
//.zr(zr),
//.ng(ng)
);
top_bcd bcd (
.number(alu_out[12:0]),
.reset(reset),
.clk(clk),
.anode(anode),
.seg(seg)
);
endmodule
| 7.233807 |
module top_bitmap_gen (
input clk,
rst_n,
input [3:0] key,
output [4:0] vga_out_r,
output [5:0] vga_out_g,
output [4:0] vga_out_b,
output vga_out_vs,
vga_out_hs
);
wire clk_out;
wire video_on;
wire [11:0] pixel_x, pixel_y;
dcm_25MHz m0 ( // Clock in ports
.clk (clk), // IN
// Clock out ports
.clk_out(clk_out), // OUT
// Status and control signals
.RESET (RESET), // IN
.LOCKED (LOCKED)
);
vga_core m1 (
.clk(clk_out),
.rst_n(rst_n), //clock must be 25MHz for 640x480
.hsync(vga_out_hs),
.vsync(vga_out_vs),
.video_on(video_on),
.pixel_x(pixel_x),
.pixel_y(pixel_y)
);
bitmap_gen m2 (
.clk(clk_out),
.rst_n(rst_n),
.key(key),
.video_on(video_on),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.vga_out_r(vga_out_r),
.vga_out_g(vga_out_g),
.vga_out_b(vga_out_b)
);
endmodule
| 7.162416 |
module top_bizhng (
clk,
rst,
echo,
trig,
dianji2,
flag,
echo2,
trig2,
data_rx,
RX232,
led1,
led0,
jiaodu,
led4,
led5,
led6,
led7,
flag1
);
input clk;
input rst;
input echo;
input echo2;
input flag;
input data_rx;
output RX232;
output [9:0] jiaodu;
output trig;
output trig2;
output led1;
output led0;
output led7;
output led6;
output led5;
output led4;
output [1:0] dianji2;
output flag1;
wire [9:0] jiaodu;
wire [9:0] jiaodu1;
wire [9:0] hq;
wire [9:0] hz;
wire rst;
bizhang bi (
.clk(clk),
.rst(rst),
.hq(hq),
.hz(hz),
.jiaodu(jiaodu),
.dianji2(dianji2),
.led7(led7),
.led6(led6),
.led5(led5),
.led4(led4),
.jiaodu1(jiaodu1),
.flag1(flag1)
);
top2 st (
.clk(clk),
.rst_n(rst),
.echo2(echo2),
.trig2(trig2),
.led0(led0),
.hz(hz)
);
top to (
.clk(clk),
.rst_n(rst),
.echo(echo),
.trig(trig),
.led1(led1),
.hq(hq)
);
/*top_gy_26 na (
.flag(flag),
.clk(clk),
.rst_n(rst),
.data_rx(data_rx),
.RX232(RX232),
.jiaodu(jiaodu)
);*/
top_gy_26 na (
.flag(flag),
.clk(clk),
.rst(rst),
.data_rx(data_rx),
.jiaodu(jiaodu),
.RX232(RX232)
);
endmodule
| 6.592085 |
module top_blackice2 (
input wire clk100,
output wire [ 3:0] LED,
output wire UART_TX,
input wire UART_RX,
output wire RAMOE,
output wire RAMWE,
output wire RAMCS, // SRAM pins
output wire RAMLB,
output wire RAMUB,
output [17:0] ADR,
input [15:0] DAT,
input wire QSPICSN,
input wire QSPICK, // QUAD SPI pins
output wire [ 3:0] QSPIDQ,
input wire B1, // buttons
input wire B2,
input wire GRESET,
input wire DONE,
input wire DIG16, // These are normally high
input wire DIG17,
input wire DIG18,
input wire DIG19,
output wire [ 3:0] red,
output wire [ 3:0] green,
output wire [ 3:0] blue,
output wire hsync,
output wire vsync,
output wire PMOD5_1,
output wire PMOD5_2,
output wire PMOD5_3,
output wire PMOD5_4,
output wire PMOD6_1,
output wire PMOD6_2,
output wire PMOD6_3,
output wire PMOD6_4,
input wire ps2_clk,
input wire ps2_data
);
// not used
assign QSPIDQ[3:0] = {4{1'b0}}; // {4{1'bz}};
//-------------------------------------------------------------------
wire clk;
pll _pll (
.clock_in (clk100),
.clock_out(clk)
);
// Yosys can't handle bidirectional pins directly, need to handle them differently.
wire [15:0] sram_pins_din;
wire [15:0] sram_pins_dout;
wire sram_pins_drive;
// Yosys component
SB_IO #(
.PIN_TYPE(6'b1010_01),
) sram_data_pins[15:0] (
.PACKAGE_PIN(DAT),
.OUTPUT_ENABLE(sram_pins_drive),
.D_OUT_0(sram_pins_dout),
.D_IN_0(sram_pins_din)
);
// Serial port assignments begin
wire serloader_rx = UART_RX; // all incoming traffic goes to serloader
wire serloader_tx;
wire tms9902_rx = (DIG19 == 1'b1) ? UART_RX : 1'b1; // if DIG19 is low, the UART receive is disabled
wire tms9902_tx;
assign UART_TX = (DIG19 == 1'b1) ? tms9902_tx : serloader_tx;
// Serial port assignments end
wire vde;
wire pin_cs, pin_sdin, pin_sclk, pin_d_cn, pin_resn, pin_vccen, pin_pmoden;
wire [22:0] sys_addr;
assign ADR = sys_addr[17:0];
sys ti994a (
.clk(clk),
.LED(LED),
.tms9902_tx(tms9902_tx),
.tms9902_rx(tms9902_rx),
.RAMOE(RAMOE),
.RAMWE(RAMWE),
.RAMCS(RAMCS),
.RAMLB(RAMLB),
.RAMUB(RAMUB),
.ADR(sys_addr),
.sram_pins_din(sram_pins_din),
.sram_pins_dout(sram_pins_dout),
.sram_pins_drive(sram_pins_drive),
.memory_busy(1'b0),
.use_memory_busy(1'b0),
.red(red),
.green(green),
.blue(blue),
.hsync(hsync),
.vsync(vsync),
.cpu_reset_switch_n(DIG18),
`ifdef LCD_SUPPORT
// LCD signals
.pin_cs(pin_cs),
.pin_sdin(pin_sdin),
.pin_sclk(pin_sclk),
.pin_d_cn(pin_d_cn),
.pin_resn(pin_resn),
.pin_vccen(pin_vccen),
.pin_pmoden(pin_pmoden),
`endif
.serloader_tx(serloader_tx),
.serloader_rx(serloader_rx), // bootloader UART
.vde(vde), // Video display enable (active area)
.ps2clk(ps2_clk),
.ps2dat(ps2_data)
);
`ifdef LCD_SUPPORT
assign PMOD5_1 = pin_cs;
assign PMOD5_2 = pin_sdin;
assign PMOD5_3 = 1'b0;
assign PMOD5_4 = pin_sclk;
assign PMOD6_1 = pin_d_cn;
assign PMOD6_2 = pin_resn;
assign PMOD6_3 = pin_vccen;
assign PMOD6_4 = pin_pmoden;
`endif
endmodule
| 7.049922 |
module top_blk #(
parameter KERNEL_SIZE = `KERNEL_SIZE,
parameter FM_SIZE = `FM_SIZE,
parameter PADDING = `PADDING,
parameter STRIDE = `STRIDE,
parameter MAXPOOL = `MAXPOOL,
parameter IN_FM_CH = `IN_FM_CH,
parameter OUT_FM_CH = `OUT_FM_CH,
localparam OUT_SIZE = ((FM_SIZE - KERNEL_SIZE + 2 * PADDING) / STRIDE) + 1
) (
input wire i_clk,
input wire i_rst,
input wire i_go,
input wire i_fm_data,
input wire i_weight_data,
output reg w_o_conv_blk,
output reg o_done
);
/*reg signed [30-1:0] FM_data [0:(FM_SIZE*FM_SIZE)-1];
reg signed [30-1:0] i_fm_data;
reg signed [18-1:0] KERNEL_data [0:(KERNEL_SIZE*KERNEL_SIZE)-1];
reg signed [(KERNEL_SIZE**2)*18-1:0] i_weight_data;*/
//tb manda sinal para começar
//este top.v está ligado a brams e lê os dados depois de receber o sinal anterior
//a partir daí ele controla quando dá o go para o conv_blk
/*conv_blk #(
.KERNEL_SIZE(KERNEL_SIZE),
.FM_SIZE(FM_SIZE),
.PADDING(PADDING),
.STRIDE(STRIDE),
.MAXPOOL(MAXPOOL)
)convolutional_block(
.i_clk(i_clk),
.i_rst(i_rst),
.i_go(i_go),
.i_fm_data(i_fm_data),
.i_weight_data(i_weight_data),
.o_en(w_o_en),
.o_conv_result(w_o_conv_blk)
);*/
endmodule
| 7.692328 |
module top_white_block_mean (
input clk,
input rstn,
input de,
input hs,
input vs,
input [7:0] rgb_r,
input [7:0] rgb_g,
input [7:0] rgb_b,
output [7:0] block_mean_white,
output data_vaild_white,
output [5:0] block_v_cnt
);
// RGB to Gray convert module
// rgb_to_gray Outputs
wire [7:0] gray_o;
wire hs_o;
wire vs_o;
wire de_o;
rgb_to_gray u_rgb_to_gray (
.rstn (rstn),
.rgb_i ({rgb_r, rgb_g, rgb_b}),
.pclk_i(clk),
.hs_i (hs),
.vs_i (vs),
.de_i (de),
.gray_o(gray_o),
.hs_o (hs_o),
.vs_o (vs_o),
.de_o (de_o)
);
//pixel counter instantiation
// video_pixel_counter Outputs
wire [10:0] p_cnt;
wire [10:0] line_cnt;
wire de_o_cnt;
wire [ 5:0] block_h_cnt;
// wire [5:0] block_v_cnt;
wire [ 5:0] inblock_line_cnt;
video_pixel_counter u_video_pixel_counter (
.pclk(clk),
.rstn(rstn),
.de (de_o),
.hs (hs_o),
.vs (vs_o),
.p_cnt (p_cnt),
.line_cnt (line_cnt),
.de_o (de_o_cnt),
.block_h_cnt (block_h_cnt),
.block_v_cnt (block_v_cnt),
.inblock_line_cnt(inblock_line_cnt)
);
// white block mean cal module
wire [7:0] block_mean_i;
wire data_valid_i;
block_mean u_block_mean_white (
.clk (clk),
.rstn (rstn),
.de (de_o_cnt),
.hs (hs_o),
.vs (vs_o),
.block_x (block_h_cnt),
.block_y (block_v_cnt),
.inblock_line(inblock_line_cnt),
.gray (gray_o),
.block_mean(block_mean_i),
.data_vaild(data_vaild_i)
);
// gamma fix module
gamma_fix_2_2_top u_gamma_fix_2_2_top (
.clk (clk),
.rstn (rstn),
.block_mean_i(block_mean_i),
.data_valid_i(data_vaild_i),
.block_mean_fixed_o(block_mean_white),
.data_valid_o (data_vaild_white)
);
endmodule
| 8.173112 |
module to instantiate the datapath and controller
// of BOOTH MULTIPLIER
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_BOOTH(
output wire done,
output wire [15:0] MUL_result,
//in1 is multiplicand
input wire [7:0] data_in1,
//in2 is multiplier
input wire [7:0] data_in2,
input wire start,
//input wire rstn,
input wire clk
);
//this wire is a hack to solve to problem of
//wire driving the other module wire.
//wire [13:0] datapath2top;
wire LdA, clrA, sftA,
LdQ, clrQ, sftQ,
clrff, sftDff,
LdM, clrM,
q0, qm1,
LdCount, decr,
add_sub, EnableALU,
eqz;
datapath_BOOTH DAT(
.eqz(eqz),
.LdA(LdA),
.clrA(clrA),
.sftA(sftA),
.LdQ(LdQ),
.clrQ(clrQ),
.sftQ(sftQ),
.LdM(LdM),
.clrM(clrM),
.clrff(clrff),
.sftDff(sftDff),
.add_sub(add_sub),
.EnableALU(EnableALU),
.q0(q0),
.qm1(qm1),
.LdCount(LdCount),
.decr(decr),
//multiplicand
.data_in1(data_in1),
//multiplier
.data_in2(data_in2),
.data_out(MUL_result),
.clk(clk)
);
//concept wise a reg should drive the other module wire.
//but this is a hack.
//assign MUL_result= datapath2top;
controller_BOOTH CTRL(
.eqz(eqz),
.LdA(LdA),
.clrA(clrA),
.sftA(sftA),
.LdQ(LdQ),
.clrQ(clrQ),
.sftQ(sftQ),
.LdM(LdM),
.clrM(clrM),
.clrff(clrff),
.sftDff(sftDff),
.add_sub(add_sub),
.EnableALU(EnableALU),
.q0(q0),
.qm1(qm1),
.LdCount(LdCount),
.decr(decr),
.start(start),
.done(done),
//.rstn(rstn),
.clk(clk)
);
endmodule
| 7.261131 |
module TOP_BUS_ARB (
//Common I/O
input wire RST,
CLK,
input wire HREADY,
//Arbiter I/O
input wire HLOCK_1,
HLOCK_2,
input wire HREQ_1,
HREQ_2,
input wire [1:0] HSPLIT,
output wire HGRANT_1,
HGRANT_2,
output wire [1:0] HMAS,
output wire MLOCK,
//BUS I/O
input wire [15:0] HADDR_1,
HADDR_2,
input wire [31:0] HWDATA_1,
HWDATA_2,
input wire [31:0] HRDATA_1,
HRDATA_2,
input wire [31:0] HRDATA_3,
input wire [ 1:0] HRESP_1,
HRESP_2,
HRESP_3,
output wire [31:0] HWDATA,
output wire [31:0] HRDATA,
output wire [15:0] HADDR,
output wire [1:0] HRESP,
output wire SEL_1,
SEL_2,
SEL_3,
//Blank wire
output wire AB
);
wire [1:0] SEL;
Arbiter Arbiter (
.CLK(CLK),
.RST(RST),
.HLOCK_1(HLOCK_1),
.HLOCK_2(HLOCK_2),
.HREQ_1(HREQ_1),
.HREQ_2(HREQ_2),
.HRESP(HRESP),
.HSPLIT(HSPLIT),
.SEL(SEL),
.HMAS(HMAS),
.HGRANT_1(HGRANT_1),
.HGRANT_2(HGRANT_2),
.MLOCK(MLOCK),
.AB(AB),
.HREADY(HREADY)
);
BUS BUS (
.CLK(CLK),
.RST(RST),
.SEL(SEL),
.HADDR_1(HADDR_1),
.HADDR_2(HADDR_2),
.HADDR(HADDR),
.HWDATA_1(HWDATA_1),
.HWDATA_2(HWDATA_2),
.HWDATA(HWDATA),
.HRDATA_1(HRDATA_1),
.HRDATA_2(HRDATA_2),
.HRDATA_3(HRDATA_3),
.HRDATA(HRDATA),
.HRESP_1(HRESP_1),
.HRESP_2(HRESP_2),
.HRESP_3(HRESP_3),
.HRESP(HRESP),
.SEL_1(SEL_1),
.SEL_2(SEL_2),
.SEL_3(SEL_3),
.AB(AB)
);
endmodule
| 7.687923 |
module top_button (
btn_in,
clk,
rst_n,
p_out
);
//This is the wrapper or top module for push button it includes synchronizer debouncer and level 2 pulse convertor
input btn_in, clk, rst_n;
output p_out;
wire b_w, db_w;
synchronizer Sync1 (
.async_in(btn_in),
.clk(clk),
.rst_n(rst_n),
.sync_out(b_w)
);
top_debounce Debounce1 (
.bounce_in(b_w),
.clk(clk),
.rst_n(rst_n),
.debounce_out(db_w)
);
lev_puls_conv L2P_1 (
.clk(clk),
.rst_n(rst_n),
.level_in(db_w),
.pulse_out(p_out)
);
endmodule
| 8.82249 |
module top_calling (
input clk,
input rst_n,
input calling_sent_en_cheng, //打电话使能，连接按键
input calling_sent_en_zhi, //第二个紧急联系人
output calling_tx
);
wire bps_sig;
wire cnt_start;
wire rx_int;
wire [ 7:0] data1;
wire [47:0] ymr_out;
wire [47:0] time_out;
wire calling_sent_en_1;
assign calling_sent_en_1 = ~calling_sent_en_cheng;
assign calling_sent_en_2 = ~calling_sent_en_zhi;
reg tx_enable;
reg [7:0] tx_data;
wire bps_sig_tx;
wire tx_done;
wire [7:0] tx_data2;
wire tx_enable1;
wire tx_enable2;
wire tx_enable3;
wire tx_enable4;
wire [7:0] tx_data1;
wire bps_sig_ring;
wire cnt_start_ring;
uart_receive u1_uart_receive (
.clk(clk),
.rst_n(rst_n),
.clk_bps(bps_sig),
.data_rx(data_rx),
.rx_int(rx_int),
.data_tx(data1),
.bps_start(cnt_start)
);
uart_bps u11_uart_bps (
.clk(clk),
.rst_n(rst_n),
.cnt_start(cnt_start),
.bps_sig(bps_sig)
);
pick_up_rx u2_pick_up_rx (
.clk(clk),
.rst_n(rst_n),
.data_rx(data1),
.rx_int(rx_int),
.data_rx_end(data_rx_end),
.time_out(time_out),
.ymr_out(ymr_out)
);
uart_bps mess_u1_uart_bps (
.clk(clk),
.rst_n(rst_n),
.cnt_start(cnt_start_ring),
.bps_sig(bps_sig_ring)
);
//打电话
calling mess_u5_calling (
.tx_enable(tx_enable2),
.tx_data(tx_data2),
.clk(clk),
.rst(rst_n),
.tx_done(tx_done),
.calling_sent_enable_1(calling_sent_en_1),
.calling_sent_enable_2(calling_sent_en_2)
);
uart_bps_mess u2_uart_bps_mess (
.clk(clk),
.rst_n(rst_n),
.bps_sig(bps_sig_tx),
.cnt_start(tx_enable2)
);
uart_sentdata_mess u3_uart_sentdata_mess (
.clk(clk),
.rst(rst_n),
.bps_sig(bps_sig_tx),
.tx_data(tx_data2),
.tx(calling_tx),
.tx_enable(tx_enable2),
.tx_done(tx_done)
);
endmodule
| 6.664888 |
module top (
input x0,
x1,
input y0,
y1,
input cin,
output A0,
A1,
output cout
);
wire cout0;
assign {cout0, A0} = cin + y0 + x0;
assign {cout, A1} = cout0 + y1 + x1;
endmodule
| 7.233807 |
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) begin
case (en)
1: o <= i;
default: o <= 1'bZ;
endcase
end
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(en),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module mux2 (
S,
A,
B,
Y
);
input S;
input A, B;
output reg Y;
always @(*) Y = (S) ? B : A;
endmodule
| 7.562788 |
module mux8 (
S,
D,
Y
);
input [2:0] S;
input [7:0] D;
output Y;
reg Y;
wire [2:0] S;
wire [7:0] D;
always @* begin
casex (S)
0: Y = D[0];
1: Y = D[1];
2: Y = D[2];
3: Y = D[3];
4: Y = D[4];
5: Y = D[5];
6: Y = D[6];
7: Y = D[7];
endcase
end
endmodule
| 7.239309 |
module mux16 (
D,
S,
Y
);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
| 8.26373 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
mux2 u_mux2 (
.S(S[0]),
.A(D[0]),
.B(D[1]),
.Y(M2)
);
mux4 u_mux4 (
.S(S[1:0]),
.D(D[3:0]),
.Y(M4)
);
mux8 u_mux8 (
.S(S[2:0]),
.D(D[7:0]),
.Y(M8)
);
mux16 u_mux16 (
.S(S[3:0]),
.D(D[15:0]),
.Y(M16)
);
endmodule
| 7.233807 |
module top_checkered (
input wire clk_25mhz,
output wire oled_csn,
output wire oled_clk,
output wire oled_mosi,
output wire oled_dc,
output wire oled_resn
);
// checkered red green blue red green blue
wire [15:0] color = x[3] ^ y[3] ? {5'd0, x[6:1], 5'd0} : {y[5:1], 6'd0, 5'd0};
wire [6:0] x, y;
/* 0.95inch oled SSD1331, resolution 96 x 64 */
oled_video #(
.C_init_file("oled_init_16bit.mem"),
.C_init_size(44)
) oled_video_inst (
.clk(clk_25mhz),
.x(x),
.y(y),
.color(color),
.oled_csn(oled_csn),
.oled_clk(oled_clk),
.oled_mosi(oled_mosi),
.oled_dc(oled_dc),
.oled_resn(oled_resn)
);
endmodule
| 6.561331 |
module top_clock (
rst,
inclk,
sec_seg1,
sec_seg10,
min_seg1,
min_seg10,
hour_seg1,
hour_seg10
);
input rst, inclk;
output wire [6:0] sec_seg1, sec_seg10;
output wire [6:0] min_seg1, min_seg10;
output wire [6:0] hour_seg1, hour_seg10;
wire sec_clk, min_clk, hour_clk;
freq_div freq_ (
rst,
inclk,
sec_clk,
min_clk,
hour_clk
);
top_secseg second_seg (
rst,
sec_clk,
sec_seg1,
sec_seg10
);
top_minseg minute_seg (
rst,
min_clk,
min_seg1,
min_seg10
);
top_hourseg hour_seg (
rst,
hour_clk,
hour_seg1,
hour_seg10
);
endmodule
| 7.457114 |
module mux16 (
D,
S,
Y
);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
| 8.26373 |
module top (
input [3:0] S,
input [15:0] D,
output M16
);
mux16 u_mux16 (
.S(S[3:0]),
.D(D[15:0]),
.Y(M16)
);
endmodule
| 7.233807 |
module top_color (
input clk,
output reg s2,
output reg s3,
output reg [2:0] color,
input ip_signal
);
wire [7:0] count;
reg [2:0] color_temp;
freq_counter(
.clk(clk), .ip_signal(ip_signal), .count(count)
);
reg [7:0] r_freq;
reg [7:0] g_freq;
reg [7:0] b_freq;
reg [32:0] delay = 0;
integer state = 1;
integer next_state = 2;
initial begin
s2 = 0;
s3 = 0;
end
always @(posedge clk) begin
case (state)
1: ////delay
begin
delay = delay + 1;
if (delay == 'd5000000) begin
delay = 0;
state = next_state;
end
end
2: begin
r_freq[7:0] <= count[7:0];
s2 = 0;
s3 = 1;
next_state = 3;
state = 1;
end
3: begin
b_freq[7:0] <= count[7:0];
s2 = 1;
s3 = 1;
next_state = 4;
state = 1;
end
4: begin
g_freq[7:0] <= count[7:0];
s2 = 0;
s3 = 0;
next_state = 5;
state = 1;
end
5: begin
if (r_freq < g_freq) begin
if (r_freq < b_freq) color_temp = 'b100;
else color = 'b001;
end else begin
if (g_freq < b_freq) color_temp = 'b010;
else color_temp = 'b001;
end
state = 1;
next_state = 6;
end
6: begin
color = color_temp;
state = 1;
next_state = 2;
end
endcase
end
endmodule
| 6.57371 |
module top (
input clk,
input [15:0] I0,
input [15:0] I1,
output reg A,
B,
C,
D,
E,
F
);
always @(posedge clk) begin
if (I0 < I1) A <= 1'b1;
else A <= 1'b0;
if (I0 <= I1) B <= 1'b1;
else B <= 1'b0;
if (I0 != I1) C <= 1'b1;
else C <= 1'b0;
if (I0 === I1) D <= 1'b1;
else D <= 1'b0;
if (I0 !== I1) E <= 1'b1;
else E <= 1'b0;
if (I0 >= I1) F <= 1'b1;
else F <= 1'b0;
end
endmodule
| 7.233807 |
module top (
input [7:0] data_a,
data_b,
input [0:0] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clka,
clkb,
output reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @(posedge clka) begin
if (we_a) begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b) begin
q_a <= ram[addr_a];
end
end
// Port B
always @(posedge clkb) begin
if (we_b) begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b) begin
q_b <= ram[addr_b];
end
end
endmodule
| 7.233807 |
module top (
input x,
input [1:0] y,
input z,
output [1:0] A,
output [2:0] B,
output [3:0] C
);
assign A = {x, z};
assign B = {x, y};
assign C = {x, y, z};
endmodule
| 7.233807 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
reg b, c = 1.01;
wire a;
endmodule
| 7.233807 |
module replication_operator ();
reg [3:0] r_VAL_1 = 4'b0111;
parameter c_MULTIPLIER = 4'b0010;
parameter WIDTH = 1;
wire [WIDTH-1:0] connection;
generate
if (WIDTH > 1) begin
assign connection = {{WIDTH - 1{1'b0}}, 1'b1};
end else begin
assign connection = 1'b1;
end
endgenerate
endmodule
| 6.74185 |
module Shift (
A,
Y1,
Y2
);
input [7:0] A;
output [7:0] Y1, Y2;
parameter B = 3;
reg [7:0] Y1, Y2;
always @(A) begin
Y1 = A << B; //logical shift left
Y2 = A >> B; //logical shift right
end
endmodule
| 6.947224 |
module SShift (
A,
Y1,
Y2
);
input [7:0] A;
output [7:0] Y1, Y2;
parameter B = 3;
reg [7:0] Y1, Y2;
always @(A) begin
Y1 = A <<< B; //logical shift left
Y2 = A >>> B; //logical shift right
end
endmodule
| 7.020674 |
module top (
input signed x,
input signed [1:0] y,
input signed z,
output signed [1:0] A,
output signed [2:0] B,
output signed [3:0] C
);
assign A = {x, z};
assign B = {x, y};
assign C = {x, y, z};
endmodule
| 7.233807 |
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1'bZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(1'b0),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1'bZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(1'b1),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module tristate (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1'bZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(en),
.i (1'b0),
.o (b)
);
endmodule
| 7.233807 |
module top (
input x,
input y,
input cin,
output reg A,
output reg cout,
output X
);
wire bb_out;
initial begin
A = 0;
cout = 0;
end
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
assign X = 1'bX;
bb ubb (
cin,
y,
x,
bb_out
);
endmodule
| 7.233807 |
module top_control (
input clk,
input rst,
// is selecting
input selecting,
// game
input mode,
output reg timer_start,
output reg countdown_en,
// supervise
input [9:0] sec,
input win,
output reg timed_win,
// end
output reg timer_endn,
output reg [1:0] mask_enable,
output reg game_rst
);
reg [1:0] i;
always @(posedge clk or negedge rst) begin
if (!rst) begin
i <= `START;
end else begin
case (i)
`SELECT: begin
// draw selecting mask
mask_enable <= 1'b1;
// hold timer
timer_start <= 1'b0;
timer_endn <= 1'b0;
// rst
game_rst <= 1'b0;
timed_win <= 1'b0;
// hold cnt
countdown_en <= 1'b0;
// change when exiting selecting
if (selecting == 1'b0) begin
i <= `START;
end
end
`START: begin
// start timing
timer_start <= 1'b1;
timer_endn <= 1'b0;
// disable mask
mask_enable <= 1'b0;
// diable rst
game_rst <= 1'b1;
// not win
timed_win <= 1'b0;
// enable cnt
countdown_en <= 1'b1;
// if enter selecting again
if (selecting == 1'b1) begin
i <= `SELECT;
end
if (win == 1'b1 || (mode == `LIMITED && sec >= `LIMITED_TIME)) begin
i <= `END;
// if win
if (win == 1'b1) begin
timed_win <= 1'b1;
end // if not win in limited time
else begin
timed_win <= 1'b0;
end
end
end
`END: begin
// hold timer result
timer_endn <= 1'b1;
timer_start <= 1'b1;
// draw end mask
mask_enable <= 2'd2;
// hold rst
game_rst <= 1'b1;
// stop cnt
countdown_en <= 1'b0;
// if enter selecting
if (selecting == 1'b1) begin
i <= `SELECT;
end
end
endcase
end
end
endmodule
| 7.478001 |
module top_conv (
clk,
in,
filter,
out
);
input clk;
input [49:0] in;
input [17:0] filter;
output [17:0] out;
mac_new mac1 (
clk,
{in[25:20], in[15:10], in[5:0]},
filter,
out[1:0]
);
mac_new mac2 (
clk,
{in[27:22], in[17:12], in[7:2]},
filter,
out[3:2]
);
mac_new mac3 (
clk,
{in[29:24], in[19:14], in[9:4]},
filter,
out[5:4]
);
mac_new mac4 (
clk,
{in[35:30], in[25:20], in[15:10]},
filter,
out[7:6]
);
mac_new mac5 (
clk,
{in[37:32], in[27:22], in[17:12]},
filter,
out[9:8]
);
mac_new mac6 (
clk,
{in[39:34], in[29:24], in[19:14]},
filter,
out[11:10]
);
mac_new mac7 (
clk,
{in[45:40], in[35:30], in[25:20]},
filter,
out[13:12]
);
mac_new mac8 (
clk,
{in[47:42], in[37:32], in[27:22]},
filter,
out[15:14]
);
mac_new mac9 (
clk,
{in[49:44], in[39:34], in[29:24]},
filter,
out[17:16]
);
endmodule
| 6.544201 |
module top_conv_8x8 (
clk,
in,
filter,
out
);
input clk;
input [127:0] in;
input [17:0] filter;
output [71:0] out;
/*
mac_new mac1(clk,{in[25:20],in[15:10],in[5:0]},filter,out[1:0]);
mac_new mac2(clk,{in[27:22],in[17:12],in[7:2]},filter,out[3:2]);
mac_new mac3(clk,{in[29:24],in[19:14],in[9:4]},filter,out[5:4]);
mac_new mac4(clk,{in[35:30],in[25:20],in[15:10]},filter,out[7:6]);
mac_new mac5(clk,{in[37:32],in[27:22],in[17:12]},filter,out[9:8]);
mac_new mac6(clk,{in[39:34],in[29:24],in[19:14]},filter,out[11:10]);
mac_new mac7(clk,{in[45:40],in[35:30],in[25:20]},filter,out[13:12]);
mac_new mac8(clk,{in[47:42],in[37:32],in[27:22]},filter,out[15:14]);
mac_new mac9(clk,{in[49:44],in[39:34],in[29:24]},filter,out[17:16]);
*/
genvar k;
genvar l;
generate
for (k = 0; k < 6; k = k + 1) begin : gen_loop
for (l = 0; l < 6; l = l + 1) begin : gen_loop
mac_new_8x8 mac_new_8x80 (
clk,
{in[2*8*(k+2)+l*2+:6], in[2*8*(k+1)+l*2+:6], in[2*8*k+l*2+:6]},
filter,
out[2*6*k+l*2+:2]
);
end
end
endgenerate
endmodule
| 7.192202 |
module top_cordic_rot #(
parameter COUNT_WIDTH = 4, // Counter width
parameter WIDTH = 16, // do rong du lieu cua goc
parameter WIDTH_WIRE = 18 //data width
) (
input clk,
input start,
input rst_n,
input signed [WIDTH_WIRE-1 : 0] x_in,
input signed [WIDTH_WIRE-1 : 0] y_in,
output reg [WIDTH_WIRE-1 : 0] x_out,
output reg [WIDTH_WIRE-1 : 0] y_out,
output reg [ WIDTH-1 : 0] z_out,
output ready
);
wire sign;
wire [COUNT_WIDTH-1 : 0] shift_bit;
wire mux_sel;
wire [ WIDTH_WIRE-1 : 0] x_out_wire;
wire [ WIDTH_WIRE-1 : 0] y_out_wire;
wire [ WIDTH-1 : 0] z_out_wire;
wire [ WIDTH-1 : 0] z_out_wire_temp; //Chuyen z_out_wire ve [0-2pi]
assign z_out_wire_temp = (z_out_wire[WIDTH-1]) ? (z_out_wire+16'd25735) : (z_out_wire);//pi->25735(16bit)
always @(posedge clk or negedge rst_n) begin //Giu gia tri x_out,y_out trong 16 chu ki
if (!rst_n) begin
x_out <= 0;
y_out <= 0;
z_out <= 0;
end else if (shift_bit == 4'd15) begin
x_out <= x_out_wire;
y_out <= y_out_wire;
z_out <= z_out_wire_temp;
end
end
// CORDIC
rot_eda_cordic #(
.WIDTH (WIDTH),
.COUNT_WIDTH(COUNT_WIDTH),
.WIDTH_WIRE (WIDTH_WIRE)
) rot_cordic_inst (
.x_in (x_in),
.y_in (y_in),
.clk (clk),
.ce (start),
.rst_n (rst_n),
.mux_sel (mux_sel),
.shift_bit(shift_bit),
.sign_in (sign),
.x_out (x_out_wire),
.y_out (y_out_wire),
.z_out (z_out_wire),
.sign_out (sign)
);
// CTRL
rot_cordic_ctrl #(
.COUNT_WIDTH(COUNT_WIDTH)
) rot_cordic_ctrl_inst (
.clk (clk),
.ce (start),
.rst_n (rst_n),
.shift_bit(shift_bit),
.mux_ctrl (mux_sel),
.ready (ready)
);
endmodule
| 7.861358 |
module top_count (
input wire clk,
input wire rst_i,
input btn_up_i,
output [6:0] ssd_o,
output sel_o,
output wire led0
);
// Local wires and regs
wire [6:0] num_display;
//ssd instantiation
ssd ssd1 (
.clk (clk),
.rst_i(rst_i),
.num_i(num_display),
.a2g_o(ssd_o),
.sel_o(sel_o)
);
//counter instantiation
count_debounce count_debounce1 (
.clk(clk),
.rst_i(rst_i),
.count_up_i(btn_up_i),
.count_o(num_display)
);
//pwm basic instantiation
pwm_basic pwm_basic1 (
.clk(clk),
.rst_i(rst_i),
.duty_cycle(num_display),
.led0(led0)
);
endmodule
| 8.177711 |
module top_counter (
input clk,
input rst,
input [ 3:0] pulse,
input en_count,
output [15:0] count1,
output [15:0] count2,
output [15:0] count3,
output [15:0] count4
);
// pulse[0] ļģ
counterfour counter_check1 (
.clk (clk),
.rst (rst),
.pulse (pulse[0]),
.en_count(en_count),
.count (count1)
);
// pulse[1] ļģ
counterfour counter_check2 (
.clk (clk),
.rst (rst),
.pulse (pulse[1]),
.en_count(en_count),
.count (count2)
);
// pulse[2] ļģ
counterfour counter_check3 (
.clk (clk),
.rst (rst),
.pulse (pulse[2]),
.en_count(en_count),
.count (count3)
);
// pulse[3] ļģ
counterfour counter_check4 (
.clk (clk),
.rst (rst),
.pulse (pulse[3]),
.en_count(en_count),
.count (count4)
);
endmodule
| 6.954323 |
module top_counter_16 (
input clk,
input rst,
input [15:0] pulse,
input en_count,
output [15:0] count1,
output [15:0] count2,
output [15:0] count3,
output [15:0] count4,
output [15:0] count5,
output [15:0] count6,
output [15:0] count7,
output [15:0] count8,
output [15:0] count9,
output [15:0] counta,
output [15:0] countb,
output [15:0] countc,
output [15:0] countd,
output [15:0] counte,
output [15:0] countf,
output [15:0] countg
);
wire [15:0] pulse_cnt[15:0]; // һά飬ǰ߱ʾλ߱ʾźŸ
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin
counter_16 counter_check (
.clk (clk),
.rst (rst),
.pulse (pulse[i]),
.en_count(en_count),
.count (pulse_cnt[i])
);
end
endgenerate
assign count1 = pulse_cnt[0];
assign count2 = pulse_cnt[1];
assign count3 = pulse_cnt[2];
assign count4 = pulse_cnt[3];
assign count5 = pulse_cnt[4];
assign count6 = pulse_cnt[5];
assign count7 = pulse_cnt[6];
assign count8 = pulse_cnt[7];
assign count9 = pulse_cnt[8];
assign counta = pulse_cnt[9];
assign countb = pulse_cnt[10];
assign countc = pulse_cnt[11];
assign countd = pulse_cnt[12];
assign counte = pulse_cnt[13];
assign countf = pulse_cnt[14];
assign countg = pulse_cnt[15];
endmodule
| 6.561184 |
module top_cpu (
input clk, // clk100mhz
input rstn, // cpu_resetn
input step, // btnu
input cont, // btnd
input chk, // btnr
input data, // btnc
input del, // btnl
input [15 : 0] x, // sw15-0
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS,
output stop, // led16r
output [15 : 0] led, // led15-0
output [ 7 : 0] an, // an7-0
output [ 6 : 0] seg, // ca-cg
output [ 2 : 0] seg_sel // led17
);
wire clk_cpu; // cpu's clk
wire rst_cpu; // cpu's rst
// IO_BUS
wire [ 7 : 0] io_addr;
wire [31 : 0] io_dout;
wire io_we;
wire io_rd;
wire [31 : 0] io_din;
// Debug_BUS
wire [31 : 0] pc;
wire [15 : 0] chk_addr;
wire [31 : 0] chk_data;
// VGA
wire clk_vga;
wire [ 9:0] vga_addr;
wire [ 31:0] vga_data;
pdu PDU (
.clk(clk),
.rstn(rstn),
.step(step),
.cont(cont),
.chk(chk),
.data(data),
.del(del),
.x(x),
.stop(stop),
.led(led),
.an(an),
.seg(seg),
.seg_sel(seg_sel),
.clk_cpu(clk_cpu),
.rst_cpu(rst_cpu),
.clk_vga(clk_vga),
.io_addr(io_addr),
.io_dout(io_dout),
.io_we(io_we),
.io_rd(io_rd),
.io_din(io_din),
.pc(pc),
.chk_addr(chk_addr),
.chk_data(chk_data)
);
cpu CPU (
.clk(clk_cpu),
.rstn(~rst_cpu),
.vga_addr(vga_addr),
.vga_data(vga_data),
.io_addr(io_addr),
.io_dout(io_dout),
.io_we(io_we),
.io_rd(io_rd),
.io_din(io_din),
.pc(pc),
.chk_addr(chk_addr),
.chk_data(chk_data)
);
vga_driver u_vga_driver (
.clk (clk_vga),
.rstn (rstn),
.VGA_R (VGA_R),
.VGA_G (VGA_G),
.VGA_B (VGA_B),
.VGA_HS (VGA_HS),
.VGA_VS (VGA_VS),
.vga_addr(vga_addr),
.vga_data(vga_data)
);
endmodule
| 6.986331 |
module tristate (
en,
i,
o
);
input en;
input i;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en) ? i : 1'bZ;
assign io[1] = (i) ? en : 1'bZ;
assign o = io;
top utop (
en,
i,
o,
io
);
endmodule
| 6.741184 |
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en(en),
.i (a),
.o (c)
);
endmodule
| 7.233807 |
module top_cyclone_four_de2_115 #(
parameter PROG_ADDR_WIDTH = 11,
parameter PROG_DATA_WIDTH = 3,
parameter MEM_ADDR_WIDTH = 16,
parameter MEM_DATA_WIDTH = 9,
parameter PROGRAM_NAME = "../prog/beer.txt"
) (
input CLOCK_50,
input [3:0] SW,
output [17:0] LEDR,
output [8:0] LEDG,
output UART_TXD,
input UART_RXD
);
wire clk;
assign clk = CLOCK_50;
wire rst;
assign rst = ~SW[0];
wire [2:0] debug_state;
wire [(PROG_ADDR_WIDTH-1):0] prog_addr;
wire [(PROG_DATA_WIDTH-1):0] prog_data_rd;
wire prog_rd_en;
single_port_rom #(
.ADDR_WIDTH (PROG_ADDR_WIDTH),
.DATA_WIDTH (PROG_DATA_WIDTH),
.PROGRAM_NAME(PROGRAM_NAME)
) program_memory (
.clk(clk),
.addr(prog_addr),
.q(prog_data_rd),
.rd_en(prog_rd_en)
);
wire [(MEM_ADDR_WIDTH-1):0] mem_addr;
wire [(MEM_DATA_WIDTH-1):0] mem_data_rd;
wire [(MEM_DATA_WIDTH-1):0] mem_data_wr;
wire mem_wr_en;
single_port_ram #(
.ADDR_WIDTH(MEM_ADDR_WIDTH),
.DATA_WIDTH(MEM_DATA_WIDTH)
) data_memory (
.clk(clk),
.addr(mem_addr),
.we(mem_wr_en),
.data(mem_data_wr),
.q(mem_data_rd)
);
wire [7:0] tx_data;
wire tx_wr; //from CORE to UART, write in data to transmit
wire tx_busy; //from UART to CORE, uart is busy transmitting
wire [7:0] rx_data;
wire rx_clear; //FROM CORE to UART, i have seen the data you received
wire rx_ready; //FROM UART to CORE, i have new data to see
wire rx_busy;
uart #(
.DATA_WIDTH(MEM_DATA_WIDTH)
) uart0 (
.clk(clk),
.rst(rst),
.input_axis_tdata (tx_data),
.input_axis_tvalid(tx_wr),
//.input_axis_tready(tx_ready), //don't care about the AXIS api
.output_axis_tdata (rx_data),
.output_axis_tvalid(rx_ready),
.output_axis_tready(rx_clear),
.rxd(UART_RXD),
.txd(UART_TXD),
.tx_busy(tx_busy),
.rx_busy(rx_busy),
//output wire rx_overrun_error //rx_overrun and rx_frame errors are not passed on to the bfcore at this stage
//output wire rx_frame_error
.prescale(16'd651) //prescale (fclk/baud*8) (50MHz / 9600 * 8)
);
brainfuck_core #(
.PROG_DATA_WIDTH(PROG_DATA_WIDTH),
.PROG_ADDR_WIDTH(PROG_ADDR_WIDTH),
.MEM_DATA_WIDTH (MEM_DATA_WIDTH),
.MEM_ADDR_WIDTH (MEM_ADDR_WIDTH)
) core (
.clk(clk),
.rst(rst),
.mem_data_rd(mem_data_rd),
.mem_data_wr(mem_data_wr),
.mem_addr(mem_addr),
.mem_wr_en(mem_wr_en),
.prog_data_rd(prog_data_rd),
.prog_addr(prog_addr),
.prog_rd_en(prog_rd_en),
.rx_data (rx_data),
.rx_ready(rx_ready),
.rx_clear(rx_clear),
.tx_data(tx_data),
.tx_busy(tx_busy),
.tx_wr (tx_wr)
);
assign LEDG[8:0] = prog_addr[8:0];
assign LEDR[7:0] = mem_data_rd[7:0];
assign LEDR[17] = clk;
endmodule
| 7.245591 |
module Top_cymometer (
input sys_clk,
input rst_n,
input clk_fx,
input nCS,
//input MOSI,
input SCK,
output MISO,
output MISO_2,
output SCK_2,
output nCS_2
);
assign SCK_2 = SCK;
assign MISO_2 = MISO;
assign nCS_2 = nCS;
wire sys_clk_h;
/*
Clk_fx_generator Clk_fx
(
.sys_clk (sys_clk_h),
.rst_n (rst_n),
.clk_fx (clk_out)
);
*/
PLL_clk_high PLL_Clk (
.sys_clk (sys_clk),
.rst_n (rst_n),
.sys_clk_h(sys_clk_h)
);
wire [31:0] fs_cnt;
wire [31:0] fx_cnt;
Cymometer Cymometer (
.clk_fs (sys_clk_h),
.rst_n (rst_n),
.clk_fx (clk_fx),
.fs_cnt_out(fs_cnt),
.fx_cnt_out(fx_cnt)
);
SPI_Top SPI_ctrl_top (
.sys_clk(sys_clk_h),
.rst_n (rst_n),
.fs_cnt (fs_cnt),
.fx_cnt (fx_cnt),
//.data_fx ({5'd0,data_fx}),//{5'd0,data_fx}
.nCS (nCS),
//.MOSI (MOSI),
.SCK (SCK),
.MISO (MISO)
);
wire [ 35:0] CONTROL0;
wire [255:0] TRIG0;
assign TRIG0[0] = SCK_2;
assign TRIG0[1] = MISO_2;
assign TRIG0[2] = nCS_2;
chipscope_icon icon_debug (.CONTROL0(CONTROL0));
chipscope_ila ila_filter_debug (
.CONTROL(CONTROL0),
.CLK (sys_clk_h),
.TRIG0 (TRIG0)
);
endmodule
| 7.219359 |
module top_czcjj (
input sys_clk,
input reset_n,
input [2:0] key, //3个按键输入
output [3:0] seg_sel, //位选
output [7:0] seg_led //段选
);
wire sys_reset_n;
wire [7:0] data_s;
wire [7:0] data_m;
wire [4:0] second_point;
wire [15:0] dis_data;
wire [4:0] dis_point;
wire change_dis;
wire add_km;
wire [15:0] data_km;
wire [3:0] point_km;
wire [15:0] data_price;
wire [3:0] point_price;
wire stop_key;
wire en_time;
wire en_km;
key u_key (
.clk (sys_clk),
.reset_n(reset_n),
.key (key),
.change_dis (change_dis),
.add_km (add_km),
.stop (stop_key),
.sys_reset_n(sys_reset_n)
);
count_1s u_count_1 (
.clk (sys_clk),
.sys_reset_n(sys_reset_n),
.EN (en_time),
.data_s(data_s),
.data_m(data_m),
.point (second_point)
);
seg u_seg (
.clk (sys_clk),
.sys_reset(sys_reset_n),
.data (dis_data),
.point (dis_point),
.seg_sel(seg_sel),
.seg_led(seg_led)
);
mux u_mux (
.key_dri (change_dis),
.sys_reset_n (sys_reset_n),
.data_1_kilometer(data_km),
.data_1_point (point_km),
.data_2_time (data_m * 100 + data_s),
.data_2_point (second_point),
.data_3_price (data_price),
.data_3_point (point_price),
.dis_data (dis_data),
.dis_point(dis_point)
);
count_km u_count_km (
.key_dri (add_km),
.sys_reset_n(sys_reset_n),
.EN (en_km),
.data_km(data_km),
.point (point_km)
);
count_money u_price (
.data_m (data_m),
.data_km (data_km),
.sys_reset_n(sys_reset_n),
.clk (sys_clk),
.data_price(data_price),
.point (point_price)
);
stop_car u_stop (
.stop_key (stop_key),
.sys_reset_n(sys_reset_n),
.en_time(en_time),
.en_km (en_km)
);
endmodule
| 7.307694 |
module TOP_Data_control (
i_clk,
data_input,
start,
out_ACC_reg,
out_A_reg,
out_B_reg,
A_out,
p_STATE,
done
);
input i_clk;
input start;
input [`DATA_WIDTH-1:0] data_input;
output [`DATA_WIDTH-1:0] out_ACC_reg;
output [`DATA_WIDTH-1:0] out_A_reg;
output [`DATA_WIDTH-1:0] out_B_reg;
output [`STATE_REG-1:0] p_STATE;
output A_out;
output done;
DATA_PATH DA (
i_clk,
load_B,
load_ACC,
load_A,
clr_ACC_reg,
sel_SUM,
shift_A_reg,
data_input,
out_ACC_reg,
out_A_reg,
out_B_reg,
Lsb_out,
Msb_out,
A_out
);
Controller CU (
i_clk,
load_ACC,
load_B,
load_A,
shift_A_reg,
clr_ACC_reg,
Lsb_out,
Msb_out,
sel_SUM,
A_out,
start,
done,
p_STATE
);
endmodule
| 8.362122 |
module Top_Data_control_tb ();
reg i_clk;
reg start;
reg [`D_WIDTH-1:0] data_input;
wire [`D_WIDTH-1:0] out_ACC_reg;
wire [`D_WIDTH-1:0] out_A_reg;
wire [`D_WIDTH-1:0] out_B_reg;
wire [`D_WIDTH-1:0] Data_out;
wire [`D_WIDTH-1:0] Data_out1;
wire [`State_WIDTH-1:0] p_STATE;
wire A_out;
wire done;
DATA_PATH DUT (
i_clk,
load_B,
load_ACC,
load_A,
clr_ACC_reg,
sel_SUM,
shift_A_reg,
data_input,
out_ACC_reg,
out_A_reg,
out_B_reg,
Lsb_out,
Msb_out,
A_out
);
Controller UUT (
i_clk,
load_ACC,
load_B,
load_A,
shift_A_reg,
clr_ACC_reg,
Lsb_out,
Msb_out,
sel_SUM,
A_out,
start,
done,
p_STATE
);
initial begin
i_clk = 1'b0;
start = 1'b0;
data_input = 8'b0;
end
////clock gen ///
always #5 i_clk = ~i_clk;
initial begin
#3 start = 1'b1;
#1 data_input = 8'b0000_0011;
#10 data_input = 8'b0000_1100;
#5 data_input = 8'b0000_1110;
#800 $finish;
end
endmodule
| 7.427108 |
module top_data_selector (
input [7:0] dat,
input [2:0] addr,
output out
);
case_data_selector u_data_selector (
.dat (dat),
.addr(addr),
.out(out)
);
endmodule
| 7.868438 |
module top_dcmctrl (
output LED1_1,
output LED1_2,
input clk,
output INT,
input SPI_CS,
input SPI_CLK,
input SPI_MOSI,
output SPI_MISO,
output SLOT1_IO0, //PWM_A (1)
output SLOT1_IO1, //PWM_B (1)
output SLOT1_IO2, //PWM_C (1)
output SLOT1_IO3, //PWM_D (1)
output SLOT1_IO4, //RESET_AB (1)
output SLOT1_IO5, //RESET_CD (1)
input SLOT1_IO6, //FAULT (1)
input SLOT1_IO7, //OTW (1)
output SLOT1_IO8, //MODE (1)
output SLOT1_IO9, //TODO: TEMP FOR TESTING
output SLOT2_IO0, //PWM_A (2)
output SLOT2_IO1, //PWM_B (2)
output SLOT2_IO2, //PWM_C (2)
output SLOT2_IO3, //PWM_D (2)
output SLOT2_IO4, //RESET_AB (2)
output SLOT2_IO5, //RESET_CD (2)
input SLOT2_IO6, //FAULT (2)
input SLOT2_IO7, //OTW (2)
output SLOT2_IO8, //MODE (2)
output SLOT2_IO9,
output SLOT4_IO0, //PWM_A (3)
output SLOT4_IO1, //PWM_B (3)
output SLOT4_IO2, //PWM_C (3)
output SLOT4_IO3, //PWM_D (3)
output SLOT4_IO4, //RESET_AB (3)
output SLOT4_IO5, //RESET_CD (3)
input SLOT4_IO6, //FAULT (3)
input SLOT4_IO7, //OTW (3)
output SLOT4_IO8, //MODE (3)
output SLOT4_IO9,
input SLOT3_IO0, //HALL 1
input SLOT3_IO1, //HALL 2
input SLOT3_IO2, //HALL 3
input SLOT3_IO3, //HALL 4
input SLOT3_IO4, //HALL 5
input SLOT3_IO5, //HALL 6
//input SLOT3_IO6 //RESET
//output SLOT3_IO7,
//output SLOT3_IO8,
//output SLOT3_IO9
);
localparam MODE = 0;
wire [7:0] motor_left;
wire [7:0] motor_right;
wire [7:0] motor_reset;
wire [7:0] motor_pulse;
wire [7:0] motor_fault = 0;
wire [7:0] motor_otw = 0;
localparam RESET = 1;
assign SLOT1_IO4 = RESET;
assign SLOT1_IO5 = RESET;
assign SLOT2_IO4 = RESET;
assign SLOT2_IO5 = RESET;
assign SLOT4_IO4 = RESET;
assign SLOT4_IO5 = RESET;
//SLOT 1
assign motor_left[1] = SLOT1_IO0;
assign motor_right[1] = SLOT1_IO1;
assign motor_left[0] = SLOT1_IO2;
assign motor_right[0] = SLOT1_IO3;
//assign motor_reset[1] = !SLOT1_IO4;
//assign motor_reset[0] = !SLOT1_IO5;
assign motor_fault[1] = !SLOT1_IO6;
assign motor_fault[0] = !SLOT1_IO6;
assign motor_otw[1] = !SLOT1_IO7;
assign motor_otw[0] = !SLOT1_IO7;
assign SLOT1_IO8 = MODE;
//SLOT 2
assign motor_left[3] = SLOT2_IO0;
assign motor_right[3] = SLOT2_IO1;
assign motor_left[2] = SLOT2_IO2;
assign motor_right[2] = SLOT2_IO3;
//assign motor_reset[3] = !SLOT2_IO4;
//assign motor_reset[2] = !SLOT2_IO5;
assign motor_fault[3] = !SLOT2_IO6;
assign motor_fault[2] = !SLOT2_IO6;
assign motor_otw[3] = !SLOT2_IO7;
assign motor_otw[2] = !SLOT2_IO7;
assign SLOT2_IO8 = MODE;
//SLOT 4
assign motor_left[5] = SLOT4_IO0;
assign motor_right[5] = SLOT4_IO1;
assign motor_left[4] = SLOT4_IO2;
assign motor_right[4] = SLOT4_IO3;
//assign motor_reset[5] = !SLOT4_IO4;
//assign motor_reset[4] = !SLOT4_IO5;
assign motor_fault[5] = !SLOT4_IO6;
assign motor_fault[4] = !SLOT4_IO6;
assign motor_otw[5] = !SLOT4_IO7;
assign motor_otw[4] = !SLOT4_IO7;
assign SLOT3_IO8 = MODE;
//SLOT 3
assign motor_pulse[0] = SLOT3_IO0;
assign motor_pulse[1] = SLOT3_IO1;
assign motor_pulse[2] = SLOT3_IO2;
assign motor_pulse[3] = SLOT3_IO3;
assign motor_pulse[4] = SLOT3_IO4;
assign motor_pulse[5] = SLOT3_IO5;
//LED
localparam LED_STATUS = 1;
wire LED = LED1_1;
assign LED = LED1_2;
assign LED = !LED_STATUS;
// Powerup Reset Logic
// generate a reset pulse on initial powerup
reg [16:0] pup_count = 0;
reg pup_reset = 1;
always @(posedge clk)
begin
pup_count <= pup_count + 1;
if (pup_count == 24000) pup_reset <= 0;
end
wire reset = pup_reset;
dcmctrl uut (
.clk(clk),
//.reset(reset),
.reset(reset),
.irq(INT),
.spi_ss(SPI_CS),
.spi_clk(SPI_CLK),
.spi_mosi(SPI_MOSI),
.spi_miso(SPI_MISO),
.motor_left(motor_left),
.motor_right(motor_right),
.motor_reset(motor_reset),
.motor_pulse(motor_pulse),
.motor_fault(motor_fault),
.motor_otw(motor_otw)
);
endmodule
| 6.976251 |
module top_dc_func (
input i_clk,
i_reset,
input [2:0] i_mode,
output o_ma,
o_mb,
o_fin,
o_pwm,
output [3:0] o_fndSel,
output [7:0] o_fndData
);
wire w_clk_1hz;
wire [7:0] w_rtime, w_ocr;
clock_divider D1 (
.i_clk (i_clk),
.i_reset(i_reset),
.o_clk (w_clk_1hz)
);
dc_function D2 (
.i_clk(w_clk_1hz),
.i_reset(i_reset),
.i_mode(i_mode),
.o_ma(o_ma),
.o_mb(o_mb),
.o_fin(o_fin),
.o_ocr(w_ocr),
.o_rtime(w_rtime)
);
top_pwm_gen D3 (
.i_clk (i_clk),
.i_reset(i_reset),
.i_ocr (w_ocr),
.o_pwm (o_pwm)
);
top_fnd_display D4 (
.i_clk(i_clk),
.i_reset(i_reset),
.i_data(w_rtime),
.o_fndSelect(o_fndSel),
.o_fndData(o_fndData)
);
endmodule
| 7.374222 |
module top_dds (
input wire sys_clk, //系统时钟,50MHz
input wire sys_rst_n, //复位信号,低电平有效
input wire [3:0] key, //输入4位按键
output wire dac_clk, //输入DAC模块时钟
output wire [7:0] dac_data //输入DAC模块波形数据
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire [3:0] wave_select; //波形选择
//dac_clka:DAC模块时钟
assign dac_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//-------------------------- dds_inst -----------------------------
dds dds_inst (
.sys_clk (sys_clk), //系统时钟,50MHz
.sys_rst_n (sys_rst_n), //复位信号,低电平有效
.wave_select(wave_select), //输出波形选择
.data_out(dac_data) //波形输出
);
//----------------------- key_control_inst ------------------------
key_control key_control_inst (
.sys_clk (sys_clk), //系统时钟,50MHz
.sys_rst_n(sys_rst_n), //复位信号,低电平有效
.key (key), //输入4位按键
.wave_select(wave_select) //输出波形选择
);
endmodule
| 6.71743 |
module top_de0_nano (
input clk,
input ext_rst_n,
output reg [7:0] led
);
`include "macros/direction.vh"
reg [2:0] int_rst_cnt = 0;
always @(posedge clk) begin
if (int_rst_cnt != 3'b111) int_rst_cnt <= int_rst_cnt + 1;
end
wire int_rst_n = int_rst_cnt == 3'b111;
wire rst_n = int_rst_n && ext_rst_n;
wire i_req;
wire [15:0] i_addr;
wire i_ack;
wire [7:0] i_rdata;
wire d_req;
wire d_dir;
wire [7:0] d_addr;
wire [7:0] d_wdata;
wire d_ack;
wire [7:0] d_rdata;
wire io_req;
wire io_dir;
wire [7:0] io_wdata;
reg io_ack;
reg [7:0] io_rdata;
bfcpu cpu (
.clk (clk),
.rst_n(rst_n),
.i_req (i_req),
.i_addr (i_addr),
.i_ack (i_ack),
.i_rdata(i_rdata),
.d_req (d_req),
.d_dir (d_dir),
.d_addr (d_addr),
.d_wdata(d_wdata),
.d_ack (d_ack),
.d_rdata(d_rdata),
.io_req (io_req),
.io_dir (io_dir),
.io_wdata(io_wdata),
.io_ack (io_ack),
.io_rdata(io_rdata)
);
i_mem_de0_nano im (
.clk(clk),
.i_req (i_req),
.i_addr (i_addr),
.i_ack (i_ack),
.i_rdata(i_rdata)
);
d_mem_de0_nano dm (
.clk(clk),
.d_req (d_req),
.d_dir (d_dir),
.d_addr (d_addr),
.d_wdata(d_wdata),
.d_ack (d_ack),
.d_rdata(d_rdata)
);
always @(posedge clk) begin
if (!rst_n) begin
led <= 7'b0;
io_ack <= 0;
end else begin
if (io_req) begin
io_ack <= 1;
if (io_dir == `DIRECTION_WRITE) led <= io_wdata;
else io_rdata <= led;
end else begin
io_ack <= 0;
end
end
end
endmodule
| 6.818493 |
module top_debounce (
bounce_in,
clk,
rst_n,
debounce_out
);
// This is wrapper for switch debouncing it includes counter for 20ms and FSM for debouncing
input bounce_in, clk, rst_n;
output debounce_out;
wire cnt_w, strt_w;
sm_debounce SM_de_1 (
.clk(clk),
.rst_n(rst_n),
.b_in(bounce_in),
.cnt(cnt_w),
.strt(strt_w),
.db_out(debounce_out)
);
counter_20ms C20_1 (
.strt (strt_w),
.clk (clk),
.rst_n(rst_n),
.cnt_p(cnt_w)
);
endmodule
| 8.164812 |
module top_decoder_3_8 (
input [2:0] addr,
output [7:0] out
);
//case_decoder_3_8 u_decoder_3_8 (
logic_decoder_3_8 u_decoder_3_8 (
.addr(addr),
.out (out)
);
endmodule
| 7.106269 |
module top_default_BUFF_ASYNC_W1_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input D;
output Q;
reg Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W1_D1_S1 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input D;
output Q;
reg Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W2_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input [1:0] D;
output [1:0] Q;
reg [1:0] Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 2'b00;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W3_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input [2:0] D;
output [2:0] Q;
reg [2:0] Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 3'b000;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W4_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input [3:0] D;
output [3:0] Q;
reg [3:0] Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 4'b0000;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W5_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input [4:0] D;
output [4:0] Q;
reg [4:0] Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 5'b00000;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top_default_BUFF_ASYNC_W12_D1_S0 (
CK,
RN,
D,
Q
);
input CK;
input RN;
input [11:0] D;
output [11:0] Q;
reg [11:0] Q;
always @(posedge CK or negedge RN) begin
if (~RN) begin
Q <= 12'b000000000000;
end else begin
Q <= D;
end
end
endmodule
| 6.719389 |
module top (
input x
);
endmodule
| 7.233807 |
module tristate (
en,
i,
io,
o
);
input en;
input i;
inout [1:0] io;
output [1:0] o;
reg [1:0] io_buf;
assign io = io_buf;
always @(en or i) io_buf[0] <= (en) ? i : 1'bZ;
always @(en or i) io_buf[1] <= (i) ? en : 1'bZ;
assign o = (en) ? io : 2'bZZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en(en),
.i (a),
.io(b),
.o (c)
);
endmodule
| 7.233807 |
module Top_design (
input i_clk,
input i_rst,
input incr,
input decr,
output [`SEG_WID-1:0] o_seg_en,
output an_seg,
output [`SEG_WIDTH-1:0] Sseg_out
);
assign an_seg = 1'b1;
wire [3:0] seg_out;
reg p_state;
reg [`N_WIDTH-1:0] digit0, digit1;
//reg [`COUNT_WIDTH-1:0] cnt_clr ;
reg [`COUNT_WID_REFRESH-1:0] refresh_cnt = 0;
seven_seg_display SS (
.i_hex_en(seg_out),
.o_out(Sseg_out)
);
wire clk_out;
clk_div DIV_CLK (
.i_clk(i_clk),
.clk_o(clk_out)
);
always @(posedge i_clk) begin
refresh_cnt <= refresh_cnt + 1'b1;
end
Multiplexer_circuit MUX (
.i_clk (refresh_cnt[16]),
.o_seg1(digit0),
.o_seg2(digit1),
.o_en (o_seg_en),
.o_seg (seg_out)
);
always @(posedge clk_out) begin
case (p_state)
0: begin
digit0 <= 4'b0000;
digit1 <= 4'b0000;
p_state <= 1'b1;
end
1: begin
if (i_rst == 1'b1) begin
p_state <= 1'b0;
end else if (incr == 1'b1 && decr == 1'b0) begin
if (digit0 < 4'b1001) begin
digit0 <= digit0 + 1'b1;
end else if (digit1 < 4'b1001) begin
digit1 <= digit1 + 1'b1;
digit0 <= 4'b0000;
end
end else if (incr == 1'b0 && decr == 1'b1) begin
if (digit0 > 4'b0000) begin
digit0 <= digit0 - 1'b1;
end else if (digit1 > 4'b0000) begin
digit1 <= digit1 - 1'b1;
digit0 <= 4'b1001;
end
end else if (incr == 1'b1 && decr == 1'b1) begin
p_state <= 0;
end
end
default: begin
p_state <= 0;
end
endcase
end
endmodule
| 7.586592 |
module top_design_file (
clk,
rst,
data_in,
data_out
, state,
Reg1,
Reg2,
Reg3
);
input clk, rst;
output [3:0] Reg1, Reg2, Reg3;
output [3:0] data_out;
input [3:0] data_in;
output [1:0] state;
wire ldr_1, ldr_2, ldr_3, sel_1;
wire [1:0] sel_2;
data_path DATAPATH (
clk,
rst,
ldr_1,
ldr_2,
ldr_3,
sel_1,
sel_2,
data_in,
data_out,
Reg1,
Reg2,
Reg3
);
controller control_path (
clk,
rst,
ldr_1,
ldr_2,
ldr_3,
sel_1,
sel_2,
state
);
endmodule
| 7.146233 |
module top_design_file_TB ();
reg [3:0] data_in;
reg clk, rst;
wire [3:0] data_out, Reg1, Reg2, Reg3;
wire [1:0] state;
top_design_file DUT (
clk,
rst,
data_in,
data_out
, state,
Reg1,
Reg2,
Reg3
);
always #10 clk = ~clk;
initial begin
#0 clk = 0;
rst = 1;
data_in = 0;
#30 rst = 0;
#20 data_in = 9;
#60 data_in = 7;
#90 data_in = 8;
#100 $stop;
end
endmodule
| 7.146233 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top_design_module(
input i_clk,
input i_select_s1,
input i_select_s0,
input i_enable ,
output o_led_drive
);
parameter DATA_WIDTH_10HZ = 24 ;
parameter DATA_WIDTH_5HZ = 25 ;
parameter DATA_WIDTH_2HZ = 26 ;
parameter DATA_WIDTH_1HZ = 27 ;
///these parameters will be the signals for the different frequencies///
parameter CNT_10HZ = 5_000_000;
parameter CNT_5HZ = 10_000_000;
parameter CNT_2HZ = 25_000_000;
parameter CNT_1HZ = 50_000_000;
///these will be the counters for counting upto certain period //
reg [DATA_WIDTH_10HZ-1:0] reg_CNT_10HZ = 0 ;
reg [DATA_WIDTH_5HZ-1:0] reg_CNT_5HZ = 0 ;
reg [DATA_WIDTH_2HZ-1:0] reg_CNT_2HZ = 0;
reg [DATA_WIDTH_1HZ-1:0] reg_CNT_1HZ = 0 ;
///these will be intermediate registers for toggling the operation of frequencies//
reg TOGGLE_CNT_10HZ = 1'b0;
reg TOGGLE_CNT_5HZ = 1'b0;
reg TOGGLE_CNT_2HZ = 1'b0;
reg TOGGLE_CNT_1HZ = 1'b0;
///for selcting the operation //
reg r_LED_SELECT ;
//10HZ clock block///
always @ (posedge i_clk)
begin
if (reg_CNT_10HZ == CNT_10HZ-1)
begin
TOGGLE_CNT_10HZ <= !TOGGLE_CNT_10HZ ;
reg_CNT_10HZ <= 0 ;
end
else
begin
reg_CNT_10HZ <= reg_CNT_10HZ + 1'b1 ;
end
end
///5HZ clock block///
always @ (posedge i_clk)
begin
if (reg_CNT_5HZ == CNT_5HZ-1 )
begin
TOGGLE_CNT_5HZ <= !TOGGLE_CNT_5HZ ;
reg_CNT_5HZ <= 0 ;
end
else
begin
reg_CNT_5HZ <= reg_CNT_5HZ + 1'b1 ;
end
end
///2HZ clock block////
always @ (posedge i_clk)
begin
if (reg_CNT_2HZ == CNT_2HZ-1 )
begin
TOGGLE_CNT_2HZ <= !TOGGLE_CNT_2HZ ;
reg_CNT_2HZ <= 0 ;
end
else
begin
reg_CNT_2HZ <= reg_CNT_2HZ + 1'b1 ;
end
end
///1HZ clock block///
always @ (posedge i_clk)
begin
if (reg_CNT_1HZ == CNT_1HZ-1 )
begin
TOGGLE_CNT_1HZ <= !TOGGLE_CNT_1HZ ;
reg_CNT_1HZ <= 0 ;
end
else
begin
reg_CNT_1HZ <= reg_CNT_1HZ + 1'b1 ;
end
end
///combinational block for multiplexing the above frequency signals for routing to one signal path///
always @(*)
begin
case({i_select_s1 , i_select_s0})
2'b00 : r_LED_SELECT <= TOGGLE_CNT_10HZ ;
2'b01 : r_LED_SELECT <= TOGGLE_CNT_5HZ ;
2'b10 : r_LED_SELECT <= TOGGLE_CNT_2HZ ;
2'b11 : r_LED_SELECT <= TOGGLE_CNT_1HZ ;
endcase
end
assign o_led_drive = r_LED_SELECT & i_enable;
endmodule
| 7.088073 |
module
// Module Name: /home/ise/xilinx/Blinking_leds/Top_design_module_tb.v
// Project Name: Blinking_leds
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top_design_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_design_module_tb;
// Inputs
reg i_clk= 0;
reg i_select_s1;
reg i_select_s0;
reg i_enable ;
// Outputs
wire o_led_drive = 0;
// Instantiate the Unit Under Test (UUT)
Top_design_module uut (
.i_clk(i_clk),
.i_select_s1(i_select_s1),
.i_select_s0(i_select_s0),
.i_enable (i_enable),
.o_led_drive(o_led_drive)
);
always #5 i_clk = ~i_clk ;
initial
begin
i_enable = 0 ;
i_select_s1 = 0;
i_select_s0 = 0 ;
end
initial
begin
i_enable = 1;
i_select_s1 = 0 ;
i_select_s0 = 0 ;
#2000000;
i_select_s1 = 0;
i_select_s0 = 1;
#2000000;
i_select_s1 = 0 ;
i_select_s0 = 0 ;
#2000000;
i_select_s1 = 0;
i_select_s0 = 1;
#2000000;
end
endmodule
| 6.999332 |
module Top_design_tb ();
reg clk, rst_n, d_in;
wire out_mealy;
wire mealy_glitch_free;
wire [`S_WIDTH-1:0] p_STATE;
/////instantiation of design block/////
TOP_design DUT (
clk,
rst_n,
d_in,
out_mealy,
p_STATE,
mealy_glitch_free
);
//setting default value of clk and reset to zero /////////
initial begin
clk = 1'b0;
rst_n = 1'b0;
end
///clock gen/////
always #5 clk = ~clk;
///// applying reset ///
initial begin
repeat (2) @(posedge clk) rst_n <= 1'b1;
repeat (5) @(posedge clk);
end
///applying input to design module //
initial begin
#5 d_in = 1'b1;
#10 d_in = 1'b0;
#15 d_in = 1'b0;
#5 d_in = 1'b1;
#4 d_in = 1'b0;
#3 d_in = 1'b0;
#5 d_in = 1'b1;
#6 d_in = 1'b0;
#7 d_in = 1'b1;
#2 d_in = 1'b0;
#6 d_in = 1'b0;
#7 d_in = 1'b0;
#8 d_in = 1'b1;
#2 d_in = 1'b1;
#5 d_in = 1'b0;
#8 d_in = 1'b1;
#9 d_in = 1'b0;
#5 d_in = 1'b0;
#7 d_in = 1'b0;
#8 d_in = 1'b1;
#4 d_in = 1'b0;
#7 d_in = 1'b0;
#3 d_in = 1'b0;
#5 d_in = 1'b0;
#2 d_in = 1'b1;
#4 d_in = 1'b0;
#5 d_in = 1'b1;
#600 $stop;
end
//200 $finish ;
endmodule
| 7.863409 |
module dff (
input d,
clk,
output reg q
);
always @(posedge clk) q <= d;
endmodule
| 7.174483 |
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