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AutoVCoder_round1

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float64
6.5
11.5
module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_36 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_35 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_34 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_33 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_32 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_31 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_30 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_29 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_28 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_27 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_26 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_19 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_18 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_17 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_16 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_15 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_14 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_13 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_12 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_11 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_10 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_25 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_24 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_23 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_22 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_21 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_20 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_19 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_18 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_17 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_16 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_15 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_14 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_13 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_0 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_9 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_8 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_7 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_6 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_5 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_4 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_3 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_2 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_add_v2_mydesign_0_mydesign_1 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24637, n2; AND2X1_HVT main_gate ( .A1(net24637), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24637) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_0 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_12 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_11 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_10 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_9 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_8 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_7 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_6 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_5 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_4 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_3 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_2 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_comp_mydesign_0_mydesign_1 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24560, n2; AND2X1_HVT main_gate ( .A1(net24560), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24560) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_0 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n1; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n1), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n1) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_59 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_58 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_57 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_56 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_55 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_54 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_53 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_52 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_51 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_50 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_49 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_48 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_47 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_46 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_45 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_44 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_43 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_42 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_41 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_40 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_39 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_38 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_37 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_36 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_35 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_34 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_33 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_32 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_31 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_30 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_29 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_28 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_27 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_26 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_25 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_24 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_23 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_22 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_21 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_20 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_19 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_18 ( CLK, EN, ENCLK ); input CLK, EN; output ENCLK; wire net24245, n2; AND2X1_HVT main_gate ( .A1(net24245), .A2(CLK), .Y (ENCLK) ); LATCHX1_HVT latch ( .CLK(n2), .D (EN), .Q (net24245) ); INVX2_HVT U1 ( .A(CLK), .Y(n2) ); endmodule
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