code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top (
input rx,
output tx,
output sync
);
wire clk;
SB_HFOSC #(
.CLKHF_DIV("0b10")
) u_SB_HFOSC (
.CLKHFPU(1),
.CLKHFEN(1),
.CLKHF (clk)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
sdk80 machine (
.clk(clk),
.reset(~resetn),
.rx(rx),
.tx(tx),
.sync(sync)
);
endmodule
| 7.233807 |
module top_sd_rw (
input sys_clk,
input sys_rst_n,
// sdӿ
input sd_miso,
output sd_clk,
output sd_cs,
output sd_mosi,
//LED
output [3:0] led
);
//wire define
wire clk_ref;
wire clk_ref_180deg;
wire rst_n;
wire locked;
wire wr_start_en;
wire [31:0] wr_sec_addr;
wire [15:0] wr_data;
wire rd_start_en;
wire [31:0] rd_sec_addr;
wire error_flag;
wire wr_busy;
wire wr_req;
wire rd_busy;
wire rd_val_en;
wire [15:0] rd_val_data;
wire sd_init_done;
// wire sys_rst_n ;
//***************************
//** main code
//***************************
assign rst_n = ~sys_rst_n & locked;
//ʱ
clk_wiz_0 clk_siz_0_inst (
.reset (1'b0),
.clk_in1 (sys_clk),
.clk_out1(clk_ref),
.clk_out2(clk_ref_180deg),
.locked (locked)
);
sd_ctrl_top sd_ctrl_top_ins (
.clk_ref (clk_ref),
.clk_ref_180deg(clk_ref_180deg),
.rst_n (rst_n),
.sd_miso(sd_miso),
.sd_clk (sd_clk),
.sd_cs (sd_cs),
.sd_mosi(sd_mosi),
.wr_start_en(wr_start_en),
.wr_sec_addr(wr_sec_addr),
.wr_data (wr_data),
.wr_busy (wr_busy),
.wr_req (wr_req),
.rd_start_en(rd_start_en),
.rd_sec_addr(rd_sec_addr),
.rd_busy (rd_busy),
.rd_val_en (rd_val_en),
.rd_val_data(rd_val_data),
.sd_init_done(sd_init_done)
);
led_alarm #(
.L_TIME(25'd25_000_000)
) led_alarm_inst (
.clk (clk_ref),
.rst_n (rst_n),
.led (led),
.error_flag(error_flag)
);
data_gen data_gen_inst (
.clk (clk_ref),
.rst_n (rst_n),
.sd_init_done(sd_init_done),
.wr_busy (wr_busy),
.wr_req (wr_req),
.wr_start_en(wr_start_en),
.wr_sec_addr(wr_sec_addr),
.wr_data (wr_data),
.rd_val_en (rd_val_en),
.rd_val_data(rd_val_data),
.rd_start_en(rd_start_en),
.rd_sec_addr(rd_sec_addr),
.error_flag(error_flag)
);
endmodule
| 6.50141 |
module top_secseg (
rst,
inclk,
seg1,
seg10
);
input rst, inclk;
output wire [6:0] seg1, seg10;
wire [5:0] sec_val;
sec_cnt counter (
rst,
inclk,
sec_val
);
sec_conv converter (
rst,
sec_val,
seg1,
seg10
);
endmodule
| 7.503114 |
module top_seg_595 (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号，低电平有效
output wire stcp, //输出数据存储寄时钟
output wire shcp, //移位寄存器的时钟输入
output wire ds, //串行数据输入
output wire oe //输出使能信号
);
//********************************************************************//
//******************** Parameter And Internal Signal *****************//
//********************************************************************//
//wire define
wire [19:0] data; //数码管要显示的值
wire [ 5:0] point; //小数点显示,高电平有效top_seg_595
wire seg_en; //数码管使能信号，高电平有效
wire sign; //符号位，高电平显示负号
//********************************************************************//
//**************************** Main Code *****************************//
//********************************************************************//
//-------------data_gen_inst--------------
data_gen data_gen_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号，低电平有效
.data (data), //数码管要显示的值
.point (point), //小数点显示,高电平有效
.seg_en(seg_en), //数码管使能信号，高电平有效
.sign (sign) //符号位，高电平显示负号
);
//-------------seg7_dynamic_inst--------------
seg_595_dynamic seg_595_dynamic_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号，低有效
.data (data), //数码管要显示的值
.point (point), //小数点显示,高电平有效
.seg_en (seg_en), //数码管使能信号，高电平有效
.sign (sign), //符号位，高电平显示负号
.stcp(stcp), //输出数据存储寄时钟
.shcp(shcp), //移位寄存器的时钟输入
.ds (ds), //串行数据输入
.oe (oe) //输出使能信号
);
endmodule
| 8.133576 |
module Top_sensor (
clk_50m,
rst,
Trig_l,
Trig_r,
Trig_f1,
Trig_f2,
Echo_l,
Echo_r,
Echo_f1,
Echo_f2,
seven_seg_out,
Select,
stop,
backward,
turn_left,
turn_right,
state,
run
);
input clk_50m, rst;
input Echo_l, Echo_r, Echo_f1, Echo_f2;
output Trig_l, Trig_r, Trig_f1, Trig_f2;
output [7:0] seven_seg_out;
output [3:0] Select;
output stop, backward, turn_left, turn_right;
output [2:0] state;
output run;
wire [11:0] fd1, fd2, ld, rd;
wire clk_1M;
NumberDisplay nd1 (
.clk(clk_50m),
.Data(fd1),
.seven_seg_out(seven_seg_out),
.Select(Select),
.rst(rst)
);
sonic_detect l1 (
.clk_50m(clk_50m),
.rst(rst),
.Trig(Trig_l),
.Echo(Echo_l),
.dis(rd)
);
sonic_detect r1 (
.clk_50m(clk_50m),
.rst(rst),
.Trig(Trig_r),
.Echo(Echo_r),
.dis(ld)
);
sonic_detect f1 (
.clk_50m(clk_50m),
.rst(rst),
.Trig(Trig_f1),
.Echo(Echo_f1),
.dis(fd1)
);
sonic_detect f2 (
.clk_50m(clk_50m),
.rst(rst),
.Trig(Trig_f2),
.Echo(Echo_f2),
.dis(fd2)
);
Clk_1M clk1 (
.outclk(clk_1M),
.inclk(clk_50m),
.rst(rst)
);
turn t1 (
.fd1(fd1),
.fd2(fd2),
.ld(ld),
.rd(rd),
.clk_1M(clk_1M),
.rst(rst),
.stop(stop),
.backward(backward),
.turn_left(turn_left),
.turn_right(turn_right),
.state(state)
);
assign run = ~stop;
/*
always@(posedge clk_50m)
begin
if(dis_m1 <50 || dis_m2 <50)
stop = 1;
if(dis_l<dis_r)
begin
if(dis_r < threshold)
backward
else
turn right
end
else//dis_l>dis_r
if(dis_l<threshold)
backward
else
turn left
else
stop = 0;
//
if(dis_l <50)
led_l = 1;
else
led_l = 0;
if(dis_r <)
led_r = 1;
else
led_r = 0;
end
*/
endmodule
| 6.707173 |
module top_sft;
wire tb_sim_rst; // simulation only reset
wire clk12m; // 12 mhz clock
wire [4:0] leds; // lattice leds
wire [7:0] tb_rx_data;
wire tb_rx_data_rdy;
wire [7:0] la_tx_data;
wire la_tx_data_rdy;
latticehx1k latticehx1k (
.sd(),
.clk_in(clk12m),
.from_pc(),
.to_ir(),
.o_serial_data(),
.led(leds),
.tb_sim_rst(tb_sim_rst),
.tb_rx_data(tb_rx_data),
.tb_rx_data_rdy(tb_rx_data_rdy),
.la_tx_data(la_tx_data),
.la_tx_data_rdy(la_tx_data_rdy)
);
tb_sft tb_sft (
.tb_sim_rst(tb_sim_rst),
.clk12m(clk12m),
.la_tx_data(la_tx_data),
.la_tx_data_rdy(la_tx_data_rdy),
.tb_rx_data(tb_rx_data),
.tb_rx_data_rdy(tb_rx_data_rdy),
.leds(leds)
);
endmodule
| 7.211458 |
module top (
input signed x,
input signed y,
input signed cin,
output signed A,
output signed cout,
output signed B,
C
);
assign A = y >> x;
assign cout = y + A >>> y;
assign {B, C} = {cout, A} << 1;
endmodule
| 7.233807 |
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock, reset, req_0, req_1;
output signed gnt_0, gnt_1;
wire clock, reset, req_0, req_1;
reg gnt_0, gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101;
reg signed [SIZE-1:0] state;
reg signed [SIZE-1:0] next_state;
always @(posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case (state)
IDLE:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1:
if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2:
if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default: state <= #1 IDLE;
endcase
end
endmodule
| 7.229634 |
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm (
.clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1)
);
endmodule
| 7.233807 |
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock, reset, req_0, req_1;
output gnt_0, gnt_1;
wire clock, reset, req_0, req_1;
reg gnt_0, gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001, GNT0 = 3'b010, GNT1 = 3'b100, GNT2 = 3'b101;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @(posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case (state)
IDLE:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0:
if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1:
if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2:
if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default: state <= #1 IDLE;
endcase
end
endmodule
| 7.229634 |
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm (
.clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1)
);
endmodule
| 7.233807 |
module top_sim1 ();
localparam FREQ = 12; // in MHZ
// clock
reg clk;
initial begin
#0 clk = 0;
forever clk = #(1000 / (FREQ * 2)) !clk;
end
// reset
reg rst;
initial begin
#0 rst = 1;
#100 rst = 0;
end
// dut
wire [7:0] leds;
wire tx;
top_syn dut (
.CLK_I(clk),
.LED_IO(leds),
.UART_RTS_N_I(rst),
.UART_RX_I(1),
.UART_TX_O(tx)
);
// simulation
initial begin
$dumpfile("build/waveform1.vcd");
$dumpvars;
// this will stop simulation at some point
#800000 $finish(0);
end
endmodule
| 6.66338 |
module top_single (
clk,
rst,
address,
start,
write_data,
read_operation,
cache_busy,
read_data
);
input clk, rst, start;
input [7:0] address;
input [7:0] write_data;
input read_operation;
output cache_busy;
output [7:0] read_data;
//module single_bus1(clk, rst, read_op, in_address, in_data, out_data, finish_flag, start );
//module cc_singlebus (CC_clk, rst, address, read_data, write_data, start, read_operation, hit, cache_busy,
//write_opn_to_bus, out_data_Mem, read_select_Mem, write_select_Mem, write_data_Mem, finish, bus_access);
wire write_opn_to_bus;
wire [7:0] read_select_Mem, write_data_Mem, out_data_Mem;
wire finish, bus_access;
cc_singlebus cc420 (
clk,
rst,
address,
read_data,
write_data,
start,
read_operation,
hit,
cache_busy,
write_opn_to_bus,
out_data_Mem,
read_select_Mem,
write_select_Mem,
write_data_Mem,
finish,
bus_access
);
single_bus1 sb520 (
clk,
rst,
write_opn_to_bus,
read_select_Mem,
write_data_Mem,
out_data_Mem,
finish,
bus_access
);
endmodule
| 6.54264 |
module top (
input [7:0] data_a,
data_b,
input [6:1] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clk,
output reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @(posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule
| 7.233807 |
module smg (
clk,
data,
sm_wei,
sm_duan,
rst
);
input clk, rst;
input [15:0] data;
output [3:0] sm_wei;
output [7:0] sm_duan;
//----------------------------------------------------------
//ƵƵΪ100Hz
integer clk_cnt; //Ƶڼ
reg clk_100Hz;
always @(posedge clk)
if (rst == 1) begin //ܷƵʾ
clk_cnt <= 1'b0;
clk_100Hz <= 1'b0;
end else if (clk_cnt == 32'd25000) begin
clk_cnt <= 1'b0; //ڽ¼
clk_100Hz <= ~clk_100Hz; //ʱӷת
end else clk_cnt <= clk_cnt + 1'b1; //Ƶڼ+1ֹȥһʱ
//----------------------------------------------------------
//λ
//reg [2:0]wei_ctrl;
//always @(posedge clk_100Hz)
//begin
// if(rst == 1) begin
// wei_ctrl <= 0;
// end
// else begin
// wei_ctrl <= wei_ctrl + 1;
// if(wei_ctrl == 3'b100) wei_ctrl <= 3'b0;
// end
//end
//ÿƵ˵ʱ4λ˸
//Ӿ˿ĸʾIJͬ
reg [3:0] wei_ctrl = 4'b1110;
always @(posedge clk_100Hz) wei_ctrl <= {wei_ctrl[2:0], wei_ctrl[3]};
//οƣÿһλܵ8ledƵ
reg [3:0] duan_ctrl;
always @(wei_ctrl)
case (wei_ctrl)
4'b1110: duan_ctrl = data[2:0];
4'b1101: duan_ctrl = data[5:3];
4'b1011: duan_ctrl = data[8:6];
4'b0111: duan_ctrl = data[11:9];
default: duan_ctrl = 4'hf;
endcase
//----------------------------------------------------------
//ģ飺8ledƵĽ룬ledƶӦλ˸͵ƽƣ
reg [7:0] duan;
always @(duan_ctrl)
case (duan_ctrl)
4'h0: duan = 8'b1100_0000; //0
4'h1: duan = 8'b1111_1001; //1
4'h2: duan = 8'b1010_0100; //2
4'h3: duan = 8'b1011_0000; //3
4'h4: duan = 8'b1001_1001; //4
4'h5: duan = 8'b1001_0010; //5
4'h6: duan = 8'b1000_0010; //6
4'h7: duan = 8'b1111_1000; //7
4'h8: duan = 8'b1000_0000; //8
4'h9: duan = 8'b1001_0000; //9
4'ha: duan = 8'b1000_1000; //a
4'hb: duan = 8'b1000_0011; //b
4'hc: duan = 8'b1100_0110; //c
4'hd: duan = 8'b1010_0001; //d
4'he: duan = 8'b1000_0110; //e
4'hf: duan = 8'b1000_1110; //f
default: duan = 8'b1100_0000; //0
endcase
//----------------------------------------------------------
assign sm_wei = wei_ctrl;
assign sm_duan = duan;
endmodule
| 7.175966 |
module top_smg (
clk,
rst,
cs,
din_a_0,
addr_a_0,
dout_a,
we_a,
oe_a,
din_b_0,
addr_b_0,
dout_b,
we_b,
oe_b,
rst_clk,
load,
sm_wei,
sm_duan
);
parameter DATA_WIDTH = 3;
parameter ADDR_WIDTH = 3;
parameter RAM_DEPTH = DATA_WIDTH;
input clk, rst, cs;
input [ADDR_WIDTH-1:0] addr_a_0, addr_b_0;
input [DATA_WIDTH-1:0] din_a_0, din_b_0;
output [DATA_WIDTH-1:0] dout_a, dout_b;
input we_a, oe_a, we_b, oe_b;
input rst_clk;
input load;
output [3:0] sm_wei; //λź
output [7:0] sm_duan; //οź
//----------------------------------------------------------
wire [11:0] data; //ʾÿһλݣÿ3λdataӦÿһλ
wire [ 3:0] sm_wei;
wire [ 7:0] sm_duan;
//----------------------------------------------------------
//ƴźΪ12λdataȻsmgʵU1Уٿ߶ܷ
assign data[11:9] = addr_a_0;
assign data[8:6] = dout_a;
assign data[5:3] = addr_b_0; //ҪļλΪ0
assign data[2:0] = dout_b;
top_double_ram_sy top_ram (
clk,
rst,
cs,
din_a_0,
addr_a_0,
dout_a,
we_a,
oe_a,
din_b_0,
addr_b_0,
dout_b,
we_b,
oe_b,
rst_clk,
load
);
smg U1 (
.clk(clk),
.data(data),
.sm_wei(sm_wei),
.sm_duan(sm_duan),
.rst(rst)
);
endmodule
| 7.048532 |
module Top_Snake (
input CLOCK,
input [2:0] btn,
input [12:0] pixel,
input [3:0] sw,
output [15:0] oled_data,
output [3:0] an,
output [7:0] seg
);
wire [35:0] SLOW_CLOCK;
slow_clock SC (
CLOCK,
SLOW_CLOCK
);
wire left_pulse, right_pulse, reset;
pulse p1 (
btn[0],
SLOW_CLOCK[15],
reset
);
pulse p2 (
btn[1],
SLOW_CLOCK[15],
left_pulse
);
pulse p3 (
btn[2],
SLOW_CLOCK[15],
right_pulse
);
wire speed_selector;
wire E, L, R;
gen_sig G (
CLOCK,
speed_selector,
reset,
left_pulse,
right_pulse,
E,
L,
R
);
wire [4:0] len;
plot_snake_test PST (
speed_selector,
E,
L,
R,
pixel,
oled_data,
len
);
snake_seven_seg_display S (
SLOW_CLOCK[15],
len,
an,
seg
);
assign speed_selector = (sw[3] == 1) ? SLOW_CLOCK[21] :
(sw[2] == 1) ? SLOW_CLOCK[22] :
(sw[1] == 1) ? SLOW_CLOCK[23] :
(sw[0] == 1) ? SLOW_CLOCK[24] :
0;
endmodule
| 7.194323 |
module top_SoC (
main_clk,
pll_reset,
core_reset,
dac_out
);
input main_clk;
input pll_reset, core_reset;
output [7:0] dac_out;
wire locked;
wire core_clk;
clk_wiz_0 uut1 (
// Clock out ports
.clk_out1(core_clk), // output clk_out1
// Status and control signals
.reset (pll_reset), // input reset
.locked (locked), // output locked
// Clock in ports
.clk_in1 (main_clk)
);
rvmyth uut2 (
core_clk,
core_reset,
dac_out
);
ila_0 uut3 (
.clk(main_clk), // input wire clk
.probe0(dac_out), // input wire [7:0] probe0
.probe1(core_reset), // input wire [0:0] probe1
.probe2(core_clk) // input wire [0:0] probe2
);
endmodule
| 7.515423 |
module top_SoC_tb ();
reg main_clk, pll_reset, core_reset;
wire [7:0] dac_out;
top_SoC uut (
main_clk,
pll_reset,
core_reset,
dac_out
);
initial begin
main_clk = 1'b0;
pll_reset = 1'b0;
core_reset = 1'b0;
#10;
pll_reset = 1'b1;
#60;
pll_reset = 1'b0;
#1400;
core_reset = 1'b1;
#50;
core_reset = 1'b0;
end
always #15.15 main_clk = ~main_clk;
initial #5000000 $finish;
endmodule
| 6.988119 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
specify
specparam TRise = 10, TFall = 15;
(S => M2) = (TRise, TFall);
endspecify
endmodule
| 7.233807 |
module StrideHandler (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_write,
input [16:0] io_in_bits_address,
input [16:0] io_in_bits_size,
input [ 2:0] io_in_bits_stride,
input io_in_bits_reverse,
input io_out_ready,
output io_out_valid,
output io_out_bits_write,
output [16:0] io_out_bits_address,
output [16:0] io_out_bits_size
);
wire handler_clock; // @[StrideHandler.scala 27:23]
wire handler_reset; // @[StrideHandler.scala 27:23]
wire handler_io_in_ready; // @[StrideHandler.scala 27:23]
wire handler_io_in_valid; // @[StrideHandler.scala 27:23]
wire handler_io_in_bits_write; // @[StrideHandler.scala 27:23]
wire [16:0] handler_io_in_bits_address; // @[StrideHandler.scala 27:23]
wire [16:0] handler_io_in_bits_size; // @[StrideHandler.scala 27:23]
wire [2:0] handler_io_in_bits_stride; // @[StrideHandler.scala 27:23]
wire handler_io_in_bits_reverse; // @[StrideHandler.scala 27:23]
wire handler_io_out_ready; // @[StrideHandler.scala 27:23]
wire handler_io_out_valid; // @[StrideHandler.scala 27:23]
wire handler_io_out_bits_write; // @[StrideHandler.scala 27:23]
wire [16:0] handler_io_out_bits_address; // @[StrideHandler.scala 27:23]
SizeAndStrideHandler handler ( // @[StrideHandler.scala 27:23]
.clock(handler_clock),
.reset(handler_reset),
.io_in_ready(handler_io_in_ready),
.io_in_valid(handler_io_in_valid),
.io_in_bits_write(handler_io_in_bits_write),
.io_in_bits_address(handler_io_in_bits_address),
.io_in_bits_size(handler_io_in_bits_size),
.io_in_bits_stride(handler_io_in_bits_stride),
.io_in_bits_reverse(handler_io_in_bits_reverse),
.io_out_ready(handler_io_out_ready),
.io_out_valid(handler_io_out_valid),
.io_out_bits_write(handler_io_out_bits_write),
.io_out_bits_address(handler_io_out_bits_address)
);
assign io_in_ready = io_in_bits_stride == 3'h0 ? io_out_ready : handler_io_in_ready; // @[StrideHandler.scala 41:32 49:14 52:19]
assign io_out_valid = io_in_bits_stride == 3'h0 ? io_in_valid : handler_io_out_valid; // @[StrideHandler.scala 41:32 50:18 61:18]
assign io_out_bits_write = io_in_bits_stride == 3'h0 ? io_in_bits_write : handler_io_out_bits_write; // @[StrideHandler.scala 41:32 44:36 55:36]
assign io_out_bits_address = io_in_bits_stride == 3'h0 ? io_in_bits_address : handler_io_out_bits_address; // @[StrideHandler.scala 41:32 47:25 58:25]
assign io_out_bits_size = io_in_bits_stride == 3'h0 ? io_in_bits_size : 17'h0; // @[StrideHandler.scala 41:32 48:22 59:22]
assign handler_clock = clock;
assign handler_reset = reset;
assign handler_io_in_valid = io_in_bits_stride == 3'h0 ? 1'h0 : io_in_valid; // @[StrideHandler.scala 37:23 41:32 52:19]
assign handler_io_in_bits_write = io_in_bits_stride == 3'h0 ? 1'h0 : io_in_bits_write; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_address = io_in_bits_stride == 3'h0 ? 17'h0 : io_in_bits_address; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_size = io_in_bits_stride == 3'h0 ? 17'h0 : io_in_bits_size; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_stride = io_in_bits_stride == 3'h0 ? 3'h0 : io_in_bits_stride; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_reverse = io_in_bits_stride == 3'h0 ? 1'h0 : io_in_bits_reverse; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_out_ready = io_in_bits_stride == 3'h0 ? 1'h0 : io_out_ready; // @[StrideHandler.scala 39:24 41:32 60:26]
endmodule
| 8.268025 |
module Demux (
output io_in_ready,
input io_in_valid,
input [15:0] io_in_bits_0,
input [15:0] io_in_bits_1,
input [15:0] io_in_bits_2,
input [15:0] io_in_bits_3,
input [15:0] io_in_bits_4,
input [15:0] io_in_bits_5,
input [15:0] io_in_bits_6,
input [15:0] io_in_bits_7,
output io_sel_ready,
input io_sel_valid,
input io_sel_bits,
input io_out_0_ready,
output io_out_0_valid,
output [15:0] io_out_0_bits_0,
output [15:0] io_out_0_bits_1,
output [15:0] io_out_0_bits_2,
output [15:0] io_out_0_bits_3,
output [15:0] io_out_0_bits_4,
output [15:0] io_out_0_bits_5,
output [15:0] io_out_0_bits_6,
output [15:0] io_out_0_bits_7,
input io_out_1_ready,
output io_out_1_valid,
output [15:0] io_out_1_bits_0,
output [15:0] io_out_1_bits_1,
output [15:0] io_out_1_bits_2,
output [15:0] io_out_1_bits_3,
output [15:0] io_out_1_bits_4,
output [15:0] io_out_1_bits_5,
output [15:0] io_out_1_bits_6,
output [15:0] io_out_1_bits_7
);
wire _GEN_19 = io_sel_bits ? io_out_1_ready : io_out_0_ready; // @[Demux.scala 34:{25,25}]
assign io_in_ready = io_sel_valid & _GEN_19; // @[Demux.scala 35:25]
assign io_sel_ready = io_in_valid & _GEN_19; // @[Demux.scala 34:25]
assign io_out_0_valid = ~io_sel_bits & (io_sel_valid & io_in_valid); // @[Demux.scala 33:{13,13} 28:15]
assign io_out_0_bits_0 = ~io_sel_bits ? $signed(
io_in_bits_0
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_0_bits_1 = ~io_sel_bits ? $signed(
io_in_bits_1
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_0_bits_2 = ~io_sel_bits ? $signed(
io_in_bits_2
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_0_bits_3 = ~io_sel_bits ? $signed(
io_in_bits_3
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_0_bits_4 = ~io_sel_bits ? $signed(
io_in_bits_4
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_0_bits_5 = ~io_sel_bits ? $signed(
io_in_bits_5
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_0_bits_6 = ~io_sel_bits ? $signed(
io_in_bits_6
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_0_bits_7 = ~io_sel_bits ? $signed(
io_in_bits_7
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_1_valid = io_sel_bits & (io_sel_valid & io_in_valid); // @[Demux.scala 33:{13,13} 28:15]
assign io_out_1_bits_0 = io_sel_bits ? $signed(
io_in_bits_0
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_1_bits_1 = io_sel_bits ? $signed(
io_in_bits_1
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_1_bits_2 = io_sel_bits ? $signed(
io_in_bits_2
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_1_bits_3 = io_sel_bits ? $signed(
io_in_bits_3
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_1_bits_4 = io_sel_bits ? $signed(
io_in_bits_4
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_1_bits_5 = io_sel_bits ? $signed(
io_in_bits_5
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_1_bits_6 = io_sel_bits ? $signed(
io_in_bits_6
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
assign io_out_1_bits_7 = io_sel_bits ? $signed(
io_in_bits_7
) : $signed(
16'sh0
); // @[Demux.scala 32:{12,12} 27:14]
endmodule
| 7.090619 |
module Mux (
output io_in_0_ready,
input io_in_0_valid,
input [15:0] io_in_0_bits_0,
input [15:0] io_in_0_bits_1,
input [15:0] io_in_0_bits_2,
input [15:0] io_in_0_bits_3,
input [15:0] io_in_0_bits_4,
input [15:0] io_in_0_bits_5,
input [15:0] io_in_0_bits_6,
input [15:0] io_in_0_bits_7,
output io_in_1_ready,
input io_in_1_valid,
input [15:0] io_in_1_bits_0,
input [15:0] io_in_1_bits_1,
input [15:0] io_in_1_bits_2,
input [15:0] io_in_1_bits_3,
input [15:0] io_in_1_bits_4,
input [15:0] io_in_1_bits_5,
input [15:0] io_in_1_bits_6,
input [15:0] io_in_1_bits_7,
output io_sel_ready,
input io_sel_valid,
input io_sel_bits,
input io_out_ready,
output io_out_valid,
output [15:0] io_out_bits_0,
output [15:0] io_out_bits_1,
output [15:0] io_out_bits_2,
output [15:0] io_out_bits_3,
output [15:0] io_out_bits_4,
output [15:0] io_out_bits_5,
output [15:0] io_out_bits_6,
output [15:0] io_out_bits_7
);
wire _GEN_17 = io_sel_bits ? io_in_1_valid : io_in_0_valid; // @[Mux.scala 58:{29,29}]
assign io_in_0_ready = ~io_sel_bits & (io_sel_valid & io_out_ready); // @[Mux.scala 60:{13,13} 52:19]
assign io_in_1_ready = io_sel_bits & (io_sel_valid & io_out_ready); // @[Mux.scala 60:{13,13} 52:19]
assign io_sel_ready = _GEN_17 & io_out_ready; // @[Mux.scala 59:26]
assign io_out_valid = io_sel_valid & _GEN_17; // @[Mux.scala 58:29]
assign io_out_bits_0 = io_sel_bits ? $signed(
io_in_1_bits_0
) : $signed(
io_in_0_bits_0
); // @[Mux.scala 57:{15,15}]
assign io_out_bits_1 = io_sel_bits ? $signed(
io_in_1_bits_1
) : $signed(
io_in_0_bits_1
); // @[Mux.scala 57:{15,15}]
assign io_out_bits_2 = io_sel_bits ? $signed(
io_in_1_bits_2
) : $signed(
io_in_0_bits_2
); // @[Mux.scala 57:{15,15}]
assign io_out_bits_3 = io_sel_bits ? $signed(
io_in_1_bits_3
) : $signed(
io_in_0_bits_3
); // @[Mux.scala 57:{15,15}]
assign io_out_bits_4 = io_sel_bits ? $signed(
io_in_1_bits_4
) : $signed(
io_in_0_bits_4
); // @[Mux.scala 57:{15,15}]
assign io_out_bits_5 = io_sel_bits ? $signed(
io_in_1_bits_5
) : $signed(
io_in_0_bits_5
); // @[Mux.scala 57:{15,15}]
assign io_out_bits_6 = io_sel_bits ? $signed(
io_in_1_bits_6
) : $signed(
io_in_0_bits_6
); // @[Mux.scala 57:{15,15}]
assign io_out_bits_7 = io_sel_bits ? $signed(
io_in_1_bits_7
) : $signed(
io_in_0_bits_7
); // @[Mux.scala 57:{15,15}]
endmodule
| 7.736456 |
module SizeHandler_3 (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_sel,
input [12:0] io_in_bits_size,
input io_out_ready,
output io_out_valid,
output io_out_bits_sel
);
wire sizeCounter_clock; // @[Counter.scala 34:19]
wire sizeCounter_reset; // @[Counter.scala 34:19]
wire sizeCounter_io_value_ready; // @[Counter.scala 34:19]
wire [12:0] sizeCounter_io_value_bits; // @[Counter.scala 34:19]
wire sizeCounter_io_resetValue; // @[Counter.scala 34:19]
wire fire = io_in_valid & io_out_ready; // @[SizeHandler.scala 32:23]
Counter_2 sizeCounter ( // @[Counter.scala 34:19]
.clock(sizeCounter_clock),
.reset(sizeCounter_reset),
.io_value_ready(sizeCounter_io_value_ready),
.io_value_bits(sizeCounter_io_value_bits),
.io_resetValue(sizeCounter_io_resetValue)
);
assign io_in_ready = sizeCounter_io_value_bits == io_in_bits_size & io_out_ready; // @[SizeHandler.scala 34:52 35:14 38:14]
assign io_out_valid = io_in_valid; // @[SizeHandler.scala 25:16]
assign io_out_bits_sel = io_in_bits_sel; // @[SizeHandler.scala 28:34]
assign sizeCounter_clock = clock;
assign sizeCounter_reset = reset;
assign sizeCounter_io_value_ready = sizeCounter_io_value_bits == io_in_bits_size ? 1'h0 : fire; // @[SizeHandler.scala 34:52 Counter.scala 36:22 SizeHandler.scala 39:32]
assign sizeCounter_io_resetValue = sizeCounter_io_value_bits == io_in_bits_size & fire; // @[SizeHandler.scala 34:52 Counter.scala 35:21 SizeHandler.scala 36:31]
endmodule
| 6.694676 |
module BurstSplitter (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [127:0] io_in_bits_data,
input io_out_ready,
output io_out_valid,
output [127:0] io_out_bits_data,
output io_out_bits_last
);
wire counter_clock; // @[Counter.scala 34:19]
wire counter_reset; // @[Counter.scala 34:19]
wire counter_io_value_ready; // @[Counter.scala 34:19]
wire [7:0] counter_io_value_bits; // @[Counter.scala 34:19]
wire counter_io_resetValue; // @[Counter.scala 34:19]
wire _counter_io_resetValue_T = io_out_ready & io_out_valid; // @[Decoupled.scala 50:35]
Counter_10 counter ( // @[Counter.scala 34:19]
.clock(counter_clock),
.reset(counter_reset),
.io_value_ready(counter_io_value_ready),
.io_value_bits(counter_io_value_bits),
.io_resetValue(counter_io_resetValue)
);
assign io_control_ready = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[MemBoundarySplitter.scala 45:51 48:22 52:22]
assign io_in_ready = io_control_valid & io_out_ready; // @[MemBoundarySplitter.scala 41:35]
assign io_out_valid = io_control_valid & io_in_valid; // @[MemBoundarySplitter.scala 40:36]
assign io_out_bits_data = io_in_bits_data; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_last = counter_io_value_bits == io_control_bits; // @[MemBoundarySplitter.scala 45:30]
assign counter_clock = clock;
assign counter_reset = reset;
assign counter_io_value_ready = counter_io_value_bits == io_control_bits ? 1'h0 : _counter_io_resetValue_T; // @[Counter.scala 36:22 MemBoundarySplitter.scala 45:51 51:28]
assign counter_io_resetValue = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[Counter.scala 35:21 MemBoundarySplitter.scala 45:51 47:27]
endmodule
| 7.518602 |
module BurstSplitter_1 (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [ 5:0] io_in_bits_id,
input [127:0] io_in_bits_data,
input [ 15:0] io_in_bits_strb,
input io_out_ready,
output io_out_valid,
output [ 5:0] io_out_bits_id,
output [127:0] io_out_bits_data,
output [ 15:0] io_out_bits_strb,
output io_out_bits_last
);
wire counter_clock; // @[Counter.scala 34:19]
wire counter_reset; // @[Counter.scala 34:19]
wire counter_io_value_ready; // @[Counter.scala 34:19]
wire [7:0] counter_io_value_bits; // @[Counter.scala 34:19]
wire counter_io_resetValue; // @[Counter.scala 34:19]
wire _counter_io_resetValue_T = io_out_ready & io_out_valid; // @[Decoupled.scala 50:35]
Counter_10 counter ( // @[Counter.scala 34:19]
.clock(counter_clock),
.reset(counter_reset),
.io_value_ready(counter_io_value_ready),
.io_value_bits(counter_io_value_bits),
.io_resetValue(counter_io_resetValue)
);
assign io_control_ready = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[MemBoundarySplitter.scala 45:51 48:22 52:22]
assign io_in_ready = io_control_valid & io_out_ready; // @[MemBoundarySplitter.scala 41:35]
assign io_out_valid = io_control_valid & io_in_valid; // @[MemBoundarySplitter.scala 40:36]
assign io_out_bits_id = io_in_bits_id; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_data = io_in_bits_data; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_strb = io_in_bits_strb; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_last = counter_io_value_bits == io_control_bits; // @[MemBoundarySplitter.scala 45:30]
assign counter_clock = clock;
assign counter_reset = reset;
assign counter_io_value_ready = counter_io_value_bits == io_control_bits ? 1'h0 : _counter_io_resetValue_T; // @[Counter.scala 36:22 MemBoundarySplitter.scala 45:51 51:28]
assign counter_io_resetValue = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[Counter.scala 35:21 MemBoundarySplitter.scala 45:51 47:27]
endmodule
| 7.518602 |
module Filter (
output io_control_ready,
input io_control_valid,
input io_control_bits,
output io_in_ready,
input io_in_valid,
input io_out_ready,
output io_out_valid
);
assign io_control_ready = io_control_bits ? io_in_valid & io_out_ready : io_in_valid; // @[MemBoundarySplitter.scala 71:25 74:22 78:22]
assign io_in_ready = io_control_bits ? io_control_valid & io_out_ready : io_control_valid; // @[MemBoundarySplitter.scala 71:25 73:17 77:17]
assign io_out_valid = io_control_bits & (io_control_valid & io_in_valid); // @[MemBoundarySplitter.scala 71:25 72:18 76:18]
endmodule
| 7.016323 |
module Serializer (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [63:0] io_in_bits_0,
input [63:0] io_in_bits_1,
input io_out_ready,
output io_out_valid,
output [63:0] io_out_bits,
input io_error
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
reg [63:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
reg [63:0] bits_0; // @[Serializer.scala 23:22]
reg [63:0] bits_1; // @[Serializer.scala 23:22]
reg valid; // @[Serializer.scala 24:22]
wire _T = valid & io_out_ready; // @[Serializer.scala 26:48]
reg ctr; // @[Counter.scala 62:40]
wire wrap = _T & ctr; // @[Counter.scala 120:{16,23}]
wire [127:0] _T_1 = {io_in_bits_1, io_in_bits_0}; // @[Serializer.scala 34:34]
assign io_in_ready = ~valid | wrap; // @[Serializer.scala 30:25]
assign io_out_valid = valid; // @[Serializer.scala 28:16]
assign io_out_bits = ctr ? bits_1 : bits_0; // @[Serializer.scala 29:{15,15}]
always @(posedge clock) begin
if (reset) begin // @[Serializer.scala 23:22]
bits_0 <= 64'h0; // @[Serializer.scala 23:22]
end else if (io_in_ready) begin // @[Serializer.scala 32:21]
if (io_in_valid) begin // @[Serializer.scala 33:23]
bits_0 <= _T_1[63:0]; // @[Serializer.scala 34:12]
end
end
if (reset) begin // @[Serializer.scala 23:22]
bits_1 <= 64'h0; // @[Serializer.scala 23:22]
end else if (io_in_ready) begin // @[Serializer.scala 32:21]
if (io_in_valid) begin // @[Serializer.scala 33:23]
bits_1 <= _T_1[127:64]; // @[Serializer.scala 34:12]
end
end
if (reset) begin // @[Serializer.scala 24:22]
valid <= 1'h0; // @[Serializer.scala 24:22]
end else if (io_in_ready) begin // @[Serializer.scala 32:21]
valid <= io_in_valid;
end
if (reset) begin // @[Counter.scala 62:40]
ctr <= 1'h0; // @[Counter.scala 62:40]
end else if (_T) begin // @[Counter.scala 120:16]
ctr <= ctr + 1'h1; // @[Counter.scala 78:15]
end
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
bits_0 = _RAND_0[63:0];
_RAND_1 = {2{`RANDOM}};
bits_1 = _RAND_1[63:0];
_RAND_2 = {1{`RANDOM}};
valid = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
ctr = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.666069 |
module StrictDecoupledTransmission (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [127:0] io_in_bits,
input io_out_ready,
output io_out_valid,
output [ 63:0] io_out_bits,
input io_error
);
wire ser_clock; // @[Transmission.scala 49:30]
wire ser_reset; // @[Transmission.scala 49:30]
wire ser_io_in_ready; // @[Transmission.scala 49:30]
wire ser_io_in_valid; // @[Transmission.scala 49:30]
wire [63:0] ser_io_in_bits_0; // @[Transmission.scala 49:30]
wire [63:0] ser_io_in_bits_1; // @[Transmission.scala 49:30]
wire ser_io_out_ready; // @[Transmission.scala 49:30]
wire ser_io_out_valid; // @[Transmission.scala 49:30]
wire [63:0] ser_io_out_bits; // @[Transmission.scala 49:30]
wire ser_io_error; // @[Transmission.scala 49:30]
Serializer ser ( // @[Transmission.scala 49:30]
.clock(ser_clock),
.reset(ser_reset),
.io_in_ready(ser_io_in_ready),
.io_in_valid(ser_io_in_valid),
.io_in_bits_0(ser_io_in_bits_0),
.io_in_bits_1(ser_io_in_bits_1),
.io_out_ready(ser_io_out_ready),
.io_out_valid(ser_io_out_valid),
.io_out_bits(ser_io_out_bits),
.io_error(ser_io_error)
);
assign io_in_ready = ser_io_in_ready; // @[package.scala 16:17 Transmission.scala 50:15]
assign io_out_valid = ser_io_out_valid; // @[Transmission.scala 51:12]
assign io_out_bits = ser_io_out_bits; // @[Transmission.scala 51:12]
assign ser_clock = clock;
assign ser_reset = reset;
assign ser_io_in_valid = io_in_valid; // @[package.scala 16:17 18:13]
assign ser_io_in_bits_0 = io_in_bits[63:0]; // @[package.scala 17:30]
assign ser_io_in_bits_1 = io_in_bits[127:64]; // @[package.scala 17:30]
assign ser_io_out_ready = io_out_ready; // @[Transmission.scala 51:12]
assign ser_io_error = io_error; // @[Transmission.scala 52:18]
endmodule
| 7.043144 |
module top_speed_mac (
clock_sys,
reset,
hall_effect,
speed,
toggle
);
localparam max_count = 435;
parameter dwidth = 11;
input clock_sys;
input reset;
input [2:0] hall_effect;
output toggle;
output [dwidth-1:0] speed;
reg toggle;
wire [dwidth-1:0] count;
wire [dwidth-1:0] commutation_tot;
wire [dwidth-1:0] reg_commutation;
wire clock_1;
wire clock_2;
clk_div #(
.n(13)
) U0 (
.clk_sys(clock_sys),
.reset(reset),
.clock_div(clock_2)
);
counter #(
.n(dwidth)
) U1 (
.clock(clock_2),
.reset(reset),
.reset_to_zero(1'b0),
.count(count)
);
speed_measurement U2 (
.clock(clock_2),
.reset(reset),
.hall_effect(hall_effect),
.mac_out(clock_1)
);
counter #(
.n(dwidth)
) U3 (
.clock(clock_1),
.reset(reset),
.reset_to_zero(toggle),
.count(commutation_tot)
);
D_ff #(
.n(dwidth)
) U4 (
.clock(clock_2),
.reset(reset),
.enable(count == (max_count - 1)),
.D(commutation_tot),
.Q(reg_commutation)
);
always @(posedge clock_2, negedge reset)
if (!reset) toggle <= 1'b0;
else if (count == (max_count - 1)) toggle <= 1'b1;
else toggle <= 1'b0;
rpm_lut U5 (
.D(reg_commutation),
.Q(speed)
);
endmodule
| 7.85582 |
module top_spi_final (
data_inp,
load,
clk,
rst,
ss0,
ss1,
ss2,
mosi,
master_data1,
slave_data1,
slave_data2,
slave_data3
);
input clk, ss0, ss1, ss2, load, rst; //Declaring the required inputs: Clock, select ports for the three slaves, a load, and reset.
input [0:7] data_inp; //Input to be loaded to the master.
output reg mosi; //MOSI is the output taken as the last bit of master that gets transferred to the slave.
//wire [0:7] master_data;
output reg [0:7] master_data1, slave_data1, slave_data2, slave_data3; //Defining the data in master and the three slaves as the output of 8 bits.
always @(posedge clk) begin
if (rst) begin
master_data1 <= 8'b0; //On reset, set everything to zero!
slave_data1 <= 8'b0;
slave_data2 <= 8'b0;
slave_data3 <= 8'b0;
mosi <= 0;
end
if (load) begin
master_data1 <= data_inp; //On loading, load the input data to the master.
mosi <= master_data1[7];
end
if(ss0 == 1) begin //When ss0 is high, it right-shifts the master data and slave data until clock edge is found and ss0 is high.
slave_data1[0] <= master_data1[7];
master_data1[0] <= slave_data1[7];
master_data1[1:7] <= master_data1[0:6];
slave_data1[1:7] <= slave_data1[0:6];
mosi <= master_data1[7];
end
else if(ss1 == 1) begin //When ss1 is high, it right-shifts the master data and slave data until clock edge is found and ss1 is high.
slave_data2[0] <= master_data1[7];
master_data1[0] <= slave_data2[7];
master_data1[1:7] <= master_data1[0:6];
slave_data2[1:7] <= slave_data2[0:6];
mosi <= master_data1[7];
end
else if(ss2 == 1) begin //When ss1 is high, it right-shifts the master data and slave data until clock edge is found and ss2 is high.
slave_data3[0] <= master_data1[7];
master_data1[0] <= slave_data3[7];
master_data1[1:7] <= master_data1[0:6];
slave_data3[1:7] <= slave_data3[0:6];
mosi <= master_data1[7];
end
end
endmodule
| 7.323644 |
module top_spi_function #(
parameter CLK_CNT_HALF = 20,
parameter CLK_CNT_HALF_WIDTH = 5,
parameter MODE = 2'b00,
parameter CPOL = MODE[1],
parameter CPHA = MODE[0]
) (
input clk,
input rst_n,
output [7:0] om_data_master,
output [7:0] om_data_slave
);
wire [7:0] im_data_master;
wire [7:0] im_data_slave;
wire MISO_spi, MOSI_spi, SCLK_spi;
wire om_send_finish_master, om_receive_finish_master;
wire om_send_finish_slave, om_receive_finish_slave;
reg finish1, finish2, finish3, finish4;
reg im_work_en;
wire finish_wait;
wire finish_end;
wire close;
assign im_data_master = "a";
assign im_data_slave = "b";
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
finish1 <= 1'b0;
end else if (om_send_finish_master) begin
finish1 <= 1'b1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
finish2 <= 1'b0;
end else if (om_receive_finish_master) begin
finish2 <= 1'b1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
finish3 <= 1'b0;
end else if (om_send_finish_slave) begin
finish3 <= 1'b1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
finish4 <= 1'b0;
end else if (om_receive_finish_slave) begin
finish4 <= 1'b1;
end
end
assign finish_wait = finish1 & finish2 & finish3 & finish4;
assign finish_end=om_send_finish_master | om_send_finish_slave
| om_receive_finish_master | om_receive_finish_slave;
assign close = (finish_wait && !finish_end);
//work forms
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
im_work_en <= 1'b0;
end else if (close) begin
im_work_en <= 1'b0;
end else begin
im_work_en <= 1'b1;
end
end
L1_spi_master_v2 #(
.CLK_CNT_HALF(CLK_CNT_HALF),
.CLK_CNT_HALF_WIDTH(CLK_CNT_HALF_WIDTH),
.MODE(MODE)
) top_U1 (
.clk (clk),
.rst_n(rst_n),
.im_work_en(im_work_en),
.im_data(im_data_master),
.om_data(om_data_master),
.im_MISO_spi(MISO_spi),
.om_MOSI_spi(MOSI_spi),
.om_SCLK_spi(SCLK_spi),
.om_send_finish(om_send_finish_master),
.om_receive_finish(om_receive_finish_master)
);
L1_spi_slave #(
.CLK_CNT_HALF(CLK_CNT_HALF),
.CLK_CNT_HALF_WIDTH(CLK_CNT_HALF_WIDTH),
.MODE(MODE)
) top_U2 (
.clk (clk),
.rst_n(rst_n),
.im_data(im_data_slave),
.om_data(om_data_slave),
.im_MOSI_spi(MOSI_spi),
.im_SCLK_spi(SCLK_spi),
.om_MISO_spi(MISO_spi),
.om_send_finish(om_send_finish_slave),
.om_receive_finish(om_receive_finish_slave)
);
endmodule
| 8.166379 |
module top (
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
output wire VGA_HS_O, // horizontal sync output
output wire VGA_VS_O, // vertical sync output
output wire [3:0] VGA_R, // 4-bit VGA red output
output wire [3:0] VGA_G, // 4-bit VGA green output
output wire [3:0] VGA_B // 4-bit VGA blue output
);
wire rst = ~RST_BTN; // reset is active low on Arty & Nexys Video
// wire rst = RST_BTN; // reset is active high on Basys3 (BTNC)
// generate a 25 MHz pixel strobe
reg [15:0] cnt;
reg pix_stb;
always @(posedge CLK) {pix_stb, cnt} <= cnt + 16'h4000; // divide by 4: (2^16)/4 = 0x4000
wire [9:0] x; // current pixel x position: 10-bit value: 0-1023
wire [8:0] y; // current pixel y position: 9-bit value: 0-511
vga640x480 display (
.i_clk(CLK),
.i_pix_stb(pix_stb),
.i_rst(rst),
.o_hs(VGA_HS_O),
.o_vs(VGA_VS_O),
.o_x(x),
.o_y(y)
);
// Four overlapping squares
wire sq_a, sq_b, sq_c, sq_d;
assign sq_a = ((x > 120) & (y > 40) & (x < 280) & (y < 200)) ? 1 : 0;
assign sq_b = ((x > 200) & (y > 120) & (x < 360) & (y < 280)) ? 1 : 0;
assign sq_c = ((x > 280) & (y > 200) & (x < 440) & (y < 360)) ? 1 : 0;
assign sq_d = ((x > 360) & (y > 280) & (x < 520) & (y < 440)) ? 1 : 0;
assign VGA_R[3] = sq_b; // square b is red
assign VGA_G[3] = sq_a | sq_d; // squares a and d are green
assign VGA_B[3] = sq_c; // square c is blue
endmodule
| 7.233807 |
module top (
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
output wire VGA_HS_O, // horizontal sync output
output wire VGA_VS_O, // vertical sync output
output wire [3:0] VGA_R, // 4-bit VGA red output
output wire [3:0] VGA_G, // 4-bit VGA green output
output wire [3:0] VGA_B // 4-bit VGA blue output
);
wire rst = ~RST_BTN; // reset is active low on Arty & Nexys Video
// wire rst = RST_BTN; // reset is active high on Basys3 (BTNC)
// generate a 40 MHz pixel strobe
reg [15:0] cnt;
reg pix_stb;
always @(posedge CLK) {pix_stb, cnt} <= cnt + 16'h6666; // divide by 2.5: (2^16)/2.5 = 0x6666
wire [10:0] x; // current pixel x position: 11-bit value: 0-2047
wire [ 9:0] y; // current pixel y position: 10-bit value: 0-1023
vga800x600 display (
.i_clk(CLK),
.i_pix_stb(pix_stb),
.i_rst(rst),
.o_hs(VGA_HS_O),
.o_vs(VGA_VS_O),
.o_x(x),
.o_y(y)
);
// Six overlapping squares
wire sq_a, sq_b, sq_c, sq_d, sq_e, sq_f;
assign sq_a = ((x > 120) & (y > 20) & (x < 280) & (y < 180)) ? 1 : 0;
assign sq_b = ((x > 200) & (y > 100) & (x < 360) & (y < 260)) ? 1 : 0;
assign sq_c = ((x > 280) & (y > 180) & (x < 440) & (y < 340)) ? 1 : 0;
assign sq_d = ((x > 360) & (y > 260) & (x < 520) & (y < 420)) ? 1 : 0;
assign sq_e = ((x > 440) & (y > 340) & (x < 600) & (y < 500)) ? 1 : 0;
assign sq_f = ((x > 520) & (y > 420) & (x < 680) & (y < 580)) ? 1 : 0;
assign VGA_R[3] = sq_b | sq_e; // squares b and e are red
assign VGA_G[3] = sq_a | sq_d; // squares a and d are green
assign VGA_B[3] = sq_c | sq_f; // squares c and f are blue
endmodule
| 7.233807 |
module TOP_stim ();
reg CLK;
reg RESET;
wire [7:0] rom_data;
wire [7:0] rom_address;
wire [7:0] BUS_DATA;
wire [7:0] BUS_ADDR;
wire bus_interrupts_raise_from_timer;
wire [1:0] bus_interrupts_raise;
wire [1:0] bus_interrupts_ack;
assign bus_interrupts_raise = {bus_interrupts_raise_from_timer, 1'b0};
wire bus_we;
wire IR_LED;
TopLevel wrap (
//Standard Signals
.CLK(CLK),
.RESET(RESET),
.switch(0),
//IRTransmitter
.IR_LED(IR_LED)
);
Processor microprocessor (
.CLK(CLK),
.RESET(RESET),
.BUS_DATA(BUS_DATA),
.BUS_ADDR(BUS_ADDR),
.BUS_WE(bus_we),
.ROM_ADDRESS(rom_address),
.ROM_DATA(rom_data),
.BUS_INTERRUPTS_RAISE(bus_interrupts_raise),
.BUS_INTERRUPTS_ACK(bus_interrupts_ack)
);
Timer timer (
.CLK(CLK),
.RESET(RESET),
.BUS_DATA(BUS_DATA),
.BUS_ADDR(BUS_ADDR),
.BUS_WE(bus_we),
.BUS_INTERRUPT_RAISE(bus_interrupts_raise_from_timer),
.BUS_INTERRUPT_ACK(bus_interrupts_ack[1])
);
ROM rom (
.CLK (CLK),
.DATA(rom_data),
.ADDR(rom_address)
);
RAM ram (
.CLK(CLK),
.BUS_DATA(BUS_DATA),
.BUS_ADDR(BUS_ADDR),
.BUS_WE(bus_we)
);
initial begin
CLK = 0;
//100MHz clock rate
forever #5 CLK = ~CLK;
end
initial begin
RESET = 0;
#5 RESET = 1;
#5 RESET = 0;
end
endmodule
| 6.560326 |
module top_STM (
input rst_n
, input clk
, input usr_en
, input display_finish
, input edit_finish
, input check_finish
, input check_4
, output reg edit_en
, output reg display_en
, output reg check_en
, output reg [2:0] row_addr_sel
);
reg [2:0] state;
reg [2:0] next_state;
/*
wire display_finish;
wire edit_finish;
wire check_4;
wire check_finish;
reg edit_en;
reg display_en;
reg check_en;
reg[2:0] row_addr_sel;*/
always @(negedge rst_n or posedge clk) begin
if (!rst_n) state <= 0;
else begin
state <= next_state;
end
end
always @(*) begin
case (state)
0: begin
next_state = (usr_en & display_finish) ? 1 : 0;
end
1: begin
next_state = (edit_finish) ? 2 : 1;
end
2: begin
next_state = (check_4) ? 3 : (check_finish) ? 4 : 2;
end
3: begin
next_state = 3;
end
4: begin
next_state = (!usr_en) ? 0 : 4;
end
default: begin
next_state = 0;
end
endcase
end // always
always @(*) begin
case (state)
0: begin
edit_en = 0;
display_en = ~(usr_en & display_finish);
check_en = 0;
row_addr_sel = 1;
end
1: begin
edit_en = ~edit_finish;
display_en = 0;
check_en = 0;
row_addr_sel = 2;
end
2: begin
edit_en = 0;
display_en = 0;
check_en = ~(check_4 | check_finish);
row_addr_sel = 4;
end
3: begin
edit_en = 0;
display_en = 1;
check_en = 0;
row_addr_sel = 1;
end
4: begin
edit_en = 0;
display_en = 1;
check_en = 0;
row_addr_sel = 1;
end
default: begin
edit_en = 0;
display_en = 1;
check_en = 0;
row_addr_sel = 1;
end
endcase
end // always
endmodule
| 6.92545 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
parameter FILE_OUT = "\"file1.txt\"";
reg [8*10:1] stringvar;
reg [ 7:0] q;
initial begin
stringvar = "Starting";
q <= '1;
end
endmodule
| 7.233807 |
module top_stripes_node (
clk, // Main clock
reset, // Reset
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_nbout, // Input from NBOut
i_first_cycle,
i_precision,
i_mux_sel,
i_max,
i_load,
o_to_nbout
);
parameter N = 16;
parameter Tn = 16;
parameter TnxTn = Tn * Tn;
parameter Tw = 16;
parameter ADDR_WIDTH = 6;
parameter N_OPS = 1;
//----------- Input Ports ---------------//
input clk;
input reset;
input i_max;
// i_inputs is a vector of Tn (16) values, 16-bits each
input [((N*Tn) - 1):0] i_inputs;
input [Tw - 1 : 0] i_load;
// i_synapses is a matrix of Tn x Tn (16x16=256) values, 16-bits each (Row-major).
input [((N*TnxTn) - 1):0] i_synapses;
input [(N*Tn*Tw)-1:0] i_nbout;
input i_first_cycle;
input [4:0] i_precision;
input [3:0] i_mux_sel;
//----------- Output Ports ---------------//
output [((N*Tn) - 1):0] o_to_nbout;
//----------- Internal Signals --------------//
// Wires
wire [(N*Tw*Tn)-1:0] nfu1_2_serial_out;
wire [ (N*Tn)-1:0] mux_to_nbout;
/*
reg i_max_reg; //
reg [((N*Tn) - 1):0] i_inputs_reg; //
reg [((N*TnxTn) - 1):0] i_synapses_reg; //
reg[(N*Tn*Tw)-1:0] i_nbout_reg; //
reg i_first_cycle_reg; //
reg [4:0] i_precision_reg;
reg[3:0] i_mux_sel_reg;
reg [((N*Tn) - 1):0] o_to_nbout_reg; //
*/
//------------- Code Start -----------------//
//assign o_to_nbout = o_to_nbout_reg;
assign o_to_nbout = mux_to_nbout;
//--------------------------------------------------//
//-------------- Main Pipeline Stages --------------//
//--------------------------------------------------//
/*
always @(posedge clk) begin
i_inputs_reg <= i_inputs;
i_synapses_reg <= i_synapses;
i_nbout_reg <= i_nbout;
i_first_cycle_reg <= i_first_cycle;
i_precision_reg <= i_precision;
i_mux_sel_reg <= i_mux_sel;
i_max_reg <= i_max;
o_to_nbout_reg <= mux_to_nbout;
end
*/
// NFU_1_2_serial_pipe
/*
nfu_1_2_serial_pipe MAIN_PIPE_STAGE (
clk,
reset,
i_first_cycle_reg,
i_precision_reg,
i_max_reg,
i_inputs_reg,
i_synapses_reg,
i_nbout_reg,
nfu1_2_serial_out
);
*/
nfu_1_2_serial_pipe MAIN_PIPE_STAGE (
clk,
reset,
i_first_cycle,
i_precision,
i_max,
i_load,
i_inputs,
i_synapses,
i_nbout,
nfu1_2_serial_out
);
genvar i;
generate
for (i = 0; i < Tn; i = i + 1) begin : MUX
mux_16_to_1_v2 MUX16_1 (
i_mux_sel,
nfu1_2_serial_out[(i+1)*Tn*N-1 : i*Tn*N],
mux_to_nbout[(i+1)*N-1 : i*N]
);
end
endgenerate
//--------------------------------------------------//
//--------------------------------------------------//
//--------------------------------------------------//
endmodule
| 7.061583 |
module top_stripes_node (
clk, // Main clock
reset, // Reset
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_nbout, // Input from NBOut
i_first_cycle,
i_precision,
i_mux_sel,
i_maxpool,
i_load,
o_to_bus
);
parameter N = 16;
parameter Tn = 1;
parameter Tw = 16;
parameter Ti = 16;
parameter ADDR_WIDTH = 6;
parameter N_OPS = 1;
parameter BIT_IDX = 4;
//----------- Input Ports ---------------//
input clk;
input reset;
input i_maxpool;
// i_inputs is a vector of Tn (16) values, 16-bits each
input [((N*Ti) - 1):0] i_inputs;
input [Tw - 1 : 0] i_load;
// i_synapses is a matrix of Tn x Tn (16x16=256) values, 16-bits each (Row-major).
input [((N*Tn*Ti) - 1):0] i_synapses;
input [(N*Tn*Tw)-1:0] i_nbout;
input i_first_cycle;
input [4:0] i_precision;
input [3:0] i_mux_sel;
// control signals for NFU3
input i_load_coef;
input [((2*N)-1):0] i_coef;
// control signals for rounder
input [N-1:0] i_max;
input [N-1:0] i_min;
input [BIT_IDX-1:0] i_offset;
//----------- Output Ports ---------------//
//output [((N*Tn) - 1):0] o_to_bus;
output [((N*Tw*Tn) - 1):0] o_to_bus;
//----------- Internal Signals --------------//
// Wires
wire [(N*Tw*Tn)-1:0] nfu1_2_serial_out;
wire [ (N*Tn)-1:0] mux_out;
/*
reg i_max_reg; //
reg [((N*Tn) - 1):0] i_inputs_reg; //
reg [((N*TnxTn) - 1):0] i_synapses_reg; //
reg[(N*Tn*Tw)-1:0] i_nbout_reg; //
reg i_first_cycle_reg; //
reg [4:0] i_precision_reg;
reg[3:0] i_mux_sel_reg;
reg [((N*Tn) - 1):0] o_to_nbout_reg; //
*/
//------------- Code Start -----------------//
//assign o_to_nbout = o_to_nbout_reg;
//assign o_to_bus = mux_to_nbout;
assign o_to_bus = nfu1_2_serial_out;
//--------------------------------------------------//
//-------------- Main Pipeline Stages --------------//
//--------------------------------------------------//
/*
always @(posedge clk) begin
i_inputs_reg <= i_inputs;
i_synapses_reg <= i_synapses;
i_nbout_reg <= i_nbout;
i_first_cycle_reg <= i_first_cycle;
i_precision_reg <= i_precision;
i_mux_sel_reg <= i_mux_sel;
i_max_reg <= i_max;
o_to_nbout_reg <= mux_to_nbout;
end
*/
nfu_1_2_serial_pipe_slice MAIN_PIPE_STAGE (
clk,
reset,
i_first_cycle,
i_precision,
i_maxpool,
i_load,
i_inputs,
i_synapses,
i_nbout,
nfu1_2_serial_out
);
//--------------------------------------------------//
//--------------------------------------------------//
//--------------------------------------------------//
endmodule
| 7.061583 |
module top_stripes_node_slice (
clk, // Main clock
reset, // Reset
i_inputs, // Inputs from eDRAM to NBin
i_synapses, // Inputs from SB
i_nbout, // Input from NBOut
i_first_cycle,
i_precision,
// i_mux_sel,
i_maxpool,
i_load,
o_to_bus
);
parameter N = 16;
parameter Tn = 1;
parameter Tw = 16;
parameter Ti = 16;
parameter ADDR_WIDTH = 6;
parameter N_OPS = 1;
parameter BIT_IDX = 4;
//----------- Input Ports ---------------//
input clk;
input reset;
input i_maxpool;
// i_inputs is a vector of Tn (16) values, 16-bits each
input [((N*Ti) - 1):0] i_inputs;
input [Tw - 1 : 0] i_load;
// i_synapses is a matrix of Tn x Tn (16x16=256) values, 16-bits each (Row-major).
input [((N*Tn*Ti) - 1):0] i_synapses;
input [(N*Tn*Tw)-1:0] i_nbout;
input i_first_cycle;
input [4:0] i_precision;
// input [3:0] i_mux_sel;
// control signals for NFU3
// input i_load_coef;
// input [((2*N)-1):0] i_coef;
// control signals for rounder
// input [N-1:0] i_max;
// input [N-1:0] i_min;
// input [BIT_IDX-1:0] i_offset;
//----------- Output Ports ---------------//
//output [((N*Tn) - 1):0] o_to_bus;
output [((N*Tw*Tn) - 1):0] o_to_bus;
//----------- Internal Signals --------------//
// Wires
wire [(N*Tw*Tn)-1:0] nfu1_2_serial_out;
wire [ (N*Tn)-1:0] mux_out;
/*
reg i_max_reg; //
reg [((N*Tn) - 1):0] i_inputs_reg; //
reg [((N*TnxTn) - 1):0] i_synapses_reg; //
reg[(N*Tn*Tw)-1:0] i_nbout_reg; //
reg i_first_cycle_reg; //
reg [4:0] i_precision_reg;
reg[3:0] i_mux_sel_reg;
reg [((N*Tn) - 1):0] o_to_nbout_reg; //
*/
//------------- Code Start -----------------//
//assign o_to_nbout = o_to_nbout_reg;
//assign o_to_bus = mux_to_nbout;
assign o_to_bus = nfu1_2_serial_out;
//--------------------------------------------------//
//-------------- Main Pipeline Stages --------------//
//--------------------------------------------------//
/*
always @(posedge clk) begin
i_inputs_reg <= i_inputs;
i_synapses_reg <= i_synapses;
i_nbout_reg <= i_nbout;
i_first_cycle_reg <= i_first_cycle;
i_precision_reg <= i_precision;
i_mux_sel_reg <= i_mux_sel;
i_max_reg <= i_max;
o_to_nbout_reg <= mux_to_nbout;
end
*/
nfu_1_2_serial_pipe_slice_regfix MAIN_PIPE_STAGE (
clk,
reset,
i_first_cycle,
i_precision,
i_maxpool,
i_load,
i_inputs,
i_synapses,
i_nbout,
nfu1_2_serial_out
);
//--------------------------------------------------//
//--------------------------------------------------//
//--------------------------------------------------//
endmodule
| 7.061583 |
module top_serial_pipe (
clk,
reset,
i_first_cycle,
i_max,
i_load,
i_precision,
i_neurons,
i_synapses,
i_nbout,
o_nfu2
);
parameter N = 16; // Synapse bits
parameter Ti = 16; // neuron tiling
parameter Tn = 16; // synapse tiling
parameter Tw = 16; // Window tiling, number of windows processed in parallel
input clk;
input reset;
input i_first_cycle;
input i_max;
input i_load;
input [4:0] i_precision;
input [Ti-1:0] i_neurons;
//input [Ti-1:0][N-1:0] i_synapses;
input [Ti*N-1:0] i_synapses;
input [N-1:0] i_nbout;
output [N-1:0] o_nfu2;
reg [N-1:0] o_nfu2_out;
assign o_nfu2 = o_nfu2_out;
serial_ip_pipe SINGLE_TILE (
clk,
reset,
i_first_cycle,
i_max,
i_load,
i_precision,
i_neurons,
i_synapses,
i_nbout,
o_nfu2_out
);
endmodule
| 7.912607 |
module Top_Student_Simulation ();
reg sw0;
reg sw1;
reg sw2;
reg sw3;
reg J_MIC3_Pin3; // Connect from this signal to Audio_Capture.v
wire J_MIC3_Pin1; // Connect to this signal from Audio_Capture.v
wire J_MIC3_Pin4;
wire [15:0] led;
wire [3:0] an;
wire [7:0] seg;
reg CLK;
reg BTNC;
reg BTNL;
reg BTNR;
wire OLED_cs, OLED_sdin, OLED_sclk, OLED_dcn, OLED_resn, OLED_vccen, OLED_pmoden;
Top_Student dut (
sw0,
sw1,
sw2,
J_MIC3_Pin3, // Connect from this signal to Audio_Capture.v
J_MIC3_Pin1, // Connect to this signal from Audio_Capture.v
J_MIC3_Pin4,
led,
an,
seg,
CLK,
BTNC,
BTNL,
BTNR,
OLED_cs,
OLED_sdin,
OLED_sclk,
OLED_dcn,
OLED_resn,
OLED_vccen,
OLED_pmoden
);
initial begin
sw0 = 1;
sw1 = 0;
sw2 = 0;
sw3 = 1;
CLK = 0;
BTNC = 0;
BTNL = 0;
BTNR = 0;
J_MIC3_Pin3 = 0;
end
always begin
CLK = ~CLK;
#1;
end
endmodule
| 7.725913 |
module top (
input x,
input y,
input cin,
output A,
output cout
);
assign cout = cin % y;
assign A = cin - x;
endmodule
| 7.233807 |
module top_subbyte (
//input
input wire clk,
input wire rst_n,
input wire [127:0] data_in,
input wire start_in,
input wire en_de,
//output
output wire [127:0] data_out,
output wire ready_out
);
//internal wires
wire [7:0] sbox_in;
wire [7:0] sbox_out;
wire ce, re;
subbyte aes_subbyte (
.clk (clk),
.rst_n (rst_n),
.data_in (data_in),
.sbox_out (sbox_out),
.data_out (data_out),
.sbox_in (sbox_in),
.sbox_en_de_in(),
.ce (ce),
.re (re),
.ready_out (ready_out),
.start_in (start_in),
.en_de (en_de)
);
sbox_rom aes_sbox (
.clk (clk),
.addr (sbox_in),
.chip_en (ce),
.read_en (re),
.data (sbox_out)
);
endmodule
| 7.404725 |
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
wire y,a,b;
buf (supply1) g1 (y, a);
buf (supply0) g2 (y, b);
endmodule
| 6.662049 |
module top_SW(
input button,
input reset,
input clk,
output [6:0] cathode,
output [3:0] anode,
output dp);
wire [1:0] refresh_signal;
wire main_clk, refresh_clk;
wire [3:0] milli_zero, milli_one, sec_zero, sec_one;
wire [3:0] final;
wire [7:0] mid_milli, mid_sec;
SW_Clk_Divide main(clk, main_clk);
SW_Refresh_Clk Refresh(clk, refresh_clk);
refresh_counter counter(refresh_clk, refresh_signal);
SW Stopwatch(main_clk, reset, button, mid_milli, mid_sec);
assign milli_zero = mid_milli[3:0];
assign milli_one = mid_milli[7:4];
assign sec_zero = mid_sec[3:0];
assign sec_one = mid_sec[7:4];
main_controller Boss(milli_zero, milli_one, sec_zero, sec_one, final, refresh_signal);
cathode_controller c(final, cathode);
anode_controller anode_signal(refresh_signal, anode, dp);
endmodule
| 6.934274 |
module: top_single
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_s_test;
// Inputs
reg clk;
reg rst;
reg [7:0] address;
reg start;
reg [7:0] write_data;
reg read_operation;
// Outputs
wire cache_busy;
wire [7:0] read_data;
// Instantiate the Unit Under Test (UUT)
top_single uut (
.clk(clk),
.rst(rst),
.address(address),
.start(start),
.write_data(write_data),
.read_operation(read_operation),
.cache_busy(cache_busy),
.read_data(read_data)
);
always #1 clk=~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
address = 0;
start = 0;
write_data = 0;
read_operation = 0;
#12
rst=0;
start=1;
read_operation = 1;
address = 8'd11;
#2
start=0;
#14
start=1;
read_operation = 0;
address = 8'd10;
write_data = 8'd7;
#2
start=0;
#10
start=1;
read_operation = 1;
address = 8'd10;
#2
start=0;
#8
start=1;
read_operation = 0;
address = 8'd10;
write_data = 8'd8;
#2
start=0;
#10
start=1;
read_operation = 1;
address = 8'd11;
#2
start=0;
end
endmodule
| 7.249066 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_t0;
// Inputs
reg clk;
reg [13:0] switch;
reg [11:0] btn_in;
// Outputs
wire [11:0] anode;
wire [15:0] segment;
wire [4:0] led;
wire [31:0] Rdata2;
wire [31:0] Rdata1;
wire [31:0] inst;
wire [31:0] PC;
wire [31:0] ALUout;
wire [31:0] wrdata;
// Instantiate the Unit Under Test (UUT)
top uut (
.clk(clk),
.anode(anode),
.segment(segment),
.switch(switch),
.btn_in(btn_in),
.led(led),
.Rdata2(Rdata2),
.Rdata1(Rdata1),
.inst(inst),
.PC(PC),
.ALUout(ALUout),
.wrdata(wrdata)
);
initial begin
// Initialize Inputs
clk = 0;
switch = 0;
btn_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
switch[1]=1;
btn_in[0]=1;
#100;
btn_in[0]=0;
#100;
btn_in[0]=1;
#100;
btn_in[0]=0;
#100;
btn_in[0]=1;
#100;
btn_in[0]=0;
#100;
btn_in[0]=1;
#100;
btn_in[0]=0;
#100;
btn_in[0]=1;
#100;
btn_in[0]=0;
#100;
btn_in[0]=1;
#100;
btn_in[0]=0;
#100;
btn_in[0]=1;
end
initial forever begin
clk=~clk;
#1;
end
endmodule
| 7.115105 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
wire [7:0] temp_a, temp_b;
wire e;
task convert;
input [7:0] temp_in;
output [7:0] temp_out;
begin
temp_out = (9 / 5) * (temp_in + 32);
end
endtask
function myfunction;
input a, b, c, d;
begin
myfunction = ((a + b) + (c - d));
end
endfunction
always @(temp_a) begin
convert(temp_a, temp_b);
end
assign e = myfunction(a, b, c, d);
endmodule
| 7.233807 |
module Top_tb;
`include "../src/utils/Assert.vh"
`include "../src/Parameters.vh"
// Input stimulus
parameter INSTRUCTION_FILE_NAME = "./test/datapath_tb1.ASM";
reg clk, rst;
Top #(
.INSTRUCTION_FILE_NAME(INSTRUCTION_FILE_NAME)
) top (
.clk(clk),
.rst(rst)
);
// Test initialization
initial begin
#0 clk = 0;
rst = 0;
// release
#10 rst = 1;
end
// Clock drive
always #5 clk = ~clk;
endmodule
| 6.942968 |
module top_tb_1000 ();
reg clk, rst_n;
reg [7:0] pixels[0:783999];
reg [9:0] img_idx;
reg [7:0] data_in;
reg [9:0] cnt; // num of input image (1000)
reg [9:0] input_cnt;
reg [9:0] rand_num; // 1000
reg state;
integer i_cnt; // loop variable
reg [9:0] accuracy; // hit/miss count (1000)
wire [3:0] decision;
wire valid_out_1, valid_out_2, valid_out_3, valid_out_4, valid_out_5, valid_out_6;
CNN_top c (
.clk(clk),
.rst_n(rst_n),
.data_in(data_in),
.valid_out_6(valid_out_6),
.decision(decision)
);
// Module Instantiation
// Clock generation
always #5 clk = ~clk;
// Read image text file
initial begin
$readmemh("input_1000.mem", pixels);
cnt <= 0;
img_idx <= 0;
clk <= 1'b0;
input_cnt <= -1;
rst_n <= 1'b1;
rand_num <= 1'b0;
accuracy <= 0;
#3 rst_n <= 1'b0;
#3 rst_n <= 1'b1;
end
always @(posedge clk) begin
if (~rst_n) begin
#3 rst_n <= 1'b1;
end else begin
// decision done
if (valid_out_6 == 1'b1) begin
if (state !== 1'bx) begin
if (cnt % 10 == 1) begin
if (rand_num % 10 == decision) begin
$display(
"%0dst input image : original value = %0d, decision = %0d at %0t ps ==> Success",
cnt, rand_num % 10, decision, $time);
accuracy <= accuracy + 1'b1;
end else begin
$display(
"%0dst input image : original value = %0d, decision = %0d at %0t ps ==> Fail",
cnt, rand_num % 10, decision, $time);
end
end else if (cnt % 10 == 2) begin
if (rand_num % 10 == decision) begin
$display(
"%0dnd input image : original value = %0d, decision = %0d at %0t ps ==> Success",
cnt, rand_num % 10, decision, $time);
accuracy <= accuracy + 1'b1;
end else begin
$display(
"%0dnd input image : original value = %0d, decision = %0d at %0t ps ==> Fail",
cnt, rand_num % 10, decision, $time);
end
end else if (cnt % 10 == 3)
if (rand_num % 10 == decision) begin
$display(
"%0drd input image : original value = %0d, decision = %0d at %0t ps ==> Success",
cnt, rand_num % 10, decision, $time);
accuracy <= accuracy + 1'b1;
end else begin
$display(
"%0drd input image : original value = %0d, decision = %0d at %0t ps ==> Fail",
cnt, rand_num % 10, decision, $time);
end
else begin
if (rand_num % 10 == decision) begin
$display(
"%0dth input image : original value = %0d, decision = %0d at %0t ps ==> Success",
cnt, rand_num % 10, decision, $time);
accuracy <= accuracy + 1'b1;
end else begin
$display(
"%0dth input image : original value = %0d, decision = %0d at %0t ps ==> Fail",
cnt, rand_num % 10, decision, $time);
end
end
end
state <= 1'b0;
rst_n <= 1'b0;
input_cnt <= input_cnt + 1'b1;
rand_num <= $urandom_range(0, 1000);
//rand_num <= rand_num + 1'b1;
end
if (state == 1'b0) begin
//data_in <= pixels[cnt*784 + img_idx];
data_in <= pixels[rand_num*784+img_idx];
//data_in <= pixel[img_idx];
img_idx <= img_idx + 1'b1;
if (img_idx == 10'd784) begin
cnt <= cnt + 1'b1;
if (cnt == 10'd1000) begin
$display("\n\n------ Final Accuracy for 1000 Input Image ------");
$display("Accuracy : %3d%%", accuracy / 10);
$stop;
end
img_idx <= 0;
state <= 1'b1; // done
end
end
end
end
endmodule
| 6.811656 |
module top_tb_bd ();
localparam HALF_CORE_PERIOD = 2.5;
reg reset;
reg fpga_sysclk;
wire fpga_sysclk_p, fpga_sysclk_n;
reference_router_wrapper top_sim_bd_wrapper (
.fpga_sysclk_n (fpga_sysclk_p),
.fpga_sysclk_p (fpga_sysclk_n),
.reset (reset)
);
// rst - ACTIVE_HIGH
initial begin
reset = 1'b1;
#(HALF_CORE_PERIOD * 2 * 200);
reset = 1'b0;
$display("Reset Deasserted");
end
//clk - 200MHz fpga_clk
initial begin
fpga_sysclk = 1'b0;
#(HALF_CORE_PERIOD);
forever #(HALF_CORE_PERIOD) fpga_sysclk = ~fpga_sysclk;
end
assign fpga_sysclk_p = fpga_sysclk;
assign fpga_sysclk_n = ~fpga_sysclk;
endmodule
| 7.247029 |
module Top_tb;
//pins
reg [ 7:0] input_test;
wire [15:0] ans;
reg clk, rst_n, next, init;
wire ready, done;
reg [15:0] gold_ans;
reg Valid;
integer i, j;
parameter num = 10; //number of answer data
//module instantiation
CHIP top (
.clk(clk),
.rst_n(rst_n),
.i_valid(Valid),
.i_text(input_test),
.o_answer(ans),
.o_valid(done)
);
`ifdef SDF
initial $sdf_annotate(`SDFFILE, top);
`endif
always #(`CYCLE / 2) clk = ~clk;
//File Handler
integer data_in, gold_out, cnt1, cnt2;
initial begin
data_in = $fopen("top_input_split.txt", "r");
gold_out = $fopen("top_output_split.txt", "r");
if (data_in == 0) begin
$display("input_file handle was NULL.");
$finish;
end
if (gold_out == 0) begin
$display("golden_output handle was NULL.");
$finish;
end
end
//initial block
initial begin
$fsdbDumpfile("top.fsdb");
$fsdbDumpvars(0, "+mda");
$display("Testbench Start.");
cnt2 = $fscanf(gold_out, "%h\n", gold_ans);
rst_n = 1;
clk = 0;
init = 0;
input_test = 8'b0;
//#10 rst_n = 0;
//#10 rst_n = 1;
// @(posedge ready);
// #50;
@(posedge clk);
#(`CYCLE / 2);
for (i = 0; i < num; i = i + 1) begin
input_test = 8'b0;
Valid = 0;
rst_n = 0;
#5;
rst_n = 1;
@(posedge clk); // #(`CYCLE)
@(posedge clk); // #(`CYCLE)
//input_test = 8'b10101010; //start signal
@(posedge clk); // #(`CYCLE)
Valid = 1;
for (j = 0; j < 64; j = j + 1) begin
cnt1 = $fscanf(data_in, "%b\n", input_test);
// $display("input%d = %h", j, input_test);
@(posedge clk); // #(`CYCLE)
end
input_test = 8'b0;
Valid = 0;
$display("Input done.");
@(posedge done);
$display("Calculation done.");
for (j = 0; j < 10; j = j + 1) begin
@(negedge clk);
if (gold_ans !== ans) $display("%derror!!! gold_out = %h; out = %h", i, gold_ans, ans);
else $display("%dSuccess!! gold_out = %h; out = %h", i, gold_ans, ans);
cnt2 = $fscanf(gold_out, "%h\n", gold_ans);
end
//check answer
//cnt2 = $fscanf(gold_out, "%h\n", gold_ans);
//if(gold_ans !== ans) $display("%derror!!! gold_out = %h; out = %h",i, gold_ans, ans);
//else $display("%dSuccess!! gold_out = %h; out = %h",i, gold_ans, ans);
#10;
end
#50;
$display("Testbench End.");
$finish;
end
initial begin
#100000 $display("Time Exceed.");
$finish;
end
endmodule
| 6.843836 |
module clk_div (
clk_in1,
clk_out1,
reset,
locked
);
input clk_in1;
output clk_out1;
input reset;
output locked;
wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
clk_div_clk_div_clk_wiz inst (
.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.reset(reset)
);
endmodule
| 7.520262 |
module dataRAM
(a,
d,
clk,
we,
spo);
input [5:0]a;
input [31:0]d;
input clk;
input we;
output [31:0]spo;
wire [5:0]a;
wire clk;
wire [31:0]d;
wire [31:0]spo;
wire we;
wire NLW_U0_i_ce_UNCONNECTED;
wire NLW_U0_qdpo_ce_UNCONNECTED;
wire NLW_U0_qdpo_clk_UNCONNECTED;
wire NLW_U0_qdpo_rst_UNCONNECTED;
wire NLW_U0_qdpo_srst_UNCONNECTED;
wire NLW_U0_qspo_ce_UNCONNECTED;
wire NLW_U0_qspo_rst_UNCONNECTED;
wire NLW_U0_qspo_srst_UNCONNECTED;
wire [31:0]NLW_U0_dpo_UNCONNECTED;
wire [5:0]NLW_U0_dpra_UNCONNECTED;
wire [31:0]NLW_U0_qdpo_UNCONNECTED;
wire [31:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_CLK = "1" *)
(* C_HAS_D = "1" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *)
(* C_HAS_QDPO = "0" *)
(* C_HAS_QDPO_CE = "0" *)
(* C_HAS_QDPO_CLK = "0" *)
(* C_HAS_QDPO_RST = "0" *)
(* C_HAS_QDPO_SRST = "0" *)
(* C_HAS_WE = "1" *)
(* C_MEM_TYPE = "1" *)
(* C_QCE_JOINED = "0" *)
(* C_REG_DPRA_INPUT = "0" *)
(* KEEP_HIERARCHY = "true" *)
(* c_addr_width = "6" *)
(* c_default_data = "0" *)
(* c_depth = "64" *)
(* c_elaboration_dir = "./" *)
(* c_has_i_ce = "0" *)
(* c_has_qspo = "0" *)
(* c_has_qspo_ce = "0" *)
(* c_has_qspo_rst = "0" *)
(* c_has_qspo_srst = "0" *)
(* c_has_spo = "1" *)
(* c_mem_init_file = "dataRAM.mif" *)
(* c_parser_type = "1" *)
(* c_pipeline_stages = "0" *)
(* c_qualify_we = "0" *)
(* c_read_mif = "1" *)
(* c_reg_a_d_inputs = "0" *)
(* c_sync_enable = "1" *)
(* c_width = "32" *)
dataRAM_dist_mem_gen_v8_0_10 U0
(.a(a),
.clk(clk),
.d(d),
.dpo(NLW_U0_dpo_UNCONNECTED[31:0]),
.dpra(NLW_U0_dpra_UNCONNECTED[5:0]),
.i_ce(NLW_U0_i_ce_UNCONNECTED),
.qdpo(NLW_U0_qdpo_UNCONNECTED[31:0]),
.qdpo_ce(NLW_U0_qdpo_ce_UNCONNECTED),
.qdpo_clk(NLW_U0_qdpo_clk_UNCONNECTED),
.qdpo_rst(NLW_U0_qdpo_rst_UNCONNECTED),
.qdpo_srst(NLW_U0_qdpo_srst_UNCONNECTED),
.qspo(NLW_U0_qspo_UNCONNECTED[31:0]),
.qspo_ce(NLW_U0_qspo_ce_UNCONNECTED),
.qspo_rst(NLW_U0_qspo_rst_UNCONNECTED),
.qspo_srst(NLW_U0_qspo_srst_UNCONNECTED),
.spo(spo),
.we(we));
endmodule
| 6.975103 |
module instructionROM
(a,
spo);
input [5:0]a;
output [31:0]spo;
wire [5:0]a;
wire [31:0]spo;
wire NLW_U0_clk_UNCONNECTED;
wire NLW_U0_i_ce_UNCONNECTED;
wire NLW_U0_qdpo_ce_UNCONNECTED;
wire NLW_U0_qdpo_clk_UNCONNECTED;
wire NLW_U0_qdpo_rst_UNCONNECTED;
wire NLW_U0_qdpo_srst_UNCONNECTED;
wire NLW_U0_qspo_ce_UNCONNECTED;
wire NLW_U0_qspo_rst_UNCONNECTED;
wire NLW_U0_qspo_srst_UNCONNECTED;
wire NLW_U0_we_UNCONNECTED;
wire [31:0]NLW_U0_d_UNCONNECTED;
wire [31:0]NLW_U0_dpo_UNCONNECTED;
wire [5:0]NLW_U0_dpra_UNCONNECTED;
wire [31:0]NLW_U0_qdpo_UNCONNECTED;
wire [31:0]NLW_U0_qspo_UNCONNECTED;
wire [30:25]NLW_U0_spo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_CLK = "0" *)
(* C_HAS_D = "0" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *)
(* C_HAS_QDPO = "0" *)
(* C_HAS_QDPO_CE = "0" *)
(* C_HAS_QDPO_CLK = "0" *)
(* C_HAS_QDPO_RST = "0" *)
(* C_HAS_QDPO_SRST = "0" *)
(* C_HAS_WE = "0" *)
(* C_MEM_TYPE = "0" *)
(* C_QCE_JOINED = "0" *)
(* C_REG_DPRA_INPUT = "0" *)
(* KEEP_HIERARCHY = "true" *)
(* c_addr_width = "6" *)
(* c_default_data = "0" *)
(* c_depth = "64" *)
(* c_elaboration_dir = "./" *)
(* c_has_i_ce = "0" *)
(* c_has_qspo = "0" *)
(* c_has_qspo_ce = "0" *)
(* c_has_qspo_rst = "0" *)
(* c_has_qspo_srst = "0" *)
(* c_has_spo = "1" *)
(* c_mem_init_file = "instructionROM.mif" *)
(* c_parser_type = "1" *)
(* c_pipeline_stages = "0" *)
(* c_qualify_we = "0" *)
(* c_read_mif = "1" *)
(* c_reg_a_d_inputs = "0" *)
(* c_sync_enable = "1" *)
(* c_width = "32" *)
instructionROM_dist_mem_gen_v8_0_10 U0
(.a(a),
.clk(NLW_U0_clk_UNCONNECTED),
.d(NLW_U0_d_UNCONNECTED[31:0]),
.dpo(NLW_U0_dpo_UNCONNECTED[31:0]),
.dpra(NLW_U0_dpra_UNCONNECTED[5:0]),
.i_ce(NLW_U0_i_ce_UNCONNECTED),
.qdpo(NLW_U0_qdpo_UNCONNECTED[31:0]),
.qdpo_ce(NLW_U0_qdpo_ce_UNCONNECTED),
.qdpo_clk(NLW_U0_qdpo_clk_UNCONNECTED),
.qdpo_rst(NLW_U0_qdpo_rst_UNCONNECTED),
.qdpo_srst(NLW_U0_qdpo_srst_UNCONNECTED),
.qspo(NLW_U0_qspo_UNCONNECTED[31:0]),
.qspo_ce(NLW_U0_qspo_ce_UNCONNECTED),
.qspo_rst(NLW_U0_qspo_rst_UNCONNECTED),
.qspo_srst(NLW_U0_qspo_srst_UNCONNECTED),
.spo({spo[31],NLW_U0_spo_UNCONNECTED[30],spo[29:26],NLW_U0_spo_UNCONNECTED[25],spo[24:0]}),
.we(NLW_U0_we_UNCONNECTED));
endmodule
| 6.735273 |
module IF (
Instruction_if,
Q,
D,
\q_reg[5] ,
E,
SR,
\q_reg[0] ,
clk
);
output [31:0] Instruction_if;
output [0:0] Q;
output [5:0] D;
input [5:0] \q_reg[5] ;
input [0:0] E;
input [0:0] SR;
input [0:0] \q_reg[0] ;
input clk;
wire [5:0] D;
wire [0:0] E;
wire [31:0] Instruction_if;
wire [7:2] PC_in;
wire [0:0] Q;
wire [0:0] SR;
wire clk;
wire dffre_PC_REG_n_10;
wire dffre_PC_REG_n_6;
wire dffre_PC_REG_n_7;
wire dffre_PC_REG_n_8;
wire dffre_PC_REG_n_9;
wire [0:0] \q_reg[0] ;
wire [5:0] \q_reg[5] ;
wire [30:25] NLW_instruction_spo_UNCONNECTED;
(* XILINX_LEGACY_PRIM = "LD" *)
LDCE #(
.INIT(1'b0)
) \PC_in_reg[2] (
.CLR(1'b0),
.D (\q_reg[5] [0]),
.G (E),
.GE (1'b1),
.Q (PC_in[2])
);
(* XILINX_LEGACY_PRIM = "LD" *)
LDCE #(
.INIT(1'b0)
) \PC_in_reg[3] (
.CLR(1'b0),
.D (\q_reg[5] [1]),
.G (E),
.GE (1'b1),
.Q (PC_in[3])
);
(* XILINX_LEGACY_PRIM = "LD" *)
LDCE #(
.INIT(1'b0)
) \PC_in_reg[4] (
.CLR(1'b0),
.D (\q_reg[5] [2]),
.G (E),
.GE (1'b1),
.Q (PC_in[4])
);
(* XILINX_LEGACY_PRIM = "LD" *)
LDCE #(
.INIT(1'b0)
) \PC_in_reg[5] (
.CLR(1'b0),
.D (\q_reg[5] [3]),
.G (E),
.GE (1'b1),
.Q (PC_in[5])
);
(* XILINX_LEGACY_PRIM = "LD" *)
LDCE #(
.INIT(1'b0)
) \PC_in_reg[6] (
.CLR(1'b0),
.D (\q_reg[5] [4]),
.G (E),
.GE (1'b1),
.Q (PC_in[6])
);
(* XILINX_LEGACY_PRIM = "LD" *)
LDCE #(
.INIT(1'b0)
) \PC_in_reg[7] (
.CLR(1'b0),
.D (\q_reg[5] [5]),
.G (E),
.GE (1'b1),
.Q (PC_in[7])
);
dffre_4 dffre_PC_REG (
.D(D),
.Q({
dffre_PC_REG_n_6, dffre_PC_REG_n_7, dffre_PC_REG_n_8, dffre_PC_REG_n_9, dffre_PC_REG_n_10, Q
}),
.SR(SR),
.clk(clk),
.\q_reg[0] (\q_reg[0] ),
.\q_reg[5]_0 (PC_in)
);
(* x_core_info = "dist_mem_gen_v8_0_10,Vivado 2016.2" *)
instructionROM instruction (
.a({
dffre_PC_REG_n_6, dffre_PC_REG_n_7, dffre_PC_REG_n_8, dffre_PC_REG_n_9, dffre_PC_REG_n_10, Q
}),
.spo({
Instruction_if[31],
NLW_instruction_spo_UNCONNECTED[30],
Instruction_if[29:26],
NLW_instruction_spo_UNCONNECTED[25],
Instruction_if[24:0]
})
);
endmodule
| 6.625137 |
module instructionROM_dist_mem_gen_v8_0_10 (
a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo
);
input [5:0] a;
input [31:0] d;
input [5:0] dpra;
input clk;
input we;
input i_ce;
input qspo_ce;
input qdpo_ce;
input qdpo_clk;
input qspo_rst;
input qdpo_rst;
input qspo_srst;
input qdpo_srst;
output [31:0] spo;
output [31:0] dpo;
output [31:0] qspo;
output [31:0] qdpo;
wire \<const0> ;
wire [5:0] a;
wire [31:0] \^spo ;
assign spo[31] = \^spo [31];
assign spo[29:28] = \^spo [29:28];
assign spo[27] = \^spo [31];
assign spo[26] = \^spo [26];
assign spo[24:21] = \^spo [24:21];
assign spo[20] = \<const0> ;
assign spo[19:16] = \^spo [19:16];
assign spo[15] = \^spo [28];
assign spo[14:12] = \^spo [14:12];
assign spo[11] = \^spo [13];
assign spo[10] = \^spo [28];
assign spo[9] = \^spo [28];
assign spo[8] = \^spo [28];
assign spo[7] = \^spo [28];
assign spo[6] = \^spo [28];
assign spo[5:0] = \^spo [5:0];
GND GND (.G(\<const0> ));
instructionROM_dist_mem_gen_v8_0_10_synth \synth_options.dist_mem_inst (
.a(a),
.spo({
\^spo [31],
\^spo [29:28],
\^spo [26],
\^spo [24:21],
\^spo [19:16],
\^spo [14:12],
\^spo [5:0]
})
);
endmodule
| 6.735273 |
module instructionROM_dist_mem_gen_v8_0_10_synth (
spo,
a
);
output [20:0] spo;
input [5:0] a;
wire [ 5:0] a;
wire [20:0] spo;
instructionROM_rom \gen_rom.rom_inst (
.a (a),
.spo(spo)
);
endmodule
| 6.735273 |
module top_TDES_encrypt (
input clk,
input [63:0] data,
input [63:0] key1,
input [63:0] key2,
input [63:0] key3,
input nrst,
output [63:0] data_out
);
logic [ 63:0] data_out_1;
logic [ 63:0] data_out_2;
logic [1023:0] key_2_decrypt;
logic [2047:0] key_3_encrypt;
always @(posedge clk or negedge nrst) begin
if (~nrst) key_2_decrypt <= 1024'h0;
else key_2_decrypt <= {key_2_decrypt[959:0], key2};
end
always @(posedge clk or negedge nrst) begin
if (~nrst) key_3_encrypt <= 2048'h0;
else key_3_encrypt <= {key_3_encrypt[1983:0], key3};
end
top_DES_encrypt des_1_encrypt (
.clk (clk),
.data (data),
.key (key1),
.nrst (nrst),
.data_out(data_out_1)
);
top_DES_decrypt des_2_decrypt (
.clk(clk),
.data(data_out_1),
.key(key_2_decrypt[1023:960]),
.nrst(nrst),
.data_out(data_out_2)
);
top_DES_encrypt des_3_encrypt (
.clk(clk),
.data(data_out_2),
.key(key_3_encrypt[2047:1984]),
.nrst(nrst),
.data_out(data_out)
);
endmodule
| 6.775213 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(enout),
.reset(reset),
.set(set),
.q(q)
);
endmodule
| 7.493109 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module CLK_MOD // source/CLK_MOD.v(1)
(
CLK,
Count_REG,
RSTn,
CLK_OUT
);
input CLK; // source/CLK_MOD.v(11)
input [31:0] Count_REG; // source/CLK_MOD.v(14)
input RSTn; // source/CLK_MOD.v(12)
output CLK_OUT; // source/CLK_MOD.v(17)
wire [31:0] Count; // source/CLK_MOD.v(15)
wire [31:0] n3;
wire [31:0] n5;
wire n0;
wire n1;
wire n2;
wire n4;
AL_DFF CLK_OUT_reg (
.clk(CLK),
.d(n4),
.reset(1'b0),
.set(n0),
.q(CLK_OUT)
); // source/CLK_MOD.v(32)
add_pu32_pu32_o32 add0 (
.i0(Count),
.i1(32'b00000000000000000000000000000001),
.o (n3)
); // source/CLK_MOD.v(32)
eq_w32 eq0 (
.i0(Count),
.i1(Count_REG),
.o (n1)
); // source/CLK_MOD.v(26)
binary_mux_s1_w32 mux0 (
.i0 (n3),
.i1 (32'b00000000000000000000000000000000),
.sel(n1),
.o (n5)
); // source/CLK_MOD.v(32)
reg_ar_as_w32 reg0 (
.clk(CLK),
.d(n5),
.reset({
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0,
n0
}),
.set(32'b00000000000000000000000000000000),
.q(Count)
); // source/CLK_MOD.v(32)
not u2 (n0, RSTn); // source/CLK_MOD.v(21)
not u3 (n2, CLK_OUT); // source/CLK_MOD.v(28)
AL_MUX u4 (
.i0 (CLK_OUT),
.i1 (n2),
.sel(n1),
.o (n4)
); // source/CLK_MOD.v(32)
endmodule
| 7.043189 |
module add_pu16_pu16_o16 (
i0,
i1,
o
);
input [15:0] i0;
input [15:0] i1;
output [15:0] o;
endmodule
| 6.909569 |
module reg_ar_as_w16 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [15:0] d;
input en;
input [15:0] reset;
input [15:0] set;
output [15:0] q;
endmodule
| 7.044453 |
module add_pu32_pu32_o32 (
i0,
i1,
o
);
input [31:0] i0;
input [31:0] i1;
output [31:0] o;
endmodule
| 6.598391 |
module reg_ar_as_w5 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [4:0] d;
input en;
input [4:0] reset;
input [4:0] set;
output [4:0] q;
endmodule
| 6.587269 |
module onehot_mux_s5_w5 (
i0,
i1,
i2,
i3,
i4,
sel,
o
);
input [4:0] i0;
input [4:0] i1;
input [4:0] i2;
input [4:0] i3;
input [4:0] i4;
input [4:0] sel;
output [4:0] o;
endmodule
| 6.655267 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(enout),
.reset(reset),
.set(set),
.q(q)
);
endmodule
| 7.493109 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module AL_FADD (
input a,
input b,
input c,
output sum,
output cout
);
wire prop;
wire not_prop;
wire sel_i0;
wire sel_i1;
xor u0 (prop, a, b);
xor u1 (sum, prop, c);
not u2 (not_prop, prop);
and u3 (sel_i1, prop, c);
and u4 (sel_i0, not_prop, a);
or u5 (cout, sel_i0, sel_i1);
endmodule
| 8.066381 |
module enable
reg linkBIM;
reg capture_rst;
#{REG_TEXT}
#{ASSIGN_TEXT}
#{IP_TEXT}
/////////////////////////////////////////////////////////////////////////////////////////////////////
reg flag_reg;
always @ (negedge bps_start or negedge rst_n)
begin
if (!rst_n)
flag_reg <= 1'b0;
else if (!bps_start)
flag_reg <= ~flag_reg;
end
assign Flag = flag_reg;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
Current <= IDLE;
else
Current <= Next;
end
// the state machine for receive data bytes
always @ (*)
begin
Next = IDLE;
case (Current)
IDLE:
if (rx_data == 8'h24) //$
Next = S1;
else
Next = IDLE;
S1:
if (Flag_temp != Flag)
begin
if (rx_data != 8'h0d) //\n
Next = S1;
else
Next = SAVE;
end
else
Next = WAIT;
WAIT:
if (Flag_temp!=Flag)
begin
if (rx_data != 8'h0d)
Next = S1;
else
Next = SAVE;
end
else
Next = WAIT;
default: Next = IDLE;
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
Flag_temp <= 1'b0;
end
else
begin
Flag_temp <= Flag;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
Buff_temp <= `Buff_size'b0;
Rx_cmd <= `Buff_size'b0;
cmd_red <= 1'b0;
end
else
begin
case (Current)
IDLE:
begin
Buff_temp <= `Buff_size'b0;
end
S1:
begin
cmd_red <= 1'b1;
Buff_temp <= {{Buff_temp[`Buff_size - 9 : 0]}, rx_data};
end
WAIT:
begin
Buff_temp <= Buff_temp;
end
SAVE:
begin
Rx_cmd <= Buff_temp[`Buff_size - 9 : 0];
Buff_temp <= `Buff_size'b0;
cmd_red <= 1'b0;
end
default:
begin
end
endcase
end
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
//////////////////add link here////////////////
#{INIT_REG_TEXT}
///////////////////////////////////////////////
led <= 1'b0; // for debug led
linkBIM <= 1'b1;
end
else if(cmd_red) begin
#{RST_REG_TEXT}
led <= 1'b0;
capture_rst <= 1'b0;
end
else
begin
case(Rx_cmd)
///////////////////add case here/////////////
#{CMD_CASE_TEXT}
/////////////////////////////////////////////
{R,S,T}: //RESET
begin
#{RST_REG_TEXT}
led <= 1'b0;
linkBIM <= 1'b1;
capture_rst <= 1'b0;
end
default:
begin
#{DFT_REG_TEXT}
led <= 1'b0;
linkBIM <= 1'b1;
capture_rst <= 1'b0;
end
endcase
end
end
/////////////////////////////////////////////////////////////
endmodule
| 7.08557 |
module top_test (
input clk, // clk100mhz
input rstn, // cpu_resetn
output [31:0] pc,
// for simulate io
output [ 7:0] io_addr,
output io_rd,
input [31:0] io_din
);
wire [31 : 0] io_dout;
wire io_we;
wire [31 : 0] chk_data;
wire [31:0] vga_data;
cpu CPU (
.clk(clk),
.rstn(rstn),
.vga_addr(0),
.vga_data(vga_data),
.io_addr(io_addr),
.io_dout(io_dout),
.io_we(io_we),
.io_rd(io_rd),
.io_din(io_din),
.pc(pc),
.chk_addr(0),
.chk_data(chk_data)
);
endmodule
| 7.337344 |
module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_Tester;
// Inputs
reg clock_100MHz;
reg reset_n;
reg [7:0] Switch;
reg UART_Rx;
// Outputs
wire [14:0] LED;
wire [6:0] LCD;
wire UART_Tx;
wire Piezo;
// Bidirs
wire i2c_scl;
wire i2c_sda;
// Instantiate the Unit Under Test (UUT)
Top uut (
.clock_100MHz(clock_100MHz),
.reset_n(reset_n),
.Switch(Switch),
.LED(LED),
.LCD(LCD),
.UART_Rx(UART_Rx),
.UART_Tx(UART_Tx),
.i2c_scl(i2c_scl),
.i2c_sda(i2c_sda),
.Piezo(Piezo)
);
integer i;
initial begin
// Initialize Inputs
clock_100MHz = 0;
reset_n = 0;
Switch = 0;
UART_Rx = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (i=0; i<900000; i=i+1) begin
reset_n = (i < 28) ? 0 : 1;
clock_100MHz = ~clock_100MHz;
if (i > 4000) Switch <= 8'h00;
if (i > 100000) i = i - 1;
#5;
end
end
endmodule
| 7.357405 |
module top_test_add;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH : 0] expected_output = 1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t (
.clk(clk),
.uart_tx_line(uart_tx)
);
always @(posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output >= OUTPUT_CNT) begin
$display("Add test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Add test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n", serial_data,
expected_output);
$finish;
end
expected_output <= expected_output + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
| 6.712228 |
module top_test_jump;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 5;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = 1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t (
.clk(clk),
.uart_tx_line(uart_tx)
);
always @(posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output >= OUTPUT_CNT) begin
$display("Jump test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Jump test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n", serial_data,
expected_output);
$finish;
end
expected_output <= expected_output + 2;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
| 7.923626 |
module top_test_load_out;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 7;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = 0;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t (
.clk(clk),
.uart_tx_line(uart_tx)
);
always @(posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output >= OUTPUT_CNT) begin
$display("Load and output test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Load and output test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n", serial_data,
expected_output);
$finish;
end
expected_output <= expected_output + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
| 6.795474 |
module top_test_load_store;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 3;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = 1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t (
.clk(clk),
.uart_tx_line(uart_tx)
);
always @(posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output >= OUTPUT_CNT) begin
$display("Load and store test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Load and store test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n", serial_data,
expected_output);
$finish;
end
expected_output <= expected_output + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
| 6.795474 |
module top_test_shl;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = 1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t (
.clk(clk),
.uart_tx_line(uart_tx)
);
always @(posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output == 0) begin
$display("Shift left test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Shift left test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n", serial_data,
expected_output);
$finish;
end
expected_output <= expected_output << 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
| 7.950308 |
module top_test_sub;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = OUTPUT_CNT - 1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t (
.clk(clk),
.uart_tx_line(uart_tx)
);
always @(posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output == 0) begin
$display("Subtract test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Subtract test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n", serial_data,
expected_output);
$finish;
end
expected_output <= expected_output - 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
| 6.577828 |
module top_b2b_proj (
FIFO_READ_empty,
FIFO_READ_rd_data,
FIFO_READ_rd_en,
clk_in1,
reset_rtl_0
);
output FIFO_READ_empty;
output [127:0] FIFO_READ_rd_data;
input FIFO_READ_rd_en;
input clk_in1;
input reset_rtl_0;
wire FIFO_READ_empty;
wire [127:0] FIFO_READ_rd_data;
wire FIFO_READ_rd_en;
wire clk_in1;
wire reset_rtl_0;
b2b_top b2b_top_i (
.FIFO_READ_empty(FIFO_READ_empty),
.FIFO_READ_rd_data(FIFO_READ_rd_data),
.FIFO_READ_rd_en(FIFO_READ_rd_en),
.clk_in1(clk_in1),
.reset_rtl_0(reset_rtl_0)
);
endmodule
| 6.71581 |
module top_tranrec (
output [7:0] data_out,
input [7:0] data,
input start,
input clk
);
wire Tx, data_valid;
wire [3:0] cnt_trans;
wire [3:0] cnt_rec;
transmitter t2 (
Tx,
cnt_trans,
data,
~start,
clk
);
receiver r2 (
data_valid,
cnt_rec,
data_out,
clk,
Tx
);
endmodule
| 6.687679 |
module tristate (
en,
i,
io,
o
);
input en;
input i;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en) ? i : 1'bZ;
assign io[1] = (i) ? en : 1'bZ;
assign o = io;
endmodule
| 6.741184 |
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en(en),
.i (a),
.io(b),
.o (c)
);
endmodule
| 7.233807 |
module top_tukka2 (
`ifdef USE_POWER_PINS
inout vdd, // User area 5.0V supply
inout vss, // User area ground
`endif
input clk1,
input clk2,
input reset_n,
input sel_clk2,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
output [7:0] dout
);
wire clk1or2;
spi_slave s1 (
.clk (clk1or2),
.rst (reset_n),
.ss (ss),
.mosi(mosi),
.miso(miso),
.sck (sck),
.done(done),
.din (din),
.dout(dout)
);
clock_mux m1 (
.clk1 (clk1), // Clock 1 supposed to be faster
.clk2 (clk2), // Clock 2 supposed to be slower
.reset_n (reset_n), // System reset
.sel_clk2(sel_clk2), // Select clock2 when high
.clk1or2 (clk1or2) // Selected clock
);
endmodule
| 7.002032 |
module top_uart #( // Default setting:
// 19,200 baud, 8 data bits, 1 stop bit, 2^2 FIFO
parameter DBIT = 8, // # data bits
SB_TICK = 16, // # ticks for stop bits, 16/24/32
// for 1/1.5/2 stop bits
DVSR = 163, // baud rate divisor
// DVSR = 50M/(16*baud rate)
DVSR_BIT = 8, // # bits of DVSR
FIFO_W = 2 // # addr bits of FIFO
// # words in FIFO=2^FIFO_W
) (
input wire clk,
reset,
input wire rd_uart,
wr_uart,
input wire [7:0] w_data,
output wire tx_full,
rx_empty,
output wire [7:0] r_data
);
// signal declaration
wire tick, rx_done_tick, tx_done_tick;
wire tx_empty, tx_fifo_not_empty;
wire [7:0] tx_fifo_out, rx_data_out;
wire tx, rx;
//body
baudrate_generator #(
.M(DVSR),
.N(DVSR_BIT)
) baud_gen_unit (
.clk(clk),
.reset(reset),
.s_tick(tick)
);
uart_rx #(
.DBIT(DBIT),
.SB_TICK(SB_TICK)
) uart_rx_unit (
.clk(clk),
.reset(reset),
.rx(tx),
.s_tick(tick),
.rx_done_tick(rx_done_tick),
.dout(rx_data_out)
);
Fifo_buffer #(
.W(DBIT),
.N(FIFO_W)
) fifo_rx_unit (
.clk(clk),
.reset(reset),
.rd(rd_uart),
.wr(rx_done_tick),
.data_w(rx_data_out),
.empty(rx_empty),
.full(),
.data_r(r_data)
);
Fifo_buffer #(
.W(DBIT),
.N(FIFO_W)
) fifo_tx_unit (
.clk(clk),
.reset(reset),
.rd(tx_done_tick),
.wr(wr_uart),
.data_w(w_data),
.empty(tx_empty),
.full(tx_full),
.data_r(tx_fifo_out)
);
uart_tx #(
.DBIT(DBIT),
.SB_TICK(SB_TICK)
) uart_tx_unit (
.clk(clk),
.reset(reset),
.tx_start(tx_fifo_not_empty),
.s_tick(tick),
.din(tx_fifo_out),
.tx_done_tick(tx_done_tick),
.tx(tx)
);
assign tx_fifo_not_empty = ~tx_empty;
endmodule
| 7.643709 |
module top_uart_buffer_echo (
sys_clk_n,
sys_clk_p,
uart_rx,
uart_tx
);
input sys_clk_n;
input sys_clk_p;
input uart_rx;
output uart_tx;
wire sys_clk_n;
wire sys_clk_p;
wire uart_rx;
wire uart_tx;
wire clk_100M; // @ 100.000000MHz
wire clk_50M; // @ 50.000000MHz
wire clk_5M; // @ 5.078120MHz;
wire clk_uart; // @ 6.914890MHz expecting 6.912MHz;
wire flag_clk_locked;
clk_wiz_0 u_clk_wiz_0 (
.clk_100M(clk_100M),
.clk_50M(clk_50M),
.clk_5M(clk_5M),
.clk_uart(clk_uart),
.locked(flag_clk_locked),
.clk_in1_p(sys_clk_p),
.clk_in1_n(sys_clk_n)
);
wire [7:0] data_rx;
wire ready_rx;
wire done_rx;
wire [7:0] data_tx;
wire ready_tx;
wire done_tx;
uart #(
.CLK_FREQ(6_914_890),
.BAUDRATE(38400)
) u_uart (
.clk(clk_uart),
.rx(uart_rx),
.tx(uart_tx),
.rst_n(flag_clk_locked),
.data_rx(data_rx),
.ready_rx(ready_rx),
.done_rx(done_rx),
.data_tx(data_tx),
.ready_tx(ready_tx),
.done_tx(done_tx),
.dbg_clk(clk_50M)
);
buffer_chain #(
.DATA_BITWIDTH(8),
.DEPTH(16)
) u_buffer (
.clk(clk_5M),
.rst_n(flag_clk_locked),
.data_in(data_rx),
.ready_in(ready_rx),
.done_in(done_rx),
.data_out(data_tx),
.ready_out(ready_tx),
.done_out(done_tx)
);
// ila_0 u_ial_0(
// .clk(clk_50M),
// .probe0(uart_rx),
// .probe1(uart_tx),
// .probe2(ready_rx),
// .probe3(done_rx),
// .probe4(ready_tx),
// .probe5(done_tx),
// .probe6(0),
// .probe7(0),
// .probe8(clk_5M),
// .probe9(clk_uart),
// .probe10(data_rx),
// .probe11(data_tx)
// );
endmodule
| 6.878899 |
module top_uart_echo (
sys_clk_n,
sys_clk_p,
uart_rx,
uart_tx
);
input sys_clk_n;
input sys_clk_p;
input uart_rx;
output uart_tx;
wire sys_clk_n;
wire sys_clk_p;
wire uart_rx;
wire uart_tx;
wire clk_100M; // @ 100.000000MHz;
wire clk_50M; // @ 50.000000MHz;
wire clk_5M; // @ 5.078120MHz;
wire clk_uart; // @ 6.914890MHz expecting 6.912MHz;
wire flag_clk_locked;
clk_wiz_0 u_clk_wiz_0 (
.clk_100M(clk_100M),
.clk_50M(clk_50M),
.clk_5M(clk_5M),
.clk_uart(clk_uart),
.locked(flag_clk_locked),
.clk_in1_p(sys_clk_p),
.clk_in1_n(sys_clk_n)
);
wire [7:0] data;
wire ready;
wire done;
uart #(
.CLK_FREQ(6_914_890),
.BAUDRATE(38400)
) u_uart (
.clk(clk_uart),
.rx(uart_rx),
.tx(uart_tx),
.rst_n(flag_clk_locked),
.data_rx(data),
.ready_rx(ready),
.done_rx(done),
.data_tx(data),
.ready_tx(ready),
.done_tx(done),
.dbg_clk(clk_50M)
);
// ila_0 u_ial_0(
// .clk(clk_50M),
// .probe0(uart_rx),
// .probe1(ready),
// .probe2(done),
// .probe3(uart_tx),
// .probe4(clk_uart),
// .probe5(0),
// .probe6(0),
// .probe7(0),
// .probe8(0),
// .probe9(0),
// .probe10(data),
// .probe11(0)
// );
endmodule
| 6.920979 |
module Top_UART_tb ();
parameter CLOCK_PERIOD = 10;
reg i_clk = 0;
reg TX_Valid = 0;
wire o_TX_Active;
wire UART_TX_RX;
wire o_TX_Serial;
wire o_TX;
wire o_RX_DV;
reg [7:0] data_TX = 0;
wire [7:0] data_RX;
/*TOP_UART TOP_DUT(
i_clk ,
i_TX_valid ,
data_TX ,
o_TX_Active ,
o_TX,
o_RX_DV ,
data_RX
);
*/
/*TOP_UART(
input i_clk ,
input i_TX_valid ,
input [`WIDTH_DATA-1:0] data_TX ,
output o_TX_Active ,
output o_TX,
output o_RX_DV ,
input i_Rx_Serial ,
output o_Tx_Serial ,
//output [`WIDTH_DATA-1:0] data_RX ,
output [1:0] seg_en ,
output [6:0] Seg_out
//output [`WIDTH_DATA-1:0] seg2_out
);
*/
UART_TX UUT_TX (
.i_clk(i_clk),
.i_TX_valid(TX_Valid),
.i_TX_DATA(data_TX), ///data to be transmitted from FPGA TO PC ///
.o_TX_Serial(o_TX_Serial) , ////serial output data to be streamed (Parallel to Serial)to the PC ///
.o_TX_active(o_TX_Active), ///output showing data transmission is active //
.o_TX(o_TX) //output showing data is successfully transmitted ///
);
Top_UART_Rx DUT_RX (
.i_clk(i_clk), ///Fpga clk ///
.i_Rx_serial(UART_TX_RX), ///data is serially loaded from PC through this ////
.o_RX_DV(o_RX_DV), ////DATA_VALID , output showing data is successfully received //
.o_RX(data_RX) ////output led's showing the received ASCII code from PC //
);
assign UART_TX_RX = o_TX_Active ? o_TX_Serial : 1'b1;
always #(CLOCK_PERIOD / 2) i_clk <= ~i_clk;
initial begin
@(posedge i_clk);
@(posedge i_clk);
TX_Valid <= 1'b1;
data_TX <= 8'h26;
@(posedge i_clk);
TX_Valid <= 1'b0;
end
endmodule
| 6.525673 |
module Top_uart_tx_dzj (
input [3:0] in_key_en,
input clk,
input rst_n,
input co,
input zhendong,
output RX232,
output over_rx,
output fengshan
);
wire [7:0] data_rx;
wire [3:0] out_key_en;
uart_tx_dzj a (
.co(co),
.zhendong(zhendong),
.in_key_en(out_key_en),
.clk(clk),
.rst_n(rst_n),
.over_tx(over_rx),
.data_rx(data_rx),
.send_en(send_en),
.fengshan(fengshan)
);
fangdou ab (
.in_key_en(in_key_en),
.rst_n(rst_n),
.clk(clk),
.out_key_en(out_key_en)
);
uart_tx abc (
.clk(clk),
.bps_clk(bps_clk),
.send_en(send_en),
.rst_n(rst_n),
.data_rx(data_rx),
.RX232(RX232),
.over_rx(over_rx),
.bps_start(bps_start)
);
bps_set abcd (
.clk(clk),
.rst_n(rst_n),
.bps_start(bps_start),
.bps_clk(bps_clk)
);
endmodule
| 6.585741 |
module: Top_uart_tx_dzj
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_uart_tx_dzj_test;
// Inputs
reg [3:0] in_key_en;
reg clk;
reg rst_n;
// Outputs
wire RX232;
wire over_rx;
// Instantiate the Unit Under Test (UUT)
Top_uart_tx_dzj uut (
.in_key_en(in_key_en),
.clk(clk),
.rst_n(rst_n),
.RX232(RX232),
.over_rx(over_rx)
);
initial begin
// Initialize Inputs
in_key_en = 0;
clk = 0;
rst_n = 0;
// Wait 100 ns for global reset to finish
#10;
rst_n=1'b1;
in_key_en=4'b0100;
#1000000;
in_key_en=4'b0;
// Add stimulus here
end
always #10 clk=~clk;
endmodule
| 8.138503 |
module: Top_uart_tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_uart_tx_test;
// Inputs
reg clk;
reg send_en;
reg rst_n;
reg [7:0] data_rx;
// Outputs
wire RX232;
wire over_rx;
// Instantiate the Unit Under Test (UUT)
Top_uart_tx uut (
.clk(clk),
.send_en(send_en),
.rst_n(rst_n),
.data_rx(data_rx),
.RX232(RX232),
.over_rx(over_rx)
);
initial begin
// Initialize Inputs
clk = 0;
send_en = 0;
rst_n = 0;
data_rx = 0;
// Wait 100 ns for global reset to finish
#10;
send_en=1'b1;
rst_n=1'b1;
data_rx=8'b01001001;
// Add stimulus here
end
always #10 clk=~clk;
endmodule
| 7.845935 |
module top_uc (
input rst,
input clk,
output reg [2:0] RGB0,
output reg [2:0] RGB1,
output reg [2:0] RGB2,
output reg [2:0] RGB3,
output reg [3:0] LED,
input [3:0] SW,
input [3:0] BTN
);
//wire pgm_re;
wire [`BUS_ADDR_PGM_LEN-1:0] pgm_addr;
wire [15:0] pgm_data;
wire data_re;
wire data_we;
wire [`BUS_ADDR_DATA_LEN-1:0] data_addr;
wire [7:0] data_in;
wire [7:0] data_out;
wire io_re;
wire io_we;
wire [5:0] io_addr;
wire [7:0] io_out;
wire [7:0] io_in;
wire core_clk;
wire CLKOUT1;
wire CLKOUT2;
wire CLKOUT3;
wire CLKOUT4;
wire CLKOUT5;
wire CLKFB;
wire LOCKED;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(10), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT0_DIVIDE(9),
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) PLLE2_BASE_inst (
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0 (core_clk), // 1-bit output: CLKOUT0
.CLKOUT1 (CLKOUT1), // 1-bit output: CLKOUT1
.CLKOUT2 (CLKOUT2), // 1-bit output: CLKOUT2
.CLKOUT3 (CLKOUT3), // 1-bit output: CLKOUT3
.CLKOUT4 (CLKOUT4), // 1-bit output: CLKOUT4
.CLKOUT5 (CLKOUT5), // 1-bit output: CLKOUT5
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(CLKFB), // 1-bit output: Feedback clock
.LOCKED (LOCKED), // 1-bit output: LOCK
.CLKIN1 (clk), // 1-bit input: Input clock
// Control Ports: 1-bit (each) input: PLL control ports
.PWRDWN (1'b0), // 1-bit input: Power-down
.RST (~rst), // 1-bit input: Reset
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN (CLKFB) // 1-bit input: Feedback clock
);
rom #(
.bus_addr_pgm_width(`BUS_ADDR_PGM_LEN),
.rom_path("core1ROM.mem")
) rom (
.pmem_a(pgm_addr),
.pmem_d(pgm_data)
);
ram #(
.bus_addr_data_width(`BUS_ADDR_DATA_LEN),
.ram_path("NONE")
) ram (
.clk(core_clk),
.dmem_re(data_re),
.dmem_we(data_we),
.dmem_a(data_addr),
.dmem_r(data_in),
.dmem_w(data_out)
);
reg [7:0] out_led;
wire io_select_0 = (io_addr == 0 & (io_we | io_re)) ? 1'b1 : 1'b0;
always @(posedge core_clk) begin
if (io_select_0 & io_we) {LED, RGB0[1], RGB1[1], RGB2[1], RGB3[1]} <= io_out;
end
assign io_in = (io_re & io_select_0) ? {BTN, SW} : 8'bz; //
reg RST = 0;
initial begin
RST = 0;
#1;
RST = 1;
#1000;
$finish;
end
mega_core #(
.bus_addr_pgm_width (`BUS_ADDR_PGM_LEN),
.bus_addr_data_width(`BUS_ADDR_DATA_LEN)
) core (
.rst(~rst),
.clk(core_clk),
//.pgm_re(1'b1),
.pgm_addr(pgm_addr),
.pgm_data(pgm_data),
.data_re (data_re),
.data_we (data_we),
.data_addr(data_addr),
.data_in (data_in),
.data_out (data_out),
.io_re (io_re),
.io_we (io_we),
.io_addr(io_addr),
.io_out (io_out),
.io_in (io_in)
);
endmodule
| 7.151178 |
module top (
input [3:0] S,
input [15:0] D,
output M2,
M4,
M8,
M16
);
wire a, c, d, e, g;
reg b, h, f;
always @(*) begin
unique case (a)
0: b = c;
1: b = d;
endcase
unique case (g)
0: h = c;
1: h = d;
endcase
priority case (e)
0: f = c;
1: f = d;
endcase
end
endmodule
| 7.233807 |
module top (
input [7:0] data_a,
data_b,
input [6:1] addr_a,
addr_b,
input we_a,
we_b,
re_a,
re_b,
clk,
output reg [7:0] q_a,
q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @(posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b) begin
q_a <= ram[addr_a];
end
end
// Port B
always @(posedge clk) begin
if (we_b) begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b) begin
q_b <= ram[addr_b];
end
end
endmodule
| 7.233807 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'UNROLL_ALL_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/UNROLL_ALL_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/UNROLL_ALL_V/sim_UNROLL_ALL_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
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