code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_17 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_16 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_15 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_14 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_13 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_cordic_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24245, n2;
AND2X1_HVT main_gate (
.A1(net24245),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24245)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_value_correct_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24210, n2;
AND2X1_HVT main_gate (
.A1(net24210),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24210)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_value_correct_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24210, n2;
AND2X1_HVT main_gate (
.A1(net24210),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24210)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_0 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n1;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n1),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n1)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_35 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_34 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_33 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_32 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_31 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_30 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_29 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_28 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_27 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_26 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_25 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_18 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_17 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_16 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_15 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_14 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_13 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_div_mantissa_DATAWIDTH57_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net24014, n2;
AND2X1_HVT main_gate (
.A1(net24014),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net24014)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_0 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n1;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n1),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n1)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_12 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_11 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_10 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_9 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_8 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_7 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_6 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_5 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_4 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_3 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_2 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_mul_mantissa_mydesign_1 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net23937, n2;
AND2X1_HVT main_gate (
.A1(net23937),
.A2(CLK),
.Y (ENCLK)
);
LATCHX1_HVT latch (
.CLK(n2),
.D (EN),
.Q (net23937)
);
INVX2_HVT U1 (
.A(CLK),
.Y(n2)
);
endmodule
| 6.575704 |
module top_pong_animated (
input clk,
rst_n,
input [1:0] key, //key[1] to move down,key[0] to move up
output [4:0] vga_out_r,
output [5:0] vga_out_g,
output [4:0] vga_out_b,
output vga_out_vs,
vga_out_hs
);
wire clk_out;
wire video_on;
wire [11:0] pixel_x, pixel_y;
dcm_25MHz m0 ( // Clock in ports
.clk (clk), // IN
// Clock out ports
.clk_out(clk_out), // OUT
// Status and control signals
.RESET (RESET), // IN
.LOCKED (LOCKED)
);
vga_core m1 //clock must be 25MHz for 640x480
(
.clk(clk_out),
.rst_n(rst_n),
.hsync(vga_out_hs),
.vsync(vga_out_vs),
.video_on(video_on),
.pixel_x(pixel_x),
.pixel_y(pixel_y)
);
pong_animated m2 //classic pong game but with breakable "bricks" rather than wall
(
.clk(clk_out),
.rst_n(rst_n),
.key(key),
.video_on(video_on),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.r(vga_out_r),
.g(vga_out_g),
.b(vga_out_b)
);
endmodule
| 7.924382 |
module top_poola_S2_K2 #(
parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
///////////architecture parameters//////
IFM_SIZE = 28,
IFM_DEPTH = 6,
ARITH_TYPE = 0,
KERNAL_SIZE = 2,
//////////////////////////////////////
IFM_SIZE_NEXT = (IFM_SIZE - KERNAL_SIZE) / 2 + 1,
ADDRESS_SIZE_IFM = $clog2(IFM_SIZE * IFM_SIZE),
ADDRESS_SIZE_NEXT_IFM = $clog2(IFM_SIZE_NEXT * IFM_SIZE_NEXT)
) (
input clk,
input reset,
input start_from_previous,
input [ DATA_WIDTH-1:0] data_in_A,
input [ DATA_WIDTH-1:0] data_in_B,
output ifm_enable_read_A_current,
output ifm_enable_read_B_current,
output [ADDRESS_SIZE_IFM-1:0] ifm_address_read_A_current,
output [ADDRESS_SIZE_IFM-1:0] ifm_address_read_B_current,
output end_to_previous,
input end_from_next,
output ifm_enable_write_next,
output [ADDRESS_SIZE_NEXT_IFM-1:0] ifm_address_write_next,
output [ DATA_WIDTH-1 : 0] data_out,
output start_to_next,
output ifm_sel_next
);
wire fifo_enable;
wire pool_enable;
poola_cu_S2 #(
.IFM_SIZE(IFM_SIZE),
.KERNAL_SIZE(KERNAL_SIZE)
) CU (
.clk(clk),
.reset(reset),
.start_from_previous(start_from_previous),
.end_from_next(end_from_next),
.end_to_previous(end_to_previous),
.ifm_enable_read_A_current(ifm_enable_read_A_current),
.ifm_enable_read_B_current(ifm_enable_read_B_current),
.ifm_address_read_A_current(ifm_address_read_A_current),
.ifm_address_read_B_current(ifm_address_read_B_current),
.fifo_enable(fifo_enable),
.pool_enable(pool_enable),
.ifm_enable_write_next(ifm_enable_write_next),
.ifm_address_write_next(ifm_address_write_next),
.start_to_next(start_to_next),
.ifm_sel_next(ifm_sel_next)
);
poola_dp_S2 #(
.DATA_WIDTH(DATA_WIDTH),
.IFM_SIZE(IFM_SIZE),
.ARITH_TYPE(ARITH_TYPE),
.IFM_DEPTH(IFM_DEPTH),
.KERNAL_SIZE(KERNAL_SIZE)
) DP (
.clk (clk),
.reset(reset),
.fifo_enable(fifo_enable),
.pool_enable(pool_enable),
.data_in_A(data_in_A),
.data_in_B(data_in_B),
.data_out (data_out)
);
endmodule
| 7.060616 |
module top_poolb_U2_S2_K2 #(
parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
///////////architecture parameters//////
IFM_SIZE = 10,
IFM_DEPTH = 16,
KERNAL_SIZE = 2,
ARITH_TYPE = 0,
NUMBER_OF_UNITS = 2,
//////////////////////////////////////
NUMBER_OF_IFM_NEXT = IFM_DEPTH,
IFM_SIZE_NEXT = (IFM_SIZE - KERNAL_SIZE) / 2 + 1,
ADDRESS_SIZE_IFM = $clog2(IFM_SIZE * IFM_SIZE),
ADDRESS_SIZE_NEXT_IFM = $clog2(IFM_SIZE_NEXT * IFM_SIZE_NEXT)
) (
input clk,
input reset,
input start_from_previous,
input [ DATA_WIDTH-1:0] data_in_A_from_previous1,
input [ DATA_WIDTH-1:0] data_in_B_from_previous1,
input [ DATA_WIDTH-1:0] data_in_A_from_previous2,
input [ DATA_WIDTH-1:0] data_in_B_from_previous2,
output ifm_enable_read_A_current,
output ifm_enable_read_B_current,
output [ADDRESS_SIZE_IFM-1:0] ifm_address_read_A_current,
output [ADDRESS_SIZE_IFM-1:0] ifm_address_read_B_current,
output end_to_previous,
input conv_ready,
input end_from_next,
output ifm_enable_write_next,
output [ADDRESS_SIZE_NEXT_IFM-1:0] ifm_address_write_next,
output [DATA_WIDTH-1 : 0] data_out_for_next1,
output [DATA_WIDTH-1 : 0] data_out_for_next2,
output start_to_next,
output [$clog2(8)-1:0] ifm_sel_next //where 8 is ceil(NUMBER_OF_IFM_NEXT/NUMBER_OF_UNITS)
);
wire fifo_enable;
wire pool_enable;
poolb_cu_U2 #(
.IFM_SIZE(IFM_SIZE),
.IFM_DEPTH(IFM_DEPTH),
.KERNAL_SIZE(KERNAL_SIZE)
) CU (
.clk(clk),
.reset(reset),
.start_from_previous(start_from_previous),
.conv_ready(conv_ready),
.end_from_next(end_from_next),
.end_to_previous(end_to_previous),
.ifm_enable_read_A_current(ifm_enable_read_A_current),
.ifm_enable_read_B_current(ifm_enable_read_B_current),
.ifm_address_read_A_current(ifm_address_read_A_current),
.ifm_address_read_B_current(ifm_address_read_B_current),
.fifo_enable(fifo_enable),
.pool_enable(pool_enable),
.ifm_enable_write_next(ifm_enable_write_next),
.ifm_address_write_next(ifm_address_write_next),
.start_to_next(start_to_next),
.ifm_sel_next(ifm_sel_next)
);
poolb_dp_U2 #(
.DATA_WIDTH(DATA_WIDTH),
.IFM_SIZE(IFM_SIZE),
.IFM_DEPTH(IFM_DEPTH),
.ARITH_TYPE(ARITH_TYPE),
.KERNAL_SIZE(KERNAL_SIZE)
) DP (
.clk (clk),
.reset(reset),
.fifo_enable(fifo_enable),
.pool_enable(pool_enable),
.data_in_A_unit1(data_in_A_from_previous1),
.data_in_B_unit1(data_in_B_from_previous1),
.data_in_A_unit2(data_in_A_from_previous2),
.data_in_B_unit2(data_in_B_from_previous2),
.data_out_1(data_out_for_next1),
.data_out_2(data_out_for_next2)
);
endmodule
| 6.696576 |
module top_poolb_U3_S2_K2 #(
parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
///////////architecture parameters//////
IFM_SIZE = 26,
IFM_DEPTH = 18,
KERNAL_SIZE = 2,
ARITH_TYPE = 0,
NUMBER_OF_UNITS = 3,
//////////////////////////////////////
NUMBER_OF_IFM_NEXT = IFM_DEPTH,
IFM_SIZE_NEXT = (IFM_SIZE - KERNAL_SIZE) / 2 + 1,
ADDRESS_SIZE_IFM = $clog2(IFM_SIZE * IFM_SIZE),
ADDRESS_SIZE_NEXT_IFM = $clog2(IFM_SIZE_NEXT * IFM_SIZE_NEXT)
) (
input clk,
input reset,
input start_from_previous,
input [ DATA_WIDTH-1:0] data_in_A_unit1,
input [ DATA_WIDTH-1:0] data_in_B_unit1,
input [ DATA_WIDTH-1:0] data_in_A_unit2,
input [ DATA_WIDTH-1:0] data_in_B_unit2,
input [ DATA_WIDTH-1:0] data_in_A_unit3,
input [ DATA_WIDTH-1:0] data_in_B_unit3,
output ifm_enable_read_A_current,
output ifm_enable_read_B_current,
output [ADDRESS_SIZE_IFM-1:0] ifm_address_read_A_current,
output [ADDRESS_SIZE_IFM-1:0] ifm_address_read_B_current,
output end_to_previous,
input conv_ready,
input end_from_next,
output ifm_enable_write_next,
output [ADDRESS_SIZE_NEXT_IFM-1:0] ifm_address_write_next,
output [DATA_WIDTH-1 : 0] data_out_1,
output [DATA_WIDTH-1 : 0] data_out_2,
output [DATA_WIDTH-1 : 0] data_out_3,
output start_to_next,
output [$clog2(6)-1:0] ifm_sel_next //where 6 is ceil(NUMBER_OF_IFM_NEXT/NUMBER_OF_UNITS)
);
wire fifo_enable;
wire pool_enable;
poolb_cu_U3 #(
.IFM_SIZE(IFM_SIZE),
.IFM_DEPTH(IFM_DEPTH),
.KERNAL_SIZE(KERNAL_SIZE)
) CU (
.clk(clk),
.reset(reset),
.start_from_previous(start_from_previous),
.conv_ready(conv_ready),
.end_from_next(end_from_next),
.end_to_previous(end_to_previous),
.ifm_enable_read_A_current(ifm_enable_read_A_current),
.ifm_enable_read_B_current(ifm_enable_read_B_current),
.ifm_address_read_A_current(ifm_address_read_A_current),
.ifm_address_read_B_current(ifm_address_read_B_current),
.fifo_enable(fifo_enable),
.pool_enable(pool_enable),
.ifm_enable_write_next(ifm_enable_write_next),
.ifm_address_write_next(ifm_address_write_next),
.start_to_next(start_to_next),
.ifm_sel_next(ifm_sel_next)
);
poolb_dp_U3 #(
.DATA_WIDTH(DATA_WIDTH),
.IFM_SIZE(IFM_SIZE),
.IFM_DEPTH(IFM_DEPTH),
.ARITH_TYPE(ARITH_TYPE),
.KERNAL_SIZE(KERNAL_SIZE)
) DP (
.clk (clk),
.reset(reset),
.fifo_enable(fifo_enable),
.pool_enable(pool_enable),
.data_in_A_unit1(data_in_A_unit1),
.data_in_B_unit1(data_in_B_unit1),
.data_in_A_unit2(data_in_A_unit2),
.data_in_B_unit2(data_in_B_unit2),
.data_in_A_unit3(data_in_A_unit3),
.data_in_B_unit3(data_in_B_unit3),
.data_out_1(data_out_1),
.data_out_2(data_out_2),
.data_out_3(data_out_3)
);
endmodule
| 6.807844 |
module top_poolb_U6_S2_K2 #(
parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
///////////architecture parameters//////
IFM_SIZE = 10,
IFM_DEPTH = 16,
KERNAL_SIZE = 2,
ARITH_TYPE = 0,
NUMBER_OF_UNITS = 6,
//////////////////////////////////////
NUMBER_OF_IFM_NEXT = IFM_DEPTH,
IFM_SIZE_NEXT = (IFM_SIZE - KERNAL_SIZE) / 2 + 1,
ADDRESS_SIZE_IFM = $clog2(IFM_SIZE * IFM_SIZE),
ADDRESS_SIZE_NEXT_IFM = $clog2(IFM_SIZE_NEXT * IFM_SIZE_NEXT)
) (
input clk,
input reset,
input start_from_previous,
input [ DATA_WIDTH-1:0] data_in_A_unit1,
input [ DATA_WIDTH-1:0] data_in_B_unit1,
input [ DATA_WIDTH-1:0] data_in_A_unit2,
input [ DATA_WIDTH-1:0] data_in_B_unit2,
input [ DATA_WIDTH-1:0] data_in_A_unit3,
input [ DATA_WIDTH-1:0] data_in_B_unit3,
input [ DATA_WIDTH-1:0] data_in_A_unit4,
input [ DATA_WIDTH-1:0] data_in_B_unit4,
input [ DATA_WIDTH-1:0] data_in_A_unit5,
input [ DATA_WIDTH-1:0] data_in_B_unit5,
input [ DATA_WIDTH-1:0] data_in_A_unit6,
input [ DATA_WIDTH-1:0] data_in_B_unit6,
output ifm_enable_read_A_current,
output ifm_enable_read_B_current,
output [ADDRESS_SIZE_IFM-1:0] ifm_address_read_A_current,
output [ADDRESS_SIZE_IFM-1:0] ifm_address_read_B_current,
output end_to_previous,
input conv_ready,
input end_from_next,
output ifm_enable_write_next,
output [ADDRESS_SIZE_NEXT_IFM-1:0] ifm_address_write_next,
output [DATA_WIDTH-1 : 0] data_out_1,
output [DATA_WIDTH-1 : 0] data_out_2,
output [DATA_WIDTH-1 : 0] data_out_3,
output [DATA_WIDTH-1 : 0] data_out_4,
output [DATA_WIDTH-1 : 0] data_out_5,
output [DATA_WIDTH-1 : 0] data_out_6,
output start_to_next,
output [$clog2(3)-1:0] ifm_sel_next //where 3 is ceil(NUMBER_OF_IFM_NEXT/NUMBER_OF_UNITS)
);
wire fifo_enable;
wire pool_enable;
poolb_cu_U6 #(
.IFM_SIZE(IFM_SIZE),
.IFM_DEPTH(IFM_DEPTH),
.KERNAL_SIZE(KERNAL_SIZE)
) CU (
.clk(clk),
.reset(reset),
.start_from_previous(start_from_previous),
.conv_ready(conv_ready),
.end_from_next(end_from_next),
.end_to_previous(end_to_previous),
.ifm_enable_read_A_current(ifm_enable_read_A_current),
.ifm_enable_read_B_current(ifm_enable_read_B_current),
.ifm_address_read_A_current(ifm_address_read_A_current),
.ifm_address_read_B_current(ifm_address_read_B_current),
.fifo_enable(fifo_enable),
.pool_enable(pool_enable),
.ifm_enable_write_next(ifm_enable_write_next),
.ifm_address_write_next(ifm_address_write_next),
.start_to_next(start_to_next),
.ifm_sel_next(ifm_sel_next)
);
poolb_dp_U6 #(
.DATA_WIDTH(DATA_WIDTH),
.IFM_SIZE(IFM_SIZE),
.IFM_DEPTH(IFM_DEPTH),
.ARITH_TYPE(ARITH_TYPE),
.KERNAL_SIZE(KERNAL_SIZE)
) DP (
.clk (clk),
.reset(reset),
.fifo_enable(fifo_enable),
.pool_enable(pool_enable),
.data_in_A_unit1(data_in_A_unit1),
.data_in_B_unit1(data_in_B_unit1),
.data_in_A_unit2(data_in_A_unit2),
.data_in_B_unit2(data_in_B_unit2),
.data_in_A_unit3(data_in_A_unit3),
.data_in_B_unit3(data_in_B_unit3),
.data_in_A_unit4(data_in_A_unit4),
.data_in_B_unit4(data_in_B_unit4),
.data_in_A_unit5(data_in_A_unit5),
.data_in_B_unit5(data_in_B_unit5),
.data_in_A_unit6(data_in_A_unit6),
.data_in_B_unit6(data_in_B_unit6),
.data_out_1(data_out_1),
.data_out_2(data_out_2),
.data_out_3(data_out_3),
.data_out_4(data_out_4),
.data_out_5(data_out_5),
.data_out_6(data_out_6)
);
endmodule
| 6.594255 |
module top (
input x,
input y,
input cin,
output A,
output cout,
output signed pow,
output signed pow2
);
wire p, n;
assign pow = 2 ** y;
assign pow2 = 2 ** 2;
assign p = +x;
assign n = -x;
assign A = cin * x;
endmodule
| 7.233807 |
module Top_Processor_Module (
input [7:0] data_in,
input clk,
input interrupt,
input reset,
output [7:0] data_out
);
wire [23:0] ins;
wire [7:0] A;
wire [7:0] B;
wire [7:0] Current_Address;
wire [7:0] ans_ex;
wire [7:0] ans_dm;
wire [7:0] ans_wb;
wire [1:0] mux_sel_A;
wire [1:0] mux_sel_B;
wire imm_sel;
wire [7:0] jmp_loc, DM_data, imm;
wire [3:0] flag_ex;
wire [4:0] op_dec, RW_dm;
// wire[1:0] mux_sel_A,mux_sel_B;
wire pc_mux_sel, Stall, Stall_pm, mem_rw_ex, mem_en_ex, mem_mux_sel_dm;
//IF
PC_IM pcim (
ins,
Current_Address,
jmp_loc,
pc_mux_sel,
Stall,
Stall_pm,
clk,
reset
); //
Dependency_Check_Block dcb (
ins,
clk,
reset,
imm,
RW_dm,
op_dec,
mux_sel_A,
mux_sel_B,
imm_sel,
mem_en_ex,
mem_rw_ex,
mem_mux_sel_dm
);
Stall_Control_Block scb (
ins,
clk,
reset,
Stall,
Stall_pm
); //
Jump_Control_Block jc (
ins,
Current_Address,
flag_ex,
interrupt,
clk,
reset,
jmp_loc,
pc_mux_sel
); //
//ID
Register_Bank rb (
ins,
ans_ex,
ans_dm,
ans_wb,
imm,
RW_dm,
mux_sel_A,
mux_sel_B,
imm_sel,
clk,
A,
B
); //
//ALU
//ALU_8bit exe(ans_ex,DM_data,data_out,flag_ex,A,B,data_in,op_dec,clk,reset);//
Execution_block eb (
ans_ex,
data_out,
DM_data,
flag_ex,
A,
B,
data_in,
op_dec,
clk,
reset
);
//DM
Data_Mem Dm (
ans_ex,
DM_data,
mem_rw_ex,
mem_en_ex,
mem_mux_sel_dm,
reset,
clk,
ans_dm
); //
//WB
Write_Back_Block wb (
ans_dm,
clk,
reset,
ans_wb
); //
endmodule
| 8.045154 |
module: Top_Processor_Module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_Processor_Module_tb;
// Inputs
reg [7:0] data_in;
reg clk;
reg interrupt;
reg reset;
// Outputs
wire [7:0] data_out;
wire [23:0] ins;
wire [7:0] A;
wire [7:0] B;
wire [7:0] Current_Address;
wire [7:0] ans_ex;
wire [7:0] ans_dm;
wire [7:0] ans_wb;
wire [1:0] mux_sel_A;
wire [1:0] mux_sel_B;
wire imm_sel;
// Instantiate the Unit Under Test (UUT)
Top_Processor_Module uut (
.data_in(data_in),
.clk(clk),
.interrupt(interrupt),
.reset(reset),
.data_out(data_out),
.ins(ins),
.A(A),
.B(B),
.Current_Address(Current_Address),
.ans_ex(ans_ex),
.ans_dm(ans_dm),
.ans_wb(ans_wb),
.mux_sel_A(mux_sel_A),
.mux_sel_B(mux_sel_B),
.imm_sel(imm_sel)
);
initial begin
// Initialize Inputs
data_in = 0;
interrupt = 0;
clk = 0;
reset = 1;
#200; reset = 0;
#500; reset = 1;
end
always
#500 clk = ~clk;
endmodule
| 7.460419 |
module tristate (
en,
i,
o
);
input en;
input i;
output o;
assign o = (en) ? i : 1'bZ;
endmodule
| 6.741184 |
module top (
input en,
input a,
output b
);
tristate u_tri (
.en(en),
.i (a),
.o (b)
);
endmodule
| 7.233807 |
module Top_prueba_botones_VGA (
input wire clk,
input wire reset,
input wire [3:0] sw, //3 interruptores
input wire [3:0] btn, //4 botones
output wire hsync,
vsync,
output wire [11:0] RGB
);
wire [3:0] sw_db; //debounce
wire [3:0] btn_db; //debounce
wire [3:0] digit0_HH, digit1_HH, digit0_MM, digit1_MM, digit0_SS, digit1_SS, //
digit0_DAY, digit1_DAY, digit0_MES, digit1_MES, digit0_YEAR, digit1_YEAR, //
digit0_HH_T, digit1_HH_T, digit0_MM_T, digit1_MM_T, digit0_SS_T, digit1_SS_T;//Decenas y unidades para los nmeros en pantalla (18 inputs de 3 bits)
wire AM_PM;
wire [7:0] dia_semana;
wire [1:0] cursor_location;
debouncing Instancia_debouncing (
.clk(clk),
.reset(reset),
.sw(sw), //3 interruptores
.btn(btn), //4 botones
.sw_db(sw_db), //debounce
.btn_db(btn_db) //debounce
);
contadores_configuracion Instancia_contadores_configuracion (
.clk(clk),
.reset(reset),
.enUP(btn_db[0]),
.enDOWN(btn_db[1]),
.enLEFT(btn_db[2]),
.enRIGHT(btn_db[3]),
.config_mode({sw_db[1], sw_db[0]}), //Cuatro estados del modo configuracin
.formato_hora(sw_db[2]),
.digit0_HH(digit0_HH),
.digit1_HH(digit1_HH),
.digit0_MM(digit0_MM),
.digit1_MM(digit1_MM),
.digit0_SS(digit0_SS),
.digit1_SS(digit1_SS), //
.digit0_DAY(digit0_DAY),
.digit1_DAY(digit1_DAY),
.digit0_MES(digit0_MES),
.digit1_MES(digit1_MES),
.digit0_YEAR(digit0_YEAR),
.digit1_YEAR(digit1_YEAR), //
.digit0_HH_T(digit0_HH_T),
.digit1_HH_T(digit1_HH_T),
.digit0_MM_T(digit0_MM_T),
.digit1_MM_T(digit1_MM_T),
.digit0_SS_T(digit0_SS_T),
.digit1_SS_T(digit1_SS_T),
.AM_PM(AM_PM), //Entrada para conocer si en la informacin de hora se despliega AM o PM
.dia_semana(dia_semana), //Para interpretar el dia de la semana a escribir (3-bits: 7 das)
.cursor_location(cursor_location) //Marca la posicin del cursor en modo configuracin
);
Clock_screen_top Instancia_Clock_screen_top (
.clock(clk),
.reset(reset),
.digit0_HH(digit0_HH),
.digit1_HH(digit1_HH),
.digit0_MM(digit0_MM),
.digit1_MM(digit1_MM),
.digit0_SS(digit0_SS),
.digit1_SS(digit1_SS), //
.digit0_DAY(digit0_DAY),
.digit1_DAY(digit1_DAY),
.digit0_MES(digit0_MES),
.digit1_MES(digit1_MES),
.digit0_YEAR(digit0_YEAR),
.digit1_YEAR(digit1_YEAR), //
.digit0_HH_T(digit0_HH_T),
.digit1_HH_T(digit1_HH_T),
.digit0_MM_T(digit0_MM_T),
.digit1_MM_T(digit1_MM_T),
.digit0_SS_T(digit0_SS_T),
.digit1_SS_T(digit1_SS_T),//Decenas y unidades para los nmeros en pantalla (18 inputs de 3 bits)
.AM_PM(AM_PM), //Entrada para conocer si en la informacin de hora se despliega AM o PM
.dia_semana(dia_semana[2:0]),//Para interpretar el dia de la semana a escribir (3-bits: 7 das)
.config_mode({sw_db[1], sw_db[0]}), //1-bit: OR de los tres estados del modo configuracin
.cursor_location(cursor_location), //Marca la posicin del cursor en modo configuracin
.timer_end(sw_db[3]),//bandera proveniente del RTC que indica la finalizacin del tiempo del timer
.formato_hora(sw_db[2]),//Seal que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
.hsync(hsync),
.vsync(vsync),
.RGB(RGB)
);
endmodule
| 7.632171 |
module TOP_test_2 (
input wire clk,
input wire entrada_PWM,
input wire C_valid_PWM,
input wire PWM_select,
output wire ready,
output wire PWM_signal
);
PWM PWM_real (
//entradas
.clk(clk),
.data(entrada_PWM),
.select(PWM_select),
.PWM_valid_I(C_valid_PWM),
//saidas
.PWM_signal(PWM_signal),
.PWM_TOP(ready)
);
endmodule
| 8.495523 |
module top_pwm_gen (
input i_clk,
i_reset,
input [7:0] i_ocr,
output o_pwm
);
wire w_clk_1M;
wire [7:0] w_cnt;
clockDivider #(
.MAX_COUNT(50)
) D0 (
.i_clk (i_clk),
.i_reset(i_reset),
.o_clk (w_clk_1M)
);
counter D1 (
.i_clk (w_clk_1M),
.i_reset(i_reset),
.o_cnt (w_cnt)
);
comparator D3 (
.i_a (w_cnt),
.i_b (i_ocr),
.o_lt(o_pwm)
);
endmodule
| 7.327685 |
module top_pwm_ScRomPc (
pwm_gen,
push_btn,
tp_clk,
tp_rst
);
input push_btn, tp_clk, tp_rst;
output pwm_gen;
wire [2:0] w_sel_dec; //Connects "sel" & "sel_dec".
selection_counter m_sc1 (
.sel (w_sel_dec),
.clk (tp_clk),
.rst_n(tp_rst),
.pb_in(push_btn)
);
wire [15:0] w_nOut; //Connects "n_out" & "n_rom".
rom_n m_rom2 (
.n_out (w_nOut),
.sel_dec(w_sel_dec)
);
pwm_counter m_pc3 (
.pwm (pwm_gen),
.strt (push_btn),
.clk (tp_clk),
.rst_n(tp_rst),
.n_rom(w_nOut)
);
endmodule
| 8.190166 |
module top_qam #(
parameter width_data = 16,
parameter wid_count = 4,
parameter No_reg = 16
) (
input clk,
input rst_n,
input rst_clk,
input start,
input data_in,
output [width_data-1:0] data_transmitter,
output [width_data-1:0] sum //tong 2 song mang
);
wire data_out_CP; //output cua Cyclic prefix
wire ready_CP;
wire [width_data-1:0] data_I;
wire [width_data-1:0] data_Q;
wire [width_data-1:0] data_out_zp_I;
wire [width_data-1:0] data_out_zp_Q;
wire [width_data-1:0] data_out_fil_I;
wire [width_data-1:0] data_out_fil_Q;
wire [width_data-1:0] data_out_carry_I;
wire [width_data-1:0] data_out_carry_Q;
wire [width_data-1:0] carrier_sum;
wire ready_mapper;
wire ready_zero;
wire ready_filter;
wire ready_carrier;
wire clk_164; //clk_164=12clk
wire clk_41; //clk_41=3clk : su dung cho khoi zero_padder va filter
wire clk_40; //clk_40=2clk : su dung cho khoi pilot
wire sel_zero_pad;
wire ce_shift;
wire [ wid_count-1:0] sel_carrier;
assign sum = carrier_sum;
controller_qam_16 #(
.wid_count(wid_count)
) controller (
.clk(clk),
.rst_clk(rst_clk),
.rst_n(rst_n),
.ready_mapper(ready_mapper),
.ready_zero(ready_zero),
.ready_filter(ready_filter),
.clk_40(clk_40),
.clk_41(clk_41),
.clk_164(clk_164),
.sel_zero_pad(sel_zero_pad),
.sel_carrier(sel_carrier),
.ce_shift(ce_shift)
);
cyclic_prefix cyclic_prefix_block (
.clk(clk_164),
.rst_n(rst_n),
.data_in(data_in),
.start(start),
.data_out(data_out_CP),
.ready(ready_CP)
);
mapper #(
.width_data(width_data)
) mapper_qam (
.data_in(data_out_CP),
.clk(clk_164),
.rst_n(rst_n),
.start(ready_CP),
.data_I(data_I),
.data_Q(data_Q),
.ready(ready_mapper)
);
zero_padder #(
.width_data(width_data)
) zero_padder_I (
.clk(clk_41),
.rst_n(rst_n),
.start(ready_mapper),
.sel(sel_zero_pad),
.data_in(data_I),
.data_out(data_out_zp_I),
.ready(ready_zero)
);
zero_padder #(
.width_data(width_data)
) zero_padder_Q (
.clk(clk_41),
.rst_n(rst_n),
.start(ready_mapper),
.sel(sel_zero_pad),
.data_in(data_Q),
.data_out(data_out_zp_Q),
.ready()
);
raised_cosin_filter #(
.width_data(width_data),
.No_reg(No_reg)
) filter_I (
.clk(clk_41),
.rst_n(rst_n),
.start(ready_zero),
.data_in(data_out_zp_I),
.ce_shift(ce_shift),
.data_out(data_out_fil_I),
.ready(ready_filter)
);
raised_cosin_filter #(
.width_data(width_data),
.No_reg(No_reg)
) filter_Q (
.clk(clk_41),
.rst_n(rst_n),
.start(ready_zero),
.data_in(data_out_zp_Q),
.ce_shift(ce_shift),
.data_out(data_out_fil_Q),
.ready()
);
carrier_multi_sin #(
.width_sym(width_data),
.width_sel(wid_count)
) carrier_multi_sin_I (
.clk(clk_41),
.rst_n(rst_n),
.sel(sel_carrier),
.data_in(data_out_fil_I),
.start(ready_filter),
.data_out(data_out_carry_I),
.ready(ready_carrier)
);
carrier_multi_cos #(
.width_sym(width_data),
.width_sel(wid_count)
) carrier_multi_cos_Q (
.clk(clk_41),
.rst_n(rst_n),
.sel(sel_carrier),
.data_in(data_out_fil_Q),
.start(ready_filter),
.data_out(data_out_carry_Q),
.ready()
);
carrier_adder #(
.width_data(width_data)
) signal_carrier (
.carrier_1(data_out_carry_I),
.carrier_2(data_out_carry_Q),
.clk(clk_41),
.rst_n(rst_n),
.carrier_sum(carrier_sum)
);
pilot #(
.width_data(width_data)
) pilot_inserter (
.clk1(clk_41),
.clk2(clk_40),
.rst_n(rst_n),
.data_in(carrier_sum),
.start(ready_carrier),
.data_out(data_transmitter)
);
endmodule
| 7.727441 |
module top_qam_receiver #(
parameter width_data = 16,
parameter width_reg = 18,
parameter COUNT_WIDTH = 4,
parameter kp = 0.026, //0.0000011010100111 6 7 9 11 14 15 16
parameter ki = 0.00069, //0.00000000001011010011
parameter k = 0.02531 //kp-ki=0.0000011001111010 6 7 10 11 12 13 15
) (
input [width_data-1:0] data_in,
input clk,
input start,
input rst_n,
input rst_clk,
output [width_data-1:0] data_out_I,
output [width_data-1:0] data_out_Q,
output ready
);
wire clk_40; //Doc du lieu vao
wire clk_41; //doc du lieu ra
wire clk_656;
wire clk_16;
wire [width_data-1:0] data_cut;
wire [width_data-1:0] data_carry_I, data_carry_Q;
wire [width_data-1:0] data_fil_I, data_fil_Q;
wire [width_data-1:0] data_sam_I, data_sam_Q;
wire ready_cut; //cut_pilot
wire ready_carry;
wire ready_fil;
wire ready_sampling;
/////////////////////////////////
//Khoi tao clock
gen_clk gen_clock (
.clk(clk),
.rst_clk(rst_clk),
.clk_40(clk_40),
.clk_41(clk_41),
.clk_656(clk_656),
.clk_16(clk_16)
);
/////////////////////////////////
//cut 10 so 1 trong doan du lieu:cut pilot
cut_pilot #(
.width_data(width_data)
) cut_pilot_inst (
.clk1(clk_40), //Doc du lieu vao
.clk2(clk_41), //Ghi du lieu ra
.rst_n(rst_n),
.data_in(data_in),
.start(start),
.data_out(data_cut),
.ready(ready_cut)
);
/////////////////////////////////
//carrier mutiplie I
carrier_multi_sin #(
.width_sym(width_data)
) carrier_I (
.clk(clk_41),
.rst_n(rst_n),
.data_in(data_cut),
.start(ready_cut),
.data_out(data_carry_I),
.ready(ready_carry)
);
//carrier mutiplie Q
carrier_multi_cos #(
.width_sym(width_data)
) carrier_Q (
.clk(clk_41),
.rst_n(rst_n),
.data_in(data_cut),
.start(ready_cut),
.data_out(data_carry_Q),
.ready()
);
/////////////////////////////////////
//raised_cosin_filter
//filter_I
raised_cosin_filter #(
.width_data(width_data),
.No_reg(width_data)
) filter_I (
.clk(clk_41),
.rst_n(rst_n),
.start(ready_carry),
.data_in(data_carry_I),
.data_out(data_fil_I),
.ready(ready_fil)
);
//filter_Q
raised_cosin_filter #(
.width_data(width_data),
.No_reg(width_data)
) filter_Q (
.clk(clk_41),
.rst_n(rst_n),
.start(ready_carry),
.data_in(data_carry_Q),
.data_out(data_fil_Q),
.ready()
);
////////////////////////////////////////////
//sampling
//sampling_I
sampling #(
.width(width_data)
) sampling_data_I (
.data_in(data_fil_I),
.clk(clk_656),
.rst_n(rst_n),
.start(ready_fil),
.data_out(data_sam_I),
.ready(ready_sampling)
);
//sampling_Q
sampling #(
.width(width_data)
) sampling_data_Q (
.data_in(data_fil_Q),
.clk(clk_656),
.rst_n(rst_n),
.start(ready_fil),
.data_out(data_sam_Q),
.ready()
);
//////////////////////////////////////////
//Phase lock loop
top_pll #(
.width_data (width_data),
.width_reg (width_reg),
.COUNT_WIDTH(COUNT_WIDTH),
.kp (kp),
.ki (ki),
.k (k)
) phase_lock_loop_qam (
.x_in (data_sam_I),
.y_in (data_sam_Q),
.clk (clk_16),
.rst_n(rst_n),
.start(ready_sampling),
.x_out(data_out_I),
.y_out(data_out_Q),
.ready(ready)
);
endmodule
| 6.869751 |
module Read_Channel #(
parameter IDW = 12, // ID
parameter AW = 32, // Addr
parameter DW = 32
) (
input clk, // global clock signal.
input resetn, // global reset singal.
//Read address channel
input [AW-1 : 0] araddr_in,
input [ 7 : 0] arlen_in,
input [ 2 : 0] arsize_in,
input [ 1 : 0] arburst_in,
input arvalid_in,
output [AW-1 : 0] axi_araddr, // master interface read address
output [ 7 : 0] axi_arlen, // burst length.
output [ 2 : 0] axi_arsize, // burst size.
output [ 1 : 0] axi_arburst, // burst type.
output axi_arvalid, // read address valid
output axi_arready, // read address ready
//Read data channel
input [63 : 0] rdata_in,
input rvalid_in,
input rready_in,
output [63 : 0] axi_rdata, // slave interface read data.
output axi_rlast, // last transfer in a read burst.
output axi_rvalid, // indicates data is ready to go
output axi_rready // master is ready for data
);
EmeshAxiMasterBridge_read m_r (
.__ILA_EmeshAxiMasterBridge_read_grant__(5'b11111),
.araddr (araddr_in),
.arburst (arburst_in),
.arlen (arlen_in),
.arsize (arsize_in),
.clk (clk),
.m_axi_aresetn (resetn),
.m_axi_arready (axi_arready),
.m_axi_rdata (axi_rdata),
.m_axi_rid (),
.m_axi_rlast (axi_rlast),
.m_axi_rresp (),
.m_axi_rvalid (axi_rvalid),
.nondet_unknown12_n20(),
.nondet_unknown13_n24(),
.nondet_unknown14_n28(),
.nondet_unknown15_n32(),
.read_ready(rready_in),
.read_valid(arvalid_in),
.rst(1'b0),
.__ILA_EmeshAxiMasterBridge_read_acc_decode__(),
.__ILA_EmeshAxiMasterBridge_read_decode_of_AR_Master_Asserted__(),
.__ILA_EmeshAxiMasterBridge_read_decode_of_AR_Master_Commit__(),
.__ILA_EmeshAxiMasterBridge_read_decode_of_AR_Master_Prepare__(),
.__ILA_EmeshAxiMasterBridge_read_decode_of_R_Master_Reset__(),
.__ILA_EmeshAxiMasterBridge_read_decode_of_R_Master_Wait__(),
.__ILA_EmeshAxiMasterBridge_read_valid__(),
.m_axi_arid (),
.m_axi_araddr (axi_araddr),
.m_axi_arlen (axi_arlen),
.m_axi_arsize (axi_arsize),
.m_axi_arburst(axi_arburst),
.m_axi_arlock (),
.m_axi_arcache(),
.m_axi_arprot (),
.m_axi_arqos (),
.m_axi_arvalid(axi_arvalid),
.m_axi_rready (axi_rready)
);
EmeshAxiSlaveBridge_read s_r (
.__ILA_EmeshAxiSlaveBridge_read_grant__(6'b111111),
.clk(clk),
.read_data_15_0(rdata_in[15:0]),
.read_data_31_0(rdata_in[31:0]),
.read_data_7_0(rdata_in[7:0]),
.read_resp(),
.read_valid(rvalid_in),
.rst(1'b0),
.s_axi_araddr (axi_araddr),
.s_axi_arburst(axi_arburst),
.s_axi_arcache(),
.s_axi_aresetn(resetn),
.s_axi_arid (),
.s_axi_arlen (axi_arlen),
.s_axi_arlock (),
.s_axi_arprot (),
.s_axi_arqos (),
.s_axi_arsize (axi_arsize),
.s_axi_arvalid(axi_arvalid),
.s_axi_rready (axi_rready),
.__ILA_EmeshAxiSlaveBridge_read_acc_decode__(),
.__ILA_EmeshAxiSlaveBridge_read_decode_of_AR_Slave_Commit__(),
.__ILA_EmeshAxiSlaveBridge_read_decode_of_AR_Slave_Wait__(),
.__ILA_EmeshAxiSlaveBridge_read_decode_of_R_Slave_Asserted__(),
.__ILA_EmeshAxiSlaveBridge_read_decode_of_R_Slave_Busy__(),
.__ILA_EmeshAxiSlaveBridge_read_decode_of_R_Slave_Prepare__(),
.__ILA_EmeshAxiSlaveBridge_read_decode_of_R_Slave_Reset__(),
.__ILA_EmeshAxiSlaveBridge_read_valid__(),
.s_axi_arready(axi_arready),
.s_axi_rid (),
.s_axi_rdata (axi_rdata),
.s_axi_rlast (axi_rlast),
.s_axi_rresp (),
.s_axi_rvalid (axi_rvalid),
.tx_ractive (),
.tx_arlen (),
.tx_arsize (),
.tx_araddr (),
.tx_arburst ()
);
endmodule
| 6.97705 |
module top_race_game (
input wire clk,
reset,
ps2d,
ps2c,
output wire hsync,
vsync,
output wire [11:0] rgb_out,
output pwm,
aud_on
);
//variables
wire left_key, right_key, enter_key, key_relese, game_reset;
wire video_on, p_tick, road_on, finish_line, car_on, start_en, crash_en, finish_en;
wire [9:0] pixel_x, pixel_y;
//intantiate models
//keyboard
keyboard inkey (
clk,
reset,
ps2d,
ps2c,
left_key,
right_key,
enter_key,
key_relese
);
//graphics
graphics race_graph (
clk,
game_reset,
pause,
left_key,
right_key,
enter_key,
video_on,
start_en,
crash_en,
finish_en,
pixel_x,
pixel_y,
road_on,
finish_line,
car_on,
rgb_out
);
//game_state
game_state game_states (
clk,
reset,
video_on,
road_on,
finish_line,
car_on,
enter_key,
key_relese,
start_en,
crash_en,
finish_en,
pause,
game_reset
);
//vga_sync
vga_sync vga (
clk,
reset,
hsync,
vsync,
video_on,
p_tick,
pixel_x,
pixel_y
);
//Sound
song1 mysong (
clk,
reset,
pause,
aud_on,
pwm
);
endmodule
| 8.773083 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module top_ram2port (
input [17:0] SW,
input [ 1:0] KEY,
input CLOCK_50,
output [17:0] LEDR,
output [ 7:0] LEDG,
input UART_RXD
);
wire [7:0] rx_data;
wire rx_done;
rx_controller rx (
.clk(CLOCK_50),
.UART_RXD(UART_RXD),
.RX_DATA(rx_data),
.RX_DONE(rx_done)
);
reg [23:0] instr_wdata;
ram2port text_mem (
.byteena_a(4'b1111),
.clock(CLOCK_50),
.data({rx_data, instr_wdata}),
.rdaddress(SW[15:0]),
.wraddress(instr_waddr[10:2]),
.wren(rx_done & SW[17] & (instr_waddr[1:0] == 2'b11)),
.q(LEDR)
);
wire instr_wen;
assign instr_wen = (rx_done) & SW[17];
wire instr_byteen = instr_waddr[1:0];
assign LEDG = instr_waddr;
reg [10:0] instr_waddr;
always @(posedge CLOCK_50) begin
if (~KEY[0]) begin
instr_waddr <= 0;
instr_wdata <= 0;
end else begin
if (instr_wen) begin
instr_waddr <= instr_waddr + 1;
instr_wdata <= {rx_data, instr_wdata[23:8]};
end
end
end
endmodule
| 6.923214 |
module top_read_id (
input clk,
input spi_miso,
output uart_tx,
output spi_clk,
output spi_cs,
output spi_mosi
);
wire clk;
wire spi_miso;
// UART Section ---------------------------------------------------
reg uart_baud_clk_enable = 1;
wire baud_clk;
reg uart_send_enable = 1;
reg [7:0] uart_send_data = 0;
wire uart_busy;
wire uart_tx;
// Instanciate Baud Clock Generator
clk_generator #(
.CLK_PER_BIT(625)
) uart_baud_clk_generator (
clk,
uart_baud_clk_enable,
baud_clk
);
// Instanciate UART
uart_tx_8n1 uart (
baud_clk,
uart_send_enable,
uart_send_data,
uart_busy,
uart_tx
);
// SPI/Sensor Section ----------------------------------------------
parameter SENSOR_ADDRESS_ID = 6'h00; // Expected Id = 11100101
reg [0:7] set_spi_data = 8'b00000000;
wire [0:7] spi_data = (spi_rw) ? 8'bzzzzzzzz : set_spi_data;
reg spi_enable = 0;
reg spi_rw = 1; // 1 = read
wire spi_busy;
wire spi_clk;
wire spi_cs;
wire spi_mosi;
reg [0:5] spi_address = 0;
// instanciate SPI acc sensor
SPI spi_sensor (
.clk(clk),
.spi_miso(spi_miso),
.en(spi_enable),
.rw(spi_rw),
.data(spi_data),
.address(spi_address),
.busy(spi_busy),
.spi_clk(spi_clk),
.spi_cs(spi_cs),
.spi_mosi(spi_mosi)
);
// LOGIC -----------------------------------------------------------
reg [20:0] wait_cnt = 0; //wait short time
parameter STATE_IDLE = 0;
parameter STATE_START_READ_SPI = 1;
parameter STATE_WAIT_READ_SPI = 2;
parameter STATE_START_SEND_UART = 3;
parameter STATE_WAIT_SEND_UART = 4;
reg [7:0] state = STATE_IDLE;
always @(posedge clk) begin
case (state)
STATE_IDLE: begin
wait_cnt <= wait_cnt + 1;
if (wait_cnt == 0) begin
state <= STATE_START_READ_SPI;
end
end
STATE_START_READ_SPI: begin
if (spi_busy == 0 && spi_enable == 0) begin
spi_rw <= 1;
set_spi_data <= 0;
spi_address <= SENSOR_ADDRESS_ID;
spi_enable <= 1;
end else if (spi_busy == 1 && spi_enable == 1) begin
spi_enable <= 0;
state <= STATE_WAIT_READ_SPI;
end
end
STATE_WAIT_READ_SPI: begin
if (spi_busy == 0) begin
uart_send_data <= spi_data;
state <= STATE_START_SEND_UART;
end
end
STATE_START_SEND_UART: begin
if (uart_busy == 0 && uart_send_enable == 0) begin
uart_send_enable <= 1;
end else if (uart_busy == 1 && uart_send_enable == 1) begin
uart_send_enable <= 0;
state <= STATE_WAIT_SEND_UART;
end
end
STATE_WAIT_SEND_UART: begin
if (uart_busy == 0) begin
state <= STATE_IDLE;
end
end
default: begin
end
endcase
end
endmodule
| 8.022287 |
module top_read_write_ts #(
parameter PLATFORM = "MODELSIM"
) (
input clk,
input rst_n,
input [31:0] local_clock,
input [3:0] host_r8_id,
input [3:0] host_wr8_id,
input [7:0] RXD_08,
input RXDV_08,
output wire [7:0] TXD_08,
output wire TX_EN_08
);
//wire [7:0] r2b00,r2b01,r2b02,r2b03;
// wire temp00,temp01,temp02,temp03;
//***************************************************
// Module Instance
//***************************************************
read_file_ts read_file_inst08 (
.clk(clk),
.rst_n(rst_n),
.host_r_id(host_r8_id),
.local_clock(local_clock),
.TXD(TXD_08),
.TX_EN(TX_EN_08)
);
////////////////////////////
write_file_ts write_file_inst08 (
.clk(clk),
.rst_n(rst_n),
.host_wr_id(host_wr8_id),
.local_clock(local_clock),
.RXD(RXD_08),
.RXDV(RXDV_08)
);
endmodule
| 6.806056 |
module top_receptor (
input iClk,
input iReset,
input iDatos,
output oDatos,
output [3:0] Anode,
output [6:0] ovDisplay
);
wire [7:0] wv_ASCII0;
wire [7:0] wv_ASCII1;
wire [7:0] wv_ASCII2;
wire [7:0] wv_ASCII3;
wire [6:0] wvDisplay0;
wire [6:0] wvDisplay1;
wire [6:0] wvDisplay2;
wire [6:0] wvDisplay3;
wire wClkmod;
wire [3:0] wvAnode;
wire wReset;
wire wDato;
wire wClkmod_UART;
assign Anode = wvAnode;
m_divisor_frecuencia_anode #(23'd5000000) divider_UART (
.iCE(1'b1),
.iClk(iClk),
.iReset(1'b0),
.oClkmod(wClkmod_UART)
);
debouncer instance_debouncer (
.iCE(1'b1),
.iClk(iClk),
.iReset(1'b0),
.iboton(iReset),
.oboton(wReset)
);
synch instance_synch (
.iCE(1'b1),
.iReset(1'b0),
.iDato(iDatos),
.iClk(iClk),
.oDato(wDato)
);
receptor instance_UART_rec (
.iDatos(wDato),
.iClk(iClk),
.iCE(wClkmod_UART),
.iReset(wReset),
.ovCarga0(wv_ASCII0),
.ovCarga1(wv_ASCII1),
.ovCarga2(wv_ASCII2),
.ovCarga3(wv_ASCII3)
);
ASCII instance_ASCII_0 (
.ivData(wv_ASCII0),
.iCE(1'b1),
.iClk(iClk),
.iReset(wReset),
.ovDisplay(wvDisplay0)
);
ASCII instance_ASCII_1 (
.ivData(wv_ASCII1),
.iCE(1'b1),
.iClk(iClk),
.iReset(wReset),
.ovDisplay(wvDisplay1)
);
ASCII instance_ASCII_2 (
.ivData(wv_ASCII2),
.iCE(1'b1),
.iClk(iClk),
.iReset(wReset),
.ovDisplay(wvDisplay2)
);
ASCII instance_ASCII_3 (
.ivData(wv_ASCII3),
.iCE(1'b1),
.iClk(iClk),
.iReset(wReset),
.ovDisplay(wvDisplay3)
);
Selecto_Display instance_Mux (
.ivAnode(wvAnode),
.iClk(iClk),
.iCE(1'b1),
.iReset(wReset),
.ivDisplay0(wvDisplay0),
.ivDisplay1(wvDisplay1),
.ivDisplay2(wvDisplay2),
.ivDisplay3(wvDisplay3),
.ovDisplay(ovDisplay)
);
mAnode instance_Anode (
.iClk(iClk),
.iReset(wReset),
.iCE(wClkmod),
.ovAnode(wvAnode)
);
m_divisor_frecuencia_anode divider (
.iCE(1'b1),
.iClk(iClk),
.iReset(wReset),
.oClkmod(wClkmod)
);
emisor instance_emisor (
.iClk(iClk),
.iCE(wClkmod_UART),
.iReset(wReset),
.ivCarga0(8'd72),
.ivCarga1(8'd79),
.ivCarga2(8'd76),
.ivCarga3(8'd65),
.oDato(oDatos)
);
endmodule
| 7.481353 |
module top (
x,
clk,
rst,
a
);
output x;
reg x;
input clk;
input [2:0] rst;
input [1:0] a;
wire rst_or;
assign rst_or = |rst;
always @(posedge clk, negedge rst_or) begin : DESIGN_PROCESSOR
reg i;
if (!rst_or) begin
i = 0;
x = 0;
end else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
| 6.963493 |
module top (
input clk,
input rst,
input [31:0] in_count,
input in_valid,
output in_ready,
input out_ready,
output out_valid
);
reg [31:0] r_remaining_count;
reg r_valid;
reg r_ready;
assign out_valid = r_valid;
assign in_ready = r_ready;
always @(posedge clk) begin
if (rst) begin
r_remaining_count <= 0;
r_valid <= 0;
r_ready <= 0;
end else begin
if (r_remaining_count == 0) begin
if (r_ready && in_valid) begin
r_remaining_count <= in_count;
r_valid <= in_count != 0;
r_ready <= 0;
end else begin
r_ready <= 1;
r_valid <= 0;
end
end else begin
r_valid <= !(r_remaining_count == 1 && out_ready && out_valid);
r_ready <= 0;
if (out_valid && out_ready) begin
r_remaining_count <= r_remaining_count - 1;
end
end
end
end
endmodule
| 7.233807 |
module dut (
input fast_clk,
slow_clk,
input [3:0] waddr,
raddr,
input [3:0] wdata,
input wen,
output [3:0] rdata
);
reg [3:0] mem[0:15];
reg [3:0] raddr_reg;
always @(posedge fast_clk) begin
if (wen) mem[waddr] <= wdata;
end
always @(posedge slow_clk) raddr_reg <= raddr;
assign rdata = mem[raddr_reg];
endmodule
| 7.120761 |
module top_control (
input clk,
reset_ctrl,
output reg carry_ctrl
);
// There is still a problem to deal with that is the gap between Stage 2 and Stage 3.
// The stage 2 requires the output_range everytime in order to execute some equations.
// However, right the output_range (output_range[v[i-1]]) will only be ready in the end of the 3rd stage.
// Hence, it creates a gap of one cycle.
// As a temporary solution, I put a permanent gap in the whole pipeline, which means that every 2 cycles I'll get an output ready.
// Hence, because of this restriction, I also need to throw data into the architecture in the same rate (1 data each 2 cycles).
localparam start_1 = 0, start_2 = 1, start_3 = 2;
localparam main = 3;
reg [2:0] state;
always @(posedge clk) begin
if (reset_ctrl) state <= start_1;
else begin
case (state)
start_1: state <= start_2;
start_2: state <= start_3;
start_3: state <= main;
main: state <= main;
endcase
end
end
always @(*) begin
case (state)
start_1: begin
carry_ctrl <= 1'b0;
end
start_2: begin
carry_ctrl <= 1'b0;
end
start_3: begin
carry_ctrl <= 1'b0;
end
main: begin
carry_ctrl <= 1'b1;
end
endcase
end
endmodule
| 7.478001 |
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'REG_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/REG_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/REG_V/sim_REG_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module top_reloj_digital (
input clk,
input reset,
input wire [3:0] sw_Nexys, //Modo configuracin (x3), formato_hora
input wire [4:0]btn_Nexys,//Botones de desplazamiento en la configuracin (x4), desactivar alarma timer
inout [7:0] dato_RTC,
output a_d,
output cs,
output rd,
output wr,
output wire hsync,
vsync,
output wire [11:0] RGB,
output wire clk_ext
);
assign clk_ext = clk;
//Conexiones entre mdulos
//FSM antirrebote
wire [3:0] sw_db; //Modo configuracin (x3), formato_hora
wire [4:0] btn_db; //Botones de desplazamiento en la configuracin (x4), desactivar alarma timer
//Control RTC a VGA
wire [7:0] out_seg_hora, out_min_hora, out_hora_hora;
wire [7:0] out_dia_fecha, out_mes_fecha, out_jahr_fecha, out_dia_semana;
wire [7:0] out_seg_timer, out_min_timer, out_hora_timer;
wire estado_alarma;
wire [1:0] cursor_location;
wire AM_PM;
//FSM's antirrebote
debouncing Instancia_debouncing (
.clk(clk),
.reset(reset),
.sw(sw_Nexys), //4 interruptores
.btn(btn_Nexys), //5 botones
.sw_db(sw_db), //debounce
.btn_db(btn_db) //debounce
);
//Control RTC
Contol_RTC Instancia_Control_RTC (
.clk(clk),
.reset(reset),
.sw0(sw_db[0]),
.sw1(sw_db[1]),
.sw2(sw_db[2]),
.enUP(btn_db[0]),
.enDOWN(btn_db[1]),
.enRIGHT(btn_db[3]),
.enLEFT(btn_db[2]),
.desactivar_alarma(btn_db[4]),
.formato_hora(sw_db[3]),
.dato(dato_RTC),
.a_d(a_d),
.cs (cs),
.rd (rd),
.wr (wr),
.out_seg_hora (out_seg_hora),
.out_min_hora (out_min_hora),
.out_hora_hora (out_hora_hora),
.out_dia_fecha (out_dia_fecha),
.out_mes_fecha (out_mes_fecha),
.out_jahr_fecha(out_jahr_fecha),
.out_dia_semana(out_dia_semana),
.out_seg_timer (out_seg_timer),
.out_min_timer (out_min_timer),
.out_hora_timer(out_hora_timer),
.estado_alarma(estado_alarma),
.cursor_location(cursor_location),
.AM_PM(AM_PM)
);
//Control VGA
Clock_screen_top Instancia_Clock_screen_top (
.clock(clk),
.reset(reset),
.digit0_HH(out_hora_hora[3:0]),
.digit1_HH(out_hora_hora[7:4]),
.digit0_MM(out_min_hora[3:0]),
.digit1_MM(out_min_hora[7:4]),
.digit0_SS(out_seg_hora[3:0]),
.digit1_SS(out_seg_hora[7:4]), //
.digit0_DAY(out_dia_fecha[3:0]),
.digit1_DAY(out_dia_fecha[7:4]),
.digit0_MES(out_mes_fecha[3:0]),
.digit1_MES(out_mes_fecha[7:4]),
.digit0_YEAR(out_jahr_fecha[3:0]),
.digit1_YEAR(out_jahr_fecha[7:4]), //
.digit0_HH_T(out_hora_timer[3:0]),
.digit1_HH_T(out_hora_timer[7:4]),
.digit0_MM_T(out_min_timer[3:0]),
.digit1_MM_T(out_min_timer[7:4]),
.digit0_SS_T(out_seg_timer[3:0]),
.digit1_SS_T(out_seg_timer[7:4]),//Decenas y unidades para los nmeros en pantalla (18 inputs de 3 bits)
.AM_PM(AM_PM), //Entrada para conocer si en la informacin de hora se despliega AM o PM
.dia_semana(out_dia_semana),//Para interpretar el dia de la semana a escribir (3-bits: 7 das)
.config_mode({sw_db[2], sw_db[1], sw_db[0]}), //Cuatro estados del modo configuracin
.cursor_location(cursor_location), //Marca la posicin del cursor en modo configuracin
.formato_hora(sw_db[3]),//Seal que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
.estado_alarma(estado_alarma),
.hsync(hsync),
.vsync(vsync),
.RGB (RGB)
//output wire pixel_tick
);
endmodule
| 8.099832 |
module top #(
parameter N = 8
) (
input wire clk,
reset,
input wire s_in,
output wire s_out
);
reg [N-1:0] r_reg;
wire [N-1:0] r_next;
always @(posedge clk, negedge reset) begin
if (~reset) r_reg <= 0;
else r_reg <= r_next;
end
assign r_next = {s_in, r_reg[N-1:1]};
assign s_out = r_reg[0];
endmodule
| 7.964012 |
module Top_RISC (
input clk,
input rst,
input [31:0] InsR
);
wire mem_wr_valid;
wire [ 2:0] mem_func3;
wire mem_rd;
wire data_ready;
wire [31:0] to_data_mem;
wire [31:0] data_mem_addr;
wire [31:0] from_data_mem;
core coreRISCV (
.from_ins_mem(InsR),
.from_data_mem(from_data_mem),
.to_data_mem_reg(to_data_mem),
// .data_valid(data_valid),
.data_ready(data_ready),
.ins_mem_addr(ins_mem_addr),
.data_mem_addr_reg(data_mem_addr),
.clk(clk),
.reset(rst),
.mem_rd_reg(mem_rd),
.mem_wr_valid_reg(mem_wr_valid),
.mem_func3_reg(mem_func3)
);
OnChipMemory Memory (
.clock(clk),
.reset(rst),
.io_port_0_req_ready(),
.io_port_0_req_valid(),
.io_port_0_req_bits_addr(),
.io_port_0_req_bits_data(),
.io_port_0_req_bits_fcn(),
.io_port_0_req_bits_typ(),
.io_port_0_resp_valid(),
.io_port_0_resp_bits_data(),
.io_port_1_req_ready(),
.io_port_1_req_valid(mem_wr_valid),
.io_port_1_req_bits_addr(data_mem_addr),
.io_port_1_req_bits_data(to_data_mem),
.io_port_1_req_bits_fcn(!mem_rd),
.io_port_1_req_bits_typ(mem_func3),
.io_port_1_resp_valid(data_ready),
.io_port_1_resp_bits_data(from_data_mem)
);
endmodule
| 6.851285 |
module top_riscv_wrapper_tb ();
reg clk, rst;
reg [15:0] sw;
wire [15:0] led;
wire [ 6:0] seg;
wire [ 3:0] an;
top_riscv_wrapper DUT (
.clk (clk),
.btnU(rst),
.sw (sw),
.led (led),
.seg (seg),
.an (an)
);
parameter clock_period = 15;
always #(clock_period / 2) clk = ~clk;
initial begin : GENERIC_TESTS
clk = 0;
rst = 1;
sw = 16'h070a;
#(clock_period * 10);
rst = 0;
#(clock_period * 200);
$finish;
end
endmodule
| 8.514135 |
module top_riscv_wrapper_int_tb ();
reg clk, rst;
reg [15:0] sw;
wire [15:0] led;
wire [ 6:0] seg;
wire [ 3:0] an;
top_riscv_wrapper DUT (
.clk (clk),
.btnU(rst),
.sw (sw),
.led (led),
.seg (seg),
.an (an)
);
reg rst_f;
reg [15:0] sw_f, led_f;
reg [3:0] an_f;
integer file_test_cases;
integer cycles;
parameter clock_period = 15;
always #(clock_period / 2) clk = ~clk;
initial begin : INTEGRATION_TESTS
//file_test_cases = $fopen("integration_testcases.csv","r");
//file_test_cases = $fopen("integration_testcases2.csv","r");
//file_test_cases = $fopen("binary_search_1.csv","r");
//file_test_cases = $fopen("cubes_positive.csv","r");
file_test_cases = $fopen("sum_cubes.csv", "r");
//file_test_cases = $fopen("rc5.csv","r");
//file_test_cases = $fopen("rc5_complex.csv","r");
if (file_test_cases == 0) begin
$display("Could not open test cases file.");
$stop;
end
$display("Opened test cases file.");
clk = 0;
rst = 1;
#(clock_period * 10);
led_f = 16'h0000;
an_f = 4'h0;
while (!$feof(
file_test_cases
)) begin
// MEM related signals
if (led !== led_f) begin
$display("LED output %h does not match expected value %h at %0t ps.", led, led_f, $time);
$stop;
end
// HALT related signals
if ((seg !== 7'h00) || (an !== an_f)) begin
$display("HALT output %h does not match expected value %h at %0t ps.", an, an_f, $time);
$stop;
end
$fscanf(file_test_cases, "%b,%h,%h,%h,%d", rst_f, sw_f, led_f, an_f, cycles);
rst = rst_f;
sw = sw_f;
#(clock_period * cycles);
end
$fclose(file_test_cases);
$display("All testcases passed!");
$finish;
end
endmodule
| 8.514135 |
module top_risc_proc (
input clk,
reset
);
wire w_memWrite, w_memRead, w_PCop, w_checkbranch;
wire [12:0] w_instruction, w_ALUresult, w_dataA, w_dataB, w_PCcurr, w_PC;
wire [8:0] w_branch;
wire [3:0] w_opcode;
wire [2:0] w_regDest, w_regAddress1, w_regAddress2;
PC u0 (
.clk(clk),
.reset(reset),
.i_PCop(w_PCop),
.i_PC(w_PC),
.i_Branch(w_branch),
.o_PCcurr(w_PCcurr)
);
instruction_memory u1 (
.reset(reset),
.i_PCcurr(w_PCcurr),
.o_instruction(w_instruction)
);
ALU u2 (
.i_opcode(w_opcode),
.i_dataA(w_dataA),
.i_dataB(w_dataB),
.o_result(w_ALUresult),
.o_checkbranch(w_checkbranch)
);
register_file u3 (
.clk(clk),
.reset(reset),
.i_memWrite(w_memWrite),
.i_memRead(w_memRead),
.i_address1(w_regAddress1),
.i_address2(w_regAddress2),
.i_destReg(w_regDest),
.i_ALUresult(w_ALUresult),
.o_dataA(w_dataA),
.o_dataB(w_dataB)
);
control u4 (
.clk(clk),
.reset(reset),
.i_checkbranch(w_checkbranch),
.i_instruction(w_instruction),
.o_opcode(w_opcode),
.o_destination(w_regDest),
.o_addr1(w_regAddress1),
.o_addr2(w_regAddress2),
.o_branch(w_branch),
.o_PC(w_PC),
.o_memWrite(w_memWrite),
.o_memRead(w_memRead),
.o_PCop(w_PCop)
);
endmodule
| 7.070053 |
module is top row reg array buffer for
* storing top row data of input feature map.
--------------------------------------------------*/
module top_row_reg_array
endmodule
| 6.693672 |
module top_rs232 (
input CLOCK_50,
input UART_RXD,
input [1:0] KEY,
input [7:0] SW,
output [7:0] LEDR,
output UART_TXD
);
wire RE, WE, KEY_1_DB, KEY_0_DB;
controller controller (
.clk(CLOCK_50),
.UART_RXD(UART_RXD),
.UART_TXD(UART_TXD),
.RE(RE),
.WE(WE),
.send_data(SW),
.receive_data(LEDR)
);
debouncer #(
.SIZE(2)
) re_debouncer (
.in ({~KEY[1], ~KEY[0]}),
.out({KEY_1_DB, KEY_0_DB}),
.clk(CLOCK_50)
);
edge_detector #(
.SIZE(2)
) re_edge (
.in ({KEY_1_DB, KEY_0_DB}),
.out({WE, RE}),
.clk(CLOCK_50)
);
endmodule
| 7.80151 |
module top_rs_hip (
// inputs:
dlup_exit,
hotrst_exit,
l2_exit,
ltssm,
npor,
pld_clk,
test_sim,
// outputs:
app_rstn,
crst,
srst
);
output app_rstn;
output crst;
output srst;
input dlup_exit;
input hotrst_exit;
input l2_exit;
input [4:0] ltssm;
input npor;
input pld_clk;
input test_sim;
reg any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg app_rstn;
reg app_rstn0;
reg crst;
reg crst0;
reg [4:0] dl_ltssm_r;
reg dlup_exit_r;
reg exits_r;
reg hotrst_exit_r;
reg l2_exit_r;
wire otb0;
wire otb1;
reg [10:0] rsnt_cntn;
reg srst;
reg srst0;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
//pipe line exit conditions
always @(posedge pld_clk or negedge any_rstn_rr) begin
if (any_rstn_rr == 0) begin
dlup_exit_r <= otb1;
hotrst_exit_r <= otb1;
l2_exit_r <= otb1;
exits_r <= otb0;
end else begin
dlup_exit_r <= dlup_exit;
hotrst_exit_r <= hotrst_exit;
l2_exit_r <= l2_exit;
exits_r <= (l2_exit_r == 1'b0) | (hotrst_exit_r == 1'b0) | (dlup_exit_r == 1'b0) | (dl_ltssm_r == 5'h10);
end
end
//LTSSM pipeline
always @(posedge pld_clk or negedge any_rstn_rr) begin
if (any_rstn_rr == 0) dl_ltssm_r <= 0;
else dl_ltssm_r <= ltssm;
end
//reset Synchronizer
always @(posedge pld_clk or negedge npor) begin
if (npor == 0) begin
any_rstn_r <= 0;
any_rstn_rr <= 0;
end else begin
any_rstn_r <= 1;
any_rstn_rr <= any_rstn_r;
end
end
//reset counter
always @(posedge pld_clk or negedge any_rstn_rr) begin
if (any_rstn_rr == 0) rsnt_cntn <= 0;
else if (exits_r == 1'b1) rsnt_cntn <= 11'h3f0;
else if (rsnt_cntn != 11'd1024) rsnt_cntn <= rsnt_cntn + 1;
end
//sync and config reset
always @(posedge pld_clk or negedge any_rstn_rr) begin
if (any_rstn_rr == 0) begin
app_rstn0 <= 0;
srst0 <= 1;
crst0 <= 1;
end else if (exits_r == 1'b1) begin
srst0 <= 1;
crst0 <= 1;
app_rstn0 <= 0;
end else // synthesis translate_off
if ((test_sim == 1'b1) & (rsnt_cntn >= 11'd32)) begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end else // synthesis translate_on
if (rsnt_cntn == 11'd1024) begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
end
//sync and config reset pipeline
always @(posedge pld_clk or negedge any_rstn_rr) begin
if (any_rstn_rr == 0) begin
app_rstn <= 0;
srst <= 1;
crst <= 1;
end else begin
app_rstn <= app_rstn0;
srst <= srst0;
crst <= crst0;
end
end
endmodule
| 7.303665 |
module top_R_cpu (
input rst,
input clk,
output ZF,
output OF,
output [31:0] F
);
reg write_reg;
wire [31:0] Inst_code;
wire [31:0] R_Data_A;
wire [31:0] R_Data_B;
reg [2:0] ALU_OP;
pc pc_connect (
clk,
rst,
Inst_code
);
Register_file R_connect (
Inst_code[25:21],
Inst_code[20:16],
Inst_code[15:11],
write_reg,
F,
~clk,
rst,
R_Data_A,
R_Data_B
);
ALU ALU_connect (
R_Data_A,
R_Data_B,
F,
ALU_OP,
ZF,
OF
);
always @(*) begin
write_reg = 0;
ALU_OP = 0;
if (Inst_code[31:26] == 0) begin
case (Inst_code[5:0])
6'b100000: ALU_OP = 3'b100;
6'b100010: ALU_OP = 3'b101;
6'b100100: ALU_OP = 3'b000;
6'b100101: ALU_OP = 3'b001;
6'b100110: ALU_OP = 3'b010;
6'b100111: ALU_OP = 3'b011;
6'b101011: ALU_OP = 3'b110;
6'b000100: ALU_OP = 3'b111;
endcase
write_reg = 1;
end
end
endmodule
| 6.701564 |
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