code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module
// One of these modules is created for each testcase that involves
// co-simulation. This one is for the 'UNROLL_FILL_V' testcase.
// The top-level module contains:
// - An instances of a co-simulation wrapper module for each instance
// simulating in Verilog.
// - Hub initialization calls that load the shared library for the
// simulation.
//
// You can add any other legal Verilog to this template file, and it appear in
// the verilog module.
`timescale 1 ps / 1 ps
module top;
// RTL wrapper instances for cosim.
dut_cosim dut0();
integer n_cur_time;
initial n_cur_time=0;
reg [63:0] cur_time;
initial cur_time=0;
`include "hub.v"
// Load library and begin co-simulation.
initial begin
// For gate-level simulations we back-annotate the instances with delays
// from the SDF file
// Open the trace file if that's appropriate.
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) )
$dumpfile( "bdw_work/sims/UNROLL_FILL_V/verilog.vcd" );
if ( hubCurrentProjectDoesTrace( hub_trace_vcd ) ) begin
$dumpvars( 0, dut0.clk );
$dumpvars( 0, dut0.rst );
$dumpvars( 0, dut0.din_busy );
$dumpvars( 0, dut0.din_vld );
$dumpvars( 0, dut0.din_data );
$dumpvars( 0, dut0.dout_busy );
$dumpvars( 0, dut0.dout_vld );
$dumpvars( 0, dut0.dout_data );
$dumpvars( 4, dut0.dut0 );
end
// If the SystemC shared library will be loaded using +qbSetOption+libdef=libname.so
// from the Verilog simulator's command line, the following line can be left
// out. In order to load the shared library directly from Verilog, uncomment
// the following line using either ther automatically generated SIM_EXEC string,
// or a hard-coded string giving the path to the shared library.
//hubLoadLibrary( "bdw_work/sims/UNROLL_FILL_V/sim_UNROLL_FILL_V.so", "" );
// Begin a co-simulation.
// This task returns after esc_end_cosim() is called from SystemC.
hubStartCosim;
#100 $stop;
end
endmodule
| 7.358787 |
module top_up5k (
clk_in,
reset_n_in,
// Global data
sck0_in,
sdi0_in,
cs0_n_in,
// Daisy data
sck1_in,
sdi1_in,
sdo1_out,
cs1_n_in,
// Success flags
ready_n_od_out,
// Indicators
status_led_n_out
);
`define SHAPOOL_NO_NONCE_OFFSET // Required for POOL_SIZE = 1
parameter POOL_SIZE = 1;
parameter POOL_SIZE_LOG2 = 0;
parameter BASE_DIFFICULTY = 64;
// 12 MHz ~ 56.25 MHz
parameter PLL_DIVR = 4'b0000;
parameter PLL_DIVF = 7'b1001010;
parameter PLL_DIVQ = 3'b100;
// Inputs and Outputs
input wire clk_in;
input wire reset_n_in;
input wire sck0_in;
input wire sdi0_in;
input wire cs0_n_in;
input wire sck1_in;
input wire sdi1_in;
output wire sdo1_out;
input wire cs1_n_in;
output wire ready_n_od_out;
output wire status_led_n_out;
top #(
.POOL_SIZE(POOL_SIZE),
.POOL_SIZE_LOG2(POOL_SIZE_LOG2),
.BASE_DIFFICULTY(BASE_DIFFICULTY),
.PLL_DIVR(PLL_DIVR),
.PLL_DIVF(PLL_DIVF),
.PLL_DIVQ(PLL_DIVQ)
) u (
clk_in,
reset_n_in,
// Global data
sck0_in,
sdi0_in,
cs0_n_in,
// Daisy data
sck1_in,
sdi1_in,
sdo1_out,
cs1_n_in,
// Success flags
ready_n_od_out,
// Indicators
status_led_n_out
);
endmodule
| 7.181474 |
module top_upduino2 (
output [2:0] led_n
);
`include "macros/direction.vh"
wire clk;
reg [2:0] int_rst_cnt = 0;
always @(posedge clk) begin
if (int_rst_cnt != 3'b111) int_rst_cnt <= int_rst_cnt + 1;
end
wire int_rst_n = int_rst_cnt == 3'b111;
wire rst_n = int_rst_n;
reg [2:0] led;
wire i_req;
wire [15:0] i_addr;
wire i_ack;
wire [7:0] i_rdata;
wire d_req;
wire d_dir;
wire [7:0] d_addr;
wire [7:0] d_wdata;
wire d_ack;
wire [7:0] d_rdata;
wire io_req;
wire io_dir;
wire [7:0] io_wdata;
reg io_ack;
reg [7:0] io_rdata;
SB_HFOSC #(
.CLKHF_DIV("0b10")
) hfosc (
.CLKHFEN(1),
.CLKHFPU(1),
.CLKHF (clk)
);
bfcpu cpu (
.clk (clk),
.rst_n(rst_n),
.i_req (i_req),
.i_addr (i_addr),
.i_ack (i_ack),
.i_rdata(i_rdata),
.d_req (d_req),
.d_dir (d_dir),
.d_addr (d_addr),
.d_wdata(d_wdata),
.d_ack (d_ack),
.d_rdata(d_rdata),
.io_req (io_req),
.io_dir (io_dir),
.io_wdata(io_wdata),
.io_ack (io_ack),
.io_rdata(io_rdata)
);
i_mem_upduino2 im (
.clk(clk),
.i_req (i_req),
.i_addr (i_addr),
.i_ack (i_ack),
.i_rdata(i_rdata)
);
d_mem_upduino2 dm (
.clk(clk),
.d_req (d_req),
.d_dir (d_dir),
.d_addr (d_addr),
.d_wdata(d_wdata),
.d_ack (d_ack),
.d_rdata(d_rdata)
);
always @(posedge clk) begin
if (!rst_n) begin
led <= 3'b000;
io_ack <= 0;
end else begin
if (io_req) begin
io_ack <= 1;
if (io_dir == `DIRECTION_WRITE) led <= io_wdata[2:0];
else io_rdata <= {5'b0, led};
end else begin
io_ack <= 0;
end
end
end
SB_RGBA_DRV #(
.RGB0_CURRENT("0b000001"),
.RGB1_CURRENT("0b000001"),
.RGB2_CURRENT("0b000001")
) rgb_driver (
.RGBLEDEN(1),
.CURREN(1),
.RGB0PWM(led[0]),
.RGB1PWM(led[1]),
.RGB2PWM(led[2]),
.RGB0(led_n[0]),
.RGB1(led_n[1]),
.RGB2(led_n[2])
);
endmodule
| 6.619851 |
module TOP_URISC (
input clk_PH1,
// input clk_PH2,
input rst_n,
input Run
);
wire CSMR_CS, WRITE, RDMR_READ;
wire [7:0] ADDRESS;
wire [7:0] WDATA;
wire [7:0] RDATA;
URISC ursic (
.clk_PH1(clk_PH1),
.clk_PH2(~clk_PH2),
.rst_n(rst_n),
.RUN(Run),
.CSMR(CSMR_CS),
.WRITE(WRITE),
.RDMR(RDMR_READ),
.ADDRESS(ADDRESS),
.DATA_IN(RDATA),
.DATA_OUT(WDATA)
);
RAM ut_ram (
.clk(clk_PH1),
.rst_n(rst_n),
.CS(CSMR_CS),
.WRITE(WRITE),
.READ(RDMR_READ),
.ADDRESS(ADDRESS),
.WDATA(WDATA),
.RDATA(RDATA)
);
endmodule
| 6.592699 |
module top_vending (
(*chip_pin = "U15"*) input dollar,
(*chip_pin = "V15"*) input quarter,
(*chip_pin = "U14"*) input dime,
(*chip_pin = "V14"*) input nickel,
(*chip_pin = "U4"*) output reg d_cookies,
(*chip_pin = "V4"*) output reg d_candy,
(*chip_pin = "U5"*) output reg d_chips,
(*chip_pin = "V5"*) output reg d_gum,
(*chip_pin = "V13"*) output c_quarter,
(*chip_pin = "U12"*) output c_dime,
(*chip_pin = "V12"*) output c_nickel,
/*
(*chip_pin = "K18"*)output c_quarter,
(*chip_pin = "M18"*)output c_dime,
(*chip_pin = "H18"*)output c_nickel,
*/
(*chip_pin = "B14,B13,B12,B11,A10,B9,B8"*) output [6:0] seg_out,
(*chip_pin = "B7,A5,A4"*) output [2:0] comm_out,
//(*chip_pin = "E17"*)output MOSI,
//(*chip_pin = "G17"*)input MISO,
//(*chip_pin = "D17"*)output SS,
//(*chip_pin = "H18"*)output SCLK,
//(*chip_pin = "U4,V4,U5,V5,V12,U12,V13,U13"*)output [7:0] led,
//(*chip_pin = "M18"*)inout VCC,
//(*chip_pin = "K18"*)inout GND,
(*chip_pin = "J6"*) input clkin,
(*chip_pin="D4,C2,D1,B4"*) input [4:1] keyrow,
(*chip_pin="J3,G4,F4,E4"*) output [3:0] keycolumn
);
wire [7:0] coins_w;
wire [5:0] key_w;
wire keypress_w;
wire gum_w;
wire candy_w;
wire chips_w;
wire cookies_w;
wire scan_clk;
wire c_quarter_w;
wire c_dime_w;
wire c_nickel_w;
wire d_cookies_w;
wire d_candy_w;
wire d_gum_w;
wire d_chips_w;
wire dollar_w;
wire quarter_w;
wire dime_w;
wire nickel_w;
wire change_w;
wire clr_pro;
wire [3:0] dig1_w;
wire [3:0] dig2_w;
wire [3:0] dig3_w;
wire clk_vend;
//assign {d_gum,d_candy,d_cookies,d_chips} = ~{gum_w,candy_w,cookies_w,chips_w};
assign {c_quarter, c_dime, c_nickel} = ~{c_quarter_w, c_dime_w, c_nickel_w};
assign {dollar_w, quarter_w, dime_w, nickel_w} = ~{dollar, quarter, dime, nickel};
//wire [7:0] led_w;
//assign led = ~led_w;
always @(negedge keypress_w or posedge clr_pro) begin
if (clr_pro) {d_gum, d_candy, d_cookies, d_chips} = 4'b1111;
else {d_gum, d_candy, d_cookies, d_chips} = ~{gum_w, candy_w, cookies_w, chips_w};
end
vending_machine V1 (
.cookies(cookies_w),
.candy(candy_w),
.chips(chips_w),
.gum(gum_w),
.clk(scan_clk),
.rst(change_w),
.dollar(dollar_w),
.quarter(quarter_w),
.dime(dime_w),
.nickel(nickel_w),
.c_quarter(c_quarter_w),
.c_dime(c_dime_w),
.c_nickel(c_nickel_w),
.done(clr_pro),
.coins(coins_w)
);
MUX_DISP disp (
.A(dig3_w),
.B(dig2_w),
.C(dig1_w),
.clk(scan_clk),
.com_1(comm_out[0]),
.com_2(comm_out[1]),
.com_3(comm_out[2]),
.seg_A(seg_out[0]),
.seg_B(seg_out[1]),
.seg_C(seg_out[2]),
.seg_D(seg_out[3]),
.seg_E(seg_out[4]),
.seg_F(seg_out[5]),
.seg_G(seg_out[6])
);
BCD_decoder3dig dec (
.in (coins_w),
.dig1(dig1_w),
.dig2(dig2_w),
.dig3(dig3_w)
);
keypad keypad (
.clk(scan_clk),
.keyrow(keyrow),
.keycolumn(keycolumn),
.Dout(key_w),
.Data_ena(keypress_w)
);
key_sequence U3 (
.key(key_w),
.keypress(keypress_w),
.clr(clr_pro),
.gum(gum_w),
.candy(candy_w),
.cookies(cookies_w),
.chips(chips_w),
.reset_out(change_w)
);
Clock_Divider clkdiv (
.CLK_in (clkin),
.Scan_clk(scan_clk),
.pwm_clk (),
.Baud_clk(clk_vend)
);
endmodule
| 7.393468 |
module top_vending_test;
reg clk;
reg rst;
reg dollar;
reg quarter;
reg dime;
reg nickel;
wire cooikes;
wire candy;
wire chips;
wire gum;
wire c_dime;
wire c_nickel;
wire c_quarter;
reg [4:1] keyrow;
wire [3:0] keycolumn;
top_vending DUT (
.clk(clk),
.rst(rst),
.dollar(dollar),
.quarter(quarter),
.dime(dime),
.d_cookies(cookies),
.d_candy(candy),
.d_gum(gum),
.d_chips(chips),
.c_quarter(c_quarter),
.c_dime(c_dime),
.c_nickel(c_nickel),
.keyrow(keyrow),
.keycolumn(keycolumn)
);
initial begin
$stop;
end
endmodule
| 6.771291 |
module sram (
input cs,
input we,
input oe,
input [16:0] addr,
input [15:0] data_i,
output [15:0] data_o
);
reg [15:0] mem[0:131071];
// initial $readmemh("./finch.hex",mem);
assign data_o = (!cs && !oe) ? mem[addr] : 16'bz;
always_latch @(we, cs, addr, data_i) begin
if (!cs && !we) mem[addr] = data_i;
end
always @(we, oe) begin
if (!we && !oe) begin
$error("we and oe conflict!");
end
end
endmodule
| 7.547687 |
module top_vga (
clk,
reset,
red,
green,
blue,
vsync,
hsync
);
input clk, reset;
output vsync, hsync;
output reg [3:0] red, green, blue;
reg CLK_50;
wire Xdisplay, Ydisplay;
wire [9:0] haddr;
wire [8:0] vaddr;
horizontal HSYNC (
CLK_50,
reset,
haddr,
hsync,
Xdisplay
);
vertical VSYNC (
CLK_50,
reset,
vaddr,
vsync,
Ydisplay
);
/***********CLK DIVIDER**************************/
always @(posedge clk or posedge reset) begin
if (reset) begin
CLK_50 <= 0;
end else begin
CLK_50 <= ~CLK_50;
end
end
always @(posedge CLK_50) begin
if (Xdisplay && Ydisplay) begin
red <= 4'b0010;
green <= 4'b0111;
blue <= 4'b0001;
end else begin
red <= 0;
green <= 0;
blue <= 0;
end
end
endmodule
| 7.258908 |
module top_vga (
input clk,
input rst,
output hsync,
output vsync,
output [3:0] red,
output [3:0] green,
output [3:0] blue
);
wire clkd;
vga1280x1024 vga1280x1024 (
.dclk (clkd), //pixel clock: 108MHz
.clr (rst), //asynchronous reset
.hsync(hsync), //horizontal sync out
.vsync(vsync), //vertical sync out
.red (red), //red vga output
.green(green), //green vga output
.blue (blue) //blue vga output
);
clockdiv_wrapper clockdiv_wrapper (
.clk (clk),
.clkd(clkd)
);
endmodule
| 7.258908 |
module: top_view
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_view_test;
// Inputs
reg clk;
reg rst_n;
reg [11:0] ad1_in;
reg [11:0] ad2_in;
// Outputs
wire led0;
wire [13:0] da1data;
wire da1_clk;
wire da1_wrt;
wire [13:0] da2data;
wire da2_clk;
wire da2_wrt;
wire ad1_clk;
wire ad2_clk;
//wire [13:0] out_2ask;
//wire [13:0] out_cos_1M;
//wire [13:0] out_cos_500K;
// Instantiate the Unit Under Test (UUT)
top_view uut (
.clk(clk),
.rst_n(rst_n),
.led0(led0),
.da1data(da1data),
.da1_clk(da1_clk),
.da1_wrt(da1_wrt),
.da2data(da2data),
.da2_clk(da2_clk),
.da2_wrt(da2_wrt),
.ad1_in(ad1_in),
.ad1_clk(ad1_clk),
.ad2_in(ad2_in),
.ad2_clk(ad2_clk)
//.out_2ask(out_2ask),
//.out_cos_1M(out_cos_1M),
//.out_cos_500K(out_cos_500K)
);
initial begin
// Initialize Inputs
clk = 0;
rst_n = 0;
ad1_in = 0;
ad2_in = 0;
// Wait 100 ns for global reset to finish
// Wait 100 ns for global reset to finish
#100;
rst_n = 1; //൱ϵ縴λ
// Add stimulus here
end
always #10 clk=~clk;
endmodule
| 7.569143 |
module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Top_VTF;
// Inputs
reg Clk;
reg Rst;
reg Rx;
// Outputs
wire Tx;
// Instantiate the Unit Under Test (UUT)
Top uut (
.Clk(Clk),
.Rst(Rst),
.Rx(Rx),
.Tx(Tx)
);
always
begin
#10 Clk = ~Clk; #10 Clk = ~Clk;
end
initial begin
// Initialize Inputs
Clk = 0;
Rst = 0;
Rx = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
Rst = 1;
#30
Rst = 0;
end
endmodule
| 7.357405 |
module dff (
input [3:0] d,
input clk,
clr,
output reg [3:0] q
);
initial begin
q = 4'b0000;
end
always @(posedge clk)
if (clr) q <= 4'b0110;
else q <= d;
endmodule
| 7.174483 |
module adff (
input [3:0] d,
input clk,
clr,
output reg [3:0] q
);
initial begin
q = 4'b0000;
end
always @(posedge clk, posedge clr)
if (clr) q <= 4'b0110;
else q <= d;
endmodule
| 7.089232 |
module dffe (
input [3:0] d,
input clk,
en,
output reg [3:0] q
);
initial begin
q = 4'b0010;
end
always @(posedge clk) if (en) q <= d;
endmodule
| 7.085902 |
module dffse (
input [3:0] d,
input clk,
en,
pre,
output reg [3:0] q
);
initial begin
q = 1;
end
always @(posedge clk)
if (!pre) q <= 4'b0101;
else if (en) q <= d;
endmodule
| 7.440558 |
module tristate (
en,
i,
io,
o
);
input en;
input [3:0] i;
inout [3:0] io;
output [1:0] o;
wire [3:0] io;
assign io[1:0] = (en) ? i[1:0] : 1'bZ;
assign io[3:2] = (i[1:0]) ? en : 1'bZ;
assign o = io[2:1];
endmodule
| 6.741184 |
module top (
input en,
input [3:0] a,
inout [3:0] b,
output [1:0] c
);
tristate u_tri (
.en(en),
.i (a),
.io(b),
.o (c)
);
endmodule
| 7.233807 |
module one_round (
state_in,
key,
state_out
);
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (
s0,
p00,
p01,
p02,
p03
),
t1 (
s1,
p10,
p11,
p12,
p13
),
t2 (
s2,
p20,
p21,
p22,
p23
),
t3 (
s3,
p30,
p31,
p32,
p33
);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @(*) state_out <= {z0, z1, z2, z3};
endmodule
| 7.018166 |
module final_round (
state_in,
key_in,
state_out
);
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3, z0, z1, z2, z3, k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03, p10, p11, p12, p13, p20, p21, p22, p23, p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (
s0,
{p00, p01, p02, p03}
),
S4_2 (
s1,
{p10, p11, p12, p13}
),
S4_3 (
s2,
{p20, p21, p22, p23}
),
S4_4 (
s3,
{p30, p31, p32, p33}
);
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @(*) state_out <= {z0, z1, z2, z3};
endmodule
| 7.609225 |
module S4 (
in,
out
);
input [31:0] in;
output [31:0] out;
S
S_0 (
in[31:24],
out[31:24]
),
S_1 (
in[23:16],
out[23:16]
),
S_2 (
in[15:8],
out[15:8]
),
S_3 (
in[7:0],
out[7:0]
);
endmodule
| 6.508373 |
module T (
in,
out
);
input [7:0] in;
output [31:0] out;
S s0 (
in,
out[31:24]
);
assign out[23:16] = out[31:24];
xS s4 (
in,
out[7:0]
);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
| 6.784554 |
module top_wrapper (
`ifdef USE_POWER_PINS
vdd3v3,
vdd1v8,
vss,
`endif
clk,
rst,
wishbone_data_in,
wishbone_data_out,
start_operation,
wishbone_address_bus,
wbs_we_i,
rd_sync_fifo_output_buffer_ADC,
rd_sync_fifo_output_buffer_CSA,
V1_WL,
V2_WL,
V3_WL,
V4_WL,
V1_SL,
V2_SL,
V3_SL,
V4_SL,
V1_BL,
V2_BL,
V3_BL,
V4_BL,
V0_REF_ADC,
V1_REF_ADC,
V2_REF_ADC,
REF_CSA,
VDD_PRE,
CSA
);
`ifdef USE_POWER_PINS
inout vdd3v3;
inout vdd1v8;
inout vss;
`endif
input clk, rst, start_operation;
input [31:0] wishbone_data_in;
output [31:0] wishbone_data_out;
input [31:0] wishbone_address_bus;
input wbs_we_i;
wire ENABLE_WL;
wire ENABLE_SL;
wire ENABLE_BL;
wire COL_SELECT;
wire PRE;
wire [1:0] CLK_EN_ADC;
wire SAEN_CSA;
output wire [15:0] CSA;
wire [15:0] ADC_OUT0;
wire [15:0] ADC_OUT1;
wire [15:0] ADC_OUT2;
wire ENABLE_CSA;
wire [15:0] IN0_WL;
wire [15:0] IN1_WL;
wire [15:0] IN0_BL;
wire [15:0] IN1_BL;
wire [15:0] IN0_SL;
wire [15:0] IN1_SL;
input rd_sync_fifo_output_buffer_ADC;
input rd_sync_fifo_output_buffer_CSA;
inout VDD_PRE;
inout V1_WL;
inout V2_WL;
inout V3_WL;
inout V4_WL;
inout V1_SL;
inout V2_SL;
inout V3_SL;
inout V4_SL;
inout V1_BL;
inout V2_BL;
inout V3_BL;
inout V4_BL;
inout V0_REF_ADC;
inout V1_REF_ADC;
inout V2_REF_ADC;
inout REF_CSA;
RRAM_ANALOG U_RRAM_ANALOG (
.REF_CSA(REF_CSA),
.V0_REF_ADC(V0_REF_ADC),
.V1_REF_ADC(V1_REF_ADC),
.V2_REF_ADC(V2_REF_ADC),
.V1_WL(V1_WL),
.V2_WL(V2_WL),
.V3_WL(V3_WL),
.V4_WL(V4_WL),
.V1_SL(V1_SL),
.V2_SL(V2_SL),
.V3_SL(V3_SL),
.V4_SL(V4_SL),
.V1_BL(V1_BL),
.V2_BL(V2_BL),
.V3_BL(V3_BL),
.V4_BL(V4_BL),
.ENABLE_SL(ENABLE_SL),
.ENABLE_BL(ENABLE_BL),
.ENABLE_WL(ENABLE_WL),
.IN0_WL(IN0_WL),
.IN1_WL(IN1_WL),
.IN0_BL(IN0_BL),
.IN1_BL(IN1_BL),
.IN0_SL(IN0_SL),
.IN1_SL(IN1_SL),
.CSA(CSA),
.ENABLE_CSA(ENABLE_CSA),
.ADC_OUT0(ADC_OUT0),
.ADC_OUT1(ADC_OUT1),
.ADC_OUT2(ADC_OUT2),
.PRE(PRE),
.CLK_EN_ADC(CLK_EN_ADC),
.SAEN_CSA(SAEN_CSA)
);
RRAM_CONTROLLER U_RRAM_CONTROLLER (
.clk(clk),
.rst(rst),
.wishbone_data_in(wishbone_data_in),
.wishbone_data_out(wishbone_data_out),
.start_operation(start_operation),
.wishbone_address_bus(wishbone_address_bus),
.wbs_we_i(wbs_we_i),
.rd_sync_fifo_output_buffer_ADC(rd_sync_fifo_output_buffer_ADC),
.rd_sync_fifo_output_buffer_CSA(rd_sync_fifo_output_buffer_CSA),
.ENABLE_WL(ENABLE_WL),
.ENABLE_SL(ENABLE_SL),
.ENABLE_BL(ENABLE_BL),
.COL_SELECT(COL_SELECT),
.PRE(PRE),
.CLK_EN_ADC(CLK_EN_ADC),
.SAEN_CSA(SAEN_CSA),
.CSA(CSA),
.ADC_OUT0(ADC_OUT0),
.ADC_OUT1(ADC_OUT1),
.ADC_OUT2(ADC_OUT2),
.IN0_WL(IN0_WL),
.IN1_WL(IN1_WL),
.IN0_BL(IN0_BL),
.IN1_BL(IN1_BL),
.IN0_SL(IN0_SL),
.IN1_SL(IN1_SL)
);
endmodule
| 6.879876 |
module top_xc2v (
input osc_clk,
input rxd,
output txd,
output led0,
output led1,
output led2,
output led3,
output led4,
output led5,
output led6,
output led7,
output j7_5,
output j7_6,
output j7_9,
output j7_10,
output j7_11,
output j7_12,
output j7_13,
output j7_14,
output j4_1,
output j4_2,
output j4_3,
output j4_4,
output j4_5,
output j4_6,
output j4_7,
output j4_8,
output j4_11,
output j4_12,
output j4_13,
output j4_14,
output j4_15,
output j4_16,
output j4_17,
output j4_18
);
wire rst;
wire motor_x_step;
wire motor_x_dir;
wire motor_x_enable;
wire motor_y_step;
wire motor_y_dir;
wire motor_y_enable;
wire motor_z_step;
wire motor_z_dir;
wire motor_z_enable;
wire motor_a_step;
wire motor_a_dir;
wire motor_a_enable;
assign rst = 0;
assign j4_2 = motor_x_step;
assign j4_4 = motor_y_step;
assign j4_6 = motor_z_step;
assign j4_8 = motor_a_step;
assign j4_1 = motor_x_dir;
assign j4_3 = motor_y_dir;
assign j4_5 = motor_z_dir;
assign j4_7 = motor_a_dir;
assign j4_11 = motor_x_enable;
assign j4_12 = motor_y_enable;
assign j4_13 = motor_z_enable;
assign j4_14 = motor_a_enable;
assign j7_11 = 0;
assign j7_12 = 0;
assign j7_13 = 0;
assign j7_5 = 0;
assign j7_6 = 0;
assign j7_9 = 0;
assign j7_10 = 0;
assign j7_14 = 0;
assign j4_15 = 0;
assign j4_16 = 0;
assign j4_17 = 0;
assign j4_18 = 0;
assign led0 = 0;
assign led1 = 0;
assign led2 = 0;
assign led3 = 0;
assign led4 = 0;
assign led5 = 0;
assign led6 = 0;
assign led7 = 0;
fpgamotion #(
.UART_TOP(15000)
) uclock1 (
.osc_clk(osc_clk),
.rst(rst),
.rxd(rxd),
.txd(txd),
.motor_x_step(motor_x_step),
.motor_x_dir(motor_x_dir),
.motor_x_enable(motor_x_enable),
.motor_y_step(motor_y_step),
.motor_y_dir(motor_y_dir),
.motor_y_enable(motor_y_enable),
.motor_z_step(motor_z_step),
.motor_z_dir(motor_z_dir),
.motor_z_enable(motor_z_enable),
.motor_a_step(motor_a_step),
.motor_a_dir(motor_a_dir),
.motor_a_enable(motor_a_enable)
);
endmodule
| 6.806586 |
module top_xinlv (
input clk,
input rst_n,
input data_rx,
output reg [7:0] xinlv
);
wire [7:0] data_tx;
wire rx_int;
wire [7:0] xinlv_1;
reg [25:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt <= 26'd0;
else if (cnt == 26'd5000_0000 - 1) cnt <= 26'd0;
else cnt <= cnt + 1;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) xinlv <= 8'b0;
else if (cnt == 26'd5000_0000 - 1) xinlv <= xinlv_1;
else xinlv <= xinlv;
end
xinlv_rx xinlv_rx (
.clk(clk),
.rst_n(rst_n),
.data_rx(data_tx),
.rx_int(rx_int),
.xinlv(xinlv_1)
);
uart_bps_xinlv u_uart_bps_xinlv (
.clk(clk),
.rst_n(rst_n),
.cnt_start(bps_start),
.bps_sig(clk_bps)
);
uart_receive_xinlv u_uart_receive_xinlv (
.clk(clk),
.rst_n(rst_n),
.clk_bps(clk_bps),
.data_rx(data_rx),
.rx_int(rx_int),
.data_tx(data_tx),
.bps_start(bps_start)
);
endmodule
| 6.65745 |
module top_z80 (
input I_CLK,
input I_N_RESET,
input I_N_NMI,
input I_N_INT,
output [15:0] O_ADDR,
output O_N_IORQ,
output O_N_HALT,
output O_N_M1,
output O_N_MREQ,
output O_N_RD,
output O_N_WR,
inout [7:0] IO_DATA,
inout VCC,
inout GND,
inout VCC3IO,
inout GNDIO
);
wire clk;
wire n_reset;
wire n_nmi;
wire n_int;
wire [15:0] addr;
wire n_iorq;
wire n_halt;
wire n_m1;
wire n_mreq;
wire n_rd;
wire n_wr;
wire [7:0] data_in;
wire [7:0] data_out;
wire data_out_en;
pads pads_i (
// Inputs
.I_CLK(I_CLK),
.I_N_RESET(I_N_RESET),
.I_N_NMI(I_N_NMI),
.I_N_INT(I_N_INT),
.n_iorq(n_iorq),
.n_halt(n_halt),
.n_m1(n_m1),
.n_mreq(n_mreq),
.n_rd(n_rd),
.n_wr(n_wr),
.addr(addr),
.data_out(data_out),
.data_out_en(data_out_en),
// Outputs
.O_ADDR(O_ADDR),
.O_N_IORQ(O_N_IORQ),
.O_N_HALT(O_N_HALT),
.O_N_M1(O_N_M1),
.O_N_MREQ(O_N_MREQ),
.O_N_RD(O_N_RD),
.O_N_WR(O_N_WR),
.clk(clk),
.n_reset(n_reset),
.n_nmi(n_nmi),
.n_int(n_int),
.data_in(data_in),
.IO_DATA(IO_DATA),
.VCC(VCC),
.GND(GND),
.VCC3IO(VCC3IO),
.GNDIO(GNDIO)
);
z80 z80_i (
// Inputs
.clk(clk),
.n_reset(n_reset),
.n_int(n_int),
.n_nmi(n_nmi),
.din(data_in),
// Outputs
.n_iorq(n_iorq),
.n_halt(n_halt),
.n_m1(n_m1),
.n_mreq(n_mreq),
.n_rd(n_rd),
.n_wr(n_wr),
.addr(addr),
.dout(data_out),
.dout_en(data_out_en)
);
endmodule
| 7.172512 |
module top (
input rx,
output tx,
output sync
);
wire clk;
SB_HFOSC #(
.CLKHF_DIV("0b10")
) u_SB_HFOSC (
.CLKHFPU(1),
.CLKHFEN(1),
.CLKHF (clk)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
z80sbc machine (
.clk(clk),
.reset(~resetn),
.rx(rx),
.tx(tx),
.mreq_n(sync)
);
endmodule
| 7.233807 |
module StrideHandler (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_write,
input [20:0] io_in_bits_address,
input [20:0] io_in_bits_size,
input [ 2:0] io_in_bits_stride,
input io_in_bits_reverse,
input io_out_ready,
output io_out_valid,
output io_out_bits_write,
output [20:0] io_out_bits_address,
output [20:0] io_out_bits_size
);
wire handler_clock; // @[StrideHandler.scala 27:23]
wire handler_reset; // @[StrideHandler.scala 27:23]
wire handler_io_in_ready; // @[StrideHandler.scala 27:23]
wire handler_io_in_valid; // @[StrideHandler.scala 27:23]
wire handler_io_in_bits_write; // @[StrideHandler.scala 27:23]
wire [20:0] handler_io_in_bits_address; // @[StrideHandler.scala 27:23]
wire [20:0] handler_io_in_bits_size; // @[StrideHandler.scala 27:23]
wire [2:0] handler_io_in_bits_stride; // @[StrideHandler.scala 27:23]
wire handler_io_in_bits_reverse; // @[StrideHandler.scala 27:23]
wire handler_io_out_ready; // @[StrideHandler.scala 27:23]
wire handler_io_out_valid; // @[StrideHandler.scala 27:23]
wire handler_io_out_bits_write; // @[StrideHandler.scala 27:23]
wire [20:0] handler_io_out_bits_address; // @[StrideHandler.scala 27:23]
SizeAndStrideHandler handler ( // @[StrideHandler.scala 27:23]
.clock(handler_clock),
.reset(handler_reset),
.io_in_ready(handler_io_in_ready),
.io_in_valid(handler_io_in_valid),
.io_in_bits_write(handler_io_in_bits_write),
.io_in_bits_address(handler_io_in_bits_address),
.io_in_bits_size(handler_io_in_bits_size),
.io_in_bits_stride(handler_io_in_bits_stride),
.io_in_bits_reverse(handler_io_in_bits_reverse),
.io_out_ready(handler_io_out_ready),
.io_out_valid(handler_io_out_valid),
.io_out_bits_write(handler_io_out_bits_write),
.io_out_bits_address(handler_io_out_bits_address)
);
assign io_in_ready = io_in_bits_stride == 3'h0 ? io_out_ready : handler_io_in_ready; // @[StrideHandler.scala 41:32 49:14 52:19]
assign io_out_valid = io_in_bits_stride == 3'h0 ? io_in_valid : handler_io_out_valid; // @[StrideHandler.scala 41:32 50:18 61:18]
assign io_out_bits_write = io_in_bits_stride == 3'h0 ? io_in_bits_write : handler_io_out_bits_write; // @[StrideHandler.scala 41:32 44:36 55:36]
assign io_out_bits_address = io_in_bits_stride == 3'h0 ? io_in_bits_address : handler_io_out_bits_address; // @[StrideHandler.scala 41:32 47:25 58:25]
assign io_out_bits_size = io_in_bits_stride == 3'h0 ? io_in_bits_size : 21'h0; // @[StrideHandler.scala 41:32 48:22 59:22]
assign handler_clock = clock;
assign handler_reset = reset;
assign handler_io_in_valid = io_in_bits_stride == 3'h0 ? 1'h0 : io_in_valid; // @[StrideHandler.scala 37:23 41:32 52:19]
assign handler_io_in_bits_write = io_in_bits_stride == 3'h0 ? 1'h0 : io_in_bits_write; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_address = io_in_bits_stride == 3'h0 ? 21'h0 : io_in_bits_address; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_size = io_in_bits_stride == 3'h0 ? 21'h0 : io_in_bits_size; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_stride = io_in_bits_stride == 3'h0 ? 3'h0 : io_in_bits_stride; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_reverse = io_in_bits_stride == 3'h0 ? 1'h0 : io_in_bits_reverse; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_out_ready = io_in_bits_stride == 3'h0 ? 1'h0 : io_out_ready; // @[StrideHandler.scala 39:24 41:32 60:26]
endmodule
| 8.268025 |
module SizeHandler_3 (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_sel,
input [13:0] io_in_bits_size,
input io_out_ready,
output io_out_valid,
output io_out_bits_sel
);
wire sizeCounter_clock; // @[Counter.scala 34:19]
wire sizeCounter_reset; // @[Counter.scala 34:19]
wire sizeCounter_io_value_ready; // @[Counter.scala 34:19]
wire [13:0] sizeCounter_io_value_bits; // @[Counter.scala 34:19]
wire sizeCounter_io_resetValue; // @[Counter.scala 34:19]
wire fire = io_in_valid & io_out_ready; // @[SizeHandler.scala 32:23]
Counter_2 sizeCounter ( // @[Counter.scala 34:19]
.clock(sizeCounter_clock),
.reset(sizeCounter_reset),
.io_value_ready(sizeCounter_io_value_ready),
.io_value_bits(sizeCounter_io_value_bits),
.io_resetValue(sizeCounter_io_resetValue)
);
assign io_in_ready = sizeCounter_io_value_bits == io_in_bits_size & io_out_ready; // @[SizeHandler.scala 34:52 35:14 38:14]
assign io_out_valid = io_in_valid; // @[SizeHandler.scala 25:16]
assign io_out_bits_sel = io_in_bits_sel; // @[SizeHandler.scala 28:34]
assign sizeCounter_clock = clock;
assign sizeCounter_reset = reset;
assign sizeCounter_io_value_ready = sizeCounter_io_value_bits == io_in_bits_size ? 1'h0 : fire; // @[SizeHandler.scala 34:52 Counter.scala 36:22 SizeHandler.scala 39:32]
assign sizeCounter_io_resetValue = sizeCounter_io_value_bits == io_in_bits_size & fire; // @[SizeHandler.scala 34:52 Counter.scala 35:21 SizeHandler.scala 36:31]
endmodule
| 6.694676 |
module BurstSplitter (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [511:0] io_in_bits_data,
input io_out_ready,
output io_out_valid,
output [511:0] io_out_bits_data,
output io_out_bits_last
);
wire counter_clock; // @[Counter.scala 34:19]
wire counter_reset; // @[Counter.scala 34:19]
wire counter_io_value_ready; // @[Counter.scala 34:19]
wire [7:0] counter_io_value_bits; // @[Counter.scala 34:19]
wire counter_io_resetValue; // @[Counter.scala 34:19]
wire _counter_io_resetValue_T = io_out_ready & io_out_valid; // @[Decoupled.scala 50:35]
Counter_10 counter ( // @[Counter.scala 34:19]
.clock(counter_clock),
.reset(counter_reset),
.io_value_ready(counter_io_value_ready),
.io_value_bits(counter_io_value_bits),
.io_resetValue(counter_io_resetValue)
);
assign io_control_ready = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[MemBoundarySplitter.scala 45:51 48:22 52:22]
assign io_in_ready = io_control_valid & io_out_ready; // @[MemBoundarySplitter.scala 41:35]
assign io_out_valid = io_control_valid & io_in_valid; // @[MemBoundarySplitter.scala 40:36]
assign io_out_bits_data = io_in_bits_data; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_last = counter_io_value_bits == io_control_bits; // @[MemBoundarySplitter.scala 45:30]
assign counter_clock = clock;
assign counter_reset = reset;
assign counter_io_value_ready = counter_io_value_bits == io_control_bits ? 1'h0 : _counter_io_resetValue_T; // @[Counter.scala 36:22 MemBoundarySplitter.scala 45:51 51:28]
assign counter_io_resetValue = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[Counter.scala 35:21 MemBoundarySplitter.scala 45:51 47:27]
endmodule
| 7.518602 |
module BurstSplitter_1 (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [ 5:0] io_in_bits_id,
input [511:0] io_in_bits_data,
input [ 63:0] io_in_bits_strb,
input io_out_ready,
output io_out_valid,
output [ 5:0] io_out_bits_id,
output [511:0] io_out_bits_data,
output [ 63:0] io_out_bits_strb,
output io_out_bits_last
);
wire counter_clock; // @[Counter.scala 34:19]
wire counter_reset; // @[Counter.scala 34:19]
wire counter_io_value_ready; // @[Counter.scala 34:19]
wire [7:0] counter_io_value_bits; // @[Counter.scala 34:19]
wire counter_io_resetValue; // @[Counter.scala 34:19]
wire _counter_io_resetValue_T = io_out_ready & io_out_valid; // @[Decoupled.scala 50:35]
Counter_10 counter ( // @[Counter.scala 34:19]
.clock(counter_clock),
.reset(counter_reset),
.io_value_ready(counter_io_value_ready),
.io_value_bits(counter_io_value_bits),
.io_resetValue(counter_io_resetValue)
);
assign io_control_ready = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[MemBoundarySplitter.scala 45:51 48:22 52:22]
assign io_in_ready = io_control_valid & io_out_ready; // @[MemBoundarySplitter.scala 41:35]
assign io_out_valid = io_control_valid & io_in_valid; // @[MemBoundarySplitter.scala 40:36]
assign io_out_bits_id = io_in_bits_id; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_data = io_in_bits_data; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_strb = io_in_bits_strb; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_last = counter_io_value_bits == io_control_bits; // @[MemBoundarySplitter.scala 45:30]
assign counter_clock = clock;
assign counter_reset = reset;
assign counter_io_value_ready = counter_io_value_bits == io_control_bits ? 1'h0 : _counter_io_resetValue_T; // @[Counter.scala 36:22 MemBoundarySplitter.scala 45:51 51:28]
assign counter_io_resetValue = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[Counter.scala 35:21 MemBoundarySplitter.scala 45:51 47:27]
endmodule
| 7.518602 |
module Filter (
output io_control_ready,
input io_control_valid,
input io_control_bits,
output io_in_ready,
input io_in_valid,
input io_out_ready,
output io_out_valid
);
assign io_control_ready = io_control_bits ? io_in_valid & io_out_ready : io_in_valid; // @[MemBoundarySplitter.scala 71:25 74:22 78:22]
assign io_in_ready = io_control_bits ? io_control_valid & io_out_ready : io_control_valid; // @[MemBoundarySplitter.scala 71:25 73:17 77:17]
assign io_out_valid = io_control_bits & (io_control_valid & io_in_valid); // @[MemBoundarySplitter.scala 71:25 72:18 76:18]
endmodule
| 7.016323 |
module StrideHandler (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_write,
input [20:0] io_in_bits_address,
input [20:0] io_in_bits_size,
input [ 2:0] io_in_bits_stride,
input io_in_bits_reverse,
input io_out_ready,
output io_out_valid,
output io_out_bits_write,
output [20:0] io_out_bits_address,
output [20:0] io_out_bits_size
);
wire handler_clock; // @[StrideHandler.scala 27:23]
wire handler_reset; // @[StrideHandler.scala 27:23]
wire handler_io_in_ready; // @[StrideHandler.scala 27:23]
wire handler_io_in_valid; // @[StrideHandler.scala 27:23]
wire handler_io_in_bits_write; // @[StrideHandler.scala 27:23]
wire [20:0] handler_io_in_bits_address; // @[StrideHandler.scala 27:23]
wire [20:0] handler_io_in_bits_size; // @[StrideHandler.scala 27:23]
wire [2:0] handler_io_in_bits_stride; // @[StrideHandler.scala 27:23]
wire handler_io_in_bits_reverse; // @[StrideHandler.scala 27:23]
wire handler_io_out_ready; // @[StrideHandler.scala 27:23]
wire handler_io_out_valid; // @[StrideHandler.scala 27:23]
wire handler_io_out_bits_write; // @[StrideHandler.scala 27:23]
wire [20:0] handler_io_out_bits_address; // @[StrideHandler.scala 27:23]
SizeAndStrideHandler handler ( // @[StrideHandler.scala 27:23]
.clock(handler_clock),
.reset(handler_reset),
.io_in_ready(handler_io_in_ready),
.io_in_valid(handler_io_in_valid),
.io_in_bits_write(handler_io_in_bits_write),
.io_in_bits_address(handler_io_in_bits_address),
.io_in_bits_size(handler_io_in_bits_size),
.io_in_bits_stride(handler_io_in_bits_stride),
.io_in_bits_reverse(handler_io_in_bits_reverse),
.io_out_ready(handler_io_out_ready),
.io_out_valid(handler_io_out_valid),
.io_out_bits_write(handler_io_out_bits_write),
.io_out_bits_address(handler_io_out_bits_address)
);
assign io_in_ready = io_in_bits_stride == 3'h0 ? io_out_ready : handler_io_in_ready; // @[StrideHandler.scala 41:32 49:14 52:19]
assign io_out_valid = io_in_bits_stride == 3'h0 ? io_in_valid : handler_io_out_valid; // @[StrideHandler.scala 41:32 50:18 61:18]
assign io_out_bits_write = io_in_bits_stride == 3'h0 ? io_in_bits_write : handler_io_out_bits_write; // @[StrideHandler.scala 41:32 44:36 55:36]
assign io_out_bits_address = io_in_bits_stride == 3'h0 ? io_in_bits_address : handler_io_out_bits_address; // @[StrideHandler.scala 41:32 47:25 58:25]
assign io_out_bits_size = io_in_bits_stride == 3'h0 ? io_in_bits_size : 21'h0; // @[StrideHandler.scala 41:32 48:22 59:22]
assign handler_clock = clock;
assign handler_reset = reset;
assign handler_io_in_valid = io_in_bits_stride == 3'h0 ? 1'h0 : io_in_valid; // @[StrideHandler.scala 37:23 41:32 52:19]
assign handler_io_in_bits_write = io_in_bits_stride == 3'h0 ? 1'h0 : io_in_bits_write; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_address = io_in_bits_stride == 3'h0 ? 21'h0 : io_in_bits_address; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_size = io_in_bits_stride == 3'h0 ? 21'h0 : io_in_bits_size; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_stride = io_in_bits_stride == 3'h0 ? 3'h0 : io_in_bits_stride; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_in_bits_reverse = io_in_bits_stride == 3'h0 ? 1'h0 : io_in_bits_reverse; // @[StrideHandler.scala 38:22 41:32 52:19]
assign handler_io_out_ready = io_in_bits_stride == 3'h0 ? 1'h0 : io_out_ready; // @[StrideHandler.scala 39:24 41:32 60:26]
endmodule
| 8.268025 |
module SizeHandler_3 (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_sel,
input [15:0] io_in_bits_size,
input io_out_ready,
output io_out_valid,
output io_out_bits_sel
);
wire sizeCounter_clock; // @[Counter.scala 34:19]
wire sizeCounter_reset; // @[Counter.scala 34:19]
wire sizeCounter_io_value_ready; // @[Counter.scala 34:19]
wire [15:0] sizeCounter_io_value_bits; // @[Counter.scala 34:19]
wire sizeCounter_io_resetValue; // @[Counter.scala 34:19]
wire fire = io_in_valid & io_out_ready; // @[SizeHandler.scala 32:23]
Counter_2 sizeCounter ( // @[Counter.scala 34:19]
.clock(sizeCounter_clock),
.reset(sizeCounter_reset),
.io_value_ready(sizeCounter_io_value_ready),
.io_value_bits(sizeCounter_io_value_bits),
.io_resetValue(sizeCounter_io_resetValue)
);
assign io_in_ready = sizeCounter_io_value_bits == io_in_bits_size & io_out_ready; // @[SizeHandler.scala 34:52 35:14 38:14]
assign io_out_valid = io_in_valid; // @[SizeHandler.scala 25:16]
assign io_out_bits_sel = io_in_bits_sel; // @[SizeHandler.scala 28:34]
assign sizeCounter_clock = clock;
assign sizeCounter_reset = reset;
assign sizeCounter_io_value_ready = sizeCounter_io_value_bits == io_in_bits_size ? 1'h0 : fire; // @[SizeHandler.scala 34:52 Counter.scala 36:22 SizeHandler.scala 39:32]
assign sizeCounter_io_resetValue = sizeCounter_io_value_bits == io_in_bits_size & fire; // @[SizeHandler.scala 34:52 Counter.scala 35:21 SizeHandler.scala 36:31]
endmodule
| 6.694676 |
module BurstSplitter (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [511:0] io_in_bits_data,
input io_out_ready,
output io_out_valid,
output [511:0] io_out_bits_data,
output io_out_bits_last
);
wire counter_clock; // @[Counter.scala 34:19]
wire counter_reset; // @[Counter.scala 34:19]
wire counter_io_value_ready; // @[Counter.scala 34:19]
wire [7:0] counter_io_value_bits; // @[Counter.scala 34:19]
wire counter_io_resetValue; // @[Counter.scala 34:19]
wire _counter_io_resetValue_T = io_out_ready & io_out_valid; // @[Decoupled.scala 50:35]
Counter_10 counter ( // @[Counter.scala 34:19]
.clock(counter_clock),
.reset(counter_reset),
.io_value_ready(counter_io_value_ready),
.io_value_bits(counter_io_value_bits),
.io_resetValue(counter_io_resetValue)
);
assign io_control_ready = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[MemBoundarySplitter.scala 45:51 48:22 52:22]
assign io_in_ready = io_control_valid & io_out_ready; // @[MemBoundarySplitter.scala 41:35]
assign io_out_valid = io_control_valid & io_in_valid; // @[MemBoundarySplitter.scala 40:36]
assign io_out_bits_data = io_in_bits_data; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_last = counter_io_value_bits == io_control_bits; // @[MemBoundarySplitter.scala 45:30]
assign counter_clock = clock;
assign counter_reset = reset;
assign counter_io_value_ready = counter_io_value_bits == io_control_bits ? 1'h0 : _counter_io_resetValue_T; // @[Counter.scala 36:22 MemBoundarySplitter.scala 45:51 51:28]
assign counter_io_resetValue = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[Counter.scala 35:21 MemBoundarySplitter.scala 45:51 47:27]
endmodule
| 7.518602 |
module BurstSplitter_1 (
input clock,
input reset,
output io_control_ready,
input io_control_valid,
input [ 7:0] io_control_bits,
output io_in_ready,
input io_in_valid,
input [ 5:0] io_in_bits_id,
input [511:0] io_in_bits_data,
input [ 63:0] io_in_bits_strb,
input io_out_ready,
output io_out_valid,
output [ 5:0] io_out_bits_id,
output [511:0] io_out_bits_data,
output [ 63:0] io_out_bits_strb,
output io_out_bits_last
);
wire counter_clock; // @[Counter.scala 34:19]
wire counter_reset; // @[Counter.scala 34:19]
wire counter_io_value_ready; // @[Counter.scala 34:19]
wire [7:0] counter_io_value_bits; // @[Counter.scala 34:19]
wire counter_io_resetValue; // @[Counter.scala 34:19]
wire _counter_io_resetValue_T = io_out_ready & io_out_valid; // @[Decoupled.scala 50:35]
Counter_10 counter ( // @[Counter.scala 34:19]
.clock(counter_clock),
.reset(counter_reset),
.io_value_ready(counter_io_value_ready),
.io_value_bits(counter_io_value_bits),
.io_resetValue(counter_io_resetValue)
);
assign io_control_ready = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[MemBoundarySplitter.scala 45:51 48:22 52:22]
assign io_in_ready = io_control_valid & io_out_ready; // @[MemBoundarySplitter.scala 41:35]
assign io_out_valid = io_control_valid & io_in_valid; // @[MemBoundarySplitter.scala 40:36]
assign io_out_bits_id = io_in_bits_id; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_data = io_in_bits_data; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_strb = io_in_bits_strb; // @[MemBoundarySplitter.scala 34:34]
assign io_out_bits_last = counter_io_value_bits == io_control_bits; // @[MemBoundarySplitter.scala 45:30]
assign counter_clock = clock;
assign counter_reset = reset;
assign counter_io_value_ready = counter_io_value_bits == io_control_bits ? 1'h0 : _counter_io_resetValue_T; // @[Counter.scala 36:22 MemBoundarySplitter.scala 45:51 51:28]
assign counter_io_resetValue = counter_io_value_bits == io_control_bits & _counter_io_resetValue_T; // @[Counter.scala 35:21 MemBoundarySplitter.scala 45:51 47:27]
endmodule
| 7.518602 |
module Filter (
output io_control_ready,
input io_control_valid,
input io_control_bits,
output io_in_ready,
input io_in_valid,
input io_out_ready,
output io_out_valid
);
assign io_control_ready = io_control_bits ? io_in_valid & io_out_ready : io_in_valid; // @[MemBoundarySplitter.scala 71:25 74:22 78:22]
assign io_in_ready = io_control_bits ? io_control_valid & io_out_ready : io_control_valid; // @[MemBoundarySplitter.scala 71:25 73:17 77:17]
assign io_out_valid = io_control_bits & (io_control_valid & io_in_valid); // @[MemBoundarySplitter.scala 71:25 72:18 76:18]
endmodule
| 7.016323 |
module top (
input rx,
output tx,
output sync
);
wire clk;
SB_HFOSC #(
.CLKHF_DIV("0b10")
) u_SB_HFOSC (
.CLKHFPU(1),
.CLKHFEN(1),
.CLKHF (clk)
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
zexall machine (
.clk(clk),
.reset(~resetn),
.rx(rx),
.tx(tx),
.mreq_n(sync)
);
endmodule
| 7.233807 |
modules holding the particle pairs that has torsion force in between
//
// Purpose:
// Providing particle ids that contribute to the torsion force
//
// Data Organization:
// Address 0 for each cell module: # of bonded pairs in the memory
// MSB-LSB: {particle_id_1, particle_id_2}
//
// Used by:
// Bonded_TOP
//
// Dependency:
// mif file extracted from input dataset
//
// Testbench:
// N/A
//
// Timing:
// 2 cycles reading delay from input address and output data.
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module Torsion_Pair_MEM
#(
parameter DATA_WIDTH = 15*4,
parameter PARTICLE_NUM = 16384,
parameter ADDR_WIDTH = 14
)
(
address,
clock,
q
);
input [ADDR_WIDTH-1:0] address;
input clock;
output [DATA_WIDTH-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [DATA_WIDTH-1:0] sub_wire0;
wire [DATA_WIDTH-1:0] q = sub_wire0[DATA_WIDTH-1:0];
altera_syncram altera_syncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address2_a (1'b1),
.address2_b (1'b1),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({DATA_WIDTH{1'b1}}),
.data_b (1'b1),
.eccencbypass (1'b0),
.eccencparity (8'b0),
.eccstatus ( ),
.q_b ( ),
.rden_a (1'b1),
.rden_b (1'b1),
.sclr (1'b0),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altera_syncram_component.address_aclr_a = "NONE",
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
/**/
altera_syncram_component.intended_device_family = "Stratix 10",
altera_syncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = PARTICLE_NUM,
altera_syncram_component.operation_mode = "ROM",
altera_syncram_component.outdata_aclr_a = "NONE",
altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_reg_a = "CLOCK0",
altera_syncram_component.enable_force_to_zero = "FALSE",
altera_syncram_component.widthad_a = ADDR_WIDTH,
altera_syncram_component.width_a = DATA_WIDTH,
altera_syncram_component.width_byteena_a = 1;
endmodule
| 8.474291 |
module torus (
input wire clk,
input wire seed,
input wire seed_ena,
input wire life_step,
output wire [TORUS_WIDTH*TORUS_HEIGHT-1:0] torusv,
output wire torus_last
);
parameter TORUS_WIDTH = 32;
parameter TORUS_HEIGHT = 16;
localparam WMASK = (TORUS_WIDTH - 1);
localparam HMASK = (TORUS_HEIGHT - 1);
genvar x;
genvar y;
generate
for (y = 0; y < TORUS_HEIGHT; y = y + 1) begin : crow
for (x = 0; x < TORUS_WIDTH; x = x + 1) begin : ccol
wire value;
wire seed_source;
assign seed_source = (y==0) && (x==0) ? seed :
(y!=0) && (x==0) ? crow[ y-1 ].ccol[ TORUS_WIDTH-1 ].value :
crow[ y ].ccol[ x-1 ].value ;
xcell my_xcell (
.clk (clk),
.seed_ena (seed_ena),
.life_step (life_step),
.in_up_left (crow[(y-1)&HMASK].ccol[(x-1)&WMASK].value),
.in_up (crow[(y-1)&HMASK].ccol[(x-0)&WMASK].value),
.in_up_right (crow[(y-1)&HMASK].ccol[(x+1)&WMASK].value),
.in_left (seed_ena ? seed_source : crow[(y-0)&HMASK].ccol[(x-1)&WMASK].value),
.in_right (crow[(y-0)&HMASK].ccol[(x+1)&WMASK].value),
.in_down_left (crow[(y+1)&HMASK].ccol[(x-1)&WMASK].value),
.in_down (crow[(y+1)&HMASK].ccol[(x-0)&WMASK].value),
.in_down_right(crow[(y+1)&HMASK].ccol[(x+1)&WMASK].value),
.cell_life (value)
);
assign torusv[y*TORUS_WIDTH+x] = crow[y].ccol[x].value;
end
end
endgenerate
assign torus_last = torusv[TORUS_HEIGHT*TORUS_WIDTH-1];
endmodule
| 7.952197 |
module torus #(
parameter H_SIZE = 3,
parameter PORT_SIZE = (37 + 2),
parameter NODES_NUM = 2
) (
input [NODES_NUM*4*PORT_SIZE-1:0] data_i,
output [NODES_NUM*4*PORT_SIZE-1:0] data_o
);
genvar i, j;
generate
for (i = 0; i < NODES_NUM; i = i + 1) // input index
for (j = i + 1; j < NODES_NUM; j = j + 1) // output index
if ( ( j == i + 1 ) & ( j % H_SIZE != 0 ) ) // port 0 to 2
begin
assign data_o [i*4*PORT_SIZE+0*PORT_SIZE+:PORT_SIZE] = data_i [j*4*PORT_SIZE + 2*PORT_SIZE+:PORT_SIZE];
assign data_o [j*4*PORT_SIZE+2*PORT_SIZE+:PORT_SIZE] = data_i [i*4*PORT_SIZE + 0*PORT_SIZE+:PORT_SIZE];
end
else if ( (j == i + 2) & ( i % H_SIZE == 0) ) // port 2 to 0
begin
assign data_o [j*4*PORT_SIZE+0*PORT_SIZE+:PORT_SIZE] = data_i [i*4*PORT_SIZE + 2*PORT_SIZE+:PORT_SIZE];
assign data_o [i*4*PORT_SIZE+2*PORT_SIZE+:PORT_SIZE] = data_i [j*4*PORT_SIZE + 0*PORT_SIZE+:PORT_SIZE];
end
else if (j == ( H_SIZE + i )) // port 1 to 3
begin
assign data_o [i*4*PORT_SIZE+1*PORT_SIZE+:PORT_SIZE] = data_i [j*4*PORT_SIZE + 3*PORT_SIZE+:PORT_SIZE];
assign data_o [j*4*PORT_SIZE+3*PORT_SIZE+:PORT_SIZE] = data_i [i*4*PORT_SIZE + 1*PORT_SIZE+:PORT_SIZE];
end
else if ( (j - i) == (NODES_NUM - H_SIZE) ) // port 3 to 1
begin
assign data_o [j*4*PORT_SIZE+1*PORT_SIZE+:PORT_SIZE] = data_i [i*4*PORT_SIZE + 3*PORT_SIZE+:PORT_SIZE];
assign data_o [i*4*PORT_SIZE+3*PORT_SIZE+:PORT_SIZE] = data_i [j*4*PORT_SIZE + 1*PORT_SIZE+:PORT_SIZE];
end
endgenerate
endmodule
| 7.203637 |
module TotalALU (
clk,
dataA,
dataB,
Signal,
Output,
reset
);
input reset;
input clk;
input [31:0] dataA;
input [31:0] dataB;
input [5:0] Signal;
output [31:0] Output;
// Signal ( 6-bits)?
// AND : 36
// OR : 37
// ADD : 32
// SUB : 34
// SLL : 00
// SLT : 42
// MULTU : 25
wire [31:0] temp;
parameter AND = 6'b100100;
parameter OR = 6'b100101;
parameter ADD = 6'b100000;
parameter SUB = 6'b100010;
parameter SLT = 6'b101010;
parameter SLL = 6'b000000;
parameter MULU = 6'b011011;
parameter MFHI = 6'b010000;
parameter MFLO = 6'b010010;
/*
wqUذT
*/
//============================
wire [5:0] SignaltoALU;
wire [5:0] SignaltoSHT;
wire [5:0] SignaltoMUL;
wire [5:0] SignaltoMUX;
wire [31:0] ALUOut, HiOut, LoOut, ShifterOut;
wire [31:0] dataOut;
wire [63:0] MulAns;
/*
wqUرu
*/
//============================
ALUControl ALUControl (
.clk(clk),
.Signal(Signal),
.SignaltoALU(SignaltoALU),
.SignaltoSHT(SignaltoSHT),
.SignaltoMUL(SignaltoMUL),
.SignaltoMUX(SignaltoMUX)
);
ALU ALU (
.dataA (dataA),
.dataB (dataB),
.Signal (SignaltoALU),
.dataOut(ALUOut),
.reset (reset)
);
Multipler Multipler (
.clk(clk),
.reset(reset),
.dataA(dataA),
.dataB(dataB),
.dataOut(MulAns),
.Signal(SignaltoMUL)
);
Shifter Shifter (
.dataA (dataA),
.dataB (dataB),
.Signal (SignaltoSHT),
.dataOut(ShifterOut),
.reset (reset)
);
HiLo HiLo (
.clk(clk),
.MulAns(MulAns),
.HiOut(HiOut),
.LoOut(LoOut),
.reset(reset)
);
MUX MUX (
.ALUOut (ALUOut),
.HiOut (HiOut),
.LoOut (LoOut),
.Shifter(ShifterOut),
.Signal (SignaltoMUX),
.dataOut(dataOut)
);
/*
إߦUmodule
*/
assign Output = dataOut;
endmodule
| 8.055983 |
module riseCount (
count,
control,
hiding,
reset
);
output [15:0] count;
input reset, hiding, control;
DecimalCounter4Dig dc4g (
.count(count),
.clock(control && hiding),
.reset(reset)
);
endmodule
| 6.775448 |
module rl (
reset,
go,
CLOCK_50,
CLOCK_WAIT,
CLOCK_RL,
Mheight,
hiding
);
input reset, go, CLOCK_50, CLOCK_RL, CLOCK_WAIT;
wire Mreset_height;
wire Mreset_wait;
wire Mheight_en;
wire Mheight_incr;
wire [2:0] Mwait;
output [4:0] Mheight;
output hiding;
MoleRL mrl (
.Mwait(Mwait),
.Mheight(Mheight),
.CLOCK_WAIT(CLOCK_WAIT),
.CLOCK_RL(CLOCK_RL),
.Mreset_wait(Mreset_wait),
.Mheight_en(Mheight_en),
.Mreset_height(Mreset_height),
.Mheight_incr(Mheight_incr)
);
MoleRLControlFSM mrlfsm (
.Mgo(go),
.reset(reset),
.CLOCK_50(CLOCK_50),
.hiding(hiding),
.Mwait(Mwait),
.Mheight(Mheight),
.Mreset_wait(Mreset_wait),
.Mheight_en(Mheight_en),
.Mreset_height(Mreset_height),
.Mheight_incr(Mheight_incr)
);
endmodule
| 6.532131 |
module DigitAdder (
A,
B,
carry_in,
out,
carry_out
);
input [3:0] A;
input [3:0] B;
input carry_in;
output reg [3:0] out;
output reg carry_out;
always @(*) begin
if (A + B + carry_in < 5'd10) begin
out[3:0] = A + B + carry_in;
carry_out = 1'b0;
end else begin
out[3:0] = A + B + carry_in + 4'd6;
carry_out = 1'b1;
end
end
endmodule
| 6.722939 |
module MoleRL (
Mwait,
Mheight,
CLOCK_WAIT,
CLOCK_RL,
Mreset_wait,
Mheight_en,
Mreset_height,
Mheight_incr
);
input Mreset_height;
input Mreset_wait;
input Mheight_en;
input Mheight_incr;
input CLOCK_WAIT;
input CLOCK_RL;
output reg [2:0] Mwait;
output reg [4:0] Mheight;
always @(posedge CLOCK_WAIT, posedge Mreset_wait) begin
if (Mreset_wait == 1'b1) Mwait <= 3'b0;
else Mwait <= Mwait + 1'b1;
end
always @(posedge CLOCK_RL, posedge Mreset_height) begin
if (Mreset_height == 1'b1) Mheight <= 3'b0;
else begin
if (Mheight_en == 1'b1 && Mheight_incr == 1'b1 && Mheight == 5'd20) Mheight <= 5'd20;
else if (Mheight_en == 1'b1 && Mheight_incr == 1'b1) Mheight <= Mheight + 1'b1;
else if (Mheight_en == 1'b1 && Mheight_incr == 1'b0 && Mheight == 5'b0) Mheight <= 5'b0;
else if (Mheight_en == 1'b1 && Mheight_incr == 1'b0) Mheight <= Mheight - 1'b1;
end
end
endmodule
| 6.557012 |
module board_capabilities (
input wire clk,
input wire poweron_rst_n,
input wire in_boot_mode,
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire [2:0] fpga_model,
input wire [7:0] din,
output wire [7:0] dout,
output wire oe,
output wire [1:0] current_value
);
`include "config.vh"
assign oe = (zxuno_addr == MEMREPORT && zxuno_regrd == 1'b1);
reg [1:0] memreport = 2'b00; // initial value
assign dout = {3'b000, fpga_model, memreport};
assign current_value = memreport[1:0];
always @(posedge clk) begin
if (poweron_rst_n == 1'b0)
memreport <= 2'b00; // or after a hardware reset (not implemented yet)
else if (zxuno_addr == MEMREPORT && zxuno_regwr == 1'b1 && in_boot_mode == 1'b1)
memreport <= din[1:0];
end
endmodule
| 7.128859 |
module total_tb ();
reg reset_n;
reg clk;
reg clk_vga;
reg wb_we;
reg [31:0] wb_dat;
reg [26:0] wb_adr;
wire wb_ack;
wire [3:0] oRed; // red signal
wire [3:0] oGreen; // green signal
wire [3:0] oBlue; // blue signal
wire oHs; // Hori sync
wire oVs; // Vert sync
GPUTop gpu (
.clk_100MHz(clk),
.reset_n(reset_n),
.wb_we_i(wb_we),
.wb_sel_i(4'hf),
.wb_adr_i(wb_adr),
.wb_dat_i(wb_dat),
.wb_ack_o(wb_ack),
.clk_vga(clk_vga),
.oRed(oRed),
.oBlue(oBlue),
.oGreen(oGreen),
.oHs(oHs),
.oVs(oVs)
);
initial begin
clk = 0;
forever begin
#5 clk = ~clk;
end
end
initial begin
clk_vga = 0;
forever begin
#12.5
clk_vga = ~clk_vga;
end
end
initial begin
reset_n = 0;
wb_we = 0;
wb_adr = 0;
wb_dat = 1;
#17 reset_n = 1;
#20 wb_we = 1;
wb_adr = 26'h2000;
wb_dat = 32'hfcfefdfa;
#20 wb_adr = 26'h100;
wb_dat = 32'h0103;
#20 wb_adr = 26'h104;
wb_dat = 32'h2010;
#20 wb_adr = 36'hc;
wb_dat = 1;
#20 wb_adr = 26'h0;
wb_dat = 1;
#20 wb_adr = 26'h4;
#20 wb_we = 0;
end
endmodule
| 6.529441 |
module touchpad_controller (
input wire cclk,
rstb,
input wire touch_busy,
data_in,
output reg touch_clk,
output wire data_out,
output reg touch_csb,
output reg [11:0] x,
y,
z
);
reg [5:0] clk_div_counter;
reg [1:0] current_dimension;
wire [7:0] transaction_message;
assign transaction_message[0] = 1'b1;
assign transaction_message[2:1] = current_dimension;
assign transaction_message[3] = 1'b1;
assign transaction_message[5:4] = 2'b00;
assign transaction_message[7:6] = 2'b11;
// Shift out module
wire shift_out_ena;
reg shift_out_rst;
shift_out SHIFT_OUT (
.clk(cclk),
.touch_clk(touch_clk),
.data_in(transaction_message),
.ena(shift_out_ena),
.rst(shift_out_rst),
.data_out(data_out)
);
// Shift in module
wire shift_in_ena;
wire [11:0] touchpad_message;
reg shift_in_rst;
shift_in SHIFT_IN (
.clk(cclk),
.touch_clk(touch_clk),
.data_in(data_in),
.ena(shift_in_ena),
.rst(shift_in_rst),
.data_out(touchpad_message)
);
// Transaction counter
wire [31:0] transaction_counter;
reg counter_ena;
reg counter_rst;
counter TRANSACTION_COUNTER (
.clk(cclk),
.touch_clk(touch_clk),
.rstb(counter_rst),
.en(counter_ena),
.out(transaction_counter)
);
// Repetition counter
reg [31:0] repetition_counter;
// Make the shift in and shift out counter enables dependent on the transaction
// counter
assign shift_out_ena = (transaction_counter >= `CALL_START && transaction_counter < `CALL_END);
assign shift_in_ena = (transaction_counter >= `RESPONSE_START && transaction_counter < `RESPONSE_END);
always @(posedge cclk) begin
if (~rstb) begin
clk_div_counter <= 0;
//data_out <= 0;
touch_csb <= 1;
current_dimension <= `TOUCH_READ_X;
// Make sure all the modules are reset
counter_rst = 1;
shift_out_rst = 0;
shift_in_rst = 0;
touch_clk <= 0;
counter_ena <= 1;
repetition_counter <= 1;
// Initialize x,y,z values
x <= 12'd0;
y <= 12'd0;
z <= 12'd0;
end else begin
// Ensure that the touchpad controller gets a low csb signal
touch_csb <= 0;
// Set reset signals
counter_rst = (transaction_counter == `TRANSACTION_END);
shift_out_rst = ~(transaction_counter == `TRANSACTION_END); // active low
shift_in_rst = ~(transaction_counter == `TRANSACTION_END); // active low
if (counter_rst) begin
if (repetition_counter == `REPETITION_END) begin
case (current_dimension)
`TOUCH_READ_X: begin
current_dimension <= `TOUCH_READ_Y;
x <= touchpad_message;
end
`TOUCH_READ_Y: begin
current_dimension <= `TOUCH_READ_Z;
y <= touchpad_message;
end
`TOUCH_READ_Z: begin
current_dimension <= `TOUCH_READ_X;
z <= touchpad_message;
end
endcase
repetition_counter <= 0;
end else begin
repetition_counter <= repetition_counter + 1;
end
end
if (clk_div_counter != (`TOUCH_CLK_DIV_COUNT - 1)) begin
clk_div_counter <= clk_div_counter + 6'd1;
end else begin
clk_div_counter <= 0;
touch_clk <= ~touch_clk;
if (touch_clk) begin //negative edge logic
/* put all of your negative edge logic here */
end
if (~touch_clk) begin //positive edge logic
/* put all of your positive edge logic here */
end
end
end
end
endmodule
| 7.307405 |
module touchpad_controller_fast (
input wire cclk,
rstb,
input wire touch_busy,
data_in,
output wire touch_clk,
data_out,
output reg touch_csb,
output reg [8:0] x,
y,
z
);
reg [4:0] clk_div_counter;
reg [1:0] channel;
reg [11:0] x_raw, y_raw, z_raw, incoming_data;
wire [8:0] x_filtered, y_filtered, z_filtered;
wire [8:0] x_prefilter, y_prefilter, z_prefilter;
wire x_raw_changed, y_raw_changed, z_raw_changed;
wire [11:0] x_adj;
wire [11:0] y_adj;
wire [11:0] x_scaled, y_scaled;
reg [1:0] state;
assign x_raw_changed = (rx_done) & (channel == `TOUCH_READ_X) & &channel_switch_count;
assign y_raw_changed = (rx_done) & (channel == `TOUCH_READ_Y) & &channel_switch_count;
assign z_raw_changed = (rx_done) & (channel == `TOUCH_READ_Z) & &channel_switch_count;
assign x_adj = (x_raw > `TOUCH_X_ADJ_MIN) ? x_raw - `TOUCH_X_ADJ_MIN : 12'h0;
assign y_adj = (y_raw > `TOUCH_Y_ADJ_MIN) ? y_raw - `TOUCH_Y_ADJ_MIN : 12'h0;
assign x_scaled = (x_adj >> 3);
assign y_scaled = (y_adj >> 4) + (y_adj >> 6);
assign x_prefilter = (x_scaled[8:0] > 9'd479) ? 9'd479 : x_scaled[8:0];
assign y_prefilter = (y_scaled[8:0] > 9'd272) ? 9'd272 : y_scaled[8:0];
assign z_prefilter = z_raw[11:3];
averager #(
.N(9),
.M(10)
) FILTER_X (
.raw(x_prefilter),
.averaged(x_filtered),
.ena(x_raw_changed),
.cclk(cclk),
.rstb(rstb)
);
averager #(
.N(9),
.M(10)
) FILTER_Y (
.raw(y_prefilter),
.averaged(y_filtered),
.ena(y_raw_changed),
.cclk(cclk),
.rstb(rstb)
);
averager #(
.N(9),
.M(10)
) FILTER_Z (
.raw(z_prefilter),
.averaged(z_filtered),
.ena(z_raw_changed),
.cclk(cclk),
.rstb(rstb)
);
always @(*) begin
x = x_filtered;
y = y_filtered;
z = z_filtered;
end
wire [ 7:0] tx_buffer;
wire [11:0] rx_buffer;
assign tx_buffer[7] = 1'b1; //start bit
assign tx_buffer[6] = (channel == `TOUCH_READ_X); //addr2
assign tx_buffer[5] = (channel == `TOUCH_READ_Z); //addr1
assign tx_buffer[4] = 1'b1; //addr0
assign tx_buffer[3] = 1'b0;
assign tx_buffer[2] = 1'b0;
assign tx_buffer[1] = 1'b1;
assign tx_buffer[0] = 1'b1;
reg [2:0] channel_switch_count;
//this module handles sending/receiving bytes on an SPI like protocol
reg tx_start;
wire tx_done, rx_done;
ussrt #(
.CLK_DIVIDER(`TOUCH_CLK_DIV_COUNT),
.TX_N(8),
.RX_N(12),
.TX_EDGE(1'b0), //tx on negative edges
.RX_EDGE(1'b1), //rx on positive edges
.TX_MSB_FIRST(1),
.RX_MSB_FIRST(1)
) AD7873_INTERFACE (
.clk(cclk),
.rstb(rstb),
.sclk(touch_clk),
.csb(touch_csb),
.tx(tx_buffer),
.rx(rx_buffer),
.dout(data_out),
.din(data_in),
.tx_start(tx_start),
.tx_busy(0),
.rx_busy(touch_busy),
.tx_done(tx_done),
.rx_done(rx_done)
);
always @(posedge cclk) begin
if (~rstb) begin
channel <= `TOUCH_READ_X;
x_raw <= 0;
y_raw <= 0;
z_raw <= 0;
state <= `S_RESET;
channel_switch_count <= 0;
tx_start <= 0;
touch_csb <= 1;
end else begin
touch_csb <= 0;
case (state)
`S_RESET: begin
tx_start <= 1;
state <= `S_TXING;
end
`S_TXING: begin
if (tx_done) begin
tx_start <= 0;
state <= `S_RXING;
end
end
`S_RXING: begin
if (rx_done) begin
channel_switch_count <= channel_switch_count + 3'd1;
//change channel
if (&channel_switch_count) begin
//save incoming data
case (channel)
`TOUCH_READ_X: x_raw <= rx_buffer;
`TOUCH_READ_Y: y_raw <= rx_buffer;
`TOUCH_READ_Z: z_raw <= rx_buffer;
endcase
case (channel)
`TOUCH_READ_X: channel <= `TOUCH_READ_Y;
`TOUCH_READ_Y: channel <= `TOUCH_READ_Z;
default: channel <= `TOUCH_READ_X;
endcase
end
tx_start <= 1;
state <= `S_TXING;
end
end
endcase
end
end
endmodule
| 7.307405 |
module touch_control (
iCLK,
iRSTN,
iREADY,
iREG_GESTURE,
ix1,
iy1,
ix2,
iy2,
itouch_count,
oButton_state
);
parameter IDLE = 1'b0;
parameter TOUCH = 1'b1;
//=======================================================
// Port declarations
//=======================================================
input iCLK;
input iRSTN;
input iREADY;
input [7:0] iREG_GESTURE;
input [9:0] ix1; // X coordinate form touch panel
input [8:0] iy1; // Y coordinate form touch panel
input [9:0] ix2; // X coordinate form touch panel
input [8:0] iy2; // Y coordinate form touch panel
input [1:0] itouch_count;
//output reg [3:0] oY_MODE;
output [3:0] oButton_state;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg [9:0] temp;
reg [2:0] ready_d;
reg touch_state;
reg [8:0] wait_count;
//wire no_gesture_code;
//wire zoom_code;
//reg zoom, zoom_out;
//wire zoom_reset, state_reset, set_trig;
//wire y_mode_non_max, y_mode_non_min;
//=======================================================
// Structural coding
//=======================================================
/*assign no_gesture_code = iREG_GESTURE==8'h0;
assign zoom_code = iREG_GESTURE[6:3]==4'b1001;
assign zoom_reset = iREADY&&no_gesture_code&&zoom;
assign state_reset = wait_count[8] || zoom_reset;
assign set_trig = touch_state && state_reset;
assign y_mode_non_max = &oY_MODE ? 1'b0 : 1'b1;
assign y_mode_non_min = |oY_MODE ? 1'b1 : 1'b0;*/
assign right_btn = ((ix1>10'd700&&ix1<10'd800&&iy1>9'd400&&itouch_count!=0)||(ix2>10'd700&&ix2<10'd800&&iy2>9'd400&&itouch_count[1]))?1'b1:1'b0;
assign left_btn = ((ix1>10'd600&&ix1<10'd700&&iy1>9'd400&&itouch_count!=0)||(ix2>10'd600&&ix2<10'd700&&iy2>9'd400&&itouch_count[1]))?1'b1:1'b0;
assign up_btn = ((ix1>10'd0&&ix1<10'd100&&iy1>9'd400&&itouch_count!=0)||(ix2>10'd0&&ix2<10'd100&&iy2>9'd400&&itouch_count[1]))?1'b1:1'b0;
assign oButton_state = {1'b0, up_btn, left_btn, right_btn};
/*always@(posedge iCLK or negedge iRSTN)
begin
if (!iRSTN)
begin
touch_state <= 1'b0;
end else if (temp != iX_COORD)
begin
touch_state <= 1'b1;
end else
begin
touch_state <= 1'b0;
end
temp <= iX_COORD;
end*/
/*always@(posedge iCLK or negedge iRSTN)
if (!iRSTN)
begin
oY_MODE <= 4'b0;
end
else
begin
if (set_trig && zoom)
begin
if (zoom_out)
oY_MODE <= oY_MODE - y_mode_non_min;
else
oY_MODE <= oY_MODE + y_mode_non_max;
end
end
*/
/*always@(posedge iCLK or negedge iRSTN)
if (!iRSTN)
begin
ready_d <= 3'b0;
touch_state <= IDLE;
end
else
begin
ready_d <= {ready_d[1:0], iREADY};
case (touch_state)
IDLE : begin
if (!ready_d[2] && ready_d[1])
begin
touch_state <= TOUCH;
wait_count <= 9'b0;
end
end
TOUCH :
begin
if (state_reset)
begin
touch_state <= IDLE;
wait_count <= 9'b0;
end
if (ready_d[2] && !ready_d[1])
//if (!ready_d[2] && ready_d[1])
begin
wait_count <= 9'b0;
end
else
wait_count <= wait_count + 9'b1;
//if (!ready_d[2] && ready_d[1])
//begin
//end
end
endcase
end*/
endmodule
| 6.639204 |
module touch_ctrl_led (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号，低电平有效
input wire touch_key, //触摸按键信号
output reg led //led输出信号
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire touch_en; //触摸使能信号
//reg define
reg touch_key_dly1; //touch_key延迟一个时钟信号
reg touch_key_dly2; //touch_key延迟两个时钟信号
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//根据触摸按键信号的下降沿判断触摸了触摸按键
assign touch_en = touch_key_dly2 & (~touch_key_dly1);
//对touch_key信号延迟两个时钟周期用来产生触摸按键信号
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) begin
touch_key_dly1 <= 1'b0;
touch_key_dly2 <= 1'b0;
end else begin
touch_key_dly1 <= touch_key;
touch_key_dly2 <= touch_key_dly1;
end
//根据触摸使能信号控制led状态
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) led <= 1'b1;
else if (touch_en == 1'b1) led <= ~led;
endmodule
| 8.444983 |
module touch_led (
//input
input sys_clk, //时钟信号50Mhz
input sys_rst_n, //复位信号
input touch_key, //触摸按键
//output
output reg led //LED灯
);
//reg define
reg touch_key_d0;
reg touch_key_d1;
reg switch;
//wire define
wire touch_en;
//根据按键信号的上升沿判断按下了按键
assign touch_en = (~touch_key_d1) & touch_key_d0;
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n == 1'b0) begin
touch_key_d0 <= 1'b0;
touch_key_d1 <= 1'b0;
end else begin
touch_key_d0 <= touch_key;
touch_key_d1 <= touch_key_d0;
end
end
//对触摸按键端口接收的数据延迟两个周期
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n == 1'b0) switch <= 1'b0;
else begin
if (touch_en) switch <= switch + 1'b1;
else switch <= switch;
end
end
//根据上升沿使能信号切换led状态
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n == 1'b0) led <= 1'b1;
else begin
if (switch) led <= 1'b0;
else led <= 1'b1;
end
end
endmodule
| 6.748639 |
module
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 07/06/30 :| Initial Revision
// --------------------------------------------------------------------
module touch_point_detector (
iCLK,
iRST_n,
iX_COORD,
iY_COORD,
iNEW_COORD,
iSDRAM_WRITE_EN,
oPHOTO_CNT,
);
//============================================================================
// PARAMETER declarations
//============================================================================
parameter PHOTO_NUM = 3; // total photo numbers
parameter NEXT_PIC_XBD1 = 12'h0;
parameter NEXT_PIC_XBD2 = 12'h300;
parameter NEXT_PIC_YBD1 = 12'he00;
parameter NEXT_PIC_YBD2 = 12'hfff;
parameter PRE_PIC_XBD1 = 12'hd00;
parameter PRE_PIC_XBD2 = 12'hfff;
parameter PRE_PIC_YBD1 = 12'h000;
parameter PRE_PIC_YBD2 = 12'h200;
//===========================================================================
// PORT declarations
//===========================================================================
input iCLK; // system clock 50Mhz
input iRST_n; // system reset
input [11:0] iX_COORD; // X coordinate form touch panel
input [11:0] iY_COORD; // Y coordinate form touch panel
input iNEW_COORD; // new coordinates indicate
input iSDRAM_WRITE_EN; // sdram write enable
output [2:0] oPHOTO_CNT; // displaed photo number
//=============================================================================
// REG/WIRE declarations
//=============================================================================
reg mnew_coord;
wire nextpic_en;
wire prepic_en;
reg nextpic_set;
reg prepic_set;
reg [2:0] photo_cnt;
//=============================================================================
// Structural coding
//=============================================================================
// if incoming x and y coordinates fit next picture command area , nextpic_en goes high
assign nextpic_en = ((iX_COORD > NEXT_PIC_XBD1) && (iX_COORD < NEXT_PIC_XBD2) &&
(iY_COORD > NEXT_PIC_YBD1) && (iY_COORD < NEXT_PIC_YBD2))
?1:0;
// if incoming x and y coordinates fit previous picture command area , nextpic_en goes high
assign prepic_en = ((iX_COORD > PRE_PIC_XBD1) && (iX_COORD < PRE_PIC_XBD2) &&
(iY_COORD > PRE_PIC_YBD1) && (iY_COORD < PRE_PIC_YBD2))
?1:0;
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
mnew_coord<= 0;
else
mnew_coord<= iNEW_COORD;
end
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
nextpic_set <= 0;
else if (mnew_coord && nextpic_en &&(!iSDRAM_WRITE_EN))
nextpic_set <= 1;
else
nextpic_set <= 0;
end
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
prepic_set <= 0;
else if (mnew_coord && prepic_en && (!iSDRAM_WRITE_EN))
prepic_set <= 1;
else
prepic_set <= 0;
end
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
photo_cnt <= 0;
else
begin
if (nextpic_set)
begin
if(photo_cnt == (PHOTO_NUM-1))
photo_cnt <= 0;
else
photo_cnt <= photo_cnt + 1;
end
if (prepic_set)
begin
if(photo_cnt == 0)
photo_cnt <= (PHOTO_NUM-1);
else
photo_cnt <= photo_cnt - 1;
end
end
end
assign oPHOTO_CNT = photo_cnt;
endmodule
| 7.097087 |
module gnr_ram #(
parameter WIDTH = 8,
parameter DEPTH = 32,
parameter DATAFILE = ""
) (
input clock,
input write_en,
input [$clog2(DEPTH) - 1:0] w_addr,
input [WIDTH - 1:0] data_i,
input [$clog2(DEPTH) - 1:0] r_addr,
output reg ready,
output [WIDTH - 1:0] data_o
);
reg [WIDTH - 1:0] words[DEPTH - 1:0];
generate
if (DATAFILE)
initial begin
$readmemh(DATAFILE, words);
end
endgenerate
always @(posedge clock) begin
data_o <= words[r_addr];
ready <= 1'b1;
if (write_en) words[w_addr] <= data_i;
end
endmodule
| 7.682162 |
module to_driver_sd_avs (
input wire clk_sys,
input wire rst,
input wire ao486_rst,
// input hdd_avalon_master
input wire [31:0] hdd_avalon_master_address,
input wire hdd_avalon_master_read,
output wire [31:0] hdd_avalon_master_readdata,
input wire hdd_avalon_master_write,
input wire [31:0] hdd_avalon_master_writedata,
output wire hdd_avalon_master_waitrequest,
output reg hdd_avalon_master_readdatavalid,
// input bios_loader
input wire [31:0] bios_loader_address,
input wire bios_loader_read,
output wire [31:0] bios_loader_readdata,
input wire bios_loader_write,
input wire [31:0] bios_loader_writedata,
output wire bios_loader_waitrequest,
input wire [ 3:0] bios_loader_byteenable,
// output driver_sd_avs
output wire [ 1:0] driver_sd_avs_address,
output wire driver_sd_avs_read,
input wire [31:0] driver_sd_avs_readdata,
output wire driver_sd_avs_write,
output wire [31:0] driver_sd_avs_writedata
);
assign driver_sd_avs_address = (~ao486_rst) ? hdd_avalon_master_address[3:2] : bios_loader_address[3:2];
assign driver_sd_avs_read = (~ao486_rst) ? hdd_avalon_master_read : bios_loader_read && bios_loader_address[31:4] == 28'h0;
assign driver_sd_avs_write = (~ao486_rst) ? hdd_avalon_master_write : bios_loader_write && bios_loader_address[31:4] == 28'h0;
assign driver_sd_avs_writedata = (~ao486_rst) ? hdd_avalon_master_writedata : bios_loader_writedata;
assign hdd_avalon_master_readdata = (~ao486_rst) ? driver_sd_avs_readdata : 0;
assign hdd_avalon_master_waitrequest = 0;
always @(posedge clk_sys)
hdd_avalon_master_readdatavalid <= (~ao486_rst) ? driver_sd_avs_read : 0;
assign bios_loader_readdata = (~ao486_rst) ? 0 : driver_sd_avs_readdata;
assign bios_loader_waitrequest = 0;
endmodule
| 6.527232 |
module dq (
clk,
q,
d
);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width = 8;
parameter depth = 2;
integer i;
reg [width-1:0] delay_line[depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for (i = 1; i < depth; i = i + 1) begin
delay_line[i] <= delay_line[i-1];
end
end
assign q = delay_line[depth-1];
endmodule
| 6.77352 |
module dq (
clk,
q,
d
);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width = 8;
parameter depth = 2;
integer i;
reg [width-1:0] delay_line[depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for (i = 1; i < depth; i = i + 1) begin
delay_line[i] <= delay_line[i-1];
end
end
assign q = delay_line[depth-1];
endmodule
| 6.77352 |
module to_upper (
OUT,
IN
);
output wire [7:0] OUT;
input wire [7:0] IN;
wire isLower = (8'h61 <= IN && IN <= 8'h7a);
// if space --> Z
assign OUT = isLower ? IN - 32 : IN;
endmodule
| 8.249279 |
module alu #(
parameter BUS_OP_SIZE = 6,
parameter BUS_SIZE = 8,
parameter BUS_BIT_ENABLE = 3
) (
input i_clk,
input [BUS_BIT_ENABLE - 1 : 0] i_en,
input [BUS_SIZE - 1 : 0] i_switch,
output [BUS_SIZE - 1 : 0] o_led,
output o_carry_bit,
output o_zero_bit
);
localparam OP_ADD = 6'b100000;
localparam OP_SUB = 6'b100010;
localparam OP_AND = 6'b100100;
localparam OP_OR = 6'b100101;
localparam OP_XOR = 6'b100110;
localparam OP_SRA = 6'b000011;
localparam OP_SRL = 6'b000010;
localparam OP_NOR = 6'b100111;
reg [BUS_SIZE - 1 : 0] data_a;
reg [BUS_SIZE - 1 : 0] data_b;
reg [BUS_OP_SIZE - 1 : 0] data_operation;
reg [BUS_SIZE : 0] result; //tiene un bit extra para el carry
assign o_led = result; //7:0
assign o_carry_bit = result[BUS_SIZE];
assign o_zero_bit = ~|o_led;
always @(posedge i_clk) begin
data_a = i_en[0] == 1 ? i_switch : data_a;
data_b = i_en[1] == 1 ? i_switch : data_b;
data_operation = i_en[2] == 1 ? i_switch : data_operation;
case (data_operation)
OP_ADD: // Addition
result = {1'b0, data_a} + {1'b0, data_b};
OP_SUB: // Subtraction
result = data_a - data_b;
OP_AND: // Logical and
result = data_a & data_b;
OP_OR: // Logical or
result = data_a | data_b;
OP_XOR: // Logical xor
result = data_a ^ data_b;
OP_SRA: // SRA
result = {data_a[0], data_a[BUS_SIZE-1], data_a[BUS_SIZE-1 : 1]};
OP_SRL: // SRL
result = {data_a[0], data_a >> 1};
OP_NOR: // Logical nor
result = ~(data_a | data_b);
default: result = data_a + data_b;
endcase
end
endmodule
| 6.7799 |
module tp84_lpf (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 220; //Sample at 49.152/220 = 223418Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.045425748, 0.045425748
//1.0000000, -0.90914850
reg signed [17:0] A2;
reg signed [17:0] B2;
reg signed [17:0] B1;
wire signed [15:0] audio_post_lpf1;
always @(*) begin
A2 = -18'd18211;
B1 = 18'd7278;
B2 = 18'd7278;
end
iir_1st_order lpf6db (
.clk(clk),
.reset(reset),
.div(div),
.A2(A2),
.B1(B1),
.B2(B2),
.in(in),
.out(audio_post_lpf1)
);
assign out = audio_post_lpf1;
endmodule
| 7.566268 |
module tp84_lpf_heavy (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 256; //Sample at 49.152/64 = 192000Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.0050118701, 0.0050118701
//1.0000000, -0.98997626
reg signed [17:0] A2;
reg signed [17:0] B2;
reg signed [17:0] B1;
wire signed [15:0] audio_post_lpf1;
always @(*) begin
A2 = -18'd32440;
B1 = 18'd164;
B2 = 18'd164;
end
iir_1st_order lpf6db (
.clk(clk),
.reset(reset),
.div(div),
.A2(A2),
.B1(B1),
.B2(B2),
.in(in),
.out(audio_post_lpf1)
);
assign out = audio_post_lpf1;
endmodule
| 7.660623 |
module tp84_lpf_light (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 256; //Sample at 49.152/256 = 192000Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.045425748, 0.045425748
//1.0000000, -0.90914850
reg signed [17:0] A2;
reg signed [17:0] B2;
reg signed [17:0] B1;
wire signed [15:0] audio_post_lpf1;
always @(*) begin
A2 = -18'd29791;
B1 = 18'd1488;
B2 = 18'd1488;
end
iir_1st_order lpf6db (
.clk(clk),
.reset(reset),
.div(div),
.A2(A2),
.B1(B1),
.B2(B2),
.in(in),
.out(audio_post_lpf1)
);
assign out = audio_post_lpf1;
endmodule
| 7.391008 |
module tp84_lpf_medium (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 256; //Sample at 49.152/64 = 192000Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.0055103045, 0.0055103045
//1.0000000, -0.98897939
reg signed [17:0] A2;
reg signed [17:0] B2;
reg signed [17:0] B1;
wire signed [15:0] audio_post_lpf1;
always @(*) begin
A2 = -18'd32406;
B1 = 18'd181;
B2 = 18'd181;
end
iir_1st_order lpf6db (
.clk(clk),
.reset(reset),
.div(div),
.A2(A2),
.B1(B1),
.B2(B2),
.in(in),
.out(audio_post_lpf1)
);
assign out = audio_post_lpf1;
endmodule
| 7.458026 |
module TPA (
clk,
reset_n,
SCL,
SDA,
cfg_req,
cfg_rdy,
cfg_cmd,
cfg_addr,
cfg_wdata,
cfg_rdata
);
input clk;
input reset_n;
// Two-Wire Protocol slave interface
input SCL;
inout SDA;
// Register Protocal Master interface
input cfg_req;
output cfg_rdy;
input cfg_cmd;
input [7:0] cfg_addr;
input [15:0] cfg_wdata;
output [15:0] cfg_rdata;
reg [15:0] Register_Spaces[0:255];
reg cfg_rdy;
reg [15:0] cfg_rdata;
localparam Idle = 4'd0;
localparam RIM_Write = 4'd1;
localparam RIM_Read = 4'd2;
localparam TWM_Write_A = 4'd4;
localparam TWM_Write_D = 4'd5;
localparam TWM_Read_A = 4'd6;
localparam TWM_Read_D_0 = 4'd7;
localparam TWM_Read_D_1 = 4'd8;
localparam TWM_Read_D_2 = 4'd9;
reg SDA_reg;
reg [7:0] TWM_A;
reg [3:0] cnt;
reg [3:0] cur_state, next_state;
assign SDA = (cur_state >= 4'd7 && cur_state <= 4'd9) ? SDA_reg : 1'bz;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
cfg_rdy <= 0;
cfg_rdata <= 16'hzz;
cnt <= 4'd0;
TWM_A <= 8'hzz;
SDA_reg <= 1'bz;
end else begin
case (cur_state)
Idle: begin
cfg_rdy <= 0;
cfg_rdata <= 16'hzz;
cnt <= 4'd0;
TWM_A <= 8'hzz;
SDA_reg <= 1'bz;
end
RIM_Write: begin
cfg_rdy <= 1;
Register_Spaces[cfg_addr] <= cfg_wdata;
end
RIM_Read: begin
cfg_rdy <= 1;
cfg_rdata <= Register_Spaces[cfg_addr];
end
TWM_Write_A: begin
cfg_rdy <= 0;
cnt <= (cnt == 4'd7) ? 4'd0 : cnt + 4'd1;
TWM_A[cnt] <= SDA;
end
TWM_Write_D: begin
cnt <= (cnt == 4'd15) ? 4'd0 : cnt + 4'd1;
Register_Spaces[TWM_A][cnt] <= SDA;
end
TWM_Read_A: begin
cfg_rdy <= 0;
cnt <= (cnt == 4'd7) ? 4'd0 : cnt + 4'd1;
TWM_A[cnt] <= SDA;
end
TWM_Read_D_0: begin
cnt <= (cnt == 4'd2) ? 4'd0 : cnt + 4'd1;
if (cnt == 4'd1) SDA_reg <= 1;
else if (cnt == 4'd2) SDA_reg <= 0;
else SDA_reg <= 1'bz;
end
TWM_Read_D_1: begin
cnt <= (cnt == 4'd15) ? 4'd0 : cnt + 4'd1;
SDA_reg <= Register_Spaces[TWM_A][cnt];
end
TWM_Read_D_2: begin
SDA_reg <= 1;
end
default: begin // 3 : do nothing
end
endcase
end
end
/* FSM */
always @(*) begin
next_state = cur_state;
case (cur_state)
4'd0: begin
if (cfg_req) next_state = (cfg_cmd) ? 1 : 2;
else if (!SDA) next_state = 3;
end
4'd3: next_state = (SDA) ? 4 : 6;
4'd4: if (cnt == 4'd7) next_state = 5;
4'd5: if (cnt == 4'd15) next_state = 0;
4'd6: if (cnt == 4'd7) next_state = 7;
4'd7: if (cnt == 4'd2) next_state = 8;
4'd8: if (cnt == 4'd15) next_state = 9;
4'd9: next_state = 0;
default: begin // 1 and 2
if (!SDA) next_state = 3;
else if (cfg_rdy) next_state = 0;
end
endcase
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) cur_state <= 4'd0;
else cur_state <= next_state;
end
endmodule
| 7.249862 |
module TPA (
clk,
reset_n,
SCL,
SDA,
cfg_req,
cfg_rdy,
cfg_cmd,
cfg_addr,
cfg_wdata,
cfg_rdata
);
input clk;
input reset_n;
// Two-Wire Protocol slave interface
input SCL;
inout SDA;
// Register Protocal Master interface
input cfg_req;
output cfg_rdy;
input cfg_cmd;
input [7:0] cfg_addr;
input [15:0] cfg_wdata;
output [15:0] cfg_rdata;
reg [15:0] Register_Spaces[0:255];
reg cfg_rdy;
reg [15:0] cfg_rdata;
localparam Idle = 4'd0;
localparam RIM_Write = 4'd1;
localparam RIM_Read = 4'd2;
localparam TWM_Write_A = 4'd4;
localparam TWM_Write_D = 4'd5;
localparam TWM_Read_A = 4'd6;
localparam TWM_Read_D_0 = 4'd7;
localparam TWM_Read_D_1 = 4'd8;
localparam TWM_Read_D_2 = 4'd9;
reg SDA_reg;
reg [7:0] TWM_A;
reg [3:0] cnt;
reg [3:0] cur_state, next_state;
assign SDA = (cur_state >= 4'd7 && cur_state <= 4'd9) ? SDA_reg : 1'bz;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
cfg_rdy <= 0;
cfg_rdata <= 16'hzz;
cnt <= 4'd0;
TWM_A <= 8'hzz;
SDA_reg <= 1'bz;
end else begin
case (cur_state)
Idle: begin
cfg_rdy <= 0;
cfg_rdata <= 16'hzz;
cnt <= 4'd0;
TWM_A <= 8'hzz;
SDA_reg <= 1'bz;
end
RIM_Write: begin
cfg_rdy <= 1;
Register_Spaces[cfg_addr] <= cfg_wdata;
end
RIM_Read: begin
cfg_rdy <= 1;
cfg_rdata <= Register_Spaces[cfg_addr];
end
TWM_Write_A: begin
cfg_rdy <= 0;
cnt <= (cnt == 4'd7) ? 4'd0 : cnt + 4'd1;
TWM_A[cnt] <= SDA;
end
TWM_Write_D: begin
cnt <= (cnt == 4'd15) ? 4'd0 : cnt + 4'd1;
Register_Spaces[TWM_A][cnt] <= SDA;
end
TWM_Read_A: begin
cfg_rdy <= 0;
cnt <= (cnt == 4'd7) ? 4'd0 : cnt + 4'd1;
TWM_A[cnt] <= SDA;
end
TWM_Read_D_0: begin
cnt <= (cnt == 4'd2) ? 4'd0 : cnt + 4'd1;
if (cnt == 4'd1) SDA_reg <= 1;
else if (cnt == 4'd2) SDA_reg <= 0;
else SDA_reg <= 1'bz;
end
TWM_Read_D_1: begin
cnt <= (cnt == 4'd15) ? 4'd0 : cnt + 4'd1;
SDA_reg <= Register_Spaces[TWM_A][cnt];
end
TWM_Read_D_2: begin
SDA_reg <= 1;
end
default: begin // 3 : do nothing
end
endcase
end
end
/* FSM */
always @(*) begin
next_state = cur_state;
case (cur_state)
4'd0: begin
if (cfg_req) next_state = (cfg_cmd) ? 1 : 2;
else if (!SDA) next_state = 3;
end
4'd3: next_state = (SDA) ? 4 : 6;
4'd4: if (cnt == 4'd7) next_state = 5;
4'd5: if (cnt == 4'd15) next_state = 0;
4'd6: if (cnt == 4'd7) next_state = 7;
4'd7: if (cnt == 4'd2) next_state = 8;
4'd8: if (cnt == 4'd15) next_state = 9;
4'd9: next_state = 0;
default: begin // 1 and 2
if (!SDA) next_state = 3;
else if (cfg_rdy) next_state = 0;
end
endcase
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) cur_state <= 4'd0;
else cur_state <= next_state;
end
endmodule
| 7.249862 |
module tPC;
reg reset, count, outEn;
wire [15:0] curAddress;
PC programCounter (
reset,
count,
outEn,
curAddress
);
initial begin
reset = 1'b1;
#5 reset = 1'b0;
count = 1'b1;
#5 count = 1'b0;
outEn = 1'b1;
#5 outEn = 1'b0;
count = 1'b1;
#5 outEn = 1'b1;
#5 count = 1'b0;
end
endmodule
| 6.822896 |
module tpg_tb;
parameter BITS = 3;
reg clk;
reg rst;
wire END;
wire [BITS-1:0] op;
tpg #(
.BITS(BITS)
) TPG (
.clk(clk),
.rst(rst),
.END(END),
.TEST_PATTERN(op)
);
initial clk <= 0;
always #5 clk <= ~clk;
always begin
$monitor("Time = %.0f, Pattern = %b, RST = %b, END_F = %b", $time, op, rst, END);
#3 rst <= 1;
#3 rst <= 0;
#30 rst <= 1;
#1 rst <= 0;
#120 $finish;
end
endmodule
| 6.709645 |
module name to match the file name
// =============================================================================
`ifndef TPIO_V
`define TPIO_V
`include "system_conf.v"
module tpio #(parameter DATA_WIDTH = 16,
parameter IRQ_MODE = 1,
parameter LEVEL = 0,
parameter EDGE = 1,
parameter POSE_EDGE_IRQ = 1,
parameter NEGE_EDGE_IRQ = 0,
parameter EITHER_EDGE_IRQ = 0)
(RST_I,
CLK_I,
DAT_I,
DAT_O,
PIO_IO,
IRQ_O,
PIO_TRI_WR_EN,
PIO_TRI_RE_EN,
PIO_DATA_RE_EN,
PIO_DATA_WR_EN,
IRQ_MASK_RE_EN,
IRQ_MASK_WR_EN,
EDGE_CAP_WR_EN);
parameter UDLY = 1;//user delay
input RST_I;
input CLK_I;
input DAT_I;
input PIO_TRI_RE_EN;
input PIO_TRI_WR_EN;
input PIO_DATA_RE_EN;
input PIO_DATA_WR_EN;
output DAT_O;
input IRQ_MASK_RE_EN;
input IRQ_MASK_WR_EN;
input EDGE_CAP_WR_EN;
output IRQ_O;
inout PIO_IO;
wire PIO_IO_I;
wire DAT_O;
wire IRQ_O;
reg PIO_DATA_O;
reg PIO_DATA_I;
reg PIO_TRI;
reg IRQ_MASK;
reg IRQ_TEMP;
reg EDGE_CAPTURE;
reg PIO_DATA_DLY;
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
PIO_TRI <= #UDLY 0;
else if (PIO_TRI_WR_EN)
PIO_TRI <= #UDLY DAT_I;
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
PIO_DATA_O <= #UDLY 0;
else if (PIO_DATA_WR_EN)
PIO_DATA_O <= #UDLY DAT_I;
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
PIO_DATA_I <= #UDLY 0;
else if (PIO_DATA_RE_EN)
PIO_DATA_I <= #UDLY PIO_IO_I;
BB tpio_inst(.I(PIO_DATA_O), .T(~PIO_TRI), .O(PIO_IO_I), .B(PIO_IO));
assign DAT_O = PIO_TRI_RE_EN ? PIO_TRI :
IRQ_MASK_RE_EN ? IRQ_MASK : PIO_DATA_I;
//IRQ_MODE
generate
if (IRQ_MODE == 1) begin
//CONFIG THE IRQ_MASK REG.
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
IRQ_MASK <= #UDLY 0;
else if (IRQ_MASK_WR_EN)
IRQ_MASK <= #UDLY DAT_I;
end
endgenerate
generate
if (IRQ_MODE == 1 && LEVEL == 1) begin
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
IRQ_TEMP <= #UDLY 0;
else
IRQ_TEMP <= #UDLY PIO_IO_I & IRQ_MASK & ~PIO_TRI;//bit-and
assign IRQ_O = IRQ_TEMP;
end
else if (IRQ_MODE == 1 && EDGE == 1) begin
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
PIO_DATA_DLY <= #UDLY 0;
else
PIO_DATA_DLY <= PIO_IO_I;
always @(posedge CLK_I or posedge RST_I)
if (RST_I)
EDGE_CAPTURE <= #UDLY 0;
else if ((PIO_IO_I & ~PIO_DATA_DLY & ~PIO_TRI) && POSE_EDGE_IRQ == 1)
EDGE_CAPTURE <= #UDLY PIO_IO_I & ~PIO_DATA_DLY;
else if ((~PIO_IO_I & PIO_DATA_DLY & ~PIO_TRI) && NEGE_EDGE_IRQ == 1)
EDGE_CAPTURE <= #UDLY ~PIO_IO_I & PIO_DATA_DLY;
else if ((PIO_IO_I & ~PIO_DATA_DLY & ~PIO_TRI) && EITHER_EDGE_IRQ == 1)
EDGE_CAPTURE <= #UDLY PIO_IO_I & ~PIO_DATA_DLY;
else if ((~PIO_IO_I & PIO_DATA_DLY & ~PIO_TRI) && EITHER_EDGE_IRQ == 1)
EDGE_CAPTURE <= #UDLY ~PIO_IO_I & PIO_DATA_DLY;
else if ( (~IRQ_MASK) & DAT_I & IRQ_MASK_WR_EN )
// interrupt mask's being set, so clear edge-capture
EDGE_CAPTURE <= #UDLY 0;
else if ( EDGE_CAP_WR_EN )
// user's writing to the edge-register, so update edge-capture
// register
EDGE_CAPTURE <= #UDLY EDGE_CAPTURE & DAT_I;
assign IRQ_O = |(EDGE_CAPTURE & IRQ_MASK);
end
else // IRQ_MODE ==0
assign IRQ_O = 0;
endgenerate
endmodule
| 7.325849 |
module tPortIn #(
`include "noc_parameter.vh"
) (
// Header: burst(1)+bsel+srcModId+srcChipId+trgX+trgY+trgZ+trgModId+trgChipId
// Payload: mode+address+data
//Interface to the remote router
input wire [ NOC_HEADER_SIZE-1:0] header_i,
input wire [NOC_PAYLOAD_SIZE-1:0] payload_i,
output wire rdreq_o,
input wire flit_avail_q_i,
//Interface to the own router
output wire [ NOC_HEADER_SIZE-1:0] BEheader_o,
output wire [NOC_PAYLOAD_SIZE-1:0] BEpayload_o,
output wire BEflitAvail_o,
input wire BEflitReq_i
);
assign rdreq_o = BEflitReq_i;
assign BEflitAvail_o = !flit_avail_q_i;
assign BEheader_o = header_i;
assign BEpayload_o = payload_i;
endmodule
| 6.878118 |
module tPortOut #(
`include "noc_parameter.vh"
) (
// Header: burst(1)+bsel+srcModId+srcChipId+trgX+trgY+trgZ+trgModId+trgChipId
// Payload: mode+address+data
//Interface to the remote router
output wire [ NOC_HEADER_SIZE-1:0] header_o,
output wire [NOC_PAYLOAD_SIZE-1:0] payload_o,
output wire wrreq_o,
input wire BEstall_i,
//Interface to the own router (to Transmitter)
input wire [ NOC_HEADER_SIZE-1:0] flitHeader_i,
input wire [NOC_PAYLOAD_SIZE-1:0] flitPayload_i,
input wire flitWrreq_i,
output wire flitStall_o
);
assign header_o = flitHeader_i;
assign payload_o = flitPayload_i;
assign wrreq_o = flitWrreq_i;
assign flitStall_o = BEstall_i;
endmodule
| 7.315445 |
module tpram_inf_be_512x16 (
input wire clock,
input wire [ 9-1:0] wraddress,
input wire wren,
input wire [ 2-1:0] byteena_a,
input wire [16-1:0] data,
input wire [ 9-1:0] rdaddress,
output reg [16-1:0] q
);
// memory
reg [8-1:0] mem0[0:512-1];
reg [8-1:0] mem1[0:512-1];
// read / write
always @(posedge clock) begin
if (wren && byteena_a[0]) mem0[wraddress] <= #1 data[8-1:0];
if (wren && byteena_a[1]) mem1[wraddress] <= #1 data[16-1:8];
q[8-1:0] <= #1 mem0[rdaddress];
q[16-1:8] <= #1 mem1[rdaddress];
end
endmodule
| 6.856212 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1;
input clk;
`ifdef SIMULATION
reg [ 7:0] ram[((1<<`AWIDTH)-1):0];
reg [31:0] i;
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q0[i*`DWIDTH+:`DWIDTH] <= ram[addr0+i];
end
end
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q1[i*`DWIDTH+:`DWIDTH] <= ram[addr1+i];
end
end
`else
//BRAMs available in VTR FPGA architectures have one bit write-enables.
//So let's combine multiple bits into 1. We don't have a usecase of
//writing/not-writing only parts of the word anyway.
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_accum,
output reg done_tpu
);
reg [3:0] state;
`define STATE_INIT 4'b0000
`define STATE_MATMUL 4'b0001
`define STATE_NORM 4'b0010
`define STATE_POOL 4'b0011
`define STATE_ACTIVATION 4'b0100
`define STATE_DONE 4'b0101
//////////////////////////////////////////////////////
// Assumption: We will always run matmul first. That is, matmul is not optional.
// The other blocks - norm, act, pool - are optional.
// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation
//////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= `STATE_INIT;
start_mat_mul <= 1'b0;
done_tpu <= 1'b0;
end else begin
case (state)
`STATE_INIT: begin
if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin
if (enable_matmul == 1'b1) begin
start_mat_mul <= 1'b1;
state <= `STATE_MATMUL;
end
end
end
//start_mat_mul is kinda used as a reset in some logic
//inside the matmul unit. So, we can't make it 0 right away after
//asserting it.
`STATE_MATMUL: begin
if (done_mat_mul == 1'b1) begin
start_mat_mul <= 1'b0;
if (save_output_to_accum) begin
state <= `STATE_DONE;
end else if (enable_norm) begin
state <= `STATE_NORM;
end else if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end else begin
start_mat_mul <= 1'b1;
end
end
`STATE_NORM: begin
if (done_norm == 1'b1) begin
if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_POOL: begin
if (done_pool == 1'b1) begin
if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_ACTIVATION: begin
if (done_activation == 1'b1) begin
state <= `STATE_DONE;
end
end
`STATE_DONE: begin
//We need to write start_tpu to 0 in the CFG block to get out of this state
if (start_tpu == 1'b0) begin
state <= `STATE_INIT;
done_tpu <= 0;
end else begin
done_tpu <= 1;
end
end
endcase
end
end
endmodule
| 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,
input reset
);
reg in_data_available_flopped;
reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped;
reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp;
reg done_pool_temp;
reg out_data_available_temp;
reg [31:0] i, j;
reg [31:0] cycle_count;
always @(posedge clk) begin
if (reset || ~enable_pool || ~in_data_available) begin
out_data_temp <= 0;
done_pool_temp <= 0;
out_data_available_temp <= 0;
cycle_count <= 0;
in_data_available_flopped <= in_data_available;
inp_data_flopped <= inp_data;
end else if (in_data_available) begin
cycle_count = cycle_count + 1;
out_data_available_temp <= 1;
case (pool_window_size)
1: begin
out_data_temp <= inp_data;
end
2: begin
for (i = 0; i < `DESIGN_SIZE / 2; i = i + 8) begin
out_data_temp[i+:8] <= (inp_data[i*2+:8] + inp_data[i*2+8+:8]) >> 1;
end
end
4: begin
for (i = 0; i < `DESIGN_SIZE / 4; i = i + 8) begin
//TODO: If 3 adders are the critical path, break into 2 cycles
out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2;
end
end
endcase
if (cycle_count == `DESIGN_SIZE) begin
done_pool_temp <= 1'b1;
end
end
end
assign out_data = enable_pool ? out_data_temp : inp_data_flopped;
assign out_data_available = enable_pool ? out_data_available_temp : in_data_available_flopped;
assign done_pool = enable_pool ? done_pool_temp : 1'b1;
//Adding a dummy signal to use validity_mask input, to make ODIN happy
wire [`MASK_WIDTH-1:0] dummy;
assign dummy = validity_mask;
endmodule
| 6.865188 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1;
input clk;
`ifdef SIMULATION
reg [ 7:0] ram[((1<<`AWIDTH)-1):0];
reg [31:0] i;
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q0[i*`DWIDTH+:`DWIDTH] <= ram[addr0+i];
end
end
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q1[i*`DWIDTH+:`DWIDTH] <= ram[addr1+i];
end
end
`else
//BRAMs available in VTR FPGA architectures have one bit write-enables.
//So let's combine multiple bits into 1. We don't have a usecase of
//writing/not-writing only parts of the word anyway.
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_accum,
output reg done_tpu
);
reg [3:0] state;
`define STATE_INIT 4'b0000
`define STATE_MATMUL 4'b0001
`define STATE_NORM 4'b0010
`define STATE_POOL 4'b0011
`define STATE_ACTIVATION 4'b0100
`define STATE_DONE 4'b0101
//////////////////////////////////////////////////////
// Assumption: We will always run matmul first. That is, matmul is not optional.
// The other blocks - norm, act, pool - are optional.
// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation
//////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= `STATE_INIT;
start_mat_mul <= 1'b0;
done_tpu <= 1'b0;
end else begin
case (state)
`STATE_INIT: begin
if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin
if (enable_matmul == 1'b1) begin
start_mat_mul <= 1'b1;
state <= `STATE_MATMUL;
end
end
end
//start_mat_mul is kinda used as a reset in some logic
//inside the matmul unit. So, we can't make it 0 right away after
//asserting it.
`STATE_MATMUL: begin
if (done_mat_mul == 1'b1) begin
start_mat_mul <= 1'b0;
if (save_output_to_accum) begin
state <= `STATE_DONE;
end else if (enable_norm) begin
state <= `STATE_NORM;
end else if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end else begin
start_mat_mul <= 1'b1;
end
end
`STATE_NORM: begin
if (done_norm == 1'b1) begin
if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_POOL: begin
if (done_pool == 1'b1) begin
if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_ACTIVATION: begin
if (done_activation == 1'b1) begin
state <= `STATE_DONE;
end
end
`STATE_DONE: begin
//We need to write start_tpu to 0 in the CFG block to get out of this state
if (start_tpu == 1'b0) begin
state <= `STATE_INIT;
done_tpu <= 0;
end else begin
done_tpu <= 1;
end
end
endcase
end
end
endmodule
| 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,
input reset
);
reg in_data_available_flopped;
reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped;
reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp;
reg done_pool_temp;
reg out_data_available_temp;
reg [31:0] i, j;
reg [31:0] cycle_count;
always @(posedge clk) begin
if (reset || ~enable_pool || ~in_data_available) begin
out_data_temp <= 0;
done_pool_temp <= 0;
out_data_available_temp <= 0;
cycle_count <= 0;
in_data_available_flopped <= in_data_available;
inp_data_flopped <= inp_data;
end else if (in_data_available) begin
cycle_count = cycle_count + 1;
out_data_available_temp <= 1;
case (pool_window_size)
1: begin
out_data_temp <= inp_data;
end
2: begin
for (i = 0; i < `DESIGN_SIZE / 2; i = i + 8) begin
out_data_temp[i+:8] <= (inp_data[i*2+:8] + inp_data[i*2+8+:8]) >> 1;
end
end
4: begin
for (i = 0; i < `DESIGN_SIZE / 4; i = i + 8) begin
//TODO: If 3 adders are the critical path, break into 2 cycles
out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2;
end
end
endcase
if (cycle_count == `DESIGN_SIZE) begin
done_pool_temp <= 1'b1;
end
end
end
assign out_data = enable_pool ? out_data_temp : inp_data_flopped;
assign out_data_available = enable_pool ? out_data_available_temp : in_data_available_flopped;
assign done_pool = enable_pool ? done_pool_temp : 1'b1;
//Adding a dummy signal to use validity_mask input, to make ODIN happy
wire [`MASK_WIDTH-1:0] dummy;
assign dummy = validity_mask;
endmodule
| 6.865188 |
module max_in_10 (
input [10 * 8 - 1:0] data_in,
output reg [7:0] data_max,
output [3:0] oIndex
);
reg [3:0] cnt;
reg [3:0] index;
assign oIndex = 9 - index;
always @(*) begin
data_max = data_in[7:0];
index = 0;
for (cnt = 0; cnt < 10; cnt = cnt + 1) begin
if (data_max == 8'b10000000) begin
data_max = 8'b10000000;
end else if (data_in[cnt*8+7-:8] == 8'b10000000) begin
data_max = 8'b10000000;
index = cnt;
end else if (data_max[7] ^ data_in[cnt*8+7] == 1) begin
if (data_max[7] == 1) begin
data_max = data_in[cnt*8+7-:8];
index = cnt;
end else data_max = data_max;
end else if (data_in[cnt*8+6-:7] > data_max[6:0]) begin
if (data_max[7] == 0) begin
data_max = data_in[cnt*8+7-:8];
index = cnt;
end
end else if (data_max[7] == 1) begin
data_max = data_in[cnt*8+7-:8];
index = cnt;
end
end
end
endmodule
| 7.140602 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module norm (
input enable_norm,
input [`DWIDTH-1:0] mean,
input [`DWIDTH-1:0] inv_var,
input in_data_available,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_norm,
input clk,
input reset
);
reg out_data_available_internal;
wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal;
reg [`DESIGN_SIZE*`DWIDTH-1:0] mean_applied_data;
reg [`DESIGN_SIZE*`DWIDTH-1:0] variance_applied_data;
reg done_norm_internal;
reg norm_in_progress;
//Muxing logic to handle the case when this block is disabled
assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available;
assign out_data = (enable_norm) ? out_data_internal : inp_data;
assign done_norm = (enable_norm) ? done_norm_internal : 1'b1;
//inp_data will have multiple elements in it. the number of elements is the same as size of the matmul.
//on each clock edge, if in_data_available is 1, then we will normalize the inputs.
//the code uses the funky part-select syntax. example:
//wire [7:0] byteN = word[byte_num*8 +: 8];
//byte_num*8 is the starting point. 8 is the width is the part-select (has to be constant).in_data_available
//+: indicates the part-select increases from the starting point
//-: indicates the part-select decreases from the starting point
//another example:
//loc = 3;
//PA[loc -:4] = PA[loc+1 +:4]; // equivalent to PA[3:0] = PA[7:4];
integer cycle_count;
integer i;
always @(posedge clk) begin
if ((reset || ~enable_norm)) begin
mean_applied_data <= 0;
variance_applied_data <= 0;
out_data_available_internal <= 0;
cycle_count <= 0;
done_norm_internal <= 0;
norm_in_progress <= 0;
end else if (in_data_available || norm_in_progress) begin
cycle_count = cycle_count + 1;
//Let's apply mean and variance as the input data comes in.
//We have a pipeline here. First stage does the add (to apply the mean)
//and second stage does the multiplication (to apply the variance).
//Note: the following loop is not a loop across multiple columns of data.
//This loop will run in 2 cycle on the same column of data that comes into
//this module in 1 clock.
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (validity_mask[i] == 1'b1) begin
mean_applied_data[i*`DWIDTH+:`DWIDTH] <= (inp_data[i*`DWIDTH+:`DWIDTH] - mean);
variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH] * inv_var);
end else begin
mean_applied_data[i*`DWIDTH+:`DWIDTH] <= (inp_data[i*`DWIDTH+:`DWIDTH]);
variance_applied_data[i*`DWIDTH+:`DWIDTH] <= (mean_applied_data[i*`DWIDTH+:`DWIDTH]);
end
end
//Out data is available starting with the second clock cycle because
//in the first cycle, we only apply the mean.
if (cycle_count == 2) begin
out_data_available_internal <= 1;
end
//When we've normalized values N times, where N is the matmul
//size, that means we're done. But there is one additional cycle
//that is taken in the beginning (when we are applying the mean to the first
//column of data). We can call this the Initiation Interval of the pipeline.
//So, for a 4x4 matmul, this block takes 5 cycles.
if (cycle_count == (`DESIGN_SIZE + 1)) begin
done_norm_internal <= 1'b1;
norm_in_progress <= 0;
end else begin
norm_in_progress <= 1;
end
end else begin
mean_applied_data <= 0;
variance_applied_data <= 0;
out_data_available_internal <= 0;
cycle_count <= 0;
done_norm_internal <= 0;
norm_in_progress <= 0;
end
end
assign out_data_internal = variance_applied_data;
endmodule
| 7.667513 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1;
input clk;
`ifdef SIMULATION
reg [7:0] ram[((1<<`AWIDTH)-1):0];
integer i;
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q0[i*`DWIDTH+:`DWIDTH] <= ram[addr0+i];
end
end
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q1[i*`DWIDTH+:`DWIDTH] <= ram[addr1+i];
end
end
`else
//BRAMs available in VTR FPGA architectures have one bit write-enables.
//So let's combine multiple bits into 1. We don't have a usecase of
//writing/not-writing only parts of the word anyway.
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_accum,
output reg done_tpu
);
reg [3:0] state;
`define STATE_INIT 4'b0000
`define STATE_MATMUL 4'b0001
`define STATE_NORM 4'b0010
`define STATE_POOL 4'b0011
`define STATE_ACTIVATION 4'b0100
`define STATE_DONE 4'b0101
//////////////////////////////////////////////////////
// Assumption: We will always run matmul first. That is, matmul is not optional.
// The other blocks - norm, act, pool - are optional.
// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation
//////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= `STATE_INIT;
start_mat_mul <= 1'b0;
done_tpu <= 1'b0;
end else begin
case (state)
`STATE_INIT: begin
if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin
if (enable_matmul == 1'b1) begin
start_mat_mul <= 1'b1;
state <= `STATE_MATMUL;
end
end
end
//start_mat_mul is kinda used as a reset in some logic
//inside the matmul unit. So, we can't make it 0 right away after
//asserting it.
`STATE_MATMUL: begin
if (done_mat_mul == 1'b1) begin
start_mat_mul <= 1'b0;
if (save_output_to_accum) begin
state <= `STATE_DONE;
end else if (enable_norm) begin
state <= `STATE_NORM;
end else if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end else begin
start_mat_mul <= 1'b1;
end
end
`STATE_NORM: begin
if (done_norm == 1'b1) begin
if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_POOL: begin
if (done_pool == 1'b1) begin
if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_ACTIVATION: begin
if (done_activation == 1'b1) begin
state <= `STATE_DONE;
end
end
`STATE_DONE: begin
//We need to write start_tpu to 0 in the CFG block to get out of this state
if (start_tpu == 1'b0) begin
state <= `STATE_INIT;
done_tpu <= 0;
end else begin
done_tpu <= 1;
end
end
endcase
end
end
endmodule
| 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,
input reset
);
reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp;
reg done_pool_temp;
reg out_data_available_temp;
integer i, j;
integer cycle_count;
always @(posedge clk) begin
if (reset || ~enable_pool || ~in_data_available) begin
out_data_temp <= 0;
done_pool_temp <= 0;
out_data_available_temp <= 0;
cycle_count <= 0;
end else if (in_data_available) begin
cycle_count = cycle_count + 1;
out_data_available_temp <= 1;
case (pool_window_size)
1: begin
out_data_temp <= inp_data;
end
2: begin
for (i = 0; i < `DESIGN_SIZE / 2; i = i + 8) begin
out_data_temp[i+:8] <= (inp_data[i*2+:8] + inp_data[i*2+8+:8]) >> 1;
end
end
4: begin
for (i = 0; i < `DESIGN_SIZE / 4; i = i + 8) begin
//TODO: If 3 adders are the critical path, break into 2 cycles
out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2;
end
end
endcase
if (cycle_count == `DESIGN_SIZE) begin
done_pool_temp <= 1'b1;
end
end
end
assign out_data = enable_pool ? out_data_temp : inp_data;
assign out_data_available = enable_pool ? out_data_available_temp : in_data_available;
assign done_pool = enable_pool ? done_pool_temp : 1'b1;
//Adding a dummy signal to use validity_mask input, to make ODIN happy
wire [`MASK_WIDTH-1:0] dummy;
assign dummy = validity_mask;
endmodule
| 6.865188 |
module ReLU(
// input [`DWIDTH-1:0] inp_data,
// output[`DWIDTH-1:0] out_data
//);
//
//assign out_data = inp_data[`DWIDTH-1] ? {`DWIDTH{1'b0}} : inp_data;
//
//endmodule
| 6.652528 |
module norm (
input enable_norm,
input [`DWIDTH-1:0] mean,
input [`DWIDTH-1:0] inv_var,
input in_data_available,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_norm,
input clk,
input reset
);
reg out_data_available_internal;
wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal;
reg [`DESIGN_SIZE*`DWIDTH-1:0] mean_applied_data;
reg [`DESIGN_SIZE*`DWIDTH-1:0] variance_applied_data;
reg done_norm_internal;
reg norm_in_progress;
//Muxing logic to handle the case when this block is disabled
assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available;
assign out_data = (enable_norm) ? out_data_internal : inp_data;
assign done_norm = (enable_norm) ? done_norm_internal : 1'b1;
//inp_data will have multiple elements in it. the number of elements is the same as size of the matmul.
//on each clock edge, if in_data_available is 1, then we will normalize the inputs.
//the code uses the funky part-select syntax. example:
//wire [7:0] byteN = word[byte_num*8 +: 8];
//byte_num*8 is the starting point. 8 is the width is the part-select (has to be constant).in_data_available
//+: indicates the part-select increases from the starting point
//-: indicates the part-select decreases from the starting point
//another example:
//loc = 3;
//PA[loc -:4] = PA[loc+1 +:4]; // equivalent to PA[3:0] = PA[7:4];
integer cycle_count;
integer i;
always @(posedge clk) begin
if ((reset || ~enable_norm)) begin
mean_applied_data <= 0;
variance_applied_data <= 0;
out_data_available_internal <= 0;
cycle_count <= 0;
done_norm_internal <= 0;
norm_in_progress <= 0;
end else if (in_data_available || norm_in_progress) begin
cycle_count = cycle_count + 1;
//Let's apply mean and variance as the input data comes in.
//We have a pipeline here. First stage does the add (to apply the mean)
//and second stage does the multiplication (to apply the variance).
//Note: the following loop is not a loop across multiple columns of data.
//This loop will run in 2 cycle on the same column of data that comes into
//this module in 1 clock.
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (validity_mask[i] == 1'b1) begin
mean_applied_data[i*`DWIDTH+:`DWIDTH] <= (inp_data[i*`DWIDTH+:`DWIDTH] - mean);
variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH] * inv_var);
end else begin
mean_applied_data[i*`DWIDTH+:`DWIDTH] <= (inp_data[i*`DWIDTH+:`DWIDTH]);
variance_applied_data[i*`DWIDTH+:`DWIDTH] <= (mean_applied_data[i*`DWIDTH+:`DWIDTH]);
end
end
//Out data is available starting with the second clock cycle because
//in the first cycle, we only apply the mean.
if (cycle_count == 2) begin
out_data_available_internal <= 1;
end
//When we've normalized values N times, where N is the matmul
//size, that means we're done. But there is one additional cycle
//that is taken in the beginning (when we are applying the mean to the first
//column of data). We can call this the Initiation Interval of the pipeline.
//So, for a 4x4 matmul, this block takes 5 cycles.
if (cycle_count == (`DESIGN_SIZE + 1)) begin
done_norm_internal <= 1'b1;
norm_in_progress <= 0;
end else begin
norm_in_progress <= 1;
end
end else begin
mean_applied_data <= 0;
variance_applied_data <= 0;
out_data_available_internal <= 0;
cycle_count <= 0;
done_norm_internal <= 0;
norm_in_progress <= 0;
end
end
assign out_data_internal = variance_applied_data;
endmodule
| 7.667513 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1;
input clk;
`ifdef SIMULATION
reg [7:0] ram[((1<<`AWIDTH)-1):0];
integer i;
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q0[i*`DWIDTH+:`DWIDTH] <= ram[addr0+i];
end
end
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q1[i*`DWIDTH+:`DWIDTH] <= ram[addr1+i];
end
end
`else
//BRAMs available in VTR FPGA architectures have one bit write-enables.
//So let's combine multiple bits into 1. We don't have a usecase of
//writing/not-writing only parts of the word anyway.
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_accum,
output reg done_tpu
);
reg [3:0] state;
`define STATE_INIT 4'b0000
`define STATE_MATMUL 4'b0001
`define STATE_NORM 4'b0010
`define STATE_POOL 4'b0011
`define STATE_ACTIVATION 4'b0100
`define STATE_DONE 4'b0101
//////////////////////////////////////////////////////
// Assumption: We will always run matmul first. That is, matmul is not optional.
// The other blocks - norm, act, pool - are optional.
// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation
//////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= `STATE_INIT;
start_mat_mul <= 1'b0;
done_tpu <= 1'b0;
end else begin
case (state)
`STATE_INIT: begin
if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin
if (enable_matmul == 1'b1) begin
start_mat_mul <= 1'b1;
state <= `STATE_MATMUL;
end
end
end
//start_mat_mul is kinda used as a reset in some logic
//inside the matmul unit. So, we can't make it 0 right away after
//asserting it.
`STATE_MATMUL: begin
if (done_mat_mul == 1'b1) begin
start_mat_mul <= 1'b0;
if (save_output_to_accum) begin
state <= `STATE_DONE;
end else if (enable_norm) begin
state <= `STATE_NORM;
end else if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end else begin
start_mat_mul <= 1'b1;
end
end
`STATE_NORM: begin
if (done_norm == 1'b1) begin
if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_POOL: begin
if (done_pool == 1'b1) begin
if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_ACTIVATION: begin
if (done_activation == 1'b1) begin
state <= `STATE_DONE;
end
end
`STATE_DONE: begin
//We need to write start_tpu to 0 in the CFG block to get out of this state
if (start_tpu == 1'b0) begin
state <= `STATE_INIT;
done_tpu <= 0;
end else begin
done_tpu <= 1;
end
end
endcase
end
end
endmodule
| 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,
input reset
);
reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp;
reg done_pool_temp;
reg out_data_available_temp;
integer i, j;
integer cycle_count;
always @(posedge clk) begin
if (reset || ~enable_pool || ~in_data_available) begin
out_data_temp <= 0;
done_pool_temp <= 0;
out_data_available_temp <= 0;
cycle_count <= 0;
end else if (in_data_available) begin
cycle_count = cycle_count + 1;
out_data_available_temp <= 1;
case (pool_window_size)
1: begin
out_data_temp <= inp_data;
end
2: begin
for (i = 0; i < `DESIGN_SIZE / 2; i = i + 8) begin
out_data_temp[i+:8] <= (inp_data[i*2+:8] + inp_data[i*2+8+:8]) >> 1;
end
end
4: begin
for (i = 0; i < `DESIGN_SIZE / 4; i = i + 8) begin
//TODO: If 3 adders are the critical path, break into 2 cycles
out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2;
end
end
endcase
if (cycle_count == `DESIGN_SIZE) begin
done_pool_temp <= 1'b1;
end
end
end
assign out_data = enable_pool ? out_data_temp : inp_data;
assign out_data_available = enable_pool ? out_data_available_temp : in_data_available;
assign done_pool = enable_pool ? done_pool_temp : 1'b1;
//Adding a dummy signal to use validity_mask input, to make ODIN happy
wire [`MASK_WIDTH-1:0] dummy;
assign dummy = validity_mask;
endmodule
| 6.865188 |
module ReLU(
// input [`DWIDTH-1:0] inp_data,
// output[`DWIDTH-1:0] out_data
//);
//
//assign out_data = inp_data[`DWIDTH-1] ? {`DWIDTH{1'b0}} : inp_data;
//
//endmodule
| 6.652528 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module norm (
input enable_norm,
input [`DWIDTH-1:0] mean,
input [`DWIDTH-1:0] inv_var,
input in_data_available,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_norm,
input clk,
input reset
);
reg out_data_available_internal;
wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal;
reg [`DESIGN_SIZE*`DWIDTH-1:0] mean_applied_data;
reg [`DESIGN_SIZE*`DWIDTH-1:0] variance_applied_data;
reg done_norm_internal;
reg norm_in_progress;
//Muxing logic to handle the case when this block is disabled
assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available;
assign out_data = (enable_norm) ? out_data_internal : inp_data;
assign done_norm = (enable_norm) ? done_norm_internal : 1'b1;
//inp_data will have multiple elements in it. the number of elements is the same as size of the matmul.
//on each clock edge, if in_data_available is 1, then we will normalize the inputs.
//the code uses the funky part-select syntax. example:
//wire [7:0] byteN = word[byte_num*8 +: 8];
//byte_num*8 is the starting point. 8 is the width is the part-select (has to be constant).in_data_available
//+: indicates the part-select increases from the starting point
//-: indicates the part-select decreases from the starting point
//another example:
//loc = 3;
//PA[loc -:4] = PA[loc+1 +:4]; // equivalent to PA[3:0] = PA[7:4];
integer cycle_count;
integer i;
always @(posedge clk) begin
if ((reset || ~enable_norm)) begin
mean_applied_data <= 0;
variance_applied_data <= 0;
out_data_available_internal <= 0;
cycle_count <= 0;
done_norm_internal <= 0;
norm_in_progress <= 0;
end else if (in_data_available || norm_in_progress) begin
cycle_count = cycle_count + 1;
//Let's apply mean and variance as the input data comes in.
//We have a pipeline here. First stage does the add (to apply the mean)
//and second stage does the multiplication (to apply the variance).
//Note: the following loop is not a loop across multiple columns of data.
//This loop will run in 2 cycle on the same column of data that comes into
//this module in 1 clock.
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (validity_mask[i] == 1'b1) begin
mean_applied_data[i*`DWIDTH+:`DWIDTH] <= (inp_data[i*`DWIDTH+:`DWIDTH] - mean);
variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH] * inv_var);
end else begin
mean_applied_data[i*`DWIDTH+:`DWIDTH] <= (inp_data[i*`DWIDTH+:`DWIDTH]);
variance_applied_data[i*`DWIDTH+:`DWIDTH] <= (mean_applied_data[i*`DWIDTH+:`DWIDTH]);
end
end
//Out data is available starting with the second clock cycle because
//in the first cycle, we only apply the mean.
if (cycle_count == 2) begin
out_data_available_internal <= 1;
end
//When we've normalized values N times, where N is the matmul
//size, that means we're done. But there is one additional cycle
//that is taken in the beginning (when we are applying the mean to the first
//column of data). We can call this the Initiation Interval of the pipeline.
//So, for a 4x4 matmul, this block takes 5 cycles.
if (cycle_count == (`DESIGN_SIZE + 1)) begin
done_norm_internal <= 1'b1;
norm_in_progress <= 0;
end else begin
norm_in_progress <= 1;
end
end else begin
mean_applied_data <= 0;
variance_applied_data <= 0;
out_data_available_internal <= 0;
cycle_count <= 0;
done_norm_internal <= 0;
norm_in_progress <= 0;
end
end
assign out_data_internal = variance_applied_data;
endmodule
| 7.667513 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1;
input clk;
`ifdef SIMULATION
reg [7:0] ram[((1<<`AWIDTH)-1):0];
integer i;
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q0[i*`DWIDTH+:`DWIDTH] <= ram[addr0+i];
end
end
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q1[i*`DWIDTH+:`DWIDTH] <= ram[addr1+i];
end
end
`else
//BRAMs available in VTR FPGA architectures have one bit write-enables.
//So let's combine multiple bits into 1. We don't have a usecase of
//writing/not-writing only parts of the word anyway.
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_accum,
output reg done_tpu
);
reg [3:0] state;
`define STATE_INIT 4'b0000
`define STATE_MATMUL 4'b0001
`define STATE_NORM 4'b0010
`define STATE_POOL 4'b0011
`define STATE_ACTIVATION 4'b0100
`define STATE_DONE 4'b0101
//////////////////////////////////////////////////////
// Assumption: We will always run matmul first. That is, matmul is not optional.
// The other blocks - norm, act, pool - are optional.
// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation
//////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= `STATE_INIT;
start_mat_mul <= 1'b0;
done_tpu <= 1'b0;
end else begin
case (state)
`STATE_INIT: begin
if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin
if (enable_matmul == 1'b1) begin
start_mat_mul <= 1'b1;
state <= `STATE_MATMUL;
end
end
end
//start_mat_mul is kinda used as a reset in some logic
//inside the matmul unit. So, we can't make it 0 right away after
//asserting it.
`STATE_MATMUL: begin
if (done_mat_mul == 1'b1) begin
start_mat_mul <= 1'b0;
if (save_output_to_accum) begin
state <= `STATE_DONE;
end else if (enable_norm) begin
state <= `STATE_NORM;
end else if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end else begin
start_mat_mul <= 1'b1;
end
end
`STATE_NORM: begin
if (done_norm == 1'b1) begin
if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_POOL: begin
if (done_pool == 1'b1) begin
if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_ACTIVATION: begin
if (done_activation == 1'b1) begin
state <= `STATE_DONE;
end
end
`STATE_DONE: begin
//We need to write start_tpu to 0 in the CFG block to get out of this state
if (start_tpu == 1'b0) begin
state <= `STATE_INIT;
done_tpu <= 0;
end else begin
done_tpu <= 1;
end
end
endcase
end
end
endmodule
| 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,
input reset
);
reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp;
reg done_pool_temp;
reg out_data_available_temp;
integer i, j;
integer cycle_count;
always @(posedge clk) begin
if (reset || ~enable_pool || ~in_data_available) begin
out_data_temp <= 0;
done_pool_temp <= 0;
out_data_available_temp <= 0;
cycle_count <= 0;
end else if (in_data_available) begin
cycle_count = cycle_count + 1;
out_data_available_temp <= 1;
case (pool_window_size)
1: begin
out_data_temp <= inp_data;
end
2: begin
for (i = 0; i < `DESIGN_SIZE / 2; i = i + 8) begin
out_data_temp[i+:8] <= (inp_data[i*2+:8] + inp_data[i*2+8+:8]) >> 1;
end
end
4: begin
for (i = 0; i < `DESIGN_SIZE / 4; i = i + 8) begin
//TODO: If 3 adders are the critical path, break into 2 cycles
out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2;
end
end
endcase
if (cycle_count == `DESIGN_SIZE) begin
done_pool_temp <= 1'b1;
end
end
end
assign out_data = enable_pool ? out_data_temp : inp_data;
assign out_data_available = enable_pool ? out_data_available_temp : in_data_available;
assign done_pool = enable_pool ? done_pool_temp : 1'b1;
//Adding a dummy signal to use validity_mask input, to make ODIN happy
wire [`MASK_WIDTH-1:0] dummy;
assign dummy = validity_mask;
endmodule
| 6.865188 |
module ReLU(
// input [`DWIDTH-1:0] inp_data,
// output[`DWIDTH-1:0] out_data
//);
//
//assign out_data = inp_data[`DWIDTH-1] ? {`DWIDTH{1'b0}} : inp_data;
//
//endmodule
| 6.652528 |
module norm (
input enable_norm,
input [`DWIDTH-1:0] mean,
input [`DWIDTH-1:0] inv_var,
input in_data_available,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_norm,
input clk,
input reset
);
reg out_data_available_internal;
wire [`DESIGN_SIZE*`DWIDTH-1:0] out_data_internal;
reg [`DESIGN_SIZE*`DWIDTH-1:0] mean_applied_data;
reg [`DESIGN_SIZE*`DWIDTH-1:0] variance_applied_data;
reg done_norm_internal;
reg norm_in_progress;
//Muxing logic to handle the case when this block is disabled
assign out_data_available = (enable_norm) ? out_data_available_internal : in_data_available;
assign out_data = (enable_norm) ? out_data_internal : inp_data;
assign done_norm = (enable_norm) ? done_norm_internal : 1'b1;
//inp_data will have multiple elements in it. the number of elements is the same as size of the matmul.
//on each clock edge, if in_data_available is 1, then we will normalize the inputs.
//the code uses the funky part-select syntax. example:
//wire [7:0] byteN = word[byte_num*8 +: 8];
//byte_num*8 is the starting point. 8 is the width is the part-select (has to be constant).in_data_available
//+: indicates the part-select increases from the starting point
//-: indicates the part-select decreases from the starting point
//another example:
//loc = 3;
//PA[loc -:4] = PA[loc+1 +:4]; // equivalent to PA[3:0] = PA[7:4];
integer cycle_count;
integer i;
always @(posedge clk) begin
if ((reset || ~enable_norm)) begin
mean_applied_data <= 0;
variance_applied_data <= 0;
out_data_available_internal <= 0;
cycle_count <= 0;
done_norm_internal <= 0;
norm_in_progress <= 0;
end else if (in_data_available || norm_in_progress) begin
cycle_count = cycle_count + 1;
//Let's apply mean and variance as the input data comes in.
//We have a pipeline here. First stage does the add (to apply the mean)
//and second stage does the multiplication (to apply the variance).
//Note: the following loop is not a loop across multiple columns of data.
//This loop will run in 2 cycle on the same column of data that comes into
//this module in 1 clock.
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (validity_mask[i] == 1'b1) begin
mean_applied_data[i*`DWIDTH+:`DWIDTH] <= (inp_data[i*`DWIDTH+:`DWIDTH] - mean);
variance_applied_data[i*`DWIDTH +: `DWIDTH] <= (mean_applied_data[i*`DWIDTH +: `DWIDTH] * inv_var);
end else begin
mean_applied_data[i*`DWIDTH+:`DWIDTH] <= (inp_data[i*`DWIDTH+:`DWIDTH]);
variance_applied_data[i*`DWIDTH+:`DWIDTH] <= (mean_applied_data[i*`DWIDTH+:`DWIDTH]);
end
end
//Out data is available starting with the second clock cycle because
//in the first cycle, we only apply the mean.
if (cycle_count == 2) begin
out_data_available_internal <= 1;
end
//When we've normalized values N times, where N is the matmul
//size, that means we're done. But there is one additional cycle
//that is taken in the beginning (when we are applying the mean to the first
//column of data). We can call this the Initiation Interval of the pipeline.
//So, for a 4x4 matmul, this block takes 5 cycles.
if (cycle_count == (`DESIGN_SIZE + 1)) begin
done_norm_internal <= 1'b1;
norm_in_progress <= 0;
end else begin
norm_in_progress <= 1;
end
end else begin
mean_applied_data <= 0;
variance_applied_data <= 0;
out_data_available_internal <= 0;
cycle_count <= 0;
done_norm_internal <= 0;
norm_in_progress <= 0;
end
end
assign out_data_internal = variance_applied_data;
endmodule
| 7.667513 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1;
input clk;
`ifdef SIMULATION
reg [7:0] ram[((1<<`AWIDTH)-1):0];
integer i;
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q0[i*`DWIDTH+:`DWIDTH] <= ram[addr0+i];
end
end
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q1[i*`DWIDTH+:`DWIDTH] <= ram[addr1+i];
end
end
`else
//BRAMs available in VTR FPGA architectures have one bit write-enables.
//So let's combine multiple bits into 1. We don't have a usecase of
//writing/not-writing only parts of the word anyway.
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_accum,
output reg done_tpu
);
reg [3:0] state;
`define STATE_INIT 4'b0000
`define STATE_MATMUL 4'b0001
`define STATE_NORM 4'b0010
`define STATE_POOL 4'b0011
`define STATE_ACTIVATION 4'b0100
`define STATE_DONE 4'b0101
//////////////////////////////////////////////////////
// Assumption: We will always run matmul first. That is, matmul is not optional.
// The other blocks - norm, act, pool - are optional.
// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation
//////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= `STATE_INIT;
start_mat_mul <= 1'b0;
done_tpu <= 1'b0;
end else begin
case (state)
`STATE_INIT: begin
if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin
if (enable_matmul == 1'b1) begin
start_mat_mul <= 1'b1;
state <= `STATE_MATMUL;
end
end
end
//start_mat_mul is kinda used as a reset in some logic
//inside the matmul unit. So, we can't make it 0 right away after
//asserting it.
`STATE_MATMUL: begin
if (done_mat_mul == 1'b1) begin
start_mat_mul <= 1'b0;
if (save_output_to_accum) begin
state <= `STATE_DONE;
end else if (enable_norm) begin
state <= `STATE_NORM;
end else if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end else begin
start_mat_mul <= 1'b1;
end
end
`STATE_NORM: begin
if (done_norm == 1'b1) begin
if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_POOL: begin
if (done_pool == 1'b1) begin
if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_ACTIVATION: begin
if (done_activation == 1'b1) begin
state <= `STATE_DONE;
end
end
`STATE_DONE: begin
//We need to write start_tpu to 0 in the CFG block to get out of this state
if (start_tpu == 1'b0) begin
state <= `STATE_INIT;
done_tpu <= 0;
end else begin
done_tpu <= 1;
end
end
endcase
end
end
endmodule
| 7.715617 |
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