code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DFF (
D,
clk,
sync_reset,
Q
);
input D; // Data input
input clk; // clock input
input sync_reset; // synchronous reset
output reg Q; // output Q
always @(negedge clk) begin
if (sync_reset == 1'b1) Q <= 1'b0;
else Q <= D;
end
endmodule
| 6.795644 |
module ratedivider (
clk,
clkout,
reset
);
input clk;
input reset;
output reg clkout;
reg [24:0] count;
always @(posedge clk) begin
if (reset) begin
if (count < 2000000) count <= count + 1;
else begin
count <= 0;
clkout <= ~clkout;
end
end else begin
clkout <= ~clkout;
end
end
endmodule
| 8.084012 |
module trsfrm (
rst,
wr,
rd,
DB,
A,
dcnt,
vdd,
indata
);
input wire rst;
input wire wr, rd;
inout wire [15:0] DB;
input wire [2:0] A;
input wire [15:0] indata;
output reg [22:0] dcnt;
output wire [15:0] vdd;
reg [15:0] Ireg0, Ireg1, Ireg2;
always @(posedge wr, negedge rst) begin
if (!rst) begin
Ireg0 <= 16'd0;
Ireg1 <= 16'd0;
Ireg2 <= 16'd0;
dcnt <= 23'd3749;
end else
case (A[1:0])
2'b00: begin
Ireg0 <= DB;
Ireg1 <= Ireg1;
Ireg2 <= Ireg2;
end
2'b01: begin
Ireg0 <= Ireg0;
Ireg1 <= DB;
Ireg2 <= Ireg2;
end
2'b10: begin
Ireg0 <= Ireg0;
Ireg1 <= Ireg1;
Ireg2 <= DB;
end
2'b11: begin
Ireg0 <= Ireg0;
Ireg1 <= Ireg1;
Ireg2 <= Ireg2;
dcnt = {Ireg1[6:0], Ireg0};
end
endcase
end
tri_gt p1 (
.OE(!rd),
.id(indata),
.od(DB)
);
assign vdd = Ireg2;
endmodule
| 6.689439 |
module true_bit;
reg [15:0] flag;
integer i, count;
initial begin
flag = 16'b0010_0010_0010_0000;
i = 0;
count = 0;
begin : block1
while (i < 16) begin
if (flag[i]) begin
$display("encountered a true bit at element no. %d", i);
count = count + 1;
//disable block1;
end
i = i + 1;
end
$display("count=%d", count);
end
end
endmodule
| 6.877277 |
module
:Version
1.0
:Modified
2015-05-01
Copyright (C) 2015 Dai Tianyu (dtysky)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://ifl.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
dtysky@outlook.com
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module True2Comp(
true,
complement);
parameter data_channel = 1;
parameter data_width = 17;
input[data_channel * data_width - 1 : 0] true;
output[data_channel * data_width - 1 : 0] complement;
genvar i;
generate
`define h (i + 1) * data_width - 1
`define l i * data_width
for (i = 0; i < data_channel; i = i + 1) begin
assign complement[`h : `l] = true[`h] == 0 ?
true[`h : `l] : {1'b1, ~true[`h - 1 : `l] + 1};
end
`undef h
`undef l
endgenerate
endmodule
| 7.135037 |
module TrueDualPortRAM #(
parameter DATA_WIDTH = 32,
parameter NUM_ENTRIES = 2048,
parameter ADDR_WIDTH = $clog2(NUM_ENTRIES)
) (
input clock,
input reset,
// PortA
input [ADDR_WIDTH-1:0] portA_addr,
output [DATA_WIDTH-1:0] portA_dout,
input portA_we,
input [DATA_WIDTH-1:0] portA_din,
// PortB
input [ADDR_WIDTH-1:0] portB_addr,
output [DATA_WIDTH-1:0] portB_dout,
input portB_we,
input [DATA_WIDTH-1:0] portB_din
);
// Xilinx True Dual Port RAM, No Change, Single Clock
xilinx_true_dual_port_no_change_1_clock_ram #(
.RAM_WIDTH (DATA_WIDTH), // Specify RAM data width
.RAM_DEPTH (NUM_ENTRIES), // Specify RAM depth (number of entries)
.RAM_PERFORMANCE("LOW_LATENCY") // Select "HIGH_PERFORMANCE" or "LOW_LATENCY"
) tdpram_inst (
.addra(portA_addr), // Port A address bus, width determined from RAM_DEPTH
.addrb(portB_addr), // Port B address bus, width determined from RAM_DEPTH
.dina(portA_din), // Port A RAM input data, width determined from RAM_WIDTH
.dinb(portB_din), // Port B RAM input data, width determined from RAM_WIDTH
.clka(clock), // Clock
.wea(portA_we), // Port A write enable
.web(portB_we), // Port B write enable
.ena(1'b1), // Port A RAM Enable, for additional power savings, disable port when not in use
.enb(1'b1), // Port B RAM Enable, for additional power savings, disable port when not in use
.rsta(reset), // Port A output reset (does not affect memory contents)
.rstb(reset), // Port B output reset (does not affect memory contents)
.regcea(1'b1), // Port A output register enable
.regceb(1'b1), // Port B output register enable
.douta(portA_dout), // Port A RAM output data, width determined from RAM_WIDTH
.doutb(portB_dout) // Port B RAM output data, width determined from RAM_WIDTH
);
endmodule
| 10.052361 |
module truedualportram_sclock_outputaclr_w60d32 (
input wire [59:0] data_a, // ram_input.datain_a
input wire [59:0] data_b, // .datain_b
input wire [ 4:0] address_a, // .address_a
input wire [ 4:0] address_b, // .address_b
input wire wren_a, // .wren_a
input wire wren_b, // .wren_b
input wire clock, // .clock
input wire rden_a, // .rden_a
input wire rden_b, // .rden_b
input wire aclr, // .aclr
output wire [59:0] q_a, // ram_output.dataout_a
output wire [59:0] q_b // .dataout_b
);
truedualportram_sclock_outputaclr_w60d32_ram_2port_191_vw5faqa ram_2port_0 (
.data_a (data_a), // ram_input.datain_a
.data_b (data_b), // .datain_b
.address_a(address_a), // .address_a
.address_b(address_b), // .address_b
.wren_a (wren_a), // .wren_a
.wren_b (wren_b), // .wren_b
.clock (clock), // .clock
.rden_a (rden_a), // .rden_a
.rden_b (rden_b), // .rden_b
.aclr (aclr), // .aclr
.q_a (q_a), // ram_output.dataout_a
.q_b (q_b) // .dataout_b
);
endmodule
| 7.196613 |
module truedualportram_sclock_outputaclr_w60d32_ram_2port_191_vw5faqa (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [4:0] address_a;
input [4:0] address_b;
input clock;
input [59:0] data_a;
input [59:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [59:0] q_a;
output [59:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [59:0] sub_wire0;
wire [59:0] sub_wire1;
wire [59:0] q_a = sub_wire0[59:0];
wire [59:0] q_b = sub_wire1[59:0];
altera_syncram altera_syncram_component (
.aclr0(aclr),
.address_a(address_a),
.address_b(address_b),
.clock0(clock),
.data_a(data_a),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(sub_wire0),
.q_b(sub_wire1),
.aclr1(1'b0),
//.address2_a (1'b1),
//.address2_b (1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
//.eccencbypass (1'b0),
//.eccencparity (8'b0),
.eccstatus()
);
//.sclr (1'b0));
defparam
altera_syncram_component.address_reg_b = "CLOCK0",
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_input_b = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.clock_enable_output_b = "BYPASS",
altera_syncram_component.indata_reg_b = "CLOCK0",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = 32,
altera_syncram_component.numwords_b = 32,
altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
altera_syncram_component.outdata_aclr_a = "CLEAR0",
//altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_aclr_b = "CLEAR0",
//altera_syncram_component.outdata_sclr_b = "NONE",
altera_syncram_component.outdata_reg_a = "CLOCK0",
altera_syncram_component.outdata_reg_b = "CLOCK0",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.widthad_a = 5,
altera_syncram_component.widthad_b = 5,
altera_syncram_component.width_a = 60,
altera_syncram_component.width_b = 60,
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.width_byteena_b = 1;
endmodule
| 7.196613 |
module truedualportram_singleclock_rdenab_outputaclr_w34d4096 (
input wire [33:0] data_a, // ram_input.datain_a
input wire [33:0] data_b, // .datain_b
input wire [11:0] address_a, // .address_a
input wire [11:0] address_b, // .address_b
input wire wren_a, // .wren_a
input wire wren_b, // .wren_b
input wire clock, // .clock
input wire rden_a, // .rden_a
input wire rden_b, // .rden_b
input wire aclr, // .aclr
output wire [33:0] q_a, // ram_output.dataout_a
output wire [33:0] q_b // .dataout_b
);
truedualportram_singleclock_rdenab_outputaclr_w34d4096_ram_2port_191_ewxmrhi ram_2port_0 (
.data_a (data_a), // ram_input.datain_a
.data_b (data_b), // .datain_b
.address_a(address_a), // .address_a
.address_b(address_b), // .address_b
.wren_a (wren_a), // .wren_a
.wren_b (wren_b), // .wren_b
.clock (clock), // .clock
.rden_a (rden_a), // .rden_a
.rden_b (rden_b), // .rden_b
.aclr (aclr), // .aclr
.q_a (q_a), // ram_output.dataout_a
.q_b (q_b) // .dataout_b
);
endmodule
| 7.196613 |
module truedualportram_singleclock_rdenab_outputaclr_w34d4096_ram_2port_191_ewxmrhi (
aclr,
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input aclr;
input [11:0] address_a;
input [11:0] address_b;
input clock;
input [33:0] data_a;
input [33:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [33:0] q_a;
output [33:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [33:0] sub_wire0;
wire [33:0] sub_wire1;
wire [33:0] q_a = sub_wire0[33:0];
wire [33:0] q_b = sub_wire1[33:0];
altera_syncram altera_syncram_component (
.aclr0(aclr),
.address_a(address_a),
.address_b(address_b),
.clock0(clock),
.data_a(data_a),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(sub_wire0),
.q_b(sub_wire1),
.aclr1(1'b0),
//.address2_a (1'b1),
//.address2_b (1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
//.eccencbypass (1'b0),
//.eccencparity (8'b0),
.eccstatus()
//.sclr (1'b0)
);
defparam altera_syncram_component.address_reg_b = "CLOCK0",
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_input_b = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.clock_enable_output_b = "BYPASS",
altera_syncram_component.indata_reg_b = "CLOCK0",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = 4096, altera_syncram_component.numwords_b = 4096,
altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
altera_syncram_component.outdata_aclr_a = "CLEAR0",
//altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_aclr_b = "CLEAR0",
//altera_syncram_component.outdata_sclr_b = "NONE",
altera_syncram_component.outdata_reg_a = "CLOCK0",
altera_syncram_component.outdata_reg_b = "CLOCK0",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.widthad_a = 12,
altera_syncram_component.widthad_b = 12,
altera_syncram_component.width_a = 34,
altera_syncram_component.width_b = 34,
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.width_byteena_b = 1;
endmodule
| 7.196613 |
module truedualportram_w163d32 (
input wire [162:0] data_a, // ram_input.datain_a
input wire [162:0] data_b, // .datain_b
input wire [ 4:0] address_a, // .address_a
input wire [ 4:0] address_b, // .address_b
input wire wren_a, // .wren_a
input wire wren_b, // .wren_b
input wire clock, // .clock
input wire rden_a, // .rden_a
input wire rden_b, // .rden_b
output wire [162:0] q_a, // ram_output.dataout_a
output wire [162:0] q_b // .dataout_b
);
truedualportram_w163d32_ram_2port_191_juicpka ram_2port_0 (
.data_a (data_a), // ram_input.datain_a
.data_b (data_b), // .datain_b
.address_a(address_a), // .address_a
.address_b(address_b), // .address_b
.wren_a (wren_a), // .wren_a
.wren_b (wren_b), // .wren_b
.clock (clock), // .clock
.rden_a (rden_a), // .rden_a
.rden_b (rden_b), // .rden_b
.q_a (q_a), // ram_output.dataout_a
.q_b (q_b) // .dataout_b
);
endmodule
| 7.196613 |
module truedualportram_w163d32_ram_2port_191_juicpka (
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b
);
input [4:0] address_a;
input [4:0] address_b;
input clock;
input [162:0] data_a;
input [162:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [162:0] q_a;
output [162:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [162:0] sub_wire0;
wire [162:0] sub_wire1;
wire [162:0] q_a = sub_wire0[162:0];
wire [162:0] q_b = sub_wire1[162:0];
altera_syncram altera_syncram_component (
.address_a(address_a),
.address_b(address_b),
.clock0(clock),
.data_a(data_a),
.data_b(data_b),
.rden_a(rden_a),
.rden_b(rden_b),
.wren_a(wren_a),
.wren_b(wren_b),
.q_a(sub_wire0),
.q_b(sub_wire1),
.aclr0(1'b0),
.aclr1(1'b0),
//.address2_a (1'b1),
//.address2_b (1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
//.eccencbypass (1'b0),
//.eccencparity (8'b0),
.eccstatus()
);
//.sclr (1'b0));
defparam
altera_syncram_component.address_reg_b = "CLOCK0",
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_input_b = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.clock_enable_output_b = "BYPASS",
altera_syncram_component.indata_reg_b = "CLOCK0",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = 32,
altera_syncram_component.numwords_b = 32,
altera_syncram_component.operation_mode = "BIDIR_DUAL_PORT",
altera_syncram_component.outdata_aclr_a = "NONE",
//altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_aclr_b = "NONE",
//altera_syncram_component.outdata_sclr_b = "NONE",
altera_syncram_component.outdata_reg_a = "CLOCK0",
altera_syncram_component.outdata_reg_b = "CLOCK0",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altera_syncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altera_syncram_component.widthad_a = 5,
altera_syncram_component.widthad_b = 5,
altera_syncram_component.width_a = 163,
altera_syncram_component.width_b = 163,
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.width_byteena_b = 1;
endmodule
| 7.196613 |
module true_dpbram #(
parameter DWIDTH = 16,
parameter AWIDTH = 12,
parameter MEM_SIZE = 3840
) (
/* Special Inputs */
input clk,
/* input for port 0 */
input [AWIDTH - 1 : 0] addr0_i,
input ce0_i,
input we0_i,
input [DWIDTH - 1 : 0] d0_i,
/* input for port 1 */
input [AWIDTH - 1 : 0] addr1_i,
input ce1_i,
input we1_i,
input [DWIDTH - 1 : 0] d1_i,
/* output for port 0 */
output reg [DWIDTH - 1 : 0] q0_o,
/* output for port 1 */
output reg [DWIDTH - 1 : 0] q1_o
);
/* Making Block Memory*/
(* ram_style = "block" *) reg [DWIDTH - 1 : 0] ram[0 : MEM_SIZE - 1];
// always block for port0
always @(posedge clk) begin
if (ce0_i) begin
if (we0_i) ram[addr0_i] <= d0_i;
else q0_o <= ram[addr0_i];
end
end
// always block for port1
always @(posedge clk) begin
if (ce1_i) begin
if (we1_i) ram[addr1_i] <= d1_i;
else q1_o <= ram[addr1_i];
end
end
endmodule
| 8.290359 |
module true_dpram#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)(
02 input [(DATA_WIDTH-1):0] data_a,
03 input [(DATA_WIDTH-1):0] data_b,
04 input [(ADDR_WIDTH-1):0] addr_b,
05 input [(ADDR_WIDTH-1):0] addr_a,
06 input we_a,
07 input we_b,
08 input clk_a,
09 input clk_b,
10 output reg [(DATA_WIDTH-1):0] q_a,
11 output reg [(DATA_WIDTH-1):0] q_b
12 );
13 reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; // Declare the RAM variable
14 always @ (posedge clk_a)
15 if (we_a)begin
16 ram[addr_a] <= data_a;
17 q_a <= data_a;
18 end else
19 q_a <= ram[addr_a];
20
21 always @ (posedge clk_b)
22 if (we_b)begin
23 ram[addr_b] <= data_b;
24 q_b <= data_b;
25 end else
26 q_b <= ram[addr_b];
27
28 endmodule
| 8.249077 |
module true_dpram_sclk (
input [9:0] data_a,
// input [7:0] data_b,
input [2:0] addr_wa,
input [2:0] addr_ra, //Añadido
// input [5:0] addr_b,
input we_a,
// input we_b,
input re_a, // Añadido
input clk,
input [3:0] state,
output reg [9:0] q_a
// output reg [7:0] q_b
);
// Declare the RAM variable
reg [9:0] ram[7:0];
// Port A
always @(posedge clk) begin
// Estado de RESET = 0001
if (state == 4'b0001) begin // Añadido
q_a <= 0;
ram[0] <= 0;
ram[1] <= 0;
ram[2] <= 0;
ram[3] <= 0;
ram[4] <= 0;
ram[5] <= 0;
ram[6] <= 0;
ram[7] <= 0;
end else begin
if (we_a) begin
ram[addr_wa] <= data_a;
// q_a <= data_a;
end
if (re_a) //Añadido
begin
q_a <= ram[addr_ra];
end else begin
q_a <= 10'b0; // Añadido
end
end
end
// Port B
// always @ (posedge clk)
// begin
// if (we_b)
// begin
// ram[addr_b] <= data_b;
// q_b <= data_b;
// end
// else
// begin
// q_b <= ram[addr_b];
// end
// end
endmodule
| 6.6614 |
module true_dp_bram #(
parameter L2_DEPTH = 8,
parameter WIDTH = 32
) (
input clk,
input we1,
input en1,
input [L2_DEPTH-1:0] addr1,
input [ WIDTH-1:0] din1,
input rst1,
input regce1,
output [ WIDTH-1:0] dout1,
input we2,
input en2,
input [L2_DEPTH-1:0] addr2,
input [ WIDTH-1:0] din2,
input rst2,
input regce2,
output [ WIDTH-1:0] dout2
);
parameter INIT_FILE = ""; // Specify name/location of RAM initialization file if using one (leave blank if not)
// <wire_or_reg> [clogb2(RAM_DEPTH-1)-1:0] addra; // Port A address bus, width determined from RAM_DEPTH
// <wire_or_reg> [clogb2(RAM_DEPTH-1)-1:0] addrb; // Port B address bus, width determined from RAM_DEPTH
// <wire_or_reg> [RAM_WIDTH-1:0] dina; // Port A RAM input data
// <wire_or_reg> [RAM_WIDTH-1:0] dinb; // Port B RAM input data
// <wire_or_reg> clka; // Port A clock
// <wire_or_reg> clkb; // Port B clock
// <wire_or_reg> wea; // Port A write enable
// <wire_or_reg> web; // Port B write enable
// <wire_or_reg> ena; // Port A RAM Enable, for additional power savings, disable port when not in use
// <wire_or_reg> enb; // Port B RAM Enable, for additional power savings, disable port when not in use
// <wire_or_reg> rsta; // Port A output reset (does not affect memory contents)
// <wire_or_reg> rstb; // Port B output reset (does not affect memory contents)
// <wire_or_reg> regcea; // Port A output register enable
// <wire_or_reg> regceb; // Port B output register enable
// wire [RAM_WIDTH-1:0] douta; // Port A RAM output data
// wire [RAM_WIDTH-1:0] doutb; // Port B RAM output data
localparam DEPTH = 2 ** L2_DEPTH;
reg [WIDTH-1:0] RAM[DEPTH-1:0];
reg [WIDTH-1:0] RAM_data_1 = {WIDTH{1'b0}};
reg [WIDTH-1:0] RAM_data_2 = {WIDTH{1'b0}};
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin : use_init_file
initial $readmemh(INIT_FILE, RAM, 0, DEPTH - 1);
end else begin : init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < DEPTH; ram_index = ram_index + 1)
RAM[ram_index] = {WIDTH{1'b0}};
end
endgenerate
always @(posedge clk)
if (en1)
if (we1) begin
RAM[addr1] <= din1;
RAM_data_1 <= din1;
end else RAM_data_1 <= RAM[addr1];
always @(posedge clk)
if (en2)
if (we2) begin
RAM[addr2] <= din2;
RAM_data_2 <= din2;
end else RAM_data_2 <= RAM[addr2];
// The following is a 2 clock cycle read latency with improve clock-to-out timing
reg [WIDTH-1:0] dout1_reg = {WIDTH{1'b0}};
reg [WIDTH-1:0] dout2_reg = {WIDTH{1'b0}};
always @(posedge clk)
if (rst1) dout1_reg <= {WIDTH{1'b0}};
else if (regce1) dout1_reg <= RAM_data_1;
always @(posedge clk)
if (rst2) dout2_reg <= {WIDTH{1'b0}};
else if (regce2) dout2_reg <= RAM_data_2;
assign dout1 = dout1_reg;
assign dout2 = dout2_reg;
endmodule
| 8.026889 |
module true_dp_bram_readfirst #(
parameter L2_DEPTH = 8,
parameter WIDTH = 32
) (
input clk,
input we1,
input en1,
input [L2_DEPTH-1:0] addr1,
input [ WIDTH-1:0] din1,
input rst1,
input regce1,
output [ WIDTH-1:0] dout1,
input we2,
input en2,
input [L2_DEPTH-1:0] addr2,
input [ WIDTH-1:0] din2,
input rst2,
input regce2,
output [ WIDTH-1:0] dout2
);
parameter INIT_FILE = ""; // Specify name/location of RAM initialization file if using one (leave blank if not)
// <wire_or_reg> [clogb2(RAM_DEPTH-1)-1:0] addra; // Port A address bus, width determined from RAM_DEPTH
// <wire_or_reg> [clogb2(RAM_DEPTH-1)-1:0] addrb; // Port B address bus, width determined from RAM_DEPTH
// <wire_or_reg> [RAM_WIDTH-1:0] dina; // Port A RAM input data
// <wire_or_reg> [RAM_WIDTH-1:0] dinb; // Port B RAM input data
// <wire_or_reg> clka; // Port A clock
// <wire_or_reg> clkb; // Port B clock
// <wire_or_reg> wea; // Port A write enable
// <wire_or_reg> web; // Port B write enable
// <wire_or_reg> ena; // Port A RAM Enable, for additional power savings, disable port when not in use
// <wire_or_reg> enb; // Port B RAM Enable, for additional power savings, disable port when not in use
// <wire_or_reg> rsta; // Port A output reset (does not affect memory contents)
// <wire_or_reg> rstb; // Port B output reset (does not affect memory contents)
// <wire_or_reg> regcea; // Port A output register enable
// <wire_or_reg> regceb; // Port B output register enable
// wire [RAM_WIDTH-1:0] douta; // Port A RAM output data
// wire [RAM_WIDTH-1:0] doutb; // Port B RAM output data
localparam DEPTH = 2 ** L2_DEPTH;
reg [WIDTH-1:0] RAM[DEPTH-1:0];
reg [WIDTH-1:0] RAM_data_1 = {WIDTH{1'b0}};
reg [WIDTH-1:0] RAM_data_2 = {WIDTH{1'b0}};
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin : use_init_file
initial $readmemh(INIT_FILE, RAM, 0, DEPTH - 1);
end else begin : init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < DEPTH; ram_index = ram_index + 1)
RAM[ram_index] = {WIDTH{1'b0}};
end
endgenerate
always @(posedge clk)
if (en1) begin
RAM_data_1 <= RAM[addr1];
if (we1) begin
RAM[addr1] <= din1;
end
end
always @(posedge clk)
if (en2) begin
RAM_data_2 <= RAM[addr2];
if (we2) begin
RAM[addr2] <= din2;
end
end
// The following is a 2 clock cycle read latency with improve clock-to-out timing
reg [WIDTH-1:0] dout1_reg = {WIDTH{1'b0}};
reg [WIDTH-1:0] dout2_reg = {WIDTH{1'b0}};
always @(posedge clk)
if (rst1) dout1_reg <= {WIDTH{1'b0}};
else if (regce1) dout1_reg <= RAM_data_1;
always @(posedge clk)
if (rst2) dout2_reg <= {WIDTH{1'b0}};
else if (regce2) dout2_reg <= RAM_data_2;
assign dout1 = dout1_reg;
assign dout2 = dout2_reg;
endmodule
| 7.82739 |
module
true_dual_port_memory #(parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
MEM_SIZE = 512
)(
input clk,
input [DATA_WIDTH-1:0] Data_Input_A,
input [$clog2(MEM_SIZE)-1:0] Address_A,
input Enable_Write_A,
input Enable_Read_A,
input [DATA_WIDTH-1:0] Data_Input_B,
input [$clog2(MEM_SIZE)-1:0] Address_B,
input Enable_Write_B,
input Enable_Read_B,
output reg [DATA_WIDTH-1:0] Data_Output_A,
output reg [DATA_WIDTH-1:0] Data_Output_B
);
reg [DATA_WIDTH-1:0] IFM_Memory [MEM_SIZE-1:0];
always @(posedge clk)
begin
if(Enable_Write_A)
IFM_Memory[Address_A] <= Data_Input_A;
if(Enable_Read_A)
Data_Output_A <= IFM_Memory[Address_A];
end
always @(posedge clk)
begin
if(Enable_Write_B)
IFM_Memory[Address_B] <= Data_Input_B;
if(Enable_Read_B)
Data_Output_B <= IFM_Memory[Address_B];
end
endmodule
| 7.350565 |
module true_dual_port_ram #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 9,
parameter WRITE_MODE_1 = "READ_FIRST", // WRITE_FIRST, READ_FIRST, NO_CHANGE
parameter WRITE_MODE_2 = "READ_FIRST",
parameter OUTPUT_REG_1 = "FALSE",
parameter OUTPUT_REG_2 = "FALSE",
parameter RAM_INIT_FILE = "ram_init_file.mem"
) (
input we1,
we2,
clka,
clkb,
input [DATA_WIDTH-1:0] din1,
din2,
input [ADDR_WIDTH-1:0] addr1,
addr2,
output [DATA_WIDTH-1:0] dout1,
dout2
);
localparam MEMORY_DEPTH = 2 ** ADDR_WIDTH;
localparam MAX_DATA = (1 << ADDR_WIDTH) - 1;
reg [DATA_WIDTH-1:0] ram[MEMORY_DEPTH-1:0];
reg [DATA_WIDTH-1:0] r_dout1_1P;
reg [DATA_WIDTH-1:0] r_dout2_1P;
reg [DATA_WIDTH-1:0] r_dout1_2P;
reg [DATA_WIDTH-1:0] r_dout2_2P;
integer i;
initial begin
// // By default the Efinix memory will initialize to 0
if (RAM_INIT_FILE != "") begin
$readmemh(RAM_INIT_FILE, ram);
end
end
generate
if (WRITE_MODE_1 == "WRITE_FIRST") begin
always @(posedge clka) begin
if (we1) begin
ram[addr1] <= din1;
r_dout1_1P <= din1;
end else r_dout1_1P <= ram[addr1];
end
end else if (WRITE_MODE_1 == "READ_FIRST") begin
always @(posedge clka) begin
if (we1) ram[addr1] <= din1;
r_dout1_1P <= ram[addr1];
end
end else if (WRITE_MODE_1 == "NO_CHANGE") begin
always @(posedge clka) begin
if (we1) ram[addr1] <= din1;
else r_dout1_1P <= ram[addr1];
end
end
if (WRITE_MODE_2 == "WRITE_FIRST") begin
always @(posedge clkb) begin
if (we2) begin
ram[addr2] <= din2;
r_dout2_1P <= din2;
end else r_dout2_1P <= ram[addr2];
end
end else if (WRITE_MODE_2 == "READ_FIRST") begin
always @(posedge clkb) begin
if (we2) ram[addr2] <= din2;
r_dout2_1P <= ram[addr2];
end
end else if (WRITE_MODE_2 == "NO_CHANGE") begin
always @(posedge clkb) begin
if (we2) ram[addr2] <= din2;
else r_dout2_1P <= ram[addr2];
end
end
if (OUTPUT_REG_1 == "TRUE") begin
always @(posedge clka) r_dout1_2P <= r_dout1_1P;
assign dout1 = r_dout1_2P;
end else assign dout1 = r_dout1_1P;
if (OUTPUT_REG_2 == "TRUE") begin
always @(posedge clkb) r_dout2_2P <= r_dout2_1P;
assign dout2 = r_dout2_2P;
end else assign dout2 = r_dout2_1P;
endgenerate
endmodule
| 9.063194 |
module true_dual_port_ram_dual_clock #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 6
) (
input [(DATA_WIDTH-1):0] data_a,
data_b,
input [(ADDR_WIDTH-1):0] addr_a,
addr_b,
input we_a,
we_b,
clk_a,
clk_b,
output reg [(DATA_WIDTH-1):0] q_a,
q_b
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @(posedge clk_a) begin
// Port A
if (we_a) begin
ram[addr_a] <= data_a;
q_a <= data_a;
end else begin
q_a <= ram[addr_a];
end
end
always @(posedge clk_b) begin
// Port B
if (we_b) begin
ram[addr_b] <= data_b;
q_b <= data_b;
end else begin
q_b <= ram[addr_b];
end
end
// Specify the initial contents.
initial begin : INIT
integer i;
for (i = 0; i < 2 ** ADDR_WIDTH; i = i + 1) ram[i] = {DATA_WIDTH{1'b0}};
end
endmodule
| 9.063194 |
module true_dual_port_ram_single_clock #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 11
) (
input [(DATA_WIDTH-1):0] data_a,
data_b,
input [(ADDR_WIDTH-1):0] addr_a,
addr_b,
input we_a,
we_b,
clk,
output reg [(DATA_WIDTH-1):0] q_a,
q_b
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
integer i;
initial begin
for (i = 0; i < 2 ** ADDR_WIDTH; i = i + 1) begin
ram[i] <= {DATA_WIDTH{1'b0}};
end
end
// Port A
always @(posedge clk) begin
if (we_a) begin
ram[addr_a] <= data_a;
q_a <= data_a;
end else begin
q_a <= ram[addr_a];
end
end
// Port B
always @(posedge clk) begin
if (we_b) begin
ram[addr_b] <= data_b;
q_b <= data_b;
end else begin
q_b <= ram[addr_b];
end
end
endmodule
| 9.063194 |
module trumpet (
SW,
KEY,
HEX0
);
input [3:1] KEY;
input [1:0] SW;
output [6:0] HEX0;
wire [4:0] note;
note_Select u0 (
.keys(~KEY[3:1]),
.airflow(SW[1:0]),
.note(note)
);
hex_decoder H0 (
.hex_digit(note[3:0]),
.segments (HEX0)
);
endmodule
| 6.778716 |
module note_Select (
keys,
airflow,
note
);
input [2:0] keys;
input [1:0] airflow;
output reg [4:0] note;
always @(*) //declare always block
begin
case (airflow[1:0])
//alternate code used for testing
2'b00: note = 5'b00000; //case 0: no airflow
2'b01: begin
if (keys == 3'b000) //Middle C
note = 5'b00001;
else if (keys == 3'b111) //C#
note = 5'b00010;
else if (keys == 3'b101) //D
note = 5'b00011;
else if (keys == 3'b011) //D#
note = 5'b00100;
else if (keys == 3'b110) //E
note = 5'b00101;
else if (keys == 3'b100) //F
note = 5'b00110;
else if (keys == 3'b010) //F#
note = 5'b00111;
else note = 5'b00000;
end
2'b10: begin
if (keys == 3'b000) //G
note = 5'b01000;
else if (keys == 3'b011) //G#
note = 5'b01001;
else if (keys == 3'b110) //A
note = 5'b01010;
else if (keys == 3'b100) //A#
note = 5'b01011;
else if (keys == 3'b010) //B
note = 5'b01100;
else note = 5'b00000;
end
2'b11: begin
if (keys == 3'b000) //High C
note = 5'b01101;
else if (keys == 3'b110) //C#
note = 5'b01110;
else if (keys == 3'b100) //D
note = 5'b01111;
else if (keys == 3'b010) //D#
note = 5'b10000;
else note = 5'b00000;
end
default: note = 5'b00000; //default case
endcase
end
endmodule
| 7.344374 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_1000;
4'hA: segments = 7'b000_1000;
4'hB: segments = 7'b000_0011;
4'hC: segments = 7'b100_0110;
4'hD: segments = 7'b010_0001;
4'hE: segments = 7'b000_0110;
4'hF: segments = 7'b000_1110;
default: segments = 7'h7f;
endcase
endmodule
| 7.584821 |
module has a latency of 0 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line[i] <= delay_line[i-1];
end
end
assign q = delay_line[depth-1];
endmodule
| 6.771891 |
module Truncate (
Data_in,
Data_out
);
input [`INTERNAL_BITS-1:0] Data_in;
output reg [`DATA_BITS-1:0] Data_out;
//complete your design here
always @(*) begin
Data_out = Data_in[23:8];
end
endmodule
| 6.618551 |
module trunc_tb;
reg clk;
reg [31:0] trunc_a;
wire [31:0] trunc_z;
integer trunc_a_file;
integer trunc_z_file;
integer trunc_a_count;
integer trunc_z_count;
trunc trunc1 (
clk,
trunc_a,
trunc_z
);
initial begin
trunc_z_file = $fopen("stim/trunc_z");
trunc_a_file = $fopen("stim/trunc_a", "r");
end
initial begin
#50010 $finish;
end
initial begin
clk <= 1'b0;
while (1) begin
#5 clk <= ~clk;
end
end
always @(posedge clk) begin
$fdisplay(trunc_z_file, "%d", trunc_z);
#0 trunc_a_count = $fscanf(trunc_a_file, "%d\n", trunc_a);
end
endmodule
| 7.135533 |
module top_module (
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = (x1 & x3) | (~x3 & x2);
endmodule
| 7.203305 |
module top_module (
input x3,
input x2,
input x1, // three inputs
output f // one output
);
// use Karnaugh map to simplify
assign f = (!x3 & x2) | (x3 & x1);
endmodule
| 7.203305 |
module trx_ahb
(
input wire HRESETn
, input wire HCLK
, `DBG_TRX_AHB output wire HBUSREQ
, `DBG_TRX_AHB input wire HGRANT
, `DBG_TRX_AHB output wire [31:0] HADDR
, `DBG_TRX_AHB output wire [ 3:0] HPROT
, `DBG_TRX_AHB output wire [ 1:0] HTRANS
, `DBG_TRX_AHB output wire HLOCK
, `DBG_TRX_AHB output wire HWRITE
, `DBG_TRX_AHB output wire [ 2:0] HSIZE
, `DBG_TRX_AHB output wire [ 2:0] HBURST
, `DBG_TRX_AHB output wire [31:0] HWDATA // non-justified data
, `DBG_TRX_AHB input wire [31:0] HRDATA // non-justified data
, `DBG_TRX_AHB input wire [ 1:0] HRESP
, `DBG_TRX_AHB input wire HREADY
, `DBG_TRX_AHB input wire IRQ // active-high interrupt
, `DBG_TRX_AHB input wire FIQ // active-high fast interrupt
, `DBG_TRX_AHB output wire [15:0] GPOUT
, `DBG_TRX_AHB input wire [15:0] GPIN
, `DBG_TRX_AHB input wire [ 3:0] transactor_sel
, `DBG_TRX_AHB output wire cmd_ready
, `DBG_TRX_AHB input wire cmd_valid
, `DBG_TRX_AHB input wire [31:0] cmd_data
, `DBG_TRX_AHB input wire [15:0] cmd_items
, `DBG_TRX_AHB output wire u2f_ready
, `DBG_TRX_AHB input wire u2f_valid
, `DBG_TRX_AHB input wire [31:0] u2f_data // justified data
, `DBG_TRX_AHB input wire [15:0] u2f_items
, `DBG_TRX_AHB input wire f2u_ready
, `DBG_TRX_AHB output wire f2u_valid
, `DBG_TRX_AHB output wire [33:0] f2u_data// justified data
, `DBG_TRX_AHB input wire [15:0] f2u_rooms
);
// synthesis attribute box_type trx_ahb "black_box"
endmodule
| 6.746507 |
module tr_channel (
note_in,
note_clk,
note_rst,
note_length,
env_atk, //envelope attack and decay are unwired in tr_channel
env_dec, //env dec is unwired in tr_channel. preserved for ease of programming
fx_sel,
fx_optA,
fx_optB,
clk50mhz,
wave_out
);
input [5:0] note_in;
input [2:0] note_length;
input [1:0] env_atk;
input [1:0] env_dec;
input note_clk;
input note_rst;
input [1:0] fx_sel;
input [1:0] fx_optA;
input [1:0] fx_optB;
input clk50mhz;
wire sq_en;
output wire [3:0] wave_out;
wire [3:0] sq_out;
wire [5:0] fx_mux_out;
wire basefreq;
wire buffreq;
//porta module specific wires
reg porta_en;
//wire [1:0] porta_speed_sel;
//assign porta_speed_sel = 1;
wire [5:0] porta_out;
//vibrato module specific wires
wire [5:0] vibra_out;
//wire [1:0] vibra_speed;
//wire [1:0] vibra_depth;
wire [2:0] vibra_offset_mul;
wire vibra_offset_dir;
wire [3:0] vib_offset_mux_out;
reg vibra_en;
//testing specific assignments: only for testing a configuration.
//assign vibra_speed = 3;
//assign vibra_depth = 3;
//slide module wires
wire [5:0] slide_out;
reg slide_en;
initial begin
porta_en <= 0;
vibra_en <= 0;
slide_en <= 0;
end
always @(posedge clk50mhz) begin
case (fx_sel)
0: begin
porta_en <= 0;
vibra_en <= 0;
slide_en <= 0;
end
1: begin
porta_en <= 1;
vibra_en <= 0;
slide_en <= 0;
end
2: begin
porta_en <= 0;
vibra_en <= 1;
slide_en <= 0;
end
3: begin
porta_en <= 0;
vibra_en <= 0;
slide_en <= 1;
end
default: begin
porta_en <= 0;
vibra_en <= 0;
slide_en <= 0;
end
endcase
end
FX_porta tr_porta (
.note_in (note_in),
.note_clk (note_clk),
.note_out (porta_out),
.speed_sel (fx_optA), //two bits FXA
.en (porta_en), //used to be butt_1
.clk50mhz (clk50mhz)
);
FX_vibrato tr_vibra (
.note_in(note_in), //6 bits
.note_clk(note_clk), //1 bit
.note_out(vibra_out), //6 bits
.speed (fx_optA), //speed: two bits FXA. speed: inverse relationship. FXA up, speed goes slower.
.depth(fx_optB), //depth: two bits FXB
.offset_mul(vibra_offset_mul), //3 bits
.offset_dir(vibra_offset_dir), //1 bit
.en(vibra_en), //1 bit
.clk50mhz(clk50mhz) //1 bit
);
FX_slide sq_slide (
.note_in (note_in),
.note_clk (note_clk),
.note_out (slide_out),
.speed (fx_optA),
.direction (fx_optB),
.en (slide_en),
.rst (note_rst),
.clk50mhz (clk50mhz)
);
mux4to1 tr_FX_mux (
.in_a(note_in),
.in_b(porta_out),
.in_c(vibra_out),
.in_d(slide_out),
.mux_sel(fx_sel),
.mux_out(fx_mux_out)
);
mux_4to1_4bit vibrato_offset_mux_tr (
.in_a(4'b0),
.in_b(4'b0),
.in_c({{vibra_offset_dir}, {vibra_offset_mul[2:0]}}),
.in_d(4'b0),
.mux_sel(fx_sel),
.mux_out(vib_offset_mux_out)
);
base_freq_genx64 tr_freqgen ( //SQUARE CHANNEL 1
.note_in(fx_mux_out),
.clk50mhz(clk50mhz),
.freq_out(basefreq),
.offset_mult(vib_offset_mux_out[2:0]),
.offset_dir(vib_offset_mux_out[3])
);
BUFG freq1_bufg (
.I(basefreq),
.O(buffreq)
); //a clock buffer?
//SQUARE WAVE CHANNEL
trigen triangle_generator (
.base_freq (buffreq),
.triangle_out (sq_out),
.en (sq_en) //CHANGE THIS; link to envelope controller
);
//Envelope Controller
tri_length_control tri_len_ctrl (
.attack (2'b00), //triangle channel does not support atk/dec
.decay (2'b00), //triangle channel does not support atk/dec
.length (note_length),
.enable_out (sq_en),
.rst (note_rst),
.note_clk (note_clk),
.square_in (sq_out),
.square_out (wave_out)
);
endmodule
| 7.442098 |
module tr_concat (
in_data,
out_data
);
input wire [25:0] in_data;
output wire [31:0] out_data;
assign out_data = {{6{in_data[25]}}, in_data};
endmodule
| 6.610109 |
module ts4231_configurator (
input wire clk_96MHz,
input wire e_in_0_r,
output reg envelop_output_enable,
output reg envelop_output,
input wire d_in_0_r,
output reg data_output_enable,
output reg data_output,
output reg configured
);
// configuration management
reg reconfigure = 1'b1;
always @(posedge clk_96MHz) begin
if (configured) begin
reconfigure <= 1'b0;
end else begin
reconfigure <= 1'b1;
end
end
// ts4231Configurator instanciation
ts4231Configurator CONFIGURATOR (
.clk(clk_96MHz),
.reconfigure(reconfigure),
.configured(configured),
.d_in(d_in_0_r),
.d_out(data_output),
.d_oe(data_output_enable),
.e_in(e_in_0_r),
.e_out(envelop_output),
.e_oe(envelop_output_enable)
);
endmodule
| 7.14567 |
module is a sample dummy stub that can be filled in by the user. Any access's on
* the TS-7300 CPU for address 0x72a00000 to 0x72fffffc arrive here. Keep in mind
* the address is a word address not the byte address and address 0x0 is 0x72000000.
* The interface used here is the WISHBONE bus, described in detail on
* http://www.opencores.org
*
* There is a 40-pin header next to the FPGA. It is broken up into 2 20 pin
* connectors. One is labeled DIO2 and contains the 18 dedicated GPIO pins. The
* other contains 17 signals that are used by the TS-VIDCORE but can also be used
* as GPIO if video is not used. DO NOT DRIVE THESE SIGNALS OVER 3.3V!!! They
* go straight into the FPGA pads unbuffered.
* ___________________________________________________________
* | 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40|
* | 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39|
* \-----------------------------------------------------------/
* * | * DIO2
*
* pins #2 and #22 are grounds
* pin #20 is fused 5V (polyfuse)
* pin #40 is regulated 3.3V
* pin #18 can be externally driven high to disable DB15 VGA connector DACs
* pin #36 and #38 also go to the red and green LEDs (active low)
* pin #39 is a dedicated clock input and cannot be programmed for output
*
*/
module ts7300_wishbone_slave(
/* 75Mhz clock is fed to this module */
wb_clk_i,
wb_rst_i,
wb_adr_i,
wb_dat_i,
wb_cyc_i,
wb_stb_i,
wb_we_i,
wb_ack_o,
wb_dat_o,
/* This is the 40 pin header next to the FPGA */
headerpin_i,
headerpin_o,
headerpin_oe_o, /* output enable */
/* Use this for an IRQ on ARM IRQ #40 -- In Linux, be sure to
* use request_irq() with the SA_SHIRQ flag which enables
* sharing interrupts with the Linux ethernet driver.
*/
irq_o
);
input wb_clk_i;
input wb_rst_i;
input wb_cyc_i;
input wb_stb_i;
input wb_we_i;
input [21:0] wb_adr_i;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
output wb_ack_o;
input [40:1] headerpin_i;
output [40:1] headerpin_o, headerpin_oe_o;
output irq_o;
/*
* BEGIN USER-SERVICEABLE SECTION
*
* The default here is to alias the entire space onto one 32-bit register "dummyreg"
* On reset, it is set to 0xdeadbeef but then retains the value last written to it.
* The value of this register drives GPIO pins 9-40 on the FPGA connector described
* above.
*/
reg [31:0] dummyreg;
assign wb_ack_o = wb_cyc_i && wb_stb_i; /* 0-wait state WISHBONE */
assign wb_dat_o = dummyreg;
assign headerpin_oe_o[40:1] = 40'hffffffffff; /* All outputs */
assign headerpin_o[40:1] = {dummyreg, 8'd0};
assign irq_o = 1'b0;
always @(posedge wb_clk_i) begin
if (wb_rst_i) dummyreg <= 32'hdeadbeef;
else if (wb_cyc_i && wb_stb_i && wb_we_i) dummyreg <= wb_dat_i;
end
/*
* END USER-SERVICEABLE SECTION
*/
endmodule
| 8.16331 |
module TsAnalyzer (
input wire nReset,
input wire isoReset,
input wire isoClk,
input wire isoVdd,
input wire isoSio,
input wire endOfRx,
input wire [7:0] rxData, //assumed to be sent lsb first, high level coding logical 1.
output wire isActivated,
output wire tsReceived,
output wire tsError,
output wire atrIsEarly, //high if TS received before 400 cycles after reset release
output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
output wire useIndirectConvention,
output reg [7:0] ts
);
reg [8:0] tsCnt; //counter to start ATR 400 cycles after reset release
reg [16:0] resetCnt;
reg waitTs;
assign tsReceived = ~waitTs;
assign atrIsEarly = ~waitTs & (resetCnt < (16'h100 + 16'd400));
assign atrIsLate = resetCnt > (16'h100 + 16'd40000);
assign useIndirectConvention = ~waitTs & (ts == 8'h3F);
assign tsError = ~waitTs & (ts != 8'h3B) & (ts != 8'h3F);
assign isActivated = isoReset & isoVdd;
wire fsm_nReset = nReset & isoReset & isoVdd;
always @(posedge isoClk, negedge fsm_nReset) begin
if (~fsm_nReset) begin
resetCnt <= 16'b0;
waitTs <= 1'b1;
end else if (isActivated) begin
if (waitTs) begin
if (endOfRx) begin
waitTs <= 1'b0;
case (rxData)
8'h3B: ts <= rxData;
8'h03: ts <= 8'h3F; //03 is 3F written LSB first and complemented
default: ts <= rxData;
endcase
end
resetCnt <= resetCnt + 1'b1;
end
end else begin
//if(isoVdd & isoReset) begin
resetCnt <= resetCnt + 1'b1;
//end else begin
// resetCnt<=16'b0;
//end
end
end
endmodule
| 8.469006 |
module tsb_32 (
out,
in,
oe
);
input [31:0] in;
input oe;
output [31:0] out;
assign out = oe ? in : 32'bz;
endmodule
| 6.697993 |
module tsdm (
input clk,
input rst,
input [7:0] din,
input blanking,
input c0,
input c1,
output reg [9:0] dout
);
reg signed [2:0] dc_bias;
wire [3:0] ones;
wire [3:0] zeros;
reg [9:0] dout_reg;
function [3:0] popcount;
input [7:0] v;
begin
popcount = v[7] + v[6] + v[5] + v[4] + v[3] + v[2] + v[1] + v[0];
end
endfunction
always @(*) begin
dout_reg[0] = din[0];
casez ({
popcount(din), din[0]
})
5'b0000z, 5'b0001z, 5'b0010z, 5'b0011z, 5'b01001: begin
dout_reg[1] = dout_reg[0] ^ din[1];
dout_reg[2] = dout_reg[1] ^ din[2];
dout_reg[3] = dout_reg[2] ^ din[3];
dout_reg[4] = dout_reg[3] ^ din[4];
dout_reg[5] = dout_reg[4] ^ din[5];
dout_reg[6] = dout_reg[5] ^ din[6];
dout_reg[7] = dout_reg[6] ^ din[7];
dout_reg[8] = 1;
end
5'b01000, 5'b0101z, 5'b0110z, 5'b0111z, 5'b1000z: begin
dout_reg[1] = dout_reg[0] == din[1];
dout_reg[2] = dout_reg[1] == din[2];
dout_reg[3] = dout_reg[2] == din[3];
dout_reg[4] = dout_reg[3] == din[4];
dout_reg[5] = dout_reg[4] == din[5];
dout_reg[6] = dout_reg[5] == din[6];
dout_reg[7] = dout_reg[6] == din[7];
dout_reg[8] = 0;
end
default: begin
dout_reg = 10'bx;
end
endcase
end
assign ones = popcount(dout_reg[7:0]);
assign zeros = 8 - ones;
always @(posedge clk) begin
if (rst) begin
dc_bias <= 4'sd0;
dout <= 10'bx;
end else begin
if (blanking) begin
case ({
c1, c0
})
2'b00: dout <= 10'b1101010100;
2'b01: dout <= 10'b0010101011;
2'b10: dout <= 10'b0101010100;
2'b11: dout <= 10'b1010101011;
endcase
dc_bias <= 4'sd0;
end else begin
if (dc_bias == 0 || (ones == zeros)) begin
dout[9] <= ~dout_reg[8];
dout[8] <= dout_reg[8];
dout[7:0] <= (dout_reg[8]) ? dout_reg[7:0] : ~dout_reg[7:0];
if (dout_reg[8] == 0) begin
dc_bias <= dc_bias + (zeros - ones);
end else begin
dc_bias <= dc_bias + (ones - zeros);
end
end else begin
if ((dc_bias > 0 && (ones > zeros)) || (dc_bias < 0 && (zeros > ones))) begin
dout[9] <= 1;
dout[8] <= dout_reg[8];
dout[7:0] <= ~dout_reg[7:0];
dc_bias <= dc_bias + 2 * dout_reg[8] + (zeros - ones);
end else begin
dout[9] <= 0;
dout[8] <= dout_reg[8];
dout[7:0] <= dout_reg[7:0];
dc_bias <= dc_bias - 2 * (~dout_reg[8]) + (ones - zeros);
end
end
end
end
end
endmodule
| 7.451759 |
module tseg_reg2 (
input wire clock, // DW 2005.06.26 Clock
input wire reset, // DW 2005.06.26 Reset aktiv low
input wire [1:0] ctrl,
input wire [2:0] tseg1, // IOCPU, genreg.
input wire [4:0] tseg1pcount, // sum
input wire [4:0] tseg1p1psjw, // sum
output reg [4:0] tseg1mpl // sum
);
// aus dem Latch wird ein Register
// DW 2005.06.26 Prescle_EN und Reset eingefgt
always @(posedge clock, negedge reset) begin
if (reset == 1'b0) tseg1mpl <= 5'b00000;
else begin
case (ctrl) // umschalten
2'b01: tseg1mpl <= {2'b00, tseg1};
2'b10: tseg1mpl <= tseg1pcount;
2'b11: tseg1mpl <= tseg1p1psjw;
default: tseg1mpl <= tseg1mpl; // halten
endcase
end
end
endmodule
| 7.024255 |
module LM07_read (
SYSCLK,
RSTN,
CS,
SCK,
SIO,
disp,
dataSeg,
dbugout
);
input SYSCLK; //System clock from the testbench
input RSTN; //Active-low reset signal
input SIO; //Serial data output from the temp sensor.
output CS; //Generate the Chip select for temp sensor
output reg SCK; //Generate the SPI clock for temp sensor
output [1:0] disp; //7-segment display select lines.
output [7:0] dataSeg; //7-segment data
output [7:0] dbugout; //the 8-bit data is latched for display
reg SYSCLK_HALF;
reg [7:0] shift_reg;
reg [1:0] spi_state;
reg [4:0] count;
wire sysclk_gated;
wire [7:0] temp_bin;
wire [3:0] bcd_msb;
wire [3:0] bcd_lsb;
wire [3:0] bcd_data;
//This output register is for debug purpose.
//assign dbugout[7:4] = bcd_msb;
//assign dbugout[3:0] = bcd_data;
//7-Segment select lines for MSB and LSB
//FIXME
//2:1 MUX for sending MSB/LSB data to the 7-segment display
//FIXME
//BCD to 7-segment decoder
//FIXME
//If you are reading 8-bits from the sensor, the LSB is 2-deg C
//So multiply it by 2 to convert it to the right magnitude.
assign temp_bin = shift_reg << 1;
//Converting 7-bit binary to BCD value
//BCD(MSB) = Temp./10 approx= Temp(1/16 + 1/32)
//NOTE: First add then shift by 4 to avoid truncation error.
//FIXME
//BCD(LSB) = temp - 10*MSB = temp - (8*MSB + 2*MSB)
//FIXME
//shift register for the input (SIO)
always @(posedge SCK or negedge RSTN)
if (~RSTN) shift_reg <= 8'h00;
else begin
shift_reg <= shift_reg << 1;
shift_reg[0] <= SIO;
end
//SPI CLOCK SCK generator
always @(negedge SYSCLK or negedge RSTN)
if (~RSTN || CS) SCK <= 1'b0;
else SCK <= ~SCK;
// Chip Select CS generator
assign CS = ~(spi_state == `SPI_READ);
// 4-state (IDLE, READ, MSB_WRITE, LSB_WRITE) state-machine
always @(posedge SYSCLK or negedge RSTN)
if (~RSTN) begin
spi_state <= `SPI_IDLE;
end else if ((count >= `CS_LOW_COUNT) && (count < `CS_HIGH_COUNT)) begin
spi_state <= `SPI_READ;
end else if (count == `CS_HIGH_COUNT) begin
spi_state <= `DISP_WRITE_MSB;
end else if (count == `WRITE_LSB_COUNT) begin
spi_state <= `DISP_WRITE_LSB;
end else begin
spi_state <= `SPI_IDLE;
end
//5-bit Counter
always @(negedge SYSCLK or negedge RSTN)
if (~RSTN) count <= `RST_COUNT;
else if (count == `MAX_COUNT) count <= `RST_COUNT;
else count <= count + 1'b1;
endmodule
| 6.85083 |
module tse_mac (
ff_tx_data,
ff_tx_eop,
ff_tx_err,
ff_tx_mod,
ff_tx_sop,
ff_tx_wren,
ff_tx_clk,
ff_rx_rdy,
ff_rx_clk,
address,
read,
writedata,
write,
clk,
reset,
rgmii_in,
rx_control,
tx_clk,
rx_clk,
set_10,
set_1000,
mdio_in,
ff_tx_crc_fwd,
ff_tx_rdy,
ff_rx_data,
ff_rx_dval,
ff_rx_eop,
ff_rx_mod,
ff_rx_sop,
rx_err,
readdata,
waitrequest,
rgmii_out,
tx_control,
ena_10,
eth_mode,
mdio_out,
mdio_oen,
mdc,
ff_tx_septy,
tx_ff_uflow,
ff_tx_a_full,
ff_tx_a_empty,
rx_err_stat,
rx_frm_type,
ff_rx_dsav,
ff_rx_a_full,
ff_rx_a_empty
);
input [31:0] ff_tx_data;
input ff_tx_eop;
input ff_tx_err;
input [1:0] ff_tx_mod;
input ff_tx_sop;
input ff_tx_wren;
input ff_tx_clk;
input ff_rx_rdy;
input ff_rx_clk;
input [7:0] address;
input read;
input [31:0] writedata;
input write;
input clk;
input reset;
input [3:0] rgmii_in;
input rx_control;
input tx_clk;
input rx_clk;
input set_10;
input set_1000;
input mdio_in;
input ff_tx_crc_fwd;
output ff_tx_rdy;
output [31:0] ff_rx_data;
output ff_rx_dval;
output ff_rx_eop;
output [1:0] ff_rx_mod;
output ff_rx_sop;
output [5:0] rx_err;
output [31:0] readdata;
output waitrequest;
output [3:0] rgmii_out;
output tx_control;
output ena_10;
output eth_mode;
output mdio_out;
output mdio_oen;
output mdc;
output ff_tx_septy;
output tx_ff_uflow;
output ff_tx_a_full;
output ff_tx_a_empty;
output [17:0] rx_err_stat;
output [3:0] rx_frm_type;
output ff_rx_dsav;
output ff_rx_a_full;
output ff_rx_a_empty;
endmodule
| 6.902323 |
module for SOPC system simulation with
// # Altera Triple Speed Ethernet (TSE) Megacore
// #
// # Generated at Mon Mar 5 10:25:49 2012 as a SOPC Builder component
// #
// #####################################################################################
// # This is a module used to provide external loopback on the TSE megacore by supplying
// # necessary clocks and default signal values on the network side interface
// # (GMII/MII/TBI/Serial)
// #
// # - by default this module generate clocks for operation in Gigabit mode that is
// # of 8 ns clock period
// # - no support for forcing collision detection and carrier sense in MII mode
// # the mii_col and mii_crs signal always pulled to zero
// # - you are recomment to set the the MAC operation mode using register access
// # rather than directly pulling the control signals
// #
// #####################################################################################
`timescale 1ns / 1ps
module tse_mac_loopback (
ref_clk,
txp,
rxp
);
output ref_clk;
input txp;
output rxp;
reg clk_tmp;
initial
clk_tmp <= 1'b0;
always
#4 clk_tmp <= ~clk_tmp;
assign ref_clk = clk_tmp;
assign rxp=txp;
endmodule
| 8.642717 |
module tsf_timer #(
parameter integer TIMER_WIDTH = 64
) (
input wire clk,
input wire rstn,
input wire tsf_load_control, //rising edge will load load_val into timer
input wire [(TIMER_WIDTH-1) : 0] tsf_load_val,
output reg [(TIMER_WIDTH-1) : 0] tsf_runtime_val,
output reg tsf_pulse_1M
);
reg [7:0] counter_1M;
reg tsf_load_control_reg;
always @(posedge clk) begin
if (rstn == 0) begin
counter_1M <= 0;
tsf_runtime_val <= 0;
tsf_pulse_1M <= 0;
tsf_load_control_reg <= 0;
end else begin
tsf_load_control_reg <= tsf_load_control;
if (counter_1M == `COUNT_TOP_1M || (tsf_load_control == 0 && tsf_load_control_reg == 1)) begin
counter_1M <= 0;
end else begin
counter_1M <= counter_1M + 1'b1;
end
if (tsf_load_control == 0 && tsf_load_control_reg == 1) begin
tsf_pulse_1M <= 0;
tsf_runtime_val <= tsf_load_val;
end else begin
if (counter_1M == 0) begin
tsf_pulse_1M <= 1;
tsf_runtime_val <= tsf_runtime_val + 1'b1;
end else begin
tsf_pulse_1M <= 0;
tsf_runtime_val <= tsf_runtime_val;
end
end
end
end
endmodule
| 7.443119 |
module tshift_cell2 (
input wire enable,
input wire preload,
input wire clock,
input wire reset,
input wire load,
input wire Input,
output reg q
);
always@(posedge clock) // rising clock edge
begin
if (reset == 1'b0) // asynchronous reset (active low)
q <= 1'b0;
else if (enable == 1'b1) begin // load ist enable, entwd. input oder preload
q <= (preload & load) | (Input & (~load));
//else
end
end
endmodule
| 6.918863 |
module tshiftreg2 (
input wire clock,
input wire [102:0] mesin,
input wire activ, // MACFSM: actvtsft, llc:actvtsftllc
input wire reset, // MAC: reset or MACFSM: resetsft
input wire load, // llc: load
input wire shift, // MACFSM: tshift
input wire extended, // IOCPU
output wire bitout, // stuff, biterrordetect
output wire crc_out_bit // tcrc
);
wire reset_i;
wire load_reg;
wire [102:0] q_i;
wire zero;
wire bitout_i;
reg enable_i;
reg edged;
assign reset_i = reset;
assign load_reg = load; // intern: laden Register
assign zero = 1'b0; // 0- input
assign bitout = (bitout_i & extended) | (q_i[82] & (~extended)); // basic: 82 extended: 102
assign crc_out_bit = (q_i[87] & extended) | (q_i[67] & (~extended)); // basic: 67, extended 87,
// crc wird mit bit, das
// erst 15 Zeiten spter
// kommt gefttert,
// wg crc-nderung
// oberstes Register (Ausgang bitout_i)
tshift_cell2 topreg ( // Nr 102
.enable (enable_i),
.preload(mesin[102]),
.clock (clock),
.reset (reset_i),
.load (load_reg),
.Input (q_i[101]),
.q (bitout_i)
);
// mittlere Register:
genvar i;
generate
for (i = 1; i < 102; i = i + 1) begin
tshift_cell2 reg_i (
.enable (enable_i),
.preload(mesin[i]),
.clock (clock),
.reset (reset_i),
.load (load_reg),
.Input (q_i[i-1]),
.q (q_i[i])
);
end
endgenerate
// unterstes Register, null als eingang
tshift_cell2 bottom_reg ( // Nr. 0
.enable (enable_i),
.preload(mesin[0]),
.clock (clock),
.reset (reset_i),
.load (load_reg),
.Input (zero),
.q (q_i[0])
);
always @(negedge clock) begin
if (reset == 1'b0) begin // synchroner reset
edged = 1'b0; // normalerweise active high
enable_i <= 1'b0;
end else if (activ == 1'b1) begin
if (edged == 1'b0) begin // Flanke?
edged = 1'b1; // jetzt war eine
if (shift == 1'b1 || load == 1'b1) enable_i <= 1'b1; // shift oder load sorgen fr
else // aktivierung der register
enable_i <= 1'b0;
end else begin
enable_i <= 1'b0;
edged = 1'b1; // immmer noch pos. Flanke
end
end else begin
enable_i <= 1'b0;
edged = 1'b0; // jetzt war activ runter
end
end
endmodule
| 6.760892 |
module TSK_NR_ASGV (
in1,
in2,
out1,
out2
);
input in1;
input in2;
output out1;
output out2;
reg out1;
reg g1;
task task1;
output o1;
input in1;
input in2;
begin
g1 = in1;
o1 = in2;
end
endtask
always @(in1 or in2) task1(out1, in1, in2);
assign out2 = g1;
endmodule
| 6.949814 |
module TSK_NR_CLKE (
clk,
in0,
out0
);
input clk, in0;
output out0;
reg out0;
task task_a;
input in1;
output reg out1;
begin
@(posedge clk) begin
out1 <= in1;
end
end
endtask
always @(posedge clk) begin
task_a(in0, out0);
end
endmodule
| 6.891432 |
module TSL (
A,
B,
EN,
Y
);
input A, B, EN;
output Y;
assign Y = (!EN) ? (A && B) : 0;
endmodule
| 6.504668 |
module AND2X1 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.586662 |
module AND2X2 (
Y,
A,
B
);
output Y;
input A, B;
and (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.581256 |
module BUFX10 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.70386 |
module BUFX14 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.849172 |
module BUFX16 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.017424 |
module BUFX18 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.576044 |
module BUFX20 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.887067 |
module BUFX2 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.749484 |
module BUFX5 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.595332 |
module BUFX8 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.734604 |
module CLKNAND2X2 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.51822 |
module DLY1X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.803121 |
module DLY1X4 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.769339 |
module DLY2X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.888716 |
module DLY2X4 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.784512 |
module DLY4X1 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.836106 |
module DLY4X4 (
Y,
A
);
output Y;
input A;
buf I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.727196 |
module INVX10 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.33871 |
module INVX12 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.954558 |
module INVX14 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.48284 |
module INVX16 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.76246 |
module INVX18 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.92667 |
module INVX1 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.147471 |
module INVX20 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.664121 |
module INVX2 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.594979 |
module INVX3 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.820921 |
module INVX4 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.745486 |
module INVX5 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.097756 |
module INVX6 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.139895 |
module INVX8 (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 7.420124 |
module INVXL (
Y,
A
);
output Y;
input A;
not I0 (Y, A);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.7964 |
module MX2X8 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
Y,
A,
B,
S0
);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// path delays
if ((A == 1'b1) && (B == 1'b0)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
if ((A == 1'b0) && (B == 1'b1)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.679592 |
module MXI2X1 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// path delays
if ((A == 1'b1) && (B == 1'b0)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
if ((A == 1'b0) && (B == 1'b1)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.596441 |
module MXI2X2 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// path delays
if ((A == 1'b1) && (B == 1'b0)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
if ((A == 1'b0) && (B == 1'b1)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.513 |
module MXI2X8 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// path delays
if ((A == 1'b1) && (B == 1'b0)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
if ((A == 1'b0) && (B == 1'b1)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.589143 |
module MXI2DX1 (
Y,
A,
B,
S0
);
output Y;
input A, B, S0;
udp_mux2 u0 (
YN,
A,
B,
S0
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0;
// path delays
if ((A == 1'b1) && (B == 1'b0)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
if ((A == 1'b0) && (B == 1'b1)) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.501998 |
module MXI3X4 (
Y,
A,
B,
C,
S0,
S1
);
output Y;
input A, B, C, S0, S1;
udp_mux4 u0 (
YN,
A,
B,
C,
C,
S0,
S1
);
not u1 (Y, YN);
specify
// delay parameters
specparam
tplh$A$Y = 1.0,
tphl$A$Y = 1.0,
tplh$B$Y = 1.0,
tphl$B$Y = 1.0,
tplh$C$Y = 1.0,
tphl$C$Y = 1.0,
tplh$S0$Y = 1.0,
tphl$S0$Y = 1.0,
tplh$S1$Y = 1.0,
tphl$S1$Y = 1.0;
// path delays
if (A == 1'b1 && C == 1'b0 && S0 == 1'b0) (S1 *> Y) = (tplh$S1$Y, tphl$S1$Y);
if (A == 1'b0 && C == 1'b1 && S0 == 1'b0) (S1 *> Y) = (tplh$S1$Y, tphl$S1$Y);
if (B == 1'b1 && C == 1'b0 && S0 == 1'b1) (S1 *> Y) = (tplh$S1$Y, tphl$S1$Y);
if (B == 1'b0 && C == 1'b1 && S0 == 1'b1) (S1 *> Y) = (tplh$S1$Y, tphl$S1$Y);
if (A == 1'b1 && B == 1'b0 && S1 == 1'b0) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
if (A == 1'b0 && B == 1'b1 && S1 == 1'b0) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
if (C == 1'b1 && S1 == 1'b1) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
if (C == 1'b0 && S1 == 1'b1) (S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
(C *> Y) = (tplh$C$Y, tphl$C$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
(A *> Y) = (tplh$A$Y, tphl$A$Y);
endspecify
endmodule
| 6.578424 |
module NAND2X1 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.753512 |
module NAND2X2 (
Y,
A,
B
);
output Y;
input A, B;
nand (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.714648 |
module NOR2X1 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.900171 |
module NOR2X2 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.834679 |
module NOR2X3 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.587063 |
module NOR2X5 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.647665 |
module NOR2X6 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.536029 |
module NOR2X8 (
Y,
A,
B
);
output Y;
input A, B;
nor (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.745176 |
module OR2X1 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.671603 |
module OR2X2 (
Y,
A,
B
);
output Y;
input A, B;
or (Y, A, B);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$B$Y = 1.0, tphl$B$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(B *> Y) = (tplh$B$Y, tphl$B$Y);
endspecify
endmodule
| 6.718483 |
module TBUFX12 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 6.509442 |
module TBUFX16 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 6.879027 |
module TBUFX1 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 7.023106 |
module TBUFX20 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 7.162916 |
module TBUFX2 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 6.905349 |
module TBUFX6 (
Y,
A,
OE
);
output Y;
input A, OE;
bufif1 I0 (Y, A, OE);
specify
// delay parameters
specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0, tplh$OE$Y = 1.0, tphl$OE$Y = 1.0;
// path delays
(A *> Y) = (tplh$A$Y, tphl$A$Y);
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
endspecify
endmodule
| 6.649416 |
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