code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tremolo (
input wire clk,
input wire sample_clk_en,
input wire [`BANK_NUM_WIDTH-1:0] bank_num,
input wire [`OP_NUM_WIDTH-1:0] op_num,
input wire dam, // depth of tremolo
output reg [`AM_VAL_WIDTH-1:0] am_val = 0
);
localparam TREMOLO_MAX_COUNT = 13 * 1024;
localparam TREMOLO_INDEX_WIDTH = 14;
reg [ TREMOLO_INDEX_WIDTH-1:0] tremolo_index = 0;
wire [TREMOLO_INDEX_WIDTH-8-1:0] am_val_tmp0;
wire [TREMOLO_INDEX_WIDTH-8-1:0] am_val_tmp1;
/*
* Low-Frequency Oscillator (LFO)
* 3.7 Hz (Sample Freq/2**14)
*/
always @(posedge clk)
if (sample_clk_en && bank_num == 0 && op_num == 0)
if (tremolo_index == TREMOLO_MAX_COUNT - 1) tremolo_index <= 0;
else tremolo_index <= tremolo_index + 1;
assign am_val_tmp0 = tremolo_index >> 8;
assign am_val_tmp1 = (am_val_tmp0 > 26) ? (2 * 26 + ~am_val_tmp0) : am_val_tmp0;
always @(posedge clk)
if (dam) am_val <= am_val_tmp1;
else am_val <= am_val_tmp1 >> 2;
endmodule
| 7.849965 |
module TRexDelegate #(
parameter ratio = 1
) (
input wire rst,
input wire animationClk,
input wire FrameClk,
input wire jump,
input wire duck,
input wire [1:0] gameState,
input wire [10:0] GroundY,
input wire [10:0] vgaX,
input wire [10:0] vgaY,
output wire inGrey,
output wire inWhite
);
reg [5:0] DinoX;
reg signed [10:0] DinoY;
wire [5:0] defaultX;
assign defaultX = 6'd50;
wire Airborne;
wire isDuck;
wire isDead;
assign onGround = (DinoY >= GroundY);
assign isDuck = duck;
assign isDead = (gameState == 2'b01);
wire dino_inWhite;
wire dino_inGrey;
wire [3:0] dinoSEL;
/*
Dino Movement
*/
reg signed [6:0] V;
reg isJumping;
localparam g = 1;
localparam v_init = 7'd17;
/* Gravity Module */
always @(posedge FrameClk or posedge rst) begin
if (rst) begin
DinoX <= defaultX;
DinoY <= GroundY;
isJumping <= 0;
V <= 0;
end else begin
case (gameState)
2'b00: DinoY <= GroundY;
2'b10: begin
if (isJumping) begin
V <= V + g;
DinoY <= DinoY + V;
if (DinoY >= GroundY) begin
DinoY <= GroundY;
V <= 0;
isJumping <= 0;
end
end else if (jump) begin
isJumping <= 1;
V <= -v_init;
DinoY <= DinoY - v_init;
end else DinoY <= GroundY;
end
2'b01: DinoY <= DinoY;
endcase
end
end
DinoFSM fsm (
.rst(rst),
.animationClk(animationClk),
.gameState(gameState),
.Airborne(~onGround),
.onGround(onGround),
.isDuck(isDuck),
.DinoMovementSelect(dinoSEL)
);
drawDino #(
.ratio(ratio)
) dino (
.rst(rst),
.ox(DinoX),
.oy(DinoY),
.X(vgaX),
.Y(vgaY),
.select(dinoSEL),
.inWhite(dino_inWhite),
.inGrey(dino_inGrey)
);
assign inGrey = dino_inGrey;
assign inWhite = dino_inWhite;
endmodule
| 7.893332 |
module tri_state_logic(
inout [31:0] signal_io,
output [31:0] signal_i,
input [31:0] signal_o,
input signal_t,
);
assign signal_io = signal_t ? 32'bz : signal_o;
assign signal_i = signal_io;
endmodule
| 7.023188 |
module tri_state_logic(
inout signal_io,
output signal_i,
input signal_o,
input signal_t,
);
assign signal_io = signal_t ? 1'bz : signal_o;
assign signal_i = signal_io;
endmodule
| 7.023188 |
module tri16bit (
input oe,
input [15:0] in,
output [15:0] out
);
assign out = oe ? in : 16'hz;
endmodule
| 8.122849 |
module short (
inout [7:0] p,
input en
);
assign p = en ? 8'h55 : 8'hzz;
endmodule
| 6.817822 |
module long (
inout [15:0] p,
input en
);
assign p = en ? 16'haaaa : 16'hzzzz;
endmodule
| 6.866635 |
module triad_decode(clock,reset,persist,triad,h_strip `triad_sm_dsp_debug);
// Version
initial $display ("triad_decode: Instantiating 4-Counter Version");
// Ports
input clock; // 40MHz system clock
input reset; // State machine to idle
input [3:0] persist; // Output persistence-1, ie 5 gives 6-clk width
input triad; // 3-bit serial triad
output [3:0] h_strip; // 4-bit parallel 1/2-strips
// Triad Decode State Machine declarations
parameter NSTATES = 3;
reg [NSTATES-1:0] triad_sm; // synthesis attribute safe_implementation of triad_sm is "yes";
parameter idle = 2'h0;
parameter lstrip = 2'h1;
parameter lhstrip = 2'h2;
// FF Buffer triad input stream for simulation only, needed for correct simulation of combinatorial fast h_strip output
`ifdef triad_decode_debug
initial $display ("triad_decode: Inserting simulation flip-flop on triad input signal !!!!");
reg triad_ff=0;
always @(posedge clock) begin // FF triad input stream only for simulation
triad_ff <= triad;
end
`else
initial $display ("triad_decode: Using direct triad input signal");
wire triad_ff = triad; // take direct triad stream for synthesis
`endif
// Triad Decode State Machine
always @(posedge clock) begin
if(reset) triad_sm <= idle;
else begin
case (triad_sm)
idle: if (triad_ff) triad_sm <= lstrip;
lstrip: triad_sm <= lhstrip;
lhstrip: triad_sm <= idle;
endcase
end
end
// Store strip bit
reg strip;
always @(posedge clock) begin
if (triad_sm == lstrip ) strip <= triad_ff;
end
wire hstrip = triad_ff;
// hstrip decoder ROM
reg [3:0] hs;
wire [1:0] adr;
assign adr = {strip,hstrip};
always @* begin
case (adr)
2'h0: hs <= 4'b0001;
2'h1: hs <= 4'b0010;
2'h2: hs <= 4'b0100;
2'h3: hs <= 4'b1000;
endcase
end
// Pulse-width persistence counters
reg [3:0] width_cnt [3:0];
wire [3:0] fire_hs;
wire [3:0] busy_hs;
integer ihs;
assign busy_hs[0] = width_cnt[0]!=0;
assign busy_hs[1] = width_cnt[1]!=0;
assign busy_hs[2] = width_cnt[2]!=0;
assign busy_hs[3] = width_cnt[3]!=0;
//! assign fire_hs[3:0] = hs[3:0]*(triad_sm==lhstrip);
assign fire_hs[3:0] = hs[3:0] & {4 {(triad_sm==lhstrip)}};
always @(posedge clock) begin
ihs=0;
while (ihs <=3) begin
if (reset) width_cnt[ihs] <= 0; // clear on reset
else if (fire_hs[ihs]) width_cnt[ihs] <= persist[3:0]; // load persistence count
else if (busy_hs[ihs]) width_cnt[ihs] <= width_cnt[ihs]-1'b1; // decrement count down to 0
ihs=ihs+1;
end
end
// hstrip pulse output flip-flops
reg [3:0] h_strip;
always @(posedge clock) begin
if (reset ) h_strip[3:0] <= 0; // synchronous reset clears hstrips
else h_strip[3:0] <= busy_hs[3:0] | fire_hs[3:0]; // fire i-th hstrip
end
// Debug
`ifdef triad_decode_debug
output reg [31:0] triad_sm_dsp;
always @* begin
case (triad_sm)
idle: triad_sm_dsp <= "idle"; // start bit arrived
lstrip: triad_sm_dsp <= "str "; // skip it if busy with last triad
lhstrip: triad_sm_dsp <= "hstr"; // not busy, so latch 1/2 strip bit
default: triad_sm_dsp <= "wtf "; // undefined
endcase
end
`endif
endmodule
| 8.612027 |
module trial (
input clock,
input reset,
input [63:0] io_in,
output [63:0] io_out,
input io_opcode
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [63:0] reg_; // @[trial.scala 11:16]
wire [63:0] _GEN_0 = io_opcode ? reg_ : io_in; // @[trial.scala 15:35 trial.scala 16:12 trial.scala 18:12]
assign io_out = ~io_opcode ? io_in : _GEN_0; // @[trial.scala 13:30 trial.scala 14:12]
always @(posedge clock) begin
reg_ <= io_in; // @[trial.scala 12:7]
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
reg_ = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.896784 |
module trial_counter (
count,
over,
state,
submit,
trials
);
output reg [3:0] count;
output reg over;
input state;
input submit;
input [3:0] trials;
initial begin
over = 1'b0;
count = 1'b0;
end
always @(negedge submit) begin
if (state != 1) begin
over <= 1'b0;
count <= 1'b0;
end else begin
if (count == trials - 1) begin
over <= 1'b1;
count <= trials;
end else count <= count + 1;
end
end
endmodule
| 6.87459 |
module Inverter (
in,
out
);
input in;
output out;
assign out = ~in;
endmodule
| 7.198219 |
module Inverter2 (
in,
out
);
input in;
output out;
assign out = ~in;
endmodule
| 7.640496 |
module Triangle (
input clk,
input [11:0] addr,
output [7:0] dout2
);
triangular_rom D (
.clka (clk),
.addra(addr),
.douta(dout2)
);
endmodule
| 7.463184 |
module triangleany (
input clk,
input rst,
/* coordinates are registered */
input [10:0] xa,
input [10:0] ya,
input [10:0] ua,
input [10:0] va,
input [10:0] xb,
input [10:0] yb,
input [10:0] ub,
input [10:0] vb,
input [10:0] xc,
input [10:0] yc,
input [10:0] uc,
input [10:0] vc,
input load,
output [10:0] x,
output [10:0] y,
output [10:0] u,
output [10:0] v,
input next,
output ready,
output finished
);
reg [3:0] state;
reg [3:0] next_state;
parameter IDLERUN = 0, CHOOSEA = 1, CHOOSEBC = 2, START = 3;
reg [10:0] xA;
reg [10:0] yA;
reg [10:0] uA;
reg [10:0] vA;
reg [10:0] xB;
reg [10:0] yB;
reg [10:0] uB;
reg [10:0] vB;
reg [10:0] xC;
reg [10:0] yC;
reg [10:0] uC;
reg [10:0] vC;
reg loadall;
reg swapAB;
reg swapAC;
reg swapBC;
reg triangleload;
wire triangleready;
wire trianglefinished;
triangle dut (
.clk(clk),
.rst(rst),
.xa(xA),
.ya(yA),
.ua(uA),
.va(vA),
.xb(xB),
.yb(yB),
.ub(uB),
.vb(vB),
.xc (xC),
.yc (yC),
.uc (uC),
.vc (vC),
.load(triangleload),
.x(x),
.y(y),
.u(u),
.v(v),
.next(next),
.ready(triangleready),
.finished(trianglefinished)
);
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= IDLERUN;
xA <= 0;
yA <= 0;
uA <= 0;
vA <= 0;
xB <= 0;
yB <= 0;
uB <= 0;
vB <= 0;
xC <= 0;
yC <= 0;
uC <= 0;
vC <= 0;
end else begin
state <= next_state;
if (loadall) begin
xA <= xa;
yA <= ya;
uA <= ua;
vA <= va;
xB <= xb;
yB <= yb;
uB <= ub;
vB <= vb;
xC <= xc;
yC <= yc;
uC <= uc;
vC <= vc;
end else begin
if (swapAB) begin
xA <= xB;
yA <= yB;
uA <= uB;
vA <= vB;
xB <= xA;
yB <= yA;
uB <= uA;
vB <= vA;
end else if (swapAC) begin
xA <= xC;
yA <= yC;
uA <= uC;
vA <= vC;
xC <= xA;
yC <= yA;
uC <= uA;
vC <= vA;
end else if (swapBC) begin
xB <= xC;
yB <= yC;
uB <= uC;
vB <= vC;
xC <= xB;
yC <= yB;
uC <= uB;
vC <= vB;
end
end
end
end
assign ready = (state == IDLERUN) & triangleready;
assign finished = (state == IDLERUN) & trianglefinished;
always @(state or load or yA or yB or yC or xC or xB) begin
/* XST does not generate a pure combinatorial function if next_state is
* not pre-affected, maybe because of the unused states.
*/
next_state = IDLERUN;
triangleload = 1'b0;
loadall = 1'b0;
swapAB = 1'b0;
swapAC = 1'b0;
swapBC = 1'b0;
case (state)
IDLERUN: begin
if (load) begin
loadall = 1'b1;
//$display("Loading triangle: (%d,%d), (%d,%d), (%d,%d)", xa, ya, xb, yb, xc, yc);
//$display("Parameters: (%d,%d), (%d,%d), (%d,%d)", ua, va, ub, vb, uc, vc);
next_state = CHOOSEA;
end else next_state = IDLERUN;
end
CHOOSEA: begin
swapAB = (yB < yA) & (yB < yC);
swapAC = (yC < yA) & (yC < yB);
next_state = CHOOSEBC;
end
CHOOSEBC: begin
swapBC = (xC < xB);
next_state = START;
end
START: begin
//$display("Ordered points: (%d,%d), (%d,%d), (%d,%d)", xA, yA, xB, yB, xC, yC);
//$display("Parameters: (%d,%d), (%d,%d), (%d,%d)", uA, vA, uB, vB, uC, vC);
triangleload = 1'b1;
next_state = IDLERUN;
end
endcase
end
endmodule
| 8.312978 |
module trianglegenerator #(
parameter BITSIZE = 24,
parameter PHASESIZE = 16,
)(
input wire enable,
input wire lrclk,
input wire [PHASESIZE-1:0] freq,
output reg [BITSIZE-1:0] out,
);
reg [PHASESIZE-1:0] phase;
always @(posedge lrclk) begin
phase <= phase + freq;
end
always @(posedge lrclk) begin
if (!enable)
out <= 0;
else if (BITSIZE == PHASESIZE)
out <= phase;
else if (BITSIZE > PHASESIZE)
out <= {phase, {(BITSIZE-PHASESIZE){1'b0}}};
else
out <= phase[PHASESIZE-1:PHASESIZE-BITSIZE-1];
end
endmodule
| 6.971125 |
module triangle_area(
clk,
rst,
nd,
us_rfd,
a_x,
a_y,
b_x,
b_y,
p_x,
p_y,
ds_rfd,
rdy,
area
);
input clk;
input rst;
input nd;
output us_rfd; // Upstream ready for data
input [15:0] a_x;
input [15:0] a_y;
input [15:0] b_x;
input [15:0] b_y;
input [15:0] p_x;
input [15:0] p_y;
input ds_rfd;
output rdy; // Downstream ready for data
output [15:0] area;
localparam HALF = 16'h3800; // 0.5f
wire [15:0] ab_x;
wire [15:0] ab_y;
wire [15:0] ap_x;
wire [15:0] ap_y;
wire [15:0] mul_xy;
wire [15:0] mul_yx;
wire [15:0] cross;
wire ab_x_sub_rfd;
wire ab_y_sub_rfd;
wire ax_x_sub_rfd;
wire ap_y_sub_rfd;
wire ab_x_ap_y_mul_rfd;
wire ab_y_ap_x_mul_rfd;
wire xy_yx_sub_rfd;
wire ab_x_rdy;
wire ab_y_rdy;
wire ap_x_rdy;
wire ap_y_rdy;
wire mul_xy_rdy;
wire mul_yx_rdy;
wire cross_rdy;
fp_sub_micro ab_x_sub(
.clk(clk),
.ce(ab_x_ap_y_mul_rfd),
.operation_rfd(ab_x_sub_rfd),
.operation_nd(nd),
.sclr(rst),
.rdy(ab_x_rdy),
.a(a_x),
.b(b_x),
.result(ab_x)
);
fp_sub_micro ab_y_sub(
.clk(clk),
.ce(ab_y_ap_x_mul_rfd),
.operation_rfd(ab_y_sub_rfd),
.operation_nd(nd),
.sclr(rst),
.rdy(ab_y_rdy),
.a(a_y),
.b(b_y),
.result(ab_y)
);
fp_sub_micro ap_x_sub(
.clk(clk),
.ce(ab_y_ap_x_mul_rfd),
.operation_rfd(ax_x_sub_rfd),
.operation_nd(nd),
.sclr(rst),
.rdy(ap_x_rdy),
.a(a_x),
.b(p_x),
.result(ap_x)
);
fp_sub_micro ap_y_sub(
.clk(clk),
.ce(ab_x_ap_y_mul_rfd),
.operation_rfd(ap_y_sub_rfd),
.operation_nd(nd),
.sclr(rst),
.rdy(ap_y_rdy),
.a(a_y),
.b(p_y),
.result(ap_y)
);
fp_mul_micro ab_x_ap_y_mul(
.clk(clk),
.ce(xy_yx_sub_rfd),
.operation_rfd(ab_x_ap_y_mul_rfd),
.operation_nd(ab_x_rdy & ap_y_rdy),
.sclr(rst),
.rdy(mul_xy_rdy),
.a(ab_x),
.b(ap_y),
.result(mul_xy)
);
fp_mul_micro ab_y_ap_x_mul(
.clk(clk),
.ce(xy_yx_sub_rfd),
.operation_rfd(ab_y_ap_x_mul_rfd),
.operation_nd(ab_y_rdy & ap_x_rdy),
.sclr(rst),
.rdy(mul_yx_rdy),
.a(ab_y),
.b(ap_x),
.result(mul_yx)
);
fp_sub_micro xy_yx_sub(
.clk(clk),
.ce(halfer_rfd),
.operation_rfd(xy_yx_sub_rfd),
.operation_nd(mul_xy_rdy & mul_yx_rdy),
.sclr(rst),
.rdy(cross_rdy),
.a(mul_xy),
.b(mul_yx),
.result(cross)
);
// Calculate magnitude and return half
fp_mul_micro halfer(
.clk(clk),
.ce(ds_rfd),
.operation_rfd(halfer_rfd),
.operation_nd(cross_rdy),
.sclr(rst),
.rdy(rdy),
.a(cross),
.b(HALF),
.result(area)
);
assign us_rfd = ab_x_sub_rfd | ab_y_sub_rfd | ax_x_sub_rfd | ap_y_sub_rfd;
endmodule
| 9.005165 |
module: triangle_area
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module triangle_area_tb;
// Inputs
reg clk;
reg rst;
reg nd;
reg [15:0] a_x;
reg [15:0] a_y;
reg [15:0] b_x;
reg [15:0] b_y;
reg [15:0] p_x;
reg [15:0] p_y;
reg ds_rfd;
// Outputs
wire us_rfd;
wire rdy;
wire [15:0] area;
// Instantiate the Unit Under Test (UUT)
triangle_area uut (
.clk(clk),
.rst(rst),
.nd(nd),
.us_rfd(us_rfd),
.a_x(a_x),
.a_y(a_y),
.b_x(b_x),
.b_y(b_y),
.p_x(p_x),
.p_y(p_y),
.ds_rfd(ds_rfd),
.rdy(rdy),
.area(area)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
nd = 0;
a_x = 0;
a_y = 0;
b_x = 0;
b_y = 0;
p_x = 0;
p_y = 0;
ds_rfd = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst = 1;
repeat(4)
#10 clk = ~clk;
rst = 0;
forever
#10 clk = ~clk;
end
initial begin
#140;
ds_rfd = 1;
#80;
nd = 1;
a_x = 16'h0000; // A = (0.0, 0.0)
a_y = 16'h0000; //
b_x = 16'h3C00; // B = (1.0, 1.0)
b_y = 16'h3C00; //
p_x = 16'h3C00; // P = (1.0, 0.0)
p_y = 16'h0000; //
#20;
nd = 0;
#20;
nd = 1;
a_x = 16'h3C00; // A = (1.0, 1.0)
a_y = 16'h3C00; //
b_x = 16'h0000; // B = (0.0, 0.0)
b_y = 16'h0000; //
p_x = 16'h3C00; // P = (1.0, 0.0)
p_y = 16'h0000; //
#20;
nd = 0;
#20;
nd = 1;
a_x = 16'h0000; // A = (0.0, 0.0)
a_y = 16'h0000; //
b_x = 16'hB800; // B = (-0.5, -0.5)
b_y = 16'hB800; //
p_x = 16'hB800; // P = (-0.5, 0.0)
p_y = 16'h0000; //
end
endmodule
| 7.79315 |
module triangle_carrier (
sys_clk,
sys_ce,
divider,
carrier
);
input sys_clk, sys_ce;
input [7:0] divider; // clock divider, switching frequency = 50e6/(divider+1)/510 Hz
output wire [7:0] carrier;
reg [7:0] count = 0;
reg [7:0] div_count = 0;
reg dp = 1; //direction to count: 1 for up, 0 for down
wire CLK;
assign CLK = sys_clk & sys_ce;
assign carrier = count;
always @(posedge CLK) begin
if (div_count < divider) div_count <= div_count + 8'd1;
else begin
div_count <= 8'd0;
if (dp == 1'b1)
if (count < 8'hFF) count <= count + 1;
else //(count == 7'hFF)
begin
dp <= 1'b0;
count <= count - 1;
end
else //dp == 1'b0 <-- going down
if (count > 7'b0) count <= count - 1;
else //count == 0
begin
count <= count + 1;
dp <= 1'b1;
end
end
end
endmodule
| 8.004782 |
module triangle_channel (
note_in,
note_clk,
channel_en,
fx_sel,
clk50mhz,
wave_out
);
input [5:0] note_in;
input note_clk;
input channel_en;
input [1:0] fx_sel;
input clk50mhz;
output wire [3:0] wave_out;
wire [5:0] porta_out;
wire [5:0] fx_mux_out;
wire basefreq;
wire buffreq;
reg porta_en;
wire [1:0] porta_speed_sel;
assign porta_speed_sel = 1;
initial begin
porta_en = 0;
end
always @(posedge clk50mhz) begin
case (fx_sel)
0: begin
porta_en <= 0;
end
1: begin
porta_en <= 1;
end
2: begin
porta_en <= 0;
end
3: begin
porta_en <= 0;
end
default: begin
porta_en <= 0;
end
endcase
end
FX_porta tr_porta (
.note_in (note_in),
.note_clk (note_clk),
.note_out (porta_out),
.en (porta_en), //used to be butt_1
.clk50mhz (clk50mhz)
);
mux4to1 tr_FX_mux (
.in_a(note_in),
.in_b(porta_out),
.in_c(0),
.in_d(0),
.mux_sel(fx_sel),
.mux_out(fx_mux_out)
);
base_freq_genx64 tr_freqgen ( //SQUARE CHANNEL 1
.note_in (fx_mux_out),
.clk50mhz(clk50mhz),
.freq_out(basefreq)
);
BUFG freq3_bufg (
.I(basefreq),
.O(buffreq)
); //a clock buffer?
//SQUARE WAVE CHANNEL
trigen trgen1 (
.base_freq (buffreq),
.triangle_out (wave_out),
.en (channel_en)
);
endmodule
| 7.082626 |
module triangle_counter_8bit (
clk,
enable,
pulse,
sign, // 1 = negative, 0 = positive (signed bit for sine LUT)
out
);
input clk;
input enable;
input pulse;
reg direction; // 1 = right, 0 = left
output reg sign;
output reg [10:0] out;
always @(posedge clk) begin
if (!enable) begin
out <= 11'b0;
sign <= 1'b0; // Initialize as positive
direction <= 1'b1;
end else if (pulse) begin
// Moving to the right
if (direction) begin
if (out == 11'b11111111111) direction <= 1'b0; // Move left now
else out <= out + 1;
end // Moving to the left
else if (!direction) begin
if (out == 11'b0) begin
direction <= 1'b1; // Move right now
sign <= ~sign; // Change sign when hitting 1 from right
end else out <= out - 1;
end
end
end
endmodule
| 6.535482 |
module triangle_gen (
CLOCK_50,
KEY,
VGA_R,
VGA_CLK
);
input CLOCK_50;
input [3:0] KEY;
output [7:0] VGA_R;
output VGA_CLK;
reg [9:0] clk_div_cnt;
reg [7:0] dac_cnt;
wire sys_clk = CLOCK_50;
wire sys_rst_n = KEY[1];
assign VGA_R = dac_cnt;
assign VGA_CLK = clk_div_cnt[9];
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) begin
clk_div_cnt <= 10'd0;
end else begin
clk_div_cnt <= clk_div_cnt + 1'b1;
end
end
always @(posedge sys_clk, negedge sys_rst_n) begin
if (~sys_rst_n) begin
dac_cnt <= 8'd0;
end else begin
if (&clk_div_cnt) dac_cnt <= dac_cnt + 1'b1;
end
end
endmodule
| 6.994046 |
module testbench;
parameter PERIOD = 20;
reg i_clk, i_rst_n;
wire [3:0] o_dac;
triangle_gen gen_inst (
.MAX10_CLK1_50(i_clk),
.KEY({i_rst_n, 1'b0}),
.VGA_R(o_dac)
);
initial begin
i_clk = 0;
forever #(PERIOD / 2) i_clk = ~i_clk;
end
initial begin
i_rst_n = 1'b0;
@(negedge i_clk) i_rst_n = 1;
repeat (100000) @(negedge i_clk);
$finish;
end
endmodule
| 7.015571 |
module Triangle_Run ();
// Timing
reg CLK;
reg RES;
wire PHI1;
wire ACLK1;
wire nACLK2;
wire nLFO1;
wire nLFO2;
// Regs
reg W4008;
reg W400A;
reg W400B;
reg W401A;
reg W4015;
reg W4017;
reg n_R4015;
wire [7:0] DataBus;
wire [31:0] AuxOut;
// Tune CLK/ACLK timing according to 2A03
always #23.28 CLK = ~CLK;
// Modules for organizing the correct operation of ACLK and LFO
CLK_Divider div (
.n_CLK_frompad(~CLK),
.PHI0_tocore (PHI0),
.PHI2_fromcore(PHI2)
);
BogusCPU core (
.PHI0(PHI0),
.PHI1(PHI1),
.PHI2(PHI2)
);
ACLKGen aclk (
.PHI1(PHI1),
.PHI2(PHI2),
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.RES(RES)
);
SoftTimer softclk (
.PHI1(PHI1),
.ACLK1(ACLK1),
.nACLK2(nACLK2),
.RES(RES),
.n_R4015(n_R4015),
.W4017(W4017),
.DB(DataBus),
.DMCINT(1'b0),
.nLFO1(nLFO1),
.nLFO2(nLFO2)
);
// Modules for the triangle sound generator
wire [7:0] LC;
wire TRI_LC;
wire NOTRI;
wire [3:0] TRI_Out;
LengthCounter_PLA pla (
.DB(DataBus),
.LC_Out(LC)
);
LengthCounter length (
.nACLK2(nACLK2),
.ACLK1(ACLK1),
.RES(RES),
.W400x_load(W400B),
.n_R4015(n_R4015),
.W4015(W4015),
.LC(LC),
.dbit_ena(DataBus[2]),
.nLFO2(nLFO2),
.Carry_in(TRI_LC),
.NotCount(NOTRI)
);
TriangleChan triangle (
.PHI1(PHI1),
.ACLK1(ACLK1),
.RES(RES),
.DB(DataBus),
.W4008(W4008),
.W400A(W400A),
.W400B(W400B),
.W401A(W401A),
.nLFO1(nLFO1),
.TRI_LC(TRI_LC),
.NOTRI(NOTRI),
.LOCK(1'b0),
.TRI_Out(TRI_Out)
);
AUX aux (
.AUX_A(8'b0000_0000),
.AUX_B({11'b0000000_0000, TRI_Out}),
.BOut (AuxOut)
);
RegDriver reg_driver (
.PHI1(PHI1),
.W4008(W4008),
.W400A(W400A),
.W400B(W400B),
.W4015(W4015),
.DataBus(DataBus)
);
initial begin
$dumpfile("triangle_output.vcd");
$dumpvars(0, div);
$dumpvars(1, core);
$dumpvars(2, aclk);
$dumpvars(3, softclk);
$dumpvars(4, pla);
$dumpvars(5, length);
$dumpvars(6, triangle);
$dumpvars(7, AuxOut);
CLK <= 1'b0;
RES <= 1'b0;
W4008 <= 1'b0;
W400A <= 1'b0;
W400B <= 1'b0;
W401A <= 1'b0; // Debug reg, unused
W4015 <= 1'b0;
W4017 <= 1'b0;
n_R4015 <= 1'b1;
// Reset
RES <= 1'b1;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
RES <= 1'b0;
// Configure the registers of the entire system
W4015 <= 1'b1;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
W4015 <= 1'b0;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
W4008 <= 1'b1;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
W4008 <= 1'b0;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
W400A <= 1'b1;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
W400A <= 1'b0;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
W400B <= 1'b1;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
W400B <= 1'b0;
repeat (`CoreCyclesPerCLK) @(posedge CLK);
// Run the simulation in free flight to obtain sound
repeat (32768 * 128) @(posedge CLK);
$finish;
end
endmodule
| 7.465736 |
module BogusCPU (
PHI0,
PHI1,
PHI2
);
input PHI0;
output PHI1;
output PHI2;
assign PHI1 = ~PHI0;
assign PHI2 = PHI0;
endmodule
| 7.703679 |
module executes a "program" sequence of writes to various registers
module RegDriver (PHI1, W4008, W400A, W400B, W4015, DataBus);
input PHI1;
input W4008;
input W400A;
input W400B;
input W4015;
inout [7:0] DataBus;
// W4015 <= 00000 1 00 (Triangle Length counter enable: 1)
// W4008 <= 0 0001111 (Triangle length counter #carry in: 0, Linear counter reload: 0xf)
// W400A <= 0110 1001 (Freq Lo=0x69)
// W400B <= 11111 010 (Length=11111, Freq Hi=2)
assign DataBus = ~PHI1 ? (W4008 ? 8'b00001111 : (W400A ? 8'b01101001 : (W400B ? 8'b11111010 : (W4015 ? 8'b00000100 : 8'hzz)))) : 8'hzz;
endmodule
| 7.110462 |
module triangle_rasterizer (
clk,
rst,
tri_ready,
us_rfd,
v1_posX,
v1_posY,
v1_posZ,
v1_colR,
v1_colG,
v1_colB,
v1_colA,
v1_texX,
v1_texY,
v2_posX,
v2_posY,
v2_posZ,
v2_colR,
v2_colG,
v2_colB,
v2_colA,
v2_texX,
v2_texY,
v3_posX,
v3_posY,
v3_posZ,
v3_colR,
v3_colG,
v3_colB,
v3_colA,
v3_texX,
v3_texY,
f1_ready,
f1_posX,
f1_posY,
f1_posZ,
f1_colR,
f1_colG,
f1_colB,
f1_colA,
f1_texX,
f1_texY
);
/*** IOs ***/
input clk;
input rst;
input tri_ready; // Triangle ready for reading
input us_rfd;
// Vertex Inputs
input [15:0] v1_posX;
input [15:0] v1_posY;
input [15:0] v1_posZ;
input [15:0] v1_colR;
input [15:0] v1_colG;
input [15:0] v1_colB;
input [15:0] v1_colA;
input [15:0] v1_texX;
input [15:0] v1_texY;
input [15:0] v2_posX;
input [15:0] v2_posY;
input [15:0] v2_posZ;
input [15:0] v2_colR;
input [15:0] v2_colG;
input [15:0] v2_colB;
input [15:0] v2_colA;
input [15:0] v2_texX;
input [15:0] v2_texY;
input [15:0] v3_posX;
input [15:0] v3_posY;
input [15:0] v3_posZ;
input [15:0] v3_colR;
input [15:0] v3_colG;
input [15:0] v3_colB;
input [15:0] v3_colA;
input [15:0] v3_texX;
input [15:0] v3_texY;
// Fragment Outputs
output f1_ready; // Fragment 1 ready for output
output [15:0] f1_posX;
output [15:0] f1_posY;
output [15:0] f1_posZ;
output [15:0] f1_colR;
output [15:0] f1_colG;
output [15:0] f1_colB;
output [15:0] f1_colA;
output [15:0] f1_texX;
output [15:0] f1_texY;
/*** LOGIC ***/
wire [15:0] fp_minX, fp_minY, fp_maxX, fp_maxY;
bounding_box b_box (
.clk (clk),
.rst (rst),
.nd (tri_ready), //<--------- TODO!!!!
.us_rfd (us_rfd), //<--------- TODO!!!!
.v1_posX(v1_posX),
.v1_posY(v1_posY),
.v2_posX(v2_posX),
.v2_posY(v2_posY),
.v3_posX(v3_posX),
.v3_posY(v3_posY),
.ds_rfd (), //<----------TODO!!!!
.rdy (), //<----------TODO!!!!
.fp_minX(fp_minX),
.fp_maxX(fp_maxX),
.fp_minY(fp_minY),
.fp_maxY(fp_max)
);
/***
MODULE: fragment iterator = Iterates over bounding box with sampling points (int->float)
MODULE: calculate bayesian coordinates
MODULE: Triangle Area
MODULE: fragment clipper = Bounds checks bayesian coordinates of fragments
MODULE: attribute interpolator
***/
endmodule
| 7.964322 |
module triangle_rom (
input clk,
input [9:0] addr,
output reg [15:0] dout
);
always @(posedge clk) dout = addr * 9'd32 - 1'b1;
endmodule
| 7.610895 |
module TriangularWave (
input clk,
output [15:0] Triangularout,
input reset,
input [31:0] phase,
input [31:0] Step
);
reg [31:0] address;
reg [31:0] SynthesisedPhase;
initial begin
address = 32'd0;
end
/**********调用TriangularROM************/
TriangularROM ROM1 (
.address(SynthesisedPhase[31:21]),
.clock(clk),
.q(Triangularout)
);
always @(negedge clk) begin
address <= address + Step; //频率
SynthesisedPhase <= address + phase; //相位
if (reset == 0) begin
address <= 32'd0;
SynthesisedPhase <= 32'd0;
end
end
endmodule
| 7.059117 |
module is used for generating triangular waves.
Input is a clock enable signal to switch on the clock,
clock input signal and a active high reset signal to
power down the control circuit
Output are triangular waves of 4KHz waves
*/
`timescale 1 ns / 1 ns
module TriangularWaves
(
clk,
reset,
clk_enable,
ce_out,
Out5
);
input clk;
input reset;
input clk_enable;
output ce_out;
output signed [15:0] Out5; // int16
wire enb;
wire signed [15:0] Constant_out1; // int16
reg [15:0] Counter_Limited_count; // ufix16
wire [15:0] Counter_Limited_out1; // uint16
wire signed [15:0] Add_out1; // int16
wire switch_compare_1;
wire signed [15:0] Counter_Limited_out1_dtc; // int16
wire signed [15:0] Switch_out1; // int16
wire signed [15:0] Constant1_out1; // int16
wire signed [15:0] Add1_out1; // int16
assign Constant_out1 = 16'sd12499;
assign enb = clk_enable;
// Count limited, Unsigned Counter
// initial value = 0
// step value = 1
// count to value = 12499
always @(posedge clk or posedge reset)
begin : Counter_Limited_process
if (reset == 1'b1) begin
Counter_Limited_count <= 16'b0000000000000000;
end
else begin
if (enb) begin
if (Counter_Limited_count == 16'b0011000011010011) begin
Counter_Limited_count <= 16'b0000000000000000;
end
else begin
Counter_Limited_count <= Counter_Limited_count + 16'b1;
end
end
end
end
assign Counter_Limited_out1 = Counter_Limited_count;
//counter value instantenously subtracted from constant value 12499
assign Add_out1 = Constant_out1 - $signed({1'b0, Counter_Limited_out1});
//output of the two opposing counters is selected as per the following
assign switch_compare_1 = (Add_out1 >= 16'sb0001100001101001 ? 1'b1 :
1'b0);
assign Counter_Limited_out1_dtc = Counter_Limited_out1;
//output is selected from previous comparison
assign Switch_out1 = (switch_compare_1 == 1'b0 ? Counter_Limited_out1_dtc :
Add_out1);
assign Constant1_out1 = 16'sd9374;
//constant value is subtracted to create properly biased output
assign Add1_out1 = Switch_out1 - Constant1_out1;
assign Out5 = Add1_out1;
assign ce_out = clk_enable;
endmodule
| 8.297361 |
module Area (
input [11:0] x1,
input [11:0] y1,
input [11:0] x2,
input [11:0] y2,
input [11:0] x3,
input [11:0] y3,
output [21:0] s
);
reg [21:0] area = 0;
assign s = area;
//Utilizando a fórmula do Trabalho 2
wire [11:0] Sy2y3; //subtração y do ponto 2 e y do ponto 3
wire [11:0] Sy3y1; //subtração y do ponto 3 e y do ponto 1
wire [11:0] Sy1y2; //subtração y do ponto 1 e y do ponto 2
wire [21:0] Mx1, Mx2, Mx3, Ad; //multiplicação por x do ponto 1, x do ponto 2 e x do ponto 3, e adição de todos
wire signed [21:0] Div; //Divisão por 2
assign Sy2y3 = (y2 - y3);
assign Sy3y1 = (y3 - y1);
assign Sy1y2 = (y1 - y2);
assign Mx1 = (x1 * Sy2y3);
assign Mx2 = (x2 * Sy3y1);
assign Mx3 = (x3 * Sy1y2);
assign Ad = (Mx1 + Mx2 + Mx3);
assign Div = (Ad / 2);
always @(x1 or y1 or x2 or y2 or x3 or y3) begin
area = $abs(Div); //valor absoluto
end
endmodule
| 6.816576 |
module Mod (
input signed [17:0] i,
output signed [17:0] j
);
assign j = i[17] ? -i : i;
endmodule
| 6.917847 |
module Area (
input [8:0] x1,
input [8:0] y1,
input [8:0] x2,
input [8:0] y2,
input [8:0] x3,
input [8:0] y3,
output [17:0] s
);
wire [17:0] Ad1, Ad2; //adições
wire signed [17:0] Sub; //subtração de tudo
assign Ad1 = ((x1 * y2) + (y1 * x3) + (x2 * y3));
assign Ad2 = ((y1 * x2) + (x1 * y3) + (y2 * x3));
assign Sub = (Ad1 - Ad2);
Mod M (
Sub,
s
);
endmodule
| 6.816576 |
module trianguloVGA (
input CLOCK_50,
output [17:0] SRAM_ADDR,
inout [15:0] SRAM_DQ,
output SRAM_WE_N,
output SRAM_OE_N,
output SRAM_UB_N,
output SRAM_LB_N,
output SRAM_CE_N,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS
);
reg [10:0] cx = 0;
reg [ 9:0] cy = 0;
assign VGA_R = (v & t) ? 4'hf : 4'b0;
assign VGA_G = (v & r) ? 4'hf : 4'b0;
assign VGA_B = v ? 4'hf : 4'b0;
//a área visivel
wire v = (cx >= 285) & (cx < 1555) & (cy >= 35) & (cy < 515);
//retangulo
wire r = (cx >= 300) & (cx < 750) & (cy >= 50) & (cy < 300);
//triangulo
wire t;
wire [10:0] px = cx - 285;
wire [9:0] py = cy - 35;
memoria m1 (
CLOCK_50,
SRAM_ADDR,
SRAM_DQ,
SRAM_WE_N,
SRAM_OE_N,
SRAM_UB_N,
SRAM_LB_N,
SRAM_CE_N,
px[10:2],
py[9:1],
r
);
assign VGA_HS = cx >= 190;
assign VGA_VS = cy >= 2;
always @(posedge CLOCK_50) begin
if (cx == 1585) begin
if (cy == 525) begin
cy <= 0;
end else cy <= cy + 1;
cx <= 0;
end else begin
cx <= cx + 1;
end
end
endmodule
| 7.61779 |
module TriArr (
input [31:0] A,
input Enable,
output [31:0] B
);
genvar i;
generate
for (i = 0; i < 32; i = i + 1) bufif1 T (B[i], A[i], Enable);
endgenerate
endmodule
| 7.285133 |
module top (
en,
i,
o
);
input en;
input i;
output reg o;
always @(en or i) o <= (en) ? i : 1'bZ;
endmodule
| 6.541524 |
module tribuf16 (
output [15:0] out,
input [15:0] in,
input output_en
);
generate
genvar i;
for (i = 0; i < 16; i = i + 1) begin : tribufs
tribuf tbuf (
out[i],
in[i],
output_en
);
end
endgenerate
endmodule
| 7.451137 |
module tribuf8 (
output [7:0] out,
input [7:0] in,
input output_en
);
generate
genvar i;
for (i = 0; i < 8; i = i + 1) begin : tribufs
tribuf tbuf (
out[i],
in[i],
output_en
);
end
endgenerate
endmodule
| 8.142369 |
module triBuff #(
parameter SIZE = 32
) (
in,
oe,
out
);
input [SIZE-1:0] in;
input oe;
output [SIZE-1:0] out;
assign out = oe ? in : {SIZE{1'bz}};
endmodule
| 6.618813 |
module bmux (
ctl,
in_0,
in_1,
z
);
input ctl;
input [1:0] in_0, in_1;
output [1:0] z;
CDN_bmux2 g1 (
.sel0(ctl),
.data0(in_0[1]),
.data1(in_1[1]),
.z(z[1])
);
CDN_bmux2 g2 (
.sel0(ctl),
.data0(in_0[0]),
.data1(in_1[0]),
.z(z[0])
);
endmodule
| 6.96567 |
module CDN_flop (
clk,
d,
sena,
aclr,
apre,
srl,
srd,
q
);
input clk, d, sena, aclr, apre, srl, srd;
output q;
reg qi;
assign #1 q = qi;
always @(posedge clk or posedge apre or posedge aclr)
if (aclr) qi <= 0;
else if (apre) qi <= 1;
else if (srl) qi <= srd;
else begin
if (sena) qi <= d;
end
initial qi <= 1'b0;
endmodule
| 7.219105 |
module DAC (
add,
clk,
strobe,
WR,
Dout
);
input wire [11:0] add;
input wire clk;
input wire strobe;
output reg WR; //Equiv of ready?
output reg [7:0] Dout;
reg [7:0] Din = 8'b00000000;
reg up = 1;
reg [31:0] counter = 0;
parameter starting = 2'b00;
parameter pre_latch = 2'b01;
parameter latch = 2'b10;
parameter post_latch = 2'b11;
reg [1:0] state = pre_latch;
// Process: Address valid --> WR low --> Data valid
always @(negedge clk) begin
case (state)
// Starting idle state
// Checks for address 0x10d and sends to pre-latch if found.
// CURRENTLY UNUSED
starting: begin
// Output
//Dout <= 7'bz;
// Next State
//if((add[11:0] == 12'h10d) && (~strobe)) begin
state <= pre_latch;
WR <= 1'b0;
//end
end
// Pre-latch state
pre_latch: begin
// Output
if (counter == 200) begin // Smaller counter = higher frequency
counter <= 0;
if (up == 1) begin
Din <= Din + 1;
if (Din == 8'b11111110) begin
up <= 0;
end
end else begin
Din <= Din - 1;
if (Din == 8'b00000001) begin
up <= 1;
end
end
end else begin
counter <= counter + 1;
end
// Next State
state <= latch;
end
// Latch State
// Latches the value of Din to Dout
latch: begin
// Output
Dout <= Din;
// Next State
state <= post_latch;
end
// Post-Latch State
// Sets WR back to 1 before going back to idle.
post_latch: begin
// Output
WR <= 1'b1;
// Next State
state <= pre_latch;
end
endcase
end
endmodule
| 6.988086 |
module Trig #(
parameter sys_clk = 24_000_000,
parameter Trig_fre = 24 //1s run 10000 times_
) (
input clk,
input rst,
output Trig_sign //signal
);
reg [25:0] Trig_num; //1ڶӦʱӸ
reg [25:0] Trig_cnt;
reg [25:0] Trig_high;
reg [25:0] Trig_sign_r;
always @(posedge clk)
if (!rst) begin
Trig_cnt <= 0;
Trig_high <= sys_clk / (Trig_fre * 2778);
Trig_sign_r <= 0;
Trig_num <= sys_clk / Trig_fre;
end else if (Trig_cnt <= Trig_high) begin
Trig_sign_r <= 1;
Trig_cnt <= Trig_cnt + 1;
end else if (Trig_cnt > Trig_high && Trig_cnt < Trig_num) begin
Trig_sign_r <= 0;
Trig_cnt <= Trig_cnt + 1;
end else if (Trig_cnt == Trig_num) begin
Trig_cnt <= 0;
end
assign Trig_sign = Trig_sign_r;
endmodule
| 7.785482 |
module trigen (
base_freq,
triangle_out,
en
);
input base_freq;
input en;
reg [5:0] count; //max value 63
output reg [3:0] triangle_out;
initial begin
count = 0;
triangle_out = 0;
end
always @(posedge base_freq) begin
case (count)
0: triangle_out = 0;
1: triangle_out = 1;
2: triangle_out = 2;
3: triangle_out = 3;
4: triangle_out = 4;
5: triangle_out = 5;
6: triangle_out = 6;
7: triangle_out = 7;
8: triangle_out = 8;
9: triangle_out = 9;
10: triangle_out = 10;
11: triangle_out = 11;
12: triangle_out = 12;
13: triangle_out = 13;
14: triangle_out = 14;
15: triangle_out = 15;
16: triangle_out = 15;
17: triangle_out = 14;
18: triangle_out = 13;
19: triangle_out = 12;
20: triangle_out = 11;
21: triangle_out = 10;
22: triangle_out = 9;
23: triangle_out = 8;
24: triangle_out = 7;
25: triangle_out = 6;
26: triangle_out = 5;
27: triangle_out = 4;
28: triangle_out = 3;
29: triangle_out = 2;
30: triangle_out = 1;
31: triangle_out = 0;
default: triangle_out = 0;
endcase
if (en) begin
count = count + 1;
end else begin
count = 0;
end
if (count >= 32) begin
count = 0;
end
//if(!en)
//begin
// count = 0;
//end
end
endmodule
| 7.115324 |
module TriggerBlock (
dataIn,
triggerMask,
clk_PLL,
reset,
triggerOut,
dataOut
);
input [2:0] dataIn;
input [2:0] triggerMask;
input reset;
input clk_PLL;
output triggerOut;
output [2:0] dataOut;
wire [2:0] dataIn;
wire [2:0] triggerMask;
wire reset;
wire clk_PLL;
wire [2:0] dataOut;
reg triggerOut;
reg [2:0] newDataReg;
reg [2:0] prevDataReg;
reg [2:0] differenceReg;
reg [2:0] triggerMaskReg;
assign dataOut = newDataReg;
always @(posedge clk_PLL) begin
if (triggerOut == 1'b0) begin
prevDataReg = newDataReg;
newDataReg = dataIn;
differenceReg = prevDataReg ^ newDataReg;
triggerOut = |(differenceReg & triggerMask);
end else begin
newDataReg = dataIn;
end
if (reset == 1'b1) begin
triggerOut = 1'b0;
end
end
always @(triggerMask) begin
triggerMaskReg <= triggerMask;
end
endmodule
| 6.566925 |
module TriggerFSM (
input wire Clock,
input wire Reset,
input wire [7:0] Cmd,
output wire TriggerArmed
);
localparam TRIGGER_NOT_ARMED = 1'b0, TRIGGER_ARMED = 1'b1;
reg CurrentState = TRIGGER_NOT_ARMED;
reg NextState = TRIGGER_NOT_ARMED;
//uncomment for real
assign TriggerArmed = (CurrentState == TRIGGER_ARMED);
//assign TriggerArmed = 1'b1; //set just for simulation
//--------------------------------------------
//Synchronous State Transition
//--------------------------------------------
always @(posedge Clock) begin
if (Reset) CurrentState <= TRIGGER_NOT_ARMED;
else CurrentState <= NextState;
end
//------------------------------------------
//Conditional State Transition
//------------------------------------------
always @(*) begin
NextState = CurrentState;
case (CurrentState)
TRIGGER_NOT_ARMED: begin
if (Cmd == 65) NextState = TRIGGER_ARMED; //'A'
end
TRIGGER_ARMED: begin
if (Cmd == 97) NextState = TRIGGER_NOT_ARMED; //'a'
end
endcase
end
endmodule
| 7.307576 |
module trigger_adjust (
input CLK,
input RSTB,
input button_u,
input button_d,
output wire [11:0] TRIG
);
reg [ 3:0] button_counter;
reg [10:0] counter;
reg [ 1:0] state;
initial begin
button_counter = 4'd6;
end
always @(posedge CLK) begin
if (~RSTB) begin
button_counter <= 4'd0;
end else begin
case (state)
2'b00: begin
if (~button_u) begin
button_counter <= button_counter + 3'd1;
state <= 2'b01;
end
if (~button_d) begin
button_counter <= button_counter - 3'd1;
state <= 2'b01;
end
end
2'b01: begin
if (counter == 10'd10000) begin
counter <= 10'd0;
state <= 2'b00;
end else begin
counter <= counter + 10'd1;
state <= 2'b01;
end
end
default: begin
state <= 2'b00;
end
endcase
end
end
assign TRIG = {button_counter, 8'd0};
endmodule
| 6.747171 |
module trigstate (
term_hits,
clock,
wrenb,
wraddr,
din,
hit
);
input [31:0] term_hits;
input clock;
input wrenb;
input [1:0] wraddr;
input din;
output [2:0] hit;
reg [3:0] wrenb_sum;
always @* begin
wrenb_sum = 0;
wrenb_sum[wraddr] = wrenb;
end
trigsum hit_sum (
term_hits,
clock,
wrenb_sum[0],
din,
hit_term
);
trigsum else_sum (
term_hits,
clock,
wrenb_sum[1],
din,
else_term
);
trigsum capture_sum (
term_hits,
clock,
wrenb_sum[2],
din,
capture_term
);
// Sample output of hits...
reg [2:0] hit, next_hit;
always @(posedge clock) hit = next_hit;
always @* next_hit = {capture_term, else_term, hit_term};
endmodule
| 6.841926 |
module trigterm_32bit (
dataIn,
clock,
wrenb,
din,
dout,
hit
);
input [31:0] dataIn;
input clock, wrenb, din;
output dout;
output [7:0] hit;
trigterm_4bit nyb0 (
dataIn[3:0],
clock,
wrenb,
din,
n0,
hit[0]
);
trigterm_4bit nyb1 (
dataIn[7:4],
clock,
wrenb,
n0,
n1,
hit[1]
);
trigterm_4bit nyb2 (
dataIn[11:8],
clock,
wrenb,
n1,
n2,
hit[2]
);
trigterm_4bit nyb3 (
dataIn[15:12],
clock,
wrenb,
n2,
n3,
hit[3]
);
trigterm_4bit nyb4 (
dataIn[19:16],
clock,
wrenb,
n3,
n4,
hit[4]
);
trigterm_4bit nyb5 (
dataIn[23:20],
clock,
wrenb,
n4,
n5,
hit[5]
);
trigterm_4bit nyb6 (
dataIn[27:24],
clock,
wrenb,
n5,
n6,
hit[6]
);
trigterm_4bit nyb7 (
dataIn[31:28],
clock,
wrenb,
n6,
dout,
hit[7]
);
endmodule
| 7.80639 |
module trigterm_4bit (
addr,
clock,
wrenb,
din,
dout,
hit
);
input [3:0] addr;
input clock, wrenb, din;
output dout, hit;
SRLC16E ram (
.A0 (addr[0]),
.A1 (addr[1]),
.A2 (addr[2]),
.A3 (addr[3]),
.CLK(clock),
.CE (wrenb),
.D (din),
.Q15(dout),
.Q (hit)
);
endmodule
| 6.670147 |
module trigterm_edge (
dataIn,
dly_dataIn,
clock,
wrenb,
din,
hit
);
input [31:0] dataIn, dly_dataIn;
input clock, wrenb, din;
output hit;
wire [63:0] use_dataIn = {
dly_dataIn[31:30],
dataIn[31:30],
dly_dataIn[29:28],
dataIn[29:28],
dly_dataIn[27:26],
dataIn[27:26],
dly_dataIn[25:24],
dataIn[25:24],
dly_dataIn[23:22],
dataIn[23:22],
dly_dataIn[21:20],
dataIn[21:20],
dly_dataIn[19:18],
dataIn[19:18],
dly_dataIn[17:16],
dataIn[17:16],
dly_dataIn[15:14],
dataIn[15:14],
dly_dataIn[13:12],
dataIn[13:12],
dly_dataIn[11:10],
dataIn[11:10],
dly_dataIn[9:8],
dataIn[9:8],
dly_dataIn[7:6],
dataIn[7:6],
dly_dataIn[5:4],
dataIn[5:4],
dly_dataIn[3:2],
dataIn[3:2],
dly_dataIn[1:0],
dataIn[1:0]
};
wire [7:0] lohit, hihit;
trigterm_32bit loword (
use_dataIn[31:0],
clock,
wrenb,
din,
doutlo,
lohit
);
trigterm_32bit hiword (
use_dataIn[63:32],
clock,
wrenb,
doutlo,
dout,
hihit
);
assign hit = |{hihit, lohit};
endmodule
| 7.070796 |
module ram_dword (
clock,
addr,
wrenb,
wrdata,
rddata
);
input clock;
input [3:0] addr;
input wrenb;
input [31:0] wrdata;
output [31:0] rddata;
ram_byte byte0 (
clock,
addr,
wrenb,
wrdata[7:0],
rddata[7:0]
);
ram_byte byte1 (
clock,
addr,
wrenb,
wrdata[15:8],
rddata[15:8]
);
ram_byte byte2 (
clock,
addr,
wrenb,
wrdata[23:16],
rddata[23:16]
);
ram_byte byte3 (
clock,
addr,
wrenb,
wrdata[31:24],
rddata[31:24]
);
endmodule
| 6.805395 |
module ram_byte (
clock,
addr,
wrenb,
wrdata,
rddata
);
input clock;
input [3:0] addr;
input wrenb;
input [7:0] wrdata;
output [7:0] rddata;
RAM16X4S ram0 (
.A0 (addr[0]),
.A1 (addr[1]),
.A2 (addr[2]),
.A3 (addr[3]),
.WCLK(clock),
.WE (wrenb),
.D0 (wrdata[0]),
.D1 (wrdata[1]),
.D2 (wrdata[2]),
.D3 (wrdata[3]),
.O0 (rddata[0]),
.O1 (rddata[1]),
.O2 (rddata[2]),
.O3 (rddata[3])
);
RAM16X4S ram1 (
.A0 (addr[0]),
.A1 (addr[1]),
.A2 (addr[2]),
.A3 (addr[3]),
.WCLK(clock),
.WE (wrenb),
.D0 (wrdata[4]),
.D1 (wrdata[5]),
.D2 (wrdata[6]),
.D3 (wrdata[7]),
.O0 (rddata[4]),
.O1 (rddata[5]),
.O2 (rddata[6]),
.O3 (rddata[7])
);
endmodule
| 6.919521 |
module trigger_clock (
zero,
clk,
in,
out,
reset,
LED
);
input clk, zero; //clk to defin time bins, zero to set to zero counts in bins
input [31:0] in; //input from count module (button presses)
output reg [31:0] out; //output into time bins
output reg reset, LED; //reset back to count module, LED for tests
reg [31:0] i; //used to set time bin
reg [ 4:0] k; //used for bit shif
reg [31:0] intern; //used for bit shift
always @(posedge clk) begin
if (zero) //used to selectc appropriate bits for zeroing according to time bin
begin
if (k == 5'b0) out[7:0] = 8'b0;
else if (k == 5'b01000) out[15:8] = 8'b0;
else if (k == 5'b10000) out[23:16] = 8'b0;
else if (k == 5'b11000) out[31:17] = 8'b0;
end
else if (i==32'd100000000) // runs once per time bin
begin
intern=in << k; //internal variable assigned to the counts shifted into correct time bin placement
out = out + intern; //counts added to time bins of output
reset = 1; //reset back to count module, starts count afresh
LED = !LED;
i = 0;
k = k + 5'b01000; //changes bit shift amount for appropriate time bin.
end else // counts i until time step condition met.
begin
i <= i + 1;
reset <= 0;
end
end
endmodule
| 6.517647 |
module trigger_clock_hundreds (
clk,
in,
out,
reset,
LED,
PIN
);
input clk;
input [7:0] in;
output reg [7:0] out = 0;
output reg reset, LED, PIN;
reg [31:0] i;
always @(posedge clk) begin
if (i==32'd250000)//5ms time bin
begin
out <= in;
reset <= 1;
LED <= !LED;
i <= 0;
end else begin
i <= i + 1;
reset <= 0;
end
end
endmodule
| 6.517647 |
module trigger_control (
trigger_activation,
trigger_level,
trigger_set,
clk_20M,
data
);
input trigger_set;
input [7:0] trigger_level;
input [7:0] data;
input clk_20M;
reg activation;
reg temp_0, temp_1;
output trigger_activation;
//触发信号只在被测信号上升沿或者下降沿时拉高一个时钟周期
assign trigger_activation = ~temp_1 & temp_0;
//上升沿下降沿触发判定
always @(posedge clk_20M) begin
if (data > trigger_level) begin
if (trigger_set == 1'b0) activation <= 1;
else activation <= 0;
end else begin
if (trigger_set == 1'b0) activation <= 0;
else activation <= 1;
end
end
always @(posedge clk_20M) begin //00,10,11,11,11,01,00 只捕获上升沿
temp_0 <= activation;
temp_1 <= temp_0;
end
endmodule
| 7.10293 |
module Trigger_Controller #(
parameter DATA_WIDTH = 8
) (
input i_sys_clk,
input [DATA_WIDTH-1:0] i_data,
input [$clog2(DATA_WIDTH)-1:0] i_channel_select,
input i_trigger_type,
input i_enable,
input i_sample_clk_posedge,
input i_trigger_delay_en,
input [7:0] i_trigger_delay,
output o_triggered_state,
output o_event_pulse
);
reg [DATA_WIDTH-1:0] r_last;
reg r_trigger_event;
wire pe, ne, w_trigger_pulse;
reg [7:0] trigger_delay_count;
wire delayed_trigger_event;
assign w_trigger_pulse = ((pe & i_trigger_type) | (ne & ~i_trigger_type)) & i_enable;
assign o_triggered_state = i_trigger_delay_en ? delayed_trigger_event : r_trigger_event;
assign o_event_pulse = (r_last != i_data) & i_sample_clk_posedge;
always @(posedge i_sys_clk) begin
if (i_sample_clk_posedge || !i_enable) begin
r_last <= i_data;
end
end // End always
// Posedge detection
assign pe = i_data[i_channel_select] & ~r_last[i_channel_select];
// Negedge detection
assign ne = ~i_data[i_channel_select] & r_last[i_channel_select];
always @(posedge i_sys_clk) begin
if (!i_enable) begin
r_trigger_event <= 0;
end else if (i_enable & w_trigger_pulse & i_sample_clk_posedge) begin
r_trigger_event <= 1;
end
end // End always
// trigger delay if enabled
assign delayed_trigger_event = (trigger_delay_count == i_trigger_delay);
always @(posedge i_sys_clk) begin
if (r_trigger_event) begin
if (i_sample_clk_posedge) begin
trigger_delay_count <= trigger_delay_count + 1;
end
end else begin
trigger_delay_count <= 0;
end
end
endmodule
| 6.831052 |
module Trigger_Controller_tb;
parameter DATA_WIDTH = 8;
reg clk, sample_clk_posedge, rst, enable, trig_type;
reg [ 2:0] channel_select;
reg [11:0] count;
wire w_triggered_state, w_trigger_pulse, w_event_pulse;
Trigger_Controller #(
.DATA_WIDTH(DATA_WIDTH)
) DUT (
.i_data(count[11:4]),
.i_channel_select(channel_select),
.i_trigger_type(trig_type),
.i_enable(enable),
.i_sys_clk(clk),
.i_sample_clk_posedge(sample_clk_posedge),
.o_triggered_state(w_triggered_state),
.o_event_pulse(w_event_pulse)
);
always #2 clk = ~clk;
initial begin
clk = 0;
sample_clk_posedge = 0;
rst = 0;
enable = 0;
trig_type = 1;
channel_select = 2;
count = 0;
#5 rst = 1;
#5 enable = 1;
end
always @(posedge clk) begin
count <= count + 1;
if (count % 3 == 0) begin
sample_clk_posedge <= 1;
end else begin
sample_clk_posedge <= 0;
end
end // End always
initial #550 $finish;
endmodule
| 6.831052 |
module Trigger_Generator (
input i_clk,
input i_rst,
input i_en, //ʹźţЧ
input i_out_level, //ƽ
input [3:0] i_width,
output o_trig
);
localparam ST_WAIT = 2'd0;
localparam ST_START = 2'd1;
localparam ST_HOLD = 2'd2;
localparam ST_END = 2'd3;
//״̬
reg [1:0] state_current = 0;
reg [1:0] state_next = 0;
//
reg [3:0] reg_hold_cnt = 0;
reg [1:0] reg_en_rise = 0;
reg reg_trig = 0; //
//־
wire flg_en; //ʹźЧ
reg flg_hold = 0; //ִﵽʱ
//
reg buffer_out_level = 1; //Ĭߵƽ
assign flg_en = (reg_en_rise == 2'b01);
assign o_trig = reg_trig;
//źŻ
always @(posedge i_clk or negedge i_rst) begin
//͵ƽλ
if (!i_rst) begin
buffer_out_level <= 1;
end else begin
buffer_out_level <= i_out_level;
end
end
//״ִ̬
always @(posedge i_clk or negedge i_rst) begin
//͵ƽλ
if (!i_rst) begin
reg_trig <= 0;
end else if (state_current == ST_HOLD) begin
reg_trig <= buffer_out_level;
end else begin
reg_trig <= !buffer_out_level;
end
end
//״̬
always @(*) begin
case (state_current)
ST_WAIT: begin
if (flg_en) begin
state_next <= ST_START;
end else begin
state_next <= ST_WAIT;
end
end
ST_START: begin
state_next <= ST_HOLD;
end
ST_HOLD: begin
if (flg_hold) begin
state_next <= ST_END;
end else begin
state_next <= ST_HOLD;
end
end
ST_END: begin
if (!flg_en) begin
state_next <= ST_WAIT;
end else begin
state_next <= ST_END;
end
end
endcase
end
//״ֵ̬
always @(posedge i_clk or negedge i_rst) begin
//͵ƽλ
if (!i_rst) begin
state_current <= ST_WAIT;
end else begin
state_current <= state_next;
end
end
//ʹźؼ
always @(posedge i_clk or negedge i_rst) begin
//͵ƽλ
if (!i_rst) begin
reg_en_rise <= 0;
end else begin
reg_en_rise <= {reg_en_rise[0], i_en};
end
end
//ּ
always @(posedge i_clk or negedge i_rst) begin
//͵ƽλ
if (!i_rst) begin
flg_hold <= 0;
reg_hold_cnt <= 0;
end else if (state_current == ST_HOLD) begin
if (reg_hold_cnt < i_width) reg_hold_cnt <= reg_hold_cnt + 1;
else begin
flg_hold <= 1;
reg_hold_cnt <= i_width;
end
end else begin
flg_hold <= 0;
reg_hold_cnt <= 0;
end
end
endmodule
| 8.536187 |
module trigger_in (
input wire trigger_in_pc, // PC mode trigger in
input wire trigger_in_external, // enternal mode trigger in
input wire trig_source, // 0 is PC trigger, 1 is external trigger
input wire clock, // input clock
input wire reset, // Opal Kelly reset
input wire resetflag, // 1 if request for no output waveform
input wire channel_disable, // 1 if request to disable the channel
input wire channel_is_disable, // 1 if the channel status is disabled
output reg flag, // 1 to output waveform
output reg new_trig // 1 if detect overlapped trigger in
);
wire trigger_in;
wire present_stage;
reg previous_stage;
reg prev_trig;
reg prev_flag;
assign trigger_in = channel_is_disable ? 1'b0
: (trig_source == 1'b1) ? trigger_in_external
: trigger_in_pc;
always @(negedge clock) begin
prev_trig <= trigger_in;
if (reset | resetflag | channel_disable | channel_is_disable) begin
prev_flag <= 1'b0;
end else begin
prev_flag <= flag;
end
if (reset | resetflag | channel_disable | channel_is_disable) begin
flag <= 1'b0;
end else if (trigger_in && ~prev_trig) begin
flag <= 1'b1;
end
end
always @(negedge clock) begin
if (reset | resetflag | channel_disable | channel_is_disable) new_trig <= 1'b0;
else if (trigger_in && ~prev_trig && prev_flag) new_trig <= 1'b1;
else new_trig <= 1'b0;
end
endmodule
| 6.826764 |
module trigger_info_fifo (
clk_i,
rst_i,
info_i,
wr_i,
wr_ce_i,
addr_i,
info_o,
rd_i
);
localparam INFO_BITS = `INFO_BITS;
localparam NUM_L4 = `SCAL_NUM_L4;
`include "clogb2.vh"
localparam NL4_BITS = clogb2(NUM_L4 - 1);
input clk_i;
input rst_i;
input [INFO_BITS*NUM_L4-1:0] info_i;
input wr_ce_i;
input [NUM_L4-1:0] wr_i;
input [NL4_BITS-1:0] addr_i;
output [INFO_BITS-1:0] info_o;
input rd_i;
wire [INFO_BITS-1:0] info_in [NUM_L4-1:0];
wire [INFO_BITS-1:0] info_out[NUM_L4-1:0];
generate
genvar ii;
for (ii = 0; ii < NUM_L4; ii = ii + 1) begin : VEC
assign info_in[ii] = info_i[INFO_BITS*ii+:INFO_BITS];
wire rd_en = (rd_i && addr_i == ii);
// These are 256 deep. This puts them as 9K BRAMs.
trigger_info_buffer info_buf (
.clk (clk_i),
.srst (rst_i),
.din (info_in[ii]),
.wr_en(wr_i[ii] && wr_ce_i),
.dout (info_out[ii]),
.rd_en(rd_en)
);
end
endgenerate
reg [INFO_BITS-1:0] info_out_reg = {INFO_BITS{1'b0}};
always @(posedge clk_i) begin
info_out_reg <= info_out[addr_i];
end
assign info_o = info_out_reg;
endmodule
| 7.297019 |
module trigger_input #(
parameter R = 8,
N = 3
) (
input wire clk,
rst,
input wire [R-1:0] trig_in, // input for trigger signals
input wire [R-1:0] trig_sel, // trigger selection
output wire trig_tick // output tick
);
//signal declaration
reg [N-1:0] cnt;
reg [N-1:0] cnt_next;
reg [2-1:0] state, state_next;
reg tirgger_now, tirgger_last;
localparam [2-1:0] // 8 posible states
idle = 2'd0, wait1 = 2'd1;
// body
always @(posedge clk)
if (rst) begin
cnt <= {N{1'b0}};
state <= 0;
tirgger_now <= 0;
tirgger_last <= 0;
end else begin
cnt <= cnt_next;
state <= state_next;
tirgger_now <= |(trig_in & trig_sel);
tirgger_last <= tirgger_now;
end
// next-state logic
always @* begin
if (state == idle) begin
if ({tirgger_now, tirgger_last} == 2'b10) begin
state_next = wait1;
cnt_next = {{N - 1{1'b0}}, 1'b1};
end else begin
state_next = idle;
cnt_next = {N{1'b0}};
end
end else begin
if (&cnt) begin
state_next = idle;
cnt_next = {N{1'b0}};
end else begin
state_next = wait1;
cnt_next = cnt + 1'b1;
end
end
end
// output logic
assign trig_tick = (state == wait1);
endmodule
| 6.826347 |
module trigger_signal_gen (
clock,
reset,
output_trigger_signal
);
input clock, reset;
output output_trigger_signal;
reg [15:0] counter;
reg output_trigger_signal_gen;
always @(posedge clock or negedge reset) begin
if (!reset) begin
counter <= 8'h00;
output_trigger_signal_gen <= 1'h0;
end else begin
counter <= counter + 1'h1;
if (counter <= 16'hFFF0) output_trigger_signal_gen <= 1'h0;
else if (counter <= 16'hFFFE) output_trigger_signal_gen <= 1'h1;
else begin
output_trigger_signal_gen <= 1'h0;
counter <= 16'h0000;
end
end
end
assign output_trigger_signal = output_trigger_signal_gen;
endmodule
| 6.775305 |
module: trigger_top_v2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`include "wb_interface.vh"
module trigger_top_test;
// Inputs
reg [7:0] d1_trig_i;
reg [7:0] d2_trig_i;
reg [7:0] d3_trig_i;
reg [7:0] d4_trig_i;
reg [7:0] d1_pwr_i;
reg [7:0] d2_pwr_i;
reg [7:0] d3_pwr_i;
reg [7:0] d4_pwr_i;
reg fclk_i;
reg sclk_i;
reg sce_i;
reg pps_flag_fclk_i;
reg [2:0] l4_ext_i;
reg disable_i;
// Outputs
wire trig_o;
wire [3:0] trig_l4_o;
wire [8:0] trig_delay_o;
wire [31:0] trig_info_o;
// Bidirs
wire [`WBIF_SIZE-1:0] scal_wbif_io;
wire [`WBIF_SIZE-1:0] trig_wbif_io;
// Instantiate the Unit Under Test (UUT)
trigger_top_v2 uut (
.d1_trig_i(d1_trig_i),
.d2_trig_i(d2_trig_i),
.d3_trig_i(d3_trig_i),
.d4_trig_i(d4_trig_i),
.d1_pwr_i(d1_pwr_i),
.d2_pwr_i(d2_pwr_i),
.d3_pwr_i(d3_pwr_i),
.d4_pwr_i(d4_pwr_i),
.fclk_i(fclk_i),
.sclk_i(sclk_i),
.sce_i(sce_i),
.pps_flag_fclk_i(pps_flag_fclk_i),
.l4_ext_i(l4_ext_i),
.scal_wbif_io(scal_wbif_io),
.trig_wbif_io(trig_wbif_io),
.disable_i(disable_i),
.trig_o(trig_o),
.trig_l4_o(trig_l4_o),
.trig_delay_o(trig_delay_o),
.trig_info_o(trig_info_o)
);
initial begin
// Initialize Inputs
d1_trig_i = 0;
d2_trig_i = 0;
d3_trig_i = 0;
d4_trig_i = 0;
d1_pwr_i = 0;
d2_pwr_i = 0;
d3_pwr_i = 0;
d4_pwr_i = 0;
fclk_i = 0;
sclk_i = 0;
sce_i = 0;
pps_flag_fclk_i = 0;
l4_ext_i = 0;
disable_i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.643681 |
module TrigMeas (
FAST_CK,
RSTb,
START_TDC,
STOP_TDC,
ALL_CLEAR,
TDC_SELECT,
TRIGGER_TIME_FIFO_RD,
TRIGGER_TIME_FIFO_CK,
TRIGGER_TIME_FIFO,
TRIGGER_TIME_FIFO_FULL,
TRIGGER_TIME_FIFO_EMPTY
);
input FAST_CK, RSTb, START_TDC, STOP_TDC, ALL_CLEAR;
input TDC_SELECT, TRIGGER_TIME_FIFO_RD, TRIGGER_TIME_FIFO_CK;
output [7:0] TRIGGER_TIME_FIFO;
output TRIGGER_TIME_FIFO_FULL, TRIGGER_TIME_FIFO_EMPTY;
wire [7:0] trig_time_lo, trig_time_hi;
wire time_valid_lo, time_valid_hi;
LoResTdc ATrgTdc (
.CLK (FAST_CK),
.RSTb (RSTb),
.START(START_TDC),
.STOP (STOP_TDC),
.TIME (trig_time_lo),
.VALID(time_valid_lo)
);
HiResTdc BTrgTdc (
.CLK (FAST_CK),
.RSTb (RSTb),
.START(START_TDC),
.STOP (STOP_TDC),
.TIME (trig_time_hi),
.VALID(time_valid_hi)
);
TdcFifo_1024x8 TrigTimeFifo (
.data(TDC_SELECT ? trig_time_hi : trig_time_lo),
.wrclk(FAST_CK),
.wrreq(TDC_SELECT ? time_valid_hi : time_valid_lo),
.q(TRIGGER_TIME_FIFO),
.rdclk(TRIGGER_TIME_FIFO_CK),
.rdreq(TRIGGER_TIME_FIFO_RD),
.rdempty(TRIGGER_TIME_FIFO_EMPTY),
.rdfull(TRIGGER_TIME_FIFO_FULL)
);
endmodule
| 6.989865 |
module trign01a (
clk,
reset_n,
in,
trigger
);
input clk;
input reset_n;
input in;
output trigger;
reg r_trigger;
reg r_stage1;
reg r_stage2;
wire w_trigger_neg;
assign trigger = r_trigger;
assign w_trigger_neg = ~r_stage1 & r_stage2;
always @(posedge clk or negedge reset_n)
if (~reset_n) begin
r_trigger <= #`D 1'b0;
r_stage1 <= #`D 1'b0;
r_stage2 <= #`D 1'b0;
end else begin
r_trigger <= #`D w_trigger_neg;
r_stage1 <= #`D in;
r_stage2 <= #`D r_stage1;
end
endmodule
| 6.967186 |
module dividor (
clk,
inp,
rst,
out
);
input clk;
input [`INPUT_WIDTH-1:0] inp;
input rst;
//////////////inputs/////////////////
output reg [`INPUT_WIDTH-1:0] out;
//////////////output/////////////////
wire [`INPUT_WIDTH-1:0] DIVISOR = `INPUT_WIDTH'd360;
always @(posedge clk)
// modulo division
if (rst)
out <= 8'd0;
else out <= inp % DIVISOR;
endmodule
| 7.703792 |
module trigp01a (
clk,
reset_n,
in,
trigger
);
input clk;
input reset_n;
input in;
output trigger;
reg r_trigger;
reg r_stage1;
reg r_stage2;
wire w_trigger_pos;
assign trigger = r_trigger;
assign w_trigger_pos = r_stage1 & ~r_stage2;
always @(posedge clk or negedge reset_n)
if (~reset_n) begin
r_trigger <= #`D 1'b0;
r_stage1 <= #`D 1'b0;
r_stage2 <= #`D 1'b0;
end else begin
r_trigger <= #`D w_trigger_pos;
r_stage1 <= #`D in;
r_stage2 <= #`D r_stage1;
end
endmodule
| 6.724178 |
module trig_cnt (
input gclk_40m,
input l0,
input l1,
input l2a,
input l2r,
input l1out_c,
input rdocmd_c,
input abortcmd_c,
input evcntres,
input bcntres,
input trigcnt_clr,
output reg l1out = 1'b0,
output reg rdocmd = 1'b0,
output reg abortcmd = 1'b0, //width: 12 clocks
output reg [31:0] l0_cnt = 32'h0,
output reg [31:0] l1_cnt = 32'h0,
output reg [31:0] l2a_cnt = 32'h0,
output reg [31:0] l2r_cnt = 32'h0,
output reg [31:0] l1out_cnt = 32'h0,
output reg [31:0] rdocmd_cnt = 32'h0,
output reg [31:0] abortcmd_cnt = 32'h0,
output reg [11:0] bunch_cnt = 12'h0,
output reg [23:0] event_cnt = 24'h0,
input reset
);
parameter st0 = 0;
parameter st1 = 1;
reg sta = st0, stb = st0, stc = st0;
reg [3:0] clkcnta = 4'b0, clkcntb = 4'b0, clkcntc = 4'b0;
always @(posedge gclk_40m)
if (reset) begin
l1out <= 1'b0;
clkcnta <= 4'd0;
sta <= st0;
end else
case (sta)
st0: begin
l1out <= 1'b0;
clkcnta <= 4'd0;
if (l1out_c) sta <= st1;
else sta <= st0;
end
st1: begin
l1out <= 1'b1;
clkcnta <= clkcnta + 4'd1;
if (clkcnta == 4'd12) sta <= st0;
else sta <= st1;
end
default: begin
l1out <= 1'b0;
clkcnta <= 4'd0;
sta <= st0;
end
endcase
//rdocmd
always @(posedge gclk_40m)
if (reset) begin
rdocmd <= 1'b0;
clkcntb <= 4'd0;
stb <= st0;
end else
case (stb)
st0: begin
rdocmd <= 1'b0;
clkcntb <= 4'd0;
if (rdocmd_c) stb <= st1;
else stb <= st0;
end
st1: begin
rdocmd <= 1'b1;
clkcntb <= clkcntb + 4'd1;
if (clkcntb == 4'd12) stb <= st0;
else stb <= st1;
end
default: begin
rdocmd <= 1'b0;
clkcntb <= 4'd0;
stb <= st0;
end
endcase
//abortcmd
always @(posedge gclk_40m)
if (reset) begin
abortcmd <= 1'b0;
clkcntc <= 4'd0;
stc <= st0;
end else
case (stc)
st0: begin
abortcmd <= 1'b0;
clkcntc <= 4'd0;
if (abortcmd_c) stc <= st1;
else stc <= st0;
end
st1: begin
abortcmd <= 1'b1;
clkcntc <= clkcntc + 4'd1;
if (clkcntb == 4'd12) stc <= st0;
else stc <= st1;
end
default: begin
abortcmd <= 1'b0;
clkcntc <= 4'd0;
stc <= st0;
end
endcase
// l0_cnt
always @(posedge gclk_40m)
if (reset) l0_cnt <= 32'h0;
else if (trigcnt_clr) l0_cnt <= 32'h0;
else if (l0) l0_cnt <= l0_cnt + 32'h1;
else l0_cnt <= l0_cnt;
always @(posedge gclk_40m)
if (reset) l1_cnt <= 32'h0;
else if (trigcnt_clr) l1_cnt <= 32'h0;
else if (l1) l1_cnt <= l1_cnt + 32'h1;
else l1_cnt <= l1_cnt;
always @(posedge gclk_40m)
if (reset) l2a_cnt <= 32'h0;
else if (trigcnt_clr) l2a_cnt <= 32'h0;
else if (l2a) l2a_cnt <= l2a_cnt + 32'h1;
else l2a_cnt <= l2a_cnt;
always @(posedge gclk_40m)
if (reset) l2r_cnt <= 32'h0;
else if (trigcnt_clr) l2r_cnt <= 32'h0;
else if (l2r) l2r_cnt <= l2r_cnt + 32'h1;
else l2r_cnt <= l2r_cnt;
always @(posedge gclk_40m)
if (reset) l1out_cnt <= 32'h0;
else if (trigcnt_clr) l1out_cnt <= 32'h0;
else if (l1out_c) l1out_cnt <= l1out_cnt + 32'h1;
else l1out_cnt <= l1out_cnt;
always @(posedge gclk_40m)
if (reset) rdocmd_cnt <= 32'h0;
else if (trigcnt_clr) rdocmd_cnt <= 32'h0;
else if (rdocmd_c) rdocmd_cnt <= rdocmd_cnt + 32'h1;
else rdocmd_cnt <= rdocmd_cnt;
always @(posedge gclk_40m)
if (reset) abortcmd_cnt <= 32'h0;
else if (trigcnt_clr) abortcmd_cnt <= 32'h0;
else if (abortcmd_c) abortcmd_cnt <= abortcmd_cnt + 32'h1;
else abortcmd_cnt <= abortcmd_cnt;
always @(posedge gclk_40m)
if (reset) bunch_cnt <= 12'h0;
else if (trigcnt_clr || bcntres) bunch_cnt <= 12'h0;
else bunch_cnt <= bunch_cnt + 12'h1;
always @(posedge gclk_40m)
if (reset) event_cnt <= 24'h0;
else if (trigcnt_clr || evcntres) event_cnt <= 24'h0;
else if (l1) event_cnt <= event_cnt + 24'h1;
else event_cnt <= event_cnt;
endmodule
| 7.095927 |
module trig_count (
j,
switch,
out,
LED2
);
input j, switch;
reg [5:0] intr;
output reg [5:0] out;
output reg LED2 = 0;
always @(posedge j or posedge switch) begin
if (j) begin
LED2 <= !LED2;
out <= intr;
//intr<=6'b0;
end else if (switch) begin
intr <= intr + 1;
end
end
endmodule
| 6.602655 |
module trig_generator (
clk,
rst_n,
address,
wdata,
xfc,
trig_i2si_fifo_overrun_clr,
trig_i2so_fifo_underrun_clr,
trig_filter_ovf_flag_clear
);
// Inputs
input clk; // master clock
input rst_n; // reset
input [10:0] address; // register address
input [7:0] wdata; // data to be written for a write op
input xfc; // transfer complete
// Outputs
output reg trig_i2si_fifo_overrun_clr; // address = 0x008 bit 0
output reg trig_i2so_fifo_underrun_clr; // address = 0x008 bit 2
output reg trig_filter_ovf_flag_clear; // address = 0x008 bit 4
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
trig_i2si_fifo_overrun_clr <= 0;
trig_i2so_fifo_underrun_clr <= 0;
trig_filter_ovf_flag_clear <= 0;
end else begin
// initializing trigger bits to zero
trig_i2si_fifo_overrun_clr <= 0;
trig_i2so_fifo_underrun_clr <= 0;
// triggering when file transfer is complete and address being written to is 0x00c
if (address == 11'h008 && xfc == 1) begin
// if written to bit 0 of 0x008, trig_i2si_fifo_overrun_clr is triggered
if (wdata[0]) trig_i2si_fifo_overrun_clr <= 1;
// if written to bit 2 of 0x008, trig_i2so_fifo_underrun_clr is triggered
if (wdata[2]) trig_i2so_fifo_underrun_clr <= 1;
// if written to bit 4 of 0x008, trig_filter_ovf_flag_clear is triggered
if (wdata[4]) trig_filter_ovf_flag_clear <= 1;
end
end
end
endmodule
| 6.647224 |
module trig_generator_testbench;
// Inputs
reg [10:0] address;
reg [ 7:0] wdata;
reg wxfc;
reg clk;
reg [31:0] count;
wire rst_n;
// Outputs
wire trig_i2si_fifo_overrun_clr;
wire trig_i2so_fifo_underrun_clr;
// Instantiate the Unit Under Test (UUT)
trig_generator uut (
.address(address),
.wdata(wdata),
.wxfc(wxfc),
.clk(clk),
.rst_n(rst_n),
.trig_i2si_fifo_overrun_clr(trig_i2si_fifo_overrun_clr),
.trig_i2so_fifo_underrun_clr(trig_i2so_fifo_underrun_clr)
);
always begin
forever begin
#5 clk = ~clk;
count = count + 1;
end
end
assign rst_n = !(count < 20);
initial begin
// Initialize Inputs
count = 0;
clk = 0;
wdata = 8'hFF;
// Wait 100 ns for global reset to finish
#1000;
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
address <= 0;
xfc <= 0;
end
else if (address < 11'h20) //hex 20 12 bits of data
begin
address <= address + 4;
xfc <= 1;
end else xfc <= 0;
end
endmodule
| 6.647224 |
module trig_generator_testbench1;
// Inputs
reg [10:0] address;
reg [ 7:0] wdata;
reg xfc;
reg clk;
reg [31:0] count;
wire rst_n;
// Outputs
wire trig_i2si_fifo_overrun_clr;
wire trig_i2so_fifo_underrun_clr;
// Instantiate the Unit Under Test (UUT)
trig_generator uut (
.address(address),
.wdata(wdata),
.xfc(xfc),
.clk(clk),
.rst_n(rst_n),
.trig_i2si_fifo_overrun_clr(trig_i2si_fifo_overrun_clr),
.trig_i2so_fifo_underrun_clr(trig_i2so_fifo_underrun_clr)
);
always begin
// Generates a clock with a clock cycle of 10 ns
forever begin
#5 clk = ~clk;
count = count + 1;
end
end
assign rst_n = !(count < 20);
initial begin
// Initialize Inputs
count = 0;
clk = 0;
address = 11'h00c;
// Wait 100 ns for global reset to finish
#1000;
end
always @(posedge clk or negedge rst_n) begin
// initializing xfc and wdata to 0
if (~rst_n) begin
wdata <= 0;
xfc <= 0;
end /*
if wdata is 12 bits of data and less than the hex value 20 wdata is
and file transfer is set to 1 - complete
*/
else if (wdata < 11'h020) begin
wdata <= wdata + 1;
xfc <= 1;
end else xfc <= 0;
end
endmodule
| 6.647224 |
module triled (
RED,
GREEN,
BLUE
, rgb
);
output RED;
output GREEN;
output BLUE;
input [2:0] rgb;
assign {RED, GREEN, BLUE} = rgb;
endmodule
| 6.791025 |
module TriLoc #(
parameter N = 8
) (
input signed [N-1:0] xA,
yA,
xB,
yB,
xC,
yC,
input signed [ N:0] rA,
rB,
rC,
output signed [N+3:0] xM,
yM
);
wire signed [N+1:0] xD, yD, xE, yE, xF, yF;
one_vertex D (
.xU(xB),
.yU(yB),
.xV(xC),
.yV(yC),
.xW(xA),
.yW(yA),
.rU(rB),
.rV(rC),
.rW(rA),
.xT(xD),
.yT(yD)
);
one_vertex E (
.xU(xC),
.yU(yC),
.xV(xA),
.yV(yA),
.xW(xB),
.yW(yB),
.rU(rC),
.rV(rA),
.rW(rB),
.xT(xE),
.yT(yE)
);
one_vertex F (
.xU(xA),
.yU(yA),
.xV(xB),
.yV(yB),
.xW(xC),
.yW(yC),
.rU(rA),
.rV(rB),
.rW(rC),
.xT(xF),
.yT(yF)
);
median_x_3 M (
.xD(xD),
.yD(yD),
.xE(xE),
.yE(yE),
.xF(xF),
.yF(yF),
.xM(xM),
.yM(yM)
);
endmodule
| 6.615499 |
module trinalport_ram #(
parameter ADDRLEN = 10,
parameter DATALEN = 2,
parameter DEPTH = 1024
) (
input rst_n,
//port a
input clk,
input [ADDRLEN-1:0] addra,
output reg [DATALEN-1:0] rdataa,
input rea,
//port b
input [ADDRLEN-1:0] addrb,
output reg [DATALEN-1:0] rdatab,
input reb,
//port c
input [ADDRLEN-1:0] addrc,
input [DATALEN-1:0] wdatac,
input wec
);
reg [DATALEN-1:0] mem[0:DEPTH-1];
integer i;
reg [ADDRLEN-1:0] addra_r, addrb_r;
always @(*) begin
if (rea) rdataa <= mem[addra];
else rdataa <= 2'b00;
if (reb) rdatab <= mem[addrb];
else rdatab <= 2'b00;
end
always @(negedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < 1024; i = i + 1) mem[i] <= {DATALEN{1'b0}};
end else if (wec) mem[addrc] <= wdatac;
end
endmodule
| 7.833331 |
module trip (
input clk, // timespec 8.0 ns
input signed [8:0] inval,
input gate, // high for first cycle of IQ pair
input [11:0] trip_thresh,
input reset, // resets tripped state
input clear, // clears peak_val
output reg tripped,
output reg [11:0] peak_val
);
reg [7:0] inabs = 0;
always @(posedge clk) begin
inabs <= inval[8] ? ~inval[7:0] : inval[7:0];
end
wire [10:0] insquared;
square sq1 (
.v (inabs),
.v2(insquared)
);
reg [10:0] last_sq = 0, prev_sq = 0;
reg [11:0] sum_sq = 0, pipe_sum_sq = 0;
reg trip = 0;
reg gate_d1 = 0, gate_d2 = 0, gate_d3 = 0, gate_d4 = 0, gate_d5 = 0;
always @(posedge clk) begin
last_sq <= insquared;
prev_sq <= last_sq;
sum_sq <= last_sq + prev_sq; // all unsigned
gate_d1 <= gate;
gate_d2 <= gate_d1;
gate_d3 <= gate_d2;
gate_d4 <= gate_d3;
gate_d5 <= gate_d4;
trip <= sum_sq > trip_thresh;
if (reset | gate_d5 & trip) tripped <= ~reset;
// can't pipeline this step easily
// my first simple attempt used a stale peak_val for comparison
if (clear | gate_d4 & (sum_sq > peak_val)) peak_val <= clear ? 0 : sum_sq;
end
endmodule
| 6.757117 |
module TripleDES (
input clk,
input reset,
input [0:63] dataIn,
input [0:63] key1,
input [0:63] key2,
input [0:63] key3,
input encrypt,
output [0:63] dataOut
);
reg [0:63] ck1, ck2, ck3;
wire [0:63] DES1Out, DES2Out;
wire decrypt = ~encrypt;
DES DES1 (
.clk(clk),
.reset(reset),
.dataIn(dataIn),
.encrypt(encrypt),
.key(ck1),
.dataOut(DES1Out)
);
DES DES2 (
.clk(clk),
.reset(reset),
.dataIn(DES1Out),
.encrypt(decrypt),
.key(ck2),
.dataOut(DES2Out)
);
DES DES3 (
.clk(clk),
.reset(reset),
.dataIn(DES2Out),
.encrypt(encrypt),
.key(ck3),
.dataOut(dataOut)
);
// Switch key order based on whether we are encrypting or decrypting
always @(*) begin
if (encrypt) begin
ck1 = key1;
ck2 = key2;
ck3 = key3;
end else begin
ck1 = key3;
ck2 = key2;
ck3 = key1;
end
end
endmodule
| 7.703894 |
module
module Triple_DES_Encryption(
input [63:0] i_plaintext,
input [63:0] i_key1,
input [63:0] i_key2,
input [63:0] i_key3,
output [63:0] o_ciphertext
);
wire [63:0] w_des1_ciphertext;
wire [63:0] w_des2_ciphertext;
// 1st DES
DES_Encryption DES_Encryption_inst1
(
.i_plaintext(i_plaintext) , // input [63:0] i_plaintext_sig
.i_key(i_key1) , // input [63:0] i_key_sig
.o_ciphertext(w_des1_ciphertext) // output [63:0] o_ciphertext_sig
);
// 2nd DES
DES_Encryption DES_Encryption_inst2
(
.i_plaintext(w_des1_ciphertext) , // input [63:0] i_plaintext_sig
.i_key(i_key2) , // input [63:0] i_key_sig
.o_ciphertext(w_des2_ciphertext) // output [63:0] o_ciphertext_sig
);
// 3rd DES
DES_Encryption DES_Encryption_inst3
(
.i_plaintext(w_des2_ciphertext) , // input [63:0] i_plaintext_sig
.i_key(i_key3) , // input [63:0] i_key_sig
.o_ciphertext(o_ciphertext) // output [63:0] o_ciphertext_sig
);
endmodule
| 6.577045 |
module triple_element_product // 16 clock latency
( // ports
input clock,
input [31:0] data_in,
output [95:0] product
);
wire [31:0] mag1, mag0;
wire [63:0] mag1_mag2;
mult_gen_1 mpy_mag1_mag2 ( // 6 clock latency
.CLK(clock),
.A (data_in),
.B (mag1),
.P (mag1_mag2)
);
mult_gen_2 mpy_mag0_mag1_mag2 ( // 10 clock latency
.CLK(clock),
.A (mag1_mag2),
.B (mag0),
.P (product)
);
shift_reg #(
.DELAY(1),
.DATA_WIDTH(32)
) mag1_delay (
.clock(clock),
.reset_n(1),
.shift(1),
.data_in(data_in),
.data_out(mag1)
);
shift_reg #(
.DELAY(8),
.DATA_WIDTH(32)
) mag0_delay ( // delay of 2 + 6 (z_mpy1)
.clock(clock),
.reset_n(1),
.shift(1),
.data_in(data_in),
.data_out(mag0)
);
endmodule
| 7.127805 |
module triple_mac_axi_mux (
input mux_select,
// mux inputs
input [7:0] tdata0,
input tvalid0,
input tlast0,
output reg tready0,
input [7:0] tdata1,
input tvalid1,
input tlast1,
output reg tready1,
// mux outputs
output reg [7:0] tdata,
output reg tvalid,
output reg tlast,
input tready
);
always @(mux_select or tdata0 or tvalid0 or tlast0 or tdata1 or tvalid1 or tlast1) begin
if (mux_select) begin
tdata = tdata1;
tvalid = tvalid1;
tlast = tlast1;
end else begin
tdata = tdata0;
tvalid = tvalid0;
tlast = tlast0;
end
end
always @(mux_select or tready) begin
if (mux_select) begin
tready0 = 1'b1;
end else begin
tready0 = tready;
end
tready1 = tready;
end
endmodule
| 6.541691 |
module to simplify the timing where a pattern
// generator and address swap module can be muxed into the data path
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module triple_mac_axi_pipe (
input axi_tclk,
input axi_tresetn,
input [7:0] rx_axis_fifo_tdata_in,
input rx_axis_fifo_tvalid_in,
input rx_axis_fifo_tlast_in,
output rx_axis_fifo_tready_in,
output [7:0] rx_axis_fifo_tdata_out,
output rx_axis_fifo_tvalid_out,
output rx_axis_fifo_tlast_out,
input rx_axis_fifo_tready_out
);
reg [5:0] rd_addr;
reg [5:0] wr_addr;
reg wea;
reg rx_axis_fifo_tready_int;
reg rx_axis_fifo_tvalid_int;
wire [1:0] wr_block;
wire [1:0] rd_block;
assign rx_axis_fifo_tready_in = rx_axis_fifo_tready_int;
assign rx_axis_fifo_tvalid_out = rx_axis_fifo_tvalid_int;
// should always write when valid data is accepted
always @(rx_axis_fifo_tvalid_in or rx_axis_fifo_tready_int)
begin
wea = rx_axis_fifo_tvalid_in & rx_axis_fifo_tready_int;
end
// simply increment the write address after any valid write
always @(posedge axi_tclk)
begin
if (!axi_tresetn) begin
wr_addr <= 0;
end
else begin
if (rx_axis_fifo_tvalid_in & rx_axis_fifo_tready_int)
wr_addr <= wr_addr + 1;
end
end
// simply increment the read address after any validated read
always @(posedge axi_tclk)
begin
if (!axi_tresetn) begin
rd_addr <= 0;
end
else begin
if (rx_axis_fifo_tvalid_int & rx_axis_fifo_tready_out)
rd_addr <= rd_addr + 1;
end
end
assign wr_block = wr_addr[5:4];
assign rd_block = rd_addr[5:4]-1;
// need to generate the ready output - this is entirely dependant upon the full state
// of the fifo
always @(posedge axi_tclk)
begin
if (!axi_tresetn) begin
rx_axis_fifo_tready_int <= 0;
end
else begin
if (wr_block == rd_block)
rx_axis_fifo_tready_int <= 0;
else
rx_axis_fifo_tready_int <= 1;
end
end
// need to generate the valid output - this is entirely dependant upon the full state
// of the fifo
always @(rd_addr or wr_addr)
begin
if (rd_addr == wr_addr)
rx_axis_fifo_tvalid_int <= 0;
else
rx_axis_fifo_tvalid_int <= 1;
end
genvar i;
generate
for (i=0; i<=7; i=i+1) begin
RAM64X1D RAM64X1D_inst (
.DPO (rx_axis_fifo_tdata_out[i]),
.SPO (),
.A0 (wr_addr[0]),
.A1 (wr_addr[1]),
.A2 (wr_addr[2]),
.A3 (wr_addr[3]),
.A4 (wr_addr[4]),
.A5 (wr_addr[5]),
.D (rx_axis_fifo_tdata_in[i]),
.DPRA0 (rd_addr[0]),
.DPRA1 (rd_addr[1]),
.DPRA2 (rd_addr[2]),
.DPRA3 (rd_addr[3]),
.DPRA4 (rd_addr[4]),
.DPRA5 (rd_addr[5]),
.WCLK (axi_tclk),
.WE (wea)
);
end
endgenerate
RAM64X1D RAM64X1D_inst_last (
.DPO (rx_axis_fifo_tlast_out),
.SPO (),
.A0 (wr_addr[0]),
.A1 (wr_addr[1]),
.A2 (wr_addr[2]),
.A3 (wr_addr[3]),
.A4 (wr_addr[4]),
.A5 (wr_addr[5]),
.D (rx_axis_fifo_tlast_in),
.DPRA0 (rd_addr[0]),
.DPRA1 (rd_addr[1]),
.DPRA2 (rd_addr[2]),
.DPRA3 (rd_addr[3]),
.DPRA4 (rd_addr[4]),
.DPRA5 (rd_addr[5]),
.WCLK (axi_tclk),
.WE (wea)
);
endmodule
| 6.900006 |
module triple_mac_clk_wiz ( // Clock in ports
input CLK_IN1_P,
input CLK_IN1_N,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFGDS clkin1_buf (
.O (clkin1),
.I (CLK_IN1_P),
.IB(CLK_IN1_N)
);
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (5.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_DIVIDE_F (8.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (5),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (8),
.CLKOUT3_PHASE (90.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5.000),
.REF_JITTER1 (0.010)
) mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED(clkinstopped_unused),
.CLKFBSTOPPED(clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET)
);
// Output buffering
//-----------------------------------
BUFG clkout1_buf (
.O(CLK_OUT1),
.I(clkout0)
);
BUFG clkout2_buf (
.O(CLK_OUT2),
.I(clkout1)
);
BUFG clkout3_buf (
.O(CLK_OUT3),
.I(clkout2)
);
BUFG clkout4_buf (
.O(CLK_OUT4),
.I(clkout3)
);
endmodule
| 8.179008 |
module triple_mac_clk_wiz_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [4:1] CLK_OUT,
// High bits of counters driven by clocks
output [4:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 4;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Insert BUFGs on all input clocks that don't already have them
//--------------------------------------------------------------
BUFG clkin1_buf (
.O(clk_in1_buf),
.I(CLK_IN1)
);
// Instantiation of the clocking network
//--------------------------------------
triple_mac_clk_wiz clknetwork ( // Clock in ports
.CLK_IN1 (clk_in1_buf),
// Clock out ports
.CLK_OUT1(clk_int[1]),
.CLK_OUT2(clk_int[2]),
.CLK_OUT3(clk_int[3]),
.CLK_OUT4(clk_int[4]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
assign CLK_OUT = clk_int;
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
assign clk[4] = clk_int[4];
// Reset synchronizer
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen] <= 1'b1;
rst_sync_int1[count_gen] <= 1'b1;
rst_sync_int2[count_gen] <= 1'b1;
end else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ{C_W{1'b0}};
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
| 8.179008 |
module triple_mac_counter_f (
Clk,
Rst,
Load_In,
Count_Enable,
Count_Load,
Count_Down,
Count_Out,
Carry_Out
);
parameter C_NUM_BITS = 9;
parameter C_FAMILY = "nofamily";
input Clk;
input Rst;
input [C_NUM_BITS - 1:0] Load_In;
input Count_Enable;
input Count_Load;
input Count_Down;
output [C_NUM_BITS - 1:0] Count_Out;
wire [C_NUM_BITS - 1:0] Count_Out;
output Carry_Out;
wire Carry_Out;
reg [C_NUM_BITS:0] icount_out;
wire [C_NUM_BITS:0] icount_out_x;
wire [C_NUM_BITS:0] load_in_x;
//-------------------------------------------------------------------
// Begin architecture
//-------------------------------------------------------------------
//-------------------------------------------------------------------
// Generate Inferred code
//-------------------------------------------------------------------
assign load_in_x = {1'b0, Load_In};
// Mask out carry position to retain legacy self-clear on next enable.
// icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
assign icount_out_x = {1'b0, icount_out[C_NUM_BITS-1:0]};
//---------------------------------------------------------------
// Process to generate counter with - synchronous reset, load,
// counter enable, count down / up features.
//---------------------------------------------------------------
always @(posedge Clk) begin : CNTR_PROC
if (Rst == 1'b1) begin
icount_out <= {C_NUM_BITS - (0) + 1{1'b0}};
end else if (Count_Load == 1'b1) begin
icount_out <= load_in_x;
end else if (Count_Down == 1'b1 & Count_Enable == 1'b1) begin
icount_out <= icount_out_x - 1;
end else if (Count_Enable == 1'b1) begin
icount_out <= icount_out_x + 1;
end
end
assign Carry_Out = icount_out[C_NUM_BITS];
assign Count_Out = icount_out[C_NUM_BITS-1:0];
endmodule
| 8.223376 |
module triple_mac (
//---------------------------------------
// asynchronous reset
input glbl_rstn,
input rx_axi_rstn,
input tx_axi_rstn,
//---------------------------------------
// Receiver Interface
input rx_axi_clk,
output rx_reset_out,
output [ 7:0] rx_axis_mac_tdata,
output rx_axis_mac_tvalid,
output rx_axis_mac_tlast,
output rx_axis_mac_tuser,
output [ 4:0] rx_axis_filter_tuser,
// Receiver Statistics
output [27:0] rx_statistics_vector,
output rx_statistics_valid,
//---------------------------------------
// Transmitter Interface
input tx_axi_clk,
output tx_reset_out,
input [7:0] tx_axis_mac_tdata,
input tx_axis_mac_tvalid,
input tx_axis_mac_tlast,
input tx_axis_mac_tuser,
output tx_axis_mac_tready,
input [ 7:0] tx_ifg_delay,
// Transmitter Statistics
output [31:0] tx_statistics_vector,
output tx_statistics_valid,
//---------------------------------------
// MAC Control Interface
input pause_req,
input [15:0] pause_val,
//---------------------------------------
// Current Speed Indication
output speed_is_100,
output speed_is_10_100,
//---------------------------------------
// Physical Interface of the core
output [7:0] gmii_txd,
output gmii_tx_en,
output gmii_tx_er,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
// MDIO Interface
output mdc_out,
input mdio_in,
output mdio_out,
output mdio_tri,
//---------------------------------------
// IPIC Interface
input bus2ip_clk,
input bus2ip_reset,
input [31:0] bus2ip_addr,
input bus2ip_cs,
input bus2ip_rdce,
input bus2ip_wrce,
input [31:0] bus2ip_data,
output [31:0] ip2bus_data,
output ip2bus_wrack,
output ip2bus_rdack,
output ip2bus_error,
output mac_irq
);
endmodule
| 6.879914 |
module triple_mac_pselect_f (
A,
AValid,
CS
);
parameter C_AB = 9;
parameter C_AW = 32;
parameter [0:C_AW - 1] C_BAR = 'bz;
parameter C_FAMILY = "nofamily";
input [0:C_AW-1] A;
input AValid;
output CS;
wire CS;
parameter [0:C_AB-1] BAR = C_BAR[0:C_AB-1];
//----------------------------------------------------------------------------
// Build a behavioral decoder
//----------------------------------------------------------------------------
generate
if (C_AB > 0) begin : XST_WA
assign CS = (A[0:C_AB-1] == BAR[0:C_AB-1]) ? AValid : 1'b0;
end
endgenerate
generate
if (C_AB == 0) begin : PASS_ON_GEN
assign CS = AValid;
end
endgenerate
endmodule
| 6.928343 |
module triple_mac_sync_block #(
parameter INITIALISE = 2'b00
) (
input clk, // clock to be sync'ed to
input data_in, // Data to be 'synced'
output data_out // synced data
);
// Internal Signals
wire data_sync1;
wire data_sync2;
(* ASYNC_REG = "TRUE", RLOC = "X0Y0", SHREG_EXTRACT = "NO" *)
FD #(
.INIT(INITIALISE[0])
) data_sync (
.C(clk),
.D(data_in),
.Q(data_sync1)
);
(* ASYNC_REG = "TRUE", RLOC = "X0Y0", SHREG_EXTRACT = "NO" *)
FD #(
.INIT(INITIALISE[1])
) data_sync_reg (
.C(clk),
.D(data_sync1),
.Q(data_sync2)
);
assign data_out = data_sync2;
endmodule
| 6.817337 |
module tri_mem_mux #(
parameter addr_bus_size = 16,
parameter data_bus_size = 16
) (
//Inputs
input [(addr_bus_size - 1):0] addr_a,
input [(data_bus_size - 1):0] data_a,
input start_a,
input rw_a,
input [(addr_bus_size - 1):0] addr_b,
input [(data_bus_size - 1):0] data_b,
input start_b,
input rw_b,
input [2:0] select,
//Outputs
output [(addr_bus_size - 1):0] addr_x,
output [(data_bus_size - 1):0] data_x,
output start_x,
output rw_x,
output [(addr_bus_size - 1):0] addr_y,
output [(data_bus_size - 1):0] data_y,
output start_y,
output rw_y,
output [(addr_bus_size - 1):0] addr_z,
output [(data_bus_size - 1):0] data_z,
output start_z,
output rw_z
);
localparam [(addr_bus_size - 1):0] dummy_addr = 0;
localparam [(data_bus_size - 1):0] dummy_data = 0;
localparam dummy_start = 1'b1; //Start is active low
localparam dummy_rw = 1'b0; //1 for a read (although it doesn't matter)
localparam [2:0] A = 3'b000, //A->X : B->Y : D->Z
B = 3'b001, //A->X : B->Z : D->Y
C = 3'b010, //A->Y : B->x : D->Z
D = 3'b011, //A->Y : B->Z : D->X
E = 3'b100, //A->Z : B->X : D->Y
F = 3'b101; //A->Z : B->Y : D->X
//X Dispatching
assign addr_x = (select == A || select == B)? addr_a : ((select == C || select == E)? addr_b : dummy_addr);
assign data_x = (select == A || select == B)? data_a : ((select == C || select == E)? data_b : dummy_data);
assign start_x = (select == A || select == B)? start_a : ((select == C || select == E)? start_b : dummy_start);
assign rw_x = (select == A || select == B)? rw_a : ((select == C || select == E)? rw_b : dummy_rw);
//Y Dispaching
assign addr_y = (select == C || select == D)? addr_a : ((select == A || select == F)? addr_b : dummy_addr);
assign data_y = (select == C || select == D)? data_a : ((select == A || select == F)? data_b : dummy_data);
assign start_y = (select == C || select == D)? start_a : ((select == A || select == F)? start_b : dummy_start);
assign rw_y = (select == C || select == D)? rw_a : ((select == A || select == F)? rw_b : dummy_rw);
//Z Dispaching
assign addr_z = (select == E || select == F)? addr_a : ((select == B || select == D)? addr_b : dummy_addr);
assign data_z = (select == E || select == F)? data_a : ((select == B || select == D)? data_b : dummy_data);
assign start_z = (select == E || select == F)? start_a : ((select == B || select == D)? start_b : dummy_start);
assign rw_z = (select == E || select == F)? rw_a : ((select == B || select == D)? rw_b : dummy_rw);
endmodule
| 8.778712 |
module tri_data_mux #(
parameter addr_bus_size = 16,
parameter data_bus_size = 16
) (
input [(data_bus_size - 1):0] data_x,
input [(data_bus_size - 1):0] data_y,
input [(data_bus_size - 1):0] data_z,
input [2:0] select,
output [(data_bus_size - 1):0] data_t //Data to be sent to transmission module
);
//A is the capture module
//B is the transmission module
//D is the dummy input
localparam [2:0] A = 3'b000, //A->X : B->Y : D->Z
B = 3'b001, //A->X : B->Z : D->Y
C = 3'b010, //A->Y : B->x : D->Z
D = 3'b011, //A->Y : B->Z : D->X
E = 3'b100, //A->Z : B->X : D->Y
F = 3'b101; //A->Z : B->Y : D->X
assign data_t = (select == C || select == E)? data_x : ((select == A || select == F)? data_y : data_z);
endmodule
| 8.643411 |
module tri_ready_mux (
input wire ready_x,
input wire ready_y,
input wire ready_z,
input [2:0] select,
output ready_a,
output ready_b
);
localparam [2:0] A = 3'b000, //A->X : B->Y : D->Z
B = 3'b001, //A->X : B->Z : D->Y
C = 3'b010, //A->Y : B->x : D->Z
D = 3'b011, //A->Y : B->Z : D->X
E = 3'b100, //A->Z : B->X : D->Y
F = 3'b101; //A->Z : B->Y : D->X
assign ready_a = (select == A || select == B)? ready_x : ((select == C || select == D)? ready_y : ready_z);
assign ready_b = (select == C || select == E)? ready_x : ((select == A || select == F)? ready_y : ready_z);
endmodule
| 8.274752 |
module MAINDEC (
BCLK,
RST_N,
WRITE,
READ,
STATUS,
SRAM_RDY,
ADDR,
BOOT_Q,
SRAM_Q,
UART_Q,
BE,
IO_DI,
UART_RD,
UART_WR,
CESRAM,
NMI_N,
DRD,
READY,
BRESET,
ENDRAM,
LEDR,
LEDG,
HEXL,
HEXM,
SSW
);
input BCLK;
input RST_N;
input WRITE;
input READ;
input [3:0] STATUS;
input SRAM_RDY;
input [31:2] ADDR;
input [31:0] BOOT_Q;
input [31:0] SRAM_Q;
input [3:0] BE;
input [31:0] IO_DI;
output UART_RD;
output [1:0] UART_WR;
input [31:0] UART_Q;
output CESRAM;
output reg NMI_N;
output [31:0] DRD;
output reg READY;
output reg BRESET;
output reg ENDRAM;
input [9:0] SSW;
output reg [6:0] HEXL, HEXM;
output reg [9:0] LEDR;
output reg [7:0] LEDG;
reg [31:0] DRD;
reg rd_rdy;
reg [ 3:0] init_cou;
reg [25:0] counter;
reg [ 9:0] ssw_reg;
reg nmie;
wire wr_leds, wr_coun;
wire access;
assign access = WRITE | READ;
assign UART_WR = (WRITE & (ADDR[31:20] == 12'h202)) ? BE[1:0] : 2'd0;
assign UART_RD = READ & (ADDR[31:20] == 12'h202) & BE[0]; // Read Data Reg. -> Int to 0
assign CESRAM = access & (ADDR[31:20] == 12'h201);
assign wr_coun = WRITE & (ADDR[31:20] == 12'h205) & ADDR[2];
assign wr_leds = WRITE & (ADDR[31:20] == 12'h204);
always @(posedge BCLK) if (wr_leds && ADDR[2] && BE[1]) HEXM <= IO_DI[14:8];
always @(posedge BCLK) if (wr_leds && ADDR[2] && BE[0]) HEXL <= IO_DI[6:0];
always @(posedge BCLK) if (wr_leds && !ADDR[2] && BE[2]) LEDG <= IO_DI[23:16];
always @(posedge BCLK) if (wr_leds && !ADDR[2] && BE[1]) LEDR[9:8] <= IO_DI[9:8];
always @(posedge BCLK) if (wr_leds && !ADDR[2] && BE[0]) LEDR[7:0] <= IO_DI[7:0];
always @(posedge BCLK) ssw_reg <= SSW;
always @(posedge BCLK)
rd_rdy <= READ & ((ADDR[31:20] == 12'h200) | (ADDR[31:29] == 3'd0)) & ~rd_rdy;
always @(access or ADDR or WRITE or rd_rdy or SRAM_RDY)
casex ({
access, ADDR[31:20]
})
13'b1_000x_xxxx_xxxx: READY = rd_rdy; // if DRAM not activ
13'b1_0010_xxxx_0000: READY = rd_rdy; // Boot-ROM
13'b1_0010_xxxx_0001: READY = SRAM_RDY;
default: READY = access; // else only one clock !!!
endcase
always @(ADDR or BOOT_Q or SRAM_Q or UART_Q or ssw_reg or counter or nmie)
casex ({
ADDR[31:20]
})
12'h201: DRD = SRAM_Q;
12'h202: DRD = UART_Q;
12'h203: DRD = {22'd0, ssw_reg[9:0]};
12'h205: DRD = {(ADDR[2] ? nmie : 1'd0), 5'd0, counter};
default: DRD = BOOT_Q; // Boot-ROM
endcase
// Program access in higher ROM area switches DRAM on
always @(posedge BCLK)
ENDRAM <= (((ADDR[31:28] == 4'h2) & (STATUS == 4'h8) & READ) | ENDRAM) & BRESET;
// ++++++++++++++++++++++++++ NMI Counter ++++++++++++++++++++++++++
always @(posedge BCLK)
if (!BRESET) counter <= 26'd0;
else counter <= (counter == 26'h2FA_F07F) ? 26'd0 : counter + 26'd1; // 50.000.000 = 2FA_F080
always @(posedge BCLK) NMI_N <= ~((counter[25:4] == 22'h2FA_F07) & nmie); // once per second
always @(posedge BCLK or negedge BRESET) // NMI Enable
if (!BRESET) nmie <= 1'b0;
else if (wr_coun) nmie <= IO_DI[31]; // is SET able
// ++++++++++++++++++++++++++ RESET Signal ++++++++++++++++++++++++++
always @(posedge BCLK or negedge RST_N)
if (!RST_N) init_cou <= 4'h0;
else init_cou <= init_cou + 4'h1;
always @(posedge BCLK or negedge RST_N)
if (!RST_N) BRESET <= 1'b0;
else if (init_cou == 4'hF) BRESET <= 1'b1;
endmodule
| 7.58968 |
module UART (
BCLK,
BRESET,
UART_RD,
UART_WR,
DIN,
UA_RX,
UA_TX,
UART_Q,
UA_INT
);
input BCLK;
input BRESET;
input UART_RD;
input [1:0] UART_WR;
input [15:0] DIN;
output UA_TX;
input UA_RX;
output [31:0] UART_Q;
output UA_INT;
reg [1:0] iena; // Interrupt enable
parameter baudrate = 10'd867; // 57600 Baud : 868 clocks of 20ns
// +++++++++++++++++++++++++++++++ Transmitter +++++++++++++++++++++++++++++++++
reg [8:0] shifter_tx;
reg [3:0] txbits;
reg [9:0] txtimer;
reg tx_int;
reg trold;
wire tx_load, tx_run, tx_shift;
assign tx_load = UART_WR[0] & ~tx_run; // no Write during transmisson
always @(posedge BCLK or negedge BRESET)
if (!BRESET) shifter_tx <= 9'h1FF;
else if (tx_load) shifter_tx <= {DIN[7:0], 1'b0};
else if (tx_shift) shifter_tx <= {1'b1, shifter_tx[8:1]}; // LSB first to send
assign UA_TX = shifter_tx[0];
// ---1__2_one_3_two_4_three_5_four_6_five_7_six_8_seven_9_eight_10---11
always @(posedge BCLK or negedge BRESET)
if (!BRESET) txbits <= 4'd0;
else if (tx_load) txbits <= 4'd1;
else if (tx_shift) txbits <= (txbits == 4'd10) ? 4'd0 : txbits + 4'd1;
assign tx_run = |txbits;
always @(posedge BCLK) trold <= tx_run;
always @(posedge BCLK) txtimer <= (~tx_run | tx_shift) ? 10'd0 : txtimer + 10'd1;
assign tx_shift = (txtimer == baudrate);
always @(posedge BCLK or negedge BRESET)
if (!BRESET) tx_int <= 1'b0;
else if (tx_load) tx_int <= 1'b0;
else if (UART_WR[1]) tx_int <= DIN[13];
else if (!tx_run && trold) tx_int <= 1'b1;
// +++++++++++++++++++++++++++++++ Receiver +++++++++++++++++++++++++++++++++
reg [2:0] inshift;
reg [3:0] rxbits;
reg [8:0] shifter_rx;
reg [9:0] rxtimer;
reg [7:0] rxhold;
reg inbit, oldin;
reg rx_int;
reg rx_end;
wire rx_go, rx_shift, rx_run;
always @(posedge BCLK) inshift <= {inshift[1:0], UA_RX};
always @(posedge BCLK) inbit <= (inshift == 3'b111) ? 1'b1 : (inshift == 3'd0) ? 1'b0 : inbit;
always @(posedge BCLK) oldin <= inbit;
assign rx_go = ~inbit & oldin & (rxbits == 4'd0);
// --1_2__3one_4two_5three_6four_7five_8six_9seven_10eight_-11--
always @(posedge BCLK or negedge BRESET)
if (!BRESET) rxbits <= 4'd0;
else if (rx_go) rxbits <= 4'd1;
else if (rx_shift)
rxbits <= (((rxbits == 4'd1) & inbit) | (rxbits == 4'd10)) ? 4'd0 : rxbits + 4'd1;
always @(posedge BCLK) if (rx_shift) shifter_rx <= {inbit, shifter_rx[8:1]};
always @(posedge BCLK) rxtimer <= (~rx_run | rx_shift) ? 10'd0 : rxtimer + 10'd1;
assign rx_shift = (rxtimer == ((rxbits == 4'd1) ? {1'b0, baudrate[9:1]} : baudrate));
assign rx_run = |rxbits;
always @(posedge BCLK) rx_end <= rx_shift & (rxbits == 4'd10) & inbit; // Stopbit must be "1"
always @(posedge BCLK or negedge BRESET)
if (!BRESET) rx_int <= 1'b0;
else if (UART_RD) rx_int <= 1'b0;
else if (UART_WR[1]) rx_int <= DIN[10];
else if (rx_end) rx_int <= 1'b1;
always @(posedge BCLK) if (rx_end) rxhold <= shifter_rx[7:0]; // hold received data
assign UART_Q = {18'd0, tx_int, iena[1], tx_run, rx_int, iena[0], rx_run, rxhold};
// +++++++++++++++++++++++++++++++ Interrupt +++++++++++++++++++++++++++++++++
always @(posedge BCLK or negedge BRESET)
if (!BRESET) iena <= 2'd0;
else if (UART_WR[1]) iena <= {DIN[12], DIN[9]};
assign UA_INT = (tx_int & iena[1]) | (rx_int & iena[0]);
endmodule
| 7.035312 |
module SRAM (
BCLK,
BRESET,
CESRAM,
WRITE,
AA,
BE,
DIN,
READY,
SRAM_Q,
SRCO,
SRAA,
SRDB
);
input BCLK;
input BRESET;
input CESRAM;
input WRITE;
input [18:1] AA;
input [3:0] BE;
input [31:0] DIN;
output READY;
output [31:0] SRAM_Q;
output reg [4:0] SRCO;
output reg [17:0] SRAA; // Word Address
inout [15:0] SRDB;
reg [15:0] do_reg;
reg [ 2:0] state;
reg [17:0] save_aa;
reg [1:0] top_be, save_be, muxbe;
reg [15:0] top_do, save_do, muxdo;
reg [15:0] di_reg, pipe_reg;
reg [15:0] oe_reg;
wire twoa;
wire [17:0] muxadr;
genvar i;
assign twoa = (BE[3] | BE[2]) & (BE[1] | BE[0]); // two Accesses
always @(posedge BCLK or negedge BRESET)
if (!BRESET) state <= 3'd0;
else
casex ({
CESRAM, WRITE, twoa, state
})
6'b0x_x_000: state <= 3'b000; // nothing to do
6'b10_1_000: state <= 3'b001;
6'b10_0_000: state <= 3'b010;
6'b11_1_000: state <= 3'b100;
6'b11_0_000: state <= 3'b110;
// Read
6'bxx_x_001: state <= 3'b010;
6'bxx_x_010: state <= 3'b011;
6'bxx_x_011: state <= 3'b000; // Send READY
// Write
6'bxx_x_100: state <= 3'b101;
6'bxx_x_101: state <= 3'b110;
6'bxx_x_110: state <= 3'b000; // State 7 at WRITE overlaps with State 0
default: state <= 3'b000;
endcase
always @(posedge BCLK) save_aa <= muxadr;
assign muxadr[17:1] = (CESRAM & (state == 3'd0)) ? AA[18:2] : save_aa[17:1];
assign muxadr[0] = (CESRAM & (state == 3'd0)) ? AA[1] : ( ((state == 3'd1) | (state == 3'd5)) ? 1'b1 : save_aa[0] );
always @(posedge BCLK) SRAA <= muxadr;
always @(posedge BCLK) if (!state[2]) top_be = ~BE[3:2];
always @(posedge BCLK) save_be <= muxbe;
always @(*)
casex ({
CESRAM, state
})
4'b0_000: muxbe = 2'b11;
4'b1_000: muxbe = AA[1] ? ~BE[3:2] : ~BE[1:0]; // READ has valid BE's
4'bx_001: muxbe = ~BE[3:2]; // READ is still active
4'bx_101: muxbe = top_be;
4'bx_010: muxbe = 2'b11; // State = 2 is End for READ !
default: muxbe = save_be;
endcase
always @(posedge BCLK) SRCO[1:0] <= muxbe;
always @(posedge BCLK) if (!state[2]) top_do <= DIN[31:16];
always @(posedge BCLK) save_do <= muxdo;
always @(*)
casex ({
CESRAM, state
})
4'b1_000: muxdo = AA[1] ? DIN[31:16] : DIN[15:0]; // READ has valid BE's
4'bx_101: muxdo = top_do;
default: muxdo = save_do;
endcase
always @(posedge BCLK) do_reg <= muxdo;
// Control Signals
always @(posedge BCLK)
SRCO[4] <= ~((CESRAM & (state == 3'd0)) | (state == 3'd1) | (state == 3'd4) | (state == 3'd5) | (state == 3'd6)); // CE
always @(posedge BCLK) SRCO[3] <= ~((CESRAM & ~WRITE & (state == 3'd0)) | (state == 3'd1)); // OE
always @(negedge BCLK) SRCO[2] <= ~((state == 3'd4) | (state == 3'd6)); // WE
always @(posedge BCLK)
oe_reg <= {16{(CESRAM & WRITE & (state == 3'd0)) | (state == 3'd4) | (state == 3'd5) | (state == 3'd6)}};
generate
for (i = 0; i <= 15; i = i + 1) begin : oectrl
assign SRDB[i] = oe_reg[i] ? do_reg[i] : 1'bz;
end
endgenerate
always @(posedge BCLK) di_reg <= SRDB; // Fast Input Register
always @(posedge BCLK) pipe_reg <= di_reg;
assign SRAM_Q = {di_reg, (twoa ? pipe_reg : di_reg)};
assign READY = CESRAM & (WRITE ? (state == 3'd0) : (state == 3'd3));
endmodule
| 7.162247 |
module triRom4096_1 (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a;
tri1 rden_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0 = 16'h0;
wire sub_wire1 = 1'h0;
wire [15:0] sub_wire2;
wire [15:0] sub_wire3;
wire [15:0] q_a = sub_wire2[15:0];
wire [15:0] q_b = sub_wire3[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (sub_wire0),
.data_b (sub_wire0),
.rden_a (rden_a),
.rden_b (rden_b),
.wren_a (sub_wire1),
.wren_b (sub_wire1),
.q_a (sub_wire2),
.q_b (sub_wire3)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "./triMIF3/triMIF_doubleHarmonics2.mif",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
| 6.762483 |
module triRom4096_2 (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a;
tri1 rden_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0 = 16'h0;
wire sub_wire1 = 1'h0;
wire [15:0] sub_wire2;
wire [15:0] sub_wire3;
wire [15:0] q_a = sub_wire2[15:0];
wire [15:0] q_b = sub_wire3[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (sub_wire0),
.data_b (sub_wire0),
.rden_a (rden_a),
.rden_b (rden_b),
.wren_a (sub_wire1),
.wren_b (sub_wire1),
.q_a (sub_wire2),
.q_b (sub_wire3)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "./triMIF3/triMIF_doubleHarmonics4.mif",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
| 6.699756 |
module triRom4096_3 (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a;
tri1 rden_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0 = 16'h0;
wire sub_wire1 = 1'h0;
wire [15:0] sub_wire2;
wire [15:0] sub_wire3;
wire [15:0] q_a = sub_wire2[15:0];
wire [15:0] q_b = sub_wire3[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (sub_wire0),
.data_b (sub_wire0),
.rden_a (rden_a),
.rden_b (rden_b),
.wren_a (sub_wire1),
.wren_b (sub_wire1),
.q_a (sub_wire2),
.q_b (sub_wire3)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "./triMIF3/triMIF_doubleHarmonics6.mif",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
| 7.012045 |
module triRom4096_4 (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a;
tri1 rden_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0 = 16'h0;
wire sub_wire1 = 1'h0;
wire [15:0] sub_wire2;
wire [15:0] sub_wire3;
wire [15:0] q_a = sub_wire2[15:0];
wire [15:0] q_b = sub_wire3[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (sub_wire0),
.data_b (sub_wire0),
.rden_a (rden_a),
.rden_b (rden_b),
.wren_a (sub_wire1),
.wren_b (sub_wire1),
.q_a (sub_wire2),
.q_b (sub_wire3)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "./triMIF3/triMIF_doubleHarmonics8.mif",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
| 6.673152 |
module triRom4096_5 (
address_a,
address_b,
clock,
rden_a,
rden_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock;
input rden_a;
input rden_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a;
tri1 rden_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0 = 16'h0;
wire sub_wire1 = 1'h0;
wire [15:0] sub_wire2;
wire [15:0] sub_wire3;
wire [15:0] q_a = sub_wire2[15:0];
wire [15:0] q_b = sub_wire3[15:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (sub_wire0),
.data_b (sub_wire0),
.rden_a (rden_a),
.rden_b (rden_b),
.wren_a (sub_wire1),
.wren_b (sub_wire1),
.q_a (sub_wire2),
.q_b (sub_wire3)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "./triMIF3/triMIF_doubleHarmonics10.mif",
altsyncram_component.intended_device_family = "MAX 10",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
| 6.631454 |
module TRIS (
inout PORT,
input DIR,
input SEND,
output READ
);
assign PORT = DIR ? SEND : 1'bZ; // Se DIR 1 -- copia DHT_OUT para saida, caso nao, deixa o pino indefinido para atuar como entrada
assign READ = DIR ? 1'bz : PORT;
endmodule
| 8.78816 |
module trisc0 #(
parameter WA = 7, // Address bit width -1
WD = 7
) // Data bit width -1
(
input clk, // System clock
input reset, // Asynchronous reset
output jc_out, // Jump condition flag
output me_ena, // Memory enable
input [WD:0] iport, // Input port
output reg [WD:0] oport, // Output port
output signed [WD:0] s0_out, // Stack register 0
output signed [WD:0] s1_out, // Stack register 1
output [WD:0] dmd_in, // Data memory data read
output [WD:0] dmd_out, // Data memory data read
output [WD:0] pc_out, // Progamm counter
output [WD:0] dma_out, // Data memory address write
output [WD:0] dma_in, // Data memory address read
output [ 7:0] ir_imm, // Immidiate value
output [ 3:0] op_code
); // Operation code
// --------------------------------------------------------
//parameter ifetch=0, load=1, store=2, incpc=3;
reg [1:0] state;
wire [3:0] op;
wire [WD:0] imm, dmd;
reg signed [WD:0] s0, s1, s2, s3;
reg [WA:0] pc;
wire [WA:0] dma;
wire [11:0] pmd, ir;
wire eq, ne, not_clk;
reg mem_ena, jc;
// OP Code of instructions:
parameter
add = 0, neg = 1, sub = 2, opand = 3, opor = 4,
inv = 5, mul = 6, pop = 7, pushi = 8, push = 9,
scan = 10, print = 11, cne = 12, ceq = 13, cjp = 14,
jmp = 15;
always @(*) // sequential FSM of processor
// Check store in register ?
case (op) // always store except Branch
pop: mem_ena <= 1;
default: mem_ena <= 0;
endcase
always @(negedge clk or posedge reset)
if (reset == 1) // update the program counter
pc <= 0;
else begin // use falling edge
if (((op == cjp) & (jc == 0)) | (op == jmp)) pc <= imm;
else pc <= pc + 1;
end
always @(posedge clk or posedge reset)
if (reset) // compute jump flag and store in FF
jc <= 0;
else jc <= ((op == ceq) & (s0 == s1)) | ((op == cne) & (s0 != s1));
// Mapping of the instruction, i.e., decode instruction
assign op = ir[11:8]; // Operation code
assign dma = ir[7:0]; // Data memory address
assign imm = ir[7:0]; // Immidiate operand
prog_rom brom (
.clk(clk),
.reset(reset),
.address(pc),
.q(pmd)
);
assign ir = pmd;
assign not_clk = ~clk;
data_ram bram (
.clk(not_clk),
.address(dma),
.q(dmd),
.data(s0),
.we(mem_ena)
);
always @(posedge clk or posedge reset) begin : P3
integer temp;
if (reset) begin // Asynchronous clear
s0 <= 0;
s1 <= 0;
s2 <= 0;
s3 <= 0;
oport <= 0;
end else begin
case (op)
add: s0 <= s0 + s1;
neg: s0 <= -s0;
sub: s0 <= s1 - s0;
opand: s0 <= s0 & s1;
opor: s0 <= s0 | s1;
inv: s0 <= ~s0;
mul: begin
temp = s0 * s1; // double width
s0 <= temp[WD:0];
end // product
pop: s0 <= s1;
push: s0 <= dmd;
pushi: s0 <= imm;
scan: s0 <= iport;
print: begin
oport <= s0;
s0 <= s1;
end
default: s0 <= 0;
endcase
case (op) // Specify the stack operations
pushi, push, scan: begin
s3 <= s2;
s2 <= s1;
s1 <= s0;
end // Push type
cjp, jmp, inv | neg: ; // Do nothing for branch
default: begin
s1 <= s2;
s2 <= s3;
s3 <= 0;
end
// Pop all others
endcase
end
end
// Extra test pins:
assign dmd_out = dmd;
assign dma_out = dma; //Data memory
assign dma_in = dma;
assign dmd_in = s0;
assign pc_out = pc;
assign ir_imm = imm;
assign op_code = op; // Program control
// Control signals:
assign jc_out = jc;
assign me_ena = mem_ena;
// Two top stack elements:
assign s0_out = s0;
assign s1_out = s1;
endmodule
| 8.686465 |
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