code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tristate_test (
input wire active1,
input wire active2,
output wire [31:0] wbs_dat
);
wrapped_picorv32 pico1 (
.active(active1),
.vccd1(1'b1),
.vssd1(1'b0),
.wbs_dat_o(wbs_dat)
);
wrapped_picorv32 pico2 (
.active(active2),
.vccd1(1'b1),
.vssd1(1'b0),
.wbs_dat_o(wbs_dat)
);
`ifdef FORMAL
always @(*) assume (active1 + active2 <= 1);
`endif
endmodule
| 7.63903 |
module tristate1_tb ();
//-- Pausa pequeña: divisor
localparam DELAY = 4;
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Led a controlar
wire led0;
//-- Instanciar el componente
tristate1 #(
.DELAY(DELAY)
) dut (
.clk (clk),
.led0(led0)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("tristate1_tb.vcd");
$dumpvars(0, tristate1_tb);
#100 $display("FIN de la simulacion");
$finish;
end
endmodule
| 7.312319 |
module triDriver (
bus,
drive,
value
);
inout [3:0] bus;
input drive;
input [3:0] value;
assign #2 bus = (drive == 1) ? value : 4'bz;
endmodule
| 6.730723 |
module tristate2_tb ();
//-- Pausa pequeña: divisor
localparam DELAY = 4;
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Led a controlar
wire led0;
//-- Instanciar el componente
tristate2 #(
.DELAY(DELAY)
) dut (
.clk (clk),
.led0(led0)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("tristate2_tb.vcd");
$dumpvars(0, tristate2_tb);
#100 $display("FIN de la simulacion");
$finish;
end
endmodule
| 6.832569 |
module tristate32 (
out,
in,
selector
);
input [31:0] in;
output [31:0] out;
input selector;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : tristate32
assign out[i] = selector ? (in[i] ? 1'b1 : 1'b0) : 1'bz;
end
endgenerate
endmodule
| 7.258794 |
module tristate541 (
Y,
A,
G1_L,
G2_L
);
parameter SIZE = 8;
output [SIZE-1:0] Y;
input [SIZE-1:0] A;
input G1_L, G2_L;
wire GL;
nor n1 (GL, G1_L, G2_L);
genvar k;
generate
for (k = 0; k < SIZE; k = k + 1) begin : LOOP
bufif1 g1 (Y[k], A[k], GL);
end
endgenerate
endmodule
| 7.466799 |
module tristate8port (
input enable,
input [7:0] in,
output [7:0] out
);
assign out = (enable) ? in : 8'bzzzzzzzz;
endmodule
| 7.921641 |
module tristatebuf (
input data,
input en,
output y
);
//always@(en,data)
assign y = en ? data : 'bz;
endmodule
| 7.163524 |
module tristateBuff1 (
input wire D,
input wire nOE,
output wire Q
);
assign Q = nOE == 1'b0 ? D : 1'bz;
endmodule
| 7.164283 |
module tristateBuff8 (
input wire [7:0] D,
input wire nOE,
output wire [7:0] Q
);
assign Q = nOE == 1'b0 ? D : 8'hz;
endmodule
| 7.593971 |
module tristateBuff16 (
input wire [15:0] D,
input wire nOE,
output wire [15:0] Q
);
assign Q = nOE == 1'b0 ? D : 16'hz;
endmodule
| 7.164283 |
module triStateBuffer (
out,
enable,
in
);
input enable;
input [31:0] in;
output [31:0] out;
assign out = enable ? in : 32'bz;
endmodule
| 7.116795 |
module TriStateBuffer16b (
input [15:0] in,
input triStateCtrl,
output reg [15:0] out
);
initial out = 16'hZZZZ;
always @(*) begin
out = triStateCtrl ? in : 16'hZZZZ;
end
endmodule
| 6.521856 |
module triStateBufferDecoder32 (
ctrl_read,
w_0,
w_1,
w_2,
w_3,
w_4,
w_5,
w_6,
w_7,
w_8,
w_9,
w_10,
w_11,
w_12,
w_13,
w_14,
w_15,
w_16,
w_17,
w_18,
w_19,
w_20,
w_21,
w_22,
w_23,
w_24,
w_25,
w_26,
w_27,
w_28,
w_29,
w_30,
w_31,
out
);
input [4:0] ctrl_read;
input [31:0] w_0, w_1, w_2, w_3, w_4,
w_5, w_6, w_7, w_8, w_9, w_10,
w_11, w_12, w_13, w_14, w_15,
w_16, w_17, w_18, w_19, w_20,
w_21, w_22, w_23, w_24, w_25,
w_26, w_27, w_28, w_29, w_30, w_31;
output [31:0] out;
wire [31:0] out_write;
wire w0, w1, w2, w3, w4, w;
not not_0 (w0, ctrl_read[0]);
not not_1 (w1, ctrl_read[1]);
not not_2 (w2, ctrl_read[2]);
not not_3 (w3, ctrl_read[3]);
not not_4 (w4, ctrl_read[4]);
and andg (w, w0, w1, w2, w3, w4);
decoder_32 d32 (
ctrl_read,
out_write
);
tristate_buffer tb0 (
w_0,
w,
out
);
tristate_buffer tb1 (
w_1,
out_write[1],
out
);
tristate_buffer tb2 (
w_2,
out_write[2],
out
);
tristate_buffer tb3 (
w_3,
out_write[3],
out
);
tristate_buffer tb4 (
w_4,
out_write[4],
out
);
tristate_buffer tb5 (
w_5,
out_write[5],
out
);
tristate_buffer tb6 (
w_6,
out_write[6],
out
);
tristate_buffer tb7 (
w_7,
out_write[7],
out
);
tristate_buffer tb8 (
w_8,
out_write[8],
out
);
tristate_buffer tb9 (
w_9,
out_write[9],
out
);
tristate_buffer tb10 (
w_10,
out_write[10],
out
);
tristate_buffer tb11 (
w_11,
out_write[11],
out
);
tristate_buffer tb12 (
w_12,
out_write[12],
out
);
tristate_buffer tb13 (
w_13,
out_write[13],
out
);
tristate_buffer tb14 (
w_14,
out_write[14],
out
);
tristate_buffer tb15 (
w_15,
out_write[15],
out
);
tristate_buffer tb16 (
w_16,
out_write[16],
out
);
tristate_buffer tb17 (
w_17,
out_write[17],
out
);
tristate_buffer tb18 (
w_18,
out_write[18],
out
);
tristate_buffer tb19 (
w_19,
out_write[19],
out
);
tristate_buffer tb20 (
w_20,
out_write[20],
out
);
tristate_buffer tb21 (
w_21,
out_write[21],
out
);
tristate_buffer tb22 (
w_22,
out_write[22],
out
);
tristate_buffer tb23 (
w_23,
out_write[23],
out
);
tristate_buffer tb24 (
w_24,
out_write[24],
out
);
tristate_buffer tb25 (
w_25,
out_write[25],
out
);
tristate_buffer tb26 (
w_26,
out_write[26],
out
);
tristate_buffer tb27 (
w_27,
out_write[27],
out
);
tristate_buffer tb28 (
w_28,
out_write[28],
out
);
tristate_buffer tb29 (
w_29,
out_write[29],
out
);
tristate_buffer tb30 (
w_30,
out_write[30],
out
);
tristate_buffer tb31 (
w_31,
out_write[31],
out
);
endmodule
| 7.116795 |
module tristatebuff_4bit (
in,
out,
low_en
);
input [3:0] in;
input low_en;
output tri [3:0] out;
assign out = low_en ? 4'bzzzz : in; //pass the output when enable is 0
endmodule
| 7.204138 |
module tristatebuff_8bit (
in,
out,
low_en
);
input [7:0] in;
input low_en;
output tri [7:0] out;
assign out = low_en ? 8'bzzzzzzzz : in; //pass the output when enable is 0
endmodule
| 7.204138 |
module tristatenet #(
parameter INPUT_COUNT = 2,
parameter WIDTH = 8
) (
input wire [WIDTH*INPUT_COUNT-1:0] i_data,
input wire [INPUT_COUNT-1:0] i_noe,
output reg [WIDTH-1:0] o_data,
output reg o_noe
);
integer i;
reg [INPUT_COUNT-1:0] ones;
always @* begin
o_data <= {WIDTH{1'b1}};
ones = 0;
for (i = 0; i < INPUT_COUNT; i = i + 1) begin
if (i_noe[i] === 0) begin
o_data <= i_data[WIDTH*(i+1)-1-:WIDTH];
ones = ones + 1;
end
end
if (ones > 1) begin
o_data <= {WIDTH{1'bx}};
$display("More than one output enable is high (%m) at %0t.", $time);
end
o_noe <= !(ones == 1);
end
endmodule
| 7.617901 |
module TristateRegBlock (
inWidth,
inHeight,
inAnimSteps,
outWidth,
outHeight,
outAnimSteps,
oe
);
input oe; // output enable
input [5:0] inWidth, inHeight;
input [2:0] inAnimSteps;
output [5:0] outWidth, outHeight;
output [2:0] outAnimSteps;
NBitTristate TriWidth (
inWidth,
oe,
outWidth
);
defparam TriWidth.n = 6;
NBitTristate TriHeight (
inHeight,
oe,
outHeight
);
defparam TriHeight.n = 6;
NBitTristate TriAnimSteps (
inAnimSteps,
oe,
outAnimSteps
);
defparam TriAnimSteps.n = 3;
endmodule
| 7.163066 |
module tristate_8bit (
input T,
input [7:0] I,
output [7:0] O
);
assign O = T ? I : 8'bZ;
endmodule
| 7.73421 |
module tristate_buffer #(
parameter N = 1
) (
data_in,
enable,
data_out
);
/*********** Inputs ***********/
input [N-1:0] data_in;
input enable;
/*********** Outputs ***********/
output [N-1:0] data_out;
/*********** Logic ***********/
assign data_out = enable ? data_in : 'bz;
endmodule
| 7.32675 |
module tristate_buffer_tb ();
localparam T = 100;
reg counter;
reg data_in;
reg enable;
wire data_out;
tristate_buffer #(1) tri_bufO (
data_in,
enable,
data_out
);
initial begin
$display("data_in enable data_out");
$monitor(" %b\t\t%b\t%b", data_in, enable, data_out);
counter = 0;
/*********** Test Case 1 ***********/
data_in = 0;
enable = 1;
#T;
/*********** Test Case 2 ***********/
data_in = 1;
enable = 1;
#T;
/*********** Test Case 3 ***********/
data_in = 0;
enable = 0;
#T;
/*********** Test Case 4 ***********/
data_in = 1;
enable = 0;
#T;
end
endmodule
| 7.32675 |
module tristate_generic #(
parameter N = 8
) (
input wire [N-1:0] in,
input wire en,
output reg [N-1:0] out
);
always @(*) begin
if (en == 1) out = in;
else out = 'bz;
end
endmodule
| 8.463288 |
module tristate_io #(
parameter SYNC_OUT = 0,
parameter SYNC_IN = 0,
parameter PULLUP = 0
) (
input wire clk,
input wire rst_n,
input wire out,
input wire oe,
output wire in,
inout wire pad
);
// ----------------------------------------------------------------------------
`ifdef FPGA_ICE40
// Based on the SB_IO library description, PIN_TYPE breaks down as follows:
//
// - bits 5:4: OUTPUT_ENABLE muxing (note OUTPUT_ENABLE is active-*high*)
//
// - 00 Always disabled
// - 01 Always enabled
// - 10: Unregistered OUTPUT_ENABLE
// - 11: Posedge-registered OUTPUT_ENABLE
//
// - bits 3:2: D_OUT_x muxing
//
// - 00: DDR, posedge-registered D_OUT_0 for half cycle following posedge,
// then negedge-registered D_OUT_1 for next half cycle
// - 01: Posedge-registered D_OUT_0
// - 10: Unregistered D_OUT_0
// - 11: Registered, inverted D_OUT_0
//
// - bits 1:0: D_IN_0 muxing (note D_IN_1 is always negedge-registered input)
//
// - 00: Posedge-registered input
// - 01: Unregistered input
// - 10: Posedge-registered input with latch (latch is transparent when
// LATCH_INPUT_VALUE is low)
// - 11: Unregistered input with latch (latch is transparent when
// LATCH_INPUT_VALUE is low)
localparam [5:0] PIN_TYPE = {
SYNC_OUT ? 2'b11 : 2'b10, SYNC_OUT ? 2'b01 : 2'b10, SYNC_IN ? 2'b00 : 2'b01
};
generate
if (SYNC_OUT == 0 && SYNC_IN == 0) begin : no_clk
// Do not connect the clock nets if not required, because it causes
// packing issues with other IOs
SB_IO #(
.PIN_TYPE(PIN_TYPE),
.PULLUP (|PULLUP)
) buffer (
.PACKAGE_PIN (pad),
.OUTPUT_ENABLE(oe),
.D_OUT_0 (out),
.D_IN_0 (in)
);
end else begin : have_clk
SB_IO #(
.PIN_TYPE(PIN_TYPE),
.PULLUP (|PULLUP)
) buffer (
.OUTPUT_CLK (clk),
.INPUT_CLK (clk),
.PACKAGE_PIN (pad),
.OUTPUT_ENABLE(oe),
.D_OUT_0 (out),
.D_IN_0 (in)
);
end
endgenerate
// ----------------------------------------------------------------------------
`else
// Synthesisable behavioural code
reg out_pad;
reg oe_pad;
wire in_pad;
generate
if (SYNC_OUT == 0) begin : no_out_ff
always @(*) begin
out_pad = out;
oe_pad = oe;
end
end else begin : have_out_ff
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out_pad <= 1'b0;
oe_pad <= 1'b0;
end else begin
out_pad <= out;
oe_pad <= oe;
end
end
end
endgenerate
generate
if (SYNC_IN == 0) begin : no_in_ff
assign in = in_pad;
end else begin : have_in_ff
reg in_r;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
in_r <= 1'b0;
end else begin
in_r <= in_pad;
end
end
assign in = in_r;
end
endgenerate
assign pad = oe_pad ? out_pad : 1'bz;
assign in_pad = pad;
`endif
endmodule
| 8.790887 |
module tristate_output (
output pin,
input wire enable,
input wire value
);
SB_IO #(
.PIN_TYPE(6'b1010_01),
.PULLUP (1'b0),
) sb_io (
.PACKAGE_PIN(pin),
.OUTPUT_ENABLE(enable),
.D_OUT_0(value),
);
endmodule
| 6.861282 |
module tristate_port (
inout io_pin,
input i_write,
output o_read
);
assign o_read = io_pin;
assign io_pin = (i_write ? 1'bz : 1'b0);
endmodule
| 7.247004 |
module TristateBuffer_Test;
// Input and outputs
logic [7:0] in, out;
// Control
logic c;
// Instantiate modules
TristateBuffer #(
.WIDTH(8)
) buffer (
.in (in),
.out(out),
.c (c)
);
initial begin
$display("Tristate buffer");
$monitor($time, " IN=%x, OUT=%x, C=%x", in, out, c);
c = 0;
in = 8'hC3;
#5 assert ($isunknown(out));
c = 0;
in = 8'h5D;
#5 assert ($isunknown(out));
c = 1;
in = 8'h81;
#5 assert (out == 8'h81);
c = 1;
in = 8'h39;
#5 assert (out == 8'h39);
c = 0;
in = 8'h39;
#5 assert ($isunknown(out));
end
endmodule
| 6.848933 |
module trivial (
input a,
input b,
output c
);
assign c = a ^ b;
endmodule
| 6.541817 |
module trivial2 (
input a,
input b,
output c
);
wire tmp1;
assign tmp1 = ~a ^ b;
wire t3o1;
wire t3o2;
trivial2a t3 (
tmp1,
t3o1,
t3o2
);
wire tmp2;
assign tmp2 = t3o1 & t3o2;
assign c = !tmp2;
endmodule
| 6.709495 |
module toplevel (
xa,
xb,
xc
);
input [10:0] xa;
input [10:0] xb;
output ya, yb;
wire [41:42] q;
reg b, c, d;
my_module #(
.BLAH(Q)
) my_name (
.a (xa),
.b (1),
.pq(1'b1),
.er(16'habcd_123),
.tr(4'd12),
.c (ya)
);
//assign ya = &xa;
//assign yb = ~&xb;
endmodule
| 8.460384 |
module triwire: bidirectional wire bus model with delay
*
* This module models the two ends of a bidirectional bus with
* transport (not inertial) delays in each direction. The
* bus has a width of WIDTH and the delays are as follows:
* a->b has a delay of Ta_b (in `timescale units)
* b->a has a delay of Tb_a (in `timescale units)
* The two delays will typically be the same. This model
* overcomes the problem of "echoes" at the receiving end of the
* wire by ensuring that data is only transmitted down the wire
* when the received data is Z. That means that there may be
* collisions resulting in X at the local end, but X's are not
* transmitted to the other end, which is a limitation of the
* model. Another compromise made in the interest of simulation
* speed is that the bus is not treated as individual wires, so
* a Z on any single wire may prevent data from being transmitted
* on other wires.
*
* The delays are reals so that they may vary throughout the
* course of a simulation. To change the delay, use the Verilog
* force command. Here is an example instantiation template:
*
real Ta_b=1, Tb_a=1;
always(Ta_b) force triwire.Ta_b = Ta_b;
always(Tb_a) force triwire.Tb_a = Tb_a;
triwire #(.WIDTH(WIDTH)) triwire (.a(a),.b(b));
* Kevin Neilson, Xilinx, 2007
*****************************************************************/
module triwire #(parameter WIDTH=1) (inout wire [WIDTH-1:0] a, b);
real Ta_b=1, Tb_a=1;
reg [WIDTH-1:0] a_dly = 'bz, b_dly = 'bz;
always @(a) a_dly <= #(Ta_b) b_dly==={WIDTH{1'bz}} ? a : 'bz;
always @(b) b_dly <= #(Tb_a) a_dly==={WIDTH{1'bz}} ? b : 'bz;
assign b = a_dly, a = b_dly;
endmodule
| 7.568704 |
module TriWireFixed #(
parameter WIDTH = 1
) (
inout wire [WIDTH-1:0] a,
b
);
tran (a, b); //not supported by xilinx ISE, even just in simulation :-S
specify
(a *> b) = (1, 1);
(b *> a) = (1, 1);
endspecify
endmodule
| 6.781771 |
module tri_agecmp (
a,
b,
a_newer_b
);
parameter SIZE = 8;
input [0:SIZE-1] a;
input [0:SIZE-1] b;
output a_newer_b;
// tri_agecmp
wire a_lt_b;
wire a_gte_b;
wire cmp_sel;
assign a_lt_b = (a[1:SIZE-1] < b[1:SIZE-1]) ? 1'b1 : 1'b0;
assign a_gte_b = (~a_lt_b);
assign cmp_sel = a[0] ~^ b[0];
assign a_newer_b = (a_lt_b & (~cmp_sel)) | (a_gte_b & cmp_sel);
endmodule
| 6.507951 |
module tri_aoi21 (
y,
a0,
a1,
b0
);
parameter WIDTH = 1;
parameter BTR = "AOI21_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;
// tri_aoi21
genvar i;
wire [0:WIDTH-1] outA;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
and I0 (outA[i], a0[i], a1[i]);
nor I2 (y[i], outA[i], b0[i]);
end // block: w
end
endgenerate
endmodule
| 7.135106 |
module tri_aoi22 (
y,
a0,
a1,
b0,
b1
);
parameter WIDTH = 1;
parameter BTR = "AOI22_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;
input [0:WIDTH-1] b1;
// tri_aoi22
genvar i;
wire [0:WIDTH-1] outA;
wire [0:WIDTH-1] outB;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
and I0 (outA[i], a0[i], a1[i]);
and I1 (outB[i], b0[i], b1[i]);
nor I2 (y[i], outA[i], outB[i]);
end // block: w
end
endgenerate
endmodule
| 7.701163 |
module tri_buf (
y,
a,
oe_n
);
parameter delay = 13;
input wire a;
input wire oe_n;
output wire y;
`ifdef TARGET_FPGA
assign y = (oe_n == 1'b0) ? a : 1'b0;
`else
assign #delay y = (oe_n == 1'b0) ? a : 1'bZ;
`endif
endmodule
| 7.410938 |
module tri_buffer_4bit (
input [3:0] signal_in,
input ctrl,
output reg [3:0] signal_out
);
always @(*) begin
if (ctrl == 0) signal_out = 4'bz;
else if (ctrl == 1) signal_out = signal_in;
end
endmodule
| 7.845289 |
module tri_compare (
clk,
a,
b,
c,
max,
mid,
min
);
parameter width = 8;
input clk;
input [width - 1:0] a;
input [width - 1:0] b;
input [width - 1:0] c;
output [width - 1:0] max;
reg [width - 1:0] max;
output [width - 1:0] mid;
reg [width - 1:0] mid;
output [width - 1:0] min;
reg [width - 1:0] min;
always @(clk) begin
if (clk == 1'b1) begin
if (a >= b & a >= c & b >= c) begin
max <= a;
mid <= b;
min <= c;
end else if (a >= b & a >= c & c >= b) begin
max <= a;
mid <= c;
min <= b;
end else if (b >= a & b >= c & a >= c) begin
max <= b;
mid <= a;
min <= c;
end else if (b >= a & b >= c & c >= a) begin
max <= b;
mid <= c;
min <= a;
end else if (c >= a & c >= b & a >= b) begin
max <= c;
mid <= a;
min <= b;
end else if (c >= a & c >= b & b >= a) begin
max <= c;
mid <= b;
min <= a;
end
end
end
endmodule
| 7.012882 |
module tri_compare (
clk,
a,
b,
c,
max,
mid,
min
);
parameter width = 8;
input clk;
input [width - 1:0] a;
input [width - 1:0] b;
input [width - 1:0] c;
output [width - 1:0] max;
reg [width - 1:0] max;
output [width - 1:0] mid;
reg [width - 1:0] mid;
output [width - 1:0] min;
reg [width - 1:0] min;
always @(clk) begin
if (clk == 1'b1) begin
if (a >= b & a >= c & b >= c) begin
max <= a;
mid <= b;
min <= c;
end else if (a >= b & a >= c & c >= b) begin
max <= a;
mid <= c;
min <= b;
end else if (b >= a & b >= c & a >= c) begin
max <= b;
mid <= a;
min <= c;
end else if (b >= a & b >= c & c >= a) begin
max <= b;
mid <= c;
min <= a;
end else if (c >= a & c >= b & a >= b) begin
max <= c;
mid <= a;
min <= b;
end else if (c >= a & c >= b & b >= a) begin
max <= c;
mid <= b;
min <= a;
end
end
end
endmodule
| 7.012882 |
module tri_csa32 (
a,
b,
c,
car,
sum,
vd,
gd
);
input a;
input b;
input c;
output car;
output sum;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *) (* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *) (* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout gd;
wire carn1;
wire carn2;
wire carn3;
// assign sum = a ^ b ^ c;
tri_xor3 CSA42_XOR3_1 (
sum,
a,
b,
c
);
// assign car = (a & b) | (a & c) | (b & c);
tri_nand2 CSA42_NAND2_1 (
carn1,
a,
b
);
tri_nand2 CSA42_NAND2_2 (
carn2,
a,
c
);
tri_nand2 CSA42_NAND2_3 (
carn3,
b,
c
);
tri_nand3 CSA42_NAND3_4 (
car,
carn1,
carn2,
carn3
);
endmodule
| 7.321591 |
module tri_csa42 (
a,
b,
c,
d,
ki,
ko,
car,
sum,
vd,
gd
);
input a;
input b;
input c;
input d;
input ki;
output ko;
output car;
output sum;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *) (* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout vd;
(* ANALYSIS_NOT_ASSIGNED="TRUE" *) (* ANALYSIS_NOT_REFERENCED="TRUE" *)
inout gd;
wire s1;
wire carn1;
wire carn2;
wire carn3;
wire kon1;
wire kon2;
wire kon3;
// assign s1 = b ^ c ^ d;
tri_xor3 CSA42_XOR3_1 (
s1,
b,
c,
d
);
// assign sum = s1 ^ a ^ ki;
tri_xor3 CSA42_XOR3_2 (
sum,
s1,
a,
ki
);
// assign car = (s1 & a) | (s1 & ki) | (a & ki);
tri_nand2 CSA42_NAND2_1 (
carn1,
s1,
a
);
tri_nand2 CSA42_NAND2_2 (
carn2,
s1,
ki
);
tri_nand2 CSA42_NAND2_3 (
carn3,
a,
ki
);
tri_nand3 CSA42_NAND3_4 (
car,
carn1,
carn2,
carn3
);
// assign ko = (b & c) | (b & d) | (c & d);
tri_nand2 CSA42_NAND2_5 (
kon1,
b,
c
);
tri_nand2 CSA42_NAND2_6 (
kon2,
b,
d
);
tri_nand2 CSA42_NAND2_7 (
kon3,
c,
d
);
tri_nand3 CSA42_NAND3_8 (
ko,
kon1,
kon2,
kon3
);
endmodule
| 7.120831 |
module tri_debug_mux4 (
// vd,
// gd,
select_bits,
dbg_group0,
dbg_group1,
dbg_group2,
dbg_group3,
trace_data_in,
trace_data_out,
// Instruction Trace (HTM) Controls
coretrace_ctrls_in,
coretrace_ctrls_out
);
// Include model build parameters
parameter DBG_WIDTH = 32; // A2o=32; A2i=88
//=====================================================================
// Port Definitions
//=====================================================================
input [0:10] select_bits;
input [0:DBG_WIDTH-1] dbg_group0;
input [0:DBG_WIDTH-1] dbg_group1;
input [0:DBG_WIDTH-1] dbg_group2;
input [0:DBG_WIDTH-1] dbg_group3;
input [0:DBG_WIDTH-1] trace_data_in;
output [0:DBG_WIDTH-1] trace_data_out;
// Instruction Trace (HTM) Control Signals:
// 0 - ac_an_coretrace_first_valid
// 1 - ac_an_coretrace_valid
// 2:3 - ac_an_coretrace_type[0:1]
input [0:3] coretrace_ctrls_in;
output [0:3] coretrace_ctrls_out;
//=====================================================================
// Signal Declarations / Misc
//=====================================================================
parameter DBG_1FOURTH = DBG_WIDTH / 4;
parameter DBG_2FOURTH = DBG_WIDTH / 2;
parameter DBG_3FOURTH = 3 * DBG_WIDTH / 4;
wire [0:DBG_WIDTH-1] debug_grp_selected;
wire [0:DBG_WIDTH-1] debug_grp_rotated;
// Don't reference unused inputs:
(* analysis_not_referenced="true" *)
wire unused;
assign unused = (|select_bits[2:4]);
// Instruction Trace controls are passed-through:
assign coretrace_ctrls_out = coretrace_ctrls_in;
//=====================================================================
// Mux Function
//=====================================================================
// Debug Mux
assign debug_grp_selected = (select_bits[0:1] == 2'b00) ? dbg_group0 :
(select_bits[0:1] == 2'b01) ? dbg_group1 :
(select_bits[0:1] == 2'b10) ? dbg_group2 :
dbg_group3;
assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
(select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
(select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
debug_grp_selected[0:DBG_WIDTH - 1];
assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
debug_grp_rotated[0:DBG_1FOURTH - 1];
assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];
assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];
assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];
endmodule
| 7.764024 |
module tri_direct_err_rpt (
vd,
gd,
err_in,
err_out
);
parameter WIDTH = 1; // use to bundle error reporting checkers of the same exact type
inout vd;
inout gd;
input [0:WIDTH-1] err_in;
output [0:WIDTH-1] err_out;
// tri_direct_err_rpt
(* analysis_not_referenced="true" *)
wire unused;
assign unused = vd | gd;
assign err_out = err_in;
endmodule
| 7.651156 |
module tri_err_rpt (
vd,
gd,
err_d1clk,
err_d2clk,
err_lclk,
err_scan_in,
err_scan_out,
mode_dclk,
mode_lclk,
mode_scan_in,
mode_scan_out,
err_in,
err_out,
hold_out,
mask_out
);
parameter WIDTH = 1; // number of errors of the same type
parameter MASK_RESET_VALUE = 1'b0; // use to set default/flush value for mask bits
parameter INLINE = 1'b0; // make hold latch be inline; err_out is sticky -- default to shadow
parameter SHARE_MASK = 1'b0; // PERMISSION NEEDED for true
// used for WIDTH >1 to reduce area of mask (common error disable)
parameter USE_NLATS = 1'b0; // only necessary in standby area to be able to reset to init value
parameter NEEDS_SRESET = 1; // for inferred latches
inout vd;
inout gd;
input err_d1clk; // caution1: if lcb uses powersavings, errors must always get reported
input err_d2clk; // caution2: if use_nlats is used these are also the clocks for the mask latches
input [0:`NCLK_WIDTH-1] err_lclk; // caution2: hence these have to be the mode clocks
// caution2: and all bits in the "func" chain have to be connected to the mode chain
// error scan chain (func or mode)
input [0:WIDTH-1] err_scan_in; // NOTE: connected to mode or func ring
output [0:WIDTH-1] err_scan_out;
// clock gateable mode clocks
input mode_dclk;
input [0:`NCLK_WIDTH-1] mode_lclk;
// mode scan chain
input [0:WIDTH-1] mode_scan_in;
output [0:WIDTH-1] mode_scan_out;
input [0:WIDTH-1] err_in;
output [0:WIDTH-1] err_out;
output [0:WIDTH-1] hold_out; // sticky error hold latch for trap usage
output [0:WIDTH-1] mask_out;
// tri_err_rpt
parameter [0:WIDTH-1] mask_initv = MASK_RESET_VALUE;
wire [0:WIDTH-1] hold_in;
wire [0:WIDTH-1] hold_lt;
wire [0:WIDTH-1] mask_lt;
(* analysis_not_referenced="true" *)
wire unused;
wire [0:WIDTH-1] unused_q_b;
// hold latches
assign hold_in = err_in | hold_lt;
tri_nlat_scan #(
.WIDTH(WIDTH),
.NEEDS_SRESET(NEEDS_SRESET)
) hold (
.vd(vd),
.gd(gd),
.d1clk(err_d1clk),
.d2clk(err_d2clk),
.lclk(err_lclk),
.scan_in(err_scan_in[0:WIDTH-1]),
.scan_out(err_scan_out[0:WIDTH-1]),
.din(hold_in),
.q(hold_lt),
.q_b(unused_q_b)
);
generate
begin
// mask
if (SHARE_MASK == 1'b0) begin : m
assign mask_lt = mask_initv;
end
if (SHARE_MASK == 1'b1) begin : sm
assign mask_lt = {WIDTH{MASK_RESET_VALUE[0]}};
end
assign mode_scan_out = {WIDTH{1'b0}};
// assign outputs
assign hold_out = hold_lt;
assign mask_out = mask_lt;
if (INLINE == 1'b1) begin : inline_hold
assign err_out = hold_lt & (~mask_lt);
end
if (INLINE == 1'b0) begin : side_hold
assign err_out = err_in & (~mask_lt);
end
assign unused = |{mode_dclk, mode_lclk, mode_scan_in, unused_q_b};
end
endgenerate
endmodule
| 8.813933 |
module tri_fu_csa22_h2 (
a,
b,
car,
sum
);
input a;
input b;
output car;
output sum;
wire car_b;
wire sum_b;
assign car_b = (~(a & b));
assign sum_b = (~(car_b & (a | b))); // this is equiv to an xnor
assign car = (~car_b);
assign sum = (~sum_b);
endmodule
| 6.614777 |
module tri_gen (
clk,
res,
d_out
);
input clk;
input res;
output [8:0] d_out;
reg [1:0] state; //主状态机的寄存器
reg [8:0] d_out;
reg [7:0] con; //计数器用于记录平顶周期个数
always @(posedge clk or negedge res) begin
if (~res) begin
state <= 0;
d_out <= 0;
con <= 0;
end else begin
case (state)
0: //上升
begin
d_out <= d_out + 1;
if (d_out == 299) begin
state <= 2;
end
end
1: //下降
begin
d_out <= d_out - 1;
if (d_out == 1) begin
state <= 3;
end
end
2: //上平顶
begin
con <= con + 1;
if (con == 200) begin
state <= 1;
con <= 0;
end else begin
con <= con + 1;
end
end
3: //下平顶
begin
con <= con + 1;
if (con == 200) begin
state <= 0;
con <= 0;
end else begin
con <= con + 1;
end
end
endcase
end
end
endmodule
| 7.18462 |
module tri_gen_tb;
reg clk;
reg res;
wire [8:0] d;
tri_gen tri_gen (
.clk (clk),
.res (res),
.d_out(d)
);
initial begin
clk <= 0;
res <= 0;
#17 res <= 1;
#40000 $stop;
end
always #5 clk <= ~clk;
initial begin
$dumpfile("tri_gen_tb.vcd");
$dumpvars;
end
endmodule
| 6.833462 |
module tri_gt (
OE,
id,
od
);
input wire OE;
input wire [15:0] id;
output wire [15:0] od;
assign od = (!OE) ? 16'dz : id;
endmodule
| 6.995172 |
module tri_inv (
y,
a
);
parameter WIDTH = 1;
parameter BTR = "INV_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
// tri_nand2
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
not I0 (y[i], a[i]);
end // block: w
end
endgenerate
endmodule
| 7.509959 |
module tri_inv_nlats (
vd,
gd,
lclk,
d1clk,
d2clk,
scanin,
scanout,
d,
qb
);
parameter OFFSET = 0;
parameter WIDTH = 1;
parameter INIT = 0;
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
parameter SYNTHCLONEDLATCH = "";
parameter BTR = "NLI0001_X1_A12TH";
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] lclk;
input d1clk;
input d2clk;
input [OFFSET:OFFSET+WIDTH-1] scanin;
output [OFFSET:OFFSET+WIDTH-1] scanout;
input [OFFSET:OFFSET+WIDTH-1] d;
output [OFFSET:OFFSET+WIDTH-1] qb;
// tri_inv_nlats
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
wire [0:WIDTH-1] din;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1) begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1) begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign din = d; // Output is inverted, so don't invert here
assign int_din = (vsreset_b & din) | (vsreset & init_v);
assign vact = {WIDTH{d1clk}};
assign vact_b = {WIDTH{~d1clk}};
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};
always @(posedge lclk[0]) begin : l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign qb = (~int_dout);
assign scanout = ZEROS;
assign unused = |{vd, gd, lclk, scanin};
end
endgenerate
endmodule
| 7.23967 |
module tri_io_buf #(
parameter WIDTH = 1
) (
input wire [WIDTH-1:0] din,
input wire oen_N,
inout wire [WIDTH-1:0] io_pad,
output wire [WIDTH-1:0] dout
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
IOBUF #(
.DRIVE (12), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD ("DEFAULT") // Specify the I/O standard
) IOBUF_inst (
.O (dout[i]), // Buffer output (data to core)
.IO(io_pad[i]), // Buffer inout port (To I/O pad)
.I (din[i]), // Buffer input (core to I/O pad)
.T (oen_N) // 3-state enable input, high=tristate hence input, low=output
);
end
endgenerate
endmodule
| 9.017246 |
module tri_lcbcntl_array_mac (
vdd,
gnd,
sg,
nclk,
scan_in,
scan_diag_dc,
thold,
clkoff_dc_b,
delay_lclkr_dc,
act_dis_dc,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
scan_out
);
inout vdd;
inout gnd;
input sg;
input [0:`NCLK_WIDTH-1] nclk;
input scan_in;
input scan_diag_dc;
input thold;
output clkoff_dc_b;
output [0:4] delay_lclkr_dc;
output act_dis_dc;
output d_mode_dc;
output [0:4] mpw1_dc_b;
output mpw2_dc_b;
output scan_out;
// tri_lcbcntl_array_mac
(* analysis_not_referenced="true" *)
wire unused;
assign clkoff_dc_b = 1'b1;
assign delay_lclkr_dc = 5'b00000;
assign act_dis_dc = 1'b0;
assign d_mode_dc = 1'b0;
assign mpw1_dc_b = 5'b11111;
assign mpw2_dc_b = 1'b1;
assign scan_out = 1'b0;
assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold;
endmodule
| 6.693849 |
module tri_lcbnd (
vd,
gd,
act,
delay_lclkr,
mpw1_b,
mpw2_b,
nclk,
force_t,
sg,
thold_b,
d1clk,
d2clk,
lclk
);
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input act;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input [0:`NCLK_WIDTH-1] nclk;
input force_t;
input sg;
input thold_b;
output d1clk;
output d2clk;
output [0:`NCLK_WIDTH-1] lclk;
// tri_lcbnd
wire gate_b;
(* analysis_not_referenced="true" *)
wire unused;
assign unused = vd | gd | delay_lclkr | mpw1_b | mpw2_b | sg;
assign gate_b = force_t | act;
assign d1clk = gate_b;
assign d2clk = thold_b;
assign lclk = nclk;
endmodule
| 7.722264 |
module tri_lcbs (
vd,
gd,
delay_lclkr,
nclk,
force_t,
thold_b,
dclk,
lclk
);
inout vd;
inout gd;
input delay_lclkr;
input [0:`NCLK_WIDTH-1] nclk;
input force_t;
input thold_b;
output dclk;
output [0:`NCLK_WIDTH-1] lclk;
// tri_lcbs
(* analysis_not_referenced="true" *)
wire unused;
assign unused = vd | gd | delay_lclkr | force_t;
// No scan chain in this methodology
assign dclk = thold_b;
assign lclk = nclk;
endmodule
| 6.98358 |
module tri_mode_ethernet_mac_0_axi_mux (
input mux_select,
// mux inputs
input [7:0] tdata0,
input tvalid0,
input tlast0,
output reg tready0,
input [7:0] tdata1,
input tvalid1,
input tlast1,
output reg tready1,
// mux outputs
output reg [7:0] tdata,
output reg tvalid,
output reg tlast,
input tready
);
always @(mux_select or tdata0 or tvalid0 or tlast0 or tdata1 or tvalid1 or tlast1) begin
if (mux_select) begin
tdata = tdata1;
tvalid = tvalid1;
tlast = tlast1;
end else begin
tdata = tdata0;
tvalid = tvalid0;
tlast = tlast0;
end
end
always @(mux_select or tready) begin
if (mux_select) begin
tready0 = 1'b1;
end else begin
tready0 = tready;
end
tready1 = tready;
end
endmodule
| 6.950534 |
module to simplify the timing where a pattern
// generator and address swap module can be muxed into the data path
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module tri_mode_ethernet_mac_0_axi_pipe (
input axi_tclk,
input axi_tresetn,
input [7:0] rx_axis_fifo_tdata_in,
input rx_axis_fifo_tvalid_in,
input rx_axis_fifo_tlast_in,
output rx_axis_fifo_tready_in,
output [7:0] rx_axis_fifo_tdata_out,
output rx_axis_fifo_tvalid_out,
output rx_axis_fifo_tlast_out,
input rx_axis_fifo_tready_out
);
reg [5:0] rd_addr;
reg [5:0] wr_addr;
reg wea;
reg rx_axis_fifo_tready_int;
reg rx_axis_fifo_tvalid_int;
wire [1:0] wr_block;
wire [1:0] rd_block;
assign rx_axis_fifo_tready_in = rx_axis_fifo_tready_int;
assign rx_axis_fifo_tvalid_out = rx_axis_fifo_tvalid_int;
// should always write when valid data is accepted
always @(rx_axis_fifo_tvalid_in or rx_axis_fifo_tready_int)
begin
wea = rx_axis_fifo_tvalid_in & rx_axis_fifo_tready_int;
end
// simply increment the write address after any valid write
always @(posedge axi_tclk)
begin
if (!axi_tresetn) begin
wr_addr <= 0;
end
else begin
if (rx_axis_fifo_tvalid_in & rx_axis_fifo_tready_int)
wr_addr <= wr_addr + 1;
end
end
// simply increment the read address after any validated read
always @(posedge axi_tclk)
begin
if (!axi_tresetn) begin
rd_addr <= 0;
end
else begin
if (rx_axis_fifo_tvalid_int & rx_axis_fifo_tready_out)
rd_addr <= rd_addr + 1;
end
end
assign wr_block = wr_addr[5:4];
assign rd_block = rd_addr[5:4]-1;
// need to generate the ready output - this is entirely dependant upon the full state
// of the fifo
always @(posedge axi_tclk)
begin
if (!axi_tresetn) begin
rx_axis_fifo_tready_int <= 0;
end
else begin
if (wr_block == rd_block)
rx_axis_fifo_tready_int <= 0;
else
rx_axis_fifo_tready_int <= 1;
end
end
// need to generate the valid output - this is entirely dependant upon the full state
// of the fifo
always @(rd_addr or wr_addr)
begin
if (rd_addr == wr_addr)
rx_axis_fifo_tvalid_int <= 0;
else
rx_axis_fifo_tvalid_int <= 1;
end
genvar i;
generate
for (i=0; i<=7; i=i+1) begin : ram_loop
RAM64X1D RAM64X1D_inst (
.DPO (rx_axis_fifo_tdata_out[i]),
.SPO (),
.A0 (wr_addr[0]),
.A1 (wr_addr[1]),
.A2 (wr_addr[2]),
.A3 (wr_addr[3]),
.A4 (wr_addr[4]),
.A5 (wr_addr[5]),
.D (rx_axis_fifo_tdata_in[i]),
.DPRA0 (rd_addr[0]),
.DPRA1 (rd_addr[1]),
.DPRA2 (rd_addr[2]),
.DPRA3 (rd_addr[3]),
.DPRA4 (rd_addr[4]),
.DPRA5 (rd_addr[5]),
.WCLK (axi_tclk),
.WE (wea)
);
end
endgenerate
RAM64X1D RAM64X1D_inst_last (
.DPO (rx_axis_fifo_tlast_out),
.SPO (),
.A0 (wr_addr[0]),
.A1 (wr_addr[1]),
.A2 (wr_addr[2]),
.A3 (wr_addr[3]),
.A4 (wr_addr[4]),
.A5 (wr_addr[5]),
.D (rx_axis_fifo_tlast_in),
.DPRA0 (rd_addr[0]),
.DPRA1 (rd_addr[1]),
.DPRA2 (rd_addr[2]),
.DPRA3 (rd_addr[3]),
.DPRA4 (rd_addr[4]),
.DPRA5 (rd_addr[5]),
.WCLK (axi_tclk),
.WE (wea)
);
endmodule
| 6.900006 |
module tri_mode_ethernet_mac_0_clk_wiz ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
// Status and control signals
input RESET,
output LOCKED
);
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F(10.000),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE_F (8.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE(0.500),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE(0.500),
.CLKOUT2_DIVIDE (40),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE(0.500),
.CLKIN1_PERIOD(10.000),
.REF_JITTER1 (0.010)
) mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout),
.CLKFBOUTB(clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (CLK_IN1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED(clkinstopped_unused),
.CLKFBSTOPPED(clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET)
);
// Output buffering
//-----------------------------------
BUFGCE clkout1_buf (
.O (CLK_OUT1),
.CE(1'b1),
.I (clkout0)
);
BUFGCE clkout2_buf (
.O (CLK_OUT2),
.CE(1'b1),
.I (clkout1)
);
BUFGCE clkout3_buf (
.O (CLK_OUT3),
.CE(1'b1),
.I (clkout2)
);
endmodule
| 6.950534 |
module tri_mode_ethernet_mac_0_example_design_clocks (
input gtx_clk,
// clock outputs
output gtx_clk_bufg,
output s_axi_aclk
);
//----------------------------------------------------------------------------
// Transmitter Clock logic for gtx_clk
//----------------------------------------------------------------------------
// route gtx_clk through a BUFGCE and onto global clock routing
BUFGCE bufg_gtx_clk (
.I (gtx_clk),
.CE(1'b1),
.O (gtx_clk_bufg)
);
//----------------------------------------------------------------------------
// Generate the s_axi_aclk for configuration by processor .
//----------------------------------------------------------------------------
// we only have one clock source (gtx_clk) so it will be derived from that
BUFGCE bufg_axi_clk (
.I (gtx_clk),
.CE(1'b1),
.O (s_axi_aclk)
);
endmodule
| 6.950534 |
module tri_mode_ethernet_mac_0_example_design_resets (
// clocks
input s_axi_aclk,
input gtx_clk,
// asynchronous resets
input glbl_rst,
input reset_error,
input rx_reset,
input tx_reset,
// asynchronous reset output
output glbl_rst_intn,
// synchronous reset outputs
output reg gtx_resetn = 0,
output reg s_axi_resetn = 0,
output reg chk_resetn = 0
);
// define internal signals
reg s_axi_pre_resetn = 0;
wire s_axi_reset_int;
reg gtx_pre_resetn = 0;
wire gtx_clk_reset_int;
reg chk_pre_resetn = 0;
wire chk_reset_int;
//----------------------------------------------------------------------------
// Generate resets required for the fifo side signals etc
//----------------------------------------------------------------------------
// in each case the async reset is first captured and then synchronised
assign glbl_rst_intn = !glbl_rst;
//---------------
// AXI-Lite reset
tri_mode_ethernet_mac_0_reset_sync axi_lite_reset_gen (
.clk (s_axi_aclk),
.enable (1'b1),
.reset_in (glbl_rst),
.reset_out(s_axi_reset_int)
);
// Create fully synchronous reset in the s_axi clock domain.
always @(posedge s_axi_aclk) begin
if (s_axi_reset_int) begin
s_axi_pre_resetn <= 0;
s_axi_resetn <= 0;
end else begin
s_axi_pre_resetn <= 1;
s_axi_resetn <= s_axi_pre_resetn;
end
end
//---------------
// gtx_clk reset
tri_mode_ethernet_mac_0_reset_sync gtx_reset_gen (
.clk(gtx_clk),
.enable (1'b1),
.reset_in(glbl_rst || rx_reset || tx_reset),
.reset_out(gtx_clk_reset_int)
);
// Create fully synchronous reset in the gtx_clk domain.
always @(posedge gtx_clk) begin
if (gtx_clk_reset_int) begin
gtx_pre_resetn <= 0;
gtx_resetn <= 0;
end else begin
gtx_pre_resetn <= 1;
gtx_resetn <= gtx_pre_resetn;
end
end
//---------------
// data check reset
tri_mode_ethernet_mac_0_reset_sync chk_reset_gen (
.clk(gtx_clk),
.enable (1'b1),
.reset_in (glbl_rst || reset_error),
.reset_out(chk_reset_int)
);
// Create fully synchronous reset in the gtx_clk domain.
always @(posedge gtx_clk) begin
if (chk_reset_int) begin
chk_pre_resetn <= 0;
chk_resetn <= 0;
end else begin
chk_pre_resetn <= 1;
chk_resetn <= chk_pre_resetn;
end
end
endmodule
| 6.950534 |
module tri_mode_ethernet_mac_0_reset_sync #(
parameter INITIALISE = 1'b1,
parameter DEPTH = 5
) (
input reset_in,
input clk,
input enable,
output reset_out
);
wire reset_sync_reg0;
wire reset_sync_reg1;
wire reset_sync_reg2;
wire reset_sync_reg3;
wire reset_sync_reg4;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDPE #(
.INIT(INITIALISE[0])
) reset_sync0 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (1'b0),
.Q (reset_sync_reg0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDPE #(
.INIT(INITIALISE[0])
) reset_sync1 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_sync_reg0),
.Q (reset_sync_reg1)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDPE #(
.INIT(INITIALISE[0])
) reset_sync2 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_sync_reg1),
.Q (reset_sync_reg2)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDPE #(
.INIT(INITIALISE[0])
) reset_sync3 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_sync_reg2),
.Q (reset_sync_reg3)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDPE #(
.INIT(INITIALISE[0])
) reset_sync4 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_sync_reg3),
.Q (reset_sync_reg4)
);
assign reset_out = reset_sync_reg4;
endmodule
| 6.950534 |
module holds the shared resets for the IDELAYCTRL
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
module tri_mode_ethernet_mac_0_support_resets
(
input glbl_rstn,
input refclk,
input idelayctrl_ready,
output idelayctrl_reset_out);
wire glbl_rst;
wire idelayctrl_reset_in; // Used to trigger reset_sync generation in refclk domain.
wire idelayctrl_reset_sync; // Used to create a reset pulse in the IDELAYCTRL refclk domain.
reg [3:0] idelay_reset_cnt; // Counter to create a long IDELAYCTRL reset pulse.
reg idelayctrl_reset;
assign glbl_rst = !glbl_rstn;
//----------------------------------------------------------------------------
// Reset circuitry associated with the IDELAYCTRL
//----------------------------------------------------------------------------
assign idelayctrl_reset_out = idelayctrl_reset;
assign idelayctrl_reset_in = glbl_rst || !idelayctrl_ready;
// Create a synchronous reset in the IDELAYCTRL refclk clock domain.
tri_mode_ethernet_mac_0_reset_sync idelayctrl_reset_gen (
.clk (refclk),
.enable (1'b1),
.reset_in (idelayctrl_reset_in),
.reset_out (idelayctrl_reset_sync)
);
// Reset circuitry for the IDELAYCTRL reset.
// The IDELAYCTRL must experience a pulse which is at least 50 ns in
// duration. This is ten clock cycles of the 200MHz refclk. Here we
// drive the reset pulse for 12 clock cycles.
always @(posedge refclk)
begin
if (idelayctrl_reset_sync) begin
idelay_reset_cnt <= 4'b0000;
idelayctrl_reset <= 1'b1;
end
else begin
case (idelay_reset_cnt)
4'b0000 : idelay_reset_cnt <= 4'b0001;
4'b0001 : idelay_reset_cnt <= 4'b0010;
4'b0010 : idelay_reset_cnt <= 4'b0011;
4'b0011 : idelay_reset_cnt <= 4'b0100;
4'b0100 : idelay_reset_cnt <= 4'b0101;
4'b0101 : idelay_reset_cnt <= 4'b0110;
4'b0110 : idelay_reset_cnt <= 4'b0111;
4'b0111 : idelay_reset_cnt <= 4'b1000;
4'b1000 : idelay_reset_cnt <= 4'b1001;
4'b1001 : idelay_reset_cnt <= 4'b1010;
4'b1010 : idelay_reset_cnt <= 4'b1011;
4'b1011 : idelay_reset_cnt <= 4'b1100;
default : idelay_reset_cnt <= 4'b1100;
endcase
if (idelay_reset_cnt == 4'b1100) begin
idelayctrl_reset <= 1'b0;
end
else begin
idelayctrl_reset <= 1'b1;
end
end
end
endmodule
| 7.143026 |
module tri_mode_ethernet_mac_0_syncer_level #(
parameter WIDTH = 1,
parameter RESET_VALUE = 1'b0
) (
input wire clk,
input wire reset,
input wire [WIDTH-1:0] datain,
output wire [WIDTH-1:0] dataout
);
(* ASYNC_REG = "TRUE" *)reg [WIDTH-1:0] dataout_reg;
reg [WIDTH-1:0] meta_nxt;
wire [WIDTH-1:0] dataout_nxt;
(* ASYNC_REG = "TRUE" *)reg [WIDTH-1:0] meta;
(* ASYNC_REG = "TRUE" *)reg [WIDTH-1:0] meta2;
always @* begin
meta_nxt = datain;
end
always @(posedge clk) begin
if (reset == 1'b1) begin
meta <= {WIDTH{RESET_VALUE}};
meta2 <= {WIDTH{RESET_VALUE}};
end else begin
meta <= meta_nxt;
meta2 <= meta;
end
end
assign dataout_nxt = meta2;
always @(posedge clk) begin
if (reset == 1'b1) begin
dataout_reg <= {WIDTH{RESET_VALUE}};
end else begin
dataout_reg <= dataout_nxt;
end
end
assign dataout = dataout_reg;
endmodule
| 6.950534 |
module tri_mode_ethernet_mac_0_sync_block #(
parameter INITIALISE = 1'b0,
parameter DEPTH = 5
) (
input clk, // clock to be sync'ed to
input data_in, // Data to be 'synced'
output data_out // synced data
);
// Internal Signals
wire data_sync0;
wire data_sync1;
wire data_sync2;
wire data_sync3;
wire data_sync4;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT(INITIALISE[0])
) data_sync_reg0 (
.C (clk),
.D (data_in),
.Q (data_sync0),
.CE(1'b1),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT(INITIALISE[0])
) data_sync_reg1 (
.C (clk),
.D (data_sync0),
.Q (data_sync1),
.CE(1'b1),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT(INITIALISE[0])
) data_sync_reg2 (
.C (clk),
.D (data_sync1),
.Q (data_sync2),
.CE(1'b1),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT(INITIALISE[0])
) data_sync_reg3 (
.C (clk),
.D (data_sync2),
.Q (data_sync3),
.CE(1'b1),
.R (1'b0)
);
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
FDRE #(
.INIT(INITIALISE[0])
) data_sync_reg4 (
.C (clk),
.D (data_sync3),
.Q (data_sync4),
.CE(1'b1),
.R (1'b0)
);
assign data_out = data_sync4;
endmodule
| 6.950534 |
module tri_mode_eth_mac_v5_2 (
//---------------------------------------
// asynchronous reset
input glbl_rstn,
input rx_axi_rstn,
input tx_axi_rstn,
//---------------------------------------
// Receiver Interface
input rx_axi_clk,
output rx_reset_out,
output [ 7:0] rx_axis_mac_tdata,
output rx_axis_mac_tvalid,
output rx_axis_mac_tlast,
output rx_axis_mac_tuser,
// Receiver Statistics
output [27:0] rx_statistics_vector,
output rx_statistics_valid,
//---------------------------------------
// Transmitter Interface
input tx_axi_clk,
output tx_reset_out,
input [7:0] tx_axis_mac_tdata,
input tx_axis_mac_tvalid,
input tx_axis_mac_tlast,
input tx_axis_mac_tuser,
output tx_axis_mac_tready,
output tx_retransmit,
output tx_collision,
input [ 7:0] tx_ifg_delay,
// Transmitter Statistics
output [31:0] tx_statistics_vector,
output tx_statistics_valid,
//---------------------------------------
// MAC Control Interface
input pause_req,
input [15:0] pause_val,
//---------------------------------------
// Current Speed Indication
output speed_is_100,
output speed_is_10_100,
//---------------------------------------
// Physical Interface of the core
output [7:0] gmii_txd,
output gmii_tx_en,
output gmii_tx_er,
input gmii_col,
input gmii_crs,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
// MDIO Interface
output mdc_out,
input mdio_in,
output mdio_out,
output mdio_tri,
//---------------------------------------
// IPIC Interface
input bus2ip_clk,
input bus2ip_reset,
input [31:0] bus2ip_addr,
input bus2ip_cs,
input bus2ip_rdce,
input bus2ip_wrce,
input [31:0] bus2ip_data,
output [31:0] ip2bus_data,
output ip2bus_wrack,
output ip2bus_rdack,
output ip2bus_error,
output mac_irq
);
endmodule
| 7.873981 |
module tri_nand2 (
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "NAND2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
// tri_nand2
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
nand I0 (y[i], a[i], b[i]);
end // block: w
end
endgenerate
endmodule
| 7.742585 |
module tri_nand2_nlats (
vd,
gd,
lclk,
d1clk,
d2clk,
scanin,
scanout,
a1,
a2,
qb
);
parameter OFFSET = 0;
parameter WIDTH = 1;
parameter INIT = 0;
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
parameter SYNTHCLONEDLATCH = "";
parameter BTR = "NLA0001_X1_A12TH";
parameter NEEDS_SRESET = 1; // for inferred latches
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] lclk;
input d1clk;
input d2clk;
input [OFFSET:OFFSET+WIDTH-1] scanin;
output [OFFSET:OFFSET+WIDTH-1] scanout;
input [OFFSET:OFFSET+WIDTH-1] a1;
input [OFFSET:OFFSET+WIDTH-1] a2;
output [OFFSET:OFFSET+WIDTH-1] qb;
// tri_nand2_nlats
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
wire [0:WIDTH-1] din;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1) begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1) begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign din = a1 & a2; // Output is inverted, so just AND2 here
assign int_din = (vsreset_b & din) | (vsreset & init_v);
assign vact = {WIDTH{d1clk}};
assign vact_b = {WIDTH{~d1clk}};
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};
always @(posedge lclk[0]) begin : l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign qb = (~int_dout);
assign scanout = ZEROS;
assign unused = |{vd, gd, lclk, scanin};
end
endgenerate
endmodule
| 6.806358 |
module tri_nand3 (
y,
a,
b,
c
);
parameter WIDTH = 1;
parameter BTR = "NAND3_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
input [0:WIDTH-1] c;
// tri_nand3
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
nand I0 (y[i], a[i], b[i], c[i]);
end // block: w
end
endgenerate
endmodule
| 7.920777 |
module tri_nand4 (
y,
a,
b,
c,
d
);
parameter WIDTH = 1;
parameter BTR = "NAND4_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
input [0:WIDTH-1] c;
input [0:WIDTH-1] d;
// tri_nand3
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
nand I0 (y[i], a[i], b[i], c[i], d[i]);
end // block: w
end
endgenerate
endmodule
| 8.0048 |
module tri_nlat (
vd,
gd,
d1clk,
d2clk,
lclk,
scan_in,
din,
q,
q_b,
scan_out
);
parameter OFFSET = 0;
parameter SCAN = 0; //SCAN = normal;
//0=normal,1=interleaved,2=reversed,3=reverse_interleaved
parameter RESET_INVERTS_SCAN = 1'b1;
parameter WIDTH = 1;
parameter INIT = 0;
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
parameter SYNTHCLONEDLATCH = "";
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0; // 0 - Internal Flop, 1 - Domain Crossing Input Flop (requires extra logic for ASICs)
inout vd;
inout gd;
input d1clk;
input d2clk;
input [0:`NCLK_WIDTH-1] lclk;
input scan_in;
input [OFFSET:OFFSET+WIDTH-1] din;
output [OFFSET:OFFSET+WIDTH-1] q;
output [OFFSET:OFFSET+WIDTH-1] q_b;
output scan_out;
// tri_nlat
parameter [0:WIDTH-1] init_v = INIT;
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1) begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1) begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign int_din = (vsreset_b & din) | (vsreset & init_v);
assign vact = {WIDTH{d1clk}};
assign vact_b = {WIDTH{~d1clk}};
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};
always @(posedge lclk[0]) begin : l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign q = int_dout;
assign q_b = (~int_dout);
assign scan_out = 1'b0;
assign unused = |{vd, gd, lclk, scan_in};
end
endgenerate
endmodule
| 7.232446 |
module tri_nlat_scan (
vd,
gd,
d1clk,
d2clk,
lclk,
din,
scan_in,
q,
q_b,
scan_out
);
parameter OFFSET = 0;
parameter WIDTH = 1;
parameter INIT = 0;
parameter RESET_INVERTS_SCAN = 1'b1;
parameter SYNTHCLONEDLATCH = "";
parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch;
//0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0; // 0 - Internal Flop, 1 - Domain Crossing Input Flop (requires extra logic for ASICs)
inout vd;
inout gd;
input d1clk;
input d2clk;
input [0:`NCLK_WIDTH-1] lclk;
input [OFFSET:OFFSET+WIDTH-1] din;
input [OFFSET:OFFSET+WIDTH-1] scan_in;
output [OFFSET:OFFSET+WIDTH-1] q;
output [OFFSET:OFFSET+WIDTH-1] q_b;
output [OFFSET:OFFSET+WIDTH-1] scan_out;
// tri_nlat_scan
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1) begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1) begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign int_din = (vsreset_b & din) | (vsreset & init_v);
assign vact = {WIDTH{d1clk}};
assign vact_b = {WIDTH{~d1clk}};
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};
always @(posedge lclk[0]) begin : l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign q = int_dout;
assign q_b = (~int_dout);
assign scan_out = ZEROS;
assign unused = |{vd, gd, lclk, scan_in};
end
endgenerate
endmodule
| 7.138693 |
module tri_nor2 (
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "NOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
// tri_nor2
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
nor I0 (y[i], a[i], b[i]);
end // block: w
end
endgenerate
endmodule
| 6.915532 |
module tri_nor3 (
y,
a,
b,
c
);
parameter WIDTH = 1;
parameter BTR = "NOR3_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
input [0:WIDTH-1] c;
// tri_nor3
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
nor I0 (y[i], a[i], b[i], c[i]);
end // block: w
end
endgenerate
endmodule
| 7.989546 |
module tri_oai21 (
y,
a0,
a1,
b0
);
parameter WIDTH = 1;
parameter BTR = "OAI21_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a0;
input [0:WIDTH-1] a1;
input [0:WIDTH-1] b0;
// tri_oai21
genvar i;
wire [0:WIDTH-1] outA;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
or I0 (outA[i], a0[i], a1[i]);
nand I2 (y[i], outA[i], b0[i]);
end // block: w
end
endgenerate
endmodule
| 7.0944 |
module tri_plat (
vd,
gd,
nclk,
flush,
din,
q
);
parameter WIDTH = 1;
parameter OFFSET = 0;
parameter INIT = 0; // will be converted to the least signficant 31 bits of init_v
parameter SYNTHCLONEDLATCH = "";
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input flush;
input [OFFSET:OFFSET+WIDTH-1] din;
output [OFFSET:OFFSET+WIDTH-1] q;
// tri_plat
reg [OFFSET:OFFSET+WIDTH-1] int_dout;
(* analysis_not_referenced="true" *)
wire unused;
assign unused = |{vd, gd, nclk[1:`NCLK_WIDTH-1]};
always @(posedge nclk[0]) begin
int_dout <= din;
end
assign q = (flush == 1'b1) ? din : int_dout;
endmodule
| 6.587067 |
module tri_ported_fifo #(
parameter WIDTH = 64,
parameter DEPTH = 24
) (
input wire [WIDTH-1:0] data_in1,
input wire [WIDTH-1:0] data_in2,
input wire [WIDTH-1:0] data_in3,
input wire clk,
input wire rst,
input wire write1,
input wire write2,
input wire write3,
input wire read,
output reg [WIDTH-1:0] data_out,
output wire fifo_full,
output wire fifo_empty
// output wire fifo_not_empty,
// output wire fifo_not_full
);
// memory will contain the FIFO data.
// $clog2(DEPTH+1) == bits-to-address-DEPTH
//reg [WIDTH-1:0] memory [0:$clog2(DEPTH+1)];
reg [ DEPTH*WIDTH-1:0] memory;
// $clog2(DEPTH+1)-2 to count from 0 to DEPTH
reg [$clog2(DEPTH)-1:0] write_ptr;
reg [$clog2(DEPTH)-1:0] read_ptr;
// Initialization
initial begin
// Init both write_cnt and read_cnt to 0
write_ptr = 0;
read_ptr = 0;
// Display error if WIDTH is 0 or less.
if (WIDTH <= 0) begin
$error("%m ** Illegal condition **, you used %d WIDTH", WIDTH);
end
// Display error if DEPTH is 0 or less.
if (DEPTH <= 0) begin
$error("%m ** Illegal condition **, you used %d DEPTH", DEPTH);
end
end // end initial
assign fifo_empty = (write_ptr == 0) ? 1'b1 : 1'b0;
assign fifo_full = (write_ptr == (DEPTH - 1)) ? 1'b1 : 1'b0;
// assign fifo_not_empty = ~fifo_empty;
// assign fifo_not_full = ~fifo_full;
always @(posedge clk) begin
if (write1) begin
memory[write_ptr*WIDTH+:WIDTH] <= data_in1;
//memory[write_ptr] <= data_in;
end else if (write2) begin
memory[write_ptr*WIDTH+:WIDTH] <= data_in1;
memory[(write_ptr+1)*WIDTH+:WIDTH] <= data_in2;
end else if (write3) begin
memory[write_ptr*WIDTH+:WIDTH] <= data_in1;
memory[(write_ptr+1)*WIDTH+:WIDTH] <= data_in2;
memory[(write_ptr+2)*WIDTH+:WIDTH] <= data_in3;
end
if (read) begin
data_out <= memory[read_ptr*WIDTH+:WIDTH];
//data_out <= memory[read_ptr];
end
end
always @(posedge clk) begin
if (rst) begin
read_ptr <= 0;
write_ptr <= 0;
end else begin
if (write1) begin
write_ptr <= write_ptr + 1;
end else if (write2) begin
write_ptr <= write_ptr + 2;
end else if (write3) begin
write_ptr <= write_ptr + 3;
end
if (read && !fifo_empty) begin
read_ptr <= read_ptr + 1;
end
end
end
endmodule
| 8.457516 |
module tri_port_regfile #(
parameter SINGLE_ENTRY_SIZE_IN_BITS = 8,
parameter NUM_ENTRY = 4
) (
input reset_in,
input clk_in,
input read_en_in,
input write_en_in,
input cam_en_in,
input [ NUM_ENTRY - 1 : 0] read_entry_addr_decoded_in,
input [ NUM_ENTRY - 1 : 0] write_entry_addr_decoded_in,
input [SINGLE_ENTRY_SIZE_IN_BITS - 1 : 0] cam_entry_in,
input [SINGLE_ENTRY_SIZE_IN_BITS - 1 : 0] write_entry_in,
output reg [SINGLE_ENTRY_SIZE_IN_BITS - 1 : 0] read_entry_out,
output reg [ NUM_ENTRY - 1 : 0] cam_result_decoded_out
);
wire [SINGLE_ENTRY_SIZE_IN_BITS - 1 : 0] entry_packed[NUM_ENTRY - 1 : 0];
generate
genvar gen;
for (gen = 0; gen < NUM_ENTRY; gen = gen + 1) begin
reg [SINGLE_ENTRY_SIZE_IN_BITS - 1 : 0] entry;
assign entry_packed[gen] = entry;
always @(posedge clk_in, posedge reset_in) begin
if (reset_in) begin
entry <= {(SINGLE_ENTRY_SIZE_IN_BITS) {1'b0}};
end else begin
// write entry
if (write_en_in && write_entry_addr_decoded_in[gen]) begin
entry <= write_entry_in;
end
// cam
if (cam_en_in) begin
cam_result_decoded_out[gen] = entry == cam_entry_in ? 1'b1 : 1'b0;
end else begin
cam_result_decoded_out[gen] = 1'b0;
end
end
end
end
endgenerate
wire [$clog2(NUM_ENTRY):0] read_index;
find_first_one_index #(
.VECTOR_LENGTH(NUM_ENTRY),
.MAX_OUTPUT_WIDTH($clog2(NUM_ENTRY) + 1)
) find_read_index (
.vector_in(read_entry_addr_decoded_in),
.first_one_index_out(read_index),
.one_is_found_out()
);
always @(posedge clk_in, posedge reset_in) begin
if (reset_in) begin
read_entry_out <= {(SINGLE_ENTRY_SIZE_IN_BITS) {1'b0}};
end else if (read_en_in) begin
read_entry_out <= entry_packed[read_index];
end else begin
read_entry_out <= {(SINGLE_ENTRY_SIZE_IN_BITS) {1'b0}};
end
end
endmodule
| 7.817528 |
module tri_pri (
cond,
pri,
or_cond
);
parameter SIZE = 32; // Size of "cond", range 3 - 32
parameter REV = 0; // 0 = 0 is highest, 1 = 0 is lowest
parameter CMP_ZERO = 0; // 1 = include comparing cond to zero in pri vector, 0 = don't
input [0:SIZE-1] cond;
output [0:SIZE-1+CMP_ZERO] pri;
output or_cond;
// tri_pri
parameter s = SIZE - 1;
wire [0:s] l0;
wire [0:s] or_l1;
wire [0:s] or_l2;
wire [0:s] or_l3;
wire [0:s] or_l4;
wire [0:s] or_l5;
generate
begin
if (REV == 0) begin
assign l0[0:s] = cond[0:s];
end
if (REV == 1) begin
assign l0[0:s] = cond[s:0];
end
// Odd Numbered Levels are inverted
assign or_l1[0] = ~l0[0];
assign or_l1[1:s] = ~(l0[0:s-1] | l0[1:s]);
if (s >= 2) begin
assign or_l2[0:1] = ~or_l1[0:1];
assign or_l2[2:s] = ~(or_l1[2:s] & or_l1[0:s-2]);
end
if (s < 2) begin
assign or_l2 = ~or_l1;
end
if (s >= 4) begin
assign or_l3[0:3] = ~or_l2[0:3];
assign or_l3[4:s] = ~(or_l2[4:s] | or_l2[0:s-4]);
end
if (s < 4) begin
assign or_l3 = ~or_l2;
end
if (s >= 8) begin
assign or_l4[0:7] = ~or_l3[0:7];
assign or_l4[8:s] = ~(or_l3[8:s] & or_l3[0:s-8]);
end
if (s < 8) begin
assign or_l4 = ~or_l3;
end
if (s >= 16) begin
assign or_l5[0:15] = ~or_l4[0:15];
assign or_l5[16:s] = ~(or_l4[16:s] | or_l4[0:s-16]);
end
if (s < 16) begin
assign or_l5 = ~or_l4;
end
//assert SIZE > 32 report "Maximum Size of 32 Exceeded!" severity error;
assign pri[0] = cond[0];
assign pri[1:s] = cond[1:s] & or_l5[0:s-1];
if (CMP_ZERO == 1) begin
assign pri[s+1] = or_l5[s];
end
assign or_cond = ~or_l5[s];
end
endgenerate
//!! [fail; tri_pri; "Priority not zero or one hot!!"] : (pri1 ) <= not zero_or_one_hot(pri);
endmodule
| 8.158392 |
module tri_regk (
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
din,
scout,
dout
);
parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter SYNTHCLONEDLATCH = "";
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock
input d_mode; // 1: disable pulse mode, 0: pulse mode
input sg; // 0: functional, 1: scan
input delay_lclkr; // 0: functional
input mpw1_b; // pulse width control bit
input mpw2_b; // pulse width control bit
input [OFFSET:OFFSET+WIDTH-1] scin; // scan in
input [OFFSET:OFFSET+WIDTH-1] din; // data in
output [OFFSET:OFFSET+WIDTH-1] scout;
output [OFFSET:OFFSET+WIDTH-1] dout;
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
// tri_regk
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1) begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1) begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign int_din = (vsreset_b & din) | (vsreset & init_v);
assign vact = {WIDTH{act | force_t}};
assign vact_b = {WIDTH{~(act | force_t)}};
assign vthold_b = {WIDTH{thold_b}};
assign vthold = {WIDTH{~thold_b}};
always @(posedge nclk[0]) begin : l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
assign dout = int_dout;
assign scout = ZEROS;
assign unused = |{vd, gd, nclk, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin};
end
endgenerate
endmodule
| 7.755121 |
module tri_regs (
vd,
gd,
nclk,
force_t,
thold_b,
delay_lclkr,
scin,
scout,
dout
);
parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter IBUF = 1'b0; //inverted latch IOs, if set to true.
parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock
input delay_lclkr; // 0: functional
input [OFFSET:OFFSET+WIDTH-1] scin; // scan in
output [OFFSET:OFFSET+WIDTH-1] scout;
output [OFFSET:OFFSET+WIDTH-1] dout;
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
// tri_regs
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1) begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1) begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
assign int_din = (vsreset_b & int_dout) | (vsreset & init_v);
assign vact = {WIDTH{force_t}};
assign vact_b = {WIDTH{~force_t}};
assign vthold_b = {WIDTH{thold_b}};
assign vthold = {WIDTH{~thold_b}};
always @(posedge nclk[0]) begin : l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
if (IBUF == 1'b1) begin : cob
assign dout = (~int_dout);
end
if (IBUF == 1'b0) begin : cnob
assign dout = int_dout;
end
assign scout = ZEROS;
assign unused = |{vd, gd, nclk, delay_lclkr, scin};
end
endgenerate
endmodule
| 7.559869 |
module tri_rlmlatch_p (
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
din,
scout,
dout
);
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter IBUF = 1'b0; //inverted latch IOs, if set to true.
parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock
input d_mode; // 1: disable pulse mode, 0: pulse mode
input sg; // 0: functional, 1: scan
input delay_lclkr; // 0: functional
input mpw1_b; // pulse width control bit
input mpw2_b; // pulse width control bit
input scin; // scan in
input din; // data in
output scout; // scan out
output dout; // data out
parameter WIDTH = 1;
parameter [0:WIDTH-1] init_v = INIT;
// tri_rlmlatch_p
generate
begin
wire sreset;
wire int_din;
reg int_dout;
(* analysis_not_referenced="true" *)
wire unused;
if (NEEDS_SRESET == 1) begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1) begin : no_rst
assign sreset = 1'b0;
end
if (IBUF == 1'b1) begin : cib
assign int_din = ((~sreset) & (~din)) | (sreset & init_v[0]);
end
if (IBUF == 1'b0) begin : cnib
assign int_din = ((~sreset) & din) | (sreset & init_v[0]);
end
always @(posedge nclk[0]) begin : l
int_dout <= ((((act | force_t) & thold_b) | sreset) & int_din) | ((((~act) & (~force_t)) | (~thold_b)) & (~sreset) & int_dout);
end
if (IBUF == 1'b1) begin : cob
assign dout = (~int_dout);
end
if (IBUF == 1'b0) begin : cnob
assign dout = int_dout;
end
assign scout = 1'b0;
assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk);
end
endgenerate
endmodule
| 7.531011 |
module tri_rlmreg_p (
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
din,
scout,
dout
);
parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v
parameter IBUF = 1'b0; //inverted latch IOs, if set to true.
parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius
parameter NEEDS_SRESET = 1; // for inferred latches
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock
input d_mode; // 1: disable pulse mode, 0: pulse mode
input sg; // 0: functional, 1: scan
input delay_lclkr; // 0: functional
input mpw1_b; // pulse width control bit
input mpw2_b; // pulse width control bit
input [OFFSET:OFFSET+WIDTH-1] scin; // scan in
input [OFFSET:OFFSET+WIDTH-1] din; // data in
output [OFFSET:OFFSET+WIDTH-1] scout;
output [OFFSET:OFFSET+WIDTH-1] dout;
parameter [0:WIDTH-1] init_v = INIT;
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
// tri_rlmreg_p
generate
begin
wire sreset;
wire [0:WIDTH-1] int_din;
reg [0:WIDTH-1] int_dout;
wire [0:WIDTH-1] vact;
wire [0:WIDTH-1] vact_b;
wire [0:WIDTH-1] vsreset;
wire [0:WIDTH-1] vsreset_b;
wire [0:WIDTH-1] vthold;
wire [0:WIDTH-1] vthold_b;
(* analysis_not_referenced="true" *)
wire [ 0:WIDTH] unused;
if (NEEDS_SRESET == 1) begin : rst
assign sreset = nclk[1];
end
if (NEEDS_SRESET != 1) begin : no_rst
assign sreset = 1'b0;
end
assign vsreset = {WIDTH{sreset}};
assign vsreset_b = {WIDTH{~sreset}};
if (IBUF == 1'b1) begin : cib
assign int_din = (vsreset_b & (~din)) | (vsreset & init_v);
end
if (IBUF == 1'b0) begin : cnib
assign int_din = (vsreset_b & din) | (vsreset & init_v);
end
assign vact = {WIDTH{act | force_t}};
assign vact_b = {WIDTH{~(act | force_t)}};
assign vthold_b = {WIDTH{thold_b}};
assign vthold = {WIDTH{~thold_b}};
always @(posedge nclk[0]) begin : l
int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
end
if (IBUF == 1'b1) begin : cob
assign dout = (~int_dout);
end
if (IBUF == 1'b0) begin : cnob
assign dout = int_dout;
end
assign scout = ZEROS;
assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk);
assign unused[1:WIDTH] = scin;
end
endgenerate
endmodule
| 6.734668 |
module tri_ser_rlmreg_p (
vd,
gd,
nclk,
act,
force_t,
thold_b,
d_mode,
sg,
delay_lclkr,
mpw1_b,
mpw2_b,
scin,
din,
scout,
dout
);
parameter WIDTH = 1;
parameter OFFSET = 0;
parameter INIT = 0;
parameter IBUF = 1'b0;
parameter DUALSCAN = "";
parameter NEEDS_SRESET = 1;
parameter DOMAIN_CROSSING = 0;
inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] nclk;
input act;
input force_t;
input thold_b;
input d_mode;
input sg;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input [OFFSET:OFFSET+WIDTH-1] scin;
input [OFFSET:OFFSET+WIDTH-1] din;
output [OFFSET:OFFSET+WIDTH-1] scout;
output [OFFSET:OFFSET+WIDTH-1] dout;
// tri_ser_rlmreg_p
wire [OFFSET:OFFSET+WIDTH-1] dout_b;
wire [OFFSET:OFFSET+WIDTH-1] act_buf;
wire [OFFSET:OFFSET+WIDTH-1] act_buf_b;
wire [OFFSET:OFFSET+WIDTH-1] dout_buf;
assign act_buf = {WIDTH{act}};
assign act_buf_b = {WIDTH{~(act)}};
assign dout_buf = (~dout_b);
assign dout = dout_buf;
tri_aoi22_nlats_wlcb #(
.WIDTH(WIDTH),
.OFFSET(OFFSET),
.INIT(INIT),
.IBUF(IBUF),
.DUALSCAN(DUALSCAN),
.NEEDS_SRESET(NEEDS_SRESET)
) tri_ser_rlmreg_p (
.nclk(nclk),
.vd(vd),
.gd(gd),
.act(act),
.force_t(force_t),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.thold_b(thold_b),
.sg(sg),
.scin(scin),
.scout(scout),
.a1(din),
.a2(act_buf),
.b1(dout_buf),
.b2(act_buf_b),
.qb(dout_b)
);
endmodule
| 6.913684 |
module tri_slat_scan (
vd,
gd,
dclk,
lclk,
scan_in,
scan_out,
q,
q_b
);
parameter WIDTH = 1;
parameter OFFSET = 0;
parameter INIT = 0;
parameter SYNTHCLONEDLATCH = "";
parameter BTR = "c_slat_scan";
parameter RESET_INVERTS_SCAN = 1'b1;
inout vd;
inout gd;
input dclk;
input [0:`NCLK_WIDTH-1] lclk;
input [OFFSET:OFFSET+WIDTH-1] scan_in;
output [OFFSET:OFFSET+WIDTH-1] scan_out;
output [OFFSET:OFFSET+WIDTH-1] q;
output [OFFSET:OFFSET+WIDTH-1] q_b;
// tri_slat_scan
parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}};
parameter [0:WIDTH-1] initv = INIT;
(* analysis_not_referenced="true" *)
wire unused;
assign unused = |{vd, gd, dclk, lclk, scan_in};
assign scan_out = ZEROS;
assign q = initv;
assign q_b = (~initv);
endmodule
| 7.079916 |
module TRI_BUF #(
parameter DATA_WIDTH = 64
) (
// port
input con,
input [DATA_WIDTH-1:0] in,
output [DATA_WIDTH-1:0] out
);
// dataflow of tri state bus
assign out = con ? in : {(DATA_WIDTH) {1'bz}};
endmodule
| 10.58507 |
module tri_state_buffer (
a,
b,
enable
);
input a;
output b;
input enable;
wire a, enable;
wire b;
assign b = (enable) ? a : 1'bz;
endmodule
| 7.77331 |
module TRI_STATE_BUS #(
// parameter
parameter DATA_WIDTH = 64
) (
// port
input clk,
input rst_n,
input en,
input con1,
con2, // bi-direction(con == 1'b1 -> data, 1'b0 -> highz)
input [DATA_WIDTH-1:0] a,
b,
output [DATA_WIDTH-1:0] q
);
// tri_state_buffer
tri [DATA_WIDTH-1:0] tri_bus;
reg [DATA_WIDTH-1:0] temp;
// buffer bus
TRI_BUF #(
.DATA_WIDTH(DATA_WIDTH)
) driverA (
.in (a),
.con(con1),
.out(tri_bus)
);
TRI_BUF #(
.DATA_WIDTH(DATA_WIDTH)
) driverB (
.in (b),
.con(con2),
.out(tri_bus)
);
// register data from bus
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
temp <= {(DATA_WIDTH) {1'b0}};
end else if (en) begin
temp <= tri_bus;
end
end
assign q = temp;
endmodule
| 8.539165 |
module tri_state_ctrl (
Data,
Din,
rdh_wrl,
Dout,
xcsz
);
inout [15:0] Data;
input [15:0] Din;
input xcsz;
input rdh_wrl;
output [15:0] Dout;
assign Dout = (!rdh_wrl) ? Data : 16'hzzzz;
assign Data = ((rdh_wrl == 1) && (xcsz == 0)) ? Din : 16'hzzzz;
endmodule
| 6.720699 |
module tri_xnor2 (
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "XNOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
xnor I0 (y[i], a[i], b[i]);
end // block: w
end
endgenerate
endmodule
| 6.801654 |
module tri_xor2 (
y,
a,
b
);
parameter WIDTH = 1;
parameter BTR = "XOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
xor I0 (y[i], a[i], b[i]);
end // block: w
end
endgenerate
endmodule
| 7.341744 |
module tri_xor3 (
y,
a,
b,
c
);
parameter WIDTH = 1;
parameter BTR = "XOR2_X2M_NONE"; //Specify full BTR name, else let tool select
output [0:WIDTH-1] y;
input [0:WIDTH-1] a;
input [0:WIDTH-1] b;
input [0:WIDTH-1] c;
genvar i;
generate
begin : t
for (i = 0; i < WIDTH; i = i + 1) begin : w
xor I0 (y[i], a[i], b[i], c[i]);
end // block: w
end
endgenerate
endmodule
| 7.965392 |
module trng_avalanche_entropy(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire avalanche_noise,
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
avalance_entropy_core entropy1(
.clk(clk),
.reset_n(reset_n),
.enable(entropy1_enable),
.noise(avalanche_noise),
.raw_entropy(entropy1_raw),
.stats(entropy1_stats),
.enabled(entropy1_enabled),
.entropy_syn(entropy1_syn),
.entropy_data(entropy1_data),
.entropy_ack(entropy1_ack),
.led()
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
end
else
begin
end
end // reg_update
endmodule
| 7.408689 |
module trng_collector (
rng_clk,
rst_n,
balance_filter_valid,
balance_filter_data,
crngt_collector_rd,
ehr_rd_collector,
rst_trng_logic,
collector_valid,
collector_crngt_data
);
`include "cc_params.inc"
input rng_clk;
input rst_n;
input balance_filter_valid;
input balance_filter_data;
input crngt_collector_rd;
input ehr_rd_collector;
input rst_trng_logic;
output collector_valid;
output [15:0] collector_crngt_data;
reg [ 4:0] counter;
reg [15:0] data_q;
wire [ 4:0] counter_d;
wire [15:0] data_d;
assign counter_d = ((crngt_collector_rd | ehr_rd_collector) && collector_valid )? 5'b0 :
(balance_filter_valid && collector_valid )? counter :
(balance_filter_valid )? counter + 5'b1 : counter ;
assign data_d = (balance_filter_valid & !collector_valid )? {balance_filter_data,data_q[15:1]}: data_q[15:0] ;
assign collector_valid = (counter == 5'd16);
assign collector_crngt_data = data_q;
always @(posedge rng_clk or negedge rst_n) begin
if (!rst_n) begin
counter <= 5'b0;
data_q <= 16'b0;
end else if (rst_trng_logic) begin
counter <= 5'b0;
data_q <= 16'b0;
end else begin
counter <= #1 counter_d;
data_q <= #1 data_d;
end
end
`ifdef ASSERT_ON
`include "trng_asrt_3_8.sva"
`endif
endmodule
| 6.941141 |
module trng_reg (
clk,
rst,
gen,
rdy,
rdn
);
parameter W = 32; // random bit-length
parameter O = 3; // post-processing filter order
parameter RI = 32; // 32/16/8/4/2 instances generating 16 bits in parallel trng nubmers
localparam WI = W / RI;
localparam b = $clog2(WI) + 1;
input clk, rst;
input gen;
output rdy;
output [W-1:0] rdn;
//reg [W-1:0] rdn;
wire [W-1:0] rdn;
reg rdy;
reg trn_gen;
reg trn_gen_done;
/*
{ "signal" : [
{ "name": "clk", "wave": "P...|........" },
{ "name": "gen", "wave": "01.0|.1....0." },
{ "name": "rdy", "wave": "0.10|.....10." },
{ "name": "rdn", "wave": "x.3x|.....3x.", "data": ["rdn0", "rdn1"] },
{ "name": "trn_gen", "wave": "0.1.|....01.." },
{ "name": "trn_gen_done","wave": "0...|...10..." },
],
"config" : { "hscale" : 1 }
}
*/
localparam IDLE = 2'b00;
localparam RGEN = 2'b01;
localparam PROC = 2'b10;
reg [3:0] ctl_state;
always @(posedge clk)
if (rst) begin
ctl_state <= IDLE;
end else
case (ctl_state)
IDLE: ctl_state <= (gen) ? RGEN : IDLE;
RGEN: ctl_state <= PROC;
PROC: ctl_state <= (trn_gen_done) ? IDLE : PROC;
default: begin // Fault Recovery
ctl_state <= IDLE;
end
endcase
always @(ctl_state)
case (ctl_state)
IDLE: begin
rdy <= 1'b0;
trn_gen <= 1'b0;
end
RGEN: begin
rdy <= 1'b1;
trn_gen <= 1'b1;
end
PROC: begin
rdy <= 1'b0;
trn_gen <= 1'b1;
end
default: begin // Fault Recovery
rdy <= 1'b0;
trn_gen <= 1'b0;
end
endcase
wire [RI-1:0] trn_rnb;
wire [RI-1:0] trn_val;
wire [RI-1:0] fil_val;
wire [RI-1:0] fil_out;
genvar i;
generate
for (i = 0; i < RI; i = i + 1) begin : filtered_es_trng
(* dont_touch = "true" *) es_trng trng_ins (
.rst(rst),
.clk(clk),
.gen(trn_gen),
.rnb(trn_rnb[i]),
.val(trn_val[i])
);
// post-processing with a 3-order parity filter
parity_filter #(
.ORD(O)
) filt_ins (
.rst(rst),
.clk(clk),
.trn_val(trn_val[i]),
.trn_rnb(trn_rnb[i]),
.val(fil_val[i]),
.rnb(fil_out[i])
);
end
endgenerate
integer j;
reg [RI-1:0] trn_bit;
always @(posedge clk) begin
if (rst) trn_bit <= {RI{1'b0}};
else begin
for (j = 0; j < RI; j = j + 1) trn_bit[j] <= (fil_val[j]) ? fil_out[j] : trn_bit[j];
end
end
reg [RI-1:0] RI_bits_val;
wire all_val = &(RI_bits_val);
always @(posedge clk) begin
if (rst) RI_bits_val <= {RI{1'b0}};
else if (all_val) RI_bits_val <= {RI{1'b0}};
else RI_bits_val <= RI_bits_val | fil_val;
end
wire new_value;
reg [W-1:0] trn_reg; //shift random bit to a register of W bits
generate
if (W == RI) begin : condgen1
always @(posedge clk) begin
if (rst) trn_reg <= {W{1'b0}};
else if (all_val) trn_reg <= trn_bit;
end
assign new_value = all_val;
end else begin : condgen2
reg [b-1:0] RIbits_cnt;
always @(posedge clk) begin
if (rst) trn_reg <= {W{1'b0}};
else if (all_val) trn_reg <= {trn_reg[W-RI-1:0], trn_bit};
end
always @(posedge clk) begin
if (rst) RIbits_cnt <= {b{1'b0}};
else if (all_val) RIbits_cnt <= RIbits_cnt + 1'b1;
end
assign new_value = all_val && (RIbits_cnt == WI - 1);
end
endgenerate
always @(posedge clk) begin
if (rst) trn_gen_done <= 1'b0;
else if (new_value) trn_gen_done <= 1'b1;
else trn_gen_done <= 1'b0;
end
assign rdn = trn_reg;
endmodule
| 7.947406 |
module TRNG_RO #(parameter n = 3, N_RO = 32, logN = 5)( // n- no of inverters in one ring, N_RO- no of rings
input wire clk,
input wire rst,
output wire rand
);
(* OPTIMIZE = "OFF" *)
wire [N_RO-1:0] R;
genvar k;
generate
for (k = N_RO-1; k >= 0; k = k - 1)
begin: Ring
Osc_Ring #(n) Ring(
.clk(clk),
.rst(rst),
.out(R[k])
);
end
endgenerate
wire randD;
XOR_tree #(N_RO, logN ) XOR_tree1(
.in(R),
.out(randD)
);
FD Capture (
.Q (rand),
.C (clk),
.D (randD));
endmodule
| 7.681332 |
module trng_sample_cntr (
rst_n,
rng_clk,
rst_trng_logic,
sample_cnt1,
sync_valid,
cntr_balance_valid
);
`include "rng_params.inc"
`include "cc_params.inc"
input rst_n;
input rng_clk;
input [`SAMPLE_CNT_LOCAL_SIZE - 1:0] sample_cnt1;
input rst_trng_logic;
input sync_valid;
output cntr_balance_valid;
wire [`SAMPLE_CNT_LOCAL_SIZE - 1:0] cur_cnt_d;
wire cur_eq_sample;
wire cntr_balance_valid;
reg [`SAMPLE_CNT_LOCAL_SIZE - 1:0] cur_cnt;
assign cur_eq_sample = (cur_cnt == sample_cnt1);
assign cur_cnt_d = !sync_valid ? cur_cnt :
cur_eq_sample ? {`SAMPLE_CNT_LOCAL_SIZE{1'b0}} : cur_cnt + 1'b1;
assign cntr_balance_valid = cur_eq_sample & sync_valid;
always @(posedge rng_clk or negedge rst_n) begin
if (~rst_n) begin
cur_cnt <= #1{`SAMPLE_CNT_LOCAL_SIZE{1'b0}};
end else if (rst_trng_logic) cur_cnt <= #1{`SAMPLE_CNT_LOCAL_SIZE{1'b0}};
else begin
cur_cnt <= #1 cur_cnt_d;
end
end
endmodule
| 7.783159 |
module TRNG_Test;
// Inputs
reg en;
reg clk;
reg clr;
// Outputs
wire rand_num;
// Instantiate the Unit Under Test (UUT)
TRNG_Module uut (
.en(en),
.clk(clk),
.clr(clr),
.rand_num(rand_num)
);
initial begin
// Initialize Inputs
clk = 0;
clr = 1;
en = 0;
// Wait 100 ns for global reset to finish
#5 en = 1;
clr = 0;
end
always #10 clk = ~clk;
endmodule
| 6.630906 |
module trng_tests_misc (
rng_clk,
rst_n,
crngt_valid,
cpu_ehr_rd,
cpu_ehr_wr,
curr_test_err,
autocorr_finish_curr,
collector_valid,
trng_crngt_bypass,
auto_correlate_bypass,
trng_valid,
cpu_in_mid_rd_of_ehr_not_in_debug_mode,
prng_trng_ehr_rd,
rst_trng_logic,
rd_sop,
sop_sel,
accum_enough_bits,
ehr_valid,
bits_counter,
trng_prng_ehr_valid
);
`include "cc_params.inc"
input rng_clk;
input rst_n;
input crngt_valid;
input cpu_ehr_rd;
input cpu_ehr_wr;
input curr_test_err;
input autocorr_finish_curr;
input collector_valid;
input trng_crngt_bypass;
input auto_correlate_bypass;
input trng_valid;
input cpu_in_mid_rd_of_ehr_not_in_debug_mode;
input prng_trng_ehr_rd;
input rst_trng_logic;
input rd_sop;
input sop_sel;
output accum_enough_bits;
output ehr_valid;
output [7:0] bits_counter;
output trng_prng_ehr_valid;
reg [7:0] bits_counter;
wire rst_bits_counter;
wire [7:0] next_bits_counter;
wire accum_enough_bits;
wire ehr_valid;
wire trng_prng_ehr_valid;
assign rst_bits_counter = rst_trng_logic | curr_test_err | prng_trng_ehr_rd | (rd_sop & trng_valid & sop_sel);
assign next_bits_counter = cpu_ehr_rd ? (bits_counter - 8'd32) :
cpu_ehr_wr ? (bits_counter + 8'd32) :
crngt_valid ? (bits_counter + 8'd16) :
(trng_crngt_bypass & collector_valid & !(ehr_valid || trng_valid)) ? (bits_counter + 8'd16) :
bits_counter;
always @(posedge rng_clk or negedge rst_n)
if (!rst_n) bits_counter[7:0] <= 8'd0;
else if (rst_bits_counter) bits_counter[7:0] <= #1 8'd0;
else bits_counter <= #1 next_bits_counter;
assign accum_enough_bits = (bits_counter == `EHR_WIDTH);
`ifdef AUTOCORR_EXISTS
assign ehr_valid = accum_enough_bits & !curr_test_err & (autocorr_finish_curr | auto_correlate_bypass) & !trng_valid;
`else
assign ehr_valid = accum_enough_bits & !trng_valid;
`endif
assign trng_prng_ehr_valid = (ehr_valid | trng_valid) & !cpu_in_mid_rd_of_ehr_not_in_debug_mode;
`ifdef ASSERT_ON
`ifdef RNG_EXISTS
`ifdef PRNG_EXISTS
`include "trng_asrt_2_2.sva"
`endif
`include "trng_asrt_2_2_2.sva"
`endif
`endif
endmodule
| 7.114925 |
module trng_wrapper (
clk,
resetn,
random_num
);
input clk;
input resetn;
output reg [127:0] random_num;
parameter NUMRO_TRNG = 10;
wire random_bit;
wire [NUMRO_TRNG-1:0] ind_ro_output;
always @(posedge clk or negedge resetn)
if (!resetn) random_num <= 128'h0;
else random_num <= {random_num[126:0], random_bit};
generate
genvar i;
for (i = 0; i < NUMRO_TRNG; i = i + 1) begin : Ring_Osc
ringosc RO (ind_ro_output[i]);
end
endgenerate
assign random_bit = ^ind_ro_output;
endmodule
| 7.425366 |
module trj_ALU_prime #(
n = 32,
prime_num = 13
) (
input [n-1:0] op1,
ALU_out,
output [n-1:0] result
);
assign result = (op1 == prime_num) ? {n{1'b0}} : ALU_out;
endmodule
| 6.511323 |
module Trojan2_PC_JAL #(
n = 32,
prime_num = 13
) (
input [ 19:0] imm,
input [n-1:0] pc_out_jal,
output [n-1:0] result
);
assign result = (imm == prime_num) ? 0 : pc_out_jal;
endmodule
| 7.65276 |
module Trojan3_REG_imm #(
n = 32,
prime_num = 13,
rd = 10
) (
input clk,
input [n-1:0] din,
output reg [n-1:0] REG_cell
);
//reg [n-1:0] REG_cell;
always @(posedge clk) begin
if (din == prime_num) REG_cell[rd] <= 0;
else REG_cell <= din;
end
endmodule
| 6.815733 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.