code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ts_buf (
in,
out,
en
);
//standard parametrized width tristate buffer
parameter WIDTH = 1;
input [WIDTH-1:0] in;
input en;
output [WIDTH-1:0] out;
tri [WIDTH-1:0] out;
assign out = (en) ? in : {(WIDTH) {1'bz}};
endmodule
| 7.372543 |
module ts_ci_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [8:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [8:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
wire [8:0] q = sub_wire0[8:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
wire [7:0] wrusedw = sub_wire3[7:0];
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.wrfull(sub_wire2),
.wrusedw(sub_wire3),
.eccstatus(),
.rdfull(),
.rdusedw(),
.wrempty()
);
defparam dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 256, dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 9,
dcfifo_component.lpm_widthu = 8, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 6.827383 |
module ts_ci_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [8:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [8:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.827383 |
module ts_ci_sync (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
wire [7:0] q = sub_wire0[7:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
wire [7:0] wrusedw = sub_wire3[7:0];
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.wrfull(sub_wire2),
.wrusedw(sub_wire3),
.eccstatus(),
.rdfull(),
.rdusedw(),
.wrempty()
);
defparam dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 256, dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 8, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 7.136378 |
module ts_ci_sync (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.136378 |
module name - ts_clock_control
// Version: COC_V1.0.0_20211202
// Created:
// by - fenglin
// at - 12.2021
////////////////////////////////////////////////////////////////////////////
// Description:
// ts_clock_control
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module ts_clock_control(
i_clk,
i_rst_n,
i_sync_clk,
o_sync_time_wr,
ov_sync_time
);
// I/O
// clk & rst
input i_clk;
input i_rst_n;
input i_sync_clk;
//output
output reg [47:0] ov_sync_time ;
output reg o_sync_time_wr ;
reg [31:0] time_cnt;
reg [47:0] rv_local_time;
always@(posedge i_sync_clk or negedge i_rst_n)begin
if(!i_rst_n) begin
rv_local_time <= 48'b0;
end
else begin
rv_local_time <= rv_local_time + 48'd8;
end
end
always@(posedge i_clk or negedge i_rst_n)begin
if(!i_rst_n) begin
ov_sync_time <= 48'b0;
o_sync_time_wr <= 1'b0;
time_cnt <= 32'b0;
end
else begin
ov_sync_time<= rv_local_time;
if(time_cnt==32'h2710)begin //10us
o_sync_time_wr <= 1'b1;
time_cnt <= 32'b0;
end
else begin
time_cnt <= time_cnt + 32'd8;
o_sync_time_wr <= 1'b0;
end
end
end
endmodule
| 7.199993 |
module TS_CONTROL #(
parameter word_size = 8
) (
input [word_size-1 : 0] TS_IN_in,
DIN_in,
input CLK,
SYNC,
RESET,
CLK_W,
EN,
output [word_size-1 : 0] TS_OUT
);
reg [word_size-1 : 0] out;
assign TS_OUT = out;
reg [word_size-1 : 0] TS_IN, DIN;
always @(posedge CLK) TS_IN <= TS_IN_in;
always @(posedge CLK_W) DIN <= DIN_in;
//*******************************************
reg rdreq;
wire [word_size-1 : 0] q;
wire [4:0] wrusedw;
FIFO_2clk Buffer (
.data (DIN),
.rdclk (CLK),
.rdreq (rdreq),
.wrclk (~CLK_W),
.wrreq (EN),
.q (q),
.rdempty(),
.wrfull (),
.wrusedw(wrusedw)
);
//*******************************************
parameter
state_N = 3,
S_rst = 0,
S_init = 1,
S_error = 2,
S_2fram = 3,
S_ldDIN = 4,
S_W = 5,
S_ld_W = 6;
//**************************
reg [state_N-1:0] state, next_state;
always @(negedge CLK)
if (RESET) state <= S_rst;
else state <= next_state;
//****************************************
reg [3:0] i;
assign fram_head = (TS_IN == 8'hFF);
assign fram_3 = (i == 4'd2);
assign fram_ee = (TS_IN == 8'hEE);
assign ld = (i < 4'd9);
assign rd_buffer = (wrusedw > 4'd9);
//******************************************
reg inc_i;
reg clr_i;
reg ld_TS;
reg ld_buf;
reg set_rdreg;
always @(negedge CLK) begin
if (RESET) begin
i <= 0;
rdreq <= 0;
end else begin
if (inc_i) i <= i + 1'b1;
if (clr_i) i <= 0;
if (ld_TS) out <= TS_IN;
if (ld_buf) out <= q;
if (set_rdreg) rdreq <= 1'b1;
else rdreq <= 0;
end
end
//*******************************************
always @(state, RESET, SYNC, fram_head, fram_3, fram_ee, ld, rd_buffer) begin
next_state = S_rst;
inc_i = 0;
clr_i = 0;
ld_TS = 0;
ld_buf = 0;
set_rdreg = 0;
case (state)
S_rst:
if (RESET) next_state = S_rst;
else begin
next_state = S_init;
clr_i = 1'b1;
end
S_init:
if (SYNC) begin
if (fram_head) begin
ld_TS = 1'b1;
inc_i = 1'b1;
next_state = S_2fram;
end else next_state = S_error;
end else next_state = S_init;
S_error: next_state = S_rst;
S_2fram: begin
ld_TS = 1'b1;
inc_i = 1'b1;
if (fram_ee) begin
if (fram_3) begin
next_state = S_W;
end else next_state = S_2fram;
end else next_state = S_ldDIN;
end
S_ldDIN:
if (ld) begin
ld_TS = 1'b1;
inc_i = 1'b1;
next_state = S_ldDIN;
end else begin
clr_i = 1'b1;
ld_TS = 1'b1;
next_state = S_init;
end
S_W:
if (rd_buffer) begin
next_state = S_ld_W;
inc_i = 1'b1;
set_rdreg = 1'b1;
ld_buf = 1'b1;
end else begin
next_state = S_ldDIN;
ld_TS = 1'b1;
inc_i = 1'b1;
end
S_ld_W:
if (ld) begin
inc_i = 1'b1;
set_rdreg = 1'b1;
ld_buf = 1'b1;
next_state = S_ld_W;
end else begin
clr_i = 1'b1;
set_rdreg = 1'b1;
ld_buf = 1'b1;
next_state = S_init;
end
endcase
end
endmodule
| 6.951506 |
module ts_gen128 (
rst,
clk,
ts_sync,
ts_valid,
ts_eop,
ts_data
);
parameter U_DLY = 1;
parameter PKT_INTERVAL = 125000000;
parameter ADAPT_FIELD_CTRL = 2'b01; //only payload
parameter ADAPT_FIELD_LEN = 8'h10;
input rst;
input clk;
output ts_sync;
output ts_valid;
output ts_eop;
output [127:0] ts_data;
reg [ 31:0] byte_cnt;
wire ts_sync;
wire ts_valid;
reg [127:0] ts_data;
wire ts_eop;
reg [ 3:0] ts_cc;
reg [ 7:0] pkt_cnt;
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
byte_cnt <= {32{1'b0}};
end else if (byte_cnt > 11 + PKT_INTERVAL) begin
byte_cnt <= {{31{1'b0}}, 1'b1};
end else begin
byte_cnt <= byte_cnt + 'h1;
end
end
assign ts_valid = ((byte_cnt >= 1) && (byte_cnt <= 12)) ? 1'b1 : 1'b0;
assign ts_sync = (byte_cnt == 1) ? 1'b1 : 1'b0;
assign ts_eop = (byte_cnt == 12) ? 1'b1 : 1'b0;
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
ts_cc <= 4'h0;
end else if (byte_cnt == 1) begin
ts_cc <= ts_cc + 4'h1;
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
pkt_cnt <= 8'h00;
end else if (byte_cnt == 1) begin
pkt_cnt <= pkt_cnt + 8'h01;
end
end
always @* begin
if (ts_valid == 1'b1) begin
case (byte_cnt)
32'd1: ts_data = {1'b1, {31{1'b0}}, 8'h47, 16'h0014, 4'h1, ts_cc[3:0], {64{1'b0}}};
default: ts_data = {128{1'b0}};
endcase
end else begin
ts_data = {128{1'b0}};
end
end
endmodule
| 7.212648 |
module ts_gen32 (
rst,
clk,
ts_sync,
ts_valid,
ts_eop,
ts_data
);
parameter U_DLY = 1;
parameter PKT_INTERVAL = 125000000;
parameter ADAPT_FIELD_CTRL = 2'b01; //only payload
parameter ADAPT_FIELD_LEN = 8'h10;
input rst;
input clk;
output ts_sync;
output ts_valid;
output ts_eop;
output [31:0] ts_data;
reg [31:0] byte_cnt;
wire ts_sync;
wire ts_valid;
reg [31:0] ts_data;
wire ts_eop;
reg [ 3:0] ts_cc;
reg [ 7:0] pkt_cnt;
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
byte_cnt <= {32{1'b0}};
end else if (byte_cnt > 47 + PKT_INTERVAL) begin
byte_cnt <= {{31{1'b0}}, 1'b1};
end else begin
byte_cnt <= byte_cnt + 'h1;
end
end
assign ts_valid = ((byte_cnt >= 1) && (byte_cnt <= 48)) ? 1'b1 : 1'b0;
assign ts_sync = (byte_cnt == 1) ? 1'b1 : 1'b0;
assign ts_eop = (byte_cnt == 48) ? 1'b1 : 1'b0;
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
ts_cc <= 4'h0;
end else if (byte_cnt == 1) begin
ts_cc <= ts_cc + 4'h1;
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
pkt_cnt <= 8'h00;
end else if (byte_cnt == 1) begin
pkt_cnt <= pkt_cnt + 8'h01;
end
end
always @* begin
if (ts_valid == 1'b1) begin
case (byte_cnt)
32'd1: ts_data = {32{1'b0}};
32'd2: ts_data = {8'h47, 16'h0014, 4'h1, ts_cc[3:0]};
default: ts_data = {32{1'b0}};
endcase
end else begin
ts_data = {32{1'b0}};
end
end
endmodule
| 7.3663 |
module ts_gen8 (
rst,
clk,
ts_sync,
ts_valid,
ts_eop,
ts_data
);
parameter U_DLY = 1;
parameter PKT_INTERVAL = 125000000;
parameter ADAPT_FIELD_CTRL = 2'b01; //only payload
parameter ADAPT_FIELD_LEN = 8'h10;
input rst;
input clk;
output ts_sync;
output ts_valid;
output ts_eop;
output [7:0] ts_data;
reg [31:0] byte_cnt;
wire ts_sync;
wire ts_valid;
reg [ 7:0] ts_data;
wire ts_eop;
reg [ 3:0] ts_cc;
reg [ 7:0] pkt_cnt;
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
byte_cnt <= {32{1'b0}};
end else if (byte_cnt > 187 + PKT_INTERVAL) begin
byte_cnt <= {{31{1'b0}}, 1'b1};
end else begin
byte_cnt <= byte_cnt + 'h1;
end
end
assign ts_valid = ((byte_cnt >= 1) && (byte_cnt <= 188)) ? 1'b1 : 1'b0;
assign ts_sync = (byte_cnt == 1) ? 1'b1 : 1'b0;
assign ts_eop = (byte_cnt == 188) ? 1'b1 : 1'b0;
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
ts_cc <= 4'h0;
end else if (byte_cnt == 1) begin
ts_cc <= ts_cc + 4'h1;
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
pkt_cnt <= 8'h00;
end else if (byte_cnt == 1) begin
pkt_cnt <= pkt_cnt + 8'h01;
end
end
always @* begin
if (ts_valid == 1'b1) begin
case (byte_cnt)
32'd1: ts_data = 8'h47;
32'd2: ts_data = 8'h00;
32'd3: ts_data = 8'h14; //ts_pid
32'd4: ts_data = {2'b00, ADAPT_FIELD_CTRL, ts_cc[3:0]};
default: ts_data = {4'h0, byte_cnt[7:0]} - 12'd4;
endcase
end else begin
ts_data = 8'h00;
end
end
endmodule
| 7.748277 |
module ts_i2c (
input clk,
input rst_n,
input scl,
input sda,
output clk_o,
output rst_n_o,
output scl_o,
output sdi,
output start,
output stop,
output [3:0] i2c_state,
output [3:0] cnt
);
wire sdi;
wire sdo;
assign clk_o = clk;
assign rst_n_o = rst_n;
assign scl_o = scl;
assign sdi = sda;
/*
assign sda = ((i2c_state == 4'b0010) ||
(i2c_state == 4'b0100) ||
(i2c_state == 4'b0111) ||
(i2c_state == 4'b1000) ||
(i2c_state == 4'b1001) )
? sdo : 1'bz;
*/
i2c_slave u_i2c_slave (
.clk (clk),
.rst_n (rst_n),
.add_nbyte (4'h2),
.data_nbyte (4'h2),
.id (7'h23),
.rdata_i (32'h454647ff),
//i2c signal
.scl (scl),
.sdi (sdi),
.sdo (sdo),
.start_o (start),
.stop_o (stop),
.i2c_state_o(i2c_state),
.cnt_o (cnt)
);
endmodule
| 7.828939 |
module name - ts_injection_schedule
// Version: TIS_V1.0
// Created:
// by - fenglin
// at - 10.2020
////////////////////////////////////////////////////////////////////////////
// Description:
// injection schedule of time-sensitive packet
// - parse command;
// - use a true dual port ram to cache injection slot table;
// - schedule descriptor of time-sensitive packet according to injection slot table;
// - top module.
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module ts_injection_schedule
(
i_clk,
i_rst_n,
iv_hardware_stage,
iv_syn_clk,
iv_time_slot_length,
i_ts_injection_addr_ack,
ov_ts_injection_addr,
o_ts_injection_addr_wr,
iv_injection_slot_table_wdata,
i_injection_slot_table_wr,
iv_injection_slot_table_addr,
ov_injection_slot_table_rdata,
i_injection_slot_table_rd,
ism_state,
iv_injection_slot_table_period
);
// I/O
// clk & rst
input i_clk;
input i_rst_n;
//configuration finish and time synchronization finish
input [2:0] iv_hardware_stage;
// calculation of time slot
input [63:0] iv_syn_clk;
input [10:0] iv_time_slot_length; // measure:us
// result of schedule
output [4:0] ov_ts_injection_addr;
output o_ts_injection_addr_wr;
input i_ts_injection_addr_ack;
input [15:0] iv_injection_slot_table_wdata;
input i_injection_slot_table_wr;
input [9:0] iv_injection_slot_table_addr;
output [15:0] ov_injection_slot_table_rdata;
input i_injection_slot_table_rd;
output [2:0] ism_state;
input [10:0] iv_injection_slot_table_period;
wire [9:0] wv_time_slot;
wire w_time_slot_switch;
time_slot_calculation injection_time_calculation_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.iv_syn_clk (iv_syn_clk),
.iv_time_slot_length(iv_time_slot_length),
.iv_slot_period (iv_injection_slot_table_period),
.ov_time_slot (wv_time_slot),
.o_time_slot_switch (w_time_slot_switch)
);
injection_schedule_module injection_schedule_module_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.iv_hardware_stage (iv_hardware_stage),
.iv_time_slot (wv_time_slot),
.i_time_slot_switch (w_time_slot_switch),
.iv_injection_slot_table_wdata(iv_injection_slot_table_wdata),
.i_injection_slot_table_wr (i_injection_slot_table_wr),
.iv_injection_slot_table_addr (iv_injection_slot_table_addr),
.ov_injection_slot_table_rdata(ov_injection_slot_table_rdata),
.i_injection_slot_table_rd (i_injection_slot_table_rd),
.i_ts_injection_addr_ack(i_ts_injection_addr_ack),
.ov_ts_injection_addr (ov_ts_injection_addr),
.o_ts_injection_addr_wr (o_ts_injection_addr_wr),
.ism_state(ism_state)
);
endmodule
| 7.593113 |
module ts_j83_buf (
rst,
clk,
clk_x2,
ts_rd_valid,
ts_i_valid,
ts_i_data,
ts_o_data
);
parameter RAM_WIDTH = 8;
parameter RAM_DEPTH_BIT = 10;
input rst;
input clk;
input clk_x2;
input ts_rd_valid;
input ts_i_valid;
input [7:0] ts_i_data;
output [7:0] ts_o_data;
wire [ 7:0] ts_o_data;
reg ram_wren;
reg [RAM_DEPTH_BIT - 1 : 0] ram_waddr;
reg [ RAM_WIDTH - 1 : 0] ram_din;
reg [RAM_DEPTH_BIT - 1 : 0] ram_raddr;
wire [ RAM_WIDTH - 1 : 0] ram_dout;
always @(posedge clk_x2 or posedge rst) begin
if (rst == 1'b1) begin
ram_wren <= 1'b0;
ram_din <= {RAM_WIDTH{1'b0}};
end else begin
ram_wren <= ts_i_valid;
ram_din <= ts_i_data;
end
end
always @(posedge clk_x2 or posedge rst) begin
if (rst == 1'b1) begin
ram_waddr <= 751;
end else if (ts_i_valid == 1'b1) begin
ram_waddr <= ram_waddr + 'h1;
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
ram_raddr <= {RAM_DEPTH_BIT{1'b0}};
end else if (ts_rd_valid == 1'b1) begin
ram_raddr <= ram_raddr + 'h1;
end
end
assign ts_o_data = ram_dout;
//width:8;depth:1024;read latency=2;
ts_j83_sdpram u0_ts_j83_sdpram (
.clka (clk_x2),
.wea (ram_wren),
.addra(ram_waddr),
.dina (ram_din),
.clkb (clk),
.addrb(ram_raddr),
.doutb(ram_dout)
);
endmodule
| 7.320353 |
module ts_j83_sdpram (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
input clkb;
input [9 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_2 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("kintex7"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("ts_j83_sdpram.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("kintex7")
) inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
| 6.7988 |
module ts_j83_sdpram (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [7 : 0] doutb;
// WARNING: This file provides a module declaration only, it does not support
// direct instantiation. Please use an instantiation template (VEO) to
// instantiate the IP within a design.
endmodule
| 6.7988 |
module ts_mike_fsm (
in,
clock,
out
);
input [3:0] in;
input clock;
output [9:0] out;
reg [9:0] out;
reg [2:0] current_state;
reg [2:0] next_state;
// Input patterns
parameter pattern_X = 4'b0000, pattern_Y = 4'b0101, pattern_Z = 4'b1111, pattern_W = 4'b0011;
// Output patterns
parameter pattern_A = 9'b1000101101,
pattern_B = 9'b0111110101,
pattern_C = 9'b1010110000,
pattern_D = 9'b1101010010;
// Only sequential operation is to remember state.
always @(posedge clock) begin
current_state <= next_state;
end
// output pattern is based on input pattern and state.
always @(in, current_state) begin
case (in)
pattern_X: begin
if (current_state == `yaska) begin
out = pattern_A;
next_state = `bryan;
end else if (current_state == `bryan) begin
out = pattern_B;
next_state = `andy;
end else begin
out = pattern_C;
next_state = `josh;
end
end
pattern_Y: begin
if (current_state == `jay) begin
out = pattern_A;
next_state = `jay;
end else if (current_state == `josh) begin
out = pattern_B;
next_state = `bryan;
end else begin
out = pattern_C;
next_state = `mike;
end
end
pattern_Z: begin
if (current_state == `jay) begin
out = pattern_A;
next_state = `andy;
end else begin
out = pattern_B;
next_state = `mike;
end
end
pattern_W: begin
out = pattern_C;
next_state = `mike;
end
default: begin
out = pattern_D;
next_state = `yaska;
end
endcase
end
endmodule
| 7.159496 |
module ts_radian (
input clk,
input rst_n,
input touch,
output [7:0] sin_o,
output clk_o,
output rst_n_o,
output touch_o,
output [3:0] cnt_o
);
reg [31:0] angle;
reg [ 3:0] cnt;
wire [31:0] sin;
assign clk_o = clk;
assign rst_n = rst_n_o;
assign touch_o = touch;
assign cnt_o[3:0] = cnt[3:0];
always @(posedge clk or negedge rst_n)
if (!rst_n) angle <= 32'd00;
else if (touch & (cnt == 4'h8)) angle <= angle + 32'd100;
else if (angle == 32'd1000) angle <= 32'd00;
always @(posedge clk or negedge rst_n)
if (!rst_n) cnt <= 4'h0;
else if (cnt == 4'h8) cnt <= 4'h0;
else if (touch) cnt <= cnt + 1'b1;
assign sin_o[7:0] = sin[7:0];
radian u_radian (
.clk(clk),
.rst_n(rst_n),
.angle(angle),
.radian(radian),
.sin_o(sin)
);
endmodule
| 7.907954 |
module name - ts_submit_schedule
// Version: TSS_V1.0
// Created:
// by - fenglin
// at - 10.2020
////////////////////////////////////////////////////////////////////////////
// Description:
// submit schedule of time-sensitive packet
// - parse command;
// - use a true dual port ram to cache submit slot table;
// - schedule descriptor of time-sensitive packet according to submit slot table.
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module ts_submit_schedule
(
i_clk,
i_rst_n,
iv_cfg_finish,
iv_syned_global_time,
iv_time_slot_length,
i_ts_submit_addr_ack,
ov_ts_submit_addr,
o_ts_submit_addr_wr,
ssm_state,
iv_submit_slot_table_wdata,
i_submit_slot_table_wr,
iv_submit_slot_table_addr,
ov_submit_slot_table_rdata,
i_submit_slot_table_rd,
iv_submit_slot_table_period
);
// I/O
// clk & rst
input i_clk;
input i_rst_n;
//configuration finish and time synchronization finish
input [1:0] iv_cfg_finish;
// calculation of time slot
input [47:0] iv_syned_global_time;
input [10:0] iv_time_slot_length; // measure:us
// result of schedule
output [4:0] ov_ts_submit_addr;
output o_ts_submit_addr_wr;
// FLM get ts_descriptor to look up table
input i_ts_submit_addr_ack;
output [2:0] ssm_state;
input [15:0] iv_submit_slot_table_wdata;
input i_submit_slot_table_wr;
input [9:0] iv_submit_slot_table_addr;
output [15:0] ov_submit_slot_table_rdata;
input i_submit_slot_table_rd;
input [10:0] iv_submit_slot_table_period;
// internal reg&wire for schedule
wire [9:0] time_slot_itc2ism;
wire w_time_slot_switch;
time_slot_calculation submit_time_calculation_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.iv_syned_global_time(iv_syned_global_time),
.iv_time_slot_length(iv_time_slot_length),
.iv_table_period(iv_submit_slot_table_period),
.ov_time_slot(time_slot_itc2ism),
.o_time_slot_switch(w_time_slot_switch)
);
submit_schedule_module submit_schedule_module_inst(
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.iv_cfg_finish(iv_cfg_finish),
.iv_time_slot(time_slot_itc2ism),
.i_time_slot_switch(w_time_slot_switch),
.iv_submit_slot_table_wdata(iv_submit_slot_table_wdata),
.i_submit_slot_table_wr(i_submit_slot_table_wr),
.iv_submit_slot_table_addr(iv_submit_slot_table_addr),
.ov_submit_slot_table_rdata(ov_submit_slot_table_rdata),
.i_submit_slot_table_rd(i_submit_slot_table_rd),
.i_ts_submit_addr_ack(i_ts_submit_addr_ack),
.ov_ts_submit_addr(ov_ts_submit_addr),
.o_ts_submit_addr_wr(o_ts_submit_addr_wr),
.ssm_state(ssm_state)
);
endmodule
| 9.018172 |
module Instruction_reg (
clk,
Read_Addr,
instruction,
reset
);
input clk, reset;
input [7:0] Read_Addr;
output [31:0] instruction;
wire instruction;
endmodule
| 6.692892 |
module CU (
instruction,
busy_wait,
OUT1addr,
OUT2addr,
INaddr,
Imm,
Select,
addSubMUX,
imValueMUX,
dmMUX,
read,
write,
address
);
input [31:0] instruction;
input busy_wait;
output [2:0] OUT1addr;
output [2:0] OUT2addr;
output [2:0] Select;
output [2:0] INaddr;
output [7:0] Imm, address;
output addSubMUX, imValueMUX, dmMUX, read, write;
reg [2:0] OUT1addr, OUT2addr, INaddr, Select;
reg [7:0] Imm, address;
reg addSubMUX, imValueMUX, dmMUX, read, write;
always @(instruction) begin
if (!busy_wait) begin //Stall if DM access is happening
assign Select = instruction[26:24]; //Common Signals
assign Imm = instruction[7:0];
assign OUT1addr = instruction[2:0];
assign OUT2addr = instruction[10:8];
assign INaddr = instruction[18:16];
assign imValueMUX = 1'b1;
assign addSubMUX = 1'b0;
assign write = 1'b0;
assign read = 1'b0;
assign dmMUX = 1'b1;
case (instruction[31:24])
8'b00000000: begin //loadi
assign imValueMUX = 1'b0;
end
8'b00001001: begin //sub
assign addSubMUX = 1'b1;
end
8'b00000100: begin //load
assign read = 1'b1;
assign dmMUX = 1'b0;
assign address = instruction[7:0];
end
8'b00000101: begin //store
assign write = 1'b1;
assign address = instruction[23:16];
end
endcase
end
end
endmodule
| 7.054686 |
module TwosComplement (
OUTPUT,
INPUT
);
input [7:0] INPUT;
output [7:0] OUTPUT;
assign OUTPUT[7:0] = -INPUT[7:0];
endmodule
| 8.45255 |
module ALU (
RESULT,
DATA1,
DATA2,
SELECT
);
input [7:0] DATA1, DATA2; //Source 1 & 2
input [2:0] SELECT;
output [7:0] RESULT;
reg [7:0] Res;
assign RESULT = Res;
always @(DATA1, DATA2, SELECT) begin
case (SELECT)
0: Res = DATA1; //Forward ( loadi, mov )
1: Res = DATA1 + DATA2; //Addition ( add, sub )
2: Res = DATA1 & DATA2; //Bitwise AND ( and )
3: Res = DATA1 | DATA2; //Bitwise OR ( or )
4: Res = DATA1; //Forward ( load )
5: Res = DATA1; //Forward ( store )
default: Res = 0;
endcase
end
endmodule
| 7.336322 |
module data_mem (
clk,
rst,
read,
write,
address,
write_data,
read_data,
busy_wait
);
input clk;
input rst;
input read;
input write;
input [6:0] address;
input [15:0] write_data;
output [15:0] read_data;
output busy_wait;
reg busy_wait = 1'b0;
reg [15:0] read_data;
integer i;
// Declare memory 128x16 bits
reg [15:0] memory_array[127:0];
always @(posedge rst) //Reset Data memory
begin
if (rst) begin
for (i = 0; i < 128; i = i + 1) memory_array[i] <= 0;
end
end
always @(read, write, address, write_data) begin
if ( write && !read ) //Write to Data memory
begin
busy_wait <= 1;
//Artificial delay 98 cycles
repeat (98) begin
@(posedge clk);
end
memory_array[address] = write_data;
busy_wait <= 0;
end
if (!write && read) begin //Read from Data memory
busy_wait <= 1;
//Artificial delay 98 cycles
repeat (98) begin
@(posedge clk);
end
read_data = memory_array[address];
busy_wait <= 0;
end
end
endmodule
| 7.214114 |
module Comparator (
Out,
Input1,
Input2
);
input [3:0] Input1;
input [3:0] Input2;
output Out;
wire out1, out2, out3, out4;
xnor xnor1 (out1, Input1[0], Input2[0]);
xnor xnor2 (out2, Input1[1], Input2[1]);
xnor xnor3 (out3, Input1[2], Input2[2]);
xnor xnor4 (out4, Input1[3], Input2[3]);
and and1 (Out, out1, out2, out3, out4);
endmodule
| 8.939213 |
module tt800 (
input clk, // timespec 3.0 ns
input en,
input init,
input [31:0] initv,
output [31:0] y
);
wire [31:0] tap1, tap2;
wire [31:0] x = tap1 ^ (tap2 >> 1) ^ ({32{tap2[0]}} & 32'h8ebfd028);
wire [31:0] newv = init ? initv : x;
reg_delay #(
.dw (32),
.len(18)
) d1 (
.clk (clk),
.reset(1'b0),
.gate (en),
.din (newv),
.dout (tap1)
);
reg_delay #(
.dw (32),
.len(7)
) d2 (
.clk (clk),
.reset(1'b0),
.gate (en),
.din (tap1),
.dout (tap2)
);
wire [31:0] y1 = tap2 ^ ((tap2 << 7) & 32'h2b5b2500); /* s and b */
wire [31:0] y2 = y1 ^ ((y1 << 15) & 32'hdb8b0000); /* t and c */
wire [31:0] y3 = y2 ^ (y2 >> 16); /* update from 1996 by Makoto Matsumoto */
reg [31:0] y_r = 0;
always @(posedge clk) if (en) y_r <= y3; // use tap2 for T800
assign y = y_r;
endmodule
| 6.724634 |
module tta16_tile_tb;
`define IO_DECODE_BITS 20:18
`define IO_FLUSH 3'b1_10__
`define IO_DMA 3'b1_00__
`define IO_CRTC 3'b0_00__
`define IO_SPROM 3'b0_01__
`define IO_LEDS 3'b0_10__
reg wb_clk = 1;
reg cpu_clk = 1;
reg reset = 0;
reg cache_reset = 0;
always #15 wb_clk = ~wb_clk;
always #5 cpu_clk = ~cpu_clk;
wire mem_cyc, mem_stb, mem_we;
reg mem_ack = 0;
reg mem_rty = 0;
reg mem_err = 0;
wire [2:0] mem_cti;
wire [1:0] mem_bte;
wire [20:0] mem_adr;
wire [3:0] mem_sel_f;
wire [31:0] mem_dat_f;
reg [3:0] mem_sel_t;
reg [31:0] mem_dat_t;
wire io_cyc, io_stb, io_we;
reg io_ack = 0;
reg io_rty = 0;
reg io_err = 0;
wire [2:0] io_cti;
wire [1:0] io_bte;
wire [20:0] io_adr;
wire [1:0] io_sel_f;
wire [15:0] io_dat_f;
reg [1:0] io_sel_t;
reg [15:0] io_dat_t;
initial begin : Sim
$dumpfile("tb.vcd");
$dumpvars;
#22 reset = 1;
#160 reset = 0;
#2400 $display("Test Completed.");
$finish;
end // Sim
initial begin : Safety_Net
#15000 $display("ERROR: Unclean exit");
$finish;
end // Safety_Net
always @(posedge wb_clk)
if (reset) mem_ack <= #2 0;
else if (mem_cyc && mem_stb) begin
// Atomic transaction or end of burst.
if (mem_ack && (mem_cti == 3'b000 || mem_cti == 3'b111)) mem_ack <= #2 0;
else mem_ack <= #2 1;
end
always @(posedge wb_clk)
if (reset) io_ack <= #2 0;
else if (io_cyc && io_stb && !io_ack) // Atomic only
io_ack <= #2 1;
else io_ack <= #2 0;
always @(posedge wb_clk)
if (reset) cache_reset <= #2 0;
else if (io_cyc && io_stb && (io_adr[`IO_DECODE_BITS] == `IO_FLUSH) && !cache_reset)
cache_reset <= #2 1;
else cache_reset <= #2 0;
tta16_tile #(
.ADDRESS(23)
) TTA0 (
.wb_rst_i(reset),
.wb_clk_i(wb_clk), // 50 MHz
.cpu_clk_i(cpu_clk), // 150 MHz, sync with WB clock
.cache_rst_i(cache_reset),
.mem_cyc_o(mem_cyc),
.mem_stb_o(mem_stb),
.mem_we_o (mem_we),
.mem_ack_i(mem_ack),
.mem_rty_i(mem_rty),
.mem_err_i(mem_err),
.mem_cti_o(mem_cti),
.mem_bte_o(mem_bte),
.mem_adr_o(mem_adr),
.mem_sel_o(mem_sel_f),
.mem_dat_o(mem_dat_f),
.mem_sel_i(mem_sel_t),
.mem_dat_i(mem_dat_t),
.io_cyc_o(io_cyc),
.io_stb_o(io_stb),
.io_we_o (io_we),
.io_ack_i(io_ack),
.io_rty_i(io_rty),
.io_err_i(io_err),
.io_cti_o(io_cti),
.io_bte_o(io_bte),
.io_adr_o(io_adr),
.io_sel_o(io_sel_f),
.io_dat_o(io_dat_f),
.io_sel_i(io_sel_t),
.io_dat_i(io_dat_t)
);
endmodule
| 8.257891 |
module tta_stream4to4_async #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1
) (
input enable_i,
input [1:0] src_i,
input [1:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
output reg [ 3:0] srcsels_o,
output reg [ 3:0] dstsels_o,
output reg [ 1:0] dstpack_o,
output reg [MSB:0] data_o
);
always @* begin
case (src_i)
0: srcsels_o <= #1 1;
1: srcsels_o <= #1 2;
2: srcsels_o <= #1 4;
3: srcsels_o <= #1 8;
endcase
case (src_i)
0: data_o <= #1 data0_i;
1: data_o <= #1 data1_i;
2: data_o <= #1 data2_i;
3: data_o <= #1 data3_i;
endcase
case (dst_i)
0: dstsels_o <= #1 1;
1: dstsels_o <= #1 2;
2: dstsels_o <= #1 4;
3: dstsels_o <= #1 8;
endcase
end
endmodule
| 8.849374 |
module tta_stream4to4_sync #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1,
parameter ENCLR = 1
) (
input clock_i,
input enable_i,
input [1:0] src_i,
input [1:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
output reg [ 3:0] srcsels_o,
output reg [ 3:0] dstsels_o,
output reg [ 1:0] dstpack_o,
output reg [MSB:0] data_o
);
always @(posedge clock_i)
if (enable_i) begin
case (src_i)
0: srcsels_o <= #1 1;
1: srcsels_o <= #1 2;
2: srcsels_o <= #1 4;
3: srcsels_o <= #1 8;
endcase
case (src_i)
0: data_o <= #1 data0_i;
1: data_o <= #1 data1_i;
2: data_o <= #1 data2_i;
3: data_o <= #1 data3_i;
endcase
case (dst_i)
0: dstsels_o <= #1 1;
1: dstsels_o <= #1 2;
2: dstsels_o <= #1 4;
3: dstsels_o <= #1 8;
endcase
dstpack_o <= #2 dst_i;
end else begin
srcsels_o <= #2 ENCLR ? 0 : srcsels_o;
dstsels_o <= #2 ENCLR ? 0 : dstsels_o;
dstpack_o <= #2 ENCLR ? 0 : dstpack_o;
end
endmodule
| 8.849374 |
module tta_stream4to8_async #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1
) (
input enable_i,
input [1:0] src_i,
input [2:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
output reg [ 3:0] srcsels_o,
output reg [ 2:0] dstpack_o,
output reg [ 7:0] dstsels_o,
output reg [MSB:0] data_o
);
always @*
if (enable_i) begin
case (src_i)
0: srcsels_o <= #1 1;
1: srcsels_o <= #1 2;
2: srcsels_o <= #1 4;
3: srcsels_o <= #1 8;
endcase
case (src_i)
0: data_o <= #1 data0_i;
1: data_o <= #1 data1_i;
2: data_o <= #1 data2_i;
3: data_o <= #1 data3_i;
endcase
case (dst_i)
0: dstsels_o <= #1 1;
1: dstsels_o <= #1 2;
2: dstsels_o <= #1 4;
3: dstsels_o <= #1 8;
4: dstsels_o <= #1 16;
5: dstsels_o <= #1 32;
6: dstsels_o <= #1 64;
7: dstsels_o <= #1 128;
endcase
dstpack_o <= #2 dst_i;
end else begin
dstsels_o <= #2 0;
dstpack_o <= #2 0;
end
endmodule
| 8.849374 |
module tta_stream4to8_sync #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1,
parameter ENCLR = 1
) (
input clock_i,
input enable_i,
input [1:0] src_i,
input [2:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
output reg [ 3:0] srcsels_o,
output reg [ 2:0] dstpack_o,
output reg [ 7:0] dstsels_o,
output reg [MSB:0] data_o
);
always @(posedge clock_i)
if (enable_i) begin
case (src_i)
0: srcsels_o <= #1 1;
1: srcsels_o <= #1 2;
2: srcsels_o <= #1 4;
3: srcsels_o <= #1 8;
endcase
case (src_i)
0: data_o <= #1 data0_i;
1: data_o <= #1 data1_i;
2: data_o <= #1 data2_i;
3: data_o <= #1 data3_i;
endcase
case (dst_i)
0: dstsels_o <= #1 1;
1: dstsels_o <= #1 2;
2: dstsels_o <= #1 4;
3: dstsels_o <= #1 8;
4: dstsels_o <= #1 16;
5: dstsels_o <= #1 32;
6: dstsels_o <= #1 64;
7: dstsels_o <= #1 128;
endcase
dstpack_o <= #2 dst_i;
end else begin
srcsels_o <= #2 ENCLR ? 0 : srcsels_o;
dstsels_o <= #2 ENCLR ? 0 : dstsels_o;
dstpack_o <= #2 ENCLR ? 0 : dstpack_o;
end
endmodule
| 8.849374 |
module tta_stream8to8_async #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1,
parameter ENCLR = 1
) (
input enable_i,
input [2:0] src_i,
input [2:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
input [MSB:0] data4_i,
input [MSB:0] data5_i,
input [MSB:0] data6_i,
input [MSB:0] data7_i,
output reg [ 7:0] srcsels_o,
output reg [ 7:0] dstsels_o,
output reg [MSB:0] data_o
);
always @*
if (enable_i) begin
case (src_i)
0: srcsels_o <= #1 1;
1: srcsels_o <= #1 2;
2: srcsels_o <= #1 4;
3: srcsels_o <= #1 8;
4: srcsels_o <= #1 16;
5: srcsels_o <= #1 32;
6: srcsels_o <= #1 64;
7: srcsels_o <= #1 128;
endcase
case (src_i)
0: data_o <= #1 data0_i;
1: data_o <= #1 data1_i;
2: data_o <= #1 data2_i;
3: data_o <= #1 data3_i;
4: data_o <= #1 data4_i;
5: data_o <= #1 data5_i;
6: data_o <= #1 data6_i;
7: data_o <= #1 data7_i;
endcase
case (dst_i)
0: dstsels_o <= #1 1;
1: dstsels_o <= #1 2;
2: dstsels_o <= #1 4;
3: dstsels_o <= #1 8;
4: dstsels_o <= #1 16;
5: dstsels_o <= #1 32;
6: dstsels_o <= #1 64;
7: dstsels_o <= #1 128;
endcase
end else begin
srcsels_o <= #1 0;
dstsels_o <= #1 0;
end
endmodule
| 8.429529 |
module tta_stream8to8_sync #(
parameter WIDTH = 18,
parameter MSB = WIDTH - 1,
parameter ENCLR = 1
) (
input clock_i,
input enable_i,
input [2:0] src_i,
input [2:0] dst_i,
input [MSB:0] data0_i,
input [MSB:0] data1_i,
input [MSB:0] data2_i,
input [MSB:0] data3_i,
input [MSB:0] data4_i,
input [MSB:0] data5_i,
input [MSB:0] data6_i,
input [MSB:0] data7_i,
output reg [ 7:0] srcsels_o,
output reg [ 7:0] dstsels_o,
output reg [ 2:0] dstpack_o,
output reg [MSB:0] data_o
);
always @(posedge clock_i)
if (enable_i) begin
case (src_i)
0: srcsels_o <= #1 1;
1: srcsels_o <= #1 2;
2: srcsels_o <= #1 4;
3: srcsels_o <= #1 8;
4: srcsels_o <= #1 16;
5: srcsels_o <= #1 32;
6: srcsels_o <= #1 64;
7: srcsels_o <= #1 128;
endcase
case (src_i)
0: data_o <= #1 data0_i;
1: data_o <= #1 data1_i;
2: data_o <= #1 data2_i;
3: data_o <= #1 data3_i;
4: data_o <= #1 data4_i;
5: data_o <= #1 data5_i;
6: data_o <= #1 data6_i;
7: data_o <= #1 data7_i;
endcase
case (dst_i)
0: dstsels_o <= #1 1;
1: dstsels_o <= #1 2;
2: dstsels_o <= #1 4;
3: dstsels_o <= #1 8;
4: dstsels_o <= #1 16;
5: dstsels_o <= #1 32;
6: dstsels_o <= #1 64;
7: dstsels_o <= #1 128;
endcase
dstpack_o <= #2 dst_i;
end else begin
srcsels_o <= #2 ENCLR ? 0 : srcsels_o;
dstsels_o <= #2 ENCLR ? 0 : dstsels_o;
dstpack_o <= #2 ENCLR ? 0 : dstpack_o;
end
endmodule
| 8.429529 |
module: timer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ttb;
// Inputs
reg clk;
reg reset;
reg [3:2] PrAddr;
reg Wr_en;
reg [31:0] Data_in;
// Outputs
wire IRQ;
wire [31:0] Data_out;
// Instantiate the Unit Under Test (UUT)
timer uut (
.clk(clk),
.reset(reset),
.PrAddr(PrAddr),
.Wr_en(Wr_en),
.Data_in(Data_in),
.IRQ(IRQ),
.Data_out(Data_out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
PrAddr = 0;
Wr_en = 0;
Data_in = 0;
// Wait 100 ns for global reset to finish
#100;
reset=0;
ADD_I = 0;
WE_I = 0;
DAT_I = 9;
#10;
ADD_I = 2'b01;
WE_I = 1;
RST_I = 0;
#10;
ADD_I = 2'b00;
DAT_I = {28'd0,1'b1,2'b00,1'b1};
#10;
WE_I = 0;
#200;
WE_I = 1;
DAT_I = {28'd0,1'b0,2'b01,1'b1};
#10;
WE_I = 0;
// Add stimulus here
end
endmodule
| 7.287821 |
module ttc_count_rst_lite (
//inputs
n_p_reset,
pclk,
pwdata,
clk_ctrl_reg_sel,
restart,
//outputs
count_en_out,
clk_ctrl_reg_out
);
//-----------------------------------------------------------------------------
// PORT DECLARATIONS
//-----------------------------------------------------------------------------
// inputs
input n_p_reset; // Reset signal
input pclk; // APB System clock
input [6:0] pwdata; // 7-Bit pwdata from APB interface
input clk_ctrl_reg_sel; // Select for the clk_ctrl_reg
input restart; // Restart reset from cntr_ctrl_reg
// outputs
output count_en_out;
output [6:0] clk_ctrl_reg_out; // Controls clock selected
//-----------------------------------------------------------------------------
// Internal Signals & Registers
//-----------------------------------------------------------------------------
reg [6:0] clk_ctrl_reg; //7-bit clock control register.
reg restart_var; //ensures prescaler reset at start of restart
reg count_en; //enable signal to counter
wire [6:0] clk_ctrl_reg_out; //clock control output wire
wire count_en_out; //counter enable output
//-----------------------------------------------------------------------------
// Logic Section:
//
// p_clk_ctrl: Process to implement the clk_ctrl_reg.
// When select line is set then the data will be inserted to
// the clock control register, otherwise it will be equal to
// the previous value of the register, else it will be zero.
//-----------------------------------------------------------------------------
assign clk_ctrl_reg_out = clk_ctrl_reg;
assign count_en_out = count_en;
// p_ps_counter: counter for clock enable generation.
always @(posedge pclk or negedge n_p_reset) begin : p_ps_counter
if (!n_p_reset) begin
restart_var <= 1'b0;
count_en <= 1'b0;
end else begin
if (restart & ~restart_var) begin
restart_var <= 1'b1;
count_en <= 1'b0;
end else begin
if (~restart) restart_var <= 1'b0;
else restart_var <= restart_var;
count_en <= 1'b1;
end
end // else: !if(!n_p_reset)
end //p_ps_counter
// p_clk_ctrl : Process for writing to the clk_ctrl_reg
always @(posedge pclk or negedge n_p_reset) begin : p_clk_ctrl
if (!n_p_reset) clk_ctrl_reg <= 7'h00;
else begin
if (clk_ctrl_reg_sel) clk_ctrl_reg <= pwdata;
else clk_ctrl_reg <= clk_ctrl_reg;
end
end //p_clk_ctrl
endmodule
| 7.404301 |
module ls74 (
input n_pre1,
n_pre2,
input n_clr1,
n_clr2,
input clk1,
clk2,
input d1,
d2,
output reg q1,
q2,
output n_q1,
n_q2
);
always @(posedge clk1 or negedge n_pre1 or negedge n_clr1) begin
if (!n_pre1) q1 <= 1;
else if (!n_clr1) q1 <= 0;
else q1 <= d1;
end
assign n_q1 = ~q1;
always @(posedge clk2 or negedge n_pre2 or negedge n_clr2) begin
if (!n_pre2) q2 <= 1;
else if (!n_clr2) q2 <= 0;
else q2 <= d2;
end
assign n_q2 = ~q2;
endmodule
| 6.902507 |
module ls161 //asynchronous reset/clear
(
input n_clr,
input clk,
input [3:0] din,
input enp,
ent,
input n_load,
output [3:0] q,
output rco
);
reg [3:0] data = 4'b0;
always @(posedge clk or negedge n_clr) begin
if (!n_clr) data <= 4'd0;
else if (!n_load) data <= din;
else if (enp && ent) data <= data + 4'd1;
end
assign q = data;
assign rco = data[0] & data[1] & data[2] & data[3] & ent;
endmodule
| 7.406391 |
module ls273 (
input [7:0] d,
input clk,
input res,
output reg [7:0] q
);
always @(posedge clk or negedge res) begin
if (!res) q <= 8'h00;
else q <= d;
end
endmodule
| 6.811434 |
module ls166 (
input clk,
input load,
input [7:0] in,
output out
);
reg [7:0] tmp;
always @(posedge clk) begin
if (!load) tmp <= in;
else tmp <= {tmp[6:0], 1'b0};
end
assign out = tmp[7];
endmodule
| 6.876022 |
module ls174 (
input [5:0] d,
input clk,
input mr,
output reg [5:0] q
);
always @(posedge clk or negedge mr) begin
if (!mr) q <= 6'b000000;
else q <= d;
end
endmodule
| 7.110512 |
module ls157 (
input [3:0] i0,
input [3:0] i1,
input n_e,
input s,
output [3:0] z
);
assign z = (!n_e && !s) ? i0 : (!n_e && s) ? i1 : 4'b0000;
endmodule
| 7.048406 |
module TTL74148_RTL (
nS,
nIN,
Y,
Ys,
Yex
);
input nS;
input [7:0] nIN;
output reg [2:0] Y;
output reg Ys;
output reg Yex;
always @(nS, nIN) begin
if (nS) begin
Y <= 3'b111;
Yex <= 1'b1;
Ys <= 1'b1;
end else if (nIN == 8'b11111111) begin
Y <= 3'b111;
Yex <= 1'b1;
Ys <= 1'b0;
end else if (!nIN[7]) begin
Y <= 3'b000;
Yex <= 1'b0;
Ys <= 1'b1;
end else if (!nIN[6]) begin
Y <= 3'b001;
Yex <= 1'b0;
Ys <= 1'b1;
end else if (!nIN[5]) begin
Y <= 3'b010;
Yex <= 1'b0;
Ys <= 1'b1;
end else if (!nIN[4]) begin
Y <= 3'b011;
Yex <= 1'b0;
Ys <= 1'b1;
end else if (!nIN[3]) begin
Y <= 3'b100;
Yex <= 1'b0;
Ys <= 1'b1;
end else if (!nIN[2]) begin
Y <= 3'b101;
Yex <= 1'b0;
Ys <= 1'b1;
end else if (!nIN[1]) begin
Y <= 3'b110;
Yex <= 1'b0;
Ys <= 1'b1;
end else begin
Y <= 3'b111;
Yex <= 1'b0;
Ys <= 1'b1;
end
end
endmodule
| 6.669471 |
module
//
`timescale 1ns/10ps
module TTL_7400 (
input A1, B1, // Unit A
output Y1,
input A2, B2, // Unit B
output Y2,
input A3, B3, // Unit C
output Y3,
input A4, B4, // Unit D
output Y4
);
not #(0:9:15, 0:10:15) (Y1, A1 & B1);
not #(0:9:15, 0:10:15) (Y2, A2 & B2);
not #(0:9:15, 0:10:15) (Y3, A3 & B3);
not #(0:9:15, 0:10:15) (Y4, A4 & B4);
endmodule
| 6.662614 |
module
//
`timescale 1ns/10ps
module TTL_7402 (
input A1, B1, // Unit A
output Y1,
input A2, B2, // Unit B
output Y2,
input A3, B3, // Unit C
output Y3,
input A4, B4, // Unit D
output Y4
);
not #(0:10:15, 0:10:15) (Y1, A1 | B1);
not #(0:10:15, 0:10:15) (Y2, A2 | B2);
not #(0:10:15, 0:10:15) (Y3, A3 | B3);
not #(0:10:15, 0:10:15) (Y4, A4 | B4);
endmodule
| 6.662614 |
module
//
`timescale 1ns/10ps
module TTL_7404 (
input A1, // Unit A
output Y1,
input A2, // Unit B
output Y2,
input A3, // Unit C
output Y3,
input A4, // Unit D
output Y4,
input A5, // Unit E
output Y5,
input A6, // Unit F
output Y6
);
not #(0:9:15, 0:10:15) (Y1, A1);
not #(0:9:15, 0:10:15) (Y2, A2);
not #(0:9:15, 0:10:15) (Y3, A3);
not #(0:9:15, 0:10:15) (Y4, A4);
not #(0:9:15, 0:10:15) (Y5, A5);
not #(0:9:15, 0:10:15) (Y6, A6);
endmodule
| 6.662614 |
module
//
`timescale 1ns/10ps
module TTL_7408 (
input A1, B1, // Unit A
output Y1,
input A2, B2, // Unit B
output Y2,
input A3, B3, // Unit C
output Y3,
input A4, B4, // Unit D
output Y4
);
and #(0:8:15, 0:10:20) (Y1, A1, B1);
and #(0:8:15, 0:10:20) (Y2, A2, B2);
and #(0:8:15, 0:10:20) (Y3, A3, B3);
and #(0:8:15, 0:10:20) (Y4, A4, B4);
endmodule
| 6.662614 |
module ttl_74107a_AsyncClr #(
parameter BLOCKS = 2
) (
input wire [BLOCKS-1:0] CLRn,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] K,
input wire [BLOCKS-1:0] Clk,
input wire [BLOCKS-1:0] Cen,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Qn
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
reg last_cen;
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1) begin : gen_blocks
initial Q_current[i] = 1'b0; //supposition
initial last_cen = 1'b1;
always @(posedge Clk[i]) begin
if (!CLRn[i]) begin
Q_current[i] <= 1'b0; //CLEAR
end else begin
last_cen <= Cen;
if (!Cen && last_cen) begin //detect falling edge of Cen
if (!J[i] && K[i]) Q_current[i] <= 1'b0; //set low
else if (J[i] && K[i]) Q_current[i] <= ~Q_current[i]; //toggle
else if (J[i] && ~K[i]) Q_current[i] <= 1'b1; //set high
// else J=K=L
// Q_current[i] <= Q_current[i]; //hold value
end
end
end
end
endgenerate
//------------------------------------------------//
assign Q = Q_current;
assign Qn = ~Q_current;
endmodule
| 6.908183 |
module ttl_74107a_sync #(
parameter BLOCKS = 2
) (
input wire [BLOCKS-1:0] Reset_n,
input wire [BLOCKS-1:0] CLRn,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] K,
input wire [BLOCKS-1:0] Clk,
input wire [BLOCKS-1:0] Cen,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Qn
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
reg last_cen;
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1) begin : gen_blocks
initial Q_current[i] = 1'b0; //supposition
always @(posedge Clk[i]) begin
if (!Reset_n[i]) begin
Q_current[i] <= 1'b0; //CLEAR
last_cen <= 1'b1;
end else begin
last_cen <= Cen;
if (!CLRn[i]) begin
Q_current[i] <= 1'b0; //CLEAR
end else if (!Cen && last_cen) begin //detect falling edge of Cen
if (!J[i] && K[i]) Q_current[i] <= 1'b0; //set low
else if (J[i] && K[i]) Q_current[i] <= ~Q_current[i]; //toggle
else if (J[i] && ~K[i]) Q_current[i] <= 1'b1; //set high
// else J=K=L
// Q_current[i] <= Q_current[i]; //hold value
end
end
end
end
endgenerate
//------------------------------------------------//
assign Q = Q_current;
assign Qn = ~Q_current;
endmodule
| 6.668561 |
module ttl_74109_cl #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire [BLOCKS-1:0] Clear_bar,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] Kn,
input wire [BLOCKS-1:0] Clk,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Q_bar
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1) begin : gen_blocks
initial Q_current[i] = 1'b0; //supposition
always @(posedge Clk[i] or negedge Clear_bar[i]) begin
if (!Clear_bar[i]) Q_current[i] <= 1'b0; //CLEAR
else begin
if (!J[i] && !Kn[i]) Q_current[i] <= 1'b0; //set low
else if (J[i] && !Kn[i]) Q_current[i] <= ~Q_current[i]; //toggle
else if (J[i] && Kn[i]) Q_current[i] <= 1'b1; //set high
// else
// Q_current[i] <= Q_current[i]; //hold value
end
end
end
endgenerate
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
assign #(DELAY_RISE, DELAY_FALL) Q_bar = ~Q_current;
endmodule
| 6.623586 |
module ttl_74109_pre #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire [BLOCKS-1:0] Preset_bar,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] Kn,
input wire [BLOCKS-1:0] Clk,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Q_bar
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1) begin : gen_blocks
initial Q_current[i] = 1'b0; //supposition
always @(posedge Clk[i] or negedge Preset_bar[i]) begin
if (!Preset_bar[i]) Q_current[i] <= 1'b1;
else begin
if (!J[i] && !Kn[i]) Q_current[i] <= 1'b0; //set low
else if (J[i] && !Kn[i]) Q_current[i] <= ~Q_current[i]; //toggle
else if (J[i] && Kn[i]) Q_current[i] <= 1'b1; //set high
else Q_current[i] <= Q_current[i]; //hold value
end
end
end
endgenerate
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
assign #(DELAY_RISE, DELAY_FALL) Q_bar = ~Q_current;
endmodule
| 6.629015 |
module ttl_74112 #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire [BLOCKS-1:0] Preset_bar,
input wire [BLOCKS-1:0] Clear_bar,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] K,
input wire [BLOCKS-1:0] Clk,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Q_bar
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
//reg [BLOCKS-1:0] Preset_bar_previous;
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1) begin : gen_blocks
initial Q_current[i] = 1'b0; //supposition
always @(negedge Clk[i] or negedge Clear_bar[i] or negedge Preset_bar[i]) begin
if (!Clear_bar[i]) Q_current[i] <= 1'b0;
//else if (!Preset_bar[i] && Preset_bar_previous[i]) // falling edge has occurred
else if (!Preset_bar[i]) // falling edge has occurred
Q_current[i] <= 1'b1;
else begin
if (J[i] && !K[i] || !J[i] && K[i]) Q_current[i] <= J[i];
else if (J[i] && K[i]) Q_current[i] <= ~Q_current[i];
else Q_current[i] <= Q_current[i];
//Preset_bar_previous[i] <= Preset_bar[i];
end
end
end
endgenerate
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
assign #(DELAY_RISE, DELAY_FALL) Q_bar = ~Q_current;
endmodule
| 6.837249 |
module ttl_74112_sync #(
parameter BLOCKS = 2
) (
input wire [BLOCKS-1:0] PREn,
input wire [BLOCKS-1:0] CLRn,
input wire [BLOCKS-1:0] J,
input wire [BLOCKS-1:0] K,
input wire [BLOCKS-1:0] Clk,
input wire [BLOCKS-1:0] Cen,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Qn
);
reg [BLOCKS-1:0] Q_current;
reg [BLOCKS-1:0] last_cen;
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1) begin : gen_blocks
initial Q_current[i] = 1'b0;
always @(posedge Clk[i]) begin
last_cen[i] <= Cen[i];
if (!PREn[i]) begin //pseudo asynchronous preset
Q_current[i] <= 1'b1; //PRESET
end else if (!CLRn[i]) begin //pseudo asynchronous clear
Q_current[i] <= 1'b0; //CLEAR
end else if (!Cen[i] && last_cen[i]) begin //detect falling edge of Cen[i]
if (!J[i] && K[i]) Q_current[i] <= 1'b0; //set low
else if (J[i] && K[i]) Q_current[i] <= ~Q_current[i]; //toggle
else if (J[i] && ~K[i]) Q_current[i] <= 1'b1; //set high
// else J=K=L
// Q_current[i] <= Q_current[i]; //hold value
end
end
assign Q[i] = Q_current[i];
assign Qn[i] = ~Q_current[i];
end
endgenerate
endmodule
| 7.543154 |
module ttl_74138 #(
parameter WIDTH_OUT = 8,
WIDTH_IN = $clog2(WIDTH_OUT),
DELAY_RISE = 15,
DELAY_FALL = 15
) (
input wire Enable1_bar, //4 G2An
input wire Enable2_bar, //5 G2Bn
input wire Enable3, //6 G1
input wire [WIDTH_IN-1:0] A, //3,2,1 C,B,A
output wire [WIDTH_OUT-1:0] Y //7,9,10,11,12,13,14,15 Y[7:0]
);
//------------------------------------------------//
reg [WIDTH_OUT-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < WIDTH_OUT; i = i + 1) begin
if (!Enable1_bar && !Enable2_bar && Enable3 && i == A) computed[i] = 1'b0;
else computed[i] = 1'b1;
end
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 7.370719 |
module ttl_74138_nodly #(
parameter WIDTH_OUT = 8,
WIDTH_IN = $clog2(WIDTH_OUT)
) (
input wire Enable1_bar, //4 G2An
input wire Enable2_bar, //5 G2Bn
input wire Enable3, //6 G1
input wire [WIDTH_IN-1:0] A, //3,2,1 C,B,A
output wire [WIDTH_OUT-1:0] Y //7,9,10,11,12,13,14,15 Y[7:0]
);
//------------------------------------------------//
reg [WIDTH_OUT-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < WIDTH_OUT; i = i + 1) begin
if (!Enable1_bar && !Enable2_bar && Enable3 && i == A) computed[i] = 1'b0;
else computed[i] = 1'b1;
end
end
//------------------------------------------------//
assign Y = computed;
endmodule
| 7.559387 |
module ttl_74139 #(
parameter DELAY = 15
) (
input wire Enable_bar,
input wire [1:0] A_2D,
output wire [3:0] Y_2D
);
assign #DELAY Y_2D[0] = ~(~Enable_bar & ~A_2D[1] & ~A_2D[0]);
assign #DELAY Y_2D[1] = ~(~Enable_bar & ~A_2D[1] & A_2D[0]);
assign #DELAY Y_2D[2] = ~(~Enable_bar & A_2D[1] & ~A_2D[0]);
assign #DELAY Y_2D[3] = ~(~Enable_bar & A_2D[1] & A_2D[0]);
endmodule
| 7.83375 |
module ttl_74139_nodly (
input wire Enable_bar,
input wire [1:0] A_2D,
output wire [3:0] Y_2D
);
assign Y_2D[0] = ~(~Enable_bar & ~A_2D[1] & ~A_2D[0]);
assign Y_2D[1] = ~(~Enable_bar & ~A_2D[1] & A_2D[0]);
assign Y_2D[2] = ~(~Enable_bar & A_2D[1] & ~A_2D[0]);
assign Y_2D[3] = ~(~Enable_bar & A_2D[1] & A_2D[0]);
endmodule
| 7.289595 |
module ttl_74153 #(
parameter BLOCKS = 2,
WIDTH_IN = 4,
WIDTH_SELECT = $clog2(WIDTH_IN),
DELAY_RISE = 12,
DELAY_FALL = 15
) (
input wire [BLOCKS-1:0] Enable_bar,
input wire [WIDTH_SELECT-1:0] Select,
input wire [BLOCKS*WIDTH_IN-1:0] A_2D,
output wire [BLOCKS-1:0] Y
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i = i + 1) begin
if (!Enable_bar[i]) computed[i] = A[i][Select];
else computed[i] = 1'b0;
end
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 7.33142 |
module ttl_74155 #(parameter BLOCKS_DIFFERENT = 2, BLOCK0 = 0, BLOCK1 = 1, WIDTH_OUT = 4,
WIDTH_IN = $clog2(WIDTH_OUT), DELAY_RISE = 13, DELAY_FALL = 18)
(
input Enable1C,
input Enable1G_bar,
input Enable2C_bar,
input Enable2G_bar,
input [WIDTH_IN-1:0] A,
output [BLOCKS_DIFFERENT*WIDTH_OUT-1:0] Y_2D
);
//------------------------------------------------//
reg [WIDTH_OUT-1:0] computed [0:BLOCKS_DIFFERENT-1];
integer i;
always @(*)
begin
for (i = 0; i < WIDTH_OUT; i=i+1)
begin
if (Enable1C && !Enable1G_bar && i == A)
computed[BLOCK0][i] = 1'b0;
else
computed[BLOCK0][i] = 1'b1;
if (!Enable2C_bar && !Enable2G_bar && i == A)
computed[BLOCK1][i] = 1'b0;
else
computed[BLOCK1][i] = 1'b1;
end
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Y_2D = `PACK_ARRAY(BLOCKS_DIFFERENT, WIDTH_OUT, computed)
endmodule
| 6.865215 |
module ttl_74157 #(
parameter BLOCKS = 4,
WIDTH_IN = 2,
WIDTH_SELECT = $clog2(WIDTH_IN),
DELAY_RISE = 12,
DELAY_FALL = 13
) (
input wire Enable_bar,
input wire [WIDTH_SELECT-1:0] Select,
input wire [BLOCKS*WIDTH_IN-1:0] A_2D,
output wire [BLOCKS-1:0] Y
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i = i + 1) begin
if (!Enable_bar) computed[i] = A[i][Select];
else computed[i] = 1'b0;
end
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 7.859778 |
module ttl_74161 #(
parameter WIDTH = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire Clear_bar,
input wire Load_bar,
input wire ENT,
input wire ENP,
input wire [WIDTH-1:0] D,
input wire Clk,
output wire RCO,
output wire [WIDTH-1:0] Q
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
assign Q_next = Q_current + 1;
always @(posedge Clk or negedge Clear_bar) begin
if (!Clear_bar) begin
Q_current <= {WIDTH{1'b0}};
end else begin
if (!Load_bar) begin
Q_current <= D;
end
if (Load_bar && ENT && ENP) begin
Q_current <= Q_next;
end
end
end
// output
assign RCO_current = ENT && (&Q_current);
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) RCO = RCO_current;
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
| 7.566493 |
module ttl_74161a #(
parameter WIDTH = 4,
DELAY_RISE = 15,
DELAY_FALL = 15
) (
input wire Clear_bar, //1
input wire Load_bar, //9
input wire ENT, //7
input wire ENP, //10
input wire [WIDTH-1:0] D, //D 6, C 5, B 4, A 3
input wire Clk, //2
output wire RCO, //15
output wire [WIDTH-1:0] Q //QD 11, QC 12, QB 13, QA 14
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
initial Q_current = 4'h0;
//initial RCO_current = 1'b0;
assign Q_next = Q_current + 1;
always @(posedge Clk or negedge Clear_bar) begin
if (!Clear_bar) begin
Q_current <= {WIDTH{1'b0}};
end else begin
if (!Load_bar) begin
Q_current <= D;
end
if (Load_bar && ENT && ENP) begin
Q_current <= Q_next;
end
end
end
// output
assign RCO_current = ENT && (&Q_current);
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) RCO = RCO_current;
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
| 7.226543 |
module ttl_74161a_sync #(
parameter WIDTH = 4
) (
input wire Clk,
input wire Cen,
input wire Clear_bar, //1
input wire Load_bar, //9
input wire ENT, //7
input wire ENP, //10
input wire [WIDTH-1:0] D, //D 6, C 5, B 4, A 3
output wire RCO, //15
output wire [WIDTH-1:0] Q //QD 11, QC 12, QB 13, QA 14
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
reg last_cen;
initial last_cen = 1'b1;
initial Q_current = {WIDTH{1'b0}};
assign Q_next = Q_current + {{(WIDTH - 1) {1'b0}}, 1'b1};
always @(posedge Clk) begin
last_cen <= Cen;
if (!Clear_bar) begin
Q_current <= {WIDTH{1'b0}};
end
else if (Cen && !last_cen) //detect rising edge of Cen
begin
if (!Load_bar) begin
Q_current <= D;
end
if (Load_bar && ENT && ENP) begin
Q_current <= Q_next;
end
end
end
assign RCO_current = ENT && (&Q_current);
// output
assign RCO = RCO_current;
assign Q = Q_current;
endmodule
| 8.145892 |
module ttl_74161_sync #(
parameter WIDTH = 4
) (
input wire Clk, //2
input wire Clear_bar, //1 ASYNCHRONOUS
input wire Load_bar, //9
input wire ENT, //7
input wire ENP, //10
input wire [WIDTH-1:0] D, //D 6, C 5, B 4, A 3
input wire Cen, //Clock enable signal and trigger
output wire RCO, //15
output wire [WIDTH-1:0] Q //QD 11, QC 12, QB 13, QA 14
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
reg last_cen;
reg load_reg;
initial Q_current = {WIDTH{1'b0}};
assign Q_next = Q_current + {{(WIDTH - 1) {1'b0}}, 1'b1};
always @(posedge Clk) begin
last_cen <= Cen;
if (!Clear_bar) begin //pseudo asynchronous clear
Q_current <= {WIDTH{1'b0}};
end else if (Cen && !last_cen) begin //rising edge
if (!Load_bar) begin
Q_current <= D;
end else if (Load_bar && ENT && ENP) begin
Q_current <= Q_next;
end
end
end
// output
assign RCO_current = ENT && (&Q_current);
//------------------------------------------------//
assign RCO = RCO_current;
assign Q = Q_current;
endmodule
| 7.692636 |
module ttl_74163a #(
parameter WIDTH = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire Clear_bar, //1
input wire Load_bar, //9
input wire ENT, //7
input wire ENP, //10
input wire [WIDTH-1:0] D, //D 6, C 5, B 4, A 3
input wire Clk, //2
output wire RCO, //15
output wire [WIDTH-1:0] Q //QD 11, QC 12, QB 13, QA 14
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
initial Q_current = 4'h0;
//initial RCO_current = 1'b0;
assign Q_next = Q_current + 1;
always @(posedge Clk) begin
if (!Clear_bar) begin
Q_current <= {WIDTH{1'b0}};
end else begin
if (!Load_bar) begin
Q_current <= D;
end
if (Load_bar && ENT && ENP) begin
Q_current <= Q_next;
end
end
end
// output
assign RCO_current = ENT && (&Q_current);
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) RCO = RCO_current;
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
| 7.111494 |
module ttl_74163a_sync #(
parameter WIDTH = 4
) (
input wire Clk, //2
input wire Clear_bar, //1 SYNCHRONOUS
input wire Load_bar, //9
input wire ENT, //7
input wire ENP, //10
input wire [WIDTH-1:0] D, //D 6, C 5, B 4, A 3
input wire Cen, //Clock enable signal and trigger
output wire RCO, //15
output wire [WIDTH-1:0] Q //QD 11, QC 12, QB 13, QA 14
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
reg last_cen;
reg load_reg;
initial last_cen = 1'b1;
initial Q_current = {WIDTH{1'b0}};
assign Q_next = Q_current + {{(WIDTH - 1) {1'b0}}, 1'b1};
always @(posedge Clk) begin
last_cen <= Cen;
if (Cen && !last_cen) begin //rising edge
if (!Clear_bar) begin //synchronous clear
Q_current <= {WIDTH{1'b0}};
end else begin
if (!Load_bar) begin
Q_current <= D;
end else if (Load_bar && ENT && ENP) begin
Q_current <= Q_next;
end
end
end
end
// output
assign RCO_current = ENT && (&Q_current);
assign RCO = RCO_current;
assign Q = Q_current;
endmodule
| 7.550143 |
module ttl_74164_sync (
input wire A,
B, //serial input data
input wire Reset_n,
input wire clk,
//(*direct_enable*) input wire Cen,
input wire Cen,
input wire MRn, //Master Reset (async)
output reg Q0,
Q1,
Q2,
Q3,
Q4,
Q5,
Q6,
Q7
);
wire serdata;
assign serdata = A & B;
reg last_cen;
always @(posedge clk) begin
if (!Reset_n) begin
Q0 <= 1'b0;
Q1 <= 1'b0;
Q2 <= 1'b0;
Q3 <= 1'b0;
Q4 <= 1'b0;
Q5 <= 1'b0;
Q6 <= 1'b0;
Q7 <= 1'b0;
last_cen <= 1'b1;
end else begin
last_cen <= Cen;
if (!MRn) begin
Q0 <= 1'b0;
Q1 <= 1'b0;
Q2 <= 1'b0;
Q3 <= 1'b0;
Q4 <= 1'b0;
Q5 <= 1'b0;
Q6 <= 1'b0;
Q7 <= 1'b0;
end else if (Cen && !last_cen) begin
Q0 <= serdata;
Q1 <= Q0;
Q2 <= Q1;
Q3 <= Q2;
Q4 <= Q3;
Q5 <= Q4;
Q6 <= Q5;
Q7 <= Q6;
end
end
end
endmodule
| 6.503079 |
module ttl_74169_sync (
input wire Reset_n,
input wire clk,
input wire cen,
input wire direction, // 1 = Up, 0 = Down
input wire load_n, // 1 = Count, 0 = Load
input wire ent_n,
input wire enp_n,
input wire [3:0] P,
output wire rco_n, // Ripple Carry-out (RCO)
output wire [3:0] Q // 4-bit output
);
//reg rco = 1'b0;
reg [3:0] count = 0;
reg last_cen;
always @(posedge clk) begin
if (!Reset_n) begin
count <= 4'h0;
last_cen <= 1'b1;
end else begin
last_cen <= cen;
if (cen && !last_cen) begin //detect rising edge
if (~load_n) begin
count <= P;
end
else if (~ent_n & ~enp_n) // Count only if both enable signals are active (low)
begin
if (direction) begin
// Counting up
if (count == 4'd15) count <= 4'd0;
else count <= count + 1;
end else begin
// Counting down
if (count == 4'd0) count <= 4'd15;
else count <= count - 1;
end
end
end
end
end
assign Q = count;
//assign rco_n = ~rco;
assign rco_n = !load_n ? 1'b0 : ~((&count) & ~ent_n);
endmodule
| 7.384956 |
module ttl_74174 #(
parameter DELAY_RISE = 20,
DELAY_FALL = 21
) (
input wire Clk,
input wire RESETn,
input wire [5:0] D,
output wire [5:0] Q
);
//------------------------------------------------//
reg [5:0] Q_current; // = 6'h00;
//initial Q_current = 6'h00; //supposition
always @(posedge Clk or negedge RESETn) begin
if (!RESETn) Q_current <= 6'h00;
else begin
Q_current <= D;
end
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
| 6.677053 |
module ttl_74174_sync #(
parameter BLOCKS = 6
) (
input wire Clk,
//(*direct_enable*) input wire Cen,
input wire Cen,
input wire Clr_n,
input wire [BLOCKS-1:0] D,
output wire [BLOCKS-1:0] Q
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
reg last_cen;
initial last_cen = 1'b1;
initial Q_current = {(BLOCKS) {1'b0}};
always @(posedge Clk) begin
last_cen <= Cen;
if (!Clr_n) //pseudo asynchronous clear
Q_current <= {(BLOCKS) {1'b0}};
else
if (Cen && !last_cen) //detect rising edge of Cen
begin
Q_current <= D;
end else begin
Q_current <= Q_current;
end
end
//------------------------------------------------//
assign Q = Q_current;
endmodule
| 6.699463 |
module ttl_74175_sync (
input wire Reset_n,
input wire Clk,
//(*direct_enable*) input wire Cen,
input wire Cen,
input wire Clr_n,
input wire [3:0] D,
output wire [3:0] Q,
output wire [3:0] Q_bar
);
//------------------------------------------------//
reg [3:0] Q_current;
reg last_cen;
initial Q_current = 4'h0; //supposition
always @(posedge Clk) begin
if (!Reset_n) begin
Q_current <= 4'h0;
last_cen <= 1'b1;
end else begin
last_cen <= Cen;
if (!Clr_n) Q_current <= 4'h0;
else if (Cen && !last_cen) //detect rising edge of Cen
Q_current <= D;
else Q_current <= Q_current;
end
end
//------------------------------------------------//
assign Q = Q_current;
assign Q_bar = ~Q_current;
endmodule
| 6.840748 |
module ttl_74194 #(
parameter DELAY_RISE = 12,
DELAY_FALL = 15
) (
input wire CR_n,
input wire CP,
input wire S0,
S1,
input wire Dsl,
Dsr,
input wire D0,
D1,
D2,
D3,
output wire Q0,
Q1,
Q2,
Q3
);
reg [0:3] q_reg = 4'b0000;
wire [1:0] s_reg;
assign s_reg = {S1, S0};
always @(posedge CP or negedge CR_n) begin //WARNING: changing from posedge CR_n
if (!CR_n) begin
q_reg <= 4'b0000;
end else begin
case (s_reg)
2'b00: q_reg <= q_reg;
2'b01: q_reg <= {Dsr, q_reg[0:2]}; //Shift right
2'b10: q_reg <= {q_reg[1:3], Dsl}; //Shift left
2'b11: q_reg <= {D0, D1, D2, D3};
default: q_reg <= 4'b0000;
endcase
end
end
assign #(DELAY_RISE, DELAY_FALL) Q0 = q_reg[0];
assign #(DELAY_RISE, DELAY_FALL) Q1 = q_reg[1];
assign #(DELAY_RISE, DELAY_FALL) Q2 = q_reg[2];
assign #(DELAY_RISE, DELAY_FALL) Q3 = q_reg[3];
endmodule
| 7.591104 |
module ttl_74194_sync (
input wire clk,
input wire cen, //CP
input wire CR_n,
input wire S0,
S1,
input wire Dsl,
Dsr,
input wire D0,
D1,
D2,
D3,
output wire Q0,
Q1,
Q2,
Q3
);
reg [3:0] q_reg;
wire [1:0] s_reg;
reg last_cen;
initial q_reg = 4'h0;
initial last_cen = 1'b1;
assign s_reg = {S1, S0};
always @(posedge clk) begin
last_cen <= cen;
if (!CR_n) begin
q_reg <= 4'b0000;
end else if (cen && !last_cen) begin //detect rising edge of Cen
case (s_reg)
2'b00: q_reg <= q_reg;
2'b01: q_reg <= {q_reg[2:0], Dsr}; //Shift right
2'b10: q_reg <= {Dsl, q_reg[3:1]}; //Shift left
2'b11: q_reg <= {D3, D2, D1, D0};
default: q_reg <= 4'b0000;
endcase
end
end
assign Q0 = q_reg[0];
assign Q1 = q_reg[1];
assign Q2 = q_reg[2];
assign Q3 = q_reg[3];
endmodule
| 7.141089 |
module
//
`timescale 1ns/10ps
module TTL_7421 (
input A1, B1, C1, D1, // Unit A
output Y1,
input A2, B2, C2, D2, // Unit B
output Y2
);
assign #(0:8:15, 0:10:20) Y1 = A1 & B1 & C1 & D1;
assign #(0:8:15, 0:10:20) Y2 = A2 & B2 & C2 & D2;
endmodule
| 6.662614 |
module ttl_74245 #(parameter DELAY_RISE = 12, DELAY_FALL = 12)
module ttl_74244 #(parameter DELAY_RISE = 12, DELAY_FALL = 12)
(
input wire G1n,
input wire G2n,
input wire [3:0] A1,
input wire [3:0] A2,
output wire [3:0] Y1,
output wire [3:0] Y2
);
assign #(DELAY_RISE, DELAY_FALL) Y1 = (!G1n) ? A1 : 4'bzzzz;
assign #(DELAY_RISE, DELAY_FALL) Y2 = (!G2n) ? A2 : 4'bzzzz;
endmodule
| 7.13794 |
module ttl_74245 #(
parameter DELAY_RISE = 12,
DELAY_FALL = 12
) (
input wire DIR,
input wire Enable_bar,
inout wire [7:0] A,
inout wire [7:0] B
);
assign #(DELAY_RISE, DELAY_FALL) A = (Enable_bar || DIR) ? 8'hzz : B; //B->A
assign #(DELAY_RISE, DELAY_FALL) B = (Enable_bar || !DIR) ? 8'hzz : A; //A->B
endmodule
| 7.462193 |
module ttl_74245_2dly #(
parameter DELAY_AB = 12,
DELAY_BA = 12
) (
input wire DIR,
input wire Enable_bar,
inout wire [7:0] A,
inout wire [7:0] B
);
assign #DELAY_BA A = (Enable_bar || DIR) ? 8'hzz : B; //B->A
assign #DELAY_AB B = (Enable_bar || !DIR) ? 8'hzz : A; //A->B
endmodule
| 7.03738 |
module ttl_74257 #(
parameter BLOCKS = 4,
WIDTH_IN = 2,
WIDTH_SELECT = $clog2(WIDTH_IN),
DELAY_RISE = 12,
DELAY_FALL = 13
) (
input wire Enable_bar, //0 enable logic output, 1 hi-Z output
input wire [WIDTH_SELECT-1:0] Select, //0 select A, 1 select B
input wire [BLOCKS*WIDTH_IN-1:0] A_2D,
output wire [BLOCKS-1:0] Y
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i = i + 1) begin
if (!Enable_bar) computed[i] = A[i][Select];
else computed[i] = 1'bz; //if Enable_bar output = Hi-Z.
end
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;
endmodule
| 7.827827 |
module ttl_74257_noHiZout #(
parameter BLOCKS = 4,
WIDTH_IN = 2,
WIDTH_SELECT = $clog2(WIDTH_IN)
) (
input wire Enable_bar, //0 enable logic output, 1 hi-Z output
input wire [WIDTH_SELECT-1:0] Select, //0 select A, 1 select B
input wire [BLOCKS*WIDTH_IN-1:0] A_2D,
output wire [BLOCKS-1:0] Y
);
//------------------------------------------------//
wire [WIDTH_IN-1:0] A[0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;
always @(*) begin
for (i = 0; i < BLOCKS; i = i + 1) begin
if (!Enable_bar) computed[i] = A[i][Select];
else computed[i] = 1'b1; //if Enable_bar output = 1.
end
end
//------------------------------------------------//
`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign Y = computed;
endmodule
| 8.288341 |
module ttl_74273 #(
parameter DELAY_RISE = 12,
DELAY_FALL = 13
) (
input wire Clk,
input wire RESETn,
input wire [7:0] D,
output wire [7:0] Q
);
//------------------------------------------------//
reg [7:0] Q_current;
// initial begin
// Q_current <= 8'h00;
// end//supposition
always @(posedge Clk or negedge RESETn) begin
if (!RESETn) Q_current <= 0;
else begin
Q_current <= D;
end
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
| 6.554858 |
module ttl_74283 #(
parameter WIDTH = 4
) (
input wire [WIDTH-1:0] A,
input wire [WIDTH-1:0] B,
input wire C_in,
output wire [WIDTH-1:0] Sum,
output wire C_out
);
//------------------------------------------------//
reg [WIDTH-1:0] Sum_computed;
reg C_computed;
always @(*) begin
{C_computed, Sum_computed} = {1'b0, A} + {1'b0, B} + C_in;
end
//------------------------------------------------//
//from SN74LS283 Datasheet
assign #12 Sum = Sum_computed;
assign #15 C_out = C_computed;
endmodule
| 7.398786 |
module ttl_74283_nodly #(
parameter WIDTH = 4
) (
input wire [WIDTH-1:0] A,
input wire [WIDTH-1:0] B,
input wire C_in,
output wire [WIDTH-1:0] Sum,
output wire C_out
);
//------------------------------------------------//
reg [WIDTH-1:0] Sum_computed;
reg C_computed;
always @(*) begin
{C_computed, Sum_computed} = {1'b0, A} + {1'b0, B} + C_in;
end
//------------------------------------------------//
//from SN74LS283 Datasheet
assign Sum = Sum_computed;
assign C_out = C_computed;
endmodule
| 8.052166 |
module ttl_74298 (
input wire WS,
input wire clk,
input wire [3:0] A,
input wire [3:0] B,
output wire [3:0] Q
);
wire WSn;
wire WSnn;
wire clkn;
assign WSn = ~WS;
assign WSnn = ~WSn;
assign clkn = ~clk;
wire [3:0] andA;
wire [3:0] andB;
wire [3:0] norAB;
wire [3:0] not_norAB;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : ls298_gen
assign andA[i] = A[i] & WSn;
assign andB[i] = B[i] & WSnn;
assign norAB[i] = ~(andA[i] | andB[i]);
assign not_norAB[i] = ~norAB[i];
SR_FF sr_ff_inst (
.S (not_norAB[i]),
.R (norAB[i]),
.clk(clkn),
.Q (Q[i])
);
end
endgenerate
endmodule
| 6.789049 |
module SR_FF #(
parameter DELAY = 18
) (
input wire S,
input wire R,
input wire clk,
output wire Q,
output wire Qn
);
reg Qr;
always @(posedge clk) begin
case ({
S, R
})
2'b00: Qr <= Qr;
2'b01: Qr <= 1'b0;
2'b10: Qr <= 1'b1;
2'b11: Qr <= 1'bx;
endcase
end
assign #DELAY Q = Qr;
assign #DELAY Qn = ~Qr;
endmodule
| 6.914922 |
module ttl_74298_sync (
input wire VIDEO_RSTn,
input wire clk,
input wire Cen,
input wire WS,
input wire [3:0] A,
input wire [3:0] B,
output wire [3:0] Q
);
wire WSn;
wire WSnn;
assign WSn = ~WS;
assign WSnn = ~WSn;
wire [3:0] andA;
wire [3:0] andB;
wire [3:0] norAB;
wire [3:0] not_norAB;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : ls928_gen
assign andA[i] = A[i] & WSn;
assign andB[i] = B[i] & WSnn;
assign norAB[i] = ~(andA[i] | andB[i]);
assign not_norAB[i] = ~norAB[i];
SR_FF_sync u0 (
.VIDEO_RSTn(VIDEO_RSTn),
.clk(clk),
.Cen(Cen),
.S(not_norAB[i]),
.R(norAB[i]),
.Q(Q[i])
); //dont uses clkn, detects falling edge of Cen
end
endgenerate
endmodule
| 7.557154 |
module SR_FF_sync //detects falling edge of Cen
(
input wire VIDEO_RSTn,
input wire clk,
input wire Cen,
input wire S,
input wire R,
output wire Q,
output wire Qn
);
reg Qr;
reg last_cen;
always @(posedge clk) begin
if (!VIDEO_RSTn) begin
Qr <= 1'b0;
last_cen <= 1'b1;
end else begin
last_cen <= Cen;
if (!Cen && last_cen) begin //detects falling edge on Cen
case ({
S, R
})
2'b00: Qr <= Qr;
2'b01: Qr <= 1'b0;
2'b10: Qr <= 1'b1;
2'b11: Qr <= 1'bx;
endcase
end
end
end
assign Q = Qr;
assign Qn = ~Qr;
endmodule
| 7.59203 |
module
//
`timescale 1ns/10ps
module TTL_7430 (
input A, B, C, D, E, F, G, H, // Unit A
output Y
);
not #(0:13:22, 0:8:15) (Y, A & B & C & D & E & F & G & H);
endmodule
| 6.662614 |
module
//
`timescale 1ns/10ps
module TTL_7432 (
input A1, B1, // Unit A
output Y1,
input A2, B2, // Unit B
output Y2,
input A3, B3, // Unit C
output Y3,
input A4, B4, // Unit D
output Y4
);
or #(0:14:22, 0:14:22) (Y1, A1, B1);
or #(0:14:22, 0:14:22) (Y2, A2, B2);
or #(0:14:22, 0:14:22) (Y3, A3, B3);
or #(0:14:22, 0:14:22) (Y4, A4, B4);
endmodule
| 6.662614 |
module ttl_7474 #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire [BLOCKS-1:0] Clear_bar,
input wire [BLOCKS-1:0] Preset_bar,
input wire [BLOCKS-1:0] D,
input wire [BLOCKS-1:0] Clk,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Q_bar
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current = 0;
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1) begin : gen_blocks
//initial Q_current[i] = 1'b0; //supposition
always @(posedge Clk[i] or negedge Clear_bar or negedge Preset_bar[i]) begin
if (!Clear_bar[i]) Q_current[i] <= 1'b0;
else if (!Preset_bar[i]) Q_current[i] <= 1'b1;
else begin
Q_current[i] <= D[i];
end
end
end
endgenerate
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
assign #(DELAY_RISE, DELAY_FALL) Q_bar = ~Q_current;
endmodule
| 6.930349 |
module ttl_7474_pre #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input wire [BLOCKS-1:0] Preset_bar,
input wire [BLOCKS-1:0] D,
input wire [BLOCKS-1:0] Clk,
output wire [BLOCKS-1:0] Q,
output wire [BLOCKS-1:0] Q_bar
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1) begin : gen_blocks
initial Q_current[i] = 1'b0; //supposition
always @(posedge Clk[i] or negedge Preset_bar[i]) begin
if (!Preset_bar[i]) Q_current[i] <= 1'b1;
else begin
Q_current[i] <= D[i];
end
end
end
endgenerate
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
assign #(DELAY_RISE, DELAY_FALL) Q_bar = ~Q_current;
endmodule
| 6.64138 |
module
//
`timescale 1ns/10ps
// #(0:13:22, 0:8:15)
module jkff(input preset, input clear, input clk, input j, input k, output reg q, output qnot);
// #(0:16:25, 0:25:40)
assign qnot = ~q;
always @(clear or preset) begin
if (!clear) begin
q <= #40 1'b0;
end else if (!preset) begin
q <= #40 1'b1;
end
end
always @(negedge clk) begin
case ({j, k})
2'b00: q <= #40 q;
2'b01: q <= #40 1'b0;
2'b10: q <= #40 1'b1;
2'b11: q <= #40 ~q;
endcase
end
endmodule
| 6.662614 |
module dff (
input d,
input preset,
input clear,
input clk,
output q
);
reg q;
initial q = 0;
always @(posedge clk or posedge clear or posedge preset) begin
if (preset) #7 q <= 1;
else if (clear) #7 q <= 0;
else #6 q <= d;
end
endmodule
| 7.174483 |
module TTL_74LS244 (
input _G1,
input [3:0] A1,
output [3:0] Y1,
input _G2,
input [3:0] A2,
output [3:0] Y2,
input VCC,
input GND
);
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : BUFF
TTL_74LS244_buff buff1 (
._g(_G1),
.a (A1[i]),
.y (Y1[i])
);
TTL_74LS244_buff buff2 (
._g(_G2),
.a (A2[i]),
.y (Y2[i])
);
end
endgenerate
endmodule
| 7.429127 |
module TTL_74LS373_DFF (
input d,
input _oe,
input le,
output o
);
reg o_hold;
bufif0 (o, o_hold, _oe);
always @(d) if (le) #10 o_hold <= d;
endmodule
| 6.786794 |
module TTL_74LS373 (
input _OE,
output [7:0] O,
input [7:0] I,
input LE,
input VCC,
input GND
);
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : DFF
TTL_74LS373_DFF dff (
.d (I[i]),
._oe(_OE),
.le (LE),
.o (O[i])
);
end
endgenerate
endmodule
| 8.690078 |
module TTL_74LS93_toggle (
input _t,
input _r,
output o
);
reg o;
always @(negedge _r or negedge _t)
if (_r == 0) o <= 1'b0;
else if (_t == 0) begin
if (o == 1'b0) o <= 1'b1;
else o <= 1'b0;
end
endmodule
| 6.835885 |
module ls74 //not used
(
input n_pre1,
n_pre2,
input n_clr1,
n_clr2,
input clk1,
clk2,
input d1,
d2,
output reg q1,
q2,
output n_q1,
n_q2
);
always @(posedge clk1 or negedge n_pre1 or negedge n_clr1) begin
if (!n_pre1) q1 <= 1;
else if (!n_clr1) q1 <= 0;
else q1 <= d1;
end
assign n_q1 = ~q1;
always @(posedge clk2 or negedge n_pre2 or negedge n_clr2) begin
if (!n_pre2) q2 <= 1;
else if (!n_clr2) q2 <= 0;
else q2 <= d2;
end
assign n_q2 = ~q2;
endmodule
| 7.057074 |
module ls139 //used
(
input a,
input b,
input n_g,
output [3:0] y
);
assign y = (!n_g && !a && !b) ? 4'b1110:
(!n_g && a && !b) ? 4'b1101:
(!n_g && !a && b) ? 4'b1011:
(!n_g && a && b) ? 4'b0111:
4'b1111;
endmodule
| 6.504395 |
module ttl_74283 #(
parameter WIDTH = 4,
DELAY_RISE = 0,
DELAY_FALL = 0
) //used
(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input c_in,
output [WIDTH-1:0] sum,
output c_out
);
//------------------------------------------------//
reg [WIDTH-1:0] Sum_computed;
reg C_computed;
always @(*) begin
{C_computed, Sum_computed} = {1'b0, a} + {1'b0, b} + c_in;
end
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) sum = Sum_computed;
assign #(DELAY_RISE, DELAY_FALL) c_out = C_computed;
endmodule
| 7.398786 |
module ls138x ( //used
input [2:0] A,
input nE1,
input nE2,
input E3,
output [7:0] Y
);
reg [7:0] Q;
wire trigger;
assign trigger = !nE1 & !nE2 & E3;
always @(*) begin
if (trigger) begin
case (A)
3'b000: Q[7:0] = 8'b11111110;
3'b001: Q[7:0] = 8'b11111101;
3'b010: Q[7:0] = 8'b11111011;
3'b011: Q[7:0] = 8'b11110111;
3'b100: Q[7:0] = 8'b11101111;
3'b101: Q[7:0] = 8'b11011111;
3'b110: Q[7:0] = 8'b10111111;
3'b111: Q[7:0] = 8'b01111111;
//default: Q[7:0]=8'b11111111;
endcase
end else begin //
Q[7:0] = 8'b11111111;
end
end
assign Y = Q;
endmodule
| 7.281695 |
module ttl_7474 #(
parameter BLOCKS = 2,
DELAY_RISE = 0,
DELAY_FALL = 0
) (
input [BLOCKS-1:0] n_pre,
input [BLOCKS-1:0] n_clr,
input [BLOCKS-1:0] d,
input [BLOCKS-1:0] clk,
output [BLOCKS-1:0] q,
output [BLOCKS-1:0] n_q
);
//------------------------------------------------//
reg [BLOCKS-1:0] Q_current;
reg [BLOCKS-1:0] Preset_bar_previous;
generate
genvar i;
for (i = 0; i < BLOCKS; i = i + 1) begin : gen_blocks
always @(posedge clk[i] or negedge n_clr[i]) begin
if (!n_clr[i]) Q_current[i] <= 1'b0;
else if (!n_pre[i] && Preset_bar_previous[i]) // falling edge has occurred
Q_current[i] <= 1'b1;
else begin
Q_current[i] <= d[i];
Preset_bar_previous[i] <= n_pre[i];
end
end
end
endgenerate
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) q = Q_current;
assign #(DELAY_RISE, DELAY_FALL) n_q = ~Q_current;
endmodule
| 6.930349 |
module mux4_1 (
input EN_n,
input A,
B,
input D0,
D1,
D2,
D3,
output Y
);
/* KEEP THE OUTPUT VALUE */
wire [1:0] S;
reg Y_reg;
assign S = {B, A};
always @(*) begin
if (EN_n) Y_reg = 1'bz;
else
case (S)
2'b00: Y_reg <= D0;
2'b01: Y_reg <= D1;
2'b10: Y_reg <= D2;
2'b11: Y_reg <= D3;
endcase
end
assign Y = Y_reg;
endmodule
| 7.631991 |
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