code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mux4_1n (
input EN_n,
input A,
B,
input D0,
D1,
D2,
D3,
output Y
);
/* KEEP THE OUTPUT VALUE */
wire [1:0] S;
reg Y_reg;
assign S = {B, A};
always @(*) begin
if (EN_n) Y_reg <= 1'b0;
else
case (S)
2'b00: Y_reg <= D0;
2'b01: Y_reg <= D1;
2'b10: Y_reg <= D2;
2'b11: Y_reg <= D3;
endcase
end
assign Y = Y_reg;
endmodule
| 7.589537 |
module mux4_2n (
input EN_n,
input A,
B,
input [1:0] D0,
D1,
D2,
D3,
output [1:0] Y
);
/* KEEP THE OUTPUT VALUE */
wire [1:0] S;
reg [1:0] Y_reg;
assign S = {B, A};
always @(*) begin
if (EN_n) Y_reg <= 2'b00;
else
case (S)
2'b00: Y_reg <= D0;
2'b01: Y_reg <= D1;
2'b10: Y_reg <= D2;
2'b11: Y_reg <= D3;
endcase
end
assign Y = Y_reg;
endmodule
| 7.911073 |
module mux4_4n (
input EN_n,
input A,
B,
input [3:0] D0,
D1,
D2,
D3,
output [3:0] Y
);
/* KEEP THE OUTPUT VALUE */
wire [1:0] S;
reg [3:0] Y_reg;
assign S = {B, A};
always @(*) begin
if (EN_n) Y_reg <= 4'b0000;
else
case (S)
2'b00: Y_reg <= D0;
2'b01: Y_reg <= D1;
2'b10: Y_reg <= D2;
2'b11: Y_reg <= D3;
endcase
end
assign Y = Y_reg;
endmodule
| 8.012155 |
module mux4_1x (
input EN_n,
input DIS_n,
input A,
B,
input D0,
D1,
D2,
D3,
output Y
);
/* KEEP THE OUTPUT VALUE */
wire [1:0] S;
reg Y_reg;
reg active;
always @(EN_n, DIS_n) begin
if (!EN_n & DIS_n) active = 1;
else if (!DIS_n) active = 0;
end
assign S = {B, A};
always @(*) begin
if (!active) Y_reg <= 1'b0;
else
case (S)
2'b00: Y_reg <= D0;
2'b01: Y_reg <= D1;
2'b10: Y_reg <= D2;
2'b11: Y_reg <= D3;
endcase
end
assign Y = Y_reg;
endmodule
| 7.362619 |
module TTT_Decoder (
input [3:0] POS_SW,
input ENABLE,
output wire [8:0] P_EN
);
reg [8:0] temp;
assign P_EN = (ENABLE == 1'b1) ? temp : 9'b0;
always @(*) begin
case (POS_SW)
4'd1: temp <= 9'b000000001; // 0001
4'd2: temp <= 9'b000000010; // 0010
4'd3: temp <= 9'b000000100; // 0011
4'd4: temp <= 9'b000001000; // 0100
4'd5: temp <= 9'b000010000; // 0101
4'd6: temp <= 9'b000100000; // 0110
4'd7: temp <= 9'b001000000; // 0111
4'd8: temp <= 9'b010000000; // 1000
4'd9: temp <= 9'b100000000; // 1001
default: temp <= 9'b000000000; //ANYTHING ELSE WILL NOT BE ASSIGNED TO ANY CELL
endcase
end
endmodule
| 7.141617 |
module TTT_Decoder_TB;
reg [3:0] POS_SW;
reg ENABLE;
wire [8:0] P_EN;
TTT_Decoder UUT (
POS_SW,
ENABLE,
P_EN
);
initial begin
#500 $finish;
end
initial begin
ENABLE = 0;
POS_SW = 0;
#10 POS_SW = 4'd1;
#10 POS_SW = 4'd2;
#10 POS_SW = 4'd3;
#10 POS_SW = 4'd4;
#10 POS_SW = 4'd5;
#10 POS_SW = 4'd6;
#10 POS_SW = 4'd7;
#10 POS_SW = 4'd8;
#10 POS_SW = 4'd9;
#10 POS_SW = 0;
#10 ENABLE = 1'b1;
#10 POS_SW = 4'd1;
#10 POS_SW = 4'd2;
#10 POS_SW = 4'd3;
#10 POS_SW = 4'd4;
#10 POS_SW = 4'd5;
#10 POS_SW = 4'd6;
#10 POS_SW = 4'd7;
#10 POS_SW = 4'd8;
#10 POS_SW = 4'd9;
end
endmodule
| 6.593233 |
module main; //: root_module
wire w4; //: /sn:0 {0}(161,113)(176,113){1}
wire [7:0] w3; //: /sn:0 {0}(#:161,96)(176,96){1}
wire [7:0] w0; //: /sn:0 {0}(#:161,88)(176,88){1}
wire w1; //: /sn:0 {0}(161,121)(176,121){1}
wire w2; //: /sn:0 {0}(161,105)(176,105){1}
wire w5; //: /sn:0 {0}(161,129)(176,129){1}
//: enddecls
TTY g0 (
.TD (w0),
.DSR(w1),
.RTS(w2),
.RD (w3),
.CTS(w4),
.DTR(w5)
); //: @(124, 109) /symbol:688686768 /sn:0 /w:[ 0 0 0 0 0 0 ]
endmodule
| 6.5859 |
module TTY (
TD,
RD,
RTS,
CTS,
DSR,
DTR
);
input CTS, DSR;
input [7:0] RD;
output [7:0] TD;
output RTS, DTR;
reg _RTS, _DTR;
reg [7:0] data;
initial begin
_RTS = 0;
data = 0;
_DTR = 0;
end
initial $tkg$post("TTY", "%m");
always begin
_DTR = 1'b0;
@(posedge DSR);
#10;
_DTR = 1'b1;
// $tkg$exec("TTY::data %m %d", RD);
$tkg$send("%m.RD", RD);
#10;
@(negedge DSR);
#10;
end
always begin
@(negedge CTS);
#10;
data = $tkg$recv("%m.TD");
#10;
_RTS = 1'b1;
@(posedge CTS);
#10;
_RTS = 1'b0;
end
assign TD = data;
assign RTS = _RTS;
assign DTR = _DTR;
endmodule
| 7.477042 |
module tt_formal;
// Signals
// -------
// DUT signals
wire [37:0] io_in;
wire [37:0] io_out;
wire [37:0] io_oeb;
wire user_clock2;
wire k_zero;
wire k_one;
// DUT
// ---
tt_top #(
.N_PADS(38),
.G_X (16),
.G_Y (24),
.N_IO (8),
.N_O (8),
.N_I (10)
) dut_I (
.io_in (io_in),
.io_out (io_out),
.io_oeb (io_oeb),
.user_clock2(user_clock2),
.k_zero (k_zero),
.k_one (k_one)
);
/*
IO in/out/oeb is split like this:
io_oeb is 'output enable bar': low means a pin is an output
37:32 control
31:24 user in/out
23:16 user out
15:06 user in
05:04 clock
*/
// loop back dedicated outs to ins
assign io_in[15:8] = io_out[23:16];
// loop back bidirectional outs to ins, depending on output enable
assign io_in[31:24] = io_out[31:24] & (~io_oeb[31:24]);
endmodule
| 6.601277 |
module tt_pg_vdd_2 (
`ifdef USE_POWER_PINS
input wire VGND,
input wire VPWR,
output wire GPWR,
`endif
input wire ctrl
);
endmodule
| 7.231902 |
module tt_prim_buf #(
parameter integer HIGH_DRIVE = 0
) (
input wire a,
output wire z
);
generate
if (HIGH_DRIVE) begin
sky130_fd_sc_hd__buf_8 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB(1'b1),
.VNB(1'b0),
`endif
.A(a),
.X(z)
);
end else begin
sky130_fd_sc_hd__buf_2 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB(1'b1),
.VNB(1'b0),
`endif
.A(a),
.X(z)
);
end
endgenerate
endmodule
| 6.998011 |
module tt_prim_inv #(
parameter integer HIGH_DRIVE = 0
) (
input wire a,
output wire z
);
generate
if (HIGH_DRIVE) begin
sky130_fd_sc_hd__bufinv_8 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB(1'b1),
.VNB(1'b0),
`endif
.A(a),
.Y(z)
);
end else begin
sky130_fd_sc_hd__inv_2 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB(1'b1),
.VNB(1'b0),
`endif
.A(a),
.Y(z)
);
end
endgenerate
endmodule
| 7.01895 |
module tt_prim_tbuf #(
parameter integer HIGH_DRIVE = 0
) (
input wire a,
input wire tx,
output wire z
);
generate
if (HIGH_DRIVE) begin
sky130_fd_sc_hd__ebufn_8 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB (1'b1),
.VNB (1'b0),
`endif
.A (a),
.TE_B(tx),
.Z (z)
);
end else begin
sky130_fd_sc_hd__ebufn_1 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB (1'b1),
.VNB (1'b0),
`endif
.A (a),
.TE_B(tx),
.Z (z)
);
end
endgenerate
endmodule
| 6.580779 |
module tt_prim_zbuf #(
parameter integer HIGH_DRIVE = 0
) (
input wire a,
input wire e,
output wire z
);
generate
if (HIGH_DRIVE) begin
wire l;
sky130_fd_sc_hd__and2_2 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB(1'b1),
.VNB(1'b0),
`endif
.A(a),
.B(e),
.X(l)
);
sky130_fd_sc_hd__buf_8 cell1_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB(1'b1),
.VNB(1'b0),
`endif
.A(l),
.X(z)
);
end else begin
sky130_fd_sc_hd__and2_2 cell0_I (
`ifdef WITH_POWER
.VPWR(1'b1),
.VGND(1'b0),
.VPB(1'b1),
.VNB(1'b0),
`endif
.A(a),
.B(e),
.X(z)
);
end
endgenerate
endmodule
| 6.519112 |
module tt_top_tb;
localparam integer MUX_ID = 12;
localparam integer BLK_ID = 0;
// Signals
// -------
// DUT signals
wire [37:0] io_in;
wire [37:0] io_out;
wire [37:0] io_oeb;
wire user_clock2;
wire k_zero;
wire k_one;
// Control
wire ctrl_sel_rst_n;
reg ctrl_sel_inc;
reg ctrl_ena;
reg [ 9:0] cur_core;
reg [ 3:0] um_rst_cnt;
// Clocks
reg clk_a = 1'b0;
reg clk_b = 1'b0;
reg rst_n = 1'b0;
// DUT
// ---
tt_top #(
.N_PADS(38),
.G_X (16),
.G_Y (24),
.N_IO (8),
.N_O (8),
.N_I (10)
) dut_I (
.io_in (io_in),
.io_out (io_out),
.io_oeb (io_oeb),
.user_clock2(user_clock2),
.k_zero (k_zero),
.k_one (k_one)
);
// DUT connections
// ---------------
assign user_clock2 = clk_b;
assign io_in[36] = ctrl_sel_rst_n;
assign io_in[34] = ctrl_sel_inc;
assign io_in[32] = ctrl_ena;
assign io_in[6] = io_out[5]; // Loop back clk_out to clk_in
assign io_in[7] = um_rst_cnt[3];
assign io_in[8] = 1'b1;
always @(negedge io_out[5])
if (~ctrl_ena) um_rst_cnt <= 0;
else if (~um_rst_cnt[3]) um_rst_cnt <= um_rst_cnt + 1;
// Core Selection
// --------------
assign ctrl_sel_rst_n = rst_n;
always @(posedge clk_a)
if (~rst_n) cur_core <= 10'b00000_00000;
else if (ctrl_sel_inc) cur_core <= cur_core + 1;
always @(posedge clk_a)
if (~rst_n) ctrl_sel_inc <= 1'b0;
else ctrl_sel_inc <= ~ctrl_sel_inc & ((cur_core[9:5] != MUX_ID) | (cur_core[4:0] != BLK_ID));
always @(posedge clk_a)
if (~rst_n) ctrl_ena <= 1'b0;
else ctrl_ena <= ~ctrl_sel_inc & (cur_core[9:5] == MUX_ID) & (cur_core[4:0] == BLK_ID);
// Clock / Reset gen
// -----------------
initial begin
#200 rst_n = 1'b1;
#100000 $finish;
end
always #10 clk_a = ~clk_a;
always #6 clk_b = ~clk_b;
// Recording setup
// ---------------
initial begin
$dumpfile("tt_top_tb.vcd");
$dumpvars(0, tt_top_tb);
end
endmodule
| 6.822897 |
module
*
* Copyright (c) 2023 Sylvain Munaut <tnt@246tNt.com>
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_example (
`ifdef TT_WITH_ANALOG
inout wire [7:0] ua, // Analog
`endif
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
endmodule
| 7.306032 |
module for formal connectivity proof
*
* Copyright (c) 2023 Matt Venn <matt@mattvenn.net>
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_formal (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
// let solver drive the outputs
rand reg [7:0] anyseq1; assign uo_out = anyseq1;
// bidirectional outputs
rand reg [7:0] anyseq2; assign uio_out = anyseq2;
// bidirectional enables
rand reg [7:0] anyseq3; assign uio_oe = anyseq3;
always @(*) begin
if(ena) begin
// if design is enabled, looped back inputs must = outputs
assert(ui_in == uo_out);
// bidirectional outputs, only should match if oe is set
assert(uio_in == (uio_out & uio_oe));
end else begin
// otherwise inputs must be 0
assert(ui_in == 0);
// design is in reset
assert(rst_n == 0);
// no clock
assert(clk == 0);
end
end
endmodule
| 8.361297 |
module used for DEF template generation
* (can't be fully empty of yosys doesn't generate anything ...)
*
* Copyright (c) 2023 Sylvain Munaut <tnt@246tNt.com>
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
(* noblackbox *)
module tt_um_template (
`ifdef TT_WITH_ANALOG
inout wire [7:0] ua, // Analog
`endif
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
endmodule
| 6.554276 |
module
*
* Copyright (c) 2023 Sylvain Munaut <tnt@246tNt.com>
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_test (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena,
input wire clk,
input wire rst_n
);
reg rst_n_i;
reg [7:0] cnt;
always @(posedge clk or negedge rst_n)
if (~rst_n)
rst_n_i <= 1'b0;
else
rst_n_i <= 1'b1;
always @(posedge clk or negedge rst_n_i)
if (~rst_n_i)
cnt <= 0;
else
cnt <= cnt + 1;
assign uo_out = ui_in[0] ? cnt : uio_in;
assign uio_out = ui_in[0] ? cnt : 8'h00;
assign uio_oe = ui_in[0] ? 8'hff : 8'h00;
endmodule
| 7.306032 |
module TubeROM (
input wire [3:0] value,
input wire auxValue,
output reg [6:0] segments
);
always @(*) begin
if (auxValue) begin
case (value)
4'h0: segments = 7'h00; // Empty
4'h1: segments = 7'h73; // P
4'h2: segments = 7'h78; // T
4'h3: segments = 7'h50; // R
4'h4: segments = 7'h1C; // V
4'h5: segments = 7'h76; // H
4'h6: segments = 7'h38; // L
default: segments = 7'b0;
endcase
end else begin
case (value)
4'h0: segments = 7'h3F; // 0
4'h1: segments = 7'h06; // 1
4'h2: segments = 7'h5B; // 2
4'h3: segments = 7'h4F; // 3
4'h4: segments = 7'h66; // 4
4'h5: segments = 7'h6D; // 5
4'h6: segments = 7'h7D; // 6
4'h7: segments = 7'h07; // 7
4'h8: segments = 7'h7F; // 8
4'h9: segments = 7'h6F; // 9
4'hA: segments = 7'h77; // A
4'hB: segments = 7'h7C; // B
4'hC: segments = 7'h39; // C
4'hD: segments = 7'h5E; // D
4'hE: segments = 7'h79; // E
4'hF: segments = 7'h71; // F
default: segments = 7'b0;
endcase
end
end
endmodule
| 6.804894 |
module is the top module.
* Modification: Simplify memory management.
*
* To AoTuman, my dear cat, thanks for your company.
*/
`timescale 1 ns / 1 ps
module TuMan32_top(
input clk,
input resetn,
// interface for configuring itcm
input conf_rden_itcm_i,
input conf_wren_itcm_i,
input [31:0] conf_addr_itcm_i,
input [31:0] conf_wdata_itcm_i,
output wire [31:0] conf_rdata_itcm_o,
// interface for configuring dtcm
input conf_sel_dtcm_i,
input conf_rden_dtcm_i,
input conf_wren_dtcm_i,
input [31:0] conf_addr_dtcm_i,
input [31:0] conf_wdata_dtcm_i,
output wire [31:0] conf_rdata_dtcm_o,
// interface for outputing "print"
output wire print_valid_o,
output wire [7:0] print_value_o,
// interface for accessing ram in pipeline
input dataIn_valid_i,
input [133:0] dataIn_i,
output wire dataOut_valid_o,
output wire [133:0] dataOut_o
);
/** sram interface for instruction and data*/
(* mark_debug = "true" *)wire mem_rinst_1b; // read request
(* mark_debug = "true" *)wire [31:0] mem_rinst_addr_32b; // read addr
(* mark_debug = "true" *)wire [31:0] mem_rdata_instr_32b; // instruction
wire mem_wren_1b; // write data request
wire mem_rden_1b; // read data request
wire [31:0] mem_addr_32b; // write/read addr
wire [31:0] mem_wdata_32b; // write data
wire [3:0] mem_wstrb_4b; // write wstrb
wire [31:0] mem_rdata_32b; // data
/** mux of writing by conf or dtcm*/
// wire conf_wren_itcm_mux, conf_wren_d2i;
// wire [31:0] conf_addr_itcm_mux, conf_addr_d2i;
// wire [31:0] conf_wdata_itcm_mux, conf_wdata_d2i;
// assign conf_wren_itcm_mux = conf_sel_dtcm? conf_wren_itcm: conf_wren_d2i;
// assign conf_addr_itcm_mux = conf_sel_dtcm? conf_addr_itcm: conf_addr_d2i;
// assign conf_wdata_itcm_mux = conf_sel_dtcm? conf_wdata_itcm: conf_wdata_d2i;
TuMan_core TuMan32(
.clk(clk),
.resetn(resetn&~conf_sel_dtcm_i),
.finish(),
.mem_rinst(mem_rinst_1b),
.mem_rinst_addr(mem_rinst_addr_32b),
.mem_rdata_instr(mem_rdata_instr_32b),
.mem_wren(mem_wren_1b),
.mem_rden(mem_rden_1b),
.mem_addr(mem_addr_32b),
.mem_wdata(mem_wdata_32b),
.mem_wstrb(mem_wstrb_4b),
.mem_rdata(mem_rdata_32b),
.trace_valid(),
.trace_data()
);
mem_instr ITCM(
.clk(clk),
.resetn(resetn),
.mem_valid_i(mem_rinst_1b),
.mem_addr_i({2'b0,mem_rinst_addr_32b[31:2]}),
.mem_rdata_instr_o(mem_rdata_instr_32b),
.conf_rden_i(conf_rden_itcm_i),
.conf_wren_i(conf_wren_itcm_i),
.conf_addr_i(conf_addr_itcm_i),
.conf_wdata_i(conf_wdata_itcm_i),
.conf_rdata_o(conf_rdata_itcm_o)
);
mem_data DTCM(
.clk(clk),
.resetn(resetn),
// .mem_valid_i(mem_wren_1b|mem_rden_1b),
.mem_rden_i(mem_rden_1b),
.mem_wren_i(mem_wren_1b),
.mem_addr_i({2'b0,mem_addr_32b[31:2]}),
.mem_wdata_i(mem_wdata_32b),
.mem_wstrb_i(mem_wstrb_4b),
.mem_rdata_o(mem_rdata_32b),
.conf_rden_i(conf_rden_dtcm_i),
.conf_wren_i(conf_wren_dtcm_i),
.conf_addr_i(conf_addr_dtcm_i),
.conf_wdata_i(conf_wdata_dtcm_i),
.conf_rdata_o(conf_rdata_dtcm_o),
.dataIn_valid_i(dataIn_valid_i),
.dataIn_i(dataIn_i),
.dataOut_valid_o(dataOut_valid_o),
.dataOut_o(dataOut_o),
.print_valid_o(print_valid_o),
.print_value_o(print_value_o)
);
endmodule
| 7.105525 |
module */
/* this module contains everything that has to deal with
drawing pixels on the VGA display*/
module tumbler_vga(
clock, // On Board 50 MHz
// Your inputs and outputs here
colour_in,
draw_full,
draw,
x_in,
y_in,
resetn,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
/* parameter passed in indicating the .mif file to load */
parameter BACKGROUND_IMAGE = "../res/spybackground.mif";
input clock; // 50 MHz expected
input [2:0] colour_in;
input [7:0] x_in, y_in;
input draw_full, draw, resetn;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
/* Create the colour, x, y and
* writeEn wires that are inputs to the controller. */
wire [2:0] colour2;
wire [7:0] x;
wire [6:0] y;
wire writeEn;
/* Create an Instance of a VGA controller - there can be only one!
* Define the number of colours as well as the initial background
* image file (.MIF) for the controller. */
vga_adapter VGA(
.resetn(resetn),
.clock(clock),
.colour(colour2),
.x(x),
.y(y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = BACKGROUND_IMAGE;
wire draw, draw_full;
// Instansiate FSM control
control c0(
.clock(clock),
.go(draw),
.in_x(x_in),
.in_y(y_in),
.in_c(colour_in),
.full(draw_full),
.reset(resetn),
.x(x),
.y(y),
.c(colour2),
.print(writeEn)
);
endmodule
| 8.02433 |
module TUNE_ADDER (
input clk,
input rst,
input en,
input [31:0] FTW,
input signed [31:0] ACTION,
output [31:0] TUNED_FTW
);
reg [31:0] reg_FTW;
assign TUNED_FTW = reg_FTW;
always @(posedge clk or posedge rst) begin
if (rst) reg_FTW <= 0;
else begin
if (en) reg_FTW <= FTW + ACTION;
else reg_FTW <= FTW;
end
end
endmodule
| 7.157137 |
module tuozhan (
in,
out
);
input [15:0] in;
output [31:0] out;
assign out[15:0] = in;
assign out[31:16] = in[15] ? 16'hffff : 16'h0000;
endmodule
| 6.611472 |
module tuple_empty_attr (
output [7:0] out,
output [7:0] out2
);
assign out = 40;
assign out2 = 3;
endmodule
| 7.514762 |
module tuple_packet_analyzer #(
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_TUSER_WIDTH = 128,
parameter NETWORK_PROTOCOL_COMBINATIONS = 4,
parameter MAX_HDR_WORDS = 6,
parameter DIVISION_FACTOR = 2,
parameter PRTCL_ID_WIDTH = 2,
parameter NUM_INPUT_QUEUES = 8,
parameter BYTES_COUNT_WIDTH = 16,
parameter TUPLE_WIDTH = 104,
parameter ATTRIBUTE_DATA_WIDTH = 135
) (
// --- Interface to the previous stage
input [ C_S_AXIS_DATA_WIDTH-1:0] tdata,
input [C_S_AXIS_TUSER_WIDTH-1:0] tuser,
input valid,
input tlast,
// --- Results
input tuple_pkt_en,
output pkt_valid,
output [ATTRIBUTE_DATA_WIDTH-1:0] pkt_attributes,
//{input_port, prtcl_id, pkt_flags, bytes, l4 dst port, l4 src port, dest ip, src ip, proto}
// --- Misc
input reset,
input clk
);
//---------------------- Wires/Regs -------------------------------
wire [C_S_AXIS_DATA_WIDTH-1:0] pkt_tdata;
wire [C_S_AXIS_TUSER_WIDTH-1:0] pkt_tuser;
wire pkt_eoh;
wire pkt_tlast;
wire pkt_tvalid;
//------------------------ Logic ----------------------------------
packet_monitor #(
.C_S_AXIS_DATA_WIDTH (C_S_AXIS_DATA_WIDTH),
.C_S_AXIS_TUSER_WIDTH(C_S_AXIS_TUSER_WIDTH),
.MAX_HDR_WORDS (MAX_HDR_WORDS)
) packet_monitor_inst (
// --- Interface to the previous stage
.tdata (tdata),
.valid (valid),
.tlast (tlast),
.tuser (tuser),
// --- Results
.out_tdata(pkt_tdata),
.out_tuser(pkt_tuser),
.out_valid(pkt_tvalid),
.out_eoh (pkt_eoh),
.out_tlast(pkt_tlast),
.sample_results(),
// --- Misc
.reset(reset),
.clk (clk)
);
tuple_ETH_IPv4_TCPnUDP #(
.C_S_AXIS_DATA_WIDTH (C_S_AXIS_DATA_WIDTH),
.C_S_AXIS_TUSER_WIDTH(C_S_AXIS_TUSER_WIDTH),
.TUPLE_WIDTH (TUPLE_WIDTH),
.NUM_INPUT_QUEUES (NUM_INPUT_QUEUES),
.PRTCL_ID_WIDTH (PRTCL_ID_WIDTH),
.BYTES_COUNT_WIDTH (BYTES_COUNT_WIDTH),
.ATTRIBUTE_DATA_WIDTH(ATTRIBUTE_DATA_WIDTH)
) tuple_ETH_IPv4_TCPnUDP (
// --- Interface to the previous stage
.in_tdata(pkt_tdata),
.in_valid(pkt_tvalid),
.in_tlast(pkt_tlast),
.in_eoh (pkt_eoh),
.in_tuser(pkt_tuser),
.tuple_pkt_en(tuple_pkt_en),
.pkt_valid (pkt_valid),
.pkt_attributes(pkt_attributes),
// --- Misc
.reset(reset),
.clk (clk)
);
endmodule
| 7.13646 |
module turbosound (
input wire clk,
input wire clkay,
input wire reset_n,
input wire disable_ay,
input wire disable_turboay,
input wire bdir,
input wire bc1,
input wire [7:0] din,
output wire [7:0] dout,
output wire oe_n,
output wire [7:0] audio_out_ay1,
output wire [7:0] audio_out_ay2,
output wire [23:0] audio_out_ay1_splitted,
output wire [23:0] audio_out_ay2_splitted
);
reg ay_select = 1'b1;
always @(posedge clk) begin
if (reset_n == 1'b0) ay_select <= 1'b1;
else if (disable_ay == 1'b0 && disable_turboay == 1'b0 && bdir && bc1 && din[7:1] == 7'b1111111)
ay_select <= din[0]; // 1: select first AY, 0: select second AY
end
wire oe_n_ay1, oe_n_ay2;
wire [7:0] dout_ay1, dout_ay2;
assign dout = (ay_select) ? dout_ay1 : dout_ay2;
assign oe_n = (ay_select && !disable_ay)? oe_n_ay1 :
(!ay_select && !disable_ay && !disable_turboay)? oe_n_ay2 :
1'b1;
YM2149 ay1 (
.I_DA(din),
.O_DA(dout_ay1),
.O_DA_OE_L(oe_n_ay1),
.I_A9_L(1'b0),
.I_A8(ay_select),
.I_BDIR(bdir),
.I_BC2(1'b1),
.I_BC1(bc1),
.I_SEL_L(1'b0),
.O_AUDIO(audio_out_ay1),
.O_AUDIO_A(audio_out_ay1_splitted[23:16]),
.O_AUDIO_B(audio_out_ay1_splitted[15:8]),
.O_AUDIO_C(audio_out_ay1_splitted[7:0]),
.I_IOA(8'h00),
.O_IOA(),
.O_IOA_OE_L(),
.I_IOB(8'h00),
.O_IOB(),
.O_IOB_OE_L(),
.ENA(~disable_ay),
.RESET_L(reset_n),
.CLK(clkay),
.CLK28(clk)
);
YM2149 ay2 (
.I_DA(din),
.O_DA(dout_ay2),
.O_DA_OE_L(oe_n_ay2),
.I_A9_L(1'b0),
.I_A8(~ay_select),
.I_BDIR(bdir),
.I_BC2(1'b1),
.I_BC1(bc1),
.I_SEL_L(1'b0),
.O_AUDIO(audio_out_ay2),
.O_AUDIO_A(audio_out_ay2_splitted[23:16]),
.O_AUDIO_B(audio_out_ay2_splitted[15:8]),
.O_AUDIO_C(audio_out_ay2_splitted[7:0]),
.I_IOA(8'h00),
.O_IOA(),
.O_IOA_OE_L(),
.I_IOB(8'h00),
.O_IOB(),
.O_IOB_OE_L(),
.ENA(~disable_ay & ~disable_turboay),
.RESET_L(reset_n),
.CLK(clkay),
.CLK28(clk)
);
endmodule
| 6.882167 |
module ture_dp_sram ( /*autoarg*/
// Outputs
douta,
doutb,
// Inputs
clka,
clkb,
csen_n,
dina,
addra,
wrena_n,
rdena_n,
dinb,
addrb,
wrenb_n,
rdenb_n
);
parameter ADDR_WIDTH = 4;
parameter DATA_WIDTH = 8;
input clka;
input clkb;
input csen_n;
//Port A Signal
input [DATA_WIDTH-1:0] dina;
input [ADDR_WIDTH-1:0] addra;
output reg [DATA_WIDTH-1:0] douta;
input wrena_n;
input rdena_n;
//Port B Signal
input [DATA_WIDTH-1:0] dinb;
input [ADDR_WIDTH-1:0] addrb;
output reg [DATA_WIDTH-1:0] doutb;
input wrenb_n;
input rdenb_n;
reg [DATA_WIDTH-1:0] register[2**ADDR_WIDTH-1:0];
always @(posedge clka) begin
if (!wrena_n && !csen_n) begin
register[addra] <= dina;
douta <= dina;
end else if (!csen_n) douta <= register[addra];
end
always @(posedge clkb) begin
if (!wrenb_n && !csen_n) begin
register[addrb] <= dinb;
doutb <= dinb;
end else if (!csen_n) begin
doutb <= register[addrb];
end
end
endmodule
| 7.104508 |
module BUF(A, Y);
input A;
output Y = A;
endmodule
| 6.918193 |
module NOT(A, Y);
input A;
output Y = ~A;
endmodule
| 7.323172 |
module NAND(A, B, Y);
input A, B;
output Y = ~(A & B);
endmodule
| 7.167084 |
module AND3(A, B, C, Y);
input A, B, C;
output Y = A & B & C;
endmodule
| 6.909346 |
module NOR(A, B, Y);
input A, B;
output Y = ~(A | B);
endmodule
| 7.436332 |
module OR(A, B, Y);
input A, B;
output Y = A | B;
endmodule
| 7.133681 |
module OR3(A, B, C, Y);
input A, B, C;
output Y = A | B | C;
endmodule
| 7.609427 |
module XOR(A, B, Y);
input A, B;
output Y = A ^ B;
endmodule
| 7.44551 |
module XNOR(A, B, Y);
input A, B;
output Y = ~(A ^ B);
endmodule
| 7.191694 |
module FA(A, B, CI, CO, Y);
input A, B, CI;
output CO = (A & B)|(B & CI)|(CI & A);
output Y = A^B^CI;
endmodule
| 6.565544 |
module DFF (
C,
D,
Q
);
input C, E, D;
output reg Q;
always @(posedge C) Q <= D;
endmodule
| 7.813248 |
module turn7seg (
input en,
input [3:0] num,
output reg [6:0] seg
);
always @*
if (en) begin
case (num)
4'd0: seg = 7'b1000000;
4'd1: seg = 7'b1111001;
4'd2: seg = 7'b0100100;
4'd3: seg = 7'b0110000;
4'd4: seg = 7'b0011001;
4'd5: seg = 7'b0010010;
4'd6: seg = 7'b0000010;
4'd7: seg = 7'b1111000;
4'd8: seg = 7'b0000000;
4'd9: seg = 7'b0010000;
4'd10: seg = 7'b0001000;
4'd11: seg = 7'b0000011;
4'd12: seg = 7'b1000110;
4'd13: seg = 7'b0100001;
4'd14: seg = 7'b0000110;
4'd15: seg = 7'b0001110;
default: seg = 7'b1111111;
endcase
end else begin
seg = {7{1'b1}};
end
endmodule
| 6.75735 |
module TURNER_LL #(
parameter BITS = 4
) (
input [BITS-1:0] IN,
input Com,
output [BITS-1:0] OUT
);
wire [BITS-1:0] bus_in, bus_out;
assign bus_in = ~IN;
ADDER_LL_CLA#(
.BITS(BITS)
) (
.A(bus_in), .B(1'b1), .S(bus_out)
);
assign OUT = Com ? bus_out : IN;
assign Min = IN[BITS-1] & bus_out[BITS-1];
assign Zero = ~IN[BITS-1] & ~bus_out[BITS-1];
endmodule
| 7.636508 |
module has inputs a clock, a left push button and a right
// push button. Its outputs are eight LED signals. Initially,
// all LEDs are off. When the left button is strobed, one LED
// walks from right to left (LSB to MSB) and then all LEDs go
// off and stay off. When the right button is strobed, one LED
// walks from left to right (MSB to LSB) and then all LEDs go
// off and stay off.
//
// The question is, what happens when the buttons strobe
// during the walking? If a different button is pressed
// than the one that started the LEDs walking, the direction
// changes. All other button presses are ignored.
//
////////////////////////////////////////////////////////////////////////////////
//
// Written and distributed by Warren Toomey
//
// This program is hereby granted to the public domain.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
module turnindicator(i_clk, i_left_stb, i_right_stb, o_led);
input wire i_clk;
input wire i_left_stb;
input wire i_right_stb;
output reg [7:0] o_led;
// State names
parameter IDLE = 0;
parameter MOVING_RIGHT = 1;
parameter MOVING_LEFT = 2;
// State variable
reg [1:0] state;
initial o_led = 0;
initial state = IDLE;
always @(posedge i_clk) begin
`ifdef FORMAL
// Formal testing. If we are idle, the LEDs must all be off.
// If we are not idle, at least one LED must be on.
assert((state==IDLE) == (o_led==0));
// Only zero or one LED can be on at any time
assert((o_led==8'h0) || (o_led==8'h1) || (o_led==8'h2) ||
(o_led==8'h4) || (o_led==8'h8) || (o_led==8'h10) ||
(o_led==8'h20) || (o_led==8'h40) || (o_led==8'h80));
`endif
case (state)
IDLE: begin
// Left button was strobed
if (i_left_stb && !i_right_stb) begin
state <= MOVING_LEFT;
o_led <= 8'b0000_0001;
end
// Right button was strobed
if (i_right_stb && !i_left_stb) begin
state <= MOVING_RIGHT;
o_led <= 8'b1000_0000;
end
// Stay idle if both or neither buttons pressed
end
MOVING_RIGHT: begin
// Walk one LED to the right
o_led <= o_led >> 1;
// Change direction if left button only pressed
if (i_left_stb && !i_right_stb)
state <= MOVING_LEFT;
// We've walked to the other end, go to idle
if (o_led == 8'b0000_0001) begin
state <= IDLE;
o_led <= 0;
end
end
MOVING_LEFT: begin
// Walk one LED to the left
o_led <= o_led << 1;
// Change direction if right button only pressed
if (i_right_stb && !i_left_stb)
state <= MOVING_RIGHT;
// We've walked to the other end, go to idle
if (o_led == 8'b1000_0000) begin
state <= IDLE;
o_led <= 0;
end
end
`ifdef FORMAL
default:
assert(0); // We must never be in any other state
`endif
endcase
end
endmodule
| 6.684547 |
module turn_around_move (
clk,
rst,
output_speed,
random_angle,
motion_command,
enable,
done_spin
);
//
//Inputs
//
input clk;
input rst;
input enable;
input done_spin;
input [9:0] random_angle;
//
//...
//Outputs
//
output [2:0] output_speed;
output [9:0] motion_command;
reg [ 2:0] output_speed;
reg [ 9:0] motion_command;
reg [31:0] timer;
//
parameter STATE_Initial = 3'd0;
parameter STATE_Rotate = 3'd1;
parameter STATE_Reverse = 3'd2;
parameter STATE_Straight = 3'd3;
parameter STATE_counters = 3'd4;
parameter ZERO_t = 16'b0000000000000000;
parameter rev_t = 16'b0000000100000000;
parameter straight_command = 10'b0000000000;
parameter Reverse_speed = 3'b101;
parameter Forward_speed = 3'b011;
parameter Zero_speed = 3'b000;
reg [2:0] CurrentState;
reg [2:0] NextState;
reg [2:0] NextSpeed;
reg [9:0] NextCommand;
always @(posedge clk) begin
if (rst) begin //global reset
CurrentState <= STATE_Initial;
motion_command <= straight_command;
output_speed <= Zero_speed;
timer <= 32'b0;
end//if
else begin
CurrentState <= NextState;
motion_command <= NextCommand;
output_speed <= NextSpeed;
if (CurrentState == STATE_Reverse) begin
timer <= timer + 1'b1;
end //if
else begin //if not reversing reset timer
timer <= 32'b0;
end //else
end //else
end //always
always @(timer or rst or done_spin or enable) begin
case (CurrentState)
STATE_Initial: begin
if (enable) begin
NextState <= STATE_Reverse;
NextCommand <= straight_command;
NextSpeed <= Reverse_speed;
end//if
else begin
NextState <= STATE_Initial;
NextCommand <= straight_command;
NextSpeed <= 3'b000;
end //else
end //state_inital
STATE_Reverse: begin
if (enable) begin
if (timer < rev_t) begin //if not done backing up keep backing up
NextState <= STATE_Reverse;
NextCommand <= straight_command;
NextSpeed <= 3'b111;
end //if
else begin //if done backing up start turning
NextState <= STATE_Rotate;
NextCommand <= random_angle;
NextSpeed <= 3'b000;
end //else
end//if
else begin //if not enable go back to STATE_Intial
NextState <= STATE_Initial;
NextCommand <= straight_command;
NextSpeed <= 3'b000;
end //else
end //state_reverse
STATE_Rotate: begin
if (enable) begin
if (done_spin) begin //if done spining, go straight
NextState <= STATE_Straight;
NextCommand <= straight_command;
NextSpeed <= 3'b011;
end //if
else begin//keep rotating
NextState <= STATE_Rotate;
NextCommand <= random_angle;
NextSpeed <= 3'b011;
end //else
end//if
else begin //if not enable go back to STATE_Intial
NextState <= STATE_Initial;
NextCommand <= straight_command;
NextSpeed <= 3'b000;
end //else
end //state_rotate
STATE_Straight: begin
if (enable) begin //keep going straight. motion_decision_fsm controls when to switch to spiral
NextState <= STATE_Straight;
NextCommand <= straight_command;
NextSpeed <= 3'b011;
end//if
else begin //if not enable go back to STATE_Intial
NextState <= STATE_Initial;
NextCommand <= straight_command;
NextSpeed <= 3'b000;
end //else
end //state_striaght
endcase
end //always
//
//
endmodule
| 9.209262 |
module spiral_move_tb;
reg clk, rst;
reg enable;
reg done_spin;
reg [9:0] random_angle;
wire [2:0] output_speed;
wire [9:0] motion_command;
turn_around_move TA (
.clk(clk),
.rst(rst),
.enable(enable),
.random_angle(random_angle),
.done_spin(done_spin),
.output_speed(output_speed),
.motion_command(motion_command)
);
initial begin
$stop;
clk = 1'b0;
rst = 1'b0;
enable = 1'b0;
done_spin = 1'b0;
random_angle = 10'b0;
#500 $stop;
end
initial begin
$dumpfile("Spiral Move.vcd");
$dumpvars;
end
always begin
#25 clk = !clk;
end
initial begin
#50 rst = 1'b1;
#50 rst = 1'b0;
#50 random_angle = 10'b00_0000_0001;
#500 enable = 1'b0;
#2000 enable = 1'b1;
#2000 done_spin = 1'b1;
#2000 done_spin = 1'b0;
#2000 $stop;
end
endmodule
| 6.797452 |
module turn_lights_control (
input clk,
input reset,
input Left,
input Right,
input Hazard,
output reg [0:7] LED
);
wire slow_clk;
clkdiv c1 (
clk,
slow_clk
);
parameter IDLE = 8'b00000000,
L4 = 8'b11110000,
L3 = 8'b01110000,
L2 = 8'b00110000,
L1 = 8'b00010000,
R1 = 8'b00001000,
R2 = 8'b00001100,
R3 = 8'b00001110,
R4 = 8'b00001111,
LR4= 8'b11111111;
always @(posedge slow_clk)
if (reset) LED <= IDLE;
else
case (LED)
IDLE:
if (Hazard || (Left && Right)) LED <= LR4;
else if (Left && ~Hazard && ~Right) LED <= L1;
else if (Right && ~Hazard && ~Left) LED <= R1;
else LED <= IDLE;
L1: LED <= L2;
L2: LED <= L3;
L3: LED <= L4;
L4: LED <= IDLE;
R1: LED <= R2;
R2: LED <= R3;
R3: LED <= R4;
R4: LED <= IDLE;
LR4: LED <= IDLE;
default: ;
endcase
endmodule
| 6.696489 |
module clkdiv (
clk,
clk_out
);
input clk;
output clk_out;
reg [22:0] COUNT;
assign clk_out = COUNT[22];
always @(posedge clk) begin
COUNT = COUNT + 1;
end
endmodule
| 7.689254 |
module turning_sim ();
reg l_sim, r_sim, e_sim, clk_sim, rst_sim;
wire l1, l2, l3, r1, r2, r3;
Turning a1 (
l1,
l2,
l3,
r1,
r2,
r3,
l_sim,
r_sim,
e_sim,
clk_sim,
rst_sim
);
always begin
clk_sim <= 0;
#20;
clk_sim <= 1;
#20;
end
initial begin
rst_sim <= 1;
l_sim = 0;
r_sim = 0;
e_sim = 0;
@(posedge clk_sim);
#90 rst_sim <= 0;
@(posedge clk_sim);
#10 e_sim <= 0;
r_sim <= 0;
l_sim <= 0;
#50;
@(posedge clk_sim);
#10 e_sim <= 0;
r_sim <= 0;
l_sim <= 1;
#100;
@(posedge clk_sim);
#10 e_sim <= 0;
r_sim <= 1;
l_sim <= 0;
#100;
@(posedge clk_sim);
#10 e_sim <= 0;
r_sim <= 1;
l_sim <= 1;
#100;
@(posedge clk_sim);
#10 e_sim <= 1;
r_sim <= 0;
l_sim <= 0;
#100;
@(posedge clk_sim);
#10 e_sim <= 1;
r_sim <= 0;
l_sim <= 1;
#100;
@(posedge clk_sim);
#10 e_sim <= 1;
r_sim <= 1;
l_sim <= 0;
#100;
@(posedge clk_sim);
#10 e_sim <= 1;
r_sim <= 1;
l_sim <= 1;
#100;
end
endmodule
| 7.126294 |
module turn_tracker (
enable,
reset,
q
);
input enable, reset;
output reg [1:0] q = 2'b01;
always @(posedge enable or posedge reset) begin
if (reset) q <= 2'b01;
else if (q == 2'b01) q <= 2'b10;
else if (q == 2'b10) q <= 2'b01;
end
endmodule
| 7.155752 |
module Turtle(
input clk,
input clk_walk_anim,
input rstn,
input initial_show,
input collapsion_impulse,
input press_impulse,
output reg [5:0] id,
output reg oriental, // 0: right; 1: left
output [10:0] w,
output [10:0] h,
output reg shell,
output reg shell_anim
);
parameter turtlel1 = 32;
parameter turtlel2 = 33;
parameter turtler1 = 34;
parameter turtler2 = 35;
parameter shell1 = 21;
parameter shell2 = 22;
parameter shell3 = 23;
parameter shell4 = 24;
parameter null = 63;
reg walk_state;
reg pre_collapsion;
reg pre_press;
reg pre_walk_anim;
always@(posedge clk) begin
if (~rstn) begin
if (pre_collapsion != collapsion_impulse) begin
pre_collapsion = collapsion_impulse;
oriental = ~oriental;
end
if (pre_press != press_impulse) begin
pre_press = press_impulse;
if (shell) shell_anim = ~shell_anim;
else begin
shell = 1;
shell_anim = 0;
end
end
if (pre_walk_anim != clk_walk_anim) begin
pre_walk_anim = clk_walk_anim;
walk_state = ~walk_state;
end
end else begin
walk_state = 1;
oriental = 1;
shell = 0;
shell_anim = 0;
pre_collapsion = collapsion_impulse;
pre_press = press_impulse;
pre_walk_anim = clk_walk_anim;
end
end
always@* begin
if (~initial_show)
id <= null;
else if (shell)
id <= shell1;
else case ({oriental, walk_state})
2'b00: id <= turtlel1;
2'b01: id <= turtlel2;
2'b10: id <= turtler1;
2'b11: id <= turtler2;
default: id <= turtler1;
endcase
end
Object object(
.id(id),
.h(h),
.w(w)
);
endmodule
| 7.722957 |
module tuser_m3_for_arty_a7_axis_broadcaster_0_0 #(
parameter C_S_AXIS_TUSER_WIDTH = 8,
parameter C_M_AXIS_TUSER_WIDTH = 8
) (
input wire [C_S_AXIS_TUSER_WIDTH-1:0] tuser,
output wire [C_M_AXIS_TUSER_WIDTH-1:0] tuser_out
);
assign tuser_out = {tuser[0:0], tuser[0:0]};
endmodule
| 7.711162 |
module tuser_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TUSER_WIDTH = 1,
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TUSER_WIDTH = 1
) (
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ C_M_AXIS_TUSER_WIDTH-1:0] tuser_out
);
assign tuser_out = {tuser[0:0]};
endmodule
| 7.711162 |
module tuser_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TUSER_WIDTH = 1,
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TUSER_WIDTH = 1
) (
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ C_M_AXIS_TUSER_WIDTH-1:0] tuser_out
);
assign tuser_out = {tuser[0:0]};
endmodule
| 7.711162 |
module source ( /*AUTOARG*/
// Outputs
flit,
valid,
// Inputs
clk,
rst,
ready
);
parameter FLIT_DATA_WIDTH = 32;
localparam FLIT_TYPE_WIDTH = 2;
localparam FLIT_WIDTH = FLIT_DATA_WIDTH + FLIT_TYPE_WIDTH;
input clk;
input rst;
output reg [FLIT_WIDTH-1:0] flit;
output reg valid;
input ready;
// For waiting phases
int clkcount;
// State variable
int state;
// The state machine is triggered on the positive edge
always @(posedge clk) begin
// Increment clock counter for wait phases
clkcount <= clkcount + 1;
// During reset: Set initial state and counter
if (rst) begin
state <= 0;
clkcount <= 0;
end else begin
// The state machine
case (state)
0: begin
// Wait for five clock cycles
if (clkcount == 5) begin
state <= 1;
end
end
1: begin
// The combinational part (below) asserts flit, switch
// state when sink is also ready at positive edge
if (ready) begin
state <= 2;
clkcount <= 0;
end
end
2: begin
// Wait for two clock cycles
if (clkcount == 2) begin
state <= 3;
end
end
3: begin
// Send a second flit like above (state 1)
if (ready) begin
state <= 4;
end
end
4: begin
// do nothing
end
endcase // case (state)
end
end
// This is the combinational part
always @(negedge clk) begin
// Default values
valid <= 0;
flit <= 'x;
case (state)
1: begin
// Assert first flit
valid <= 1;
flit <= {2'b01, 32'h0123_4567};
end
3: begin
// Assert second flit
valid <= 1;
flit <= {2'b10, 32'hdead_beef};
end
endcase
end
endmodule
| 7.81398 |
module sink ( /*AUTOARG*/
// Outputs
ready,
// Inputs
clk,
rst,
flit,
valid
);
parameter FLIT_DATA_WIDTH = 32;
localparam FLIT_TYPE_WIDTH = 2;
localparam FLIT_WIDTH = FLIT_DATA_WIDTH + FLIT_TYPE_WIDTH;
input clk;
input rst;
input [FLIT_WIDTH-1:0] flit;
input valid;
output reg ready;
// Clock counting variable
int clkcount;
// The state
int state;
// The state machine is triggered on the positive edge
always @(posedge clk) begin
// Increment clock counter
clkcount <= clkcount + 1;
// Set initials during reset
if (rst) begin
state <= 0;
clkcount <= 0;
end else begin
case (state)
0: begin
// Wait six cycles
if (clkcount == 6) begin
state <= 1;
end
end
1: begin
// Wait for flit
if (valid) begin
$display("Received %x", flit);
state <= 2;
end
end
2: begin
// Wait for second flit
if (valid) begin
$display("Received %x", flit);
state <= 3;
end
end
3: begin
end
endcase // case (state)
end
end
// This is the combinational part
always @(negedge clk) begin
// Default
ready <= 0;
case (state)
1: begin
// Set ready
ready <= 1;
end
2: begin
// Set ready
ready <= 1;
end
endcase
end
endmodule
| 7.280857 |
modules
module tutorial_01(input clk, input rst);
localparam FLIT_WIDTH = 34;
wire [FLIT_WIDTH:0] flit;
wire valid;
wire ready;
source
u_source(/*AUTOINST*/
// Outputs
.flit (flit[FLIT_WIDTH-1:0]),
.valid (valid),
// Inputs
.clk (clk),
.rst (rst),
.ready (ready));
sink
u_sink(/*AUTOINST*/
// Outputs
.ready (ready),
// Inputs
.clk (clk),
.rst (rst),
.flit (flit[FLIT_WIDTH-1:0]),
.valid (valid));
endmodule
| 7.473142 |
module source ( /*AUTOARG*/
// Outputs
flit,
valid,
// Inputs
clk,
rst,
ready
);
parameter FLIT_DATA_WIDTH = 32;
localparam FLIT_TYPE_WIDTH = 2;
localparam FLIT_WIDTH = FLIT_DATA_WIDTH + FLIT_TYPE_WIDTH;
parameter VCHANNELS = 2;
input clk;
input rst;
output reg [FLIT_WIDTH-1:0] flit;
output reg [VCHANNELS-1:0] valid;
input [VCHANNELS-1:0] ready;
// For waiting phases
int clkcount;
// State variable
int state;
// The state machine is triggered on the positive edge
always @(posedge clk) begin
// Increment clock counter for wait phases
clkcount <= clkcount + 1;
// During reset: Set initial state and counter
if (rst) begin
state <= 0;
clkcount <= 0;
end else begin
// The state machine
case (state)
0: begin
// Wait for five clock cycles
if (clkcount == 5) begin
state <= 1;
end
end
1: begin
// The combinational part (below) asserts flit, switch
// state when VC in sink is also ready at positive edge
if (ready[0]) begin
state <= 2;
end
end
2: begin
// Now the VC is not ready anymore, so we use the other
if (ready[1]) begin
state <= 3;
end
end
3: begin
// Send on the first VC again
if (ready[0]) begin
state <= 4;
end
end
4: begin
// And a last one
if (ready[1]) begin
state <= 5;
end
end
4: begin
// do nothing
end
endcase // case (state)
end
end
// This is the combinational part
always @(negedge clk) begin
// Default values
valid <= 0;
flit <= 'x;
case (state)
1: begin
// Assert first flit
valid <= 2'b01;
flit <= {2'b01, 32'h0123_4567};
end
2: begin
// Assert flit on other VC
valid <= 2'b10;
flit <= {2'b01, 32'hdead_beef};
end
3: begin
// Assert first flit
valid <= 2'b01;
flit <= {2'b10, 32'h7654_3210};
end
4: begin
// Assert flit on other VC
valid <= 2'b10;
flit <= {2'b10, 32'h00de_adff};
end
endcase
end
endmodule
| 7.81398 |
module sink ( /*AUTOARG*/
// Outputs
ready,
// Inputs
clk,
rst,
flit,
valid
);
parameter FLIT_DATA_WIDTH = 32;
localparam FLIT_TYPE_WIDTH = 2;
localparam FLIT_WIDTH = FLIT_DATA_WIDTH + FLIT_TYPE_WIDTH;
parameter VCHANNELS = 2;
input clk;
input rst;
input [FLIT_WIDTH-1:0] flit;
input [VCHANNELS-1:0] valid;
output reg [VCHANNELS-1:0] ready;
// Clock counting variable
int clkcount;
// The state
int state;
// The state machine is triggered on the positive edge
always @(posedge clk) begin
// Increment clock counter
clkcount <= clkcount + 1;
// Set initials during reset
if (rst) begin
state <= 0;
clkcount <= 0;
end else begin
case (state)
0: begin
// Wait six cycles
if (clkcount == 6) begin
state <= 1;
end
end
1: begin
// Wait for flit
if (valid[0]) begin
$display("Received on VC0: %x", flit);
state <= 2;
end
end
2: begin
// Wait for second flit
if (valid[1]) begin
$display("Received on VC1: %x", flit);
state <= 3;
clkcount <= 0;
end
end
3: begin
// Wait six cycles
if (clkcount == 2) begin
state <= 4;
end
end
4: begin
// Wait for second flit
if (valid[0]) begin
$display("Received on VC0: %x", flit);
state <= 5;
end
end
5: begin
// Wait for second flit
if (valid[1]) begin
$display("Received on VC0: %x", flit);
state <= 6;
end
end
6: begin
end
endcase // case (state)
end
end
// This is the combinational part
always @(negedge clk) begin
// Default
ready <= 0;
case (state)
1: begin
// Set ready
ready <= 2'b11;
end
2: begin
// Set ready
ready <= 2'b10;
end
4: begin
// Set ready
ready <= 2'b11;
end
5: begin
// Set ready
ready <= 2'b11;
end
endcase
end
endmodule
| 7.280857 |
modules
module tutorial_02(input clk, input rst);
localparam FLIT_WIDTH = 34;
localparam VCHANNELS = 2;
wire [FLIT_WIDTH:0] flit;
wire [VCHANNELS-1:0] valid;
wire [VCHANNELS-1:0] ready;
source
u_source(/*AUTOINST*/
// Outputs
.flit (flit[FLIT_WIDTH-1:0]),
.valid (valid),
// Inputs
.clk (clk),
.rst (rst),
.ready (ready));
sink
u_sink(/*AUTOINST*/
// Outputs
.ready (ready),
// Inputs
.clk (clk),
.rst (rst),
.flit (flit[FLIT_WIDTH-1:0]),
.valid (valid));
endmodule
| 7.473142 |
module two_bit_pred(
input clock, reset, taken, transition,
output prediction);
logic [1:0] state;
loggic [1:0] next_state;
assign prediction = state[1];
always_comb begin
case(state)
2'b01, 2'b10 : next_state = taken ? 2'b11 : 2'b00;
2'b00 : next_state = taken ? 2'b01 : 2'b00;
2'b11 : next_state = taken ? 2'b11 : 2'b10;
endcase
end
always_ff @(posedge clock) begin
if(reset)
state <= #1 2'b01;
else if(transition)
state <= #1 next_state;
end
endmodule
| 6.84792 |
module two_bit_pred(
input clock, reset, taken, transition,
output prediction);
logic loop1, loop2;
logic [1:0] state;
logic [1:0] next_state;
assign prediction = state[1];
assign loop1 = (taken & loop2) ? 0 : 1;
assign loop2 = (taken & loop1) ? 1 : 0;
always_comb begin
case(state)
2'b01, 2'b10 : next_state = taken ? 2'b11 : 2'b00;
2'b00 : next_state = taken ? 2'b01 : 2'b00;
2'b11 : next_state = taken ? 2'b11 : 2'b10;
endcase
end
always_ff @(posedge clock) begin
if(reset)
state <= #1 2'b01;
else if(transition)
state <= #1 next_state;
end
endmodule
| 6.84792 |
module testbench;
logic clock, reset, taken, transition;
logic [15:0] bigsignal;
logic prediction;
two_bit_pred tbp(.clock(clock), .reset(reset), .taken(taekn),
.transition(transition), .prediction(prediction));
always begin
#5;
clock=~clock;
end
initial begin
$monitor("Time:%4.0f clock:%b reset:%b taken:%b transition:%b prediction:%b",
$time, clock, reset, taken, transition, prediction);
bigsignal = 16'hdead;
clock = 1'b0;
reset = 1'b1;
taken = 1'b0;
transition = 1'b1;
@(negedge clock);
@(negedge clock);
reset = 1'b0;
@(negedge clock);
taken = 1'b1;
@(negedge clock);
transition = 1'b0;
bigsignal = 16'hbeef;
@(negedge clock);
@(negedge clock);
transition = 1'b1;
#3 transition = 1'b0;
@(negedge clock);
transition = 1'b1;
@(negedge clock);
taken = 1'b0;
@(negedge clock);
@(negedge clock);
$finish;
end
endmodule
| 7.015571 |
module gates (
a,
b,
q,
r
);
input a, b;
output q, r;
assign q = a & b;
assign r = a | b;
endmodule
| 7.748371 |
module mfa (
P,
Q,
R,
C,
S
);
input P;
input Q;
input R;
output C;
output S;
assign S = (P & Q & R) | (~P & ~Q & R) | (~P & Q & ~R) | (P & ~Q & ~R);
assign C = (P & Q) | (P & R) | (Q & R);
endmodule
| 7.242357 |
module tv80_reg ( /*AUTOARG*/
// Outputs
DOBH,
DOAL,
DOCL,
DOBL,
DOCH,
DOAH,
// Inputs
AddrC,
AddrA,
AddrB,
DIH,
DIL,
clk,
CEN,
WEH,
WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
input [7:0] DIL;
output [7:0] DOBL;
output [7:0] DOCH;
output [7:0] DOAH;
input clk, CEN, WEH, WEL;
reg [7:0] RegsH[0:7];
reg [7:0] RegsL[0:7];
always @(posedge clk) begin
if (CEN) begin
if (WEH) RegsH[AddrA] <= DIH;
if (WEL) RegsL[AddrA] <= DIL;
end
end
assign DOAH = RegsH[AddrA];
assign DOAL = RegsL[AddrA];
assign DOBH = RegsH[AddrB];
assign DOBL = RegsL[AddrB];
assign DOCH = RegsH[AddrC];
assign DOCL = RegsL[AddrC];
// break out ram bits for waveform debug
wire [7:0] H = RegsH[2];
wire [7:0] L = RegsL[2];
// synopsys dc_script_begin
// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet
// synopsys dc_script_end
endmodule
| 6.903785 |
module tvmix_calc (
clk,
palentry,
cc_i,
cc_q
);
//initial begin
input clk;
input reg [32-1:0] palentry;
input reg signed [16-1:0] cc_i;
input reg signed [16-1:0] cc_q;
always @(posedge clk) begin
reg [16-1:0] pal_luma;
reg signed [8-1:0] pal_imix;
reg signed [8-1:0] pal_qmix;
reg signed [16-1:0] ires;
reg signed [16-1:0] qres;
reg [16-1:0] video;
//palentry = 32'hf000007f;
// extract bits
pal_luma <= (palentry >> 16) & 16'hFFFF;
pal_imix <= (palentry >> 8) & 8'hFF;
pal_qmix <= (palentry >> 0) & 8'hFF;
$display("luma: %d", pal_luma);
$display("imix: %d", pal_imix);
$display("qmix: %d", pal_qmix);
// incoming color carrier components
$display("cc_i: %d, cc_q %d", cc_i, cc_q);
// modulate by palette values
//ires = ($signed({{0{pal_imix[7]}}, pal_imix[7:0]}) * cc_i) / 64;
ires = ($signed(pal_imix[7:0]) * cc_i) / 64;
qres = ($signed(pal_qmix[7:0]) * cc_q) / 64;
//ires = (pal_imix * cc_i) / 64;
//qres = (pal_qmix * cc_q) / 64;
//ires = (pal_imix[7:0] * cc_i) / 64;
// calculate and print results
$display("ires: %d, qres: %d", ires, qres);
video = ires;
video = pal_luma + ires + qres;
$display("video: 0x%X", video);
//$finish;
end
endmodule
| 6.822592 |
module TV_FYP (
///////////// CLOCK /////////////
input CLOCK_50,
///////////// HDMI //////////////
inout HDMI_I2C_SCL,
inout HDMI_I2C_SDA,
inout HDMI_I2S,
inout HDMI_LRCLK,
inout HDMI_MCLK,
inout HDMI_SCLK,
output HDMI_TX_CLK,
output [23:0] HDMI_TX_D,
output HDMI_TX_DE,
output HDMI_TX_HS,
input HDMI_TX_INT,
output HDMI_TX_VS,
///////////// GPIO //////////////
inout [35:0] GPIO_0,
output [3:0] GPIO_1,
///////////// KEY ///////////////
input [1:0] KEY,
///////////// SW //////////////
input [3:0] SW,
///////////// LED //////////////
output [7:0] LED
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire reset_n;
wire i2c_clk;
wire hdmi_clk;
wire CAM_SCL;
wire CAM_SDA;
wire CAM_VS;
wire CAM_HS;
wire CAM_XLK;
wire CAM_PLK;
wire CAM_RST;
wire CAM_PWD;
wire [7:0] CAM_DTA;
// Assign Camera Pins
assign CAM_HS = GPIO_0[23];
assign CAM_VS = GPIO_0[22];
assign CAM_PLK = GPIO_0[20];
assign CAM_PWD = 1'b0;
assign CAM_RST = 1'b1;
assign GPIO_0[21] = CAM_XLK;
assign GPIO_0[10] = CAM_RST;
assign GPIO_0[11] = CAM_PWD;
assign GPIO_0[24] = CAM_SCL;
assign GPIO_0[25] = CAM_SDA;
// Camera Data
assign CAM_DTA[7] = GPIO_0[18];
assign CAM_DTA[6] = GPIO_0[19];
assign CAM_DTA[5] = GPIO_0[16];
assign CAM_DTA[4] = GPIO_0[17];
assign CAM_DTA[3] = GPIO_0[14];
assign CAM_DTA[2] = GPIO_0[15];
assign CAM_DTA[1] = GPIO_0[12];
assign CAM_DTA[0] = GPIO_0[13];
// Indicator
assign LED[7] = reset_n;
// Clock
HDMI_PLL u_hdmi_pll (
.refclk(CLOCK_50),
.rst(!KEY[0]),
.outclk_0(CAM_XLK), // 25 MHz (640x480 @ 60fps)
.outclk_1(i2c_clk), // 1 MHz
.locked(reset_n)
);
// HDMI I2C Config
HDMI_I2C_Config u_HDMI_I2C_Config (
.clk(i2c_clk),
.reset(reset_n),
.I2C_SCL(HDMI_I2C_SCL),
.I2C_SDA(HDMI_I2C_SDA),
.HDMI_TX_INT(HDMI_TX_INT)
);
// Camera I2C Config
CAM_I2C_Config u_CAM_I2C_Config (
.clk(i2c_clk),
.reset(reset_n),
.I2C_SCL(CAM_SCL),
.I2C_SDA(CAM_SDA),
.finish(LED[6])
);
wire [15:0] pixel;
wire cam_o_pclk;
wire CAM_EN;
// Camera RGB Data Capture
CAM_RGB_Capture u_CAM_RGB_Capture (
// Input
.i_pclk(CAM_PLK),
.CAM_RGB(CAM_DTA),
.HREF(CAM_HS),
.VSYNC(CAM_VS),
// Output
.HDMI_En(HDMI_EN),
.PIXEL(pixel),
.o_pclk(cam_o_pclk),
.en(CAM_EN)
);
wire HDMI_EN;
// HDMI Pattern Generator
HDMI_RGB_VPG HDMI_u (
// Input
.clk(cam_o_pclk),
.HDMI_EN(HDMI_EN),
.PIXEL(pixel),
.SLO(SLO),
// Output
.pclk(HDMI_TX_CLK),
.hs(HDMI_TX_HS),
.vs(HDMI_TX_VS),
.de(HDMI_TX_DE),
.vga_r(HDMI_TX_D[23:16]),
.vga_g(HDMI_TX_D[15:8]),
.vga_b(HDMI_TX_D[7:0])
);
reg [18:0] counter_1200k;
reg en_150;
reg [1:0] SLO = 2'd0;
always @(posedge i2c_clk or negedge reset_n) begin
if (!reset_n) begin
counter_1200k <= 19'b0;
en_150 <= 1'b0; //frequency divider
end else begin
counter_1200k <= counter_1200k + 19'b1;
en_150 <= &counter_1200k;
end
end
always @(posedge en_150) begin
if (!KEY[1])
if (SLO == 2'd2) SLO <= 2'd0;
else SLO <= SLO + 2'd1;
end
assign LED[1:0] = SLO;
assign GPIO_1[0] = HDMI_TX_HS;
assign GPIO_1[1] = HDMI_TX_VS;
assign GPIO_1[2] = HDMI_TX_DE;
assign GPIO_1[3] = HDMI_TX_CLK;
endmodule
| 6.602318 |
module tv_gen (
clk,
rst,
in0,
in1
); //Testvector Generator, Top Module
input clk; //CLOCK
input rst; //Reset Signal
output reg in0, in1; //INPUT SIGNALS for ""Test_Unit""
//STATES begin
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
//STATES end
reg [9:0] STEP = 1000; //CLOCK DELAY PARAMATER, It means "Delay 1000 Clocks"
reg [1:0] c_state, next;
wire div_clk; //Divided Clock Wire
//Module Instance for Clock Dividing
clk_counter frq_div (
.clk (clk),
.rst (rst),
.step(STEP),
.out (div_clk)
); //Instance End
always @(posedge div_clk, negedge rst) begin
//Designating Running State
if (!rst) c_state <= S0;
else c_state <= next;
end
always @(c_state) begin
//Designating Next State
case (c_state)
S0: next = S1;
S1: next = S2;
S2: next = S3;
S3: next = S0;
default: next = S0;
endcase
end
always @(c_state) begin
//Desginating Output
case (c_state)
S0: begin
in1 = 1'b0;
in0 = 1'b0;
end
S1: begin
in1 = 1'b0;
in0 = 1'b1;
end
S2: begin
in1 = 1'b1;
in0 = 1'b0;
end
S3: begin
in1 <= 1'b1;
in0 <= 1'b1;
end
endcase
end
endmodule
| 7.530758 |
module clk_counter (
clk,
rst,
step,
out
); //clk divider, Sub Module
input clk, rst;
input [9:0] step; //Clock Delay Parameter
output reg out; //New Clock OUTPUT
reg [9:0] counter;
always @(posedge clk, negedge rst) begin
if (!rst) begin
//RESET Condition
counter <= 8'b1;
out <= 1'b0;
end else begin
if (counter == step) begin
//Generate Rising Edge
counter <= 8'b1;
out <= 1'b1;
end else begin
//Default State, maintain LOW LEVEL
counter <= counter + 1'b1;
out <= 1'b0;
end
end
end
always @(posedge clk, negedge clk) begin
//Passthrow clk when STEP == 1
if (step == 1) begin
out <= clk;
end
end
endmodule
| 7.09339 |
module twelve (
MR,
EN,
CLK,
Q,
CO
);
input wire MR, CLK, EN;
output reg [3:0] Q;
output CO;
always @(posedge CLK or negedge MR) begin
if (~MR) Q <= 4'b0000;
else if (EN) begin
if (Q == 4'b0000) Q <= 4'b1001;
else Q <= Q - 1'b1;
end
end
assign CO = (~Q[0]) & (~Q[1]) & (~Q[2]) & (~Q[3]) & (MR);
endmodule
| 7.128572 |
module twenty_to_eight #(
parameter WORD_LEN = 66
) (
input clk,
arst,
input [20*WORD_LEN-1:0] din,
input din_valid,
output din_ready,
output reg [8*WORD_LEN-1:0] dout,
input dout_ready,
output reg dout_valid
);
// Possible states :
// 0: holding 0, accept 20, 8 out
// 1: holding 12, no accept, 8 out
// 2: holding 4, accept 20, 8 out
// 3: holding 16, no accept, 8 out
// 4: holding 8, no accept, 8 out
reg [4:0] state;
wire din_wanted = state[0] | state[2];
wire input_wait = din_wanted & !din_valid;
wire output_wait = dout_valid & !dout_ready;
assign din_ready = din_wanted & !output_wait;
always @(posedge clk or posedge arst) begin
if (arst) state <= 5'b1;
else if (!input_wait & !output_wait) state <= {state[3:0], state[4]};
end
reg [16*WORD_LEN-1:0] surplus;
always @(posedge clk or posedge arst) begin
if (arst) begin
dout <= 0;
dout_valid <= 0;
end else begin
if (dout_valid & dout_ready) dout_valid <= 1'b0;
if (!input_wait & !output_wait) begin
dout_valid <= 1'b1;
if (state[0]) begin
dout <= din[8*WORD_LEN-1:0];
surplus <= din[20*WORD_LEN-1:8*WORD_LEN];
end
if (state[1]) begin
dout <= surplus[8*WORD_LEN-1:0];
surplus <= {{(12 * WORD_LEN) {1'b0}}, surplus[12*WORD_LEN-1:8*WORD_LEN]};
end
if (state[2]) begin
dout[4*WORD_LEN-1:0] <= surplus[4*WORD_LEN-1:0];
dout[8*WORD_LEN-1:4*WORD_LEN] <= din[4*WORD_LEN-1:0];
surplus <= din[20*WORD_LEN-1:4*WORD_LEN];
end
if (state[3]) begin
dout <= surplus[8*WORD_LEN-1:0];
surplus <= {{(8 * WORD_LEN) {1'b0}}, surplus[16*WORD_LEN-1:8*WORD_LEN]};
end
if (state[4]) begin
dout <= surplus[8*WORD_LEN-1:0];
end
end
end
end
endmodule
| 7.24617 |
module twenty_to_five #(
parameter WORD_LEN = 66
) (
input clk,
arst,
input [20*WORD_LEN-1:0] din,
input din_valid,
output din_ready,
output [5*WORD_LEN-1:0] dout,
input dout_ready,
output dout_valid
);
reg [2:0] holding; // holding 0..4 blocks of 5 words
reg [20*WORD_LEN-1:0] storage;
assign din_ready = (holding == 3'b0) || ((holding == 3'b1) && dout_ready);
assign dout_valid = (|holding);
assign dout = storage[5*WORD_LEN-1:0];
always @(posedge clk or posedge arst) begin
if (arst) begin
storage <= 0;
holding <= 0;
end else begin
if (din_ready & din_valid) begin
// if we are reloading it goes to 4 blocks available
storage <= din;
holding <= 3'b100;
end else begin
// not reloading
// if the output side is ready lose one block
if (dout_valid & dout_ready) begin
holding <= holding - 1'b1;
storage <= {{(5 * WORD_LEN) {1'b0}}, storage[20*WORD_LEN-1:5*WORD_LEN]};
end
end
end
end
endmodule
| 7.075203 |
module twiddle_rom (
clk,
rst,
addr,
data_read,
rd_en
);
parameter ADDR_WIDTH = 2;
parameter ROM_WIDTH = 81; //3*8+6*9
input clk, rst, rd_en;
input [ADDR_WIDTH-1:0] addr;
output reg [ROM_WIDTH-1:0] data_read;
reg [ROM_WIDTH-1:0] rom[3:0];
always @(posedge clk) begin
if (rst) data_read <= 0;
else if (rd_en) data_read <= rom[addr];
end
///Here the gray coding is used for address generation;
initial begin
//twiddle_r_b twiddle_r_c twiddle_r_d rpi_b_in rmi_b_in rpi_c_in rmi_c_in rpi_d_in rmi_d_in
rom[0] = 81'b010000000010000000010000000010000000010000000010000000010000000010000000010000000;
rom[1] = 81'b001110110001011011000110001001000101010100111000000000010110101110111011010100111;
rom[3] = 81'b001011011000000000110100101000000000010110101110000000010000000101001011000000000;
rom[2] = 81'b000110001110100101110001010110111011010100111101001011000000000110111011101011001;
end
endmodule
| 7.090187 |
module twiddle64_0 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
assign dout_rere = din_real;
assign dout_imim = din_imag;
assign dout_reim = din_real;
assign dout_imre = din_imag;
endmodule
| 7.511271 |
module twiddle64_1 #(
parameter DATA_WIDTH = 14
) (
input signed [DATA_WIDTH-1:0] din_real,
input signed [DATA_WIDTH-1:0] din_imag,
output signed [DATA_WIDTH-1:0] dout_rere,
output signed [DATA_WIDTH-1:0] dout_imim,
output signed [DATA_WIDTH-1:0] dout_reim,
output signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real - (din_real >>> 4);
assign tmp1_rere = tmp0_rere - (tmp0_rere >>> 6);
assign dout_rere = tmp0_rere + (tmp1_rere >>> 4);
assign tmp0_imim = din_imag >>> 4;
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 2);
assign tmp2_imim = tmp1_imim + (tmp1_imim >>> 6);
assign dout_imim = tmp1_imim + (tmp2_imim >>> 2);
assign tmp0_imre = din_imag - (din_imag >>> 4);
assign tmp1_imre = tmp0_imre - (tmp0_imre >>> 6);
assign dout_imre = tmp0_imre + (tmp1_imre >>> 4);
assign tmp0_reim = din_real >>> 4;
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 2);
assign tmp2_reim = tmp1_reim + (tmp1_reim >>> 6);
assign dout_reim = tmp1_reim + (tmp2_reim >>> 2);
endmodule
| 6.918234 |
module twiddle64_2 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real + (din_real >>> 2);
assign tmp1_rere = tmp0_rere - (tmp0_rere >>> 6);
assign dout_rere = din_real - (tmp1_rere >>> 6);
assign tmp0_imim = din_imag >>> 3;
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 4);
assign tmp2_imim = tmp1_imim - (tmp1_imim >>> 4);
assign dout_imim = tmp1_imim + (tmp2_imim >>> 1);
assign tmp0_imre = din_imag + (din_imag >>> 2);
assign tmp1_imre = tmp0_imre - (tmp0_imre >>> 6);
assign dout_imre = din_imag - (tmp1_imre >>> 6);
assign tmp0_reim = din_real >>> 3;
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 4);
assign tmp2_reim = tmp1_reim - (tmp1_reim >>> 4);
assign dout_reim = tmp1_reim + (tmp2_reim >>> 1);
endmodule
| 7.168156 |
module twiddle64_3 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp3_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
wire signed [DATA_WIDTH:0] tmp3_reim;
assign tmp0_rere = din_real - (din_real >>> 5);
assign tmp1_rere = tmp0_rere + (tmp0_rere >>> 8);
assign dout_rere = tmp1_rere - (din_real >>> 6);
assign tmp0_imim = din_imag >>> 2;
assign tmp1_imim = tmp0_imim - (tmp0_imim >>> 2);
assign tmp2_imim = tmp1_imim + (tmp1_imim >>> 5);
assign tmp3_imim = tmp1_imim - (tmp2_imim >>> 3);
assign dout_imim = tmp3_imim + (tmp0_imim >>> 1);
assign tmp0_imre = din_imag - (din_imag >>> 5);
assign tmp1_imre = tmp0_imre + (tmp0_imre >>> 8);
assign dout_imre = tmp1_imre - (din_imag >>> 6);
assign tmp0_reim = din_real >>> 2;
assign tmp1_reim = tmp0_reim - (tmp0_reim >>> 2);
assign tmp2_reim = tmp1_reim + (tmp1_reim >>> 5);
assign tmp3_reim = tmp1_reim - (tmp2_reim >>> 3);
assign dout_reim = tmp3_reim + (tmp0_reim >>> 1);
endmodule
| 7.472133 |
module twiddle64_4 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real - (din_real >>> 3);
assign tmp1_rere = din_real + (tmp0_rere >>> 2);
assign dout_rere = din_real - (tmp1_rere >>> 4);
assign tmp0_imim = din_imag >>> 2;
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 1);
assign tmp2_imim = tmp0_imim - (tmp0_imim >>> 7);
assign dout_imim = tmp1_imim + (tmp2_imim >>> 5);
assign tmp0_imre = din_imag - (din_imag >>> 3);
assign tmp1_imre = din_imag + (tmp0_imre >>> 2);
assign dout_imre = din_imag - (tmp1_imre >>> 4);
assign tmp0_reim = din_real >>> 2;
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 1);
assign tmp2_reim = tmp0_reim - (tmp0_reim >>> 7);
assign dout_reim = tmp1_reim + (tmp2_reim >>> 5);
endmodule
| 7.362297 |
module twiddle64_5 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp3_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
wire signed [DATA_WIDTH:0] tmp3_reim;
assign tmp0_rere = din_real + (din_real >>> 7);
assign tmp1_rere = tmp0_rere + (tmp0_rere >>> 4);
assign dout_rere = din_real - (tmp1_rere >>> 3);
assign tmp0_imim = din_imag >>> 1;
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 2);
assign tmp2_imim = tmp1_imim + (tmp1_imim >>> 3);
assign tmp3_imim = (tmp2_imim >>> 6) - tmp1_imim;
assign dout_imim = (tmp3_imim >>> 2) + tmp1_imim;
assign tmp0_imre = din_imag + (din_imag >>> 7);
assign tmp1_imre = tmp0_imre + (tmp0_imre >>> 4);
assign dout_imre = din_imag - (tmp1_imre >>> 3);
assign tmp0_reim = din_real >>> 1;
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 2);
assign tmp2_reim = tmp1_reim + (tmp1_reim >>> 3);
assign tmp3_reim = (tmp2_reim >>> 6) - tmp1_reim;
assign dout_reim = (tmp3_reim >>> 2) + tmp1_reim;
endmodule
| 7.181315 |
module twiddle64_6 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp2_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp2_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real + (din_real >>> 2);
assign tmp1_rere = tmp0_rere - (tmp0_rere >>> 5);
assign tmp2_rere = tmp0_rere + (tmp1_rere >>> 4);
assign dout_rere = (din_real >>> 1) + (tmp2_rere >>> 2);
assign tmp0_imim = din_imag >>> 1;
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 6);
assign tmp2_imim = tmp1_imim - (tmp1_imim >>> 3);
assign dout_imim = tmp0_imim + (tmp2_imim >>> 3);
assign tmp0_imre = din_imag + (din_imag >>> 2);
assign tmp1_imre = tmp0_imre - (tmp0_imre >>> 5);
assign tmp2_imre = tmp0_imre + (tmp1_imre >>> 4);
assign dout_imre = (din_imag >>> 1) + (tmp2_imre >>> 2);
assign tmp0_reim = din_real >>> 1;
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 6);
assign tmp2_reim = tmp1_reim - (tmp1_reim >>> 3);
assign dout_reim = tmp0_reim + (tmp2_reim >>> 3);
endmodule
| 6.972645 |
module twiddle64_7 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp2_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
wire signed [DATA_WIDTH:0] tmp2_reim;
assign tmp0_rere = din_real - (din_real >>> 5);
assign tmp1_rere = tmp0_rere - (tmp0_rere >>> 4);
assign dout_rere = din_real - (tmp1_rere >>> 2);
assign tmp0_imim = din_imag + (din_imag >>> 4);
assign tmp1_imim = din_imag + (tmp0_imim >>> 7);
assign tmp2_imim = tmp1_imim + (tmp1_imim >>> 3);
assign dout_imim = tmp2_imim - (din_imag >>> 1);
assign tmp0_imre = din_imag - (din_imag >>> 5);
assign tmp1_imre = tmp0_imre - (tmp0_imre >>> 4);
assign dout_imre = din_imag - (tmp1_imre >>> 2);
assign tmp0_reim = din_real + (din_real >>> 4);
assign tmp1_reim = din_real + (tmp0_reim >>> 7);
assign tmp2_reim = tmp1_reim + (tmp1_reim >>> 3);
assign dout_reim = tmp2_reim - (din_real >>> 1);
endmodule
| 7.309479 |
module twiddle64_8 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output wire signed [DATA_WIDTH-1:0] dout_imre
);
wire signed [DATA_WIDTH:0] tmp0_rere;
wire signed [DATA_WIDTH:0] tmp1_rere;
wire signed [DATA_WIDTH:0] tmp0_imim;
wire signed [DATA_WIDTH:0] tmp1_imim;
wire signed [DATA_WIDTH:0] tmp0_imre;
wire signed [DATA_WIDTH:0] tmp1_imre;
wire signed [DATA_WIDTH:0] tmp0_reim;
wire signed [DATA_WIDTH:0] tmp1_reim;
assign tmp0_rere = din_real - (din_real >>> 4);
assign tmp1_rere = tmp0_rere + (tmp0_rere >>> 2);
assign dout_rere = din_real - (tmp1_rere >>> 2);
assign tmp0_imim = din_imag - (din_imag >>> 4);
assign tmp1_imim = tmp0_imim + (tmp0_imim >>> 2);
assign dout_imim = din_imag - (tmp1_imim >>> 2);
assign tmp0_imre = din_imag - (din_imag >>> 4);
assign tmp1_imre = tmp0_imre + (tmp0_imre >>> 2);
assign dout_imre = din_imag - (tmp1_imre >>> 2);
assign tmp0_reim = din_real - (din_real >>> 4);
assign tmp1_reim = tmp0_reim + (tmp0_reim >>> 2);
assign dout_reim = din_real - (tmp1_reim >>> 2);
endmodule
| 6.980159 |
module twiddle8_multiplier #(
parameter DATA_WIDTH_IN = 10,
parameter DATA_WIDTH_OUT = DATA_WIDTH_IN + 1,
parameter TWIDDLE_RANK = 8
) (
input wire [ 1:0] twiddle,
input wire signed [ DATA_WIDTH_IN-1:0] din_real,
input wire signed [ DATA_WIDTH_IN-1:0] din_imag,
output reg signed [DATA_WIDTH_OUT-1:0] dout_real,
output reg signed [DATA_WIDTH_OUT-1:0] dout_imag
);
generate
case (TWIDDLE_RANK)
2: begin : rank2
always @(twiddle, din_real, dout_real) begin
dout_real = din_real;
dout_imag = din_imag;
end
end
4: begin : rank4
always @(twiddle, din_real, din_imag) begin
if (twiddle == 1) begin
dout_real = din_imag;
dout_imag = -din_real;
end else begin
dout_real = din_real;
dout_imag = din_imag;
end
end
end
8: begin : rank8
reg signed [DATA_WIDTH_OUT-1:0] const_din_real;
reg signed [DATA_WIDTH_OUT-1:0] const_din_imag;
wire signed [DATA_WIDTH_OUT-1:0] const_dout_real;
wire signed [DATA_WIDTH_OUT-1:0] const_dout_imag;
twiddle_45degree #(
.DATA_WIDTH(DATA_WIDTH_OUT)
) twiddle_45degree (
.din_real (const_din_real),
.din_imag (const_din_imag),
.dout_real(const_dout_real),
.dout_imag(const_dout_imag)
);
always @(twiddle, din_real, din_imag, const_dout_real, const_dout_imag) begin
if (twiddle == 3) begin
const_din_real = din_imag - din_real;
const_din_imag = -din_imag - din_real;
dout_real = const_dout_real;
dout_imag = const_dout_imag;
end else if (twiddle == 2) begin
dout_real = din_imag;
dout_imag = -din_real;
end else if (twiddle == 1) begin
const_din_real = din_real + din_imag;
const_din_imag = din_imag - din_real;
dout_real = const_dout_real;
dout_imag = const_dout_imag;
end else begin
dout_real = din_real;
dout_imag = din_imag;
end
end
end
endcase
endgenerate
endmodule
| 6.6709 |
module twiddle_45degree #(
parameter DATA_WIDTH = 10
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_real,
output wire signed [DATA_WIDTH-1:0] dout_imag
);
wire signed [DATA_WIDTH-1:0] tmp1_real;
wire signed [DATA_WIDTH-1:0] tmp2_real;
assign tmp1_real = din_real - (din_real >>> 4);
assign tmp2_real = tmp1_real + (tmp1_real >>> 2);
assign dout_real = din_real - (tmp2_real >>> 2);
wire signed [DATA_WIDTH-1:0] tmp1_imag;
wire signed [DATA_WIDTH-1:0] tmp2_imag;
assign tmp1_imag = din_imag - (din_imag >>> 4);
assign tmp2_imag = tmp1_imag + (tmp1_imag >>> 2);
assign dout_imag = din_imag - (tmp2_imag >>> 2);
endmodule
| 7.408505 |
module TwiddleConvert4 #(
parameter LOG_N = 6, // Address Bit Length
parameter WIDTH = 16, // Data Bit Length
parameter TW_FF = 1, // Use Twiddle Output Register
parameter TC_FF = 1 // Use Output Register
) (
input clock, // Master Clock
input [LOG_N-1:0] tw_addr, // Twiddle Number
input [WIDTH-1:0] tw_re, // Twiddle Value (Real)
input [WIDTH-1:0] tw_im, // Twiddle Value (Imag)
output [LOG_N-1:0] tc_addr, // Converted Twiddle Number
output [WIDTH-1:0] tc_re, // Converted Twiddle Value (Real)
output [WIDTH-1:0] tc_im // Converted Twiddle Value (Imag)
);
// Internal Nets
reg [LOG_N-1:0] ff_addr;
wire [LOG_N-1:0] sel_addr;
reg [WIDTH-1:0] mx_re;
reg [WIDTH-1:0] mx_im;
reg [WIDTH-1:0] ff_re;
reg [WIDTH-1:0] ff_im;
// Convert Twiddle Number
assign tc_addr[LOG_N-1:LOG_N-2] = 2'd0;
assign tc_addr[LOG_N-3:0] = tw_addr[LOG_N-3:0];
// Convert Twiddle Value
always @(posedge clock) begin
ff_addr <= tw_addr;
end
assign sel_addr = TW_FF ? ff_addr : tw_addr;
always @* begin
if (sel_addr[LOG_N-3:0] == {LOG_N - 2{1'b0}}) begin
case (sel_addr[LOG_N-1:LOG_N-2])
2'd0: {mx_re, mx_im} <= {{WIDTH{1'b0}}, {WIDTH{1'b0}}};
2'd1: {mx_re, mx_im} <= {{WIDTH{1'b0}}, {1'b1, {WIDTH - 1{1'b0}}}};
default: {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end else begin
case (sel_addr[LOG_N-1:LOG_N-2])
2'd0: {mx_re, mx_im} <= {tw_re, tw_im};
2'd1: {mx_re, mx_im} <= {tw_im, -tw_re};
2'd2: {mx_re, mx_im} <= {-tw_re, -tw_im};
default: {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end
end
always @(posedge clock) begin
ff_re <= mx_re;
ff_im <= mx_im;
end
assign tc_re = TC_FF ? ff_re : mx_re;
assign tc_im = TC_FF ? ff_im : mx_im;
endmodule
| 6.684026 |
module TwiddleConvert8 #(
parameter LOG_N = 6, // Address Bit Length
parameter WIDTH = 16, // Data Bit Length
parameter TW_FF = 1, // Use Twiddle Output Register
parameter TC_FF = 1 // Use Output Register
) (
input clock, // Master Clock
input [LOG_N-1:0] tw_addr, // Twiddle Number
input [WIDTH-1:0] tw_re, // Twiddle Value (Real)
input [WIDTH-1:0] tw_im, // Twiddle Value (Imag)
output [LOG_N-1:0] tc_addr, // Converted Twiddle Number
output [WIDTH-1:0] tc_re, // Converted Twiddle Value (Real)
output [WIDTH-1:0] tc_im // Converted Twiddle Value (Imag)
);
// Define Constants
localparam [WIDTH-1:0] COSMQ = (((32'h5A82799A << 1) >> (32 - WIDTH)) + 1) >> 1; // cos(-pi/4)
localparam [WIDTH-1:0] SINMH = 32'h80000000 >> (32 - WIDTH); // sin(-pi/2)
// Internal Nets
reg [LOG_N-1:0] ff_addr;
wire [LOG_N-1:0] sel_addr;
reg [WIDTH-1:0] mx_re;
reg [WIDTH-1:0] mx_im;
reg [WIDTH-1:0] ff_re;
reg [WIDTH-1:0] ff_im;
// Convert Twiddle Number
assign tc_addr[LOG_N-1:LOG_N-3] = 3'd0;
assign tc_addr[LOG_N-4:0] = tw_addr[LOG_N-3] ? -tw_addr[LOG_N-4:0] : tw_addr[LOG_N-4:0];
// Convert Twiddle Value
always @(posedge clock) begin
ff_addr <= tw_addr;
end
assign sel_addr = TW_FF ? ff_addr : tw_addr;
always @* begin
if (sel_addr[LOG_N-4:0] == {LOG_N - 3{1'b0}}) begin
case (sel_addr[LOG_N-1:LOG_N-3])
3'd0: {mx_re, mx_im} <= {{WIDTH{1'b0}}, {WIDTH{1'b0}}};
3'd1: {mx_re, mx_im} <= {COSMQ, -COSMQ};
3'd2: {mx_re, mx_im} <= {{WIDTH{1'b0}}, SINMH};
3'd3: {mx_re, mx_im} <= {-COSMQ, -COSMQ};
default: {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end else begin
case (sel_addr[LOG_N-1:LOG_N-3])
3'd0: {mx_re, mx_im} <= {tw_re, tw_im};
3'd1: {mx_re, mx_im} <= {-tw_im, -tw_re};
3'd2: {mx_re, mx_im} <= {tw_im, -tw_re};
3'd3: {mx_re, mx_im} <= {-tw_re, tw_im};
3'd4: {mx_re, mx_im} <= {-tw_re, -tw_im};
3'd5: {mx_re, mx_im} <= {tw_im, tw_re};
default: {mx_re, mx_im} <= {{WIDTH{1'bx}}, {WIDTH{1'bx}}};
endcase
end
end
always @(posedge clock) begin
ff_re <= mx_re;
ff_im <= mx_im;
end
assign tc_re = TC_FF ? ff_re : mx_re;
assign tc_im = TC_FF ? ff_im : mx_im;
endmodule
| 6.684026 |
module twiddlefactors (
input wire clk,
input wire [ 3:0] addr,
input wire addr_nd,
output reg signed [23:0] tf_out
);
always @(posedge clk) begin
if (addr_nd) begin
case (addr)
4'd0: tf_out <= {12'sd1024, -12'sd0};
4'd1: tf_out <= {12'sd1004, -12'sd200};
4'd2: tf_out <= {12'sd946, -12'sd392};
4'd3: tf_out <= {12'sd851, -12'sd569};
4'd4: tf_out <= {12'sd724, -12'sd724};
4'd5: tf_out <= {12'sd569, -12'sd851};
4'd6: tf_out <= {12'sd392, -12'sd946};
4'd7: tf_out <= {12'sd200, -12'sd1004};
4'd8: tf_out <= {12'sd0, -12'sd1024};
4'd9: tf_out <= {-12'sd200, -12'sd1004};
4'd10: tf_out <= {-12'sd392, -12'sd946};
4'd11: tf_out <= {-12'sd569, -12'sd851};
4'd12: tf_out <= {-12'sd724, -12'sd724};
4'd13: tf_out <= {-12'sd851, -12'sd569};
4'd14: tf_out <= {-12'sd946, -12'sd392};
4'd15: tf_out <= {-12'sd1004, -12'sd200};
default: begin
tf_out <= 24'd0;
end
endcase
end
end
endmodule
| 7.097069 |
module Twiddlegen #(
parameter length = 32,
parameter R = 5,
parameter N = 32,
parameter TWIDDLEFILE = "TWIDDLE.txt"
) (
input i_clk,
input i_rst,
input [R-2:0] i_twiddle_exponent,
output reg [length-1:0] o_twiddle_cos,
output reg [length-1:0] o_twiddle_sin
);
reg [2*length-1:0] TWROM[0:N/2-1];
initial $readmemh(TWIDDLEFILE, TWROM);
always @(posedge i_clk) begin
if (i_rst) begin
o_twiddle_cos <= 0;
o_twiddle_sin <= 0;
end else begin
o_twiddle_cos <= TWROM[i_twiddle_exponent][2*length-1:length];
o_twiddle_sin <= TWROM[i_twiddle_exponent][length-1:0];
end
end
endmodule
| 8.545007 |
module twiddleROM #(
parameter N = 32,
word_size = 16,
memory_file = "/home/saviour/study/fft_hdl/data/out.real"
) (
input wire [ $clog2(N)-1:0] read_address,
output wire [word_size*2-1:0] twiddle
// output reg [word_size-1: 0] twiddle_im
);
//CALLING THEM TWIDDLE FACTORS IS NOT ACCURATE
//I JUST COULDN'T THINK OF A BETTER NAME
reg [word_size*2-1:0] twiddleROM[N-1:0];
//reg [$clog2(N)-1: 0] reg_read_address;
initial begin
$readmemh(memory_file, twiddleROM);
end
// initial begin
// $dumpfile("twiddleROM.vcd");
// $dumpvars(0, twiddleROM);
// end
//reg_read_address <= read_address;
assign twiddle = {twiddleROM[read_address]};
// assign twiddle = {twiddle_real_ROM[read_address] ,twiddle_im_ROM[read_address]};
endmodule
| 7.230195 |
module twiddle_LUT (
input clk,
input rst,
input [3:0] twiddle_num,
output reg [15:0] twiddle_val_real,
output reg [15:0] twiddle_val_imag
);
always @(posedge clk, posedge rst) begin
if (rst) begin
twiddle_val_real <= 16'b0;
twiddle_val_imag <= 16'b0;
end else begin
case (twiddle_num)
4'd0: begin
twiddle_val_real <= 16'b0111111111111111;
twiddle_val_imag <= 16'b0000000000000000;
end
4'd1: begin
twiddle_val_real <= 16'b0111011001000001;
twiddle_val_imag <= 16'b1100111100000101;
end
4'd2: begin
twiddle_val_real <= 16'b0101101010000010;
twiddle_val_imag <= 16'b1010010101111110;
end
4'd3: begin
twiddle_val_real <= 16'b0011000011111011;
twiddle_val_imag <= 16'b1000100110111111;
end
4'd4: begin
twiddle_val_real <= 16'b0000000000000000;
twiddle_val_imag <= 16'b1000000000000001;
end
4'd5: begin
twiddle_val_real <= 16'b1100111100000101;
twiddle_val_imag <= 16'b1000100110111111;
end
4'd6: begin
twiddle_val_real <= 16'b1010010101111110;
twiddle_val_imag <= 16'b1010010101111110;
end
4'd7: begin
twiddle_val_real <= 16'b1000100110111111;
twiddle_val_imag <= 16'b1100111100000101;
end
4'd8: begin
twiddle_val_real <= 16'b1000000000000001;
twiddle_val_imag <= 16'b0000000000000000;
end
4'd9: begin
twiddle_val_real <= 16'b1000100110111111;
twiddle_val_imag <= 16'b0011000011111011;
end
4'd10: begin
twiddle_val_real <= 16'b1010010101111110;
twiddle_val_imag <= 16'b0101101010000010;
end
4'd11: begin
twiddle_val_real <= 16'b1100111100000101;
twiddle_val_imag <= 16'b0111011001000001;
end
4'd12: begin
twiddle_val_real <= 16'b0000000000000000;
twiddle_val_imag <= 16'b0111111111111111;
end
4'd13: begin
twiddle_val_real <= 16'b0011000011111011;
twiddle_val_imag <= 16'b0111011001000001;
end
4'd14: begin
twiddle_val_real <= 16'b0101101010000010;
twiddle_val_imag <= 16'b0101101010000010;
end
4'd15: begin
twiddle_val_real <= 16'b0111011001000001;
twiddle_val_imag <= 16'b0011000011111011;
end
endcase
end
end
endmodule
| 6.840287 |
module twiddle_mod #(
parameter division = 16,
parameter fft_length = 16,
parameter ff_in_en = 0,
parameter ff_out_en = 0,
parameter dsp_ff_num = 0
) (
input sys_clk,
input sys_nrst,
input sys_en,
output [16 : 0] tw_fac_r,
output [16 : 0] tw_fac_i,
output cordic_rdy
);
`include "logfunc.vh"
localparam phase_bw = 16;
localparam cordic_bw = clog2(division);
localparam tick_bw = clog2(fft_length);
localparam pwr_cmp = clog4(fft_length) - clog4(division);
localparam offset = (pwr_cmp > 0) ? 1 : 0;
localparam tick_ff_path_dsp = (dsp_ff_num > 0) ? pwr_cmp * dsp_ff_num : 0;
localparam tick_ff_path_num = (ff_in_en + ff_out_en) * 2;
localparam cordic_offset = (tick_ff_path_num) * (pwr_cmp + 1) + tick_ff_path_dsp;
localparam cordic_rdy_cnt = 17 + (fft_length / 4) - cordic_offset;
localparam cordic_init_cnt = (division / 4) * offset - cordic_offset;
reg cordic_rdy_r;
reg [ tick_bw : 0] cordic_init;
reg [cordic_bw-1 : 0] phase_cnt;
always @(posedge sys_clk or negedge sys_nrst) begin
if (!sys_nrst) begin
phase_cnt <= 'd0;
end else begin
if (sys_en) begin
if (cordic_init[0+:(cordic_bw-2)] == {(cordic_bw - 2) {1'b1}}) begin
phase_cnt <= 'd0;
end else begin
phase_cnt <= phase_cnt -
{{(cordic_bw-2){1'b0}}, cordic_init[cordic_bw-2], cordic_init[cordic_bw-1]};
end
end
end
end
cordic #(
.pipeline(16)
) cordic_s0 (
.sys_clk (sys_clk),
.sys_nrst (sys_nrst),
.sys_en (sys_en),
.phase_in ({phase_cnt, {(phase_bw-cordic_bw){1'b0}}}),
.cos (tw_fac_r),
.sin (tw_fac_i),
.eps ()
);
always @(posedge sys_clk or negedge sys_nrst) begin
if (!sys_nrst) begin
cordic_init <= cordic_init_cnt;
end else if (sys_en) begin
cordic_init <= cordic_init + 'd1;
end
end
always @(posedge sys_clk) begin
if (!sys_nrst) begin
cordic_rdy_r <= 1'b0;
end else if (sys_en) begin
if (cordic_init == cordic_rdy_cnt) begin
cordic_rdy_r <= 1'b1;
end
end
end
assign cordic_rdy = cordic_rdy_r;
endmodule
| 8.792314 |
module twiddle_rom #(
parameter FILE_REAL = "hdl/twiddle_real.list",
parameter FILE_IMAJ = "hdl/twiddle_imag.list",
parameter addr_w = 7,
parameter data_w = 8
) (
input wire clk,
input wire [addr_w-1:0] addr,
output reg [data_w-1:0] dout_real,
output reg [data_w-1:0] dout_imag
);
reg [data_w-1:0] rom_real[(1 << addr_w)-1:0];
reg [data_w-1:0] rom_imag[(1 << addr_w)-1:0];
initial begin
if (FILE_REAL) $readmemh(FILE_REAL, rom_real);
if (FILE_IMAJ) $readmemh(FILE_IMAJ, rom_imag);
end
always @(posedge clk) begin
dout_real = rom_real[addr];
dout_imag = rom_imag[addr];
end
endmodule
| 8.00741 |
module twiddle_rom_imag #(
parameter N = 16
) (
input clk,
input rst,
output reg [N-1:0] reg0_i,
output reg [N-1:0] reg1_i,
output reg [N-1:0] reg2_i,
output reg [N-1:0] reg3_i,
output reg [N-1:0] reg4_i,
output reg [N-1:0] reg5_i,
output reg [N-1:0] reg6_i,
output reg [N-1:0] reg7_i,
output reg [N-1:0] reg8_i,
output reg [N-1:0] reg9_i,
output reg [N-1:0] reg10_i,
output reg [N-1:0] reg11_i,
output reg [N-1:0] reg12_i,
output reg [N-1:0] reg13_i,
output reg [N-1:0] reg14_i,
output reg [N-1:0] reg15_i
);
always @(posedge clk or posedge rst) begin
if (rst) begin
reg0_i <= 0;
reg1_i <= 0;
reg2_i <= 0;
reg3_i <= 0;
reg4_i <= 0;
reg5_i <= 0;
reg6_i <= 0;
reg7_i <= 0;
reg8_i <= 0;
reg9_i <= 0;
reg10_i <= 0;
reg11_i <= 0;
reg12_i <= 0;
reg13_i <= 0;
reg14_i <= 0;
reg15_i <= 0;
end else begin
reg0_i <= 16'b0000000000000000;
reg1_i <= 16'b0000000000110001;
reg2_i <= 16'b0000000001100010;
reg3_i <= 16'b0000000010001110;
reg4_i <= 16'b0000000010110100;
reg5_i <= 16'b0000000011010100;
reg6_i <= 16'b0000000011101100;
reg7_i <= 16'b0000000011111011;
reg8_i <= 16'b0000000100000000;
reg9_i <= 16'b0000000011111011;
reg10_i <= 16'b0000000011101100;
reg11_i <= 16'b0000000011010100;
reg12_i <= 16'b0000000010110100;
reg13_i <= 16'b0000000010001110;
reg14_i <= 16'b0000000001100010;
reg15_i <= 16'b0000000000110001;
end
end // always
endmodule
| 8.290644 |
module twiddle_rom_real #(
parameter N = 16
) (
input clk,
input rst,
output reg [N-1:0] reg0_r,
output reg [N-1:0] reg1_r,
output reg [N-1:0] reg2_r,
output reg [N-1:0] reg3_r,
output reg [N-1:0] reg4_r,
output reg [N-1:0] reg5_r,
output reg [N-1:0] reg6_r,
output reg [N-1:0] reg7_r,
output reg [N-1:0] reg8_r,
output reg [N-1:0] reg9_r,
output reg [N-1:0] reg10_r,
output reg [N-1:0] reg11_r,
output reg [N-1:0] reg12_r,
output reg [N-1:0] reg13_r,
output reg [N-1:0] reg14_r,
output reg [N-1:0] reg15_r
);
always @(posedge clk or posedge rst) begin
if (rst) begin
reg0_r <= 0;
reg1_r <= 0;
reg2_r <= 0;
reg3_r <= 0;
reg4_r <= 0;
reg5_r <= 0;
reg6_r <= 0;
reg7_r <= 0;
reg8_r <= 0;
reg9_r <= 0;
reg10_r <= 0;
reg11_r <= 0;
reg12_r <= 0;
reg13_r <= 0;
reg14_r <= 0;
reg15_r <= 0;
end else begin
reg0_r <= 16'b0000000100000000;
reg1_r <= 16'b0000000011111011;
reg2_r <= 16'b0000000011101100;
reg3_r <= 16'b0000000011010100;
reg4_r <= 16'b0000000010110100;
reg5_r <= 16'b0000000010001110;
reg6_r <= 16'b0000000001100010;
reg7_r <= 16'b0000000000110001;
reg8_r <= 16'b0000000000000000;
reg9_r <= 16'b1111111111001111;
reg10_r <= 16'b1111111110011110;
reg11_r <= 16'b1111111101110010;
reg12_r <= 16'b1111111101001100;
reg13_r <= 16'b1111111100101100;
reg14_r <= 16'b1111111100010100;
reg15_r <= 16'b1111111100000101;
end
end // always
endmodule
| 7.793548 |
module: twiddle_LUT
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module twiddle_tb;
// Inputs
reg clk;
reg rst;
reg [3:0] twiddle_num;
// Outputs
wire [15:0] twiddle_val_real;
wire [15:0] twiddle_val_imag;
// Instantiate the Unit Under Test (UUT)
twiddle_LUT uut (
.clk(clk),
.rst(rst),
.twiddle_num(twiddle_num),
.twiddle_val_real(twiddle_val_real),
.twiddle_val_imag(twiddle_val_imag)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
twiddle_num = 0;
#10 rst = 0;
// Add stimulus here
#40 twiddle_num = 0;
#80 twiddle_num = 4;
#120 twiddle_num = 8;
#160 twiddle_num = 12;
end
always #5 clk = ~clk;
endmodule
| 7.806959 |
module twi_core (
input clk,
input rst,
input wr, //we
input [7:0] data_in, //dat1
input [7:0] wr_addr, //adr1
output [7:0] i2cr,
output [7:0] i2rd,
output twi_scl_o,
input twi_sda_i,
output twi_sda_oen
);
parameter TWI_F = 1;
parameter START_SDA = 1200 / TWI_F + 1;
parameter SDA_SET = 1400 / TWI_F + 1;
parameter SDA_WAIT = 1200 / TWI_F + 1;
parameter START_SCL = START_SDA + 100 / TWI_F + 1;
parameter TWI_DONE = START_SCL + 1300 / TWI_F + 1;
parameter STOP_SCL = 50 / TWI_F + 1;
reg [7:0] rd_buf;
reg [11:0] cnt;
reg done;
reg [3:0] byte_cnt;
reg [7:0] i2wd_r;
reg [7:0] i2rd_r;
assign i2wd = i2wd_r;
assign i2rd = rd_buf;
reg en_r, init_r;
reg [2:0] cmd_r ;
wire cmd_start = cmd_r == 3'b000 && en_r ;
wire cmd_wr = cmd_r == 3'b001 && en_r ;
wire cmd_rd = cmd_r == 3'b010 && en_r ;
wire cmd_stop = cmd_r == 3'b011 && en_r ;
wire cmd_rd_no = cmd_r == 3'b100 && en_r ;
assign i2cr = {1'b0, cmd_r, 1'b0, done, init_r, en_r};
//register twir
always @(posedge clk) begin
if (rst) begin
en_r <= 1'b0;
init_r <= 1'b0;
cmd_r <= 3'b0;
end else if (wr_addr == `I2CR && wr) begin
en_r <= data_in[0];
init_r <= data_in[1];
cmd_r <= data_in[6:4];
end else begin
init_r <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) i2wd_r <= 8'b0;
else if (wr_addr == `I2WD && wr) i2wd_r <= data_in;
else if (cmd_wr && cnt == (SDA_SET * 2 + SDA_WAIT)) i2wd_r <= {i2wd_r[6:0], 1'b1};
end
always @(posedge clk) begin
if (rst) done <= 1'b0;
else if (wr_addr == `I2CR && wr) done <= data_in[2];
else if (init_r) done <= 1'b0;
else if ((cmd_start || cmd_stop) && cnt == TWI_DONE) done <= 1'b1;
else if ((cmd_wr || cmd_rd) && byte_cnt == 9) done <= 1'b1;
end
always @(posedge clk) begin
if (rst) byte_cnt <= 4'b0;
else if (init_r) byte_cnt <= 4'b0;
else if ((cmd_wr || cmd_rd) && (cnt == (SDA_SET * 2 + SDA_WAIT))) byte_cnt <= byte_cnt + 4'b1;
end
always @(posedge clk) begin
if (rst || ~en_r) cnt <= 12'b0;
else if ((cmd_start || cmd_stop) && init_r) cnt <= 12'b1;
else if ((cmd_start || cmd_stop) && cnt != 0) cnt <= cnt + 12'b1;
else if ((cmd_wr || cmd_rd) && init_r) cnt <= 12'b0;
else if ((cmd_wr || cmd_rd) && cnt < (SDA_SET * 2 + SDA_WAIT) && byte_cnt < 9)
cnt <= cnt + 12'b1;
else if ((cmd_wr || cmd_rd) && cnt == (SDA_SET * 2 + SDA_WAIT)) cnt <= 12'b0;
end
reg scl_o;
always @(posedge clk) begin
if (rst || ~en_r) begin
scl_o <= 1'b1;
end else if (cmd_start) begin
if (cnt == START_SCL) scl_o <= 1'b0;
end else if (cmd_wr || cmd_rd) begin
scl_o <= cnt == 12'b0 ? 1'b0 :
cnt == SDA_SET ? 1'b1 :
cnt == (SDA_SET+SDA_WAIT) ? 1'b0 : scl_o ;
end else if (cmd_stop && cnt == SDA_SET) begin
scl_o <= 1'b1;
end
end
reg sda_oen;
always @(posedge clk) begin
if (rst || ~en_r) begin
sda_oen <= 1'b1;
end else if (cmd_start) begin
if (cnt == START_SDA) sda_oen <= 1'b0;
end else if (cmd_wr) begin
sda_oen <= i2wd_r[7];
end else if (cmd_rd) begin
if (byte_cnt == 8 || byte_cnt == 9) sda_oen <= 1'b0; //master read ack
else sda_oen <= 1'b1;
end else if (cmd_stop) begin
if (init_r) sda_oen <= 1'b0;
else if (cnt == STOP_SCL + SDA_SET) sda_oen <= 1'b1;
end else if (cmd_rd_no) begin
sda_oen <= 1'b1; //master read no ack
end
end
always @(posedge clk) begin
if (rst) rd_buf <= 8'b0;
else if (cmd_rd && cnt == (SDA_SET + 100) && byte_cnt <= 7) rd_buf <= {rd_buf[6:0], twi_sda_i};
end
assign twi_scl_o = scl_o;
assign twi_sda_oen = sda_oen;
endmodule
| 7.255932 |
module twmux (
i0,
i1,
out,
s
);
parameter n = 16;
input [n-1:0] i0, i1;
input s;
output reg [n-1:0] out;
always @(s) begin
out = s ? i1 : i0;
end
endmodule
| 7.277553 |
module game (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
LEDR,
HEX3,
HEX1
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
output [6:0] HEX3;
output [6:0] HEX1;
output [9:0] LEDR; //test with leds
wire [3:0] score1, score2;
assign score1 = 4'd0;
assign score2 = 4'd0;
hex_decoder hex3 (
score1,
HEX3
);
hex_decoder hex0 (
score2,
HEX1
);
wire resetn;
assign resetn = KEY[0];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn, ld_top, ld_bottom, ld_left, ld_right, ld_color, enable;
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "black.mif";
wire [7:0] x_p;
wire [6:0] y_p;
wire [2:0] color_p;
process p0 (
.clk(CLOCK_50),
.enable(enable),
.resetn(resetn),
.ld_color(ld_color),
.color_in(SW[9:7]),
.x_out(x_p),
.y_out(y_p),
.color_out(color_p)
);
wire [7:0] x_b;
wire [6:0] y_b;
wire [2:0] color_b;
border_datapath d0 (
.clk(CLOCK_50),
.enable(writeEn),
.resetn(resetn),
.ld_top(ld_top),
.ld_bottom(ld_bottom),
.ld_left(ld_left),
.ld_right(ld_right),
.x_out(x_b),
.y_out(y_b),
.color_out(color_b)
);
wire hold;
control c0 (
.clk(CLOCK_50),
.resetn(resetn),
.go(!KEY[1]),
.ld_top(ld_top),
.ld_bottom(ld_bottom),
.ld_left(ld_left),
.ld_right(ld_right),
.writeEn(writeEn),
.ld_color(ld_color),
.enable(enable),
.hold(hold)
);
assign LEDR[0] = ld_top;
assign LEDR[1] = ld_bottom;
assign LEDR[2] = ld_left;
assign LEDR[3] = ld_right;
assign LEDR[4] = enable;
assign LEDR[9] = hold;
reg [7:0] x_temp;
reg [6:0] y_temp;
reg [2:0] color_temp;
always @(*) begin
if (ld_color) begin
x_temp = x_p;
y_temp = y_p;
color_temp = color_p;
end else begin
x_temp = x_b;
y_temp = y_b;
color_temp = color_b;
end
end
assign x = x_temp;
assign y = y_temp;
assign colour = color_temp;
endmodule
| 8.621551 |
module control (
input clk,
resetn,
go,
output reg ld_top,
ld_bottom,
ld_left,
ld_right,
writeEn,
ld_color,
enable,
output hold
);
wire delay_enable;
delay_counter dc0 (
.clk(clk),
.resetn(resetn),
.enable(writeEn),
.delay_enable(delay_enable)
); //count 1/60 sec
one_sec_counter o0 (
.clk60 (delay_enable),
.resetn (resetn),
.enable (writeEn),
.one_sec(hold)
); // count 1sec, hold change every 1 sec
reg [3:0] current_state, next_state;
localparam TOP = 4'd0,
TOP_WAIT = 4'd1,
BOTTOM = 4'd2,
BOTTOM_WAIT = 4'd3,
LEFT = 4'd4,
LEFT_WAIT = 4'd5,
RIGHT = 4'd6,
RIGHT_WAIT = 4'd7,
// LD_COLOR = 4'd8, // part3 starts...
// LD_COLOR_WAIT = 4'd9,
PLOT = 4'd8;
//reset
always @(posedge clk) begin
if (!resetn) current_state <= TOP;
else current_state <= next_state;
end
//state table
always @(*) begin : state_table
case (current_state)
TOP: next_state = hold ? TOP_WAIT : TOP;
TOP_WAIT: next_state = hold ? TOP_WAIT : BOTTOM;
BOTTOM: next_state = hold ? BOTTOM_WAIT : BOTTOM;
BOTTOM_WAIT: next_state = hold ? BOTTOM_WAIT : LEFT;
LEFT: next_state = hold ? LEFT_WAIT : LEFT;
LEFT_WAIT: next_state = hold ? LEFT_WAIT : RIGHT;
RIGHT: next_state = go ? RIGHT_WAIT : RIGHT;
RIGHT_WAIT: next_state = go ? RIGHT_WAIT : PLOT;
// LD_COLOR: next_state = PLOT;
// LD_COLOR_WAIT: next_state = go ? LD_COLOR_WAIT : PLOT;
PLOT: next_state = PLOT;
default: next_state = TOP;
endcase
end
//output logic aka output of datapath control signals
always @(*) begin
ld_top = 1'b0;
ld_bottom = 1'b0;
ld_left = 1'b0;
ld_right = 1'b0;
writeEn = 1'b0;
ld_color = 1'b0;
enable = 1'b0;
case (current_state)
TOP: begin
ld_top = 1'b1;
ld_bottom = 1'b0;
writeEn = 1'b1;
end
TOP_WAIT: begin
ld_top = 1'b1;
ld_bottom = 1'b0;
writeEn = 1'b1;
end
BOTTOM: begin
writeEn = 1'b1;
ld_top = 1'b0;
ld_bottom = 1'b1;
end
BOTTOM_WAIT: begin
writeEn = 1'b1;
ld_top = 1'b0;
ld_bottom = 1'b1;
end
LEFT: begin
writeEn = 1'b1;
ld_left = 1'b1;
end
LEFT_WAIT: begin
writeEn = 1'b1;
ld_left = 1'b1;
end
RIGHT: begin
writeEn = 1'b1;
ld_right = 1'b1;
end
RIGHT_WAIT: begin
writeEn = 1'b1;
ld_right = 1'b1;
end
// LD_COLOR: begin
// ld_color = 1'b1;
// writeEn = 1'b1;
// enable = 1'b1;
// end
// LD_COLOR_WAIT: begin
// // ld_color = 1'b1;
// end
PLOT: begin
ld_color = 1'b1;
writeEn = 1'b1;
enable = 1'b1;
end
endcase
end
endmodule
| 7.715617 |
module border_datapath (
input clk,
enable,
resetn,
ld_top,
ld_bottom,
ld_left,
ld_right,
input [2:0] color_in,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
reg [7:0] x;
reg [6:0] y;
reg [2:0] color;
always @(posedge clk) begin
if (!resetn) begin
x <= 8'b0;
y <= 7'b0;
color <= 3'b0;
end else begin
if (ld_top) begin
x <= 8'd74;
y <= 7'd10;
color <= 3'b010;
end else if (ld_left) begin
x <= 8'd50;
y <= 7'd10;
color <= 3'b111;
end else if (ld_bottom) begin
x <= 8'd74;
y <= 7'd108;
color <= 3'b010;
end else if (ld_right) begin
x <= 8'd110;
y <= 7'd10;
color <= 3'b111;
end
end
end
reg [7:0] counter;
//counter
always @(posedge clk) begin
if (!resetn) counter <= 8'd0;
else begin
if (enable) begin
if (ld_left || ld_right) begin
if (counter < 8'd100) counter <= counter + 1'b1;
else counter <= 7'd0;
end else begin
if (counter < 8'd12) counter <= counter + 1'b1;
else counter <= 8'd0;
end
// begin
// if (ld_top)
// begin
// if(counter < 8'd60)
// counter <= counter + 1'b1;
// else
// counter <= 8'd0;
// end
// else if (ld_bottom)
// begin
// if(counter < 8'd20)
// counter <= counter + 1'b1;
// else
// counter <= 8'd0;
// end
// end
end
end
end
reg [7:0] x_temp;
reg [6:0] y_temp;
always @(*) begin
x_temp = (ld_top || ld_bottom) ? (x + counter[7:0]) : x;
y_temp = (ld_left || ld_right) ? (y + counter[7:0]) : y;
end
assign x_out = x_temp;
assign y_out = y_temp;
assign color_out = color;
endmodule
| 6.538823 |
module delay_counter (
input clk,
resetn,
enable,
output delay_enable
);
reg [19:0] count;
always @(posedge clk) begin
if (!resetn) count <= 20'd833334;
else if (enable) begin
if (count == 20'd0) count <= 20'd833334;
else count <= count - 1'b1;
end
end
assign delay_enable = (count == 20'd0) ? 1 : 0;
endmodule
| 6.853164 |
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