code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,
input reset
);
reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp;
reg done_pool_temp;
reg out_data_available_temp;
integer i, j;
integer cycle_count;
always @(posedge clk) begin
if (reset || ~enable_pool || ~in_data_available) begin
out_data_temp <= 0;
done_pool_temp <= 0;
out_data_available_temp <= 0;
cycle_count <= 0;
end else if (in_data_available) begin
cycle_count = cycle_count + 1;
out_data_available_temp <= 1;
case (pool_window_size)
1: begin
out_data_temp <= inp_data;
end
2: begin
for (i = 0; i < `DESIGN_SIZE / 2; i = i + 8) begin
out_data_temp[i+:8] <= (inp_data[i*2+:8] + inp_data[i*2+8+:8]) >> 1;
end
end
4: begin
for (i = 0; i < `DESIGN_SIZE / 4; i = i + 8) begin
//TODO: If 3 adders are the critical path, break into 2 cycles
out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2;
end
end
endcase
if (cycle_count == `DESIGN_SIZE) begin
done_pool_temp <= 1'b1;
end
end
end
assign out_data = enable_pool ? out_data_temp : inp_data;
assign out_data_available = enable_pool ? out_data_available_temp : in_data_available;
assign done_pool = enable_pool ? done_pool_temp : 1'b1;
//Adding a dummy signal to use validity_mask input, to make ODIN happy
wire [`MASK_WIDTH-1:0] dummy;
assign dummy = validity_mask;
endmodule
| 6.865188 |
module ReLU(
// input [`DWIDTH-1:0] inp_data,
// output[`DWIDTH-1:0] out_data
//);
//
//assign out_data = inp_data[`DWIDTH-1] ? {`DWIDTH{1'b0}} : inp_data;
//
//endmodule
| 6.652528 |
module TPU_Adder (
input [32 * 8 - 1:0] data_in1,
input [32 * 8 - 1:0] data_in2,
output [32 * 8 - 1:0] data_out,
output overflow
);
wire [31:0] overflows;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin
Float8Adder inst (
.iNum1(data_in1[8*i+7:8*i]),
.iNum2(data_in2[8*i+7:8*i]),
.oNum(data_out[8*i+7:8*i]),
.overflow(overflows[i])
);
end
endgenerate
assign overflow = |overflows;
endmodule
| 7.630956 |
module TPU_Conv_25 (
input [25 * 8 - 1:0] data_in1,
input [25 * 8 - 1:0] data_in2,
output [7:0] data_out,
output overflow
);
wire [24:0] overflows;
wire [25 * 15 - 1:0] mult_out;
wire [25 * 15 - 1:0] add_out;
assign add_out[14:0] = mult_out[14:0];
assign overflows[0] = 1'b0;
generate
genvar i;
for (i = 0; i < 25; i = i + 1) begin : Mult
Float8Mult inst (
.iNum1(data_in1[8*i+7:8*i]),
.iNum2(data_in2[8*i+7:8*i]),
.oNum (mult_out[15*i+14:15*i])
);
end
for (i = 1; i < 25; i = i + 1) begin : Add
Float8Adder inst (
.iNum1(add_out[15*i-1:15*i-15]),
.iNum2(mult_out[15*i+14:15*i]),
.oNum(add_out[15*i+14:15*i]),
.overflow(overflows[i])
);
end
endgenerate
assign overflow = |overflows;
assign data_out = add_out[25*15-1:25*15-8];
endmodule
| 6.766492 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1;
input clk;
`ifdef SIMULATION
reg [`DWIDTH-1:0] ram[((1<<`AWIDTH)-1):0];
reg [31:0] i;
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q0[i*`DWIDTH+:`DWIDTH] <= ram[addr0+i];
end
end
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q1[i*`DWIDTH+:`DWIDTH] <= ram[addr1+i];
end
end
`else
//BRAMs available in VTR FPGA architectures have one bit write-enables.
//So let's combine multiple bits into 1. We don't have a usecase of
//writing/not-writing only parts of the word anyway.
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_accum,
output reg done_tpu
);
reg [3:0] state;
`define STATE_INIT 4'b0000
`define STATE_MATMUL 4'b0001
`define STATE_NORM 4'b0010
`define STATE_POOL 4'b0011
`define STATE_ACTIVATION 4'b0100
`define STATE_DONE 4'b0101
//////////////////////////////////////////////////////
// Assumption: We will always run matmul first. That is, matmul is not optional.
// The other blocks - norm, act, pool - are optional.
// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation
//////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= `STATE_INIT;
start_mat_mul <= 1'b0;
done_tpu <= 1'b0;
end else begin
case (state)
`STATE_INIT: begin
if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin
if (enable_matmul == 1'b1) begin
start_mat_mul <= 1'b1;
state <= `STATE_MATMUL;
end
end
end
//start_mat_mul is kinda used as a reset in some logic
//inside the matmul unit. So, we can't make it 0 right away after
//asserting it.
`STATE_MATMUL: begin
if (done_mat_mul == 1'b1) begin
start_mat_mul <= 1'b0;
if (save_output_to_accum) begin
state <= `STATE_DONE;
end else if (enable_norm) begin
state <= `STATE_NORM;
end else if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end else begin
start_mat_mul <= 1'b1;
end
end
`STATE_NORM: begin
if (done_norm == 1'b1) begin
if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_POOL: begin
if (done_pool == 1'b1) begin
if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_ACTIVATION: begin
if (done_activation == 1'b1) begin
state <= `STATE_DONE;
end
end
`STATE_DONE: begin
//We need to write start_tpu to 0 in the CFG block to get out of this state
if (start_tpu == 1'b0) begin
state <= `STATE_INIT;
done_tpu <= 0;
end else begin
done_tpu <= 1;
end
end
endcase
end
end
endmodule
| 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,
input reset
);
reg in_data_available_flopped;
reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped;
reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp;
reg done_pool_temp;
reg out_data_available_temp;
reg [31:0] i, j;
reg [31:0] cycle_count;
always @(posedge clk) begin
if (reset || ~enable_pool || ~in_data_available) begin
out_data_temp <= 0;
done_pool_temp <= 0;
out_data_available_temp <= 0;
cycle_count <= 0;
in_data_available_flopped <= in_data_available;
inp_data_flopped <= inp_data;
end else if (in_data_available) begin
cycle_count = cycle_count + 1;
out_data_available_temp <= 1;
case (pool_window_size)
1: begin
out_data_temp <= inp_data;
end
2: begin
for (i = 0; i < `DESIGN_SIZE / 2; i = i + 8) begin
out_data_temp[i+:8] <= (inp_data[i*2+:8] + inp_data[i*2+8+:8]) >> 1;
end
end
4: begin
for (i = 0; i < `DESIGN_SIZE / 4; i = i + 8) begin
//TODO: If 3 adders are the critical path, break into 2 cycles
out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2;
end
end
endcase
if (cycle_count == `DESIGN_SIZE) begin
done_pool_temp <= 1'b1;
end
end
end
assign out_data = enable_pool ? out_data_temp : inp_data_flopped;
assign out_data_available = enable_pool ? out_data_available_temp : in_data_available_flopped;
assign done_pool = enable_pool ? done_pool_temp : 1'b1;
//Adding a dummy signal to use validity_mask input, to make ODIN happy
wire [`MASK_WIDTH-1:0] dummy;
assign dummy = validity_mask;
endmodule
| 6.865188 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`DESIGN_SIZE*`DWIDTH-1:0] d0;
input [`DESIGN_SIZE*`DWIDTH-1:0] d1;
input [`DESIGN_SIZE-1:0] we0;
input [`DESIGN_SIZE-1:0] we1;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q0;
output reg [`DESIGN_SIZE*`DWIDTH-1:0] q1;
input clk;
`ifdef SIMULATION
reg [`DWIDTH-1:0] ram[((1<<`AWIDTH)-1):0];
reg [31:0] i;
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we0[i]) ram[addr0+i] <= d0[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q0[i*`DWIDTH+:`DWIDTH] <= ram[addr0+i];
end
end
always @(posedge clk) begin
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
if (we1[i]) ram[addr0+i] <= d1[i*`DWIDTH+:`DWIDTH];
end
for (i = 0; i < `DESIGN_SIZE; i = i + 1) begin
q1[i*`DWIDTH+:`DWIDTH] <= ram[addr1+i];
end
end
`else
//BRAMs available in VTR FPGA architectures have one bit write-enables.
//So let's combine multiple bits into 1. We don't have a usecase of
//writing/not-writing only parts of the word anyway.
wire we0_coalesced;
assign we0_coalesced = |we0;
wire we1_coalesced;
assign we1_coalesced = |we1;
dual_port_ram u_dual_port_ram (
.addr1(addr0),
.we1 (we0_coalesced),
.data1(d0),
.out1 (q0),
.addr2(addr1),
.we2 (we1_coalesced),
.data2(d1),
.out2 (q1),
.clk (clk)
);
`endif
endmodule
| 6.838627 |
module control (
input clk,
input reset,
input start_tpu,
input enable_matmul,
input enable_norm,
input enable_activation,
input enable_pool,
output reg start_mat_mul,
input done_mat_mul,
input done_norm,
input done_pool,
input done_activation,
input save_output_to_accum,
output reg done_tpu
);
reg [3:0] state;
`define STATE_INIT 4'b0000
`define STATE_MATMUL 4'b0001
`define STATE_NORM 4'b0010
`define STATE_POOL 4'b0011
`define STATE_ACTIVATION 4'b0100
`define STATE_DONE 4'b0101
//////////////////////////////////////////////////////
// Assumption: We will always run matmul first. That is, matmul is not optional.
// The other blocks - norm, act, pool - are optional.
// Assumption: Order is fixed: Matmul -> Norm -> Pool -> Activation
//////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= `STATE_INIT;
start_mat_mul <= 1'b0;
done_tpu <= 1'b0;
end else begin
case (state)
`STATE_INIT: begin
if ((start_tpu == 1'b1) && (done_tpu == 1'b0)) begin
if (enable_matmul == 1'b1) begin
start_mat_mul <= 1'b1;
state <= `STATE_MATMUL;
end
end
end
//start_mat_mul is kinda used as a reset in some logic
//inside the matmul unit. So, we can't make it 0 right away after
//asserting it.
`STATE_MATMUL: begin
if (done_mat_mul == 1'b1) begin
start_mat_mul <= 1'b0;
if (save_output_to_accum) begin
state <= `STATE_DONE;
end else if (enable_norm) begin
state <= `STATE_NORM;
end else if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end else begin
start_mat_mul <= 1'b1;
end
end
`STATE_NORM: begin
if (done_norm == 1'b1) begin
if (enable_pool) begin
state <= `STATE_POOL;
end else if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_POOL: begin
if (done_pool == 1'b1) begin
if (enable_activation) begin
state <= `STATE_ACTIVATION;
end else begin
state <= `STATE_DONE;
end
end
end
`STATE_ACTIVATION: begin
if (done_activation == 1'b1) begin
state <= `STATE_DONE;
end
end
`STATE_DONE: begin
//We need to write start_tpu to 0 in the CFG block to get out of this state
if (start_tpu == 1'b0) begin
state <= `STATE_INIT;
done_tpu <= 0;
end else begin
done_tpu <= 1;
end
end
endcase
end
end
endmodule
| 7.715617 |
module pool (
input enable_pool,
input in_data_available,
input [`MAX_BITS_POOL-1:0] pool_window_size,
input [`DESIGN_SIZE*`DWIDTH-1:0] inp_data,
output [`DESIGN_SIZE*`DWIDTH-1:0] out_data,
output out_data_available,
input [`MASK_WIDTH-1:0] validity_mask,
output done_pool,
input clk,
input reset
);
reg in_data_available_flopped;
reg [`DESIGN_SIZE*`DWIDTH-1:0] inp_data_flopped;
reg [`DESIGN_SIZE*`DWIDTH-1:0] out_data_temp;
reg done_pool_temp;
reg out_data_available_temp;
reg [31:0] i, j;
reg [31:0] cycle_count;
always @(posedge clk) begin
if (reset || ~enable_pool || ~in_data_available) begin
out_data_temp <= 0;
done_pool_temp <= 0;
out_data_available_temp <= 0;
cycle_count <= 0;
in_data_available_flopped <= in_data_available;
inp_data_flopped <= inp_data;
end else if (in_data_available) begin
cycle_count = cycle_count + 1;
out_data_available_temp <= 1;
case (pool_window_size)
1: begin
out_data_temp <= inp_data;
end
2: begin
for (i = 0; i < `DESIGN_SIZE / 2; i = i + 8) begin
out_data_temp[i+:8] <= (inp_data[i*2+:8] + inp_data[i*2+8+:8]) >> 1;
end
end
4: begin
for (i = 0; i < `DESIGN_SIZE / 4; i = i + 8) begin
//TODO: If 3 adders are the critical path, break into 2 cycles
out_data_temp[ i +: 8] <= (inp_data[i*4 +: 8] + inp_data[i*4 + 8 +: 8] + inp_data[i*4 + 16 +: 8] + inp_data[i*4 + 24 +: 8]) >> 2;
end
end
endcase
if (cycle_count == `DESIGN_SIZE) begin
done_pool_temp <= 1'b1;
end
end
end
assign out_data = enable_pool ? out_data_temp : inp_data_flopped;
assign out_data_available = enable_pool ? out_data_available_temp : in_data_available_flopped;
assign done_pool = enable_pool ? done_pool_temp : 1'b1;
//Adding a dummy signal to use validity_mask input, to make ODIN happy
wire [`MASK_WIDTH-1:0] dummy;
assign dummy = validity_mask;
endmodule
| 6.865188 |
module TPU_MultAdd (
input [128 * 8 - 1:0] data_in1,
input [128 * 8 - 1:0] data_in2,
output [14:0] data_out,
output wire overflow
);
wire [127:0] overflows;
wire [128 * 15 - 1:0] mult_out;
wire [128 * 15 - 1:0] add_out;
assign add_out[14:0] = mult_out[14:0];
assign overflows[0] = 1'b0;
genvar i;
generate
for (i = 0; i < 128; i = i + 1) begin : MULT
Float8Mult multInst (
.iNum1(data_in1[i*8+7:i*8]),
.iNum2(data_in2[i*8+7:i*8]),
.oNum(data_out[i*15+14:i*15])
);
end
for (i = 1; i < 128; i = i + 1) begin : ADD
Float8Adder inst (
.iNum1(add_out[15*i-1:15*i-15]),
.iNum2(mult_out[15*i+14:15*i]),
.oNum(add_out[15*i+14:15*i]),
.overflow(overflows[i])
);
end
endgenerate
assign overflow = |overflows;
assign data_out = add_out[128*15-1:128*15-8];
endmodule
| 6.581073 |
module mem_icache_12_7 (
resetn,
// CPU data bus
bus_clk,
bus_address,
bus_readdata,
bus_writedata,
bus_byteen,
bus_en,
bus_wren,
bus_wait,
// Mem hierarchy
mem_clk,
mem_filladdr,
mem_filldata,
mem_fillwe,
bus_flush, // runs on mem_clk
// Cache signals
cache_hit,
cache_miss,
mem_icache_address,
mem_icache_data,
mem_icache_out,
mem_icache_byteen,
mem_icache_wren
);
// In bits, subtract 3 for bytes
parameter CACHELINESIZE = 2 ** 12; // 128
parameter CACHEDEPTH = 2 ** 7; // 64
parameter TAGSIZE = 32 - 7 - 12 + 3;
`define TAGRANGE 31:32-TAGSIZE
`define OFFSETRANGE 7-1+12-3:12-3
// selects 32-bit word
`define OFFSETWORDRANGE 7-1+12-3:2
input resetn;
// CPU data bus
input bus_clk;
input [31:0] bus_address;
output [31:0] bus_readdata;
input [31:0] bus_writedata;
input [3:0] bus_byteen;
input bus_en;
input bus_wren;
output bus_wait;
input bus_flush;
// Mem hierarchy
input mem_clk;
input [31:0] mem_filladdr;
input [CACHELINESIZE-1:0] mem_filldata;
input mem_fillwe;
// Cache signals
output cache_hit;
output cache_miss;
//wire [TAGSIZE-1:0] cache_tagout;
//wire cache_validout;
wire [32-1:0] cache_dataout;
//wire [CACHELINESIZE-1:0] cache_lineout;
input [31:0] mem_icache_address;
input [CACHELINESIZE-1:0] mem_icache_data;
output [31:0] mem_icache_out;
input [CACHELINESIZE/8-1:0] mem_icache_byteen;
input mem_icache_wren;
//wire tagmatch;
reg [32-1:0] bus_address_saved;
parameter [1:0] S_IDLE = 2'b00, S_TAGLOOKUP = 2'b01, S_RESULT = 2'b10;
//reg [1:0] cache_state;
wire cache_hit;
//reg [7-1:0] count;
// always@(posedge mem_clk)
// if (bus_flush)
// count <= count + 1'b1;
dpram1_26_67108864_32 data1 (
.clk(bus_clk),
.address_a(bus_address[27:2]),
.address_b(mem_icache_address[25:0]),
.wren_a(1'b0),
.wren_b(mem_icache_wren),
.data_a(0),
.data_b(mem_icache_data),
.byteen_a(-1),
.byteen_b(mem_icache_byteen),
.out_a(cache_dataout),
.out_b(mem_icache_out)
);
assign bus_readdata = cache_dataout;
// Save offset to make sure still asking for same data
always @(posedge bus_clk or negedge resetn)
if (!resetn) bus_address_saved <= 0;
else bus_address_saved <= bus_address;
assign cache_hit = 1'b1;
assign cache_miss = bus_en && ~cache_hit;
assign bus_wait = bus_en & ~cache_hit;
endmodule
| 6.941324 |
module pipe_1_28 (
d,
clk,
resetn,
en,
squash,
q
);
input [1-1:0] d;
input clk;
input resetn;
input [28-1:0] en;
input [28-1:0] squash;
output [1*(28+1)-1:0] q;
reg [1*28-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[1-1:0] <= 0;
else if (en[0]) tq[1-1:0] <= d;
// All the rest registers
for (i = 1; i < 28; i = i + 1)
if (!resetn || squash[i]) tq[i*1+:1] <= 0;
else if (en[i]) tq[i*1+:1] <= tq[(i-1)*1+:1];
end
assign q[1-1:0] = d;
assign q[1*(28+1)-1:1] = tq;
endmodule
| 6.9482 |
module pipe_8_28 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input [28-1:0] en;
input [28-1:0] squash;
output [8*(28+1)-1:0] q;
reg [8*28-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[8-1:0] <= 0;
else if (en[0]) tq[8-1:0] <= d;
// All the rest registers
for (i = 1; i < 28; i = i + 1)
if (!resetn || squash[i]) tq[i*8+:8] <= 0;
else if (en[i]) tq[i*8+:8] <= tq[(i-1)*8+:8];
end
assign q[8-1:0] = d;
assign q[8*(28+1)-1:8] = tq;
endmodule
| 7.094266 |
module pipe_8_28 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input [28-1:0] en;
input [28-1:0] squash;
output [8*(28+1)-1:0] q;
reg [8*28-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[8-1:0] <= 0;
else if (en[0]) tq[8-1:0] <= d;
// All the rest registers
for (i = 1; i < 28; i = i + 1)
if (!resetn || squash[i]) tq[i*8+:8] <= 0;
else if (en[i]) tq[i*8+:8] <= tq[(i-1)*8+:8];
end
assign q[8-1:0] = d;
assign q[8*(28+1)-1:8] = tq;
endmodule
| 7.094266 |
module bfloat_adder_16 (
input clk,
input resetn,
input en,
input stall,
input [16-1:0] a,
input [16-1:0] b,
output reg [16-1:0] out
);
always @(posedge clk) begin
if (!resetn) out <= 'h0;
else if (en) out <= a + b;
end
endmodule
| 6.882044 |
module ram_wrapper_5_32_32 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [5-1:0] address_a;
input [5-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden_b;
input [32-1:0] data_a;
input [32-1:0] data_b;
output [32-1:0] out_a;
output [32-1:0] out_b;
reg [5-1:0] q_address_a;
reg [5-1:0] q_address_b;
reg [5-1:0] mux_address_b;
// not connect ports
wire rden_a_nc;
assign rden_a_nc = rden_a;
dpram_5_32_32 dpram1 (
.clk(clk),
.address_a(address_a),
.address_b(mux_address_b),
.wren_a(wren_a),
.wren_b(wren_b),
.data_a(data_a),
.data_b(data_b),
.out_a(out_a),
.out_b(out_b)
);
always @(posedge clk) begin
if (!resetn) begin
q_address_a <= 'h0;
q_address_b <= 'h0;
end else begin
if (rden_b) q_address_b <= address_b;
end
end
always @(*) begin
if (rden_b) mux_address_b = address_b;
else mux_address_b = q_address_b;
end
endmodule
| 6.914131 |
module dpram_7_128_8 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input [7-1:0] address_a;
input [7-1:0] address_b;
input wren_a;
input wren_b;
input [8-1:0] data_a;
input [8-1:0] data_b;
output [8-1:0] out_a;
output [8-1:0] out_b;
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
endmodule
| 7.16071 |
module vregfile_inc_32_8_3 (
clk,
resetn,
a_reg,
a_en,
a_readdataout,
c_reg,
c_writedatain,
c_we
);
input clk;
input resetn;
input a_en;
input [3-1:0] a_reg, c_reg;
output [32-1:0] a_readdataout;
input [32-1:0] c_writedatain;
input c_we;
ram_wrapper_3_8_32 reg_file1 (
.clk(clk),
.resetn(resetn),
.rden_a(1'b0),
.rden_b(a_en),
.address_a(c_reg[3-1:0]),
.address_b(a_reg[3-1:0]),
.wren_a(c_we & (|c_reg)),
.wren_b(1'b0),
.data_a(c_writedatain),
.data_b(0),
.out_a(),
.out_b(a_readdataout)
);
endmodule
| 7.120329 |
module local_mult_17_17_34 (
dataa,
datab,
clock,
clken,
aclr,
result
);
input [17-1:0] dataa;
input [17-1:0] datab;
input clock;
input clken;
input aclr;
output reg [34-1:0] result;
wire [17-1:0] unsignedinputA;
wire [17-1:0] unsignedinputB;
wire [34-1:0] unsignedoutputP;
wire gated_clock;
assign unsignedinputA = dataa;
assign unsignedinputB = datab;
assign unsignedoutputP = unsignedinputA * unsignedinputB;
assign gated_clock = clock & clken;
always @(posedge gated_clock) begin
if (aclr) begin
result <= 0;
end else result <= unsignedoutputP;
end
endmodule
| 6.672015 |
module ram_wrapper_7_128_128 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [7-1:0] address_a;
input [7-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden_b;
input [128-1:0] data_a;
input [128-1:0] data_b;
output [128-1:0] out_a;
output [128-1:0] out_b;
reg [7-1:0] q_address_a;
reg [7-1:0] q_address_b;
reg [7-1:0] mux_address_b;
// not connect ports
wire rden_a_nc;
assign rden_a_nc = rden_a;
dpram_7_128_128 dpram1 (
.clk(clk),
.address_a(address_a),
.address_b(mux_address_b),
.wren_a(wren_a),
.wren_b(wren_b),
.data_a(data_a),
.data_b(data_b),
.out_a(out_a),
.out_b(out_b)
);
always @(posedge clk) begin
if (!resetn) begin
q_address_a <= 'h0;
q_address_b <= 'h0;
end else begin
if (rden_b) q_address_b <= address_b;
end
end
always @(*) begin
if (rden_b) mux_address_b = address_b;
else mux_address_b = q_address_b;
end
endmodule
| 7.021767 |
module dpram1_22_67108864_512 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteen_a,
byteen_b,
out_a,
out_b
);
// parameter AWIDTH=10;
// parameter NUM_WORDS=1024;
// parameter DWIDTH=32;
// parameter LOG2DWIDTH = $clog2(DWIDTH);
input clk;
input [(22-1):0] address_a;
input [(22-1):0] address_b;
input wren_a;
input wren_b;
input [(512/8)-1:0] byteen_a;
input [(512/8)-1:0] byteen_b;
input [(512-1):0] data_a;
input [(512-1):0] data_b;
output reg [(512-1):0] out_a;
output reg [(512-1):0] out_b;
`ifdef SIMULATION_MEMORY
integer i;
integer k;
//reg [32-1:0] ram [67108864-1:0];
reg [(((1096-1)-(0)+1)*((32-1)-(0)+1))-1 : 0] ram;
reg [25:0] addr_a;
reg [25:0] addr_b;
initial begin
//This is TOO big for 256 MB RAM! We right shift data by 1
//$readmemh("instr.dat",ram,'h100_0000);
$readmemh("instr.dat", ram, 'h100);
//$readmemh("data.dat",ram,'h400_0000>>1);
$readmemh("data.dat", ram, 'h400 >> 1);
end
always @(*) begin
addr_a = address_a << 26 - 22;
addr_b = address_b << 26 - 22;
end
always @(posedge clk) begin
if (wren_a) begin
for (k = 0; k < 512 / 32; k = k + 1) begin
for (i = 0; i < 4; i = i + 1) begin
if (byteen_a[((512/8-1)-((4*k)+i))]) ram[addr_a+k][(i*8)+:8] <= data_a[((32*k)+(i*8))+:8];
end
end
end else begin
for (i = 0; i < 512 / 32; i = i + 1) begin
out_a[(32*i)+:32] <= ram[addr_a+i];
end
end
if (wren_b) begin
for (k = 0; k < 512 / 32; k = k + 1) begin
for (i = 0; i < 4; i = i + 1) begin
if (byteen_b[((512/8-1)-((4*k)+i))]) ram[addr_b+k][(i*8)+:8] <= data_b[((32*k)+(i*8))+:8];
end
end
end else begin
for (i = 0; i < 512 / 32; i = i + 1) begin
out_b[32*i+:32] <= ram[addr_b+i];
end
end
end
`else
// Not connected wires
wire [(512/8)-1:0] byteen_a_nc;
wire [(512/8)-1:0] byteen_b_nc;
assign byteen_a_nc = byteen_a;
assign byteen_b_nc = byteen_b;
dual_port_ram u_dual_port_ram (
.addr1(address_a[11:0]),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b[11:0]),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
`endif
endmodule
| 7.017766 |
module register_17 (
d,
clk,
resetn,
en,
q
);
input clk;
input resetn;
input en;
input [17-1:0] d;
output [17-1:0] q;
reg [17-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.325339 |
module register_5 (
d,
clk,
resetn,
en,
q
);
input clk;
input resetn;
input en;
input [5-1:0] d;
output [5-1:0] q;
reg [5-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.165575 |
module register_1 (
d,
clk,
resetn,
en,
q
);
input clk;
input resetn;
input en;
input [1-1:0] d;
output [1-1:0] q;
reg [1-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.832907 |
module vlane_saturatesum_16 (
in,
op,
out
);
parameter WIDTH = 16;
input [WIDTH+2-1:0] in;
input [1:0] op;
output [WIDTH-1:0] out;
reg [WIDTH-1:0] out;
wire op_saturate;
wire op_signed;
assign op_saturate = op[1];
assign op_signed = op[0];
wire [WIDTH-1:0] maxunsigned;
wire [WIDTH-1:0] minunsigned;
wire [WIDTH-1:0] maxsigned;
wire [WIDTH-1:0] minsigned;
assign maxunsigned = {WIDTH{1'b1}};
assign minunsigned = 0;
assign maxsigned = {1'b0, {WIDTH - 1{1'b1}}};
assign minsigned = {1'b1, {WIDTH - 1{1'b0}}};
wire [WIDTH-1:0] through;
assign through = in[WIDTH-1:0];
wire [2:0] top3bits = (op_saturate) ? in[WIDTH+2-1:WIDTH-1] : 3'b0;
always @*
case (top3bits)
3'b010: out = maxunsigned;
3'b011: out = maxunsigned;
3'b001: out = (op_signed) ? maxsigned : through;
3'b111: out = (op_signed) ? through : minunsigned;
3'b110: out = (op_signed) ? minsigned : minunsigned;
default: out = through;
endcase
endmodule
| 7.414376 |
module dpram_5_32_32 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input [5-1:0] address_a;
input [5-1:0] address_b;
input wren_a;
input wren_b;
input [32-1:0] data_a;
input [32-1:0] data_b;
output [32-1:0] out_a;
output [32-1:0] out_b;
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
endmodule
| 7.96205 |
module local_shifter_17_2_ARITHMATIC (
data,
distance,
direction,
result
);
parameter LPM_SHIFTTYPE = "ARITHMATIC";
input [17-1:0] data;
input [2-1:0] distance;
input direction;
output reg [17-1:0] result;
reg [17-1:0] arith_reg;
always @* begin
arith_reg = {17{1'b1}};
if (LPM_SHIFTTYPE == "ARITHMETIC") begin
if (direction) begin
result = data << distance;
end else begin
if (data[17-1] == 1'b1) result = ((arith_reg << (17 - distance)) || (data >> distance));
else result = data >> distance;
end
end else begin
if (direction == 1'b0) begin
result = data << distance;
end else begin
result = data >> distance;
end
end
end
endmodule
| 7.322067 |
module vlane_mulshift_16_4 (
clk,
resetn,
opA,
opB,
sa,
op,
en,
result
);
parameter WIDTH = 16;
parameter LOG2WIDTH = 4;
input clk;
input resetn;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
input [LOG2WIDTH-1:0] sa;
input [4:0] op;
input [3:1] en; //Enable for each pipestage
output [WIDTH-1:0] result;
wire [3:0] temp;
/********* Control Signals *********/
wire is_signed, dir, is_mul, saturate, half;
assign is_mul = op[2]; // selects between opB and the computed shift amount
assign is_signed = ~op[1];
assign dir = op[0]; // selects between 2^sa and 2^(32-sa) for right shift
assign saturate = op[3];
assign half = op[4];
assign temp = en;
/********* Circuit Body *********/
wire dum, dum2, dum3;
wire [WIDTH:0] opB_mux_out;
wire [WIDTH-1:0] opA_mux_out;
wire [WIDTH-1:0] opB_mul;
wire [5-1:0] left_sa; // Amount of left shift required for both left/right
reg [WIDTH:0] decoded_sa;
wire [WIDTH-1:0] hi;
wire [WIDTH-1:0] lo;
assign opA_mux_out = (~half) ? ( opA ) : (WIDTH<2) ? 0 : (dir) ?
{{WIDTH/2{is_signed&is_mul&opA[WIDTH-1]}},opA[WIDTH-1:WIDTH/2]} :
{{WIDTH/2{is_signed&is_mul&opA[WIDTH/2-1]}},opA[WIDTH/2-1:0]};
assign opB_mul = (~half) ? opB : (WIDTH<2) ? 0 : (dir) ?
{{WIDTH/2{is_signed&is_mul&opB[WIDTH-1]}},opB[WIDTH-1:WIDTH/2]} :
{{WIDTH/2{is_signed&is_mul&opB[WIDTH/2-1]}},opB[WIDTH/2-1:0]};
assign opB_mux_out = (is_mul) ? {is_signed & opB_mul[WIDTH-1], opB_mul} : decoded_sa;
reg zeroout;
`ifndef USE_INHOUSE_LOGIC
`define USE_INHOUSE_LOGIC
`endif
always @(posedge clk) if (en[1]) zeroout <= (op[3:0] == 0);
`ifdef USE_INHOUSE_LOGIC
wire [(WIDTH+1)-1:0] dataa;
wire aclr;
wire [34-1:0] local_mult_component_result;
assign dataa = {is_signed & opA_mux_out[WIDTH-1], opA_mux_out};
assign aclr = ~resetn;
assign {dum2, dum, hi, lo} = local_mult_component_result;
local_mult_17_17_34 local_mult_component (
.dataa (dataa),
.datab (opB_mux_out),
.clock (clk),
.clken (en[1]),
.aclr (aclr),
.result(local_mult_component_result)
);
`else
lpm_mult lpm_mult_component (
.dataa({is_signed & opA_mux_out[WIDTH-1], opA_mux_out}),
.datab(opB_mux_out),
.sum(),
.clock(clk),
.clken(en[1]),
.aclr(~resetn),
.result({dum2, dum, hi, lo})
);
defparam lpm_mult_component.lpm_widtha = WIDTH + 1, lpm_mult_component.lpm_widthb = WIDTH + 1,
lpm_mult_component.lpm_widthp = 2 * WIDTH + 2, lpm_mult_component.lpm_widths = 1,
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_type = "LPM_MULT", lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=6";
`endif
// if A is positive/negative make it maximum/minimum positive/negative
wire [WIDTH-1:0] signedsaturate=
(opA_mux_out[WIDTH-1]) ? {1'b1,{WIDTH-1{1'b0}}} :
{1'b0,{WIDTH-1{1'b1}}};
reg [WIDTH-1:0] saturatedval_s2;
reg saturate_s2;
//Capture saturated value and saturate signal for next stage
always @(posedge clk)
if (!resetn) begin
saturatedval_s2 <= 0;
saturate_s2 <= 0;
end else if (en[1]) begin
saturatedval_s2 <= ((~is_signed) ? {WIDTH{1'b1}} : signedsaturate);
saturate_s2 <= saturate;
end
reg sel_hi;
always @(posedge clk)
if (!resetn) sel_hi <= 0;
else if (en[1]) sel_hi <= (is_mul && dir || ~is_mul && dir && |sa);
assign result = (zeroout) ? 0 : (saturate_s2 && |hi) ? saturatedval_s2 : (sel_hi) ? hi : lo;
assign {dum3, left_sa} = (dir) ? WIDTH - sa : {1'b0, sa};
//Decoder - computes 2^left_sa
always @* begin
decoded_sa = 1 << left_sa;
end
endmodule
| 8.216479 |
module vregfile_scalar_32_32_5 (
clk,
resetn,
a_reg,
a_en,
a_readdataout,
c_reg,
c_writedatain,
c_we
);
input clk;
input resetn;
input a_en;
input [5-1:0] a_reg, c_reg;
output [32-1:0] a_readdataout;
input [32-1:0] c_writedatain;
input c_we;
ram_wrapper_5_32_32 reg_file1 (
.clk(clk),
.resetn(resetn),
.rden_a(1'b0),
.rden_b(a_en),
.address_a(c_reg[5-1:0]),
.address_b(a_reg[5-1:0]),
.wren_a(c_we & (|c_reg)),
.wren_b(1'b0),
.data_a(c_writedatain),
.data_b(0),
.out_a(),
.out_b(a_readdataout)
);
endmodule
| 7.237439 |
module dpram_3_8_32 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input [3-1:0] address_a;
input [3-1:0] address_b;
input wren_a;
input wren_b;
input [32-1:0] data_a;
input [32-1:0] data_b;
output [32-1:0] out_a;
output [32-1:0] out_b;
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
endmodule
| 6.939366 |
module local_add_sub_18_0_SIGNED (
dataa,
datab,
cin,
add_sub,
result
);
input [18-1:0] dataa;
input [18-1:0] datab;
input cin;
input add_sub;
output reg [18-1:0] result;
always @(*) begin
if (add_sub == 1'b1) result = dataa + datab + cin;
else result = dataa - datab;
end
endmodule
| 6.568602 |
module reduction_processing_element_16_20 (
A,
B,
OUT,
MODE
);
input [16-1:0] A;
input [16-1:0] B;
output [20-1:0] OUT;
input [1:0] MODE;
wire [20-1:0] greater;
wire [20-1:0] smaller;
wire [20-1:0] sum;
assign greater = (A > B) ? A : B;
assign smaller = (A < B) ? A : B;
assign sum = A + B;
assign OUT = (MODE == 0) ? sum : (MODE == 1) ? greater : smaller;
endmodule
| 7.129714 |
module reduction_processing_element_20_20 (
A,
B,
OUT,
MODE
);
input [20-1:0] A;
input [20-1:0] B;
output [20-1:0] OUT;
input [1:0] MODE;
wire [20-1:0] greater;
wire [20-1:0] smaller;
wire [20-1:0] sum;
assign greater = (A > B) ? A : B;
assign smaller = (A < B) ? A : B;
assign sum = A + B;
assign OUT = (MODE == 0) ? sum : (MODE == 1) ? greater : smaller;
endmodule
| 7.129714 |
module ram_wrapper_3_8_32 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [3-1:0] address_a;
input [3-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden_b;
input [32-1:0] data_a;
input [32-1:0] data_b;
output [32-1:0] out_a;
output [32-1:0] out_b;
reg [3-1:0] q_address_a;
reg [3-1:0] q_address_b;
reg [3-1:0] mux_address_b;
// not connect ports
wire rden_a_nc;
assign rden_a_nc = rden_a;
dpram_3_8_32 dpram1 (
.clk(clk),
.address_a(address_a),
.address_b(mux_address_b),
.wren_a(wren_a),
.wren_b(wren_b),
.data_a(data_a),
.data_b(data_b),
.out_a(out_a),
.out_b(out_b)
);
always @(posedge clk) begin
if (!resetn) begin
q_address_a <= 'h0;
q_address_b <= 'h0;
end else begin
if (rden_b) q_address_b <= address_b;
end
end
always @(*) begin
if (rden_b) mux_address_b = address_b;
else mux_address_b = q_address_b;
end
endmodule
| 7.507949 |
module pipereg_1 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [1-1:0] d;
output [1-1:0] q;
reg [1-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.738505 |
module pipereg_17 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [17-1:0] d;
output [17-1:0] q;
reg [17-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.078539 |
module pipereg_1 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [1-1:0] d;
output [1-1:0] q;
reg [1-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.738505 |
module pipereg_8 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [8-1:0] d;
output [8-1:0] q;
reg [8-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.267674 |
module pipereg_65 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [65-1:0] d;
output [65-1:0] q;
reg [65-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.340723 |
module pipereg_32 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [32-1:0] d;
output [32-1:0] q;
reg [32-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.124819 |
module pipereg_5 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [5-1:0] d;
output [5-1:0] q;
reg [5-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.022103 |
module pipereg_5 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [5-1:0] d;
output [5-1:0] q;
reg [5-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.022103 |
module pipereg_32 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [32-1:0] d;
output [32-1:0] q;
reg [32-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.124819 |
module pipereg_6 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [6-1:0] d;
output [6-1:0] q;
reg [6-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.857215 |
module pipereg_2 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [2-1:0] d;
output [2-1:0] q;
reg [2-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.873167 |
module pipereg_1 (
d,
clk,
resetn,
en,
squashn,
q
);
input clk;
input resetn;
input en;
input squashn;
input [1-1:0] d;
output [1-1:0] q;
reg [1-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn == 0 || squashn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 6.738505 |
module vregfile_stride_32_8_3 (
clk,
resetn,
a_reg,
a_en,
a_readdataout,
c_reg,
c_writedatain,
c_we
);
input clk;
input resetn;
input a_en;
input [3-1:0] a_reg, c_reg;
output [32-1:0] a_readdataout;
input [32-1:0] c_writedatain;
input c_we;
ram_wrapper_3_8_32 reg_file1 (
.clk(clk),
.resetn(resetn),
.rden_a(1'b0),
.rden_b(a_en),
.address_a(c_reg[3-1:0]),
.address_b(a_reg[3-1:0]),
.wren_a(c_we),
.wren_b(1'b0),
.data_a(c_writedatain),
.data_b(0),
.out_a(),
.out_b(a_readdataout)
);
endmodule
| 6.888041 |
module vlane_saturatesize(
in,
op,
out
);
parameter WIDTH=32;
input [WIDTH-1:0] in;
input [3:0] op;
output [WIDTH-1:0] out;
wire op_outsigned;
wire op_signed;
wire op_size;
reg [WIDTH-1:0] out;
assign op_outsigned=op[3];
assign op_signed=op[2];
assign op_size=op[1:0]; //0 - word, 1 - byte, 2 - half
always@*
case(op_size)
2'b01: //byte
case({op_signed,op_outsigned})
2'b11: // signed
out = ((in[WIDTH-1])&(!(&in[WIDTH-2:7]))) ? {{WIDTH-8{1'b1}},8'h80} :
((~in[WIDTH-1]) && (|in[WIDTH-2:7])) ? 127 : in;
2'b10: // signed-unsigned
out = (in[WIDTH-1]) ? 0 :
(~in[WIDTH-1]&&(|in[WIDTH-2:8])) ? 255 : in;
default: //2'b00: unsigned
out=(|in[WIDTH-1:8]) ? 255 : in;
endcase
2'b10: //half-word 16-bits
case({op_signed,op_outsigned})
2'b11: // signed
out=((in[WIDTH-1])&(!(&in[WIDTH-2:15])))? {{WIDTH-16{1'b1}},16'h8000}:
((~in[WIDTH-1]) && (|in[WIDTH-2:15])) ? 32767 : in;
2'b10: // signed-unsigned
out = (in[WIDTH-1]) ? 0 :
(~in[WIDTH-1]&&(|in[WIDTH-2:16])) ? 65535 : in;
default: //2'b00: unsigned
out=(|in[WIDTH-1:16]) ? 65535 : in;
endcase
default:
case({op_signed,op_outsigned})
2'b10: // signed-unsigned
out = (in[WIDTH-1]) ? 0 : in;
default: //2'b00: unsigned
out=in;
endcase
endcase
endmodule
| 7.414376 |
module dpram_7_128_128 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input [7-1:0] address_a;
input [7-1:0] address_b;
input wren_a;
input wren_b;
input [128-1:0] data_a;
input [128-1:0] data_b;
output [128-1:0] out_a;
output [128-1:0] out_b;
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
endmodule
| 7.144072 |
module ram_wrapper_4_16_32 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [4-1:0] address_a;
input [4-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden_b;
input [32-1:0] data_a;
input [32-1:0] data_b;
output [32-1:0] out_a;
output [32-1:0] out_b;
reg [4-1:0] q_address_a;
reg [4-1:0] q_address_b;
reg [4-1:0] mux_address_b;
// not connect ports
wire rden_a_nc;
assign rden_a_nc = rden_a;
dpram_4_16_32 dpram1 (
.clk(clk),
.address_a(address_a),
.address_b(mux_address_b),
.wren_a(wren_a),
.wren_b(wren_b),
.data_a(data_a),
.data_b(data_b),
.out_a(out_a),
.out_b(out_b)
);
always @(posedge clk) begin
if (!resetn) begin
q_address_a <= 'h0;
q_address_b <= 'h0;
end else begin
if (rden_b) q_address_b <= address_b;
end
end
always @(*) begin
if (rden_b) mux_address_b = address_b;
else mux_address_b = q_address_b;
end
endmodule
| 7.79626 |
module pipe_1_2 (
d,
clk,
resetn,
en,
squash,
q
);
input [1-1:0] d;
input clk;
input resetn;
input [2-1:0] en;
input [2-1:0] squash;
output [1*(2+1)-1:0] q;
reg [1*2-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[1-1:0] <= 0;
else if (en[0]) tq[1-1:0] <= d;
// All the rest registers
for (i = 1; i < 2; i = i + 1)
if (!resetn || squash[i]) tq[i*1+:1] <= 0;
else if (en[i]) tq[i*1+:1] <= tq[(i-1)*1+:1];
end
assign q[1-1:0] = d;
assign q[1*(2+1)-1:1] = tq;
endmodule
| 6.739448 |
module pipe_4_2 (
d,
clk,
resetn,
en,
squash,
q
);
input [4-1:0] d;
input clk;
input resetn;
input [2-1:0] en;
input [2-1:0] squash;
output [4*(2+1)-1:0] q;
reg [4*2-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[4-1:0] <= 0;
else if (en[0]) tq[4-1:0] <= d;
// All the rest registers
for (i = 1; i < 2; i = i + 1)
if (!resetn || squash[i]) tq[i*4+:4] <= 0;
else if (en[i]) tq[i*4+:4] <= tq[(i-1)*4+:4];
end
assign q[4-1:0] = d;
assign q[4*(2+1)-1:4] = tq;
endmodule
| 6.555797 |
module pipe_8_2 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input [2-1:0] en;
input [2-1:0] squash;
output [8*(2+1)-1:0] q;
reg [8*2-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[8-1:0] <= 0;
else if (en[0]) tq[8-1:0] <= d;
// All the rest registers
for (i = 1; i < 2; i = i + 1)
if (!resetn || squash[i]) tq[i*8+:8] <= 0;
else if (en[i]) tq[i*8+:8] <= tq[(i-1)*8+:8];
end
assign q[8-1:0] = d;
assign q[8*(2+1)-1:8] = tq;
endmodule
| 6.878884 |
module pipe_7_5 (
d,
clk,
resetn,
en,
squash,
q
);
input [7-1:0] d;
input clk;
input resetn;
input [5-1:0] en;
input [5-1:0] squash;
output [7*(5+1)-1:0] q;
reg [7*5-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[7-1:0] <= 0;
else if (en[0]) tq[7-1:0] <= d;
// All the rest registers
for (i = 1; i < 5; i = i + 1)
if (!resetn || squash[i]) tq[i*7+:7] <= 0;
else if (en[i]) tq[i*7+:7] <= tq[(i-1)*7+:7];
end
assign q[7-1:0] = d;
assign q[7*(5+1)-1:7] = tq;
endmodule
| 6.613178 |
module pipe_1_3 (
d,
clk,
resetn,
en,
squash,
q
);
input [1-1:0] d;
input clk;
input resetn;
input [3-1:0] en;
input [3-1:0] squash;
output [1*(3+1)-1:0] q;
reg [1*3-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[1-1:0] <= 0;
else if (en[0]) tq[1-1:0] <= d;
// All the rest registers
for (i = 1; i < 3; i = i + 1)
if (!resetn || squash[i]) tq[i*1+:1] <= 0;
else if (en[i]) tq[i*1+:1] <= tq[(i-1)*1+:1];
end
assign q[1-1:0] = d;
assign q[1*(3+1)-1:1] = tq;
endmodule
| 6.651202 |
module pipe_8_1 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input en;
input squash;
output [8*(1+1)-1:0] q;
reg [8*1-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash) tq[8-1:0] <= 0;
else if (en) tq[8-1:0] <= d;
end
assign q[8-1:0] = d;
assign q[8*(1+1)-1:8] = tq;
endmodule
| 6.619595 |
module pipe_32_4 (
d,
clk,
resetn,
en,
squash,
q
);
input [32-1:0] d;
input clk;
input resetn;
input [4-1:0] en;
input [4-1:0] squash;
output [32*(4+1)-1:0] q;
reg [32*4-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash[0]) tq[32-1:0] <= 0;
else if (en[0]) tq[32-1:0] <= d;
// All the rest registers
for (i = 1; i < 4; i = i + 1)
if (!resetn || squash[i]) tq[i*32+:32] <= 0;
else if (en[i]) tq[i*32+:32] <= tq[(i-1)*32+:32];
end
assign q[32-1:0] = d;
assign q[32*(4+1)-1:32] = tq;
endmodule
| 7.524638 |
module pipe_8_1 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input en;
input squash;
output [8*(1+1)-1:0] q;
reg [8*1-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash) tq[8-1:0] <= 0;
else if (en) tq[8-1:0] <= d;
end
assign q[8-1:0] = d;
assign q[8*(1+1)-1:8] = tq;
endmodule
| 6.619595 |
module pipe_8_1 (
d,
clk,
resetn,
en,
squash,
q
);
input [8-1:0] d;
input clk;
input resetn;
input en;
input squash;
output [8*(1+1)-1:0] q;
reg [8*1-1:0] tq;
reg [31:0] i;
always @(posedge clk) begin
// 1st register
if (!resetn || squash) tq[8-1:0] <= 0;
else if (en) tq[8-1:0] <= d;
end
assign q[8-1:0] = d;
assign q[8*(1+1)-1:8] = tq;
endmodule
| 6.619595 |
module
////////////////////////////////////////////
module reduction_layer_16_4_32_5_10
(
input clk,
input resetn, //resets the processing elements
input en, //indicates valid reduction operation
input [1:0] reduction_type, //can have 3 values: 0 (Add), 1 (Max), 2 (Min)
input read,
input [8 * 16 -1:0] a, // input data to reduction logic
output [8 * 16 -1:0] reduced_out, //output
output reg done, //output is valid when done is 1
output reg busy
);
wire [8 * 16 -1:0] reduced_out_1; //output
wire [8 * 16 -1:0] reduced_out_add; //output
wire [16 + 4-1:0] reduced_out_unrounded;
wire reset_reduction_unit;
assign reset_reduction_unit = ~resetn;
reduction_unit_16_4 ucu(
.clk(clk),
.reset(reset_reduction_unit),
.inp0(a[1*16-1:0*16]),
.inp1(a[2*16-1:1*16]),
.inp2(a[3*16-1:2*16]),
.inp3(a[4*16-1:3*16]),
.inp4(a[5*16-1:4*16]),
.inp5(a[6*16-1:5*16]),
.inp6(a[7*16-1:6*16]),
.inp7(a[8*16-1:7*16]),
.mode(reduction_type),
.outp(reduced_out_unrounded)
);
////////////////////////////////////////////////////////////////
// Rounding of the output of reduction unit (from 20 bits to 16 bits).
// This is required only when reduction type is "sum"
////////////////////////////////////////////////////////////////
rounding_20_16 u_round(.i_data(reduced_out_unrounded), .o_data(reduced_out_add));
assign reduced_out_1 = (reduction_type==2'b0) ? reduced_out_add : reduced_out_unrounded[16-1:0];
assign reduced_out = {8{reduced_out_1}};
reg[2:0] count;
always@(posedge clk)begin
if(!resetn)begin
count <= 3'b0;
end
else begin
if(en)
count <= count + 1;
if(read)
count <= count - 1;
end
end
always@(*)begin
if(count == 8)begin
busy = 1'b1;
end
else begin
busy = 1'b0;
end
end
always@(posedge clk)begin
if(!resetn)begin
done <= 1'b0;
end
else begin
if(count == 8)
done <= 1'b1;
else if(count ==0)
done <= 1'b0;
end
end
endmodule
| 6.558648 |
module dpram_4_16_32 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input [4-1:0] address_a;
input [4-1:0] address_b;
input wren_a;
input wren_b;
input [32-1:0] data_a;
input [32-1:0] data_b;
output [32-1:0] out_a;
output [32-1:0] out_b;
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
endmodule
| 7.275288 |
module ram_wrapper_5_32_32 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [5-1:0] address_a;
input [5-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden_b;
input [32-1:0] data_a;
input [32-1:0] data_b;
output [32-1:0] out_a;
output [32-1:0] out_b;
reg [5-1:0] q_address_a;
reg [5-1:0] q_address_b;
reg [5-1:0] mux_address_b;
// not connect ports
wire rden_a_nc;
assign rden_a_nc = rden_a;
dpram_5_32_32 dpram1 (
.clk(clk),
.address_a(address_a),
.address_b(mux_address_b),
.wren_a(wren_a),
.wren_b(wren_b),
.data_a(data_a),
.data_b(data_b),
.out_a(out_a),
.out_b(out_b)
);
always @(posedge clk) begin
if (!resetn) begin
q_address_a <= 'h0;
q_address_b <= 'h0;
end else begin
if (rden_b) q_address_b <= address_b;
end
end
always @(*) begin
if (rden_b) mux_address_b = address_b;
else mux_address_b = q_address_b;
end
endmodule
| 6.914131 |
module ram_wrapper_7_128_8 (
clk,
resetn,
address_a,
address_b,
rden_a,
rden_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
input clk;
input resetn;
input [7-1:0] address_a;
input [7-1:0] address_b;
input wren_a;
input wren_b;
input rden_a;
input rden_b;
input [8-1:0] data_a;
input [8-1:0] data_b;
output [8-1:0] out_a;
output [8-1:0] out_b;
reg [7-1:0] q_address_a;
reg [7-1:0] q_address_b;
reg [7-1:0] mux_address_b;
// not connect ports
wire rden_a_nc;
assign rden_a_nc = rden_a;
dpram_7_128_8 dpram1 (
.clk(clk),
.address_a(address_a),
.address_b(mux_address_b),
.wren_a(wren_a),
.wren_b(wren_b),
.data_a(data_a),
.data_b(data_b),
.out_a(out_a),
.out_b(out_b)
);
always @(posedge clk) begin
if (!resetn) begin
q_address_a <= 'h0;
q_address_b <= 'h0;
end else begin
if (rden_b) q_address_b <= address_b;
end
end
always @(*) begin
if (rden_b) mux_address_b = address_b;
else mux_address_b = q_address_b;
end
endmodule
| 7.021767 |
module rounding_20_16 (
i_data,
o_data
);
input [20-1:0] i_data;
output [16-1:0] o_data;
wire [20-1:0] w_convergent;
assign w_convergent = i_data[(20-1):0]
+ { {(16){1'b0}},
i_data[(20-16)],
{(20-16-1){!i_data[(20-16)]}}};
assign o_data = w_convergent[(20-1):(20-16)];
endmodule
| 7.312513 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0] out_a;
reg [`DWIDTH-1:0] out_b;
wire [`DWIDTH-1:0] out_c;
wire [`DWIDTH-1:0] out_mac;
assign out_c = out_mac;
seq_mac u_mac (
.a(in_a),
.b(in_b),
.out(out_mac),
.reset(reset),
.clk(clk)
);
always @(posedge clk) begin
if (reset) begin
out_a <= 0;
out_b <= 0;
end else begin
out_a <= in_a;
out_b <= in_b;
end
end
endmodule
| 6.504296 |
module vregfile_control_32_32_5 (
clk,
resetn,
a_reg,
a_en,
a_readdataout,
c_reg,
c_writedatain,
c_we,
vl,
matmul_masks
);
input clk;
input resetn;
input a_en;
input [5-1:0] a_reg, c_reg;
output [32-1:0] a_readdataout;
input [32-1:0] c_writedatain;
input c_we;
output [32-1:0] vl;
output [3*8-1:0] matmul_masks;
reg [32-1:0] vl;
reg [32-1:0] matmul_masks;
ram_wrapper_5_32_32 reg_file1 (
.clk(clk),
.resetn(resetn),
.rden_a(1'b0),
.rden_b(a_en),
.address_a(c_reg[5-1:0]),
.address_b(a_reg[5-1:0]),
.wren_a(c_we),
.wren_b(1'b0),
.data_a(c_writedatain),
.data_b(0),
.out_a(),
.out_b(a_readdataout)
);
`ifdef TEST_BENCH
initial begin
$readmemh("vregfile_control.dat", reg_file1.dpram1.ram, 'h0);
end
`endif
always @(posedge clk) begin
if (!resetn) begin
vl <= 0;
matmul_masks <= 32'hffffffff;
end else begin
if (c_we) begin
if (c_reg == 0) begin
vl <= c_writedatain;
end else if (c_reg == 31) begin //a_rows
matmul_masks[1*8-1:0*8] <= c_writedatain[8-1:0];
end else if (c_reg == 30) begin //a_cols, b_rows
matmul_masks[2*8-1:1*8] <= c_writedatain[8-1:0];
end else if (c_reg == 29) begin //b_cols
matmul_masks[3*8-1:2*8] <= c_writedatain[8-1:0];
end
end
end
end
endmodule
| 8.151167 |
module addersub_32 (
opA,
opB,
op,
result,
result_slt
);
input [32-1:0] opA;
input [32-1:0] opB;
//input carry_in;
input [3-1:0] op;
output [32-1:0] result;
output result_slt;
wire carry_out;
wire [32:0] sum;
// Mux between sum, and slt
wire is_slt;
wire signext;
wire addsub;
assign is_slt = op[2];
assign signext = op[1];
assign addsub = op[0];
assign result = sum[32-1:0];
//assign result_slt[32-1:1]={31{1'b0}};
//assign result_slt[0]=sum[32];
assign result_slt = sum[32];
`ifndef USE_INHOUSE_LOGIC
`define USE_INHOUSE_LOGIC
`endif
`ifdef USE_INHOUSE_LOGIC
wire [(32+1)-1:0] dataa;
wire [(32+1)-1:0] datab;
wire cin;
assign dataa = {signext & opA[32-1], opA};
assign datab = {signext & opB[32-1], opB};
assign cin = ~addsub;
local_add_sub_33_0_SIGNED local_adder_inst (
.dataa(dataa),
.datab(datab),
.cin(cin),
.add_sub(addsub),
.result(sum)
);
`else
lpm_add_sub adder_inst (
.dataa({signext & opA[32-1], opA}),
.datab({signext & opB[32-1], opB}),
.cin(~addsub),
.add_sub(addsub),
.result(sum)
// synopsys translate_off
, .cout(),
.clken(),
.clock(),
.overflow(),
.aclr()
// synopsys translate_on
);
defparam adder_inst.lpm_width = 32 + 1, adder_inst.lpm_representation = "SIGNED";
`endif
assign carry_out = sum[32];
endmodule
| 7.769077 |
module local_add_sub_33_0_SIGNED (
dataa,
datab,
cin,
add_sub,
result
);
input [33-1:0] dataa;
input [33-1:0] datab;
input cin;
input add_sub;
output reg [33-1:0] result;
always @(*) begin
if (add_sub == 1'b1) result = dataa + datab + cin;
else result = dataa - datab;
end
endmodule
| 6.568602 |
module logic_unit_32 (
opA,
opB,
op,
result
);
input [32-1:0] opA;
input [32-1:0] opB;
input [2-1:0] op;
output [32-1:0] result;
reg [32-1:0] logic_result;
always @(opA or opB or op)
case (op)
2'b00: logic_result = opA & opB;
2'b01: logic_result = opA | opB;
2'b10: logic_result = opA ^ opB;
2'b11: logic_result = ~(opA | opB);
endcase
assign result = logic_result;
endmodule
| 8.293771 |
module register_32 (
d,
clk,
resetn,
en,
q
);
input clk;
input resetn;
input en;
input [32-1:0] d;
output [32-1:0] q;
reg [32-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.25423 |
module register_2 (
d,
clk,
resetn,
en,
q
);
input clk;
input resetn;
input en;
input [2-1:0] d;
output [2-1:0] q;
reg [2-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1) q <= d;
end
endmodule
| 7.170601 |
module branchpredict_32_4096_12_1 ( clk, resetn,
predict,
prediction,
pc_predict,
result_rdy,
result,
pc_result);
input clk;
input resetn;
// Prediction Port
input predict; // When high tells predictor to predict in next cycle
input [32-1:0] pc_predict; // The PC value for which to predict
output reg prediction; // The actual prediction 1-taken, 0-nottaken
wire prediction_temp;
// Prediction Result Port - tells us if the prediction made at pc_result was taken
input result_rdy; // The branch has been resolved when result_rdy goes hi
input [32-1:0] pc_result; // The PC value that this result is for
input result; // The actual result 1-taken, 0-nottaken
wire resetn_nc;
wire predict_nc;
wire [32-1:0] pc_predict_local;
wire [32-1:0] pc_result_local;
assign resetn_nc = resetn;
assign predict_nc = predict;
assign pc_predict_local = pc_predict;
assign pc_result_local = pc_result;
wire [12-1:0] address_b;
assign address_b=pc_predict_local[12+2-1:2];
`ifndef USE_INHOUSE_LOGIC
`define USE_INHOUSE_LOGIC
`endif
`ifdef USE_INHOUSE_LOGIC
wire [1-1:0] pred_table_out_a_nc;
dpram_12_4096_1 pred_table(
.clk(clk),
.address_a(pc_result_local[12+2-1:2]),
.address_b(address_b),
.wren_a(result_rdy),
.wren_b(0),
.data_a(result),
.data_b(0),
.out_a(pred_table_out_a_nc),
.out_b(prediction_temp)
);
// HACK...HACK....HACK
// Somehow abc was thinking that output of dpram is a combinational port. Though the port is sequential as per the architecture file (agilex_arch.auto_layout.xml). The input address (address_b, pc_predict) comes from the parent module and the output data (out_b, prediction) goes to parent module without any logic in between. The output and input of a dpram are connected combinatoraly in the parent module. So abc thinks that here is a combinatoral loop.
always @(posedge clk)
begin
prediction <= prediction_temp;
end
`else
altsyncram pred_table(
.clock0 (clk),
.wren_a (result_rdy),
.address_a (pc_result[LOG2TABLEDEPTH+2-1:2]),
.data_a (result),
.address_b (address_b),
.clock1 (clk),
.clocken1 (predict),
.q_b (prediction)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.wren_b (1'b0),
.rden_b(1'b1),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
pred_table.operation_mode = "DUAL_PORT",
pred_table.width_a = TABLEWIDTH,
pred_table.widthad_a = LOG2TABLEDEPTH,
pred_table.numwords_a = TABLEDEPTH,
pred_table.width_b = TABLEWIDTH,
pred_table.widthad_b = LOG2TABLEDEPTH,
pred_table.numwords_b = TABLEDEPTH,
pred_table.lpm_type = "altsyncram",
pred_table.width_byteena_a = 1,
pred_table.outdata_reg_b = "UNREGISTERED",
pred_table.indata_aclr_a = "NONE",
pred_table.wrcontrol_aclr_a = "NONE",
pred_table.address_aclr_a = "NONE",
pred_table.rdcontrol_reg_b = "CLOCK1",
pred_table.address_reg_b = "CLOCK1",
pred_table.address_aclr_b = "NONE",
pred_table.outdata_aclr_b = "NONE",
pred_table.read_during_write_mode_mixed_ports = "OLD_DATA",
pred_table.ram_block_type = "AUTO",
pred_table.intended_device_family = "Stratix";
`endif
endmodule
| 7.210838 |
module mul_32 (
clk,
resetn,
start,
stalled,
dst,
opA,
opB,
sa,
op,
shift_result,
hi,
lo
);
input clk;
input resetn;
input start;
output stalled;
input [4:0] dst;
input [32-1:0] opA;
input [32-1:0] opB;
input [5-1:0] sa;
input [2:0] op;
output [32-1:0] shift_result;
output [32-1:0] hi;
output [32-1:0] lo;
/********* Control Signals *********/
wire is_signed, dir, is_mul;
assign is_mul = op[2]; // selects between opB and the computed shift amount
assign is_signed = op[1];
assign dir = op[0]; // selects between 2^sa and 2^(32-sa) for right shift
/********* Circuit Body *********/
wire dum, dum2, dum3;
wire [ 32:0] opB_mux_out;
wire [5-1:0] left_sa; // Amount of left shift required for both left/right
reg [ 32:0] decoded_sa;
assign opB_mux_out = (is_mul) ? {is_signed & opB[32-1], opB} : decoded_sa;
`ifndef USE_INHOUSE_LOGIC
`define USE_INHOUSE_LOGIC
`endif
`ifdef USE_INHOUSE_LOGIC
wire [33-1:0] mult_dataa;
wire mult_aclr;
wire [66-1:0] mult_result;
assign mult_dataa = {is_signed & opA[32-1], opA};
assign mult_aclr = ~resetn;
assign {dum2, dum, hi, lo} = mult_result;
local_mult_33_33_66 local_mult_component (
.dataa (mult_dataa),
.datab (opB_mux_out),
.clock (clk),
.clken (1'b1),
.aclr (mult_aclr),
.result(mult_result)
);
`else
lpm_mult lpm_mult_component (
.dataa({is_signed & opA[32-1], opA}),
.datab(opB_mux_out),
.sum(),
.clock(clk),
.clken(),
.aclr(~resetn),
.result({dum2, dum, hi, lo})
);
defparam lpm_mult_component.lpm_widtha = 32 + 1, lpm_mult_component.lpm_widthb = 32 + 1,
lpm_mult_component.lpm_widthp = 2 * 32 + 2, lpm_mult_component.lpm_widths = 1,
lpm_mult_component.lpm_pipeline = 1, lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=6";
`endif
assign shift_result = (dir && |sa) ? hi : lo;
assign {dum3, left_sa} = (dir) ? 32 - sa : {1'b0, sa};
always @(left_sa or dir) begin
decoded_sa = 1 << left_sa;
end
// 1 cycle stall state machine
wire staller_request;
assign staller_request = (start & is_mul) | (start & (|dst) & ~is_mul);
onecyclestall staller (
staller_request,
clk,
resetn,
stalled
);
endmodule
| 7.227089 |
module local_mult_33_33_66 (
dataa,
datab,
clock,
clken,
aclr,
result
);
input [33-1:0] dataa;
input [33-1:0] datab;
input clock;
input clken;
input aclr;
output reg [66-1:0] result;
wire [33-1:0] unsignedinputA;
wire [33-1:0] unsignedinputB;
wire [66-1:0] unsignedoutputP;
wire gated_clock;
assign unsignedinputA = dataa;
assign unsignedinputB = datab;
assign unsignedoutputP = unsignedinputA * unsignedinputB;
assign gated_clock = clock & clken;
always @(posedge gated_clock) begin
if (aclr) begin
result <= 0;
end else result <= unsignedoutputP;
end
endmodule
| 6.784166 |
module div_0_1_2 (
en,
resetn,
stalled,
quotient,
remainder,
dividend,
divider,
sign,
clk
);
input clk;
input resetn;
input sign;
input en;
input [31:0] dividend, divider;
output [31:0] quotient, remainder;
output stalled;
reg [31:0] quotient, quotient_temp;
reg [63:0] dividend_copy, divider_copy, diff;
reg negative_output;
wire [31:0] remainder = (!negative_output) ? dividend_copy[31:0] : ~dividend_copy[31:0] + 1'b1;
reg [ 5:0] bits;
reg [ 1:0] state;
always @(posedge clk)
if (!resetn) state <= 0;
else
case (state)
0: state <= (en) ? 1 : 0;
1: state <= (bits == 5'd1) ? 2 : 1;
2: state <= 0;
default: state <= 0;
endcase
assign stalled = (state == 1) || (state == 0 && en);
//assign stalled = (bits==0 && en) || (|bits);
always @(posedge clk)
if (!resetn) begin
bits = 0;
quotient = 0;
quotient_temp = 0;
dividend_copy = 0;
divider_copy = 0;
negative_output = 0;
diff = 0;
end else if (en && state == 0) begin
bits = 6'd32;
quotient = 0;
quotient_temp = 0;
dividend_copy = (!sign || !dividend[31]) ? {32'd0, dividend} : {32'd0, ~dividend + 1'b1};
divider_copy = (!sign || !divider[31]) ?
{1'b0,divider,31'd0} :
{1'b0,~divider + 1'b1,31'd0};
negative_output = sign && ((divider[31] && !dividend[31]) || (!divider[31] && dividend[31]));
end else if (bits > 0) begin
diff = dividend_copy - divider_copy;
if (!diff[63]) begin
dividend_copy = diff;
quotient_temp = (quotient_temp << 1) | 1'd1;
end else begin
quotient_temp = quotient_temp << 1;
end
quotient = (!negative_output) ? quotient_temp : ~quotient_temp + 1'b1;
divider_copy = divider_copy >> 1;
bits = bits - 1'b1;
end
endmodule
| 6.704407 |
module data_mem_32_32_4_16_16384 (
clk,
resetn,
en,
stalled,
d_writedata,
d_address,
op,
d_loadresult,
ecause,
boot_daddr,
boot_ddata,
boot_dwe,
bus_address,
bus_byteen,
bus_we,
bus_en,
bus_writedata,
bus_readdata,
bus_wait,
bus_ecause
);
input clk;
input resetn;
input en;
output stalled;
output [31:0] ecause;
input [31:0] boot_daddr;
input [31:0] boot_ddata;
input boot_dwe;
input [32-1:0] d_address;
input [4-1:0] op;
input [32-1:0] d_writedata;
output [32-1:0] d_loadresult;
output [32-1:0] bus_address;
output [4-1:0] bus_byteen;
output bus_we;
output bus_en;
output [32-1:0] bus_writedata;
input [32-1:0] bus_readdata;
input bus_wait;
input [32-1:0] bus_ecause;
wire [4-1:0] d_byteena;
wire [32-1:0] d_readdatain;
wire [32-1:0] d_writedatamem;
wire d_write;
wire [1:0] d_address_latched;
// not connected ports
wire resetn_nc;
assign resetn_nc = resetn;
wire [31:0] boot_daddr_nc;
assign boot_daddr_nc = boot_daddr;
wire [31:0] boot_ddata_nc;
assign boot_ddata_nc = boot_ddata;
wire boot_dwe_nc;
assign boot_dwe_nc = boot_dwe;
assign d_write = op[3];
assign ecause = bus_ecause;
register_2 d_address_reg (
d_address[1:0],
clk,
1'b1,
en,
d_address_latched
);
store_data_translator_32 sdtrans_inst (
.write_data(d_writedata),
.d_address(d_address[1:0]),
.store_size(op[1:0]),
.d_byteena(d_byteena),
.d_writedataout(d_writedatamem)
);
load_data_translator_32 ldtrans_inst (
.d_readdatain(d_readdatain),
.d_address(d_address_latched[1:0]),
.load_size(op[1:0]),
.load_sign_ext(op[2]),
.d_loadresult(d_loadresult)
);
assign bus_address = d_address;
assign bus_byteen = d_byteena;
assign bus_we = d_write;
assign bus_en = en;
assign bus_writedata = d_writedatamem;
assign d_readdatain = bus_readdata;
assign stalled = bus_wait;
/*
altsyncram dmem (
.wren_a (d_write&en&(~d_address[31])),
.clock0 (clk),
.clocken0 (),
.clock1 (clk),
.clocken1 (boot_dwe),
`ifdef TEST_BENCH
.aclr0(~resetn),
`endif
.byteena_a (d_byteena),
.address_a (d_address[DM_ADDRESSWIDTH+2-1:2]),
.data_a (d_writedatamem),
.wren_b (boot_dwe), .data_b (boot_ddata), .address_b (boot_daddr),
// synopsys translate_off
.rden_b (),
.aclr1 (), .byteena_b (),
.addressstall_a (), .addressstall_b (), .q_b (),
// synopsys translate_on
.q_a (d_readdatain)
);
defparam
dmem.intended_device_family = "Stratix",
dmem.width_a = DM_DATAWIDTH,
dmem.widthad_a = DM_ADDRESSWIDTH-2,
dmem.numwords_a = DM_SIZE,
dmem.width_byteena_a = DM_BYTEENAWIDTH,
dmem.operation_mode = "BIDIR_DUAL_PORT",
dmem.width_b = DM_DATAWIDTH,
dmem.widthad_b = DM_ADDRESSWIDTH-2,
dmem.numwords_b = DM_SIZE,
dmem.width_byteena_b = 1,
dmem.outdata_reg_a = "UNREGISTERED",
dmem.address_reg_b = "CLOCK1",
dmem.wrcontrol_wraddress_reg_b = "CLOCK1",
dmem.wrcontrol_aclr_a = "NONE",
dmem.address_aclr_a = "NONE",
dmem.outdata_aclr_a = "NONE",
dmem.byteena_aclr_a = "NONE",
dmem.byte_size = 8,
`ifdef TEST_BENCH
dmem.indata_aclr_a = "CLEAR0",
dmem.init_file = "data.rif",
`endif
`ifdef QUARTUS_SIM
dmem.init_file = "data.mif",
dmem.ram_block_type = "M4K",
`else
dmem.ram_block_type = "MEGARAM",
`endif
dmem.lpm_type = "altsyncram";
*/
endmodule
| 6.697471 |
module store_data_translator_32 (
write_data, // data in least significant position
d_address,
store_size,
d_byteena,
d_writedataout
); // shifted data to coincide with address
input [32-1:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d_byteena;
output [32-1:0] d_writedataout;
reg [3:0] d_byteena;
reg [32-1:0] d_writedataout;
always @(write_data or d_address or store_size) begin
case (store_size)
2'b11:
case (d_address[1:0])
0: begin
d_byteena = 4'b1000;
d_writedataout = {write_data[7:0], 24'b0};
end
1: begin
d_byteena = 4'b0100;
d_writedataout = {8'b0, write_data[7:0], 16'b0};
end
2: begin
d_byteena = 4'b0010;
d_writedataout = {16'b0, write_data[7:0], 8'b0};
end
default: begin
d_byteena = 4'b0001;
d_writedataout = {24'b0, write_data[7:0]};
end
endcase
2'b01:
case (d_address[1])
0: begin
d_byteena = 4'b1100;
d_writedataout = {write_data[15:0], 16'b0};
end
default: begin
d_byteena = 4'b0011;
d_writedataout = {16'b0, write_data[15:0]};
end
endcase
default: begin
d_byteena = 4'b1111;
d_writedataout = write_data;
end
endcase
end
endmodule
| 8.280191 |
module load_data_translator_32 (
d_readdatain,
d_address,
load_size,
load_sign_ext,
d_loadresult
);
input [32-1:0] d_readdatain;
input [1:0] d_address;
input [1:0] load_size;
input load_sign_ext;
output [32-1:0] d_loadresult;
reg [32-1:0] d_loadresult;
always @(d_readdatain or d_address or load_size or load_sign_ext) begin
case (load_size)
2'b11: begin
case (d_address[1:0])
0: d_loadresult[7:0] = d_readdatain[31:24];
1: d_loadresult[7:0] = d_readdatain[23:16];
2: d_loadresult[7:0] = d_readdatain[15:8];
default: d_loadresult[7:0] = d_readdatain[7:0];
endcase
d_loadresult[31:8] = {24{load_sign_ext & d_loadresult[7]}};
end
2'b01: begin
case (d_address[1])
0: d_loadresult[15:0] = d_readdatain[31:16];
default: d_loadresult[15:0] = d_readdatain[15:0];
endcase
d_loadresult[31:16] = {16{load_sign_ext & d_loadresult[15]}};
end
default: d_loadresult = d_readdatain;
endcase
end
endmodule
| 9.105161 |
module ram_wrapper_5_32_32 (
// clk,
// resetn,
// address_a,
// address_b,
// rden_a,
// rden_b,
// wren_a,
// wren_b,
// data_a,
// data_b,
// out_a,
// out_b
//);
//
//input clk;
//input resetn;
//input [(5-1):0] address_a;
//input [(5-1):0] address_b;
//input wren_a;
//input wren_b;
//input rden_a;
//input rden_b;
//input [(32-1):0] data_a;
//input [(32-1):0] data_b;
//output [(32-1):0] out_a;
//output [(32-1):0] out_b;
//
//reg [(5-1):0] q_address_a;
//reg [(5-1):0] q_address_b;
//reg [(5-1):0] mux_address_b;
//
//// not connect ports
//wire rden_a_nc;
//assign rden_a_nc = rden_a;
//
//dpram_5_32_32 dpram1(
// .clk(clk),
// .address_a(address_a),
// .address_b(mux_address_b),
// .wren_a(wren_a),
// .wren_b(wren_b),
// .data_a(data_a),
// .data_b(data_b),
// .out_a(out_a),
// .out_b(out_b)
//);
//
//always@(posedge clk)begin
// if(!resetn)begin
// q_address_a <= 'h0;
// q_address_b <= 'h0;
// end
// else begin
// if(rden_b)
// q_address_b <= address_b;
// end
//end
//
//always@(*)begin
// if(rden_b)
// mux_address_b = address_b;
// else
// mux_address_b = q_address_b;
//end
//
//endmodule
| 6.914131 |
module dpram_5_32_32 (
// clk,
// address_a,
// address_b,
// wren_a,
// wren_b,
// data_a,
// data_b,
// out_a,
// out_b
//);
//
//input clk;
//input [(5-1):0] address_a;
//input [(5-1):0] address_b;
//input wren_a;
//input wren_b;
//input [(32-1):0] data_a;
//input [(32-1):0] data_b;
//output reg [(32-1):0] out_a;
//output reg [(32-1):0] out_b;
//
//`ifdef SIMULATION_MEMORY
//
//reg [32-1:0] ram[32-1:0];
//
//always @ (posedge clk) begin
// if (wren_a) begin
// ram[address_a] <= data_a;
// end
// else begin
// out_a <= ram[address_a];
// end
//end
//
//always @ (posedge clk) begin
// if (wren_b) begin
// ram[address_b] <= data_b;
// end
// else begin
// out_b <= ram[address_b];
// end
//end
//
//`else
//
//dual_port_ram u_dual_port_ram(
//.addr1(address_a),
//.we1(wren_a),
//.data1(data_a),
//.out1(out_a),
//.addr2(address_b),
//.we2(wren_b),
//.data2(data_b),
//.out2(out_b),
//.clk(clk)
//);
//
//`endif
//
//endmodule
| 7.96205 |
module pcadder_32 (
pc,
offset,
result
);
input [32-1:0] pc;
input [32-1:0] offset;
output [32-1:0] result;
// not connect ports
wire [32-1:0] offset_nc;
assign offset_nc = offset;
wire dum;
assign {dum, result} = pc + {offset[32-3:0], 2'b0};
endmodule
| 7.043462 |
module signext16 (
in,
out
);
input [15:0] in;
output [31:0] out;
assign out = {{{{16{{in[15]}}}}, in[15:0]}};
endmodule
| 7.934159 |
module branchresolve_32 (
en,
rs,
rt,
eq,
ne,
ltz,
lez,
gtz,
gez,
eqz
);
parameter WIDTH = 32;
input en;
input [WIDTH-1:0] rs;
input [WIDTH-1:0] rt;
output eq;
output ne;
output ltz;
output lez;
output gtz;
output gez;
output eqz;
assign eq = (en) & (rs == rt);
assign ne = (en) & ~eq;
assign eqz = (en) & ~(|rs);
assign ltz = (en) & rs[WIDTH-1];
assign lez = (en) & rs[WIDTH-1] | eqz;
assign gtz = (en) & (~rs[WIDTH-1]) & ~eqz;
assign gez = (en) & (~rs[WIDTH-1]);
endmodule
| 9.028008 |
module lo_reg_32 (
d,
clk,
resetn,
squashn,
en,
q
);
input clk;
input resetn;
input squashn;
input en;
input [32-1:0] d;
output [32-1:0] q;
reg [32-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn == 0) q <= 0;
else if (en == 1 && squashn) q <= d;
end
endmodule
| 7.658015 |
module const_32_0 (
out
);
output [32-1:0] out;
assign out = 0;
endmodule
| 6.943542 |
module const_32_16 (
out
);
output [32-1:0] out;
assign out = 16;
endmodule
| 7.582393 |
module const_32_31 (
out
);
output [32-1:0] out;
assign out = 31;
endmodule
| 7.210659 |
module pipereg_32(d,clk,resetn,en,squashn,q);
//
//input clk;
//input resetn;
//input en;
//input squashn;
//input [32-1:0] d;
//output [32-1:0] q;
//reg [32-1:0] q;
//
//always @(posedge clk) //synchronous reset
//begin
// if (resetn==0 || squashn==0)
// q<=0;
// else if (en==1)
// q<=d;
//end
//
//endmodule
| 7.03887 |
module pipereg_5(d,clk,resetn,en,squashn,q);
//
//input clk;
//input resetn;
//input en;
//input squashn;
//input [5-1:0] d;
//output [5-1:0] q;
//reg [5-1:0] q;
//
//always @(posedge clk) //synchronous reset
//begin
// if (resetn==0 || squashn==0)
// q<=0;
// else if (en==1)
// q<=d;
//end
//
//endmodule
| 6.672761 |
module nop_32 (
d,
q
);
input [32-1:0] d;
output [32-1:0] q;
assign q = d;
endmodule
| 7.567936 |
module zeroer_5 (
d,
en,
q
);
input en;
input [5-1:0] d;
output [5-1:0] q;
assign q = (en) ? d : 0;
endmodule
| 6.817711 |
module cop2 (
clk,
resetn,
stalled,
fromcpu,
fromcpu_en,
tocpu,
tocpu_en,
//Global I/O
tocop2,
tocop2_en,
tocop2_wait,
fromcop2,
fromcop2_en,
fromcop2_wait
);
input clk;
input resetn;
output stalled;
input [31:0] fromcpu;
input fromcpu_en;
output [31:0] tocpu;
input tocpu_en;
output [31:0] tocop2;
output tocop2_en;
input tocop2_wait;
input [31:0] fromcop2;
input fromcop2_en;
output fromcop2_wait;
// not connected ports
wire clk_nc;
assign clk_nc = clk;
wire resetn_nc;
assign resetn_nc = resetn;
assign tocop2 = fromcpu;
assign tocop2_en = fromcpu_en;
assign tocpu = fromcop2;
assign fromcop2_wait = fromcop2_en & ~tocpu_en; //assign 1 if pipe is stalled
assign stalled = (fromcpu_en & tocop2_wait) || (tocpu_en & ~fromcop2_en);
endmodule
| 7.323016 |
module cop0 (
clk,
resetn,
stalled,
instr,
exception,
read_addr,
dest_addr,
fromcpu,
fromcpu_en,
tocpu,
tocpu_en,
epc_in,
ext_cause_in,
int_cause_in_stage1, //very weak - implement OR in SPREE instead
int_cause_in_stage2,
status,
badvaddr_in,
badvaddr_we
);
//parameter NUMSTAGESTIMES32=64;
//parameter NUMSTAGES=NUMSTAGESTIMES32/32;
input clk;
input resetn;
output stalled;
input [31:0] instr;
output exception;
input [4:0] read_addr;
input [4:0] dest_addr;
input [31:0] fromcpu;
input fromcpu_en;
output [31:0] tocpu;
input tocpu_en;
input [31:0] epc_in;
input [31:0] ext_cause_in;
input [31:0] int_cause_in_stage1;
input [31:0] int_cause_in_stage2;
output [31:0] status;
input [31:0] badvaddr_in;
input badvaddr_we;
// not connected ports
wire [31:0] instr_nc;
assign instr_nc = instr;
wire [31:0] cause_in;
reg [31:0] epc_out;
reg [31:0] cause_out;
reg [31:0] status;
reg [31:0] badvaddr_out;
reg [31:0] tocpu;
assign cause_in = ext_cause_in | int_cause_in_stage1 | int_cause_in_stage2;
always @(posedge clk)
if (!resetn) epc_out <= 0;
else if (fromcpu_en && dest_addr == 14) epc_out <= fromcpu;
else if (exception) epc_out <= epc_in;
always @(posedge clk)
if (!resetn) cause_out <= 0;
else if (fromcpu_en && dest_addr == 13) cause_out <= fromcpu;
else cause_out <= cause_in;
always @(posedge clk)
if (!resetn) status <= 0;
else if (fromcpu_en && dest_addr == 12) status <= fromcpu;
else if (exception) status[5:0] <= {status[3:0], 2'b0};
always @(posedge clk)
if (!resetn) badvaddr_out <= 0;
else if (fromcpu_en && dest_addr == 8) badvaddr_out <= fromcpu;
else if (badvaddr_we) badvaddr_out <= badvaddr_in;
always @(posedge clk)
tocpu <= (read_addr==14) ? epc_out :
(read_addr==13) ? cause_out :
(read_addr==8) ? badvaddr_out : status;
// 1 cycle stall
multicyclestall mc (
tocpu_en,
0,
clk,
resetn,
stalled
);
//assign stalled= 0;
assign exception = ((|(cause_in[15:8] & status[15:8])) && status[0]);
endmodule
| 6.731171 |
module pipereg_6(d,clk,resetn,en,squashn,q);
//
//input clk;
//input resetn;
//input en;
//input squashn;
//input [6-1:0] d;
//output [6-1:0] q;
//reg [6-1:0] q;
//
//always @(posedge clk) //synchronous reset
//begin
// if (resetn==0 || squashn==0)
// q<=0;
// else if (en==1)
// q<=d;
//end
//
//endmodule
| 6.611143 |
module branch_detector (
opcode,
func,
is_branch
);
input [5:0] opcode;
input [5:0] func;
output is_branch;
wire is_special;
wire [5:0] func_local;
assign func_local = func & 6'b111000;
assign is_special = !(|opcode);
assign is_branch=((!(|opcode[5:3])) && !is_special) ||
((is_special)&&(func_local==6'b001000));
endmodule
| 7.697954 |
module vmem_busmux_128_7_32_5 (
clk,
resetn,
sel,
in,
out
);
parameter SELWIDTH = 7 - 5; // LOG2(INWIDTH/OUTWIDTH) = 4
input clk;
input resetn;
input [SELWIDTH-1 : 0] sel;
input [128-1 : 0] in;
output [32-1 : 0] out;
reg [32-1 : 0] out;
wire clk_nc, resetn_nc;
assign clk_nc = clk;
assign resetn_nc = resetn;
always @* begin
out = 0;
for (k = 0; k < 128 / 32; k = k + 1) if (k == sel) out = in[k*32+:32];
end
endmodule
| 6.612997 |
module vmem_crossbar_128_7_8_32_5 (
clk,
resetn,
sel,
in,
out
);
parameter SELWIDTH = 7 - 5; // LOG2(INWIDTH/OUTWIDTH) = 4
input clk;
input resetn;
input [(SELWIDTH*8)-1 : 0] sel;
input [128-1 : 0] in;
output [(32*8)-1 : 0] out;
vmem_busmux_128_7_32_5 bmux0 (
clk,
resetn,
sel[(0+1)*SELWIDTH-1 : 0*SELWIDTH],
in,
out[(0+1)*32-1 : 0*32]
);
vmem_busmux_128_7_32_5 bmux1 (
clk,
resetn,
sel[(1+1)*SELWIDTH-1 : 1*SELWIDTH],
in,
out[(1+1)*32-1 : 1*32]
);
vmem_busmux_128_7_32_5 bmux2 (
clk,
resetn,
sel[(2+1)*SELWIDTH-1 : 2*SELWIDTH],
in,
out[(2+1)*32-1 : 2*32]
);
vmem_busmux_128_7_32_5 bmux3 (
clk,
resetn,
sel[(3+1)*SELWIDTH-1 : 3*SELWIDTH],
in,
out[(3+1)*32-1 : 3*32]
);
vmem_busmux_128_7_32_5 bmux4 (
clk,
resetn,
sel[(4+1)*SELWIDTH-1 : 4*SELWIDTH],
in,
out[(4+1)*32-1 : 4*32]
);
vmem_busmux_128_7_32_5 bmux5 (
clk,
resetn,
sel[(5+1)*SELWIDTH-1 : 5*SELWIDTH],
in,
out[(5+1)*32-1 : 5*32]
);
vmem_busmux_128_7_32_5 bmux6 (
clk,
resetn,
sel[(6+1)*SELWIDTH-1 : 6*SELWIDTH],
in,
out[(6+1)*32-1 : 6*32]
);
vmem_busmux_128_7_32_5 bmux7 (
clk,
resetn,
sel[(7+1)*SELWIDTH-1 : 7*SELWIDTH],
in,
out[(7+1)*32-1 : 7*32]
);
endmodule
| 7.332389 |
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