code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module vstore_data_translator (
write_data, // data in least significant position
d_address,
store_size, // 0-byte, 1-16bits, 2-32bits, 3-64bits
d_byteena,
d_writedataout
); // shifted data to coincide with address
parameter WIDTH = 32;
input [WIDTH-1:0] write_data;
input [1:0] d_address;
input [1:0] store_size;
output [3:0] d_byteena;
output [WIDTH-1:0] d_writedataout;
reg [3:0] d_byteena;
reg [WIDTH-1:0] d_writedataout;
always @* begin
case (store_size)
2'b00: begin
case (d_address[1:0])
2'b00: begin
d_byteena = 4'b1000;
d_writedataout = {write_data[7:0], 24'b0};
end
2'b01: begin
d_byteena = 4'b0100;
d_writedataout = {8'b0, write_data[7:0], 16'b0};
end
2'b10: begin
d_byteena = 4'b0010;
d_writedataout = {16'b0, write_data[7:0], 8'b0};
end
default: begin
d_byteena = 4'b0001;
d_writedataout = {24'b0, write_data[7:0]};
end
endcase
end
2'b01: begin
d_writedataout = (d_address[1]) ? {16'b0, write_data[15:0]} : {write_data[15:0], 16'b0};
d_byteena = (d_address[1]) ? 4'b0011 : 4'b1100;
end
default: begin
d_byteena = 4'b1111;
d_writedataout = write_data;
end
endcase
end
endmodule
| 9.156778 |
module dpram1_26_67108864_32 (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteen_a,
byteen_b,
out_a,
out_b
);
// parameter AWIDTH=10;
// parameter NUM_WORDS=1024;
// parameter DWIDTH=32;
// parameter LOG2DWIDTH = $clog2(DWIDTH);
input clk;
input [(26-1):0] address_a;
input [(26-1):0] address_b;
input wren_a;
input wren_b;
input [(32/8)-1:0] byteen_a;
input [(32/8)-1:0] byteen_b;
input [(32-1):0] data_a;
input [(32-1):0] data_b;
output reg [(32-1):0] out_a;
output reg [(32-1):0] out_b;
`ifdef SIMULATION_MEMORY
integer i;
integer k;
//reg [32-1:0] ram [67108864-1:0];
reg [(((1096-1)-(0)+1)*((32-1)-(0)+1))-1 : 0] ram;
reg [25:0] addr_a;
reg [25:0] addr_b;
initial begin
//This is TOO big for 256 MB RAM! We right shift data by 1
//$readmemh("instr.dat",ram,'h100_0000);
$readmemh("instr.dat", ram, 'h100);
//$readmemh("data.dat",ram,'h400_0000>>1);
$readmemh("data.dat", ram, 'h400 >> 1);
end
always @(*) begin
addr_a = address_a << 26 - 26;
addr_b = address_b << 26 - 26;
end
always @(posedge clk) begin
if (wren_a) begin
for (k = 0; k < 32 / 32; k = k + 1) begin
for (i = 0; i < 4; i = i + 1) begin
if (byteen_a[((32/8-1)-((4*k)+i))]) ram[addr_a+k][(i*8)+:8] <= data_a[((32*k)+(i*8))+:8];
end
end
end else begin
for (i = 0; i < 32 / 32; i = i + 1) begin
out_a[(32*i)+:32] <= ram[addr_a+i];
end
end
if (wren_b) begin
for (k = 0; k < 32 / 32; k = k + 1) begin
for (i = 0; i < 4; i = i + 1) begin
if (byteen_b[((32/8-1)-((4*k)+i))]) ram[addr_b+k][(i*8)+:8] <= data_b[((32*k)+(i*8))+:8];
end
end
end else begin
for (i = 0; i < 32 / 32; i = i + 1) begin
out_b[32*i+:32] <= ram[addr_b+i];
end
end
end
`else
// Not connected wires
wire [(32/8)-1:0] byteen_a_nc;
wire [(32/8)-1:0] byteen_b_nc;
assign byteen_a_nc = byteen_a;
assign byteen_b_nc = byteen_b;
dual_port_ram u_dual_port_ram (
.addr1(address_a[11:0]),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b[11:0]),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
`endif
endmodule
| 6.955389 |
module vlane_barrelshifter_16_4(clk, resetn,
opB, sa,
op,
result);
//parameter 16=32;
//parameter 4=5;
//Shifts the first 2 bits in one cycle, the rest in the next cycle
//parameter (4-2)=4-2;
input clk;
input resetn;
input [16-1:0] opB;
input [4-1:0] sa; // Shift Amount
input [2-1:0] op;
output [16-1:0] result;
wire sign_ext;
wire shift_direction;
assign sign_ext=op[1];
assign shift_direction=op[0];
wire dum,dum_,dum2;
wire [16-1:0] partial_result_,partial_result;
`ifndef USE_INHOUSE_LOGIC
`define USE_INHOUSE_LOGIC
`endif
`ifdef USE_INHOUSE_LOGIC
wire [17-1:0] local_shifter_inst1_result;
assign {dum,partial_result} = local_shifter_inst1_result;
wire [2-1:0] local_shifter_inst1_distance;
assign local_shifter_inst1_distance = sa&(32'hffffffff<<(((4-2)>0) ? (4-2) : 0));
wire [17-1:0] local_shifter_inst1_data;
assign local_shifter_inst1_data = {sign_ext&opB[16-1],opB};
local_shifter_17_2_ARITHMATIC local_shifter_inst1(
.data(local_shifter_inst1_data),
.distance(local_shifter_inst1_distance),
.direction(shift_direction),
.result(local_shifter_inst1_result)
);
//defparam
// local_shifter_inst1.LPM_WIDTH = 16+1,
// local_shifter_inst1.LPM_WIDTHDIST = 4,
// local_shifter_inst1.LPM_SHIFTTYPE="ARITHMETIC";
`else
lpm_clshift shifter_inst1(
.data({sign_ext&opB[16-1],opB}),
.distance(sa&(32'hffffffff<<(((4-2)>0) ? (4-2) : 0))),
.direction(shift_direction),
.result(dum,partial_result));
defparam
shifter_inst1.lpm_width = 16+1,
shifter_inst1.lpm_widthdist = 4,
shifter_inst1.lpm_shifttype="ARITHMETIC";
`endif
wire [17-1:0] partial_reg_q;
assign partial_reg_q = {dum_,partial_result_};
register_17 partial_reg
({dum,partial_result},clk,resetn,1'b1,partial_reg_q);
wire [5-1:0] sa_2;
wire shift_direction_2;
register_5 secondstage (sa, clk,resetn,1'b1,sa_2);
register_1 secondstagedir (shift_direction, clk,resetn,1'b1,shift_direction_2);
`ifdef USE_INHOUSE_LOGIC
wire [17-1:0] local_shifter_inst2_result;
assign {dum2,result} = local_shifter_inst2_result;
wire [2-1:0] local_shifter_inst2_distance;
assign local_shifter_inst2_distance = sa_2[(4-2)-1:0];
wire [17-1:0] local_shifter_inst2_data;
assign local_shifter_inst2_data = {dum_,partial_result_};
local_shifter_17_2_ARITHMATIC local_shifter_inst2(
.data(local_shifter_inst2_data),
.distance(local_shifter_inst2_distance),
.direction(shift_direction_2),
.result(local_shifter_inst2_result)
);
// defparam
// local_shifter_inst2.LPM_WIDTH = 16+1,
// local_shifter_inst2.LPM_WIDTHDIST = ((4-2)>0) ? (4-2) : 1,
// local_shifter_inst2.LPM_SHIFTTYPE ="ARITHMETIC";
`else
lpm_clshift_17_2_ARITHMATIC shifter_inst2(
.data({dum_,partial_result_}),
.distance(sa_2[(((4-2)>0) ? (4-2)-1 : 0):0]),
.direction(shift_direction_2),
.result({dum2,resulti}));
defparam
shifter_inst2.lpm_width = 16+1,
shifter_inst2.lpm_widthdist = ((4-2)>0) ? (4-2) : 1,
shifter_inst2.lpm_shifttype="ARITHMETIC";
`endif
endmodule
| 7.537708 |
module vregfile_base_32_16_4 (
clk,
resetn,
a_reg,
a_en,
a_readdataout,
c_reg,
c_writedatain,
c_we
);
input clk;
input resetn;
input [4-1:0] a_reg, c_reg;
output [32-1:0] a_readdataout;
input [32-1:0] c_writedatain;
input a_en, c_we;
ram_wrapper_4_16_32 reg_file1 (
.clk(clk),
.resetn(resetn),
.rden_a(1'b0),
.rden_b(a_en),
.address_a(c_reg[4-1:0]),
.address_b(a_reg[4-1:0]),
.wren_a(c_we),
.wren_b(1'b0),
.data_a(c_writedatain),
.data_b(0),
.out_a(),
.out_b(a_readdataout)
);
endmodule
| 7.008004 |
module bfloat_mult_16 (
input clk,
input resetn,
input en,
input stall,
input [16-1:0] a,
input [16-1:0] b,
output reg [16-1:0] out
);
always @(posedge clk) begin
if (!resetn) out <= 'h0;
else if (en) out <= a * b;
end
endmodule
| 6.919654 |
module activation_16 (
input clk,
input resetn,
input en,
input stall,
input [16-1:0] a,
output reg [16-1:0] out
);
always @(posedge clk) begin
if (!resetn) out <= 'h0;
else if (en)
if (a > 0) out <= a;
else out <= 0;
end
endmodule
| 7.789715 |
module PDO08CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.68925 |
module PDO12CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.566034 |
module PDO24CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.504196 |
module PRO08CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.516191 |
module PRT24DGZ (
I,
OEN,
PAD
);
input I, OEN;
output PAD;
bufif0 (PAD, I, OEN);
always @(PAD) begin
if (!$test$plusargs("bus_conflict_off"))
if ($countdrivers(PAD) && (PAD === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime);
end
specify
(I => PAD) = (0, 0);
(OEN => PAD) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.709022 |
module PRO08CDG (
I,
PAD
);
input I;
output PAD;
endmodule
| 6.516191 |
module PRT24DGZ (
I,
OEN,
PAD
);
input I;
input OEN;
output PAD;
endmodule
| 6.709022 |
module PDO08CDG (
I,
PAD
);
input I;
output PAD;
endmodule
| 6.68925 |
module PDO12CDG (
I,
PAD
);
input I;
output PAD;
endmodule
| 6.566034 |
module PDO24CDG (
I,
PAD
);
input I;
output PAD;
endmodule
| 6.504196 |
module PDO08CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.68925 |
module PDO12CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.566034 |
module PDO24CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.504196 |
module PRO08CDG (
I,
PAD
);
input I;
output PAD;
buf (PAD, I);
specify
(I => PAD) = (0, 0);
endspecify
endmodule
| 6.516191 |
module PRT24DGZ (
I,
OEN,
PAD
);
input I, OEN;
output PAD;
bufif0 (PAD, I, OEN);
always @(PAD) begin
if (!$test$plusargs("bus_conflict_off"))
if ($countdrivers(PAD) && (PAD === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime);
end
specify
(I => PAD) = (0, 0);
(OEN => PAD) = (0, 0, 0, 0, 0, 0);
endspecify
endmodule
| 6.709022 |
module tp_lpf_heavy (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 220; //Sample at 49.152/220 = 223418Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.0041276697, 0.0041276697
//1.0000000, -0.99174466
reg signed [17:0] A2;
reg signed [17:0] B2;
reg signed [17:0] B1;
wire signed [15:0] audio_post_lpf1;
always @(*) begin
A2 = -18'd32498;
B1 = 18'd135;
B2 = 18'd135;
end
iir_1st_order lpf6db (
.clk(clk),
.reset(reset),
.div(div),
.A2(A2),
.B1(B1),
.B2(B2),
.in(in),
.out(audio_post_lpf1)
);
assign out = audio_post_lpf1;
endmodule
| 7.215321 |
module tp_lpf_light (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 220; //Sample at 49.152/220 = 223418Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.017174022, 0.017174022
//1.0000000, -0.96565196
reg signed [17:0] A2;
reg signed [17:0] B2;
reg signed [17:0] B1;
wire signed [15:0] audio_post_lpf1;
always @(*) begin
A2 = -18'd31642;
B1 = 18'd563;
B2 = 18'd563;
end
iir_1st_order lpf6db (
.clk(clk),
.reset(reset),
.div(div),
.A2(A2),
.B1(B1),
.B2(B2),
.in(in),
.out(audio_post_lpf1)
);
assign out = audio_post_lpf1;
endmodule
| 7.237937 |
module tp_lpf_medium (
input clk,
input reset,
input signed [15:0] in,
output signed [15:0] out
);
reg [9:0] div = 220; //Sample at 49.152/220 = 223418Hz
//Coefficients computed with Octave/Matlab/Online filter calculators.
//or with scipy.signal.bessel or similar tools
//0.0053024160, 0.0053024160
//1.0000000, -0.98939517
reg signed [17:0] A2;
reg signed [17:0] B2;
reg signed [17:0] B1;
wire signed [15:0] audio_post_lpf1;
always @(*) begin
A2 = -18'd32420;
B1 = 18'd174;
B2 = 18'd174;
end
iir_1st_order lpf6db (
.clk(clk),
.reset(reset),
.div(div),
.A2(A2),
.B1(B1),
.B2(B2),
.in(in),
.out(audio_post_lpf1)
);
assign out = audio_post_lpf1;
endmodule
| 7.013674 |
module tq_dequant2x2_dc (
qpmod6_i,
qpdiv6_i,
scale00_i,
scale01_i,
scale10_i,
scale11_i,
coeff00_o,
coeff01_o,
coeff10_o,
coeff11_o
);
parameter IN_WIDTH = 15;
parameter OUT_WIDTH = 15;
input [2:0] qpmod6_i;
input [3:0] qpdiv6_i;
input signed [IN_WIDTH-1:0] scale00_i;
input signed [IN_WIDTH-1:0] scale01_i;
input signed [IN_WIDTH-1:0] scale10_i;
input signed [IN_WIDTH-1:0] scale11_i;
output signed [OUT_WIDTH-1:0] coeff00_o;
output signed [OUT_WIDTH-1:0] coeff01_o;
output signed [OUT_WIDTH-1:0] coeff10_o;
output signed [OUT_WIDTH-1:0] coeff11_o;
wire signed [25-1:0] coeff00_o_w;
wire signed [25-1:0] coeff01_o_w;
wire signed [25-1:0] coeff10_o_w;
wire signed [25-1:0] coeff11_o_w;
wire [IN_WIDTH+9:0] bias_w;
reg [3:0] shift_len_w;
reg signed [5:0] de_mf00_w;
wire signed [IN_WIDTH+9:0] product_tmp00_w;
wire signed [IN_WIDTH+9:0] product_tmp01_w;
wire signed [IN_WIDTH+9:0] product_tmp10_w;
wire signed [IN_WIDTH+9:0] product_tmp11_w;
assign product_tmp00_w = scale00_i * ({de_mf00_w, 4'b0});
assign product_tmp01_w = scale01_i * ({de_mf00_w, 4'b0});
assign product_tmp10_w = scale10_i * ({de_mf00_w, 4'b0});
assign product_tmp11_w = scale11_i * ({de_mf00_w, 4'b0});
assign coeff00_o_w = (qpdiv6_i < 5)? ((product_tmp00_w + bias_w) >> shift_len_w) : (product_tmp00_w << shift_len_w);
assign coeff01_o_w = (qpdiv6_i < 5)? ((product_tmp01_w + bias_w) >> shift_len_w) : (product_tmp01_w << shift_len_w);
assign coeff10_o_w = (qpdiv6_i < 5)? ((product_tmp10_w + bias_w) >> shift_len_w) : (product_tmp10_w << shift_len_w);
assign coeff11_o_w = (qpdiv6_i < 5)? ((product_tmp11_w + bias_w) >> shift_len_w) : (product_tmp11_w << shift_len_w);
assign coeff00_o = coeff00_o_w[14 : 0];
assign coeff01_o = coeff01_o_w[14 : 0];
assign coeff10_o = coeff10_o_w[14 : 0];
assign coeff11_o = coeff11_o_w[14 : 0];
assign bias_w = 25'd1 << (shift_len_w - 1'b1);
always @(*)
case (qpdiv6_i)
4'b0000: shift_len_w = 3'd5;
4'b0001: shift_len_w = 3'd4;
4'b0010: shift_len_w = 3'd3;
4'b0011: shift_len_w = 3'd2;
4'b0100: shift_len_w = 3'd1;
default: shift_len_w = qpdiv6_i - 3'd5;
endcase
always @(*)
case (qpmod6_i)
3'b000: de_mf00_w = 5'd10;
3'b001: de_mf00_w = 5'd11;
3'b010: de_mf00_w = 5'd13;
3'b011: de_mf00_w = 5'd14;
3'b100: de_mf00_w = 5'd16;
3'b101: de_mf00_w = 5'd18;
default: de_mf00_w = 5'd0;
endcase
endmodule
| 6.937702 |
module tq_quant2x2_dc (
qpmod6_i,
qpdiv6_i,
intra,
coeff00_i,
coeff01_i,
coeff10_i,
coeff11_i,
scale00_o,
scale01_o,
scale10_o,
scale11_o
);
parameter IN_WIDTH = 15;
parameter OUT_WIDTH = 15;
input [2:0] qpmod6_i;
input [3:0] qpdiv6_i;
input intra;
input [IN_WIDTH-1:0] coeff00_i;
input [IN_WIDTH-1:0] coeff01_i;
input [IN_WIDTH-1:0] coeff10_i;
input [IN_WIDTH-1:0] coeff11_i;
output [OUT_WIDTH-1:0] scale00_o;
output [OUT_WIDTH-1:0] scale01_o;
output [OUT_WIDTH-1:0] scale10_o;
output [OUT_WIDTH-1:0] scale11_o;
wire [2:0] qpmod6_i;
wire [3:0] qpdiv6_i;
wire [23:0] bias_w;
wire [4:0] rshift_len_w;
reg [13:0] mf00_w;
wire [IN_WIDTH-2:0] coef_abs00;
wire [IN_WIDTH-2:0] coef_abs01;
wire [IN_WIDTH-2:0] coef_abs10;
wire [IN_WIDTH-2:0] coef_abs11;
wire [IN_WIDTH-1:0] scale_abs00;
wire [IN_WIDTH-1:0] scale_abs01;
wire [IN_WIDTH-1:0] scale_abs10;
wire [IN_WIDTH-1:0] scale_abs11;
wire [31:0] scale_abs00_w;
wire [31:0] scale_abs01_w;
wire [31:0] scale_abs10_w;
wire [31:0] scale_abs11_w;
assign coef_abs00 = coeff00_i[IN_WIDTH-1]? (~coeff00_i[IN_WIDTH-2:0] + 1'b1) : coeff00_i[IN_WIDTH-2:0];
assign coef_abs01 = coeff01_i[IN_WIDTH-1]? (~coeff01_i[IN_WIDTH-2:0] + 1'b1) : coeff01_i[IN_WIDTH-2:0];
assign coef_abs10 = coeff10_i[IN_WIDTH-1]? (~coeff10_i[IN_WIDTH-2:0] + 1'b1) : coeff10_i[IN_WIDTH-2:0];
assign coef_abs11 = coeff11_i[IN_WIDTH-1]? (~coeff11_i[IN_WIDTH-2:0] + 1'b1) : coeff11_i[IN_WIDTH-2:0];
assign scale_abs00_w = (coef_abs00 * mf00_w + bias_w) >> rshift_len_w;
assign scale_abs01_w = (coef_abs01 * mf00_w + bias_w) >> rshift_len_w;
assign scale_abs10_w = (coef_abs10 * mf00_w + bias_w) >> rshift_len_w;
assign scale_abs11_w = (coef_abs11 * mf00_w + bias_w) >> rshift_len_w;
assign scale_abs00 = scale_abs00_w[14 : 0];
assign scale_abs01 = scale_abs01_w[14 : 0];
assign scale_abs10 = scale_abs10_w[14 : 0];
assign scale_abs11 = scale_abs11_w[14 : 0];
assign scale00_o = coeff00_i[IN_WIDTH-1] ? (~scale_abs00 + 1'b1) : scale_abs00;
assign scale01_o = coeff01_i[IN_WIDTH-1] ? (~scale_abs01 + 1'b1) : scale_abs01;
assign scale10_o = coeff10_i[IN_WIDTH-1] ? (~scale_abs10 + 1'b1) : scale_abs10;
assign scale11_o = coeff11_i[IN_WIDTH-1] ? (~scale_abs11 + 1'b1) : scale_abs11;
//specify shift length
assign rshift_len_w = qpdiv6_i + 5'd16; //qbits = 15 + 1 + qp/6
assign bias_w = 24'd682 << (3'd5 + qpdiv6_i); //changed!!!
always @(*) begin
case (qpmod6_i)
3'b000: mf00_w = 14'd13107;
3'b001: mf00_w = 14'd11916;
3'b010: mf00_w = 14'd10082;
3'b011: mf00_w = 14'd9362;
3'b100: mf00_w = 14'd8192;
3'b101: mf00_w = 14'd7282;
default: mf00_w = 14'd0;
endcase
end
endmodule
| 7.081817 |
module tq_ram_sp_32x16 (
data_o,
clk,
cen_i, // low active
wen_i, // low active
addr_i,
data_i
);
//--- input/output ------------------------------------------------
input clk;
input cen_i;
input wen_i;
input [5 -1 : 0] addr_i;
input [16-1 : 0] data_i;
output [16-1 : 0] data_o;
`ifdef RTL_MODEL
ram_1p #(
.Word_Width(16),
.Addr_Width(5)
) u_ram_1p (
.clk (clk),
.cen_i (cen_i),
.oen_i (1'b0),
.wen_i (wen_i),
.addr_i(addr_i),
.data_i(data_i),
.data_o(data_o)
);
`endif
`ifdef XM_MODEL
rfsphd_32x16 u_rfsphd_32x16 (
.Q (data_o), // output data
.CLK (clk), // clk
.CEN (cen_i), // low active
.WEN (wen_i), // low active
.A (addr_i), // address
.D (data_i), // input data
.EMA (3'b1),
.EMAW (2'b0),
.RET1N(1'b1)
);
`endif
endmodule
| 7.218486 |
module JK (
output reg Q,
output wire nQ,
input wire J,
input wire K,
input wire C
);
initial Q = 0;
not (nQ, Q);
always @(negedge C)
case ({
J, K
})
2'b01: Q = 0;
2'b10: Q = 1;
2'b11: Q = ~Q;
endcase
endmodule
| 8.11998 |
module CAMBIO (
output wire [3:0] Q,
input wire [3:0] I
);
wire [3:0] nI;
wire aQ2_1, aQ2_2, aQ2_3;
wire aQ1_1, aQ1_2, aQ1_3, aQ1_4;
wire aQ0_1, aQ0_2, aQ0_3;
not n4 (nI[0], I[0]);
not n5 (nI[1], I[1]);
not n6 (nI[2], I[2]);
not n7 (nI[3], I[3]);
//CAMBIOS 3->4; 5->0; 8->10
//Q3
assign Q[3] = I[3];
//Q2
and a19 (aQ2_1, I[2], nI[0]);
and a20 (aQ2_2, I[3], I[2]);
and a21 (aQ2_3, nI[3], I[1], I[0]);
or o9 (Q[2], aQ2_1, aQ2_2, aQ2_3);
//Q1
and a22 (aQ1_1, I[1], nI[0]);
and a23 (aQ1_2, I[2], I[1]);
and a24 (aQ1_3, I[3], I[1]);
and a25 (aQ1_4, I[3], nI[2], nI[0]);
or o10 (Q[1], aQ1_1, aQ1_2, aQ1_3, aQ1_4);
//Q0
and a26 (aQ0_1, I[3], I[0]);
and a27 (aQ0_2, nI[2], nI[1], I[0]);
and a28 (aQ0_3, I[2], I[1], I[0]);
or o11 (Q[0], aQ0_1, aQ0_2, aQ0_3);
endmodule
| 6.500928 |
module trab8 (
input CLOCK_50,
output VGA_HS,
output VGA_VS,
output VGA_R,
output VGA_G,
output VGA_B
);
reg [ 3:0] Red;
reg [ 3:0] Green;
reg [ 3:0] Blue;
reg [11:0] V_Sync;
reg [11:0] H_Sync;
reg [11:0] i;
reg [11:0] j;
reg [ 3:0] count = 0;
assign VGA_R = Red;
assign VGA_B = Blue;
assign VGA_G = Green;
assign VGA_HS = H_Sync;
assign VGA_VS = V_Sync;
always @(posedge CLOCK_50) begin
case (count)
0: begin
i <= 0;
j <= 0;
count <= 2;
end
2: begin
if (i < 480) begin
count <= 3;
j <= 0;
end else count <= 4;
end
3: begin
if (j < 640) begin
// sempe alterar aqui (dentro for)
H_Sync <= i;
V_Sync <= j;
if (i > 200 & j > 200 & i < 300 & j < 300) begin
Red <= 4'b1;
Green <= 4'b1;
Blue <= 4'b1;
end else begin
Red <= 4'b0;
Green <= 4'b0;
Blue <= 4'b0;
end
//altera até aqui (dentro for)
j <= j + 1;
count <= 3;
end else begin
i <= i + 1;
count <= 2;
end
end
endcase
end
endmodule
| 6.594484 |
module trace (
input wire clk,
input wire rst,
input wire [136:0] dbg_i
);
wire [31:0] pc;
wire [31:0] sp;
wire [31:0] tos;
wire [31:0] nos;
wire [7:0] inst;
wire valid_dbg;
integer tracefile;
assign pc = dbg_i[31:0]; //pc
assign sp = dbg_i[63:32]; //sp
assign tos = dbg_i[95:64]; //tos
assign nos = dbg_i[127:96]; //nos
assign inst = dbg_i[135:128]; //inst
assign dbgok = dbg_i[136]; // valid data
reg [31:0] counter;
initial begin
tracefile = $fopen("trace.log", "w");
$fwrite(tracefile, "#PC Opcode SP A=[SP] B=[SP+1] Clk Counter\n");
$fwrite(tracefile, "#----------------------------------------------------------\n");
$fwrite(tracefile, "\n");
counter <= 0;
end
always @(posedge clk) begin
if (rst == 1) begin
counter <= 0;
end else begin
counter <= counter + 1;
if (dbgok == 1) begin
$fwrite(tracefile, "0x%h 0x%h 0x%h 0x%h 0x%h 0x%h \n", pc, inst, sp,
tos, nos, counter);
end
end
end
endmodule
| 6.769849 |
module traceback_compare (
curr_index,
top_score,
diag_score,
left_score,
current_score,
//seq1,
// seq2,
// seq1_out,
// seq2_out,
next_index
);
parameter n = 4;
input [31:0] top_score, diag_score, left_score, current_score;
input [n:0] curr_index;
output [n:0] next_index;
assign next_index = (diag_score<top_score)?((top_score>left_score)?curr_index-n-1:curr_index-1):((diag_score<left_score)?curr_index-1:curr_index-n-2);
endmodule
| 6.991434 |
module traceback_prefetch_column_finder (
column_k1,
column_k0,
prefetch_request,
in_block_x_startpoint,
prefetch_x_startpoint,
prefetch_column
);
//I/O
input [0:`MEM_WIDTH*`DIRECTION_WIDTH-1] column_k0, column_k1;
input [1:0] prefetch_request;
input [`POSITION_WIDTH-1:0] in_block_x_startpoint, prefetch_x_startpoint;
output reg [0:`PREFETCH_LENGTH*`DIRECTION_WIDTH-1] prefetch_column;
//wire
reg [`MEM_WIDTH*`DIRECTION_WIDTH-1:0] column_k0_arranged, column_k1_arranged;
wire [`MEM_WIDTH*`DIRECTION_WIDTH*2-1:0] memory_column_cascade,
memory_column_cascade_shifted_current,
memory_column_cascade_shifted_prefetch;
integer i;
//combinaitonal
always @(*) begin
for (i = 0; i < `MEM_WIDTH; i = i + 1) begin
column_k0_arranged[i*`DIRECTION_WIDTH+:`DIRECTION_WIDTH] = column_k0[(i*`DIRECTION_WIDTH+4)-:`DIRECTION_WIDTH];
column_k1_arranged[i*`DIRECTION_WIDTH+:`DIRECTION_WIDTH] = column_k1[(i*`DIRECTION_WIDTH+4)-:`DIRECTION_WIDTH];
end
end
assign memory_column_cascade = {column_k1_arranged, column_k0_arranged};
assign memory_column_cascade_shifted_current = memory_column_cascade >> (({`log_MEM_WIDTH{1'b1}}-in_block_x_startpoint[`log_MEM_WIDTH-1:0])*`DIRECTION_WIDTH);
assign memory_column_cascade_shifted_prefetch = memory_column_cascade >> (({`log_MEM_WIDTH{1'b1}}-prefetch_x_startpoint[`log_MEM_WIDTH-1:0])*`DIRECTION_WIDTH);
always @(*) begin
if (prefetch_request == 2'b10) begin
prefetch_column = memory_column_cascade_shifted_prefetch[`PREFETCH_LENGTH*`DIRECTION_WIDTH-1:0];
end else if (prefetch_request == 2'b01) begin
prefetch_column = memory_column_cascade_shifted_current[`PREFETCH_LENGTH*`DIRECTION_WIDTH-1:0];
end else begin
prefetch_column = memory_column_cascade_shifted_current[`PREFETCH_LENGTH*`DIRECTION_WIDTH-1:0];
end
end
endmodule
| 6.544244 |
module traceback_prefetch_row_dealer (
row_k1,
row_k0,
prefetch_request,
in_block_y_startpoint,
prefetch_y_startpoint,
prefetch_row
);
//I/O
input [`N*`DIRECTION_WIDTH-1:0] row_k0, row_k1;
input [1:0] prefetch_request;
input [`POSITION_WIDTH-1:0] in_block_y_startpoint, prefetch_y_startpoint;
output reg [0:`PREFETCH_LENGTH*`DIRECTION_WIDTH-1] prefetch_row;
//wire
wire [`N*`DIRECTION_WIDTH*2-1:0] memory_row_cascade, memory_row_cascade_shifted_current, memory_row_cascade_shifted_prefetch;
//combinaitonal
assign memory_row_cascade = {row_k1, row_k0};
assign memory_row_cascade_shifted_current = memory_row_cascade >> (({`log_N{1'b1}}-in_block_y_startpoint[`log_N-1:0])*`DIRECTION_WIDTH);
assign memory_row_cascade_shifted_prefetch = memory_row_cascade >> (({`log_N{1'b1}}-prefetch_y_startpoint[`log_N-1:0])*`DIRECTION_WIDTH);
always @(*) begin
if (prefetch_request == 2'b10) begin
prefetch_row = memory_row_cascade_shifted_prefetch[`PREFETCH_LENGTH*`DIRECTION_WIDTH-1:0];
end else if (prefetch_request == 2'b01) begin
prefetch_row = memory_row_cascade_shifted_current[`PREFETCH_LENGTH*`DIRECTION_WIDTH-1:0];
end else begin
prefetch_row = memory_row_cascade_shifted_current[`PREFETCH_LENGTH*`DIRECTION_WIDTH-1:0];
end
end
endmodule
| 6.544244 |
module testbench (
input clk,
mem_ready_0,
mem_ready_1
);
// set this to 1 to test generation of counter examples
localparam ENABLE_COUNTERS = 0;
reg resetn = 0;
always @(posedge clk) resetn <= 1;
(* keep *) wire trap_0, trace_valid_0, mem_valid_0, mem_instr_0;
(* keep *) wire [3:0] mem_wstrb_0;
(* keep *) wire [31:0] mem_addr_0, mem_wdata_0, mem_rdata_0;
(* keep *) wire [35:0] trace_data_0;
(* keep *) wire trap_1, trace_valid_1, mem_valid_1, mem_instr_1;
(* keep *) wire [3:0] mem_wstrb_1;
(* keep *) wire [31:0] mem_addr_1, mem_wdata_1, mem_rdata_1;
(* keep *) wire [35:0] trace_data_1;
reg [31:0] mem_0[0:2**30-1];
reg [31:0] mem_1[0:2**30-1];
assign mem_rdata_0 = mem_0[mem_addr_0>>2];
assign mem_rdata_1 = mem_1[mem_addr_1>>2];
always @(posedge clk) begin
if (resetn && mem_valid_0 && mem_ready_0) begin
if (mem_wstrb_0[3]) mem_0[mem_addr_0>>2][31:24] <= mem_wdata_0[31:24];
if (mem_wstrb_0[2]) mem_0[mem_addr_0>>2][23:16] <= mem_wdata_0[23:16];
if (mem_wstrb_0[1]) mem_0[mem_addr_0>>2][15:8] <= mem_wdata_0[15:8];
if (mem_wstrb_0[0]) mem_0[mem_addr_0>>2][7:0] <= mem_wdata_0[7:0];
end
if (resetn && mem_valid_1 && mem_ready_1) begin
if (mem_wstrb_1[3]) mem_1[mem_addr_1>>2][31:24] <= mem_wdata_1[31:24];
if (mem_wstrb_1[2]) mem_1[mem_addr_1>>2][23:16] <= mem_wdata_1[23:16];
if (mem_wstrb_1[1]) mem_1[mem_addr_1>>2][15:8] <= mem_wdata_1[15:8];
if (mem_wstrb_1[0]) mem_1[mem_addr_1>>2][7:0] <= mem_wdata_1[7:0];
end
end
(* keep *)reg [7:0] trace_balance;
reg [7:0] trace_balance_q;
always @* begin
trace_balance = trace_balance_q;
if (trace_valid_0) trace_balance = trace_balance + 1;
if (trace_valid_1) trace_balance = trace_balance - 1;
end
always @(posedge clk) begin
trace_balance_q <= resetn ? trace_balance : 0;
end
picorv32 #(
// do not change this settings
.ENABLE_COUNTERS(ENABLE_COUNTERS),
.ENABLE_TRACE(1),
// change this settings as you like
.ENABLE_REGS_DUALPORT(1),
.TWO_STAGE_SHIFT(1),
.BARREL_SHIFTER(0),
.TWO_CYCLE_COMPARE(0),
.TWO_CYCLE_ALU(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0)
) cpu_0 (
.clk (clk),
.resetn (resetn),
.trap (trap_0),
.mem_valid (mem_valid_0),
.mem_instr (mem_instr_0),
.mem_ready (mem_ready_0),
.mem_addr (mem_addr_0),
.mem_wdata (mem_wdata_0),
.mem_wstrb (mem_wstrb_0),
.mem_rdata (mem_rdata_0),
.trace_valid(trace_valid_0),
.trace_data (trace_data_0)
);
picorv32 #(
// do not change this settings
.ENABLE_COUNTERS(ENABLE_COUNTERS),
.ENABLE_TRACE(1),
// change this settings as you like
.ENABLE_REGS_DUALPORT(1),
.TWO_STAGE_SHIFT(1),
.BARREL_SHIFTER(0),
.TWO_CYCLE_COMPARE(0),
.TWO_CYCLE_ALU(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0)
) cpu_1 (
.clk (clk),
.resetn (resetn),
.trap (trap_1),
.mem_valid (mem_valid_1),
.mem_instr (mem_instr_1),
.mem_ready (mem_ready_1),
.mem_addr (mem_addr_1),
.mem_wdata (mem_wdata_1),
.mem_wstrb (mem_wstrb_1),
.mem_rdata (mem_rdata_1),
.trace_valid(trace_valid_1),
.trace_data (trace_data_1)
);
endmodule
| 6.751666 |
module testbench (
input clk,
input [31:0] mem_rdata_in,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready
);
reg resetn = 0;
always @(posedge clk) resetn <= 1;
wire cpu0_trap;
wire cpu0_mem_valid;
wire cpu0_mem_instr;
wire cpu0_mem_ready;
wire [31:0] cpu0_mem_addr;
wire [31:0] cpu0_mem_wdata;
wire [ 3:0] cpu0_mem_wstrb;
wire [31:0] cpu0_mem_rdata;
wire cpu0_trace_valid;
wire [35:0] cpu0_trace_data;
wire cpu1_trap;
wire cpu1_mem_valid;
wire cpu1_mem_instr;
wire cpu1_mem_ready;
wire [31:0] cpu1_mem_addr;
wire [31:0] cpu1_mem_wdata;
wire [ 3:0] cpu1_mem_wstrb;
wire [31:0] cpu1_mem_rdata;
wire cpu1_trace_valid;
wire [35:0] cpu1_trace_data;
wire mem_ready;
wire [31:0] mem_rdata;
assign mem_ready = cpu0_mem_valid && cpu1_mem_valid;
assign mem_rdata = mem_rdata_in;
assign cpu0_mem_ready = mem_ready;
assign cpu0_mem_rdata = mem_rdata;
assign cpu1_mem_ready = mem_ready;
assign cpu1_mem_rdata = mem_rdata;
reg [2:0] trace_balance = 3'b010;
reg [35:0] trace_buffer_cpu0 = 0, trace_buffer_cpu1 = 0;
always @(posedge clk) begin
if (resetn) begin
if (cpu0_trace_valid) trace_buffer_cpu0 <= cpu0_trace_data;
if (cpu1_trace_valid) trace_buffer_cpu1 <= cpu1_trace_data;
if (cpu0_trace_valid && !cpu1_trace_valid) trace_balance <= trace_balance << 1;
if (!cpu0_trace_valid && cpu1_trace_valid) trace_balance <= trace_balance >> 1;
end
end
always @* begin
if (resetn && cpu0_mem_ready) begin
assert (cpu0_mem_addr == cpu1_mem_addr);
assert (cpu0_mem_wstrb == cpu1_mem_wstrb);
if (cpu0_mem_wstrb[3]) assert (cpu0_mem_wdata[31:24] == cpu1_mem_wdata[31:24]);
if (cpu0_mem_wstrb[2]) assert (cpu0_mem_wdata[23:16] == cpu1_mem_wdata[23:16]);
if (cpu0_mem_wstrb[1]) assert (cpu0_mem_wdata[15:8] == cpu1_mem_wdata[15:8]);
if (cpu0_mem_wstrb[0]) assert (cpu0_mem_wdata[7:0] == cpu1_mem_wdata[7:0]);
end
if (trace_balance == 3'b010) begin
assert (trace_buffer_cpu0 == trace_buffer_cpu1);
end
end
picorv32 #(
.ENABLE_COUNTERS(0),
.REGS_INIT_ZERO(1),
.COMPRESSED_ISA(1),
.ENABLE_TRACE(1),
.TWO_STAGE_SHIFT(0),
.ENABLE_PCPI(1)
) cpu0 (
.clk (clk),
.resetn (resetn),
.trap (cpu0_trap),
.mem_valid (cpu0_mem_valid),
.mem_instr (cpu0_mem_instr),
.mem_ready (cpu0_mem_ready),
.mem_addr (cpu0_mem_addr),
.mem_wdata (cpu0_mem_wdata),
.mem_wstrb (cpu0_mem_wstrb),
.mem_rdata (cpu0_mem_rdata),
.pcpi_wr (pcpi_wr),
.pcpi_rd (pcpi_rd),
.pcpi_wait (pcpi_wait),
.pcpi_ready (pcpi_ready),
.trace_valid(cpu0_trace_valid),
.trace_data (cpu0_trace_data)
);
picorv32 #(
.ENABLE_COUNTERS(0),
.REGS_INIT_ZERO(1),
.COMPRESSED_ISA(1),
.ENABLE_TRACE(1),
.TWO_STAGE_SHIFT(1),
.TWO_CYCLE_COMPARE(1),
.TWO_CYCLE_ALU(1)
) cpu1 (
.clk (clk),
.resetn (resetn),
.trap (cpu1_trap),
.mem_valid (cpu1_mem_valid),
.mem_instr (cpu1_mem_instr),
.mem_ready (cpu1_mem_ready),
.mem_addr (cpu1_mem_addr),
.mem_wdata (cpu1_mem_wdata),
.mem_wstrb (cpu1_mem_wstrb),
.mem_rdata (cpu1_mem_rdata),
.trace_valid(cpu1_trace_valid),
.trace_data (cpu1_trace_data)
);
endmodule
| 6.751666 |
module traced_objects (
input clk,
input [2:0] obj_id,
output reg [2:0] sub_id,
output reg [0:0] type_id
);
parameter TYPE_SPHERE = 0;
parameter TYPE_PLANE = 1;
always @(posedge clk) begin
case (obj_id)
3'd0: begin
sub_id <= 0;
type_id <= TYPE_SPHERE;
end
3'd1: begin
sub_id <= 1;
type_id <= TYPE_SPHERE;
end
3'd2: begin
sub_id <= 2;
type_id <= TYPE_SPHERE;
end
3'd3: begin
sub_id <= 0;
type_id <= TYPE_PLANE;
end
default: begin
sub_id <= 3'b111;
type_id <= TYPE_PLANE;
end
endcase
end
endmodule
| 6.523174 |
module traced_planes (
input clk,
input [2:0] obj_id,
output reg [95:0] plane_origin,
output reg [95:0] plane_normal,
output reg [ 2:0] mat_id
);
always @(posedge clk) begin
case (obj_id)
3'd0: begin
plane_origin[31:0] <= 0;
plane_origin[63:32] <= $signed(-33554432); //-2.0
plane_origin[95:64] <= 0;
plane_normal[31:0] <= 0;
plane_normal[63:32] <= 32'd16777216; //1.0
plane_normal[95:64] <= 0;
mat_id <= 0;
end
default: begin
plane_origin <= ~(0);
plane_normal <= ~(0);
mat_id <= ~(0);
end
endcase
end
endmodule
| 7.324007 |
module TraceROM (
input clock,
input reset,
output stream_valid,
input stream_ready,
output [63:0] stream_bits_data,
output [ 7:0] stream_bits_keep,
output stream_bits_last,
output [47:0] macAddr,
output [31:0] length
);
bit __stream_valid;
longint __stream_data;
byte __stream_keep;
bit __stream_last;
reg __stream_valid_reg;
reg [63:0] __stream_data_reg;
reg [ 7:0] __stream_keep_reg;
reg __stream_last_reg;
string fname;
longint __macAddr;
int __length;
reg [47:0] macAddr_reg;
reg [31:0] length_reg;
assign macAddr = macAddr_reg;
assign length = length_reg;
assign stream_valid = __stream_valid_reg;
assign stream_bits_data = __stream_data_reg;
assign stream_bits_keep = __stream_keep_reg;
assign stream_bits_last = __stream_last_reg;
initial begin
if ($value$plusargs("trace=%s", fname)) begin
__length = trace_rom_init(fname);
length_reg = __length;
end
if ($value$plusargs("macaddr=%x", __macAddr)) begin
macAddr_reg = __macAddr;
end
end
always @(posedge clock) begin
if (reset) begin
__stream_valid = 0;
__stream_data = 0;
__stream_keep = 0;
__stream_last = 0;
__stream_valid_reg <= 0;
__stream_data_reg <= 0;
__stream_keep_reg <= 0;
__stream_last_reg <= 0;
end else begin
trace_rom_tick(__stream_valid, stream_ready, __stream_data, __stream_keep, __stream_last);
__stream_valid_reg <= __stream_valid;
__stream_data_reg <= __stream_data;
__stream_keep_reg <= __stream_keep;
__stream_last_reg <= __stream_last;
end
end
endmodule
| 6.546507 |
module trace_reg #(
parameter p_width = 6
) (
input [p_width - 1:0] i_tr,
input i_clk,
input i_rst_n,
output [p_width - 1:0] o_tr
);
reg [p_width - 1:0] r_tr;
assign o_tr = r_tr;
always @(posedge i_clk or negedge i_rst_n) begin
if (!i_rst_n) r_tr <= {p_width{1'b0}};
else r_tr <= i_tr;
end
endmodule
| 7.778591 |
module sim (
input clk,
input rst_n,
output reg [31:0] pc,
output reg pc_valid
);
initial begin
pc <= 0;
pc_valid <= 0;
end
always @(posedge clk) begin
if (rst_n) begin
pc <= pc + 4;
pc_valid <= 1;
end
end
endmodule
| 6.626082 |
module tracking (
input clk,
input rst_n,
input t_en,
input i_en,
input [10:0] c_min_i,
input [10:0] c_max_i,
input [10:0] r_min_i,
input [10:0] r_max_i,
input cmd_full,
input data_empty,
input [10:0] h_i,
input [10:0] w_i,
input [7:0] h_value,
output data_rd,
output cmd_wr,
output [32:0] cam_addr,
output [10:0] c_min_o,
output [10:0] r_min_o,
output [10:0] c_max_o,
output [10:0] r_max_o,
output t_done,
output [1:0] frame_addr,
input [1:0] wr_frame_addr,
output frame_false
);
wire [10:0] c_min_t;
wire [10:0] r_min_t;
wire [10:0] c_max_t;
wire [10:0] r_max_t;
wire [10:0] cam_x;
wire [10:0] cam_y;
wire [21:0] cam_s;
wire cam_done;
wire cam_en;
wire [10:0] c_max;
wire [10:0] c_min;
wire [10:0] r_max;
wire [10:0] r_min;
// reg [6:0] t_en_cnt;
// reg [6:0] t_done_cnt;
//zclin 2016.12.30
// always@(posedge clk or negedge rst_n)
// begin
// if(!rst_n)
// t_en_cnt <= 0;
// else if(t_en)
// t_en_cnt <= t_en_cnt + 1'd1;
// else
// t_en_cnt <= t_en_cnt;
// end
// always@(posedge clk or negedge rst_n)
// begin
// if(!rst_n)
// t_done_cnt <= 0;
// else if(t_done)
// t_done_cnt <= t_done_cnt + 1'd1;
// else
// t_done_cnt <= t_done_cnt;
// end
//
kalman calc_kalman (
.clk(clk),
.rst_n(rst_n),
.i_en(i_en),
.t_en(t_en),
.h_i(h_i),
.w_i(w_i),
.r_min_i(r_min_i),
.r_max_i(r_max_i),
.c_min_i(c_min_i),
.c_max_i(c_max_i),
.cam_c_min_i(c_min),
.cam_r_min_i(r_min),
.cam_c_max_i(c_max),
.cam_r_max_i(r_max),
.cam_x_i(cam_x),
.cam_y_i(cam_y),
.cam_s(cam_s),
.cam_done(cam_done),
.cam_en(cam_en),
.c_min_o(c_min_o),
.c_max_o(c_max_o),
.r_min_o(r_min_o),
.r_max_o(r_max_o),
.cam_c_max_o(c_max_t),
.cam_c_min_o(c_min_t),
.cam_r_max_o(r_max_t),
.cam_r_min_o(r_min_t),
.t_done(t_done),
.frame_addr(frame_addr),
.wr_frame_addr(wr_frame_addr),
.frame_false(frame_false)
);
camshift calc_camshift (
.clk(clk),
.rst_n(rst_n),
.cam_en(cam_en),
.c_min_i(c_min_t),
.c_max_i(c_max_t),
.r_min_i(r_min_t),
.r_max_i(r_max_t),
.h_i(h_i),
.w_i(w_i),
.h_value(h_value),
.fifo_e(data_empty),
.fifo_f(cmd_full),
.addr_length(cam_addr),
.cam_x_o(cam_x),
.cam_y_o(cam_y),
.c_max_o(c_max),
.c_min_o(c_min),
.r_max_o(r_max),
.r_min_o(r_min),
.cam_s(cam_s),
.cam_done(cam_done),
.data_rd(data_rd),
.cmd_wr(cmd_wr)
);
endmodule
| 7.251841 |
module tracking_iq_fifo (
input clock,
input [(WIDTH-1):0] data,
input rdreq,
input sclr,
input wrreq,
output wire empty,
output wire [(WIDTH-1):0] q
);
parameter WIDTH = 108;
parameter DEPTH = 4;
scfifo scfifo_component (
.rdreq(rdreq),
.sclr(sclr),
.clock(clock),
.wrreq(wrreq),
.data(data),
.empty(empty),
.q(q)
// synopsys translate_off
, .aclr(),
.almost_empty(),
.almost_full(),
.full(),
.usedw()
// synopsys translate_on
);
defparam scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", scfifo_component.lpm_numwords = DEPTH,
scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = WIDTH, scfifo_component.lpm_widthu = 2,
scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
| 6.571644 |
module tracking_loop_ram (
input clock,
input [(ADDR_WIDTH-1):0] address_a,
input [(ADDR_WIDTH-1):0] address_b,
input [(DATA_WIDTH-1):0] data_a,
input [(DATA_WIDTH-1):0] data_b,
input wren_a,
input wren_b,
output wire [(DATA_WIDTH-1):0] q_a,
output wire [(DATA_WIDTH-1):0] q_b);
parameter DEPTH;
parameter ADDR_WIDTH;
parameter DATA_WIDTH;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
altsyncram altsyncram_component(.wren_a (wren_a),
.clock0 (clock),
.wren_b (wren_b),
.address_a (address_a),
.address_b (address_b),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = DEPTH,
altsyncram_component.numwords_b = DEPTH,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
| 6.574553 |
module TrackManager (
input iFpgaClock,
iFpgaReset
, input [7:0] iPianoCommand
, output reg [5:0] track0
, output reg [5:0] track1
, output reg [5:0] track2
, output reg [5:0] track3
);
always @(posedge iFpgaClock or posedge iFpgaReset) begin
if (iFpgaReset) begin
track0 <= 0;
track1 <= 0;
track2 <= 0;
track3 <= 0;
end else
case (iPianoCommand[7:6])
0: track0 <= iPianoCommand[5:0];
1: track1 <= iPianoCommand[5:0];
2: track2 <= iPianoCommand[5:0];
3: track3 <= iPianoCommand[5:0];
endcase
end
endmodule
| 6.684485 |
module TrackMarkDetector (
clock,
cke,
reset,
index,
threshold,
detect
);
input clock; // clock input, positive-edge-triggered
input cke; // clock enable, positive-true
input reset; // reset input, positive-edge-triggered
input index; // index pulse input, active high
input [7:0] threshold; // threshold value
output detect; // detection state output
/////////////////////////////////////////////////////////////////////////////
// Time counter and latch
// Synchronise index with clock
reg [2:0] INDEX_SYNC_r;
always @(posedge clock) INDEX_SYNC_r <= {INDEX_SYNC_r[0], index};
// Detect rising edge of index pulse
wire INDEX_RISING_EDGE = !INDEX_SYNC_r[1] && INDEX_SYNC_r[0];
// Measure time between last index pulse and this one
reg [7:0] timer;
reg [7:0] tlatch;
always @(posedge clock) begin
if (INDEX_RISING_EDGE) begin
// Index pulse -- save current frequency count and clear counter
tlatch <= timer;
timer <= 8'd0;
end else begin
if (cke) begin
// Clocked with enable active. Increment index frequency count.
timer <= timer + 8'd1;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Track last few output states -- must see delta>threshold, THEN
// delta<=threshold twice in order to trigger. To do this, we track the
// previous and current index pulse states.
reg [2:0] prevstate;
always @(posedge index) begin
prevstate <= {prevstate[1:0], (tlatch <= threshold)};
end
/////////////////////////////////////////////////////////////////////////////
// Detect logic --
// First delta: longer than threshold
// Second and third deltas: shorter than threshold
//
// In a sense, we're after:
// _ _ _ _
// ______/ \________/ \____/ \____/ \_____
// sector: n-1 n n.5 1
// ^^^ INDEX HERE
//
assign detect = (!prevstate[2] && prevstate[1] && prevstate[0]);
endmodule
| 7.21522 |
module Traductor (
in,
out,
clk,
rst
);
input wire clk, rst;
input wire [2:0] in;
output reg [6:0] out;
always @(posedge clk, posedge rst)
if (rst) begin
out <= 7'd0;
end else
case (in)
4'b0000: out <= 7'd104; //30k
4'b0001: out <= 7'd62; //50k
4'b0010: out <= 7'd41; //75k
4'b0011: out <= 7'd31; //100k
4'b0100: out <= 7'd25; //125k
4'b0101: out <= 7'd21; //150k
4'b0110: out <= 7'd18; //175k
4'b0111: out <= 7'd15; //200k
default out <= 7'd0;
endcase
endmodule
| 7.101518 |
module traducto_addr_rtc_addr_mem_local (
input reset,
input [7:0] addr_rtc,
output reg [3:0] addr_mem_local
);
always @* begin
if (reset) addr_mem_local = 4'b1111;
else begin
case (addr_rtc)
8'h21: addr_mem_local = 4'b0000;
8'h22: addr_mem_local = 4'b0001;
8'h23: addr_mem_local = 4'b0010;
8'h24: addr_mem_local = 4'b0011;
8'h25: addr_mem_local = 4'b0100;
8'h26: addr_mem_local = 4'b0101;
8'h27: addr_mem_local = 4'b0110;
8'h41: addr_mem_local = 4'b0111;
8'h42: addr_mem_local = 4'b1000;
8'h43: addr_mem_local = 4'b1001;
default: addr_mem_local = 4'b1111;
endcase
end
end
endmodule
| 8.237331 |
module traf3 (
input wire clk,
input wire clr,
output reg [5:0] lights
);
reg [ 2:0] state;
reg [24:0] count = 26'd11111111;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, // states
S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
parameter SEC5 = 26'd33333333, SEC1 = 26'd22222222; // delays
always @(posedge clk) begin
if (clr == 1) begin
state <= S0;
count <= 0;
end else
case (state)
S0:
if (count < SEC5) begin
state <= S0;
count <= count + 1;
end else begin
state <= S1;
count <= 0;
end
S1:
if (count < SEC1) begin
state <= S1;
count <= count + 1;
end else begin
state <= S2;
count <= 0;
end
S2:
if (count < SEC1) begin
state <= S2;
count <= count + 1;
end else begin
state <= S3;
count <= 0;
end
S3:
if (count < SEC5) begin
state <= S3;
count <= count + 1;
end else begin
state <= S4;
count <= 0;
end
S4:
if (count < SEC1) begin
state <= S4;
count <= count + 1;
end else begin
state <= S5;
count <= 0;
end
S5:
if (count < SEC1) begin
state <= S5;
count <= count + 1;
end else begin
state <= S0;
count <= 0;
end
default state <= S0;
endcase
end
always @(*) begin
case (state)
S0: lights = 6'b100001;
S1: lights = 6'b100010;
S2: lights = 6'b100100;
S3: lights = 6'b001100;
S4: lights = 6'b010100;
S5: lights = 6'b100100;
default lights = 6'b100001;
endcase
end
endmodule
| 6.855346 |
module nBitCounter (
count,
clk,
rst_n,
stop_v,
max_num
);
parameter n = 7;
output reg [n:0] count;
input clk;
input rst_n;
input stop_v;
input [n:0] max_num;
// Set the initial value
initial count = 90;
// Increment count on clock
always @(posedge clk or negedge rst_n)
if (!rst_n) count = max_num;
else if (!(count[0] || count[1] || count[2] || count[3] || count[4] || count[5] || count[6] || count[7]))
#20 count = max_num;
else if (!stop_v) count = count - 1;
endmodule
| 6.668753 |
module nBitCounter_1 (
count,
clk,
rst_n,
stop_v,
max_num
);
parameter n = 7;
output reg [n:0] count;
input clk;
input rst_n;
input stop_v;
input [n:0] max_num;
// Set the initial value
initial count = 90;
// Increment count on clock
always @(posedge clk or negedge rst_n)
if (!rst_n) count = max_num;
else if (!stop_v && (count[0] || count[1] || count[2] || count[3] || count[4] || count[5] || count[6] || count[7]))
count = count - 1;
endmodule
| 6.512867 |
module get the 8-bits input and makes hundreds, tens, ones from the input
module binaryToBCD(number, hundreds, tens, ones);
// I/O Signal Definitions
input [7:0] number;
output reg [3:0] hundreds;
output reg [3:0] tens;
output reg [3:0] ones;
// Internal variable for storing bits
reg [19:0] shift;
integer i;
always @(number)
begin
// Clear previous number and store new number in shift register
shift[19:8] = 0;
shift[7:0] = number;
// Loop eight times
for (i=0; i<8; i=i+1) begin
if (shift[11:8] >= 5)
shift[11:8] = shift[11:8] + 3;
if (shift[15:12] >= 5)
shift[15:12] = shift[15:12] + 3;
if (shift[19:16] >= 5)
shift[19:16] = shift[19:16] + 3;
// Shift entire register left once
shift = shift << 1;
end
// Push decimal numbers to output
hundreds = shift[19:16];
tens = shift[15:12];
ones = shift[11:8];
end
endmodule
| 6.529157 |
module the core of program that get the inputs and predict nextStates from the input ...
// ... and presentStates and determine the output of machine
module stateMachine (R, A, B, CLK, RST, Counter,CounterValue, A_TIME_L, A_TIME_H, B_TIME_L, B_TIME_H, A_LIGHT, B_LIGHT, TEMP);
input R, A, B, CLK, RST, Counter;
input[7:0] CounterValue;
output [3:0] A_TIME_L;
output [3:0] A_TIME_H;
output [3:0] B_TIME_L;
output [3:0] B_TIME_H;
output A_LIGHT , B_LIGHT;
wire [3:0] A_TIME_L;
wire [3:0] A_TIME_H;
wire [3:0] B_TIME_L;
wire [3:0] B_TIME_H;
reg A_LIGHT , B_LIGHT;
reg [3:0] presentState, nextState;
output[3:0] TEMP;
wire[3:0] TEMP;
// parameter reggggg = CounterValue;
parameter S0 = 3'b000 , S1 = 3'b001 , S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
// assign Counter = reggggg;
always @ (posedge CLK or posedge RST)
if (RST) presentState = S0;
else presentState = nextState;
always @ (presentState or Counter or R)
begin
if(R) nextState = S0;
if(~R && A && ~B) nextState = S2;
if(~R && ~A && B) nextState = S3;
case (presentState)
S0:
begin
if (~R && ~A && ~B && ~Counter)
nextState = S0;
else if (~R && ~A && ~B && Counter)
nextState = S5;
end
S1:
begin
if (~R && ~A && ~B && ~Counter)
nextState = S1;
else if (~R && ~A && ~B && Counter)
nextState = S4;
end
S2:
begin
if (~R && ~A && ~B)
nextState = S2;
end
S3:
begin
if (~R && ~A && ~B)
nextState = S3;
end
S4:
begin
if (~R && ~A && ~B && ~Counter)
nextState = S4;
else if (~R && ~A && ~B && Counter)
nextState = S0;
end
S5:
begin
if (~R && ~A && ~B && ~Counter)
nextState = S5;
else if (~R && ~A && ~B && Counter)
nextState = S1;
end
endcase
end
binaryToBCD bbcd1 (CounterValue, TEMP, A_TIME_L, A_TIME_H);
binaryToBCD bbcd2 (CounterValue, TEMP, B_TIME_L, B_TIME_H);
always @ (presentState or Counter)
begin
case(presentState)
S0:
begin
A_LIGHT <= 1;
B_LIGHT <= 0;
end
S1:
begin
A_LIGHT <= 0;
B_LIGHT <= 1;
end
S2:
begin
A_LIGHT <= 1;
B_LIGHT <= 0;
end
S3:
begin
A_LIGHT <= 0;
B_LIGHT <= 1;
end
S4:
begin
A_LIGHT <= 0;
B_LIGHT <= 0;
end
S5:
begin
A_LIGHT <= 0;
B_LIGHT <= 0;
end
endcase
end
endmodule
| 6.506388 |
module: TrafficControllerMain
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
// Run this module for at least 0.004ms
module TrafficControllerMain_test;
// Inputs
reg Reset;
reg Sensor;
reg Walk_Request;
reg Reprogram;
reg [1:0] Time_Parameter_Selector;
reg [3:0] Time_Value;
reg clk;
// Outputs
wire [6:0] LEDs;
/*wire start_timer; //for visual purposes only
wire Reset_Sync;
wire expired;
wire oneHz_enable;
wire [3:0] value;
wire [1:0] interval;*/
// Instantiate the Unit Under Test (UUT)
TrafficControllerMain uut (
.Reset(Reset),
.Sensor(Sensor),
.Walk_Request(Walk_Request),
.Reprogram(Reprogram),
.Time_Parameter_Selector(Time_Parameter_Selector),
.Time_Value(Time_Value),
.clk(clk),
.LEDs(LEDs)/*, //Visual pourpose only
.start_timer(start_timer),
.Reset_Sync(Reset_Sync),
.expired(expired),
.oneHz_enable(oneHz_enable),
.value(value),
.interval(interval)*/
);
initial begin
// Initialize Inputs
Reset = 0;
Sensor = 0;
Walk_Request = 0;
Reprogram = 0;
Time_Parameter_Selector = 0;
Time_Value = 0;
clk = 0;
#20
// Wait 100 ns for global reset to finish
#5
Reset = 1;
#5
Reset = 0;
//#100
//walk request
//Walk_Request = 1;
//#20
//Walk_Request = 0;
// Vehicle sensor request
//Sensor = 1;
// Add stimulus here
end
initial begin
forever begin
#5 clk = ~clk;
end
end
endmodule
| 7.078693 |
module testbench;
reg ar, ag, ay, br, bg, by;
wire a_move, b_move;
traffic_four t (
ar,
ag,
ay,
br,
bg,
by,
a_move,
b_move
);
initial begin
$dumpfile("vcd/TrafficLightsTwo.vcd");
$dumpvars(0, testbench);
$display("ar\tag\tay\t\tbr\tbg\tby\t\ta_move\tb_move");
$monitor("%b\t%b\t%b\t\t%b\t%b\t%b\t\t%b\t%b\t", ar, ag, ay, br, bg, by, a_move, b_move);
ag = 0;
ar = 1;
ay = 0;
bg = 1;
br = 0;
by = 0;
#30 ag = 0;
ar = 1;
ay = 0;
bg = 0;
br = 0;
by = 1;
#15 ag = 1;
ar = 0;
ay = 0;
bg = 0;
br = 1;
by = 0;
#30 ag = 0;
ar = 0;
ay = 1;
bg = 0;
br = 1;
by = 0;
#15 $finish;
end
endmodule
| 7.015571 |
module Mux2x1 (
out,
in1,
in2,
s
);
output reg [1:0] out;
input [1:0] in1, in2;
input s;
always @(in1, in2, s) begin
if (s == 0) out = in1;
else if (s == 1) out = in2;
else out = 2'bxx;
end
endmodule
| 6.963017 |
module Xor (
out,
a,
b
);
output out;
input a, b;
wire x, y, z;
nand (x, a, b);
nand (y, a, x);
nand (z, b, x);
nand (out, y, z);
endmodule
| 7.144897 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/traffic_cl_comb/traffic_cl_comb.opt (
a_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad
);
input a_pad, b_pad, c_pad, d_pad, e_pad;
output f_pad;
wire new_n9_, new_n10_;
assign f_pad = d_pad | ((new_n9_ | (new_n10_ & c_pad)) & (new_n10_ | c_pad));
assign new_n9_ = a_pad & b_pad;
assign new_n10_ = e_pad & (b_pad | a_pad);
endmodule
| 6.939825 |
module trattic_control (
Clk,
Reset,
Done_NS,
Done_EW,
Red1,
Yellow1,
Green1,
Red2,
Yellow2,
Green2,
Sload_NS,
Sload_EW,
State_cnt
);
input Clk, Reset;
input Done_NS, Done_EW;
output Red1, Yellow1, Green1, Red2, Yellow2, Green2;
output Sload_NS, Sload_EW;
output [3:0] State_cnt;
//Define the states
parameter S0 = 4'b0001, S1 = 4'b0010, S2 = 4'b0100, S3 = 4'b1000;
reg [3:0] current_state, next_state;
reg Red1, Yellow1, Green1, Red2, Yellow2, Green2;
reg Sload_NS, Sload_EW;
assign State_cnt = current_state;
//state update
always @(posedge Clk or posedge Reset) begin
if (Reset) current_state <= S0;
else current_state <= next_state;
end
//Calculate the next state and the outputs
always @(current_state or Done_NS or Done_EW) begin : fsmtr
case (current_state)
S0: begin
if (Done_NS) next_state <= S1;
else next_state <= S0;
end
S1: begin
if (Done_NS) next_state <= S2;
else next_state <= S1;
end
S2: begin
if (Done_EW) next_state <= S3;
else next_state <= S2;
end
S3: begin
if (Done_EW) next_state <= S0;
else next_state <= S3;
end
default: next_state <= S0;
endcase
end
always @(*) begin
Sload_NS <= 1'b0;
Sload_EW <= 1'b0;
case (current_state)
S0: begin
Green1 <= 1'b1;
Yellow1 <= 1'b0;
Red1 <= 1'b0;
Green2 <= 1'b0;
Yellow2 <= 1'b0;
Red2 <= 1'b1;
if (Done_NS) begin
Sload_NS <= 1'b1;
end
end
S1: begin
Green1 <= 1'b0;
Yellow1 <= 1'b1;
Red1 <= 1'b0;
Green2 <= 1'b0;
Yellow2 <= 1'b0;
Red2 <= 1'b1;
if (Done_NS) begin
Sload_NS <= 1'b1;
Sload_EW <= 1'b1;
end
end
S2: begin
Green1 <= 1'b0;
Yellow1 <= 1'b0;
Red1 <= 1'b1;
Green2 <= 1'b1;
Yellow2 <= 1'b0;
Red2 <= 1'b0;
if (Done_NS) begin
Sload_EW <= 1'b1;
end
end
S3: begin
Green1 <= 1'b0;
Yellow1 <= 1'b0;
Red1 <= 1'b1;
Green2 <= 1'b0;
Yellow2 <= 1'b1;
Red2 <= 1'b0;
if (Done_NS) begin
Sload_NS <= 1'b1;
Sload_EW <= 1'b1;
end
end
default: begin
Green1 <= 1'b1;
Yellow1 <= 1'b0;
Red1 <= 1'b0;
Green2 <= 1'b0;
Yellow2 <= 1'b0;
Red2 <= 1'b1;
Sload_NS <= 1'b1;
Sload_EW <= 1'b1;
end
endcase
end
endmodule
| 6.777755 |
module divider (
clk100Mhz,
slowClk
);
input clk100Mhz; //fast clock
output slowClk; //slow clock
reg [27:0] counter;
// switch to 27 for visible division
assign slowClk = counter[24]; //(2^27 / 100E6) = 1.34seconds
initial begin
counter <= 0;
end
always @(posedge clk100Mhz) begin
counter <= counter + 1; //increment the counter every 10ns (1/100 Mhz) cycle.
end
endmodule
| 7.389371 |
module top (
RST,
lighta,
lightb,
lightw,
clk100Mhz
);
input RST, clk100Mhz;
output lighta, lightb, lightw;
wire slowClk;
wire [2:0] lighta, lightb;
wire [1:0] lightw;
divider divide (
clk100Mhz,
slowClk
);
traffic_controller traffic (
RST,
slowClk,
lighta,
lightb,
lightw
);
endmodule
| 6.735964 |
module nsCounter (
input clk,
output [4:0] count
);
wire clk;
reg [4:0] count;
initial count = 0;
always @(negedge clk) count[0] <= ~count[0];
always @(negedge count[0]) count[1] <= ~count[1];
always @(negedge count[1]) count[2] <= ~count[2];
always @(negedge count[2]) count[3] <= ~count[3];
always @(negedge count[3]) count[4] <= ~count[4];
endmodule
| 6.866158 |
module ewCounter (
input clk,
output [3:0] count
);
wire clk;
reg [3:0] count;
initial count = 0;
always @(negedge clk) count[0] <= ~count[0];
always @(negedge count[0]) count[1] <= ~count[1];
always @(negedge count[1]) count[2] <= ~count[2];
always @(negedge count[2]) count[3] <= ~count[3];
endmodule
| 6.917313 |
module injection_ratio_ctrl #(
parameter MAX_PCK_SIZ = 10,
parameter MAX_RATIO = 100
) (
en,
pck_size, // average packet size in flit
clk,
reset,
inject, // inject one packet
freez,
ratio // 0~100 flit injection ratio
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
localparam PCK_SIZw = log2(MAX_PCK_SIZ);
localparam CNTw = log2(MAX_RATIO);
localparam STATE_INIT = MAX_PCK_SIZ * MAX_RATIO;
localparam STATEw = log2(MAX_PCK_SIZ * 2 * MAX_RATIO);
input clk, reset, freez, en;
output reg inject;
input [CNTw-1 : 0] ratio;
input [PCK_SIZw-1 : 0] pck_size;
wire [CNTw-1 : 0] on_clks, off_clks;
reg [STATEw-1 : 0] state, next_state;
wire input_changed;
reg [CNTw-1 : 0] ratio_old;
always @(posedge clk) ratio_old <= ratio;
assign input_changed = (ratio_old != ratio);
assign on_clks = ratio;
assign off_clks = MAX_RATIO - ratio;
reg [PCK_SIZw-1 : 0] flit_counter, next_flit_counter;
reg sent, next_sent, next_inject;
always @(*) begin
next_state = state;
next_flit_counter = flit_counter;
next_sent = sent;
if (en && ~freez) begin
case (sent)
1'b1: begin
/* verilator lint_off WIDTH */
next_state = state + off_clks;
/* verilator lint_on WIDTH */
next_flit_counter = (flit_counter >= pck_size-1'b1) ? {PCK_SIZw{1'b0}} : flit_counter +1'b1;
next_inject = (flit_counter == {PCK_SIZw{1'b0}});
if (next_flit_counter >= pck_size - 1'b1) begin
if (next_state >= STATE_INIT) next_sent = 1'b0;
end
end
1'b0: begin
if (next_state < STATE_INIT) next_sent = 1'b1;
next_inject = 1'b0;
/* verilator lint_off WIDTH */
next_state = state - on_clks;
/* verilator lint_on WIDTH */
end
endcase
end else begin
next_inject = 1'b0;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= STATE_INIT;
inject <= 1'b0;
sent <= 1'b1;
flit_counter <= 0;
end else begin
if (input_changed) begin
state <= STATE_INIT;
inject <= 1'b0;
sent <= 1'b1;
flit_counter <= 0;
end
state <= next_state;
if (ratio != {CNTw{1'b0}}) inject <= next_inject;
sent <= next_sent;
flit_counter <= next_flit_counter;
end
end
endmodule
| 7.08373 |
module packet_gen #(
parameter P = 5,
parameter T1 = 4,
parameter T2 = 4,
parameter T3 = 4,
parameter RAw = 3,
parameter EAw = 3,
parameter TOPOLOGY = "MESH",
parameter DSTPw = 4,
parameter ROUTE_NAME = "XY",
parameter ROUTE_TYPE = "DETERMINISTIC",
parameter MAX_PCK_NUM = 10000,
parameter MAX_SIM_CLKs = 100000,
parameter TIMSTMP_FIFO_NUM = 16,
parameter MIN_PCK_SIZE = 2
) (
clk_counter,
pck_wr,
pck_rd,
current_r_addr,
pck_number,
dest_e_addr,
pck_timestamp,
destport,
buffer_full,
pck_ready,
valid_dst,
clk,
reset
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
localparam PCK_CNTw = log2(MAX_PCK_NUM + 1), CLK_CNTw = log2(MAX_SIM_CLKs + 1);
input reset, clk, pck_wr, pck_rd;
input [RAw-1 : 0] current_r_addr;
input [CLK_CNTw-1 : 0] clk_counter;
output [PCK_CNTw-1 : 0] pck_number;
input [EAw-1 : 0] dest_e_addr;
output [CLK_CNTw-1 : 0] pck_timestamp;
output buffer_full, pck_ready;
input valid_dst;
output [DSTPw-1 : 0] destport;
reg [PCK_CNTw-1 :0] packet_counter;
wire buffer_empty;
assign pck_ready = ~buffer_empty & valid_dst;
ni_conventional_routing #(
.TOPOLOGY(TOPOLOGY),
.ROUTE_NAME(ROUTE_NAME),
.ROUTE_TYPE(ROUTE_TYPE),
.T1(T1),
.T2(T2),
.T3(T3),
.RAw(RAw),
.EAw(EAw),
.DSTPw(DSTPw)
) the_ni_conventional_routing (
.reset(reset),
.clk(clk),
.current_r_addr(current_r_addr),
.dest_e_addr(dest_e_addr),
.destport(destport)
);
wire timestamp_fifo_nearly_full, timestamp_fifo_full;
assign buffer_full = (MIN_PCK_SIZE == 1) ? timestamp_fifo_nearly_full : timestamp_fifo_full;
wire recieve_more_than_0;
fwft_fifo #(
.DATA_WIDTH(CLK_CNTw),
.MAX_DEPTH (TIMSTMP_FIFO_NUM)
) timestamp_fifo (
.din(clk_counter),
.wr_en(pck_wr),
.rd_en(pck_rd),
.dout(pck_timestamp),
.full(timestamp_fifo_full),
.nearly_full(timestamp_fifo_nearly_full),
.recieve_more_than_0(recieve_more_than_0),
.recieve_more_than_1(),
.reset(reset),
.clk(clk)
);
assign buffer_empty = ~recieve_more_than_0;
/*
fifo #(
.Dw(CLK_CNTw),
.B(TIMSTMP_FIFO_NUM)
)
timestamp_fifo
(
.din(clk_counter),
.wr_en(pck_wr),
.rd_en(pck_rd),
.dout(pck_timestamp),
.full(timestamp_fifo_full),
.nearly_full(timestamp_fifo_nearly_full),
.empty(buffer_empty),
.reset(reset),
.clk(clk)
);
*/
always @(posedge clk or posedge reset) begin
if (reset) begin
packet_counter <= {PCK_CNTw{1'b0}};
end else begin
if (pck_rd) begin
packet_counter <= packet_counter + 1'b1;
end
end
end
assign pck_number = packet_counter;
endmodule
| 8.086403 |
module distance_gen #(
parameter TOPOLOGY = "MESH",
parameter T1 = 4,
parameter T2 = 4,
parameter T3 = 4,
parameter EAw = 2,
parameter DISTw = 4
) (
src_e_addr,
dest_e_addr,
distance
);
input [EAw-1 : 0] src_e_addr;
input [EAw-1 : 0] dest_e_addr;
output [DISTw-1 : 0] distance;
generate
/* verilator lint_off WIDTH */
if (TOPOLOGY == "MESH" || TOPOLOGY == "TORUS" || TOPOLOGY == "RING" || TOPOLOGY == "LINE")begin : tori_noc
/* verilator lint_on WIDTH */
mesh_torus_distance_gen #(
.T1(T1),
.T2(T2),
.T3(T3),
.TOPOLOGY(TOPOLOGY),
.DISTw(DISTw),
.EAw(EAw)
) distance_gen (
.src_e_addr(src_e_addr),
.dest_e_addr(dest_e_addr),
.distance(distance)
);
/* verilator lint_off WIDTH */
end else if (TOPOLOGY == "FATTREE" || TOPOLOGY == "TREE") begin : fat
/* verilator lint_on WIDTH */
fattree_distance_gen #(
.K(T1),
.L(T2)
) distance_gen (
.src_addr_encoded(src_e_addr),
.dest_addr_encoded(dest_e_addr),
.distance(distance)
);
end
endgenerate
endmodule
| 7.138576 |
module traffic_generator (
clk,
reset,
i__config,
i__generate_phase,
i__phase_count,
i__pifo_ready,
o__packet_flow_id,
o__packet_priority,
o__valid_packet_generated,
o__num_pkts_sent
);
`include "common_tb_headers.vh"
//------------------------------------------------------------------------------
// Interface signals
//------------------------------------------------------------------------------
input logic clk;
input logic reset;
input TGConfig i__config;
input logic i__generate_phase;
input CounterSignal i__phase_count;
input logic i__pifo_ready;
output FlowId o__packet_flow_id;
output Priority o__packet_priority;
output logic o__valid_packet_generated;
output CounterSignal o__num_pkts_sent;
//------------------------------------------------------------------------------
// Internal signals
//------------------------------------------------------------------------------
TGConfig w__config;
InjectionRate w__lfsr_injrate;
FlowId w__packet_flow_id;
Priority w__packet_priority;
logic w__generate_packet;
CounterSignal r__num_pkts_sent__pff;
logic r__initial__pff;
//------------------------------------------------------------------------------
// Output signal assignments
//------------------------------------------------------------------------------
assign o__packet_flow_id = w__packet_flow_id % NUM_FLOWS;
assign o__packet_priority = w__packet_priority;
assign o__valid_packet_generated = w__generate_packet;
assign o__num_pkts_sent = r__num_pkts_sent__pff;
//------------------------------------------------------------------------------
// Sub-modules
//------------------------------------------------------------------------------
linear_feedback_shift_register #(
.NUM_BITS($bits(InjectionRate))
) lfsr_injrate (
.clk (clk),
.reset (reset),
.i__seed (w__config.injrate_seed),
.i__next (i__generate_phase),
.o__value(w__lfsr_injrate)
);
linear_feedback_shift_register #(
.NUM_BITS($bits(Priority))
) lfsr_prio (
.clk (clk),
.reset (reset),
.i__seed (w__config.priority_seed),
.i__next (w__generate_packet),
.o__value(w__packet_priority)
);
linear_feedback_shift_register #(
.NUM_BITS($bits(FlowId))
) lfsr_pkt_pointer (
.clk (clk),
.reset (reset),
.i__seed (w__config.flow_id_seed),
.i__next (w__generate_packet),
.o__value(w__packet_flow_id)
);
//------------------------------------------------------------------------------
// Combinational logic
//------------------------------------------------------------------------------
assign w__config = i__config;
assign w__generate_packet = i__generate_phase && i__pifo_ready && (r__num_pkts_sent__pff < w__config.total_packets)
&& (w__lfsr_injrate < w__config.injrate) && r__initial__pff;
//------------------------------------------------------------------------------
// Sequential logic
//------------------------------------------------------------------------------
always_ff @(posedge clk) begin
if (reset) begin
r__num_pkts_sent__pff <= '0;
r__initial__pff <= 1'b0;
end else begin
r__num_pkts_sent__pff <= w__generate_packet ? (r__num_pkts_sent__pff + 1'b1) : r__num_pkts_sent__pff;
r__initial__pff <= 1'b1;
end
end
endmodule
| 6.512301 |
module traffic_led(
input sys_clk , //系统时钟信号
input sys_rst_n , //系统复位信号
input [3:0] key ,
output [7:0] bit , //数码管位选信号
output [7:0] segment , //数码管段选信号
output [23:0] led //LED使能信号
);
//wire define
wire [9:0] n_time; //北方向状态剩余时间数据
wire [9:0] e_time; //东方向状态剩余时间数据
wire [9:0] s_time; //南方向状态剩余时间数据
wire [9:0] w_time; //西方向状态剩余时间数据
wire [9:0] nl_time; //北方向状态剩余时间数据
wire [9:0] el_time; //东方向状态剩余时间数据
wire [9:0] sl_time; //南方向状态剩余时间数据
wire [9:0] wl_time; //西方向状态剩余时间数据
wire [3:0] state ; //交通灯的状态，用于控制LED灯的点亮
state_trans_model u0_state_trans_model(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.n_time (n_time),
.e_time (e_time),
.s_time (s_time),
.w_time (w_time),
.nl_time (nl_time),
.el_time (el_time),
.sl_time (sl_time),
.wl_time (wl_time),
.state (state)
);
//数码管显示模块
bit_seg_module u1_bit_seg_module(
.sys_clk (sys_clk) ,
.sys_rst_n (sys_rst_n),
.n_time (n_time),
.e_time (e_time),
.s_time (s_time),
.w_time (w_time),
.en (1'b1),
.bit (bit),
.segment (segment)
);
//led灯控制模块
led_module u2_led_module(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n),
.state (state ),
.led (led ),
.key (key )
);
endmodule
| 7.407 |
module sevensegment (
clk,
in,
out
);
input clk;
input [2:0] in;
output reg [7:0] out;
always @(posedge clk) begin
case (in)
0: out <= 8'b00000011;
1: out = 8'b10011111;
2: out = 8'b00100101;
3: out = 8'b00001101;
4: out = 8'b10011001;
5: out = 8'b01001001;
6: out = 8'b01000001;
7: out = 8'b00011111;
default: out = 8'b00000011;
endcase
end
endmodule
| 7.484815 |
module Display_fd (
clk_in,
reset,
clk_out
);
input clk_in, reset;
output reg clk_out;
reg [31:0] count;
always @(posedge clk_in) begin
if (!reset) begin
count <= 32'd0;
clk_out <= 1'b0;
end else begin
if (count == `DisplayTime) begin
count <= 0;
clk_out <= ~clk_out;
end else begin
count = count + 1;
end
end
end
endmodule
| 7.522834 |
module Second_fd (
clk_in,
reset,
clk_out
);
input clk_in, reset;
output reg clk_out;
reg [31:0] count;
always @(posedge clk_in) begin
if (!reset) begin
count <= 32'd0;
clk_out <= 1'b0;
end else begin
if (count == `SecondTime) begin
count <= 0;
clk_out <= ~clk_out;
end else begin
count = count + 1;
end
end
end
endmodule
| 6.88559 |
module
//
//////////////////////////////////////////////////////////////////////////////////
module traffic_light_top(
output wire red_light_nrth_s10th_st,
output wire ylw_light_nrth_s10th_st,
output wire grn_light_nrth_s10th_st,
output wire red_light_west_s10th_st,
output wire ylw_light_west_s10th_st,
output wire grn_light_west_s10th_st,
output wire red_light_nrth_s11th_st,
output wire ylw_light_nrth_s11th_st,
output wire grn_light_nrth_s11th_st,
output wire red_light_west_s11th_st,
output wire ylw_light_west_s11th_st,
output wire grn_light_west_s11th_st,
output wire walk_light_nrth_s10th_st,
output wire stop_light_nrth_s10th_st,
output wire walk_light_west_s10th_st,
output wire stop_light_west_s10th_st,
output wire walk_light_nrth_s11th_st,
output wire stop_light_nrth_s11th_st,
output wire walk_light_west_s11th_st,
output wire stop_light_west_s11th_st,
output wire debug_out,// DEBUG
output wire debug_10n_q,// DEBUG
output wire debug_10w_q,// DEBUG
input wire nrth_ped_button,
input wire west_ped_button,
input wire reset_n,
input wire clk_50_mhz
);
wire clk_1_hz;
wire enable_n;
wire reset;
wire nrth_xwalk_sig;
wire west_xwalk_sig;
debounce rst(
.sig_out(reset),
.button_n(reset_n),
.clk_50_mhz(clk_50_mhz)
);
debounce north_button(
.sig_out(nrth_xwalk_sig),
.button_n(nrth_ped_button),
.clk_50_mhz(clk_50_mhz)
);
debounce west_button(
.sig_out(west_xwalk_sig),
.button_n(west_ped_button),
.clk_50_mhz(clk_50_mhz)
);
master_timer timer(
.clk_mstr(clk_1_hz),
.enable_n(enable_n),
.clk_50_mhz(clk_50_mhz)
);
two_way_intersection two_way(
.reda_0(red_light_nrth_s10th_st),
.ylwa_0(ylw_light_nrth_s10th_st),
.grna_0(grn_light_nrth_s10th_st),
.reda_1(red_light_west_s10th_st),
.ylwa_1(ylw_light_west_s10th_st),
.grna_1(grn_light_west_s10th_st),
.redb_0(red_light_nrth_s11th_st),
.ylwb_0(ylw_light_nrth_s11th_st),
.grnb_0(grn_light_nrth_s11th_st),
.redb_1(red_light_west_s11th_st),
.ylwb_1(ylw_light_west_s11th_st),
.grnb_1(grn_light_west_s11th_st),
.walka_0(walk_light_nrth_s10th_st),
.stopa_0(stop_light_nrth_s10th_st),
.walka_1(walk_light_west_s10th_st),
.stopa_1(stop_light_west_s10th_st),
.walkb_0(walk_light_nrth_s11th_st),
.stopb_0(stop_light_nrth_s11th_st),
.walkb_1(walk_light_west_s11th_st),
.stopb_1(stop_light_west_s11th_st),
.debug_10n_q(debug_10n_q),// DEBUG
.debug_10w_q(debug_10w_q),// DEBUG
.crosswalk_0(nrth_xwalk_sig),
.crosswalk_1(west_xwalk_sig),
.reset_n(reset),
.clk(clk_1_hz)
);
assign enable_n = ~reset;
assign debug_out = clk_1_hz;
endmodule
| 6.643738 |
module traffic_signal_controller (
clk,
x,
reset,
hwy,
cntry
);
input clk, reset, x;
parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100;
parameter green = 2'b00, red = 2'b01, yellow = 2'b10;
reg [2:0] state, next_state;
output reg [1:0] hwy, cntry;
initial begin
state = s0;
next_state = s0;
hwy = green;
cntry = red;
end
always @(posedge clk) begin
if (reset) state <= s0;
else state <= next_state;
end
always @(state or x) begin
case (state)
s0: begin
hwy = green;
cntry = red;
next_state = x ? s1 : s0;
end
s1: begin
hwy = yellow;
cntry = red;
next_state = s2;
end
s2: begin
hwy = red;
cntry = red;
next_state = s3;
end
s3: begin
hwy = red;
cntry = green;
next_state = x ? s3 : s4;
end
s4: begin
hwy = red;
cntry = yellow;
next_state = s0;
end
default: begin
next_state = s0;
hwy = green;
cntry = red;
end
endcase
end
endmodule
| 6.677289 |
module tb_traffic_signal_controller;
// Inputs
reg clk;
reg x;
reg reset;
// Outputs
wire [1:0] hwy;
wire [1:0] cntry;
// Instantiate the Unit Under Test (UUT)
traffic_signal_controller uut (
.clk(clk),
.x(x),
.reset(reset),
.hwy(hwy),
.cntry(cntry)
);
always
#5 clk ~= clk;
initial begin
// Initialize Inputs
clk = 0;
x = 0; reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#10; x=0;
#10; x=0;
#10; x=1;
#10; x=0;
#10; x=0;
#10; x=1;
#10; x=1;
#10; reset=1;
end
endmodule
| 6.723729 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules
nsCounter clock1 (
clk,
count1
); // Count a total of 32 seconds
ewCounter clock2 (
clk,
count2
); // Counts a total of 16 seconds
yellowCounter clock3 (
clk,
count3
); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (
count1,
count2,
count3,
NS_VEHICLE_DETECT,
EW_VEHICLE_DETECT,
NS_RED,
NS_YELLOW,
NS_GREEN,
EW_RED,
EW_YELLOW,
EW_GREEN
);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 0;
$display(" NS | EW ");
$display("R Y G R Y G ");
$monitor("%h %h %h %h %h %h", NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
endmodule
| 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules
nsCounter clock1 (
clk,
count1
); // Count a total of 32 seconds
ewCounter clock2 (
clk,
count2
); // Counts a total of 16 seconds
yellowCounter clock3 (
clk,
count3
); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (
count1,
count2,
count3,
NS_VEHICLE_DETECT,
EW_VEHICLE_DETECT,
NS_RED,
NS_YELLOW,
NS_GREEN,
EW_RED,
EW_YELLOW,
EW_GREEN
);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW,
EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @(clk) begin
if ($time % 21 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
| 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules
nsCounter clock1 (
clk,
count1
); // Count a total of 32 seconds
ewCounter clock2 (
clk,
count2
); // Counts a total of 16 seconds
yellowCounter clock3 (
clk,
count3
); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (
count1,
count2,
count3,
NS_VEHICLE_DETECT,
EW_VEHICLE_DETECT,
NS_RED,
NS_YELLOW,
NS_GREEN,
EW_RED,
EW_YELLOW,
EW_GREEN
);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW,
EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @(clk) begin
if ($time % 15 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 6 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
| 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules
nsCounter clock1 (
clk,
count1
); // Count a total of 32 seconds
ewCounter clock2 (
clk,
count2
); // Counts a total of 16 seconds
yellowCounter clock3 (
clk,
count3
); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (
count1,
count2,
count3,
NS_VEHICLE_DETECT,
EW_VEHICLE_DETECT,
NS_RED,
NS_YELLOW,
NS_GREEN,
EW_RED,
EW_YELLOW,
EW_GREEN
);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW,
EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @(clk) begin
if ($time % 6 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 15 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
| 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules
nsCounter clock1 (
clk,
count1
); // Count a total of 32 seconds
ewCounter clock2 (
clk,
count2
); // Counts a total of 16 seconds
yellowCounter clock3 (
clk,
count3
); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (
count1,
count2,
count3,
NS_VEHICLE_DETECT,
EW_VEHICLE_DETECT,
NS_RED,
NS_YELLOW,
NS_GREEN,
EW_RED,
EW_YELLOW,
EW_GREEN
);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW,
EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @(clk) begin
if ($time % 2 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 15 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
| 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules
nsCounter clock1 (
clk,
count1
); // Count a total of 32 seconds
ewCounter clock2 (
clk,
count2
); // Counts a total of 16 seconds
yellowCounter clock3 (
clk,
count3
); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (
count1,
count2,
count3,
NS_VEHICLE_DETECT,
EW_VEHICLE_DETECT,
NS_RED,
NS_YELLOW,
NS_GREEN,
EW_RED,
EW_YELLOW,
EW_GREEN
);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW,
EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @(clk) begin
if ($time % 15 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 2 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
| 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules
nsCounter clock1 (
clk,
count1
); // Count a total of 32 seconds
ewCounter clock2 (
clk,
count2
); // Counts a total of 16 seconds
yellowCounter clock3 (
clk,
count3
); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (
count1,
count2,
count3,
NS_VEHICLE_DETECT,
EW_VEHICLE_DETECT,
NS_RED,
NS_YELLOW,
NS_GREEN,
EW_RED,
EW_YELLOW,
EW_GREEN
);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW,
EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @(clk) begin
if ($time % 2 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 3 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
| 6.668911 |
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire [4:0] count1;
wire [3:0] count2;
wire [1:0] count3;
// Counter Modules
nsCounter clock1 (
clk,
count1
); // Count a total of 32 seconds
ewCounter clock2 (
clk,
count2
); // Counts a total of 16 seconds
yellowCounter clock3 (
clk,
count3
); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (
count1,
count2,
count3,
NS_VEHICLE_DETECT,
EW_VEHICLE_DETECT,
NS_RED,
NS_YELLOW,
NS_GREEN,
EW_RED,
EW_YELLOW,
EW_GREEN
);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 1;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW,
EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
endmodule
| 6.668911 |
module ram(
// read domain
input rd_clk,
input [ADDR_WIDTH-1:0] rd_addr,
output [DATA_WIDTH-1:0] rd_data,
// write domain
input wr_clk,
input wr_enable,
input [ADDR_WIDTH-1:0] wr_addr,
input [DATA_WIDTH-1:0] wr_data,
);
parameter ADDR_WIDTH=8;
parameter DATA_WIDTH=8;
parameter NUM_BYTES=256;
reg [DATA_WIDTH-1:0] mem[0:NUM_BYTES-1];
reg [DATA_WIDTH-1:0] rd_data;
//initial $readmemh("packed0.hex", mem);
initial $readmemh("fb-init.hex", mem);
always @(posedge rd_clk)
rd_data <= mem[rd_addr];
//assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
if (wr_enable)
mem[wr_addr] <= wr_data;
endmodule
| 7.686454 |
module display_mapper (
input [12:0] linear_addr,
output [12:0] ram_addr
);
parameter PANEL_SHIFT_WIDTH = (13 * 32) / 32;
wire y_bank = linear_addr[4];
wire [4:0] y_addr = linear_addr[3:0] + (y_bank ? 0 : 16);
wire [12:0] x_value = linear_addr[12:5];
wire [12:0] x_offset;
reg [2:0] x_minor;
reg [12:0] x_major;
always @(*) begin
if (x_value >= 7 * PANEL_SHIFT_WIDTH) begin
x_minor = 7;
x_major = x_value - 7 * PANEL_SHIFT_WIDTH;
end else if (x_value >= 6 * PANEL_SHIFT_WIDTH) begin
x_minor = 6;
x_major = x_value - 6 * PANEL_SHIFT_WIDTH;
end else if (x_value >= 5 * PANEL_SHIFT_WIDTH) begin
x_minor = 5;
x_major = x_value - 5 * PANEL_SHIFT_WIDTH;
end else if (x_value >= 4 * PANEL_SHIFT_WIDTH) begin
x_minor = 4;
x_major = x_value - 4 * PANEL_SHIFT_WIDTH;
end else if (x_value >= 3 * PANEL_SHIFT_WIDTH) begin
x_minor = 3;
x_major = x_value - 3 * PANEL_SHIFT_WIDTH;
end else if (x_value >= 2 * PANEL_SHIFT_WIDTH) begin
x_minor = 2;
x_major = x_value - 2 * PANEL_SHIFT_WIDTH;
end else if (x_value >= 1 * PANEL_SHIFT_WIDTH) begin
x_minor = 1;
x_major = x_value - 1 * PANEL_SHIFT_WIDTH;
end else begin
x_minor = 0;
x_major = x_value;
end
end
wire [12:0] x_addr = x_major * 8 + x_minor;
assign ram_addr = x_addr + y_addr * `PANEL_PITCH;
endmodule
| 6.82078 |
module adder_8bit (
a,
b,
y
);
input [0:7] a;
input [0:7] b;
output [0:7] y;
wire n2, n3, n4, n5, n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58;
INV_X2 U5 (
.I (b[2]),
.ZN(n34)
);
NOR2_X1 U6 (
.A1(b[6]),
.A2(a[6]),
.ZN(n3)
);
NOR2_X1 U7 (
.A1(n24),
.A2(n23),
.ZN(n28)
);
AOI21_X2 U8 (
.A1(n29),
.A2(n28),
.B (n2),
.ZN(n7)
);
OAI21_X2 U9 (
.A1(n27),
.A2(n26),
.B (n25),
.ZN(n2)
);
NAND2_X1 U10 (
.A1(n34),
.A2(n33),
.ZN(n4)
);
NAND2_X2 U11 (
.A1(n34),
.A2(n33),
.ZN(n5)
);
NAND2_X1 U12 (
.A1(n34),
.A2(n33),
.ZN(n42)
);
AOI21_X1 U13 (
.A1(n5),
.A2(n41),
.B (n40),
.ZN(n6)
);
INV_X2 U14 (
.I (n32),
.ZN(n41)
);
NAND2_X2 U15 (
.A1(b[4]),
.A2(a[4]),
.ZN(n25)
);
NOR2_X2 U16 (
.A1(a[4]),
.A2(b[4]),
.ZN(n24)
);
AOI21_X2 U17 (
.A1(n12),
.A2(n22),
.B (n21),
.ZN(n29)
);
NAND2_X2 U18 (
.A1(b[6]),
.A2(a[6]),
.ZN(n12)
);
NAND2_X2 U19 (
.A1(a[7]),
.A2(b[7]),
.ZN(n22)
);
INV_X1 U20 (
.I (n13),
.ZN(n9)
);
NOR2_X1 U21 (
.A1(n9),
.A2(n8),
.ZN(y[7])
);
NOR2_X2 U23 (
.A1(b[6]),
.A2(a[6]),
.ZN(n21)
);
NOR2_X1 U24 (
.A1(n58),
.A2(n21),
.ZN(n11)
);
XNOR2_X1 U26 (
.A1(n11),
.A2(n13),
.ZN(y[6])
);
NOR2_X2 U27 (
.A1(a[5]),
.A2(b[5]),
.ZN(n23)
);
INV_X1 U28 (
.I (n23),
.ZN(n16)
);
NAND2_X2 U29 (
.A1(a[5]),
.A2(b[5]),
.ZN(n26)
);
NAND2_X1 U30 (
.A1(n16),
.A2(n26),
.ZN(n14)
);
OAI21_X1 U31 (
.A1(n13),
.A2(n3),
.B (n57),
.ZN(n17)
);
XNOR2_X1 U32 (
.A1(n14),
.A2(n17),
.ZN(y[5])
);
AND2_X1 U33 (
.A1(a[5]),
.A2(b[5]),
.Z (n15)
);
AOI21_X1 U34 (
.A1(n17),
.A2(n16),
.B (n15),
.ZN(n20)
);
AND2_X1 U35 (
.A1(a[4]),
.A2(b[4]),
.Z (n18)
);
NOR2_X1 U36 (
.A1(n18),
.A2(n24),
.ZN(n19)
);
XNOR2_X1 U37 (
.A1(n20),
.A2(n19),
.ZN(y[4])
);
NOR2_X2 U38 (
.A1(a[4]),
.A2(b[4]),
.ZN(n27)
);
INV_X2 U39 (
.I (n7),
.ZN(n54)
);
INV_X1 U40 (
.I (n54),
.ZN(n31)
);
NAND2_X1 U41 (
.A1(b[3]),
.A2(a[3]),
.ZN(n32)
);
NOR2_X1 U42 (
.A1(n41),
.A2(n37),
.ZN(n30)
);
XNOR2_X1 U43 (
.A1(n31),
.A2(n30),
.ZN(y[3])
);
OAI21_X1 U44 (
.A1(n37),
.A2(n7),
.B (n32),
.ZN(n36)
);
INV_X2 U45 (
.I (a[2]),
.ZN(n33)
);
NAND2_X1 U46 (
.A1(b[2]),
.A2(a[2]),
.ZN(n39)
);
NAND2_X1 U47 (
.A1(n4),
.A2(n39),
.ZN(n35)
);
XNOR2_X1 U48 (
.A1(n36),
.A2(n35),
.ZN(y[2])
);
INV_X1 U49 (
.I (n37),
.ZN(n38)
);
NAND2_X1 U50 (
.A1(n42),
.A2(n38),
.ZN(n48)
);
INV_X1 U51 (
.I (n39),
.ZN(n40)
);
AOI21_X2 U52 (
.A1(n5),
.A2(n41),
.B (n40),
.ZN(n51)
);
OAI21_X1 U53 (
.A1(n48),
.A2(n7),
.B (n6),
.ZN(n46)
);
NAND2_X1 U57 (
.A1(n47),
.A2(n49),
.ZN(n45)
);
XNOR2_X1 U58 (
.A1(n46),
.A2(n45),
.ZN(y[1])
);
INV_X1 U59 (
.I (n47),
.ZN(n50)
);
NOR2_X1 U60 (
.A1(n48),
.A2(n50),
.ZN(n53)
);
OAI21_X2 U61 (
.A1(n51),
.A2(n50),
.B (n49),
.ZN(n52)
);
AOI21_X2 U62 (
.A1(n54),
.A2(n53),
.B (n52),
.ZN(n56)
);
XOR2_X1 U63 (
.A1(b[0]),
.A2(a[0]),
.Z (n55)
);
XNOR2_X1 U64 (
.A1(n56),
.A2(n55),
.ZN(y[0])
);
OR2_X1 U4 (
.A1(a[1]),
.A2(b[1]),
.Z (n47)
);
NOR2_X2 U54 (
.A1(b[3]),
.A2(a[3]),
.ZN(n37)
);
NAND2_X1 U2 (
.A1(b[1]),
.A2(a[1]),
.ZN(n49)
);
NAND2_X1 U3 (
.A1(b[6]),
.A2(a[6]),
.ZN(n57)
);
AND2_X1 U22 (
.A1(b[6]),
.A2(a[6]),
.Z (n58)
);
NOR2_X1 U25 (
.A1(a[7]),
.A2(b[7]),
.ZN(n8)
);
NAND2_X2 U55 (
.A1(a[7]),
.A2(b[7]),
.ZN(n13)
);
endmodule
| 6.892153 |
module adder_8bit (
a,
b,
y
);
input [0:7] a;
input [0:7] b;
output [0:7] y;
wire n2, n3, n4, n5, n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58;
INV_X2 U5 (
.I (b[2]),
.ZN(n34)
);
NOR2_X1 U6 (
.A1(b[6]),
.A2(a[6]),
.ZN(n3)
);
NOR2_X1 U7 (
.A1(n24),
.A2(n23),
.ZN(n28)
);
AOI21_X2 U8 (
.A1(n29),
.A2(n28),
.B (n2),
.ZN(n7)
);
OAI21_X2 U9 (
.A1(n27),
.A2(n26),
.B (n25),
.ZN(n2)
);
NAND2_X1 U10 (
.A1(n34),
.A2(n33),
.ZN(n4)
);
NAND2_X2 U11 (
.A1(n34),
.A2(n33),
.ZN(n5)
);
NAND2_X1 U12 (
.A1(n34),
.A2(n33),
.ZN(n42)
);
AOI21_X1 U13 (
.A1(n5),
.A2(n41),
.B (n40),
.ZN(n6)
);
INV_X2 U14 (
.I (n32),
.ZN(n41)
);
NAND2_X2 U15 (
.A1(b[4]),
.A2(a[4]),
.ZN(n25)
);
NOR2_X2 U16 (
.A1(a[4]),
.A2(b[4]),
.ZN(n24)
);
AOI21_X2 U17 (
.A1(n12),
.A2(n22),
.B (n21),
.ZN(n29)
);
NAND2_X2 U18 (
.A1(b[6]),
.A2(a[6]),
.ZN(n12)
);
NAND2_X2 U19 (
.A1(a[7]),
.A2(b[7]),
.ZN(n22)
);
INV_X1 U20 (
.I (n13),
.ZN(n9)
);
NOR2_X1 U21 (
.A1(n9),
.A2(n8),
.ZN(y[7])
);
NOR2_X2 U23 (
.A1(b[6]),
.A2(a[6]),
.ZN(n21)
);
NOR2_X1 U24 (
.A1(n58),
.A2(n21),
.ZN(n11)
);
XNOR2_X1 U26 (
.A1(n11),
.A2(n13),
.ZN(y[6])
);
NOR2_X2 U27 (
.A1(a[5]),
.A2(b[5]),
.ZN(n23)
);
INV_X1 U28 (
.I (n23),
.ZN(n16)
);
NAND2_X2 U29 (
.A1(a[5]),
.A2(b[5]),
.ZN(n26)
);
NAND2_X1 U30 (
.A1(n16),
.A2(n26),
.ZN(n14)
);
OAI21_X1 U31 (
.A1(n13),
.A2(n3),
.B (n57),
.ZN(n17)
);
XNOR2_X1 U32 (
.A1(n14),
.A2(n17),
.ZN(y[5])
);
AND2_X1 U33 (
.A1(a[5]),
.A2(b[5]),
.Z (n15)
);
AOI21_X1 U34 (
.A1(n17),
.A2(n16),
.B (n15),
.ZN(n20)
);
AND2_X1 U35 (
.A1(a[4]),
.A2(b[4]),
.Z (n18)
);
NOR2_X1 U36 (
.A1(n18),
.A2(n24),
.ZN(n19)
);
XNOR2_X1 U37 (
.A1(n20),
.A2(n19),
.ZN(y[4])
);
NOR2_X2 U38 (
.A1(a[4]),
.A2(b[4]),
.ZN(n27)
);
INV_X2 U39 (
.I (n7),
.ZN(n54)
);
INV_X1 U40 (
.I (n54),
.ZN(n31)
);
NAND2_X1 U41 (
.A1(b[3]),
.A2(a[3]),
.ZN(n32)
);
NOR2_X1 U42 (
.A1(n41),
.A2(n37),
.ZN(n30)
);
XNOR2_X1 U43 (
.A1(n31),
.A2(n30),
.ZN(y[3])
);
OAI21_X1 U44 (
.A1(n37),
.A2(n7),
.B (n32),
.ZN(n36)
);
INV_X2 U45 (
.I (a[2]),
.ZN(n33)
);
NAND2_X1 U46 (
.A1(b[2]),
.A2(a[2]),
.ZN(n39)
);
NAND2_X1 U47 (
.A1(n4),
.A2(n39),
.ZN(n35)
);
XNOR2_X1 U48 (
.A1(n36),
.A2(n35),
.ZN(y[2])
);
INV_X1 U49 (
.I (n37),
.ZN(n38)
);
NAND2_X1 U50 (
.A1(n42),
.A2(n38),
.ZN(n48)
);
INV_X1 U51 (
.I (n39),
.ZN(n40)
);
AOI21_X2 U52 (
.A1(n5),
.A2(n41),
.B (n40),
.ZN(n51)
);
OAI21_X1 U53 (
.A1(n48),
.A2(n7),
.B (n6),
.ZN(n46)
);
NAND2_X1 U57 (
.A1(n47),
.A2(n49),
.ZN(n45)
);
XNOR2_X1 U58 (
.A1(n46),
.A2(n45),
.ZN(y[1])
);
INV_X1 U59 (
.I (n47),
.ZN(n50)
);
NOR2_X1 U60 (
.A1(n48),
.A2(n50),
.ZN(n53)
);
OAI21_X2 U61 (
.A1(n51),
.A2(n50),
.B (n49),
.ZN(n52)
);
AOI21_X2 U62 (
.A1(n54),
.A2(n53),
.B (n52),
.ZN(n56)
);
XOR2_X1 U63 (
.A1(b[0]),
.A2(a[0]),
.Z (n55)
);
XNOR2_X1 U64 (
.A1(n56),
.A2(n55),
.ZN(y[0])
);
OR2_X1 U4 (
.A1(a[1]),
.A2(b[1]),
.Z (n47)
);
NOR2_X2 U54 (
.A1(b[3]),
.A2(a[3]),
.ZN(n37)
);
NAND2_X1 U2 (
.A1(b[1]),
.A2(a[1]),
.ZN(n49)
);
NAND2_X1 U3 (
.A1(b[6]),
.A2(a[6]),
.ZN(n57)
);
AND2_X1 U22 (
.A1(b[6]),
.A2(a[6]),
.Z (n58)
);
NOR2_X1 U25 (
.A1(a[7]),
.A2(b[7]),
.ZN(n8)
);
NAND2_X2 U55 (
.A1(a[7]),
.A2(b[7]),
.ZN(n13)
);
endmodule
| 6.892153 |
module adder_8bit (
a,
b,
y
);
input [0:7] a;
input [0:7] b;
output [0:7] y;
wire n2, n3, n4, n5, n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58;
INV_X2 U5 (
.I (b[2]),
.ZN(n34)
);
NOR2_X1 U6 (
.A1(b[6]),
.A2(a[6]),
.ZN(n3)
);
NOR2_X1 U7 (
.A1(n24),
.A2(n23),
.ZN(n28)
);
AOI21_X2 U8 (
.A1(n29),
.A2(n28),
.B (n2),
.ZN(n7)
);
OAI21_X2 U9 (
.A1(n27),
.A2(n26),
.B (n25),
.ZN(n2)
);
NAND2_X1 U10 (
.A1(n34),
.A2(n33),
.ZN(n4)
);
NAND2_X2 U11 (
.A1(n34),
.A2(n33),
.ZN(n5)
);
NAND2_X1 U12 (
.A1(n34),
.A2(n33),
.ZN(n42)
);
AOI21_X1 U13 (
.A1(n5),
.A2(n41),
.B (n40),
.ZN(n6)
);
INV_X2 U14 (
.I (n32),
.ZN(n41)
);
NAND2_X2 U15 (
.A1(b[4]),
.A2(a[4]),
.ZN(n25)
);
NOR2_X2 U16 (
.A1(a[4]),
.A2(b[4]),
.ZN(n24)
);
AOI21_X2 U17 (
.A1(n12),
.A2(n22),
.B (n21),
.ZN(n29)
);
NAND2_X2 U18 (
.A1(b[6]),
.A2(a[6]),
.ZN(n12)
);
NAND2_X2 U19 (
.A1(a[7]),
.A2(b[7]),
.ZN(n22)
);
INV_X1 U20 (
.I (n13),
.ZN(n9)
);
NOR2_X1 U21 (
.A1(n9),
.A2(n8),
.ZN(y[7])
);
NOR2_X2 U23 (
.A1(b[6]),
.A2(a[6]),
.ZN(n21)
);
NOR2_X1 U24 (
.A1(n58),
.A2(n21),
.ZN(n11)
);
XNOR2_X1 U26 (
.A1(n11),
.A2(n13),
.ZN(y[6])
);
NOR2_X2 U27 (
.A1(a[5]),
.A2(b[5]),
.ZN(n23)
);
INV_X1 U28 (
.I (n23),
.ZN(n16)
);
NAND2_X2 U29 (
.A1(a[5]),
.A2(b[5]),
.ZN(n26)
);
NAND2_X1 U30 (
.A1(n16),
.A2(n26),
.ZN(n14)
);
OAI21_X1 U31 (
.A1(n13),
.A2(n3),
.B (n57),
.ZN(n17)
);
XNOR2_X1 U32 (
.A1(n14),
.A2(n17),
.ZN(y[5])
);
AND2_X1 U33 (
.A1(a[5]),
.A2(b[5]),
.Z (n15)
);
AOI21_X1 U34 (
.A1(n17),
.A2(n16),
.B (n15),
.ZN(n20)
);
AND2_X1 U35 (
.A1(a[4]),
.A2(b[4]),
.Z (n18)
);
NOR2_X1 U36 (
.A1(n18),
.A2(n24),
.ZN(n19)
);
XNOR2_X1 U37 (
.A1(n20),
.A2(n19),
.ZN(y[4])
);
NOR2_X2 U38 (
.A1(a[4]),
.A2(b[4]),
.ZN(n27)
);
INV_X2 U39 (
.I (n7),
.ZN(n54)
);
INV_X1 U40 (
.I (n54),
.ZN(n31)
);
NAND2_X1 U41 (
.A1(b[3]),
.A2(a[3]),
.ZN(n32)
);
NOR2_X1 U42 (
.A1(n41),
.A2(n37),
.ZN(n30)
);
XNOR2_X1 U43 (
.A1(n31),
.A2(n30),
.ZN(y[3])
);
OAI21_X1 U44 (
.A1(n37),
.A2(n7),
.B (n32),
.ZN(n36)
);
INV_X2 U45 (
.I (a[2]),
.ZN(n33)
);
NAND2_X1 U46 (
.A1(b[2]),
.A2(a[2]),
.ZN(n39)
);
NAND2_X1 U47 (
.A1(n4),
.A2(n39),
.ZN(n35)
);
XNOR2_X1 U48 (
.A1(n36),
.A2(n35),
.ZN(y[2])
);
INV_X1 U49 (
.I (n37),
.ZN(n38)
);
NAND2_X1 U50 (
.A1(n42),
.A2(n38),
.ZN(n48)
);
INV_X1 U51 (
.I (n39),
.ZN(n40)
);
AOI21_X2 U52 (
.A1(n5),
.A2(n41),
.B (n40),
.ZN(n51)
);
OAI21_X1 U53 (
.A1(n48),
.A2(n7),
.B (n6),
.ZN(n46)
);
NAND2_X1 U57 (
.A1(n47),
.A2(n49),
.ZN(n45)
);
XNOR2_X1 U58 (
.A1(n46),
.A2(n45),
.ZN(y[1])
);
INV_X1 U59 (
.I (n47),
.ZN(n50)
);
NOR2_X1 U60 (
.A1(n48),
.A2(n50),
.ZN(n53)
);
OAI21_X2 U61 (
.A1(n51),
.A2(n50),
.B (n49),
.ZN(n52)
);
AOI21_X2 U62 (
.A1(n54),
.A2(n53),
.B (n52),
.ZN(n56)
);
XOR2_X1 U63 (
.A1(b[0]),
.A2(a[0]),
.Z (n55)
);
XNOR2_X1 U64 (
.A1(n56),
.A2(n55),
.ZN(y[0])
);
OR2_X1 U4 (
.A1(a[1]),
.A2(b[1]),
.Z (n47)
);
NOR2_X2 U54 (
.A1(b[3]),
.A2(a[3]),
.ZN(n37)
);
NAND2_X1 U2 (
.A1(b[1]),
.A2(a[1]),
.ZN(n49)
);
NAND2_X1 U3 (
.A1(b[6]),
.A2(a[6]),
.ZN(n57)
);
AND2_X1 U22 (
.A1(b[6]),
.A2(a[6]),
.Z (n58)
);
NOR2_X1 U25 (
.A1(a[7]),
.A2(b[7]),
.ZN(n8)
);
NAND2_X2 U55 (
.A1(a[7]),
.A2(b[7]),
.ZN(n13)
);
endmodule
| 6.892153 |
module adder_8bit (
a,
b,
y
);
input [0:7] a;
input [0:7] b;
output [0:7] y;
wire n2, n3, n4, n5, n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58;
INV_X2 U5 (
.I (b[2]),
.ZN(n34)
);
NOR2_X1 U6 (
.A1(b[6]),
.A2(a[6]),
.ZN(n3)
);
NOR2_X1 U7 (
.A1(n24),
.A2(n23),
.ZN(n28)
);
AOI21_X2 U8 (
.A1(n29),
.A2(n28),
.B (n2),
.ZN(n7)
);
OAI21_X2 U9 (
.A1(n27),
.A2(n26),
.B (n25),
.ZN(n2)
);
NAND2_X1 U10 (
.A1(n34),
.A2(n33),
.ZN(n4)
);
NAND2_X2 U11 (
.A1(n34),
.A2(n33),
.ZN(n5)
);
NAND2_X1 U12 (
.A1(n34),
.A2(n33),
.ZN(n42)
);
AOI21_X1 U13 (
.A1(n5),
.A2(n41),
.B (n40),
.ZN(n6)
);
INV_X2 U14 (
.I (n32),
.ZN(n41)
);
NAND2_X2 U15 (
.A1(b[4]),
.A2(a[4]),
.ZN(n25)
);
NOR2_X2 U16 (
.A1(a[4]),
.A2(b[4]),
.ZN(n24)
);
AOI21_X2 U17 (
.A1(n12),
.A2(n22),
.B (n21),
.ZN(n29)
);
NAND2_X2 U18 (
.A1(b[6]),
.A2(a[6]),
.ZN(n12)
);
NAND2_X2 U19 (
.A1(a[7]),
.A2(b[7]),
.ZN(n22)
);
INV_X1 U20 (
.I (n13),
.ZN(n9)
);
NOR2_X1 U21 (
.A1(n9),
.A2(n8),
.ZN(y[7])
);
NOR2_X2 U23 (
.A1(b[6]),
.A2(a[6]),
.ZN(n21)
);
NOR2_X1 U24 (
.A1(n58),
.A2(n21),
.ZN(n11)
);
XNOR2_X1 U26 (
.A1(n11),
.A2(n13),
.ZN(y[6])
);
NOR2_X2 U27 (
.A1(a[5]),
.A2(b[5]),
.ZN(n23)
);
INV_X1 U28 (
.I (n23),
.ZN(n16)
);
NAND2_X2 U29 (
.A1(a[5]),
.A2(b[5]),
.ZN(n26)
);
NAND2_X1 U30 (
.A1(n16),
.A2(n26),
.ZN(n14)
);
OAI21_X1 U31 (
.A1(n13),
.A2(n3),
.B (n57),
.ZN(n17)
);
XNOR2_X1 U32 (
.A1(n14),
.A2(n17),
.ZN(y[5])
);
AND2_X1 U33 (
.A1(a[5]),
.A2(b[5]),
.Z (n15)
);
AOI21_X1 U34 (
.A1(n17),
.A2(n16),
.B (n15),
.ZN(n20)
);
AND2_X1 U35 (
.A1(a[4]),
.A2(b[4]),
.Z (n18)
);
NOR2_X1 U36 (
.A1(n18),
.A2(n24),
.ZN(n19)
);
XNOR2_X1 U37 (
.A1(n20),
.A2(n19),
.ZN(y[4])
);
NOR2_X2 U38 (
.A1(a[4]),
.A2(b[4]),
.ZN(n27)
);
INV_X2 U39 (
.I (n7),
.ZN(n54)
);
INV_X1 U40 (
.I (n54),
.ZN(n31)
);
NAND2_X1 U41 (
.A1(b[3]),
.A2(a[3]),
.ZN(n32)
);
NOR2_X1 U42 (
.A1(n41),
.A2(n37),
.ZN(n30)
);
XNOR2_X1 U43 (
.A1(n31),
.A2(n30),
.ZN(y[3])
);
OAI21_X1 U44 (
.A1(n37),
.A2(n7),
.B (n32),
.ZN(n36)
);
INV_X2 U45 (
.I (a[2]),
.ZN(n33)
);
NAND2_X1 U46 (
.A1(b[2]),
.A2(a[2]),
.ZN(n39)
);
NAND2_X1 U47 (
.A1(n4),
.A2(n39),
.ZN(n35)
);
XNOR2_X1 U48 (
.A1(n36),
.A2(n35),
.ZN(y[2])
);
INV_X1 U49 (
.I (n37),
.ZN(n38)
);
NAND2_X1 U50 (
.A1(n42),
.A2(n38),
.ZN(n48)
);
INV_X1 U51 (
.I (n39),
.ZN(n40)
);
AOI21_X2 U52 (
.A1(n5),
.A2(n41),
.B (n40),
.ZN(n51)
);
OAI21_X1 U53 (
.A1(n48),
.A2(n7),
.B (n6),
.ZN(n46)
);
NAND2_X1 U57 (
.A1(n47),
.A2(n49),
.ZN(n45)
);
XNOR2_X1 U58 (
.A1(n46),
.A2(n45),
.ZN(y[1])
);
INV_X1 U59 (
.I (n47),
.ZN(n50)
);
NOR2_X1 U60 (
.A1(n48),
.A2(n50),
.ZN(n53)
);
OAI21_X2 U61 (
.A1(n51),
.A2(n50),
.B (n49),
.ZN(n52)
);
AOI21_X2 U62 (
.A1(n54),
.A2(n53),
.B (n52),
.ZN(n56)
);
XOR2_X1 U63 (
.A1(b[0]),
.A2(a[0]),
.Z (n55)
);
XNOR2_X1 U64 (
.A1(n56),
.A2(n55),
.ZN(y[0])
);
OR2_X1 U4 (
.A1(a[1]),
.A2(b[1]),
.Z (n47)
);
NOR2_X2 U54 (
.A1(b[3]),
.A2(a[3]),
.ZN(n37)
);
NAND2_X1 U2 (
.A1(b[1]),
.A2(a[1]),
.ZN(n49)
);
NAND2_X1 U3 (
.A1(b[6]),
.A2(a[6]),
.ZN(n57)
);
AND2_X1 U22 (
.A1(b[6]),
.A2(a[6]),
.Z (n58)
);
NOR2_X1 U25 (
.A1(a[7]),
.A2(b[7]),
.ZN(n8)
);
NAND2_X2 U55 (
.A1(a[7]),
.A2(b[7]),
.ZN(n13)
);
endmodule
| 6.892153 |
module adder_8bit (
a,
b,
y
);
input [0:7] a;
input [0:7] b;
output [0:7] y;
wire n2, n3, n4, n5, n6, n7, n8, n9, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58;
INV_X2 U5 (
.I (b[2]),
.ZN(n34)
);
NOR2_X1 U6 (
.A1(b[6]),
.A2(a[6]),
.ZN(n3)
);
NOR2_X1 U7 (
.A1(n24),
.A2(n23),
.ZN(n28)
);
AOI21_X2 U8 (
.A1(n29),
.A2(n28),
.B (n2),
.ZN(n7)
);
OAI21_X2 U9 (
.A1(n27),
.A2(n26),
.B (n25),
.ZN(n2)
);
NAND2_X1 U10 (
.A1(n34),
.A2(n33),
.ZN(n4)
);
NAND2_X2 U11 (
.A1(n34),
.A2(n33),
.ZN(n5)
);
NAND2_X1 U12 (
.A1(n34),
.A2(n33),
.ZN(n42)
);
AOI21_X1 U13 (
.A1(n5),
.A2(n41),
.B (n40),
.ZN(n6)
);
INV_X2 U14 (
.I (n32),
.ZN(n41)
);
NAND2_X2 U15 (
.A1(b[4]),
.A2(a[4]),
.ZN(n25)
);
NOR2_X2 U16 (
.A1(a[4]),
.A2(b[4]),
.ZN(n24)
);
AOI21_X2 U17 (
.A1(n12),
.A2(n22),
.B (n21),
.ZN(n29)
);
NAND2_X2 U18 (
.A1(b[6]),
.A2(a[6]),
.ZN(n12)
);
NAND2_X2 U19 (
.A1(a[7]),
.A2(b[7]),
.ZN(n22)
);
INV_X1 U20 (
.I (n13),
.ZN(n9)
);
NOR2_X1 U21 (
.A1(n9),
.A2(n8),
.ZN(y[7])
);
NOR2_X2 U23 (
.A1(b[6]),
.A2(a[6]),
.ZN(n21)
);
NOR2_X1 U24 (
.A1(n58),
.A2(n21),
.ZN(n11)
);
XNOR2_X1 U26 (
.A1(n11),
.A2(n13),
.ZN(y[6])
);
NOR2_X2 U27 (
.A1(a[5]),
.A2(b[5]),
.ZN(n23)
);
INV_X1 U28 (
.I (n23),
.ZN(n16)
);
NAND2_X2 U29 (
.A1(a[5]),
.A2(b[5]),
.ZN(n26)
);
NAND2_X1 U30 (
.A1(n16),
.A2(n26),
.ZN(n14)
);
OAI21_X1 U31 (
.A1(n13),
.A2(n3),
.B (n57),
.ZN(n17)
);
XNOR2_X1 U32 (
.A1(n14),
.A2(n17),
.ZN(y[5])
);
AND2_X1 U33 (
.A1(a[5]),
.A2(b[5]),
.Z (n15)
);
AOI21_X1 U34 (
.A1(n17),
.A2(n16),
.B (n15),
.ZN(n20)
);
AND2_X1 U35 (
.A1(a[4]),
.A2(b[4]),
.Z (n18)
);
NOR2_X1 U36 (
.A1(n18),
.A2(n24),
.ZN(n19)
);
XNOR2_X1 U37 (
.A1(n20),
.A2(n19),
.ZN(y[4])
);
NOR2_X2 U38 (
.A1(a[4]),
.A2(b[4]),
.ZN(n27)
);
INV_X2 U39 (
.I (n7),
.ZN(n54)
);
INV_X1 U40 (
.I (n54),
.ZN(n31)
);
NAND2_X1 U41 (
.A1(b[3]),
.A2(a[3]),
.ZN(n32)
);
NOR2_X1 U42 (
.A1(n41),
.A2(n37),
.ZN(n30)
);
XNOR2_X1 U43 (
.A1(n31),
.A2(n30),
.ZN(y[3])
);
OAI21_X1 U44 (
.A1(n37),
.A2(n7),
.B (n32),
.ZN(n36)
);
INV_X2 U45 (
.I (a[2]),
.ZN(n33)
);
NAND2_X1 U46 (
.A1(b[2]),
.A2(a[2]),
.ZN(n39)
);
NAND2_X1 U47 (
.A1(n4),
.A2(n39),
.ZN(n35)
);
XNOR2_X1 U48 (
.A1(n36),
.A2(n35),
.ZN(y[2])
);
INV_X1 U49 (
.I (n37),
.ZN(n38)
);
NAND2_X1 U50 (
.A1(n42),
.A2(n38),
.ZN(n48)
);
INV_X1 U51 (
.I (n39),
.ZN(n40)
);
AOI21_X2 U52 (
.A1(n5),
.A2(n41),
.B (n40),
.ZN(n51)
);
OAI21_X1 U53 (
.A1(n48),
.A2(n7),
.B (n6),
.ZN(n46)
);
NAND2_X1 U57 (
.A1(n47),
.A2(n49),
.ZN(n45)
);
XNOR2_X1 U58 (
.A1(n46),
.A2(n45),
.ZN(y[1])
);
INV_X1 U59 (
.I (n47),
.ZN(n50)
);
NOR2_X1 U60 (
.A1(n48),
.A2(n50),
.ZN(n53)
);
OAI21_X2 U61 (
.A1(n51),
.A2(n50),
.B (n49),
.ZN(n52)
);
AOI21_X2 U62 (
.A1(n54),
.A2(n53),
.B (n52),
.ZN(n56)
);
XOR2_X1 U63 (
.A1(b[0]),
.A2(a[0]),
.Z (n55)
);
XNOR2_X1 U64 (
.A1(n56),
.A2(n55),
.ZN(y[0])
);
OR2_X1 U4 (
.A1(a[1]),
.A2(b[1]),
.Z (n47)
);
NOR2_X2 U54 (
.A1(b[3]),
.A2(a[3]),
.ZN(n37)
);
NAND2_X1 U2 (
.A1(b[1]),
.A2(a[1]),
.ZN(n49)
);
NAND2_X1 U3 (
.A1(b[6]),
.A2(a[6]),
.ZN(n57)
);
AND2_X1 U22 (
.A1(b[6]),
.A2(a[6]),
.Z (n58)
);
NOR2_X1 U25 (
.A1(a[7]),
.A2(b[7]),
.ZN(n8)
);
NAND2_X2 U55 (
.A1(a[7]),
.A2(b[7]),
.ZN(n13)
);
endmodule
| 6.892153 |
module add_mul_1_bit (
a,
b,
operation,
Result
);
input a, b, operation;
output Result;
wire Result_add, Result_mul, n3, n4;
INV_X1 U4 (
.I (Result_add),
.ZN(n4)
);
NAND2_X1 U5 (
.A1(Result_mul),
.A2(operation),
.ZN(n3)
);
OAI21_X1 U6 (
.A1(n4),
.A2(operation),
.B (n3),
.ZN(Result)
);
XOR2_X1 \adder_1/U1 (
.A1(a),
.A2(b),
.Z (Result_add)
);
AND2_X1 \multiplier_1/U1 (
.A1(a),
.A2(b),
.Z (Result_mul)
);
endmodule
| 6.690052 |
module add_mul_2_bit (
a,
b,
operation,
Result
);
input [0:1] a;
input [0:1] b;
output [0:3] Result;
input operation;
wire n6, n7, n8, SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2,
\adder_1/n2 , \adder_1/n1 , \multiplier_1/n3 , \multiplier_1/n2 ,
\multiplier_1/n1 ;
wire [2:3] Result_add;
wire [0:3] Result_mul;
INV_X1 U10 (
.I (Result_add[2]),
.ZN(n8)
);
INV_X1 U11 (
.I (Result_mul[2]),
.ZN(n7)
);
INV_X1 U12 (
.I (operation),
.ZN(n6)
);
OAI22_X1 U13 (
.A1(n8),
.A2(operation),
.B1(n7),
.B2(n6),
.ZN(Result[2])
);
MUX2_X1 U14 (
.I0(Result_add[3]),
.I1(Result_mul[3]),
.S (operation),
.Z (Result[3])
);
AND2_X1 U15 (
.A1(Result_mul[1]),
.A2(operation),
.Z (Result[1])
);
AND2_X1 U16 (
.A1(Result_mul[0]),
.A2(operation),
.Z (Result[0])
);
XOR2_X1 \adder_1/U5 (
.A1(a[1]),
.A2(b[1]),
.Z (Result_add[3])
);
XNOR2_X1 \adder_1/U4 (
.A1(a[0]),
.A2(b[0]),
.ZN(\adder_1/n2 )
);
XNOR2_X1 \adder_1/U3 (
.A1(\adder_1/n2 ),
.A2(\adder_1/n1 ),
.ZN(Result_add[2])
);
AND2_X1 \adder_1/U2 (
.A1(a[1]),
.A2(b[1]),
.Z (\adder_1/n1 )
);
AOI22_X1 \multiplier_1/U1 (
.A1(a[0]),
.A2(b[1]),
.B1(b[0]),
.B2(a[1]),
.ZN(\multiplier_1/n3 )
);
NOR2_X1 \multiplier_1/U7 (
.A1(Result_mul[0]),
.A2(\multiplier_1/n3 ),
.ZN(Result_mul[2])
);
NOR2_X1 \multiplier_1/U6 (
.A1(\multiplier_1/n2 ),
.A2(\multiplier_1/n1 ),
.ZN(Result_mul[0])
);
NOR2_X1 \multiplier_1/U5 (
.A1(Result_mul[3]),
.A2(\multiplier_1/n1 ),
.ZN(Result_mul[1])
);
INV_X1 \multiplier_1/U4 (
.I (\multiplier_1/n2 ),
.ZN(Result_mul[3])
);
NAND2_X2 \multiplier_1/U3 (
.A1(b[1]),
.A2(a[1]),
.ZN(\multiplier_1/n2 )
);
NAND2_X2 \multiplier_1/U2 (
.A1(a[0]),
.A2(b[0]),
.ZN(\multiplier_1/n1 )
);
endmodule
| 6.768282 |
module add_mul_combine_2_bit (
a,
b,
Result_mul,
Result_add
);
input [0:1] a;
input [0:1] b;
output [0:3] Result_mul;
output [0:1] Result_add;
wire \adder_1/n2 , \adder_1/n1 , \multiplier_1/n3 , \multiplier_1/n2 , \multiplier_1/n1 ;
XOR2_X1 \adder_1/U4 (
.A1(a[1]),
.A2(b[1]),
.Z (Result_add[1])
);
XNOR2_X1 \adder_1/U3 (
.A1(a[0]),
.A2(b[0]),
.ZN(\adder_1/n2 )
);
XNOR2_X1 \adder_1/U2 (
.A1(\adder_1/n2 ),
.A2(\adder_1/n1 ),
.ZN(Result_add[0])
);
AND2_X1 \adder_1/U1 (
.A1(a[1]),
.A2(b[1]),
.Z (\adder_1/n1 )
);
AOI22_X1 \multiplier_1/U1 (
.A1(a[0]),
.A2(b[1]),
.B1(b[0]),
.B2(a[1]),
.ZN(\multiplier_1/n2 )
);
NOR2_X1 \multiplier_1/U7 (
.A1(Result_mul[3]),
.A2(\multiplier_1/n3 ),
.ZN(Result_mul[1])
);
NOR2_X1 \multiplier_1/U6 (
.A1(Result_mul[0]),
.A2(\multiplier_1/n2 ),
.ZN(Result_mul[2])
);
NOR2_X1 \multiplier_1/U5 (
.A1(\multiplier_1/n3 ),
.A2(\multiplier_1/n1 ),
.ZN(Result_mul[0])
);
INV_X1 \multiplier_1/U4 (
.I (\multiplier_1/n1 ),
.ZN(Result_mul[3])
);
NAND2_X2 \multiplier_1/U3 (
.A1(a[0]),
.A2(b[0]),
.ZN(\multiplier_1/n3 )
);
NAND2_X2 \multiplier_1/U2 (
.A1(b[1]),
.A2(a[1]),
.ZN(\multiplier_1/n1 )
);
endmodule
| 6.911403 |
module add_mul_comp_2_bit (
a,
b,
Result
);
input [0:1] a;
input [0:1] b;
output [0:3] Result;
wire n6, n7, n8, n9, n12, SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2,
\adder_1/n2 , \adder_1/n1 , \multiplier_1/n3 , \multiplier_1/n2 ,
\multiplier_1/n1 , \comparator_1/n5 , \comparator_1/n4 ,
\comparator_1/n3 , \comparator_1/n2 , \comparator_1/n1 ;
wire [2:3] Result_add;
wire [0:3] Result_mul;
NAND2_X1 U10 (
.A1(Result_mul[2]),
.A2(n12),
.ZN(n6)
);
INV_X1 U11 (
.I (Result_add[2]),
.ZN(n7)
);
OAI21_X1 U12 (
.A1(n7),
.A2(n12),
.B (n6),
.ZN(Result[2])
);
INV_X1 U13 (
.I (n12),
.ZN(n9)
);
AOI22_X1 U14 (
.A1(n9),
.A2(Result_add[3]),
.B1(Result_mul[3]),
.B2(n12),
.ZN(n8)
);
INV_X1 U15 (
.I (n8),
.ZN(Result[3])
);
AND2_X1 U16 (
.A1(n12),
.A2(Result_mul[1]),
.Z (Result[1])
);
AND2_X1 U17 (
.A1(n12),
.A2(Result_mul[0]),
.Z (Result[0])
);
XOR2_X1 \adder_1/U5 (
.A1(a[1]),
.A2(b[1]),
.Z (Result_add[3])
);
XNOR2_X1 \adder_1/U4 (
.A1(\adder_1/n2 ),
.A2(\adder_1/n1 ),
.ZN(Result_add[2])
);
AND2_X1 \adder_1/U3 (
.A1(a[1]),
.A2(b[1]),
.Z (\adder_1/n1 )
);
XNOR2_X1 \adder_1/U2 (
.A1(b[0]),
.A2(a[0]),
.ZN(\adder_1/n2 )
);
NAND2_X2 \multiplier_1/U3 (
.A1(a[0]),
.A2(b[0]),
.ZN(\multiplier_1/n1 )
);
AOI22_X1 \multiplier_1/U2 (
.A1(a[0]),
.A2(b[1]),
.B1(b[0]),
.B2(a[1]),
.ZN(\multiplier_1/n3 )
);
NAND2_X2 \multiplier_1/U1 (
.A1(b[1]),
.A2(a[1]),
.ZN(\multiplier_1/n2 )
);
NOR2_X1 \multiplier_1/U7 (
.A1(Result_mul[0]),
.A2(\multiplier_1/n3 ),
.ZN(Result_mul[2])
);
NOR2_X1 \multiplier_1/U6 (
.A1(\multiplier_1/n2 ),
.A2(\multiplier_1/n1 ),
.ZN(Result_mul[0])
);
NOR2_X1 \multiplier_1/U5 (
.A1(Result_mul[3]),
.A2(\multiplier_1/n1 ),
.ZN(Result_mul[1])
);
INV_X1 \multiplier_1/U4 (
.I (\multiplier_1/n2 ),
.ZN(Result_mul[3])
);
INV_X2 \comparator_1/U3 (
.I (a[0]),
.ZN(\comparator_1/n3 )
);
INV_X2 \comparator_1/U2 (
.I (b[1]),
.ZN(\comparator_1/n2 )
);
NAND2_X2 \comparator_1/U6 (
.A1(\comparator_1/n2 ),
.A2(a[1]),
.ZN(\comparator_1/n4 )
);
AOI22_X2 \comparator_1/U5 (
.A1(\comparator_1/n5 ),
.A2(\comparator_1/n4 ),
.B1(b[0]),
.B2(\comparator_1/n3 ),
.ZN(n12)
);
NAND2_X2 \comparator_1/U4 (
.A1(\comparator_1/n1 ),
.A2(a[0]),
.ZN(\comparator_1/n5 )
);
INV_X2 \comparator_1/U1 (
.I (b[0]),
.ZN(\comparator_1/n1 )
);
endmodule
| 6.970429 |
module add_mul_mix_2_bit (
a,
b,
c,
d,
Result
);
input [0:1] a;
input [0:1] b;
input [0:1] c;
input [0:1] d;
output [0:3] Result;
wire \adder_1/n3 , \adder_1/n2 , \adder_1/n1 , \adder_2/n7 , \adder_2/n6 ,
\adder_2/n5 , \adder_2/n4 , \adder_2/n3 , \adder_2/n2 , \adder_2/n1 ,
\multiplier_1/n6 , \multiplier_1/n5 , \multiplier_1/n4 ,
\multiplier_1/n3 , \multiplier_1/n2 , \multiplier_1/n1 ;
wire [0:1] Result_add;
wire [0:1] Result_add_2;
XNOR2_X1 \adder_1/U5 (
.A1(\adder_1/n3 ),
.A2(b[1]),
.ZN(Result_add[1])
);
INV_X12 \adder_1/U4 (
.I (a[1]),
.ZN(\adder_1/n3 )
);
XNOR2_X1 \adder_1/U3 (
.A1(a[0]),
.A2(b[0]),
.ZN(\adder_1/n2 )
);
XNOR2_X1 \adder_1/U2 (
.A1(\adder_1/n2 ),
.A2(\adder_1/n1 ),
.ZN(Result_add[0])
);
AND2_X1 \adder_1/U1 (
.A1(a[1]),
.A2(b[1]),
.Z (\adder_1/n1 )
);
XNOR2_X1 \adder_2/U9 (
.A1(\adder_2/n7 ),
.A2(\adder_2/n6 ),
.ZN(Result_add_2[0])
);
NAND2_X1 \adder_2/U8 (
.A1(\adder_2/n5 ),
.A2(\adder_2/n4 ),
.ZN(\adder_2/n7 )
);
INV_X12 \adder_2/U7 (
.I (d[0]),
.ZN(\adder_2/n3 )
);
XNOR2_X1 \adder_2/U6 (
.A1(\adder_2/n1 ),
.A2(d[1]),
.ZN(Result_add_2[1])
);
INV_X12 \adder_2/U5 (
.I (c[1]),
.ZN(\adder_2/n1 )
);
INV_X12 \adder_2/U4 (
.I (c[0]),
.ZN(\adder_2/n2 )
);
NAND2_X2 \adder_2/U3 (
.A1(\adder_2/n2 ),
.A2(d[0]),
.ZN(\adder_2/n5 )
);
NAND2_X2 \adder_2/U2 (
.A1(\adder_2/n3 ),
.A2(c[0]),
.ZN(\adder_2/n4 )
);
NAND2_X1 \adder_2/U1 (
.A1(c[1]),
.A2(d[1]),
.ZN(\adder_2/n6 )
);
CLKBUF_X1 \multiplier_1/U10 (
.I(Result_add[1]),
.Z(\multiplier_1/n6 )
);
NOR2_X1 \multiplier_1/U9 (
.A1(Result[0]),
.A2(\multiplier_1/n5 ),
.ZN(Result[2])
);
AOI22_X1 \multiplier_1/U8 (
.A1(Result_add[0]),
.A2(Result_add_2[1]),
.B1(\multiplier_1/n6 ),
.B2(Result_add_2[0]),
.ZN(\multiplier_1/n5 )
);
NOR2_X1 \multiplier_1/U7 (
.A1(\multiplier_1/n4 ),
.A2(\multiplier_1/n3 ),
.ZN(Result[1])
);
NOR2_X1 \multiplier_1/U6 (
.A1(\multiplier_1/n2 ),
.A2(\multiplier_1/n3 ),
.ZN(Result[0])
);
INV_X2 \multiplier_1/U5 (
.I (Result_add[0]),
.ZN(\multiplier_1/n3 )
);
NAND2_X1 \multiplier_1/U4 (
.A1(\multiplier_1/n1 ),
.A2(Result_add_2[0]),
.ZN(\multiplier_1/n4 )
);
INV_X1 \multiplier_1/U3 (
.I (Result[3]),
.ZN(\multiplier_1/n1 )
);
AND2_X1 \multiplier_1/U2 (
.A1(Result_add_2[1]),
.A2(Result_add[1]),
.Z (Result[3])
);
NAND2_X1 \multiplier_1/U1 (
.A1(Result_add_2[0]),
.A2(Result[3]),
.ZN(\multiplier_1/n2 )
);
endmodule
| 6.645763 |
module Train_Display_Generator (
clock,
act_D,
addr16[15:0],
disp10[9:0]
);
// PI and PO
input act_D;
input clock;
input [15:0] addr16;
output [9:0] disp10;
reg [9:0] disp10;
always @(posedge clock)
if (act_D == 1) begin
case (addr16)
16'b0000000000000000: disp10 <= 10'b0000000000;
16'b0000000100100011: disp10 <= 10'b0000001111;
16'b0001001000110100: disp10 <= 10'b0000011110;
16'b0010001101000101: disp10 <= 10'b0000111100;
16'b0011010001010110: disp10 <= 10'b0001111000;
16'b0100010101100111: disp10 <= 10'b0011110000;
16'b0101011001111000: disp10 <= 10'b0111100000;
16'b0110011110001001: disp10 <= 10'b1111000000;
//16'b01111000: disp10 <= 10'b0110000000;
//16'b10001001: disp10 <= 10'b1100000000;
16'b0000000011111111: disp10 <= 10'b0000000000;
16'b0000000111111111: disp10 <= 10'b0000000011;
16'b0001001011111111: disp10 <= 10'b0000000110;
16'b0010001111111111: disp10 <= 10'b0000001100;
16'b0011010011111111: disp10 <= 10'b0000011000;
16'b0100010111111111: disp10 <= 10'b0000110000;
16'b0101011011111111: disp10 <= 10'b0001100000;
16'b0110011111111111: disp10 <= 10'b0011000000;
16'b0111100011111111: disp10 <= 10'b0110000000;
16'b1000100111111111: disp10 <= 10'b1100000000;
default: disp10 <= 10'b0000000000; // Number other than 0-9 is not displayed
endcase
end else begin
disp10 <= 10'b0000000000;
end
endmodule
| 6.726888 |
module: topFile
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module trajectoryTest;
// Inputs
reg CLK_50MHZ;
// Outputs
wire [0:7] LED;
wire LCD_E;
wire LCD_RS;
wire LCD_RW;
wire [11:8] SF_D;
// Instantiate the Unit Under Test (UUT)
topFile uut (
.CLK_50MHZ(CLK_50MHZ),
.LED(LED),
.LCD_E(LCD_E),
.LCD_RS(LCD_RS),
.LCD_RW(LCD_RW),
.SF_D(SF_D)
);
always
#20 CLK_50MHZ = !CLK_50MHZ;
initial begin
// Initialize Inputs
CLK_50MHZ = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 8.26225 |
module Tran (
input wire reset_n,
clk,
start,
byte,
[7 : 0] data_in,
output wire [7 : 0] data_o,
wire data_en
);
reg state;
parameter S_0 = 0;
parameter S_4 = 1;
reg [7 : 0] do;
reg en;
reg [3 : 0] buffer;
always @(posedge clk, negedge reset_n) begin
if(!reset_n) begin
state = 0;
buffer = 0;
en = 0;
do = 0;
end
else
if(start)
case(state)
S_0:
case(byte)
1: begin
state = state;
do = data_in;
en = 1;
end
0: begin
state = S_4;
buffer = data_in[3 : 0];
en = 0;
end
default: begin
state = 'bx;
en = 0;
end
endcase
S_4:
case(byte)
1: begin
state = state;
do = {data_in[3 : 0], buffer};
buffer = data_in[7 : 4];
en = 1;
end
0: begin
state = S_0;
do = {data_in[3 : 0], buffer};
en = 1;
end
default: begin
state = 'bx;
en = 0;
end
endcase
endcase
else begin
state = S_0;
buffer = 0;
en = 0;
end
end
assign data_o = do;
assign data_en = en;
endmodule
| 6.852328 |
module Tran2 (
input wire Rst,
Clk,
start,
byt,
input wire [7:0] DB,
output reg Out_en,
output reg [7:0] Out
);
reg [3:0] DB_reg; //hold the valid bits
reg empty; //there is data in DB_reg, 0 no, 1 yes
always @(posedge Clk, negedge Rst)
if (!Rst) empty <= 1'b0;
else if (start)
if (empty == 1'b0 && byt == 1'b0) empty <= 1'b1;
else if (empty == 1'b1 && byt == 1'b0) empty <= 1'b0;
always @(posedge Clk)
if (start)
if (empty == 1'b0 && byt == 1'b0) DB_reg <= DB[3 : 0];
else if (empty == 1'b1 && byt == 1'b1) DB_reg <= DB[3 : 0];
always @(*)
if (start)
if (empty == 1'b0)
if (byt == 1'b1) begin
Out = DB;
Out_en = 1'b1;
end else begin
Out = 'bx;
Out_en = 1'b0;
end
else if (byt == 1'b1) begin
Out = {DB_reg, DB[7:4]};
Out_en = 1'b1;
end else begin
Out = {DB_reg, DB[3:0]};
Out_en = 1'b1;
end
else begin
Out = DB;
Out_en = 1'b0;
end
endmodule
| 6.755404 |
module main;
// Model a pin with a weak keeper circuit. The way this works:
// If the pin value is 1, then attach a weak1 pullup, but
// if the pin value is 0, attach a weak0 pulldown.
wire pin;
pullup (weak1) (keep1);
pulldown (weak0) (keep0);
tranif1 (pin, keep1, pin);
tranif0 (pin, keep0, pin);
// Logic to drive a value onto a pin.
reg value, enable;
bufif1 (pin, value, enable);
initial begin
value = 0;
enable = 1;
#1
if (pin !== 0) begin
$display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin);
$finish;
end
// pin should hold its value after the drive is removed.
enable = 0;
#1
if (pin !== 0) begin
$display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin);
$finish;
end
value = 1;
enable = 1;
#1
if (pin !== 1) begin
$display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin);
$finish;
end
// pin should hold its value after the drive is removed.
enable = 0;
#1
if (pin !== 1) begin
$display("FAILED -- value=%b, enable=%b, pin=%b", value, enable, pin);
$finish;
end
$display("PASSED");
end
endmodule
| 6.7632 |
module Trans (
input clk,
reset,
transmitir,
bandera,
output reg salidaTx,
input [7:0] entradaSw
);
reg [5:0] estado;
always @(posedge clk, posedge reset) begin
if (reset) begin
estado <= 0;
salidaTx <= 1;
end else
case (estado)
0: begin
if (transmitir | bandera) begin
salidaTx <= 0; //Start bit
estado <= 1; //Siguiente estado
end else begin
estado <= 0; //regresamos al estado 0
salidaTx <= 1; //continuamos high
end
end
1: begin
salidaTx <= entradaSw[0]; //mandamos primer bit
estado <= 2; //nos vamos al estado 2
end
2: begin
salidaTx <= entradaSw[1];
estado <= 3; //nos vamos al estado 3
end
3: begin
salidaTx <= entradaSw[2];
estado <= 4; //nos vamos al estado 4
end
4: begin
salidaTx <= entradaSw[3];
estado <= 5; //nos vamos al estado 5
end
5: begin
salidaTx <= entradaSw[4];
estado <= 6; //nos vamos al estado 6
end
6: begin
salidaTx <= entradaSw[5];
estado <= 7; //nos vamos al estado 7
end
7: begin
salidaTx <= entradaSw[6];
estado <= 8; //nos vamos al estado 8
end
8: begin
salidaTx <= entradaSw[7];
estado <= 9; //nos vamos al estado 9
end
9: begin
salidaTx <= 0; //Bit vaquero de paridad. FIERRO
estado <= 10;
end
10: begin
salidaTx <= 1; //Stop Bit
estado <= 11; //Estado 0 vaquero
end
90: begin
estado <= 0;
end
default: estado <= estado + 1; //mandalo al estado 0 vaquero por cualquier cosirijilla
endcase
end
endmodule
| 6.577126 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.