code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Trans24To12 (
Hour24,
ncr,
Hour12
);
input [7:0] Hour24;
input ncr;
output reg [7:0] Hour12;
always @(Hour24) begin
if (!ncr) Hour12 = 8'b0000_0000;
else if (Hour24 < 8'd19) Hour12 = Hour24;
else
case (Hour24)
/*
8'b0000_0000:{HexH,HexL} <= 8'b0000_0000;
8'b0000_0001:{HexH,HexL} <= 8'b0000_0001;
8'b0000_0010:{HexH,HexL} <= 8'b0000_0010;
8'b0000_0011:{HexH,HexL} <= 8'b0000_0011;
8'b0000_0100:{HexH,HexL} <= 8'b0000_0100;
8'b0000_0101:{HexH,HexL} <= 8'b0000_0101;
8'b0000_0110:{HexH,HexL} <= 8'b0000_0110;
8'b0000_0111:{HexH,HexL} <= 8'b0000_0111;
8'b0000_1000:{HexH,HexL} <= 8'b0000_1000;
8'b0000_1001:{HexH,HexL} <= 8'b0000_1001;
8'b0001_0000:{HexH,HexL} <= 8'b0001_0000;
8'b0001_0001:{HexH,HexL} <= 8'b0001_0001;
8'b0001_0010:{HexH,HexL} <= 8'b0001_0010;
*/
8'b0001_0011: Hour12 = 8'b0000_0001;
8'b0001_0100: Hour12 = 8'b0000_0010;
8'b0001_0101: Hour12 = 8'b0000_0011;
8'b0001_0110: Hour12 = 8'b0000_0100;
8'b0001_0111: Hour12 = 8'b0000_0101;
8'b0001_1000: Hour12 = 8'b0000_0110;
8'b0001_1001: Hour12 = 8'b0000_0111;
8'b0010_0000: Hour12 = 8'b0000_1000;
8'b0010_0001: Hour12 = 8'b0000_1001;
8'b0010_0010: Hour12 = 8'b0001_0000;
8'b0010_0011: Hour12 = 8'b0001_0001;
8'b0010_0100: Hour12 = 8'b0001_0010;
endcase
end
endmodule
| 7.444021 |
module trans8to1 (
rst_n,
indata_8,
outdata_P,
outdata_N,
clk
);
input rst_n, clk;
input [7:0] indata_8;
output outdata_P, outdata_N;
reg outdata_P, outdata_N;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// 复位初始化
outdata_P <= 0;
outdata_N <= 0;
end else begin
// 三个区间分别对应三种双极性P和N的值来表示+1、0和-1
if (indata_8 >= 8'h58) begin
outdata_P <= 1;
outdata_N <= 0;
end else if (indata_8 <= 8'h3f && indata_8 >= 8'h30) begin
outdata_P <= 0;
outdata_N <= 0;
end else if (indata_8 <= 8'h0f) begin
outdata_P <= 0;
outdata_N <= 1;
end
end
end
endmodule
| 8.168136 |
module TransactionProb (
CLK,
Reset,
Push_fifos,
VC_ID,
DataWord,
Th_L,
Th_H,
Selector,
Matrix,
Weight,
Pop_CF,
Pop_buffer,
Set_init,
Idle,
Pause_stb,
Continue_stb,
Error_full
);
input Idle;
input [3:0] Pause_stb, Continue_stb, Error_full;
output reg CLK, Reset, Set_init, Pop_buffer, Pop_CF, Push_fifos;
output reg [1:0] VC_ID, Weight, Selector;
output reg [3:0] DataWord;
output reg [6:0] Th_L, Th_H;
output reg [31:0] Matrix;
reg transmitter;
initial begin
$dumpfile("Transmitter.vcd");
$dumpvars;
VC_ID <= 2'b00;
DataWord <= 4'b1010;
Pop_CF <= 0;
Pop_buffer <= 0;
CLK <= 0;
Reset <= 0;
Set_init <= 1;
Th_H <= 7'd75;
Th_L <= 7'd25;
Matrix <= 32'b10110001100111100110111110010010;
;
Selector <= 2'b01;
Weight <= 2'b00;
#30 @(posedge CLK);
Reset <= 1;
#10 @(posedge CLK);
Set_init <= 0;
#30 @(posedge CLK);
transmitter <= 0;
Push_fifos <= 1;
VC_ID <= 2'b00;
DataWord <= 4'd0;
#20 @(posedge CLK);
VC_ID <= 2'b00;
DataWord <= 4'd1;
#20 @(posedge CLK);
VC_ID <= 2'b00;
DataWord <= 4'd2;
#20 @(posedge CLK);
VC_ID <= 2'b01;
DataWord <= 4'd3;
#20 @(posedge CLK);
VC_ID <= 2'b01;
DataWord <= 4'd4;
#20 @(posedge CLK);
VC_ID <= 2'b10;
DataWord <= 4'd5;
#20 @(posedge CLK);
VC_ID <= 2'b10;
DataWord <= 4'd6;
#20 @(posedge CLK);
VC_ID <= 2'b11;
DataWord <= 4'd7;
#20 @(posedge CLK);
VC_ID <= 2'b10;
DataWord <= 4'd8;
#20 @(posedge CLK);
VC_ID <= 2'b01;
DataWord <= 4'd9;
#20 @(posedge CLK);
VC_ID <= 2'b11;
DataWord <= 4'd10;
#20 @(posedge CLK);
VC_ID <= 2'b11;
DataWord <= 4'd11;
#20 @(posedge CLK);
VC_ID <= 2'b11;
DataWord <= 4'd12;
#20 @(posedge CLK);
VC_ID <= 2'b00;
DataWord <= 4'd13;
#20 @(posedge CLK);
VC_ID <= 2'b00;
DataWord <= 4'd14;
#20 @(posedge CLK);
VC_ID <= 2'b01;
DataWord <= 4'd15;
#20 @(posedge CLK);
VC_ID <= 2'b10;
DataWord <= 4'd12;
#20 @(posedge CLK);
VC_ID <= 2'b10;
DataWord <= 4'd13;
#20 @(posedge CLK);
VC_ID <= 2'b11;
DataWord <= 4'd15;
Pop_CF <= 1;
#20 @(posedge CLK);
VC_ID <= 2'b01;
DataWord <= 4'd11;
#20 @(posedge CLK);
transmitter <= 1;
Pop_buffer <= 1;
#40 @(posedge CLK);
Pop_buffer <= 0;
#20 @(posedge CLK);
Pop_buffer <= 1;
#40 @(posedge CLK);
Pop_buffer <= 0;
#40 @(posedge CLK);
Pop_buffer <= 1;
#40 @(posedge CLK);
Pop_buffer <= 0;
#10 @(posedge CLK);
Pop_buffer <= 1;
#40 @(posedge CLK);
Pop_buffer <= 0;
#30 @(posedge CLK);
Pop_buffer <= 1;
#40 @(posedge CLK);
Pop_buffer <= 0;
#30 $finish;
end
always begin
#10 CLK <= ~CLK;
end
// always @(Set_init)
// begin
// if(!Set_init)
// begin
// Push_fifos <= 1;
// VC_ID <= 2'd3;
// transmitter <= 1;
// DataWord <= 4'b1001;
// end
// end
always @(posedge CLK) begin
if (transmitter) begin
if (DataWord >= 4'b1111) begin
DataWord <= 4'b0000;
end else begin
DataWord <= DataWord + 3;
end
if (|Continue_stb) begin
if (Continue_stb[0] == 1) begin
VC_ID <= 0;
end else if (Continue_stb[1] == 1) begin
VC_ID <= 1;
end else if (Continue_stb[2] == 1) begin
VC_ID <= 2;
end else if (Continue_stb[3] == 1) begin
VC_ID <= 3;
end
end else begin
if (VC_ID >= 2'b11) begin
VC_ID <= 2'b00;
end else begin
VC_ID <= VC_ID + 1;
end
if (Pause_stb[VC_ID] == 1) begin
Push_fifos <= 0;
end else begin
Push_fifos <= 1;
end
end
end
end
endmodule
| 6.71406 |
module transaction_fifo_dist (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
overflow,
prog_full,
underflow
);
input [32 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [32 : 0] dout;
output empty;
output full;
output overflow;
output prog_full;
output underflow;
// synthesis translate_off
FIFO_GENERATOR_V4_4 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(33),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(33),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex5"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(1),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(1),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(14),
.C_PROG_FULL_THRESH_NEGATE_VAL(13),
.C_PROG_FULL_TYPE(1),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.OVERFLOW(overflow),
.PROG_FULL(prog_full),
.UNDERFLOW(underflow),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.PROG_EMPTY(),
.VALID(),
.RD_DATA_COUNT(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 6.726982 |
module \$paramod\fifo_sint\MEM_SIZE=8\WORD_SIZE=12\PTR=3 (
clk,
reset,
fifo_wr,
fifo_rd,
full_threshold,
empty_threshold,
fifo_data_in,
error,
almost_empty,
almost_full,
fifo_full,
fifo_empty,
fifo_data_out
);
(* src = "fifo.v:23" *)
output almost_empty;
(* src = "fifo.v:24" *)
output almost_full;
(* src = "fifo.v:15" *)
input clk;
(* src = "fifo.v:30" *)
wire [11:0] data_out_MM;
(* src = "fifo.v:20" *)
input [2:0] empty_threshold;
(* src = "fifo.v:22" *)
output error;
(* src = "fifo.v:21" *)
input [11:0] fifo_data_in;
(* src = "fifo.v:27" *)
output [11:0] fifo_data_out;
(* src = "fifo.v:26" *)
output fifo_empty;
(* src = "fifo.v:25" *)
output fifo_full;
(* src = "fifo.v:18" *)
input fifo_rd;
(* src = "fifo.v:17" *)
input fifo_wr;
(* src = "fifo.v:19" *)
input [2:0] full_threshold;
(* src = "fifo.v:31" *)
wire pop;
(* src = "fifo.v:32" *)
wire push;
(* src = "fifo.v:33" *)
wire [2:0] rd_ptr;
(* src = "fifo.v:16" *)
input reset;
(* src = "fifo.v:34" *)
wire [2:0] wr_ptr;
(* src = "fifo.v:58" *)
\$paramod\control_logic_sint\MEM_SIZE=8\WORD_SIZE=12\PTR=3 control_log (
.almost_empty(almost_empty),
.almost_full(almost_full),
.clk(clk),
.empty_threshold(empty_threshold),
.error(error),
.fifo_empty(fifo_empty),
.fifo_full(fifo_full),
.fifo_rd(fifo_rd),
.fifo_wr(fifo_wr),
.full_threshold(full_threshold),
.reset(reset)
);
(* src = "fifo.v:73" *)
\$paramod\memory_sint\MEM_SIZE=8\WORD_SIZE=12\PTR=3 memoria (
.clk(clk),
.data_in_MM(fifo_data_in),
.data_out_MM(data_out_MM),
.pop(pop),
.push(push),
.rd_ptr(rd_ptr),
.reset(reset),
.wr_ptr(wr_ptr)
);
(* src = "fifo.v:47" *)
\$paramod\read_logic_sint\MEM_SIZE=8\WORD_SIZE=12\PTR=3 read_log (
.clk(clk),
.fifo_empty(fifo_empty),
.fifo_rd(fifo_rd),
.fifo_wr(fifo_wr),
.pop(pop),
.rd_ptr(rd_ptr),
.reset(reset)
);
(* src = "fifo.v:36" *)
\$paramod\writed_logic_sint\MEM_SIZE=8\WORD_SIZE=12\PTR=3 write_log (
.clk(clk),
.fifo_full(fifo_full),
.fifo_rd(fifo_rd),
.fifo_wr(fifo_wr),
.push(push),
.reset(reset),
.wr_ptr(wr_ptr)
);
assign fifo_data_out = data_out_MM;
endmodule
| 7.480712 |
module transceiver_clock (
input wire clk,
output wire sysclk_in,
output wire gt0_cplllockdetclk_in,
output wire gt0_drpclk_in,
input wire gt0_rxoutclk_out,
output wire gt0_rxusrclk_in,
output wire gt0_rxusrclk2_in,
input wire gt0_txoutclk_out,
output wire gt0_txusrclk_in,
output wire gt0_txusrclk2_in,
output wire gt0_gtrefclk0_in,
output wire gt0_gtrefclk1_in,
output wire gt0_qplloutclk_in,
output wire gt0_qplloutrefclk_in
);
reg clk0 = 0;
always #(6.667 / 2) clk0 = ~clk0;
reg clk1 = 0;
always #(16.667 / 2) clk1 = ~clk1;
assign gt0_cplllockdetclk_in = clk1;
assign gt0_drpclk_in = clk1;
assign sysclk_in = clk1;
assign gt0_rxusrclk_in = gt0_rxoutclk_out;
assign gt0_rxusrclk2_in = gt0_rxoutclk_out;
assign gt0_txusrclk_in = gt0_txoutclk_out;
assign gt0_txusrclk2_in = gt0_txoutclk_out;
assign gt0_gtrefclk0_in = 0;
assign gt0_gtrefclk1_in = clk0;
assign gt0_qplloutclk_in = 1;
assign gt0_qplloutrefclk_in = 0;
endmodule
| 7.033493 |
module transceiver_config (
input wire clk,
input wire rst,
/*port*/
output soft_reset_tx_in, // 复位TX FSM并且启动TX初始化，高电平复位
output soft_reset_rx_in, // 复位RX FSM并且启动RX初始化，高电平复位
output dont_reset_on_data_error_in, // 设置为0时，如果检测到错误，RX自动复位
output gt0_data_valid_in, // 此信号有效后，gt0_rx_fsm_reset_done_out才会有效, RX部分初始化才算完成
output gt0_cpllreset_in, // 高电平复位
output [ 8:0] gt0_drpaddr_in,
output [15:0] gt0_drpdi_in,
output gt0_drpen_in,
output gt0_drpwe_in,
output gt0_eyescanreset_in,
output gt0_rxuserrdy_in, // RXUSRCLK和RXUSRCLK2稳定后，置高该信号
output gt0_eyescantrigger_in,
output gt0_rxcdrhold_in,
output gt0_rxdfelpmreset_in, // LPM和DFE复位
output [ 1:0] gt0_rxmonitorsel_in,
output gt0_gtrxreset_in,
output gt0_rxpmareset_in,
output gt0_rxslide_in,
output gt0_gttxreset_in,
output gt0_txuserrdy_in,
output gt0_txelecidle_in,
output gt0_txcominit_in,
output gt0_txcomsas_in,
output gt0_txcomwake_in
);
assign soft_reset_tx_in = 0;
assign soft_reset_rx_in = 0;
assign dont_reset_on_data_error_in = 0;
assign gt0_cpllreset_in = 0;
assign gt0_drpaddr_in = 8'h00;
assign gt0_drpdi_in = 16'h0000;
assign gt0_drpen_in = 0;
assign gt0_drpwe_in = 0;
assign gt0_eyescanreset_in = 0;
assign gt0_rxuserrdy_in = 1;
assign gt0_eyescantrigger_in = 0;
assign gt0_rxcdrhold_in = 0;
assign gt0_rxdfelpmreset_in = 0;
assign gt0_rxmonitorsel_in = 0;
assign gt0_gtrxreset_in = 0;
assign gt0_rxpmareset_in = 0;
assign gt0_rxslide_in = 0;
assign gt0_gttxreset_in = 0;
assign gt0_txuserrdy_in = 1;
assign gt0_txelecidle_in = 0;
assign gt0_txcominit_in = 0;
assign gt0_txcomsas_in = 0;
assign gt0_txcomwake_in = 0;
initial begin
force gt0_data_valid_in = 0;
#58107;
force gt0_data_valid_in = 1;
end
endmodule
| 7.033493 |
module is an intermediate for two entities communicating through a two
// phase handshake. Signals with postfix 1 belong to the channel with the
// sending entity (i.e. req1 asks the module to transmit data1) and those with
// postfix 2 belong to the channel with the receiving entity (i.e. req2
// initiates a handshake with the item in data2).
module transceiver_dummy (clk, reset, req1, ack1, data1, req2, ack2, data2);
parameter ID = -1; // parent router id
parameter PORT = "unknown";
parameter SIZE = 8;
input clk, reset;
// router-side port:
input req1;
input [SIZE-1:0] data1;
output ack1;
// remote rx port:
output req2;
output [SIZE-1:0] data2;
input ack2;
assign req2 = req1;
assign ack1 = ack2;
assign data2 = data1;
endmodule
| 6.745243 |
module transceiver_reset (
input reset,
input clk, //init clock
output reg transceiver_dis,
output reg gtp_rst,
output reg aurora_rst
);
reg [2:0] state;
localparam IDLE = 3'd0, RESET_DIS = 3'd1, WAIT_DIS = 3'd2, WAIT_GTP = 3'd3, WAIT_RST = 3'd4;
reg [23:0] dis_100ms;
reg [23:0] dis_300ms;
reg reset_dis_done;
reg wait_dis_done;
reg [7:0] gtp_reset_cnt;
reg wait_gtp_done;
reg [7:0] wait_rst_cnt;
reg wait_rst_done;
initial begin
dis_100ms <= 24'b0;
dis_300ms <= 24'b0;
reset_dis_done <= 1'b0;
wait_dis_done <= 1'b0;
gtp_reset_cnt <= 8'b0;
wait_gtp_done <= 1'b0;
wait_rst_cnt <= 8'b0;
wait_rst_done <= 1'b0;
end
always @(posedge clk) begin
if (reset) dis_100ms <= 24'b0;
else if (state == RESET_DIS) dis_100ms <= dis_100ms + 1'b1;
else dis_100ms <= dis_100ms;
end
always @(posedge clk) begin
if (reset) reset_dis_done <= 1'b0;
else reset_dis_done <= dis_100ms[22];
end
always @(posedge clk) begin
if (reset) dis_300ms <= 24'b0;
else if (state == WAIT_DIS) dis_300ms <= dis_300ms + 1'b1;
else dis_300ms <= dis_300ms;
end
always @(posedge clk) begin
if (reset) wait_dis_done <= 1'b0;
else wait_dis_done <= dis_300ms[23] & dis_300ms[22];
end
always @(posedge clk) begin
if (reset) gtp_reset_cnt <= 8'b0;
else if (state == WAIT_GTP) gtp_reset_cnt <= gtp_reset_cnt + 1'b1;
else gtp_reset_cnt <= gtp_reset_cnt;
end
always @(posedge clk) begin
if (reset) wait_gtp_done <= 1'b0;
else wait_gtp_done <= gtp_reset_cnt[7];
end
always @(posedge clk) begin
if (reset) wait_rst_cnt <= 8'b0;
else if (state == WAIT_RST) wait_rst_cnt <= wait_rst_cnt + 1'b1;
else wait_rst_cnt <= wait_rst_cnt;
end
always @(posedge clk) begin
if (reset) wait_rst_done <= 1'b0;
else wait_rst_done <= wait_rst_cnt[7];
end
initial begin
state <= IDLE;
end
always @(posedge clk) begin
if (reset) state <= RESET_DIS;
else begin
case (state)
RESET_DIS: begin
if (reset_dis_done) state <= WAIT_DIS;
else state <= state;
end
WAIT_DIS: begin
if (wait_dis_done) state <= WAIT_GTP;
else state <= state;
end
WAIT_GTP: begin
if (wait_gtp_done) state <= WAIT_RST;
else state <= state;
end
WAIT_RST: begin
if (wait_rst_done) state <= IDLE;
else state <= WAIT_RST;
end
IDLE: state <= IDLE;
default: state <= IDLE;
endcase
end
end
always @(posedge clk) begin
if (state == RESET_DIS) transceiver_dis <= 1'b1;
else transceiver_dis <= 1'b0;
end
always @(posedge clk) begin
if (state == RESET_DIS || state == WAIT_DIS || state == WAIT_GTP) gtp_rst <= 1'b1;
else gtp_rst <= 1'b0;
end
always @(posedge clk) begin
if (state != IDLE) aurora_rst <= 1'b1;
else aurora_rst <= 1'b0;
end
endmodule
| 7.389824 |
module transceiver_tb ();
localparam period = 4;
localparam max_test = 50;
localparam data_size = 4;
localparam addr_size = 1;
localparam ports_num = 4;
localparam bus_size = data_size + addr_size + 1;
localparam test_size = 3 + 2 * (ports_num + 1) + bus_size * (ports_num + 1) + bus_size;
reg clk_r;
// module connections
// input data
reg rst_t;
reg is_empty_t;
reg [ ports_num:0] out_w_t;
reg [ bus_size-1:0] data_i_t;
// output data
wire r_req_t;
wire [ ports_num:0] out_r_t;
wire [bus_size*(ports_num+1)-1:0] data_o_t;
// output expected data
reg r_req_exp;
reg [ ports_num:0] out_r_exp;
reg [bus_size*(ports_num+1)-1:0] data_o_exp;
transceiver #(
.DATA_SIZE(4),
.ADDR_SIZE(1),
.NODES_NUM(4)
) test_trans (
.clk (clk_r),
.a_rst (rst_t),
.empty (is_empty_t),
.out_w (out_w_t),
.data_i(data_i_t),
.r_req (r_req_t),
.out_r (out_r_t),
.data_o(data_o_t)
);
// clk generate
initial begin
clk_r = 1'b0;
forever #(period / 2) clk_r = ~clk_r;
end
// data load, indexes init
integer test_idx;
integer errors_num;
reg [test_size-1:0] test_data[max_test-1:0];
initial begin
test_idx = 0;
errors_num = 0;
$readmemb(`TESTFILE, test_data);
rst_t = 1'b1;
end
always @(posedge clk_r)
{rst_t, is_empty_t, out_w_t, data_i_t, r_req_exp, out_r_exp, data_o_exp} = test_data[test_idx];
always @(posedge clk_r) begin
#(period / 4); // waiting for changing
$display("%4d Output : state = %d, r_req = %b, out_r = %b, data_o = %b\n", test_idx,
test_trans.state, r_req_t, out_r_t, data_o_t);
if (r_req_exp !== r_req_t || out_r_exp !== out_r_t || data_o_exp !== data_o_t) begin
$display("Error, expected: r_req = %b, out_r = %b, data_o = %b\n", r_req_exp, out_r_exp,
data_o_exp);
errors_num = errors_num + 1;
end
test_idx = test_idx + 1;
if (test_idx == max_test || test_data[test_idx] === {test_size{1'bx}}) begin
$display("Finish: %d tests, %d errors\n", test_idx, errors_num);
$finish;
end
end
endmodule
| 7.788608 |
module transceiver_write (
input wire clk,
input wire rst,
/*port*/
input wire gtx_ready,
input wire s_axi_tvalid,
input wire s_axi_tlast,
output wire s_axi_tready,
input wire [31:00] s_axi_tdata,
/*
* gt0_txcharisk_in[0] 对应 gt0_txdata_in[07:00]
* gt0_txcharisk_in[1] 对应 gt0_txdata_in[15:08]
* gt0_txcharisk_in[2] 对应 gt0_txdata_in[23:16]
* gt0_txcharisk_in[3] 对应 gt0_txdata_in[31:24]
* 一般情况下，gt0_txdata_in[07:00]发送数据被8'BC(K28.5)时, gt0_txcharisk_in[0] = 1
*/
output reg [31:00] gt_txdata_in,
output reg [03:00] gt_txcharisk_in
);
assign s_axi_tready = gtx_ready;
always @(posedge clk) begin
if (rst) gt_txdata_in <= 0;
else if (s_axi_tready & s_axi_tvalid) gt_txdata_in <= s_axi_tdata;
else gt_txdata_in <= 0;
end
always @(posedge clk) begin
if (rst) gt_txcharisk_in <= 0;
else if (s_axi_tready & s_axi_tvalid) begin
if (s_axi_tdata[07:00] == 8'hBC) gt_txcharisk_in[0] <= 1;
else gt_txcharisk_in[0] <= 0;
if (s_axi_tdata[15:08] == 8'hBC) gt_txcharisk_in[1] <= 1;
else gt_txcharisk_in[1] <= 0;
if (s_axi_tdata[23:16] == 8'hBC) gt_txcharisk_in[2] <= 1;
else gt_txcharisk_in[2] <= 0;
if (s_axi_tdata[31:24] == 8'hBC) gt_txcharisk_in[3] <= 1;
else gt_txcharisk_in[3] <= 0;
end else gt_txcharisk_in <= 0;
end
endmodule
| 7.49117 |
module transceiver (
input wire Rx,
output wire Tx,
input wire start_Tx,
input wire clk,
input wire [7:0] data_in,
output wire [7:0] data_out,
output wire ready,
output wire [15:0] D_address,
output wire Rx_done,
output wire [15:0] LEDR,
output wire [7:0] LEDG,
output wire Tx_done,
input wire clear
);
wire tb;
wire wr_en;
reg en;
wire Rx_ready;
UART UART1 (
.data_in(data_in), //input data
.wr_en(wr_en), //enable tx
.clk(clk),
.Tx(Tx),
.Rx(Rx),
.Tx_busy(tb),
.Rx_ready(Rx_ready), //originally rx_ready
.data_out(data_out)
);
reg busy;
reg status1;
reg status2;
reg status3;
reg [2:0] counter;
reg [2:0] counter2;
reg ready1;
reg ready2;
//wire ready;
reg [15:0] W_address;
reg [15:0] R_address;
assign D_address = status2 ? R_address : W_address;
assign Rx_done = status2;
assign wr_en = en;
assign LEDR = D_address;
assign LEDG = data_out;
assign ready = (~ready2) && ready1;
assign Tx_done = status3;
initial begin
//full=0;
status1 = 0;
status2 = 0;
status3 = 0;
W_address = 0;
R_address = 0;
en = 1;
counter = 0;
counter2 = 0;
end
always@(posedge ready)//originally rx_ready
begin
if (~status1 && ~status2) begin
counter = counter + 1;
if (counter == 2) status1 = 1;
end else if (status1 && ~status2 && W_address < 65535) W_address = W_address + 1;
if(W_address==65535)//5
begin
counter = counter + 1;
if (counter == 4) begin
status2 = 1;
W_address = 0;
end
end
end
always @(posedge clk) begin
busy = tb;
ready1 <= Rx_ready;
ready2 <= ready1;
if (start_Tx && status2 && ~busy && R_address < 65535 && counter2 < 2) begin
en = 0;
counter2 = counter2 + 1;
end else if (start_Tx && status2 && ~busy && R_address < 65535 && counter2 == 2) begin
R_address = R_address + 1;
en = 0;
end else if (R_address == 65535 && status2 && ~busy) begin
counter2 = counter2 + 1;
if (counter2 == 4) begin
status3 = 1;
en = 1;
end
end
end
endmodule
| 7.048036 |
module transcoderDirect (
input F1,
input F0,
input en,
output reg [6:0] led_out
);
always @(*) begin
if (!en) led_out = 7'b0000000;
else begin
case ({
F1, F0
})
2'b00: led_out = 7'b0000001; //stay
2'b01: led_out = 7'b0011100; //up
2'b10: led_out = 7'b1100010; //down
default: led_out = 7'b0000001; //stay
endcase
end
end
endmodule
| 6.935652 |
module Transcoder (
output reg [15:0] out,
input [3:0] in
);
always @(*) begin
case (in)
4'd0: out[15:0] = 16'b0000000000000000;
4'd1: out[15:0] = 16'b0000000000000010;
4'd2: out[15:0] = 16'b0000000000000100;
4'd3: out[15:0] = 16'b0000000000001000;
4'd4: out[15:0] = 16'b0000000000010000;
4'd5: out[15:0] = 16'b0000000000100000;
4'd6: out[15:0] = 16'b0000000001000000;
4'd7: out[15:0] = 16'b0000000010000000;
4'd8: out[15:0] = 16'b0000000100000000;
4'd9: out[15:0] = 16'b0000001000000000;
4'hA: out[15:0] = 16'b0000010000000000;
4'hB: out[15:0] = 16'b0000100000000000;
4'hC: out[15:0] = 16'b0001000000000000;
4'hD: out[15:0] = 16'b0010000000000000;
4'hE: out[15:0] = 16'b0100000000000000;
4'hF: out[15:0] = 16'b1111111111111111;
endcase
end
endmodule
| 6.677228 |
module transcodor (
input [3:0] data_in,
output reg [6:0] data_out
);
always @(*)
case (data_in)
8'h0: data_out = 7'b1000000;
8'h1: data_out = 7'b1111001;
8'h2: data_out = 7'b0100100; //2
8'h3: data_out = 7'b0110000;
8'h4: data_out = 7'b0011001;
8'h5: data_out = 7'b0010010;
8'h6: data_out = 7'b0000010;
8'h7: data_out = 7'b1111000;
8'h8: data_out = 7'b0000000;
8'h9: data_out = 7'b0010000;
8'hA: data_out = 7'b0001000;
8'hB: data_out = 7'b0000011; //B
8'hC: data_out = 7'b1000110;
8'hD: data_out = 7'b0100001;
8'hE: data_out = 7'b0000110;
8'hF: data_out = 7'b0001110;
default: data_out = 7'b1111111;
endcase
endmodule
| 6.849279 |
module transc_uart (
input clk, //Main clk input (50 MHz)
input rx, //Rx input of UART comunication
output tx, //Tx input of UART comunication
//Actual baudrate does not matter since both devices FPGAs
//... are using the same code, hence same baudrate.
input [7:0] dataIn, //Data to be transmitted
output [7:0] dataOut, //To display received data
output motor //Motor to be activated when receive command.
);
wire baud;
BaudGen BG_U0 ( //Generates a baudrate of 8*Desired_BaudRate
.clk (clk),
.baud(baud)
);
reg [11:0] div = 12'h0; //Used for both as a divisor to generate a baudrate ...
//... for transmision and a delay between transmisions.
wire tx_baud;
always @(posedge baud) div <= div + 1;
assign tx_baud = div[1]; //baudrate for transmision (2 times Desired_BaudRate) .
uart_tx uartTx_U0 ( //Transmitter module.
.clk(tx_baud), //Works @ 2*Desired_BaudRate
.data(dataIn), //Data to be transmitted
.start(div[11]), //A pulse is needed to command it to transmit
.tx(tx)
);
uart_rx uartRx_U0 ( //Receiver mocule
.clk(baud), //Works @ 8*Desired_BaudRate
.rx(rx),
.dataR(dataOut) //Received data
);
assign motor = dataOut[7]; //MSB of received data drives external motor.
endmodule
| 7.224786 |
module transferencia (
Permiso_Transf,
Data_Transfer_Direction_Select,
DAT_LEN,
DAT_ADR,
transferencia_finalizada
);
parameter WAIT = 4'b0001; //DirecciónTransferencia
parameter CARD_TO_HOST = 4'b0010;
parameter HOST_TO_CARD = 4'b0100;
input Permiso_Transf;
input Data_Transfer_Direction_Select;
input [15:0] DAT_LEN;
input [63:0] DAT_ADR;
output transferencia_finalizada;
wire Permiso_Transf;
wire Data_Transfer_Direction_Select;
wire [15:0] DAT_LEN;
wire [63:0] DAT_ADR;
reg transferencia_finalizada = 0;
reg [15:0] transfer_data_length = 0;
always @(*) begin
if (transfer_data_length == DAT_LEN) begin
transferencia_finalizada <= 1;
end else begin
transferencia_finalizada <= transferencia_finalizada;
end
end
endmodule
| 7.725215 |
module TransferFunction (
input wire clk_in,
input wire rst_in,
input wire cmd_trig_in,
input wire [15:0] cmd_addr_in,
input wire [15:0] cmd_data1_in,
input wire [15:0] cmd_data2_in,
output reg signed [15:0] sin_out,
output reg signed [15:0] cos_out,
output reg signed [23:0] mod0_out,
output reg signed [23:0] mod1_out,
output reg signed [23:0] mod2_out
);
// Latch the input commands
reg [31:0] pinc_f;
reg [4:0] rs0_f, rs1_f, rs2_f;
always @(posedge clk_in) begin
if (rst_in) begin
pinc_f <= 32'b0;
rs0_f <= 5'b11111;
rs1_f <= 5'b11111;
rs2_f <= 5'b11111;
end else begin
if (cmd_trig_in & (cmd_addr_in[15:12] == 4'h4)) begin
case (cmd_addr_in[11:0])
12'h000: begin
pinc_f <= {cmd_data2_in, cmd_data1_in};
end
12'h100: begin
rs0_f <= cmd_data1_in[4:0];
end
12'h101: begin
rs1_f <= cmd_data1_in[4:0];
end
12'h102: begin
rs2_f <= cmd_data1_in[4:0];
end
endcase
end
end
end
// DDS
wire signed [23:0] MODsin, MODcos;
dds_pw32_ow24 transfer_dds_inst (
.clk(clk_in),
.pinc_in(pinc_f),
.sine(MODsin),
.cosine(MODcos)
);
always @(posedge clk_in) sin_out <= (MODsin >>> 8);
always @(posedge clk_in) cos_out <= (MODcos >>> 8);
// right shift
always @(posedge clk_in) mod0_out <= (MODsin >>> rs0_f);
always @(posedge clk_in) mod1_out <= (MODsin >>> rs1_f);
always @(posedge clk_in) mod2_out <= (MODsin >>> rs2_f);
endmodule
| 8.345457 |
module transferstb (
i_src_clk,
i_dest_clk,
i_stb,
o_stb
);
input wire i_src_clk, i_dest_clk, i_stb;
output reg o_stb;
// Generate a sticky flip-flop
reg lcl_stb, lcl_ack;
initial lcl_stb = 1'b0;
always @(posedge i_src_clk)
if (i_stb) lcl_stb <= 1'b1;
else if (lcl_ack) lcl_stb <= 1'b0;
// Transfer this sticky flip-flop
reg [2:0] tfr_stb;
initial tfr_stb = 3'h0;
always @(posedge i_dest_clk) tfr_stb <= {tfr_stb[1:0], lcl_stb};
always @(posedge i_dest_clk) o_stb <= (!tfr_stb[2]) && (tfr_stb[1]);
// Create an acknowledgement for the return trip
reg [1:0] tfr_ack;
initial tfr_ack = 2'h0;
always @(posedge i_src_clk) tfr_ack <= {tfr_ack[0], (tfr_stb[2])};
initial lcl_ack = 1'b0;
always @(posedge i_src_clk) lcl_ack <= tfr_ack[1];
endmodule
| 6.552857 |
module TipoDeTransferencia (
Multi_Single_Block_Select,
Block_Count_Enable,
Transfer_Type
);
input Multi_Single_Block_Select;
input Block_Count_Enable;
output [1:0] Transfer_Type;
wire Multi_Single_Block_Select;
wire Block_Count_Enable;
reg [1:0] Transfer_Type;
reg [1:0] Temporal;
parameter Single_Transfer = 2'b00;
parameter Infinite_Transfer = 2'b01;
parameter Multiple_Transfer = 2'b10;
parameter Stop_Multiple_Transfer = 2'b11;
always @(*) begin
Temporal[1] <= Multi_Single_Block_Select;
Temporal[0] <= Block_Count_Enable;
case (Temporal)
2'b00: begin
Transfer_Type <= Single_Transfer;
end
2'b01: begin
Transfer_Type <= Single_Transfer;
end
2'b10: begin
Transfer_Type <= Infinite_Transfer;
end
2'b11: begin
if (Block_Count_Enable == 0) begin
Transfer_Type <= Stop_Multiple_Transfer;
end else begin
Transfer_Type <= Multiple_Transfer;
end
end
//default:
//definir
endcase
end
endmodule
| 8.032533 |
module Transfer_Data_Module #(
parameter Data = 32
) (
input wire [Data-1:0] command,
output wire Reg_fifo_In_Core1,
output wire [1:0] Data_A_B_Core1,
output wire [2:0] Addr_Reg_Core1_A,
output wire [2:0] Addr_Reg_Core1_B,
output wire Msb_A_Core1,
output wire [1:0] command_Core1,
output wire Reg_fifo_In_Core2,
output wire Mul_Msb,
output wire [2:0] Addr_Reg_B,
output wire [1:0] command_Core2,
output wire Transfer_Cmd,
output wire Transfer_Fifo_Out_Core1,
output wire [2:0] Addr_Fifo_Out_Core1,
output wire Transfer_Fifo_Out_Core2,
output wire [2:0] Addr_Fifo_Out_Core2
);
assign Reg_fifo_In_Core1 = command[0];
assign Data_A_B_Core1 = command[2:1];
assign Addr_Reg_Core1_A = command[5:3];
assign Addr_Reg_Core1_B = command[8:6];
assign Msb_A_Core1 = command[9];
assign command_Core1 = command[12:10];
assign Reg_fifo_In_Core2 = command[13];
assign Mul_Msb = command[14];
assign Addr_Reg_B = command[17:15];
assign command_Core2 = command[19:18];
assign Transfer_Fifo_Out_Core1 = command[20];
assign Addr_Fifo_Out_Core1 = command[23:21];
assign Transfer_Fifo_Out_Core2 = command[24];
assign Addr_Fifo_Out_Core1 = command[27:25];
endmodule
| 7.767255 |
module transform (
input clk,
input rst_n,
input en,
input [8:0] data_in,
input read,
output reg finish,
output reg [31:0] data_out
);
wire [31:0] data_out_r;
reg [ 1:0] state;
reg [ 1:0] next_state;
reg [23:0] data_to_trans;
reg [ 1:0] cnt;
localparam IDLE = 1;
localparam WORK = 2;
localparam WAIT = 3;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) state <= IDLE;
else state <= next_state;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt <= 0;
else if (state == WORK) begin
if (cnt < 3) cnt <= cnt + 1;
else cnt <= 0;
end
end
always @(*) begin
case (state)
IDLE: if (en) next_state <= WORK;
else next_state <= IDLE;
WORK: if (cnt == 3) next_state <= WAIT;
else next_state <= WORK;
WAIT: if (read) next_state <= IDLE;
else next_state <= WAIT;
endcase
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) finish <= 0;
else if (state == WORK) data_out <= data_out_r;
else if (state == WAIT) finish <= 1;
else if (state == IDLE) finish <= 0;
end
transform_base64 m0 (
clk,
rst_n,
data_in[23:0],
data_out_r[31:0]
);
endmodule
| 7.983857 |
module transformationPlusActivation #(
parameter dataWidth = 32,
parameter psys = 32,
parameter featureLen = 128,
parameter pactivation = 128,
parameter pavdd = 128,
parameter k = 1024
) (
clk,
rst,
enable,
// define port for weight buffer
weightWriteEnable,
weigthDataIn,
//define port for systolic array
//define the port for aggregation in
rowbuffer_address,
rowbuffer_dataOut,
//define the model
mode,
//
resultOut
);
input clk;
input rst;
input enable;
input weightWriteEnable;
input [dataWidth*psys -1 : 0] weigthDataIn;
input mode;
input [featureLen*dataWidth - 1:0] rowbuffer_dataOut;
output wire [psys*dataWidth - 1:0] resultOut;
wire [psys*dataWidth - 1:0] reluIn;
wire [psys*dataWidth - 1:0] reluOut;
wire [dataWidth*psys -1 : 0] weightBufferTosysArray;
reg [$clog2(k) - 1:0] rowAddressCounter;
output wire [$clog2(k) - 1:0] rowbuffer_address;
always @(posedge clk or negedge rst) begin : rowAddressCounter_r
if (~rst) begin
rowAddressCounter <= 0;
end else begin
rowAddressCounter <= rowAddressCounter + 1;
end
end
assign rowbuffer_address = rowAddressCounter;
parameter integer round = $floor(featureLen / psys);
wire [dataWidth*psys -1 : 0] sysin[0:round- 2];
wire [dataWidth*psys -1 : 0] sysDataOut;
genvar i;
generate
for (i = 0; i < round - 2; i = i + 1) begin : sysin_loop
if (i == 0) begin : round_r
assign sysin[i] = rowbuffer_dataOut[(i+1)*psys * dataWidth - 1: i*psys*dataWidth] & rowbuffer_dataOut[(i+2)*psys * dataWidth - 1: (i + 1)*psys*dataWidth];
end else begin : round_p
assign sysin[i] = sysin[i - 1] & rowbuffer_dataOut[(i+2)*psys * dataWidth - 1: (i + 1)*psys*dataWidth];
end
end
endgenerate
wire [dataWidth*psys -1 : 0] sysarrayIn;
assign sysarrayIn = (mode == 1'b0) ? sysin[round-2] : reluOut;
assign reluIn = (mode == 1'b0) ? sysDataOut : sysin[round-2];
assign resultOut = (mode == 1'b0) ? reluOut : sysDataOut;
sysArray #(
.dataWidth(dataWidth),
.SysDimension(psys),
.featureLen(featureLen)
) singlesysArray (
.clk (clk), // define the input clock
.rst (rst), // define the input reset
.enable (enable), // define the enable signal port
.weightArray (weightBufferTosysArray), // define the input weight array
.featureArray(sysarrayIn), // define the input feature array
.outputArray (sysDataOut) // define the output feature array
);
parameter weightBufferAddressWidth = $clog2(featureLen * featureLen / psys);
reg [weightBufferAddressWidth - 1:0] WeightAddr;
always @(posedge clk or negedge rst) begin : proc_WeightAddr
if (~rst) begin
WeightAddr <= 0;
end else begin
WeightAddr <= WeightAddr + 1;
end
end
weightBuffer #(
.dataWidth(dataWidth),
.featureLen(featureLen),
.psys(psys)
) singleWeightBuffer (
.clk(clk),
.rst(rst),
.enable(enable),
.writenable(weightWriteEnable),
.din(weigthDataIn),
.dout(weightBufferTosysArray),
.addr(WeightAddr)
);
reluArray #(
.dataWidth (dataWidth),
.pactivation(pactivation)
) singlereluArray (
.clk(clk),
.rst(rst),
.inputArray(reluIn),
.outputArray(reluOut)
);
endmodule
| 8.556904 |
module TransformFilter (
rst,
clk,
din,
clkdv,
dout
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟，频率为数据速率的16倍：64MHz
input signed [11:0] din; //输入数据：4MHz
output clkdv; //输出时钟：4MHz
output signed [15:0] dout; //滤波后的输出数据
wire [11:0] count16_256;
wire signed [15:0] dout_interlaced;
wire signed [15:0] xk_re, xk_im;
window u0 (
.rst(rst),
.clk(clk),
.din(din),
.clkdv(clkdv),
.count16_256(count16_256),
.dout_interlaced(dout_interlaced)
);
fftfilter u1 (
.rst (rst),
.clk (clk),
.din (dout_interlaced),
.addr (count16_256),
.xk_re(xk_re),
.xk_im(xk_im)
);
wire [15:0] douttem;
ifftout u2 (
.rst (rst),
.clk (clk),
.clkdv(clkdv),
.addr (count16_256),
.xk_re(xk_re),
.xk_im(xk_im),
.dout (dout)
);
endmodule
| 8.280168 |
modules in one
***********************************************************************/
module transform_aes (
/***** INPUT */
/***** DATA SIGNALS */
input wire clk,
input wire rst_n,
input wire [127:0] data_in,
input wire [127:0] key_in,
input wire [3:0] round_in,
/***** OUTPUT */
output wire [127:0] data_out,
output wire sub_ready_out,
output wire colmix_ready_out,
/***** CONTROL SIGNALS */
input wire en_de,
input wire sub_start_in,
input wire colmix_start_in,
input wire ark_en
);
//internal wire
wire [127:0] colmix_data_in;
wire [127:0] addroundkey_in;
top_subbyte subbyte_t (
.clk (clk),
.rst_n (rst_n),
.data_in (data_out),
.start_in (sub_start_in),
.en_de (en_de),
.data_out (colmix_data_in),
.ready_out (sub_start_in)
);
columnmix columnmix_t (
.clk (clk),
.rst_n (rst_n),
.data_in (colmix_data_in),
.data_out (addroundkey_in),
.ready_out (colmix_ready_out),
.start_in (colmix_start_in),
.en_de (en_de)
);
addroundkey addroundkey_t (
.ori_data_in (data_in),
.new_data_in (addroundkey_in),
.key_in (key_in),
.round_in (round_in),
.data_out (data_out),
.ark_en ()
);
endmodule
| 7.002497 |
module transform_base64 (
input clk,
input rst_n,
input [23:0] data_in,
output [31:0] data_out
);
reg [639:0] data_insert;
reg finish_flag;
wire [639:0] data_out_w;
assign data_out = (!rst_n) ? 0 : data_out_w;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_insert <= 630'b0;
end else
data_insert = {
2'b0, data_in[23:18], 2'b0, data_in[17:12], 2'b0, data_in[11:6], 2'b0, data_in[5:0]
};
end
rom_base64 rom_base64_inst0 (
.address(data_insert[7:0]),
.clock(clk),
.q(data_out_w[7:0])
);
rom_base64 rom_base64_inst1 (
.address(data_insert[15:8]),
.clock(clk),
.q(data_out_w[15:8])
);
rom_base64 rom_base64_inst2 (
.address(data_insert[23:16]),
.clock(clk),
.q(data_out_w[23:16])
);
rom_base64 rom_base64_inst3 (
.address(data_insert[31:24]),
.clock(clk),
.q(data_out_w[31:24])
);
endmodule
| 7.927402 |
module dequant_coeff_ram (
clk,
wr,
wr_addr,
rd_addr,
data_in,
data_out
);
parameter addr_bits = 6;
parameter data_bits = 39;
input clk;
input wr;
input [addr_bits-1:0] wr_addr;
input [addr_bits-1:0] rd_addr;
input [data_bits-1:0] data_in;
output [data_bits-1:0] data_out;
reg [data_bits-1:0] ram [0:(1 << addr_bits) -1];
reg [data_bits-1:0] data_out;
//read
always @(posedge clk) begin
data_out <= ram[rd_addr];
end
//write
always @(posedge clk) begin
if (wr) ram[wr_addr] <= data_in;
end
endmodule
| 7.112235 |
module transform_DC_regs (
input clk,
input rst_n,
input ena,
input clr,
input [3:0] residual_state,
input wr,
input [3:0] rd_idx,
input [15:0] data_in_0,
input [15:0] data_in_1,
input [15:0] data_in_2,
input [15:0] data_in_3,
input [15:0] data_in_4,
input [15:0] data_in_5,
input [15:0] data_in_6,
input [15:0] data_in_7,
input [15:0] data_in_8,
input [15:0] data_in_9,
input [15:0] data_in_10,
input [15:0] data_in_11,
input [15:0] data_in_12,
input [15:0] data_in_13,
input [15:0] data_in_14,
input [15:0] data_in_15,
output reg [15:0] data_out
);
//------------------
// FFs
//-----------------
reg [15:0] reg_0;
reg [15:0] reg_1;
reg [15:0] reg_2;
reg [15:0] reg_3;
reg [15:0] reg_4;
reg [15:0] reg_5;
reg [15:0] reg_6;
reg [15:0] reg_7;
reg [15:0] reg_8;
reg [15:0] reg_9;
reg [15:0] reg_10;
reg [15:0] reg_11;
reg [15:0] reg_12;
reg [15:0] reg_13;
reg [15:0] reg_14;
reg [15:0] reg_15;
reg [15:0] Cb_reg_0;
reg [15:0] Cb_reg_1;
reg [15:0] Cb_reg_2;
reg [15:0] Cb_reg_3;
reg [15:0] Cr_reg_0;
reg [15:0] Cr_reg_1;
reg [15:0] Cr_reg_2;
reg [15:0] Cr_reg_3;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
reg_0 <= 0;
reg_1 <= 0;
reg_2 <= 0;
reg_3 <= 0;
reg_4 <= 0;
reg_5 <= 0;
reg_6 <= 0;
reg_7 <= 0;
reg_8 <= 0;
reg_9 <= 0;
reg_10 <= 0;
reg_11 <= 0;
reg_12 <= 0;
reg_13 <= 0;
reg_14 <= 0;
reg_15 <= 0;
Cb_reg_0 <= 0;
Cb_reg_1 <= 0;
Cb_reg_2 <= 0;
Cb_reg_3 <= 0;
Cr_reg_0 <= 0;
Cr_reg_1 <= 0;
Cr_reg_2 <= 0;
Cr_reg_3 <= 0;
end else if (ena && clr) begin
reg_0 <= 0;
reg_1 <= 0;
reg_2 <= 0;
reg_3 <= 0;
reg_4 <= 0;
reg_5 <= 0;
reg_6 <= 0;
reg_7 <= 0;
reg_8 <= 0;
reg_9 <= 0;
reg_10 <= 0;
reg_11 <= 0;
reg_12 <= 0;
reg_13 <= 0;
reg_14 <= 0;
reg_15 <= 0;
Cb_reg_0 <= 0;
Cb_reg_1 <= 0;
Cb_reg_2 <= 0;
Cb_reg_3 <= 0;
Cr_reg_0 <= 0;
Cr_reg_1 <= 0;
Cr_reg_2 <= 0;
Cr_reg_3 <= 0;
end else if (ena && wr && residual_state == `Intra16x16DCLevel_s) begin
reg_0 <= data_in_0;
reg_1 <= data_in_1;
reg_4 <= data_in_2;
reg_5 <= data_in_3;
reg_2 <= data_in_4;
reg_3 <= data_in_5;
reg_6 <= data_in_6;
reg_7 <= data_in_7;
reg_8 <= data_in_8;
reg_9 <= data_in_9;
reg_12 <= data_in_10;
reg_13 <= data_in_11;
reg_10 <= data_in_12;
reg_11 <= data_in_13;
reg_14 <= data_in_14;
reg_15 <= data_in_15;
end else if (ena && wr && residual_state == `ChromaDCLevel_Cb_s) begin
Cb_reg_0 <= data_in_0;
Cb_reg_2 <= data_in_1;
Cb_reg_3 <= data_in_2;
Cb_reg_1 <= data_in_3;
end else if (ena && wr && residual_state == `ChromaDCLevel_Cr_s) begin
Cr_reg_0 <= data_in_0;
Cr_reg_2 <= data_in_1;
Cr_reg_3 <= data_in_2;
Cr_reg_1 <= data_in_3;
end
always @(posedge clk or negedge rst_n)
if (!rst_n) data_out <= 0;
else if(ena && (residual_state ==`Intra16x16ACLevel_s ||
residual_state == `Intra16x16ACLevel_0_s))//lumaAC
case (rd_idx)
0: data_out <= reg_0;
1: data_out <= reg_1;
2: data_out <= reg_2;
3: data_out <= reg_3;
4: data_out <= reg_4;
5: data_out <= reg_5;
6: data_out <= reg_6;
7: data_out <= reg_7;
8: data_out <= reg_8;
9: data_out <= reg_9;
10: data_out <= reg_10;
11: data_out <= reg_11;
12: data_out <= reg_12;
13: data_out <= reg_13;
14: data_out <= reg_14;
default: data_out <= reg_15;
endcase
else if (ena)
case (rd_idx)
0: data_out <= Cb_reg_0;
1: data_out <= Cb_reg_1;
2: data_out <= Cb_reg_2;
3: data_out <= Cb_reg_3;
4: data_out <= Cr_reg_0;
5: data_out <= Cr_reg_1;
6: data_out <= Cr_reg_2;
default: data_out <= Cr_reg_3;
endcase
endmodule
| 7.628693 |
module: transform_mapping
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module transform_test;
// Inputs
reg clk;
reg [10:0] sin_x;
reg [10:0] sin_y;
reg [10:0] x;
reg [10:0] y;
// Outputs
wire [10:0] x_out;
wire [10:0] y_out;
// Instantiate the Unit Under Test (UUT)
transform_mapping uut (
.clk(clk),
.sin_x(sin_x),
.sin_y(sin_y),
.x(x),
.y(y),
.x_out(x_out),
.y_out(y_out)
);
initial begin
// Initialize Inputs
clk = 0;
sin_x = -11'd2;
sin_y = -11'd2;
x = 11'd200;
y = 11'd200;
// Wait 100 ns for global reset to finish
#100;
forever begin
clk = ~clk;
#5;
end
// Add stimulus here
end
endmodule
| 6.859781 |
module transistor_vs_gate_testbench ();
reg aa1 = 0, bb1 = 0, ee0 = 0, gg0 = 0;
wire transistor_e1, transistor_g1, gate_e1, gate_g1;
mybcs UUT1 (
.a1(aa1),
.b1(bb1),
.e0(ee0),
.g0(gg0),
.e1(transistor_e1),
.g1(transistor_g1)
);
mybcs_gatelevel UUT2 (
.a1(aa1),
.b1(bb1),
.e0(ee0),
.g0(gg0),
.e1(gate_e1),
.g1(gate_g1)
);
initial begin
#100 aa1 = 0;
bb1 = 1;
ee0 = 1;
gg0 = 1; //worst delay
#1000 aa1 = 0;
bb1 = 0;
ee0 = 0;
gg0 = 0;
#1000 aa1 = 0;
bb1 = 0;
ee0 = 0;
gg0 = 1;
#1000 aa1 = 0;
bb1 = 0;
ee0 = 1;
gg0 = 0;
#1000 aa1 = 0;
bb1 = 0;
ee0 = 1;
gg0 = 1;
#1000 aa1 = 0;
bb1 = 1;
ee0 = 0;
gg0 = 0;
#1000 aa1 = 0;
bb1 = 1;
ee0 = 0;
gg0 = 1;
#1000 aa1 = 0;
bb1 = 1;
ee0 = 1;
gg0 = 0;
#1000 aa1 = 0;
bb1 = 1;
ee0 = 1;
gg0 = 1;
#1000 $stop;
end
endmodule
| 7.242624 |
module translate (
input clk,
inout [3:0] sw,
output [9:0] x_out
);
parameter START_X = 256;
reg [9:0] xx = START_X;
reg [31:0] counter = 1;
reg temp_clk = 0;
always @(posedge (clk)) begin
if (counter == 2500000) begin
counter <= 1;
temp_clk <= ~temp_clk;
end else counter <= counter + 1;
end
assign clk_out = temp_clk;
always @(posedge clk_out) begin
xx <= xx - sw;
end
assign x_out = xx;
endmodule
| 7.340418 |
module translate256x176 (
input [7:0] x,
input [7:0] y,
output reg [15:0] mem_address
);
always @(*) begin
mem_address = ({1'b0, y, 8'd0} + x);
end
endmodule
| 7.405835 |
module translateLinkSprite64x48 (
input [5:0] x,
input [5:0] y,
output reg [11:0] mem_address
);
always @(*) begin
mem_address = ({1'b0, y, 6'd0} + x);
end
endmodule
| 8.279386 |
module is to break the critical path on instruction
* address translation, since address translation using TLB introduces high
* combinatorial delay.
* This module uses the result of previous address translation to predict the
* translated address of current instruction reference.
*
* @author Yunye Pu
*/
module TranslatePredict(
input clk, input rst, input stall,
input [15:0] pageMask, input [31:0] pPCin,
input [31:0] vPC, output [31:0] pPCOut,
output flush
);
reg [15:0] pageMask_reg;
reg [31:0] pPC_reg;
reg [31:0] pPCPred_reg;
wire [31:0] pPCPredict;
assign pPCPredict[31:28] = pPC_reg[31:28];
assign pPCPredict[11:0] = vPC[11:0];
assign pPCPredict[27:12] = (pPC_reg[27:12] & ~pageMask_reg) | (vPC[27:12] & pageMask_reg);
assign pPCOut = flush? pPC_reg: pPCPredict;
assign flush = (pPC_reg != pPCPred_reg);
always @ (posedge clk)
begin
if(rst)
begin
pageMask_reg <= 16'hffff;
pPC_reg <= 32'h1fc00000;
pPCPred_reg <= 32'h1fc00000;
end
else if(~stall)
begin
pageMask_reg <= pageMask;
pPC_reg <= pPCin;
pPCPred_reg <= pPCPredict;
end
end
endmodule
| 7.55305 |
module translater (
input clk,
input reset,
input vm_enable,
input launch_translation,
output reg [31:0] physical_address,
input [31:0] virtual_address,
output translation_complete,
input [31:0] ptbr,
input flush_tlb,
/* memory interface */
output reg [31:0] translate_addr,
output translate_mem_enable,
input [31:0] request_data,
input translate_data_valid
);
wire [31:0] tlb_output_address;
wire tlb_hit;
wire translation_required;
localparam S_IDLE = 2'd0;
localparam S_TLB = 2'd1;
localparam S_TRAN_PPN1 = 2'd2;
localparam S_TRAN_PPN0 = 2'd3;
reg [31:0] address;
reg [ 1:0] state;
reg [ 1:0] next_state;
always @(posedge clk) begin
if (reset) state <= S_IDLE;
else state <= next_state;
end
always @(posedge clk) begin
if (reset) address <= 0;
else if (state == S_IDLE && launch_translation) address <= virtual_address;
end
always @(*) begin
case (state)
S_IDLE: next_state = launch_translation ? S_TLB : S_IDLE;
S_TLB:
if (tlb_hit) next_state = S_IDLE;
else if (translation_required) next_state = S_TRAN_PPN1;
else next_state = S_TLB;
S_TRAN_PPN1: next_state = translate_data_valid ? S_TRAN_PPN0 : S_TRAN_PPN1;
S_TRAN_PPN0: next_state = translate_data_valid ? S_IDLE : S_TRAN_PPN0;
default: next_state = S_IDLE;
endcase
end
reg [31:0] ppn1_data;
reg ppn1_valid;
reg [31:0] ppn0_data;
reg ppn0_valid;
always @(posedge clk) begin
if (reset) begin
ppn1_valid <= 0;
ppn1_data <= 0;
ppn0_valid <= 0;
ppn0_data <= 0;
end else begin
if (state == S_IDLE && launch_translation) begin
ppn1_valid <= 0;
ppn1_data <= 0;
ppn0_valid <= 0;
ppn0_data <= 0;
end else if (state == S_TRAN_PPN1 && translate_data_valid) begin
ppn1_data <= request_data;
ppn1_valid <= 1;
end else if (state == S_TRAN_PPN0 && translate_data_valid) begin
ppn0_data <= request_data;
ppn0_valid <= 1;
end
end
end
always @(*) begin
case (state)
S_TRAN_PPN1: translate_addr = {ptbr[31:12], address[31:22], 2'b0};
S_TRAN_PPN0: translate_addr = {ppn1_data[31:12], address[21:12], 2'b0};
default: translate_addr = 32'b0;
endcase
end
assign translate_mem_enable = (state == S_TRAN_PPN1) || (state == S_TRAN_PPN0);
assign translation_complete = (state == S_IDLE);
/* Latch inferred. */
always @(*) begin
if (translation_complete)
if (tlb_hit) physical_address = {tlb_output_address[31:12], address[11:0]};
else physical_address = {ppn0_data[31:12], address[11:0]};
end
/* TLB */
wire tlb_enable = (state == S_TLB);
tlb tlb (
.clk(clk),
.reset(reset),
.flush(flush_tlb),
.vm_enable(vm_enable),
.enable(tlb_enable),
.virtual_address(virtual_address),
.physical_address(tlb_output_address),
.tlb_hit(tlb_hit),
.translation_required(translation_required),
.translated_address(physical_address),
.translation_complete(translation_complete)
);
endmodule
| 6.769971 |
module translater_tb ();
wire ENB, clk, selector, selector3;
wire [6:0] in_1, in_2;
wire [31:0] in_3;
wire [6:0] out_1, out_2;
wire [31:0] out_3;
translater_p transp (
ENB,
clk,
in_1,
in_2,
in_3,
selector,
selector3
);
translater trans (
ENB,
clk,
in_1,
in_2,
in_3,
selector,
selector3,
out_1,
out_2,
out_3
);
initial begin
$dumpfile("translate.vcd");
$dumpvars;
end
endmodule
| 7.406074 |
module transmesconreg2 (
input wire clk,
input wire rst,
input wire cpu, // IOCPU, CPU wuenscht Zugriff
input wire can, // controller wuenscht Zugriff
input wire tsucf, // llc, successful transmission
input wire [15:0] reginp, // Register Bus (daten)
output reg [15:0] regout // generalregister
);
always @(posedge clk) begin
if (rst == 1'b0) begin
regout <= 16'd0; // synchroner Reset
end else if (cpu == 1'b1) begin // cpu schreibt
regout <= reginp;
end else if (can == 1'b1) begin // can schreibt nur
regout[15] <= 1'b0; // treq auf 0
regout[14] <= tsucf; // transmit indication (llc)
end
end
endmodule
| 7.406218 |
module Transmisor #(
parameter DBIT = 8, // #databits
SB_TICK = 16 // #ticks fors top bits
) (
input wire clk,
reset,
input wire tx_start,
s_tick,
input wire [7:0] din,
output reg TX_Done = 0,
output wire tx
);
// synlbolic s t a t e d e c l a r a t i o n
localparam [1:0] idle = 2'b00, start = 2'b01, data = 2'b10, stop = 2'b11;
// signal declaratio n
reg [1:0] state_reg = 0, state_next = 0;
reg [3:0] s_reg = 0, s_next = 0;
reg [2:0] n_reg = 0, n_next = 0;
reg [7:0] b_reg = 0, b_next = 0;
reg tx_reg = 1, tx_next = 1;
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset) begin
state_reg <= idle;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
tx_reg <= 1'b1;
end else begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end
// FSMD next_state logic&functional units
always @* begin
state_next = state_reg;
TX_Done = 1'b0;
s_next = s_reg;
n_next = n_reg;
b_next = b_reg;
tx_next = tx_reg;
case (state_reg)
idle: begin
tx_next = 1'b1;
if (tx_start) begin
state_next = start;
s_next = 0;
b_next = din;
end
end
start: begin
tx_next = 1'b0;
if (s_tick)
if (s_reg == 15) begin
state_next = data;
s_next = 0;
n_next = 0;
end else s_next = s_reg + 1;
end
data: begin
tx_next = b_reg[0];
if (s_tick)
if (s_reg == 15) begin
s_next = 0;
b_next = b_reg >> 1;
if (n_reg == (DBIT - 1)) state_next = stop;
else n_next = n_reg + 1;
end else s_next = s_reg + 1;
end
stop: begin
tx_next = 1'b1;
if (s_tick)
if (s_reg == (SB_TICK - 1)) begin
state_next = idle;
TX_Done = 1'b1;
end else s_next = s_reg + 1;
end
endcase
end
// output
assign tx = tx_reg;
endmodule
| 7.92361 |
module Transmisor_TX (
input RST,
CLK,
TX_Start,
input [7:0] DATAIN,
input s_tick,
output TX,
TX_Done
);
//wires
wire WTX_Start;
wire [7:0] WDATAIN;
UBuffer TX_Buffer (
.clk(CLK),
.rst(RST),
.r_data(TX_Start),
.datain(DATAIN),
.dataout(WDATAIN),
.ready(WTX_Start)
);
Transmisor TXTrasmisor (
.clk(CLK),
.reset(RST),
.tx_start(WTX_Start),
.s_tick(s_tick),
.din(WDATAIN),
.TX_Done(TX_Done),
.tx(TX)
);
endmodule
| 8.092115 |
module
//In this implementation, buffer reads out pixels to VGA controller
//Copyright (C) <2018> <James Williams>
////This program is free software: you can redistribute it and/or modify
////it under the terms of the GNU General Public License as published by
////Free Software Foundation, either version 3 of the License, or
////(at your option) any later version.
////This program is distributed in the hope that it will be useful,
////but WITHOUT ANY WARRANTY; without even the implied warranty of
////MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
////GNU General Public License for more details.
///You should have received a copy of the GNU General Public License
////along with this program. If not, see <https://www.gnu.org/licenses/>.
module tr_buff
#(
parameter addr_bus_size = 16,
parameter data_bus_size = 16
)
(
input clk,
input reset,
input ready,//From SRAM when data is ready
input [16:0] addr_in,//From VGA
input [(data_bus_size - 1):0] sram_data,
output [(addr_bus_size - 1):0] sram_addr,
output [(data_bus_size - 1):0] dummy_data,//For MUX
output reg start,
output rw,
output [11:0] data_out
);
reg [16:0] addr_in_old;
reg state;
//State defs
localparam state_start = 1'b0,
state_wait = 1'b1;
initial begin
start <= 1'b1;
state <= state_start;
addr_in_old <= 17'b11111111111111111;//Make sure we get triggered by the first addr
end
always @ (posedge clk or negedge reset) begin
if(reset == 1'b0) begin//Reset State
start <= 1'b1;
state <= state_start;
addr_in_old <= 17'b11111111111111111;
end
else begin
case (state)
//If we see a new address
state_start: begin
if(addr_in_old != addr_in && addr_in[16] != 1'b1) begin//VGA controller needs next pixel
//Get the next pixel
addr_in_old <= addr_in;
start <= 1'b0;
state <= state_wait;
end
end
state_wait: begin
//Wait until the data is there
start <= 1'b1;
if(ready == 1'b1) begin
state <= state_start;
end
end
default: begin
state <= state_start;
end
endcase
end
end
//sends vga controller black pixels if we're out of the address range
assign data_out = addr_in[16]? 12'b0 : sram_data[11:0];
assign sram_addr = addr_in[(addr_bus_size - 1):0];
assign dummy_data = 16'b0;
assign rw = 1'b1;//1 for read
endmodule
| 8.472483 |
module transmitreg2 (
input wire clk,
input wire rst,
input wire cpu, // CPU wuenscht Zugriff
input wire [15:0] reginp, // Registerbus
output reg [15:0] regout // Generalregister
);
always @(posedge clk) begin
if (rst == 1'b0) begin // synchroner Reset
regout <= 16'd0;
end else if (cpu == 1'b1) begin // cpu schriebt zu sendende Daten
regout <= reginp;
end
end
endmodule
| 7.363792 |
module transmitter_tb;
reg [7:0] dataInTofifo;
reg clk = 0, reset;
reg writeEn = 0;
baud_gen br1 (
.clk (clk),
.divsr(11'd650),
.reset(reset)
);
Transmitter #(8, 16) t1 (
.tx_start(~f.EMPTY),
.s_tick(br1.tick),
.tx_dataIn(f.dataOut)
);
fifo f (
.clk(clk),
.dataIn(dataInTofifo),
.reset(reset),
.readEn(t1.tx_done_tick),
.writeEn(writeEn)
);
initial begin
$dumpfile("transmitter");
$dumpvars(0, transmitter_tb);
reset = 1;
#15 reset = 0;
dataInTofifo = 8'b01010101;
writeEn = 1; //put data in fifo
#15 writeEn = 0;
#15 writeEn = 1;
dataInTofifo = 8'b01010111;
#15 writeEn = 0;
end
always #5 clk = ~clk;
endmodule
| 6.782935 |
module transmitter #(
parameter data_width = 8 //数据宽度8位
) (
input tx_clk,
input rst_n,
input [data_width-1:0] data_in,
input enable, //输入使能位
output reg tx_out
);
localparam IDLE = 3'b000;
localparam START = 3'b001; //发送低电平
localparam DATA = 3'b010;
localparam CRC = 3'b011; //校验,但暂时不用
localparam FINISH = 3'b100;
reg [3:0] state, nstate;
reg [3:0] count_data; //输出数据位计数器
//状态机第一段
always @(posedge tx_clk or negedge rst_n)
if (!rst_n) state <= IDLE;
else state <= nstate;
//状态机第二段
always @(*) begin
case (state)
IDLE: nstate = (enable ? START : IDLE); //注意enable的时序
START: nstate = DATA;
DATA: nstate = (count_data == (data_width - 1) ? FINISH : DATA);
CRC: nstate = FINISH; //正常情况进不来CRC的
FINISH: nstate = IDLE; //注意count_data和count_stop的时序
default: nstate = IDLE;
endcase
end
//状态机的输出
always @(*)
case (state)
IDLE: tx_out = 1'b1;
START: tx_out = 1'b0;
DATA: tx_out = data_in[count_data]; //由低位到高位依次输出
CRC: tx_out = 1'b0;
FINISH: tx_out = 1'b1;
default: tx_out = 1'b1;
endcase
//DATA状态，输出数据位的计数器
always @(posedge tx_clk or negedge rst_n)
if (!rst_n) count_data <= 4'b0000;
else if (count_data < data_width && state == DATA) count_data <= count_data + 1'b1;
else count_data <= 4'b0000;
endmodule
| 7.396496 |
module transmittercontrol (
input wire Rx,
output wire Tx,
input wire start_Tx,
input wire clk,
input wire [7:0] data_in,
output wire [15:0] D_address,
output wire [15:0] LEDR,
output wire [7:0] LEDG,
output wire Tx_done
);
wire tb;
wire wr_en;
reg en;
reg Rx_ready;
UART UART1 (
.data_in(data_in), //input data
.wr_en(wr_en), //enable tx
.clk(clk),
.Tx(Tx),
.Rx(Rx),
.Tx_busy(tb),
.data_out(data_out)
);
reg busy;
reg status3;
reg [1:0] status2;
reg [15:0] R_address;
assign D_address = R_address;
assign wr_en = en;
assign LEDR = D_address;
assign LEDG = data_out;
assign Tx_done = status3;
initial begin
status3 = 0;
status2 = 0;
R_address = 0;
en = 1;
end
always @(posedge clk) begin
busy = tb;
if (start_Tx && status2 != 2'b10 && ~busy && R_address == 0) begin
en = 0;
status2 = status2 + 1;
//en=1;
end
if (start_Tx && status2 == 2'b10 && ~busy && R_address < 65535) begin
R_address = R_address + 1;
en = 0;
if (R_address == 65535) begin
status3 = 1;
en = 1;
end
end
/*if (status3==1 && ~busy)
begin
en=1;
end*/
end
endmodule
| 7.083388 |
module transmitterNew (
input clk,
input reset,
input transmit_en,
input [35:0] to_transmitter_data,
input [18:0] transmit_address,
input [15:0] crc_tail,
input crc_done,
output reg crc_start,
output reg serial_data,
output reg [1:0] state,
output reg deserial_on,
output reg [5:0] counter,
output reg [5:0] crc_counter,
output reg [58:0] packet
);
reg [15:0] crc_checksum;
parameter idle = 0;
parameter transmitData = 1;
parameter transmitCRC = 2;
initial state = 0;
//reg [5:0] counter;
//reg [4:0] crc_counter;
always @(posedge clk) begin
if (reset) begin
state <= idle;
crc_checksum <= 16'hFFFF;
serial_data <= 0;
crc_counter <= 0;
crc_start <= 0;
counter <= 0;
deserial_on <= 0;
end
case (state)
idle: begin
if (transmit_en) begin
crc_start <= 1;
state <= transmitData;
packet <= {4'b1001, transmit_address, to_transmitter_data};
end else begin
crc_checksum <= 16'hFFFF;
serial_data <= 0;
crc_counter <= 0;
crc_start <= 0;
counter <= 0;
deserial_on <= 0;
end
end
transmitData: begin
if (counter != 59) begin
crc_start <= 0;
deserial_on <= 1;
serial_data <= packet[58];
packet <= {packet[57:0], 1'b0};
counter <= counter + 1;
if (crc_done) crc_checksum <= crc_tail;
end else begin
serial_data <= crc_checksum[15];
crc_checksum <= {crc_checksum[14:0], 1'b0};
crc_counter <= crc_counter + 1;
if (crc_counter == 16) begin
crc_counter <= 0;
counter <= 0;
deserial_on <= 0;
state <= idle;
end
end
end
default: state <= idle;
endcase
end
endmodule
| 6.964288 |
module Transmittersint (
CLK,
PCLK,
IN_DATA,
K,
RESET_PS,
RESET_PLL,
ENB_CONV,
OUT_SERIAL
);
input CLK;
wire CLK_CONV;
wire CLK_PS;
input ENB_CONV;
wire [9:0] ENC_OUT_10B;
input [31:0] IN_DATA;
input K;
wire [7:0] OUT_CONV;
output OUT_SERIAL;
input [1:0] PCLK;
input RESET_PLL;
input RESET_PS;
convertidors conv (
.CLK(CLK_CONV),
.ENB(ENB_CONV),
.PCLK(PCLK),
.in(IN_DATA),
.out_8(OUT_CONV)
);
encoders enc (
.dataK (K),
.in_8b (OUT_CONV),
.out_10b(ENC_OUT_10B)
);
PLLs pll (
.CLK(CLK),
.CLK_10(CLK_CONV),
.CLK_5(CLK_PS),
.reset(RESET_PLL)
);
paraleloserials ps (
.CLOCK(CLK_PS),
.D(ENC_OUT_10B),
.ENABLE(RESET_PS),
.OS(OUT_SERIAL)
);
endmodule
| 7.361723 |
module Transmittersynt (
CLK,
PCLK,
IN_DATA,
K,
RESET_PS,
RESET_PLL,
ENB_CONV,
OUT_SERIAL
);
input CLK;
wire CLK_CONV;
wire CLK_PS;
input ENB_CONV;
wire [9:0] ENC_OUT_10B;
input [31:0] IN_DATA;
input K;
wire [7:0] OUT_CONV;
output OUT_SERIAL;
input [1:0] PCLK;
input RESET_PLL;
input RESET_PS;
convertidors #(0) conv (
.CLK(CLK_CONV),
.ENB(ENB_CONV),
.PCLK(PCLK),
.in(IN_DATA),
.out_8(OUT_CONV)
);
encoders enc (
.dataK (K),
.in_8b (OUT_CONV),
.out_10b(ENC_OUT_10B)
);
PLLs #(1) pll (
.CLK(CLK),
.CLK_10(CLK_CONV),
.CLK_5(CLK_PS),
.reset(RESET_PLL)
);
paraleloserials #(2) ps (
.CLOCK(CLK_PS),
.D(ENC_OUT_10B),
.ENABLE(RESET_PS),
.OS(OUT_SERIAL)
);
endmodule
| 6.830867 |
module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module transmitter_db(clk, rst, TxD_Start, baud_pulse, TxD_Data,
baud_gen_init, baud_gen_en, TxD, busy);
// Input Ports
input clk;
input rst;
input TxD_Start;
input baud_pulse;
input [7:0] TxD_Data;
// Output Ports
output baud_gen_init;
output baud_gen_en;
output TxD;
output busy;
// Wires
wire load_data;
wire shift;
wire count;
wire set_count;
wire end_count;
wire [1:0] out_sel;
// Modules Instances
transmitter_dp TRANSMITTER_DP (
.clk(clk),
.load_data(load_data),
.shift(shift),
.count(count),
.set_count(set_count),
.out_sel(out_sel),
.TxD_Data(TxD_Data),
.end_count(end_count),
.TxD(TxD)
);
transmitter_fsm TRANSMITTER_FSM (
.clk(clk),
.rst(rst),
.TxD_Start(TxD_Start),
.end_count(end_count),
.baud_pulse(baud_pulse),
.load_data(load_data),
.count(count),
.shift(shift),
.set_count(set_count),
.out_sel(out_sel),
.baud_gen_init(baud_gen_init),
.baud_gen_en(baud_gen_en),
.busy(busy)
);
endmodule
| 7.612722 |
module transmitter_dp (
clk,
load_data,
shift,
count,
set_count,
out_sel,
TxD_Data,
end_count,
TxD
);
input clk;
input load_data;
input shift;
input count;
input set_count;
input [1:0] out_sel;
input [7:0] TxD_Data;
output end_count;
output reg TxD;
reg end_count;
reg mux_out;
reg [2:0] count_reg;
reg [7:0] shift_reg;
// Shift Register
always @(posedge clk)
if (load_data) shift_reg <= TxD_Data;
else if (shift) shift_reg <= {1'b1, shift_reg[7:1]};
//Mux
always @(out_sel, shift_reg)
case (out_sel)
2'b00: mux_out = 0;
2'b01: mux_out = shift_reg[0];
2'b10: mux_out = 1;
default: mux_out = 1;
endcase
// DownCounter
always @(posedge clk)
if (set_count) begin
count_reg <= 3'b111;
end_count <= 1'b0;
end else if (count) begin
count_reg <= count_reg - 1;
end_count <= (count_reg == 0);
end else end_count <= 1'b0;
// output reg
always @(posedge clk) TxD <= mux_out;
endmodule
| 6.726929 |
module transmitter_fsm (
clk,
rst,
TxD_Start,
end_count,
baud_pulse,
load_data,
count,
shift,
set_count,
out_sel,
baud_gen_init,
baud_gen_en,
busy
);
parameter IDLE = 0, START_BIT = 1, SEND_BIT = 2, STOP_BIT = 3;
input clk;
input rst;
input TxD_Start;
input end_count;
input baud_pulse;
output load_data;
output count;
output shift;
output set_count;
output baud_gen_init;
output baud_gen_en;
output busy;
output [1:0] out_sel;
reg [1:0] ns, cs;
reg [4:0] mealy_out;
reg [3:0] moore_out;
// Current state refresh
always @(posedge clk)
if (rst) cs <= IDLE;
else cs <= ns;
// Next State Logic
always @(cs, TxD_Start, baud_pulse, end_count)
case (cs)
IDLE: ns = TxD_Start ? START_BIT : IDLE;
START_BIT: ns = baud_pulse ? SEND_BIT : START_BIT;
SEND_BIT: ns = end_count ? STOP_BIT : SEND_BIT;
STOP_BIT:
ns = (TxD_Start & baud_pulse) ? START_BIT : (~TxD_Start & baud_pulse) ? IDLE : STOP_BIT;
default: ns = IDLE;
endcase
// Mealy outputs
assign {load_data, set_count, baud_gen_init, count, shift} = mealy_out;
always @(cs, TxD_Start, baud_pulse, end_count)
case (cs)
IDLE: mealy_out = TxD_Start ? 5'b1_1_1_0_0 : 5'b0_0_0_0_0;
START_BIT: mealy_out = 5'b0_0_0_0_0;
SEND_BIT: mealy_out = (end_count) ? 5'b0_0_0_0_0 : (baud_pulse) ? 5'b0_0_0_1_1 : 5'b0_0_0_0_0;
STOP_BIT: mealy_out = (TxD_Start & baud_pulse) ? 5'b1_1_1_0_0 : 5'b0_0_0_0_0;
default: mealy_out = 5'b0_0_0_0_0;
endcase
// Moore outputs
assign {baud_gen_en, out_sel, busy} = moore_out;
always @(cs)
case (cs)
IDLE: moore_out = 4'b0_10_0;
START_BIT: moore_out = 4'b1_00_1;
SEND_BIT: moore_out = 4'b1_01_1;
STOP_BIT: moore_out = 9'b1_10_1;
default: moore_out = 9'b0_10_0;
endcase
endmodule
| 7.847676 |
module transmitter_tb;
parameter data_width = 8;
reg tx_clk;
reg rst_n;
wire [data_width-1:0] data_in;
wire enable;
wire tx_out;
transmitter tm1 (
tx_clk,
rst_n,
data_in,
enable,
tx_out
);
transmitter_gen tg1 (
tx_clk,
rst_n,
enable,
data_in
);
// initial begin
// tx_clk<=1'b0;
// rst_n<=1'b0;
// data_in<=$random;
// enable<=0;
// $dumpfile("transmitter.vcd");
// $dumpvars;
// #45 rst_n<=1;
// repeat(10)begin
// data_in<=$random;
// @(posedge tx_clk) enable<=1;
// @(posedge tx_clk) enable<=0;
// #400;
// end
// #1000 $finish;
// end
initial begin
tx_clk <= 1'b0;
rst_n <= 1'b0;
$dumpfile("transmitter.vcd");
$dumpvars;
#45 rst_n <= 1;
#4000 $finish;
end
always #10 tx_clk <= ~tx_clk;
endmodule
| 6.782935 |
module transmitter_test (
input clk,
input button,
input [7:0] i_Tx_Byte,
output serial
);
wire buttonout;
buttonlimiter(
.buttonin(button), .clk(clk), .buttonout(buttonout)
); uart_tx(
.i_Clock(clk),
.i_Tx_DV(button),
.i_Tx_Byte(i_Tx_Byte),
.o_Tx_Active(),
.o_Tx_Serial(serial),
.o_Tx_Done()
);
endmodule
| 6.782935 |
module TransmitTop_min_frame_tb();
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to be injected into the data
reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
//input to transmit fault signals
reg RXTXLINKFAULT;
reg LOCALLINKFAULT;
reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
//apply pause timing
reg [15:0] FC_TX_PAUSEDATA;
reg FC_TX_PAUSEVALID;
//apply configuration value
reg [31:0] TX_CFG_REG_VALUE;
reg TX_CFG_REG_VALID;
//output to stat register
wire TX_STATS_VALID;
wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
wire [63:0] TXD;
wire [7:0] TXC;
wire TX_ACK;
reg D_START;
reg START_TX_BITS;
// Initialize all variables
initial begin
Append_last_bit = 0;
TX_CLK = 1; // initial value of clock
RESET <= 0; // initial value of reset
TX_START <= 0; // initial value of enable
TX_DATA_VALID <= 8'h00;
D_START = 0;
FC_TX_PAUSEVALID <= 0;
FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
TX_UNDERRUN = 0;
#5 RESET= 1; // Assert the reset
#10 RESET= 0; // De-assert the reset
#15 TX_START = 1;
// TX_DATA = 64'h0000560000000000;
TX_DATA_VALID = 8'hFF;
D_START = 1;
#20 TX_START = 0;
//#1800 TX_DATA_VALID = 8'h07;
#60 TX_DATA_VALID = 8'h07;
// #1960 TX_DATA_VALID = 8'h07;
// TX_DATA = 64'h0000000000000011;
#10 TX_DATA_VALID = 8'h00;
D_START = 0;
//next frame
#20 TX_START <= 1;
TX_DATA_VALID <= 8'hFF;
D_START = 1;
#20 TX_START <= 0;
#400 TX_DATA_VALID <= 8'h00;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
#1000 $finish; // Terminate simulation
end
always @(posedge D_START or posedge TX_CLK)
begin
if (D_START == 0) begin
TX_DATA = 64'h0000000000000000;
end
//else if (TX_DATA_VALID == 8'h07) begin
// TX_DATA = 64'h000000000077FFCC;
//end
else if (Append_last_bit == 1) begin
// TX_DATA = 64'h202020202077FFCC;
TX_DATA = 64'h000000000077FFCC;
end
else if (START_TX_BITS == 1) begin
TX_DATA = TX_DATA + 1;
end
else begin
TX_DATA = 64'h0000000000000001;
end
end
always @(TX_DATA)
begin
if (TX_DATA == 2) begin
TX_DATA_int[31:0] <= TX_DATA[31:0];
TX_DATA_int[47:32] <= 300;
TX_DATA_int[63:48] <= TX_DATA[63:48];
end
else begin
TX_DATA_int <= TX_DATA;
end
end
always @(TX_ACK | TX_START)
begin
if (TX_ACK) begin
START_TX_BITS = 1;
end
else if (TX_START) begin
START_TX_BITS = 0;
end
end
// Clock generator
always begin
#5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
TRANSMIT_TOP U_top_module (
TX_DATA_int,
TX_DATA_VALID,
TX_CLK,
RESET,
TX_START,
TX_ACK,
TX_UNDERRUN,
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,
FC_TRANS_PAUSEDATA,
FC_TRANS_PAUSEVAL,
FC_TX_PAUSEDATA,
FC_TX_PAUSEVALID,
TX_CFG_REG_VALUE,
TX_CFG_REG_VALID
);
endmodule
| 7.798866 |
module TransmitTop_min_frame_tb();
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to be injected into the data
reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
//input to transmit fault signals
reg RXTXLINKFAULT;
reg LOCALLINKFAULT;
reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
//apply pause timing
reg [15:0] FC_TX_PAUSEDATA;
reg FC_TX_PAUSEVALID;
//apply configuration value
reg [31:0] TX_CFG_REG_VALUE;
reg TX_CFG_REG_VALID;
//output to stat register
wire TX_STATS_VALID;
wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
wire [63:0] TXD;
wire [7:0] TXC;
wire TX_ACK;
reg D_START;
reg START_TX_BITS;
// Initialize all variables
initial begin
Append_last_bit = 0;
TX_CLK = 1; // initial value of clock
RESET <= 0; // initial value of reset
TX_START <= 0; // initial value of enable
TX_DATA_VALID <= 8'h00;
D_START = 0;
FC_TX_PAUSEVALID <= 0;
FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
TX_UNDERRUN = 0;
#5 RESET= 1; // Assert the reset
#10 RESET= 0; // De-assert the reset
#15 TX_START = 1;
// TX_DATA = 64'h0000560000000000;
TX_DATA_VALID = 8'hFF;
D_START = 1;
#20 TX_START = 0;
//#1800 TX_DATA_VALID = 8'h07;
#60 TX_DATA_VALID = 8'h07;
// #1960 TX_DATA_VALID = 8'h07;
// TX_DATA = 64'h0000000000000011;
#10 TX_DATA_VALID = 8'h00;
D_START = 0;
//next frame
#20 TX_START <= 1;
TX_DATA_VALID <= 8'hFF;
D_START = 1;
#20 TX_START <= 0;
#400 TX_DATA_VALID <= 8'h00;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
#1000 $finish; // Terminate simulation
end
always @(posedge D_START or posedge TX_CLK)
begin
if (D_START == 0) begin
TX_DATA = 64'h0000000000000000;
end
//else if (TX_DATA_VALID == 8'h07) begin
// TX_DATA = 64'h000000000077FFCC;
//end
else if (Append_last_bit == 1) begin
// TX_DATA = 64'h202020202077FFCC;
TX_DATA = 64'h000000000077FFCC;
end
else if (START_TX_BITS == 1) begin
TX_DATA = TX_DATA + 1;
end
else begin
TX_DATA = 64'h0000000000000001;
end
end
always @(TX_DATA)
begin
if (TX_DATA == 2) begin
TX_DATA_int[31:0] <= TX_DATA[31:0];
TX_DATA_int[47:32] <= 300;
TX_DATA_int[63:48] <= TX_DATA[63:48];
end
else begin
TX_DATA_int <= TX_DATA;
end
end
always @(TX_ACK | TX_START)
begin
if (TX_ACK) begin
START_TX_BITS = 1;
end
else if (TX_START) begin
START_TX_BITS = 0;
end
end
// Clock generator
always begin
#5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
TRANSMIT_TOP U_top_module (
TX_DATA_int,
TX_DATA_VALID,
TX_CLK,
RESET,
TX_START,
TX_ACK,
TX_UNDERRUN,
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,
FC_TRANS_PAUSEDATA,
FC_TRANS_PAUSEVAL,
FC_TX_PAUSEDATA,
FC_TX_PAUSEVALID,
TX_CFG_REG_VALUE,
TX_CFG_REG_VALID
);
endmodule
| 7.798866 |
module TransmitTopPause_tb();
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to be injected into the data
reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
//input to transmit fault signals
reg RXTXLINKFAULT;
reg LOCALLINKFAULT;
reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
//apply pause timing
reg [15:0] FC_TX_PAUSEDATA;
reg FC_TX_PAUSEVALID;
//apply configuration value
reg [31:0] TX_CFG_REG_VALUE;
reg TX_CFG_REG_VALID;
//output to stat register
wire TX_STATS_VALID;
wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
wire [63:0] TXD;
wire [7:0] TXC;
wire TX_ACK;
reg D_START;
reg START_TX_BITS;
// Initialize all variables
initial begin
Append_last_bit = 0;
TX_CLK = 1; // initial value of clock
RESET <= 0; // initial value of reset
TX_START <= 0; // initial value of enable
TX_DATA_VALID <= 8'h00;
D_START = 0;
FC_TX_PAUSEVALID <= 0;
FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
TX_UNDERRUN = 0;
#5 RESET <= 1; // Assert the reset
#10 RESET <= 0; // De-assert the reset
#15 //TX_START <= 1;
//TX_DATA_VALID <= 8'hFF;
//D_START <= 1;
#20 TX_START <= 0;
#400 //TX_DATA_VALID <= 8'h00;
//FC_TX_PAUSEVALID <= 1;
//FC_TX_PAUSEDATA <= 30;
FC_TRANS_PAUSEDATA <= 30;
FC_TRANS_PAUSEVAL <= 1;
//TX_DATA_VALID <= 8'h7f;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
//FC_TX_PAUSEVALID <= 0;
//FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
#20 //TX_START <= 1;
//TX_DATA_VALID <= 8'hFF;
//D_START = 1;
#20 TX_START <= 0;
#400 TX_DATA_VALID <= 8'h00;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
#1300 $finish; // Terminate simulation
end
always @(posedge D_START or posedge TX_CLK)
begin
if (D_START == 0) begin
TX_DATA = 64'h0000000000000000;
end
//else if (TX_DATA_VALID == 8'h07) begin
// TX_DATA = 64'h000000000077FFCC;
//end
else if (Append_last_bit == 1) begin
// TX_DATA = 64'h202020202077FFCC;
TX_DATA = 64'h000000000077FFCC;
end
else if (START_TX_BITS == 1) begin
TX_DATA = TX_DATA + 1;
end
else begin
TX_DATA = 64'h0000000000000001;
end
end
always @(TX_DATA)
begin
if (TX_DATA == 2) begin
TX_DATA_int[31:0] <= TX_DATA[31:0];
TX_DATA_int[47:32] <= 300;
TX_DATA_int[63:48] <= TX_DATA[63:48];
end
else begin
TX_DATA_int <= TX_DATA;
end
end
always @(TX_ACK | TX_START)
begin
if (TX_ACK) begin
START_TX_BITS = 1;
end
else if (TX_START) begin
START_TX_BITS = 0;
end
end
// Clock generator
always begin
#5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
TRANSMIT_TOP U_top_module (
TX_DATA_int,
TX_DATA_VALID,
TX_CLK,
RESET,
TX_START,
TX_ACK,
TX_UNDERRUN,
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,
FC_TRANS_PAUSEDATA,
FC_TRANS_PAUSEVAL,
FC_TX_PAUSEDATA,
FC_TX_PAUSEVALID,
TX_CFG_REG_VALUE,
TX_CFG_REG_VALID
);
endmodule
| 8.001368 |
module TransmitTop_tb();
//Input from user logic
reg [63:0] TX_DATA;
reg [63:0] TX_DATA_int;
reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
reg Append_last_bit;
reg TX_CLK;
reg RESET;
reg TX_START; // This signify the first frame of data
reg TX_UNDERRUN; // this will cause an error to be injected into the data
reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
//input to transmit fault signals
reg RXTXLINKFAULT;
reg LOCALLINKFAULT;
reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
//apply pause timing
reg [15:0] FC_TX_PAUSEDATA;
reg FC_TX_PAUSEVALID;
//apply configuration value
reg [31:0] TX_CFG_REG_VALUE;
reg TX_CFG_REG_VALID;
//output to stat register
wire TX_STATS_VALID;
wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
wire [63:0] TXD;
wire [7:0] TXC;
wire TX_ACK;
reg D_START;
reg START_TX_BITS;
// Initialize all variables
initial begin
Append_last_bit = 0;
TX_CLK = 1; // initial value of clock
RESET <= 0; // initial value of reset
TX_START <= 0; // initial value of enable
TX_DATA_VALID <= 8'h00;
D_START = 0;
FC_TX_PAUSEVALID <= 0;
FC_TX_PAUSEDATA <= 0;
FC_TRANS_PAUSEDATA <= 0;
FC_TRANS_PAUSEVAL <= 0;
TX_UNDERRUN = 0;
#5 RESET <= 1; // Assert the reset
#10 RESET <= 0; // De-assert the reset
#15 TX_START <= 1;
TX_DATA_VALID <= 8'hFF;
D_START <= 1;
#20 TX_START <= 0;
#400 //TX_DATA_VALID <= 8'h00;
//FC_TX_PAUSEVALID <= 1;
//FC_TX_PAUSEDATA <= 30;
// FC_TRANS_PAUSEDATA <= 30;
// FC_TRANS_PAUSEVAL <= 1;
TX_DATA_VALID <= 8'h7f;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
//FC_TX_PAUSEVALID <= 0;
//FC_TX_PAUSEDATA <= 0;
// FC_TRANS_PAUSEDATA <= 0;
// FC_TRANS_PAUSEVAL <= 0;
#20 TX_START <= 1;
TX_DATA_VALID <= 8'hFF;
D_START = 1;
#20 TX_START <= 0;
#400 TX_DATA_VALID <= 8'h00;
#10 TX_DATA_VALID <= 8'h00;
D_START = 0;
#1300 $finish; // Terminate simulation
end
always @(posedge D_START or posedge TX_CLK)
begin
if (D_START == 0) begin
TX_DATA = 64'h0000000000000000;
end
//else if (TX_DATA_VALID == 8'h07) begin
// TX_DATA = 64'h000000000077FFCC;
//end
else if (Append_last_bit == 1) begin
// TX_DATA = 64'h202020202077FFCC;
TX_DATA = 64'h000000000077FFCC;
end
else if (START_TX_BITS == 1) begin
TX_DATA = TX_DATA + 1;
end
else begin
TX_DATA = 64'h0000000000000001;
end
end
always @(TX_DATA)
begin
if (TX_DATA == 2) begin
TX_DATA_int[31:0] <= TX_DATA[31:0];
TX_DATA_int[47:32] <= 300;
TX_DATA_int[63:48] <= TX_DATA[63:48];
end
else begin
TX_DATA_int <= TX_DATA;
end
end
always @(TX_ACK | TX_START)
begin
if (TX_ACK) begin
START_TX_BITS = 1;
end
else if (TX_START) begin
START_TX_BITS = 0;
end
end
// Clock generator
always begin
#5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
TRANSMIT_TOP U_top_module (
TX_DATA_int,
TX_DATA_VALID,
TX_CLK,
RESET,
TX_START,
TX_ACK,
TX_UNDERRUN,
TX_IFG_DELAY,
RXTXLINKFAULT,
LOCALLINKFAULT,
TX_STATS_VALID,
TXSTATREGPLUS,
TXD,
TXC,
FC_TRANS_PAUSEDATA,
FC_TRANS_PAUSEVAL,
FC_TX_PAUSEDATA,
FC_TX_PAUSEVALID,
TX_CFG_REG_VALUE,
TX_CFG_REG_VALID
);
endmodule
| 7.593141 |
module transmit_debouncing #(
parameter threshold = 20
) //100000)// set parameter thresehold to guage how long button pressed
(
input clk, //clock signal
input btn1, //input buttons for transmit and reset
input stop,
input t_done,
output reg transmit //transmit signal
);
reg button_ff1 = 0; //button flip-flop for synchronization. Initialize it to 0
reg button_ff2 = 0; //button flip-flop for synchronization. Initialize it to 0
reg [30:0]count = 0; //20 bits count for increment & decrement when button is pressed or released. Initialize it to 0
// First use two flip-flops to synchronize the button signal the "clk" clock domain
always @(posedge clk) begin
button_ff1 <= btn1;
button_ff2 <= button_ff1;
end
// When the push-button is pushed or released, we increment or decrement the counter
// The counter has to reach threshold before we decide that the push-button state has changed
always @(posedge clk) begin
if (stop) begin
count <= 0;
transmit <= 0;
end else begin
if (button_ff2) //if button_ff2 is 1
begin
if (~&count)//if it isn't at the count limit. Make sure won't count up at the limit. First AND all count and then not the AND
count <= count + 1; // when btn pressed, count up
end else begin
if (|count) //if count has at least 1 in it. Make sure no subtraction when count is 0
count <= count - 1; //when btn relesed, count down
end
if (count > threshold) //if the count is greater the threshold
if (!stop) transmit <= 1; //debounced signal is 1
else;
else transmit <= 0; //debounced signal is 0
end
end
endmodule
| 7.696014 |
module transmit_en (
transmit_en1,
transmit_en2
);
input transmit_en1;
output wire transmit_en2;
assign transmit_en2 = transmit_en1;
endmodule
| 6.613043 |
module transmit_test_entity (
//input
input clk_in,
input reset_n,
//output
output Sample_Gate, //
output [15:0] P,
output [15:0] N,
output HV_SW_CLR,
output HV_SW_LE,
output HV_SW_CLK,
output HV_SW_DOUT,
output [3:0] AX,
output [2:0] AY,
output MT_CS,
output MT_Strobe,
output MT_Data
);
//wire
wire [7:0] Line_Num;
wire [1:0] Focus_Num;
wire Pr_Gate;
wire RX_Gate;
wire End_Gate;
wire Envelop;
//reg
//combination
//seq
transmit_test_model transmit_test_model (
//input
.clk_100M(clk_in),
.reset_n (reset_n),
//output
.Line_Num(Line_Num),
.Focus_Num(Focus_Num),
.Pr_Gate(Pr_Gate),
.RX_Gate(RX_Gate),
.End_Gate(End_Gate),
.Envelop(Envelop)
);
Transmit Transmit_module (
//input
.Transmit_CLK(clk_in), //100MHz
.Line_Num (Line_Num), //Line Num,256 Lines totally,0~255
.Focus_Num (Focus_Num), //Focus_num ,3 totally
.Pr_Gate (Pr_Gate), //prepare for everythings
.RX_Gate (RX_Gate), // Start Transmit
//output
.Sample_Gate (Sample_Gate), //
.P (P),
.N (N),
.HV_SW_CLR (HV_SW_CLR),
.HV_SW_LE (HV_SW_LE),
.HV_SW_CLK (HV_SW_CLK),
.HV_SW_DOUT (HV_SW_DOUT),
.AX (AX),
.AY (AY),
.MT_CS (MT_CS),
.MT_Strobe(MT_Strobe),
.MT_Data (MT_Data)
);
endmodule
| 6.750036 |
module transmit_test_entity_tb;
//input
reg clk_in;
reg reset_n;
//output
wire Sample_Gate;
wire [15:0] P;
wire [15:0] N;
wire HV_SW_CLR;
wire HV_SW_LE;
wire HV_SW_CLK;
wire HV_SW_DOUT;
wire [ 3:0] AX;
wire [ 2:0] AY;
wire MT_CS;
wire MT_Strobe;
wire MT_Data;
transmit_test_entity transmit_test_entity (
//input
.clk_in(clk_in),
.reset_n (reset_n),
//output
.Sample_Gate(Sample_Gate), //
.P(P),
.N(N),
.HV_SW_CLR(HV_SW_CLR),
.HV_SW_LE(HV_SW_LE),
.HV_SW_CLK(HV_SW_CLK),
.HV_SW_DOUT(HV_SW_DOUT),
.AX(AX),
.AY(AY),
.MT_CS(MT_CS),
.MT_Strobe(MT_Strobe),
.MT_Data(MT_Data)
);
initial clk_in = 1'b0;
always clk_in = #5 ~clk_in;
initial begin
reset_n = 1'b0;
#400;
reset_n = 1'b1;
end
endmodule
| 6.750036 |
module transmonitor_dummy (
input wire hclk,
input wire hresetn,
// AHB-LITE MASTER PORT --------------
input wire [31:0] hmaster_m, // AHB transfer: non-sequential only
input wire hsel_m,
input wire [31:0] haddr_m, // AHB transaction address
input wire [ 2:0] hsize_m, // AHB size: byte, half-word or word
input wire [ 3:0] hprot_m,
input wire [31:0] hwdata_m, // AHB write-data
input wire hwrite_m, // AHB write control
output reg [31:0] hrdata_m, // AHB read-data
output reg hready_m, // AHB stall signal
output reg hresp_m, // AHB error response
// AHB-LITE SLAVE PORT --------------
output wire hsel_s, // AHB transfer: non-sequential only
output wire [31:0] hmaster_s, // AHB transaction address
output wire [31:0] haddr_s, // AHB transaction address
output wire [ 2:0] hsize_s, // AHB size: byte, half-word or word
output wire [31:0] hwdata_s, // AHB write-data
output wire hwrite_s, // AHB write control
input wire [31:0] hrdata_s, // AHB read-data
input wire hready_s, // AHB stall signal
input wire hresp_s // AHB error response
);
//----------------------------------
//wire and localparam declaration
//----------------------------------
wire hsel_loc;
wire hwrite_loc;
wire [31:0] hrdata_loc;
wire [31:0] hwdata_loc;
wire [31:0] haddr_loc;
reg hresp_loc;
reg hready_loc;
reg [ 7:0] hmaster_d;
reg [31:0] haddr_m_d;
reg [ 2:0] hsize_m_d;
reg [ 3:0] hprot_m_d;
reg [31:0] hwdata_m_d;
reg hwrite_m_d;
reg hsel_m_d;
assign hready_m = hready_s;
assign hresp_m = hresp_s;
assign hrdata_m = hrdata_s;
assign hsel_s = hsel_m;
assign haddr_s = haddr_m;
assign hmaster_s = hmaster_m;
assign hwdata_s = hwdata_m;
assign hwrite_s = hwrite_m;
assign hsize_s = hsize_m;
endmodule
| 8.678247 |
module BRAM_FIFO #(
parameter ALMOST_EMPTY_OFFSET = 12'h080,
parameter ALMOST_FULL_OFFSET = 12'h080
) (
input clk,
input rst,
input [15:0] din,
input wr_en,
input rd_en,
output [15:0] dout,
output full,
output empty,
output prog_empty,
output prog_full
);
// FIFO18E1: 18Kb FIFO (First-In-First-Out) Block RAM Memory
// 7 Series
// Xilinx HDL Libraries Guide, version 13.2
FIFO18 #(
.SIM_MODE("FAST"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
.ALMOST_EMPTY_OFFSET((ALMOST_EMPTY_OFFSET > 12'h006) ? ALMOST_EMPTY_OFFSET : 12'h006), // Sets the almost empty threshold
.DATA_WIDTH(18), // Sets data width to 4, 9, or 18
.DO_REG(1), // Enable output register (0 or 1) -> must be 1 if EN_SYN = "FALSE"
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous ("FALSE") or Synchronous ("TRUE")
.FIRST_WORD_FALL_THROUGH("TRUE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
) FIFO36_inst (
.ALMOSTEMPTY(prog_empty), // 1-bit almost empty output flag
.ALMOSTFULL (prog_full), // 1-bit almost full output flag
.DO (dout), // 16-bit data output
.DOP (), // 2-bit parity data output
.EMPTY (empty), // 1-bit empty output flag
.FULL (full), // 1-bit full output flag
.RDCOUNT (), // 12-bit read count output
.RDERR (), // 1-bit read error output
.WRCOUNT (), // 12-bit write count output
.WRERR (), // 1-bit write error
.DI (din), // 16-bit data input
.DIP (), // 2-bit parity input
.RDCLK (clk), // 1-bit read clock input
.RDEN (rd_en), // 1-bit read enable input
.RST (rst), // 1-bit reset input
.WRCLK (clk), // 1-bit write clock input
.WREN (wr_en) // 1-bit write enable input
);
endmodule
| 7.307344 |
module transport_in2out
/// transport input block from input pipeling memories to output pipeling memories
(
input clk, // input clock planned to be 56 Mhz
input reset, // active high asynchronous reset
// active high flag for one clock to indicate that the block should work
input S_Ready,
output reg RE,
WE, /// RE for input memories , WE for output memories
output reg [7:0] RdAdd,
WrAdd,
output reg Wr_done
);
reg cnt;
reg state; //// 0 or 1
always @(posedge clk or posedge reset) begin
if (reset) begin
WE <= 0;
RE <= 0;
RdAdd <= 0;
WrAdd <= 0;
Wr_done <= 0;
state <= 0;
cnt <= 0;
end else begin
case (state)
////////////////////////////////////
1: begin //// operation is runing
cnt <= ~cnt;
if (cnt) begin
WrAdd <= WrAdd + 1;
if (WrAdd == 186) begin
state <= 0;
Wr_done <= 1;
end
end else begin
RdAdd <= RdAdd - 1;
end
end
///////////////////////////////////////
default: begin //// idle state
Wr_done <= 0;
if (S_Ready) begin
state <= 1;
RE <= ~RE;
WE <= ~WE;
RdAdd <= 204;
WrAdd <= 255;
cnt <= 0;
end
end
///////////////////////////////////
endcase
end
end
endmodule
| 7.17857 |
module transport (clk,
rst_n,
router_algorithm_out_x,
router_algorithm_out_y,
router_algorithm_out_local,
control_x,
control_y,
control_local， fail,
control_clk);
input clk, rst_n;
input [1:0] router_algorithm_out_x;
input [1:0] router_algorithm_out_y;
input [1:0] router_algorithm_out_local;
input control_clk;
output [1:0] control_x;
output [1:0] control_y;
output [1:0] control_local;
input [2:0]fail;
// input [39:0] din_x;
// input [39:0] din_y;
// input [39:0] din_local;
always @(posedge clk or posedge rst_n) begin
// reset
if (!rst_n) begin
control_x <= 2'b00;
control_y <= 2'b00;
control_local <= 2'b00;
end
// normally go weill
else
begin
if (!control_clk) // control_clk is enabled
// if control_clk is disabled, a bubble occurs here
begin
case (fail)
3'b001: control_x <= 2'b00;
3'b010: control_y <= 2'b00;
3'b100: control_local <= 2'b00;
default: begin
control_x <= 2'b00;
control_y <= 2'b00;
control_local <= 2'b00;
end
endcase
// judgment of the fail signal
// fail is 3-bit and only the 3 situations are valid
// otherwise, set all ports invalid
// transfer from router outcome to control signals at mux later
begin
case (router_algorithm_out_x)
2'b00: control_x <= 2'b00;
2'b01: control_x <= 2'b01;
2'b10: control_y <= 2'b01;
2'b11: control_local <= 2'b01;
default: control_x <= 2'b00;
endcase
case (router_algorithm_out_y)
2'b00: control_y <= 2'b00;
2'b01: control_x <= 2'b10;
2'b10: control_y <= 2'b10;
2'b11: control_local <= 2'b10;
default: control_y <= 2'b00;
endcase
case (router_algorithm_out_local)
2'b00: lcoal <= 2'b00;
2'b01: control_x <= 2'b11;
2'b10: control_y <= 2'b11;
2'b11: control_local <= 2'b11;
default: control_local <= 2'b00;
endcase
end
end
end
end
endmodule
| 7.410905 |
module register (
clk,
enable,
d,
q
);
input clk;
input enable;
input d;
output reg q;
always @(posedge clk) begin
if (enable == 1) q <= d;
end
endmodule
| 6.542519 |
module transposer (
clk,
i_enable,
i_sel,
i_data,
o_stream
);
parameter SEL_BITS = 4;
parameter WL = 16;
parameter WORDS = 16;
input clk;
input i_enable;
input [SEL_BITS - 1 : 0] i_sel;
input [WL * WORDS - 1 : 0] i_data;
wire [WL * WORDS - 1 : 0] q;
output [WORDS - 1 : 0] o_stream;
genvar i, j;
generate
for (j = 0; j < WORDS; j = j + 1) begin : words
for (i = 0; i < WL; i = i + 1) begin : bits
register REG (
clk,
i_enable,
i_data[j*WORDS+i],
q[j*WORDS+i]
);
end
mux_16_to_1 #(1) MUX_ARRAY (
i_sel,
q[j*WORDS+0],
q[j*WORDS+1],
q[j*WORDS+2],
q[j*WORDS+3],
q[j*WORDS+4],
q[j*WORDS+5],
q[j*WORDS+6],
q[j*WORDS+7],
q[j*WORDS+8],
q[j*WORDS+9],
q[j*WORDS+10],
q[j*WORDS+11],
q[j*WORDS+12],
q[j*WORDS+13],
q[j*WORDS+14],
q[j*WORDS+15],
o_stream[j]
);
end
endgenerate
endmodule
| 6.738023 |
module transposer_array (
clk,
i_enable,
i_sel,
i_data,
o_stream
);
parameter SEL_BITS = 4;
parameter WL = 16;
parameter WORDS = 16;
parameter ARRAY_SIZE = 16;
parameter BL = WL * WORDS; // BRICK LENGTH in bits
input clk;
input [ARRAY_SIZE - 1 : 0] i_enable;
input [SEL_BITS - 1 : 0] i_sel;
input [ARRAY_SIZE * BL - 1 : 0] i_data;
wire [ARRAY_SIZE * BL - 1 : 0] q;
output [ARRAY_SIZE * WORDS - 1 : 0] o_stream;
genvar i;
generate
for (i = 0; i < ARRAY_SIZE; i = i + 1) begin : TRANS_ARRAY
transposer TRANS (
clk,
i_enable[i],
i_sel,
i_data[(i+1)*BL-1 : i*BL],
o_stream[(i+1)*WORDS-1 : i*WORDS]
);
end
endgenerate
endmodule
| 7.044707 |
module register (
clk,
enable,
d,
q
);
input clk;
input enable;
input d;
output reg q;
always @(posedge clk) begin
if (enable == 1) q <= d;
end
endmodule
| 6.542519 |
module transposer (
clk,
i_enable,
i_sel,
i_data,
o_stream
);
parameter SEL_BITS = 4;
parameter WL = 16;
parameter WORDS = 16;
input clk;
input i_enable;
input [SEL_BITS - 1 : 0] i_sel;
input [WL * WORDS - 1 : 0] i_data;
wire [WL * WORDS - 1 : 0] q;
output [WORDS - 1 : 0] o_stream;
genvar i, j;
generate
for (j = 0; j < WORDS; j = j + 1) begin : words
for (i = 0; i < WL; i = i + 1) begin : bits
register REG (
clk,
i_enable,
i_data[j*WORDS+i],
q[j*WORDS+i]
);
end
mux_16_to_1 #(1) MUX_ARRAY (
i_sel,
q[j*WORDS+0],
q[j*WORDS+1],
q[j*WORDS+2],
q[j*WORDS+3],
q[j*WORDS+4],
q[j*WORDS+5],
q[j*WORDS+6],
q[j*WORDS+7],
q[j*WORDS+8],
q[j*WORDS+9],
q[j*WORDS+10],
q[j*WORDS+11],
q[j*WORDS+12],
q[j*WORDS+13],
q[j*WORDS+14],
q[j*WORDS+15],
o_stream[j]
);
end
endgenerate
endmodule
| 6.738023 |
module transposer_array (
clk,
i_enable,
i_sel,
i_data,
o_stream
);
parameter SEL_BITS = 4;
parameter WL = 16;
parameter WORDS = 16;
parameter ARRAY_SIZE = 16;
parameter BL = WL * WORDS; // BRICK LENGTH in bits
input clk;
input [ARRAY_SIZE - 1 : 0] i_enable;
input [SEL_BITS - 1 : 0] i_sel;
input [ARRAY_SIZE * BL - 1 : 0] i_data;
wire [ARRAY_SIZE * BL - 1 : 0] q;
output [ARRAY_SIZE * WORDS - 1 : 0] o_stream;
reg [ARRAY_SIZE - 1 : 0] i_enable_reg;
reg [SEL_BITS - 1 : 0] i_sel_reg;
reg [ARRAY_SIZE * BL - 1 : 0] i_data_reg;
reg [ARRAY_SIZE * WORDS - 1 : 0] o_stream_reg;
wire [ARRAY_SIZE * WORDS - 1 : 0] o;
assign o_stream = o_stream_reg;
always @(posedge clk) begin
i_enable_reg <= i_enable;
i_sel_reg <= i_sel;
i_data_reg <= i_data;
o_stream_reg <= o;
end
genvar i;
generate
for (i = 0; i < ARRAY_SIZE; i = i + 1) begin : TRANS_ARRAY
transposer TRANS (
clk,
i_enable_reg[i],
i_sel_reg,
i_data_reg[(i+1)*BL-1 : i*BL],
o[(i+1)*WORDS-1 : i*WORDS]
);
end
endgenerate
endmodule
| 7.044707 |
module testbench;
parameter SEL_BITS = 4;
parameter WL = 16;
parameter WORDS = 16;
reg clk;
reg enable;
reg [WORDS*WL - 1 : 0] data;
reg [ SEL_BITS : 0] sel;
wire [ WORDS - 1 : 0] stream;
initial begin
clk = 1;
data = 64'h0003000A000E000F;
enable = 1;
sel = 4'h0;
#15 enable = 0;
data = 'bx;
for (sel = 1; sel < 16; sel = sel + 1) begin
#10;
end
#10 $finish;
end
always #5 clk = !clk;
initial begin
$dumpfile("serial_ip_testbench.vcd");
$dumpvars;
end
always @(posedge clk) begin
#1 $display("%4d data=%h select=%2d stream=%b", $time, data, sel, stream);
end
transposer t1 (
clk,
enable,
sel,
data,
stream
);
endmodule
| 7.015571 |
module transpose ( //output
atrcol_out1,
atrcol_out2,
//input
col_ldata,
col_hdata,
col_out_vld,
dwt_work,
clk_tr,
rst,
rst_syn
);
output [15:0] atrcol_out1;
output [15:0] atrcol_out2;
input [15:0] col_ldata;
input [15:0] col_hdata;
input col_out_vld;
input clk_tr;
input rst;
input rst_syn;
input dwt_work;
reg [15:0] stage1_reg1;
reg [15:0] stage1_reg2;
always @(posedge clk_tr or negedge rst) begin
if (!rst) begin
stage1_reg1 <= 16'b0;
end else if (rst_syn) begin
stage1_reg1 <= 16'b0;
end else if (dwt_work == 1'b1) begin
stage1_reg1 <= col_ldata;
end
end
always @(posedge clk_tr or negedge rst) begin
if (!rst) begin
stage1_reg2 <= 16'b0;
end else if (rst_syn) begin
stage1_reg2 <= 16'b0;
end else if (dwt_work == 1'b1) begin
stage1_reg2 <= col_hdata;
end
end
reg [15:0] stage2_reg;
always @(posedge clk_tr or negedge rst) begin
if (!rst) begin
stage2_reg <= 16'b0;
end else if (rst_syn) begin
stage2_reg <= 16'b0;
end else if (dwt_work == 1'b1) begin
stage2_reg <= stage1_reg2;
end
end
reg sel_cnt;
always @(posedge clk_tr or negedge rst) begin
if (!rst) begin
sel_cnt <= 1'b0;
end else if (rst_syn) begin
sel_cnt <= 1'b0;
end else if (dwt_work == 1'b1) begin
if (col_out_vld == 1'b1) begin
sel_cnt <= (sel_cnt ^ 1'b1);
end else begin
sel_cnt <= 1'b0;
end
end
end
wire [15:0] atrcol_out1;
wire [15:0] atrcol_out2;
assign atrcol_out1 = (sel_cnt == 1'b1) ? stage1_reg1 : stage2_reg;
assign atrcol_out2 = (sel_cnt == 1'b1) ? col_ldata : stage1_reg2;
endmodule
| 6.546641 |
module tb_transposy;
reg [255:0] input1;
reg [1:0] select;
reg clk;
wire [511:0] result;
reg reset;
//Testbench specific variables
integer i;
parameter CLK_PERIOD = 10;
transpose DUT (
.dataa(input1),
.clk(clk),
.result(result),
.reset(reset),
.in_select(select)
);
initial begin
clk = 1'b0;
reset = 0;
input1 = 0;
select = 2'b01;
#CLK_PERIOD;
end
always #(CLK_PERIOD) begin
for (i = 0; i < 16; i = i + 1) begin
input1[i*16+:16] <= input1[i*16+:16] + i;
end
end
always #(CLK_PERIOD / 2) clk = ~clk;
endmodule
| 7.027717 |
module transpose_test (
A,
B
);
input [23:0] A; //3*2*4-1
output [23:0] B; //2*3*4-1
wire signed [3:0] A_arr[2:0][1:0];
reg signed [3:0] B_arr[1:0][2:0];
assign {{A_arr[0][0], A_arr[0][1]}, {A_arr[1][0], A_arr[1][1]}, {A_arr[2][0], A_arr[2][1]}} = A;
integer i, j;
always @* begin
for (i = 0; i < 2; i = i + 1) begin
for (j = 0; j < 3; j = j + 1) B_arr[i][j] = A_arr[j][i];
end
end
assign B = {{B_arr[0][0], B_arr[0][1], B_arr[0][2]}, {B_arr[1][0], B_arr[1][1], B_arr[1][2]}};
endmodule
| 6.519533 |
module Trans_RX (
input rst_n, // Connect to system rst_n
input clk_trans, // Connect to top level transceiver clk port, 125MHz
// Used as transceiver input reference clock
input SMA_GXB_RX_p, // RX seriel receiving PIN
output rx_std_clkout, // RX output clock signal for DRAM controller
output [15:0] rx_parallel_data, // RX received data output for DRAM write
output [ 1:0] rx_syncstatus,
output [ 1:0] rx_datak,
// Reconfig ctrl input
input [69:0] RX_reconfig_to_xcvr,
output [45:0] RX_reconfig_from_xcvr,
// DRAM signal
input DRAM_RD_clk, // DRAM read clk for the buffer
input DRAM_RD_req, // DRAM read request
output RX_Buffer_empty, // Buffer empty
output [15:0] Buffer_RD_Data, // Read out data to DRAM
output Buffer_Data_Ready // Signal to let DRAM know the data is ready
);
//RX
wire Transceiver_Clk_125MHz; // Transceiver clk to RX
assign Transceiver_Clk_125MHz = clk_trans;
wire rx_pma_clkout; // rx_pma_clkout
wire rx_is_lockedtoref; // rx_is_lockedtoref
wire [ 1:0] rx_errdetect; // rx_errdetect
wire [ 1:0] rx_disperr; // rx_disperr
wire [ 1:0] rx_runningdisp; // rx_runningdisp
wire [35:0] unused_rx_parallel_data; // unused_rx_parallel_data
wire reconfig_busy;
wire [ 1:0] rx_patterndetect; // rx_patterndetect
// PHY_reset
wire rx_analogreset;
wire rx_digitalreset;
wire rx_ready;
wire rx_is_lockedtodata;
wire rx_cal_busy;
reg tx_datak;
wire rx_std_pcfifo_full;
wire rx_std_pcfifo_empty;
reg rx_std_byteorder_ena;
wire rx_std_byteorder_flag;
reg rx_std_wa_patternalign;
// RX controller module by Ethan
// To detect if RX is starting to receive data and send signal to DRAM
RX_Buf_Ctrl RX_Buf_Ctrl (
.rx_std_clkout(rx_std_clkout),
.rst_n(rst_n),
.rx_syncstatus(rx_syncstatus),
.rx_datak(rx_datak),
.RX_data(rx_parallel_data),
.DRAM_RD_clk(DRAM_RD_clk),
.DRAM_RD_req(DRAM_RD_req),
.RX_Buffer_empty(RX_Buffer_empty),
.Buffer_RD_Data(Buffer_RD_Data),
.Buffer_Data_Ready(Buffer_Data_Ready)
);
// Transciever Reset Controller
PHY_reset PHY_reset (
.clock(clk_trans),
.reset(!rst_n),
.rx_analogreset(rx_analogreset),
.rx_digitalreset(rx_digitalreset),
.rx_ready(rx_ready),
.rx_is_lockedtodata(rx_is_lockedtodata),
.rx_cal_busy(rx_cal_busy)
);
// RX
// Running at 125 MHz, data rate 1Gbps (eventually this should be at least 2Gbps)
GXB_RX GXB_RX (
.rx_serial_data(SMA_GXB_RX_p),
.rx_analogreset(rx_analogreset),
.rx_digitalreset(rx_digitalreset),
.rx_cdr_refclk(Transceiver_Clk_125MHz),
.rx_std_coreclkin(Transceiver_Clk_125MHz),
.rx_pma_clkout(rx_pma_clkout),
.rx_is_lockedtoref(rx_is_lockedtoref),
.rx_is_lockedtodata(rx_is_lockedtodata),
.rx_std_clkout(rx_std_clkout),
.rx_std_pcfifo_full(rx_std_pcfifo_full),
.rx_std_pcfifo_empty(rx_std_pcfifo_empty),
.rx_std_byteorder_ena(rx_std_byteorder_ena),
.rx_std_byteorder_flag(rx_std_byteorder_flag),
.rx_std_wa_patternalign(rx_std_wa_patternalign),
.rx_cal_busy(rx_cal_busy),
.reconfig_to_xcvr(RX_reconfig_to_xcvr),
.reconfig_from_xcvr(RX_reconfig_from_xcvr),
.rx_parallel_data(rx_parallel_data),
.rx_datak(rx_datak),
.rx_errdetect(rx_errdetect),
.rx_disperr(rx_disperr),
.rx_runningdisp(rx_runningdisp),
.rx_patterndetect(rx_patterndetect),
.rx_syncstatus(rx_syncstatus),
.unused_rx_parallel_data(unused_rx_parallel_data)
);
endmodule
| 7.884833 |
module top (
input clk,
we,
re,
input [7:0] ra,
wa,
wd,
output reg [7:0] rd
);
reg [7:0] mem[0:255];
always @(posedge clk) begin
if (we) mem[wa] <= wd;
if (re) begin
rd <= mem[ra];
if (we && ra == wa) rd <= wd;
end
end
endmodule
| 7.233807 |
module top (
input clk,
we,
re,
input [7:0] addr,
wd,
output reg [7:0] rd
);
reg [7:0] mem[0:255];
always @(posedge clk) begin
if (we) mem[addr] <= wd;
if (re) begin
rd <= mem[addr];
if (we) rd <= wd;
end
end
endmodule
| 7.233807 |
module TRANS_TEST_RECEIVE (
input wire CLK,
input wire RESET_N,
input wire SPI_RD_SS, // : AD <- DE1
input wire SPI_RD_SCK, // : AD <- DE1
input wire SPI_RD_SD, // : AD <- DE1
output wire SPI_RD_SACK, // : AD -> DE1
output wire SPI_WR_SS, // : AD -> DE1
output wire SPI_WR_SCK, // : AD -> DE1
output wire SPI_WR_SD, // : AD -> DE1
input wire SPI_WR_SACK // : AD <- DE1
);
reg [ 7:0] state = 0;
reg WR = 0;
reg RD = 0;
wire VALID_RD;
wire BUSY_WR;
reg [63:0] DATA_WR = 0;
wire [63:0] DATA_RD;
always @(posedge CLK) begin
if (!RESET_N) begin
WR <= 0;
RD <= 0;
state <= 0;
end else begin
case (state)
0: begin
WR <= 0;
RD <= 0;
state <= 1;
end
1: begin
if (VALID_RD) begin
DATA_WR <= DATA_RD;
RD <= 1;
state <= 2;
end
end
2: begin
if (!VALID_RD) begin
RD <= 0;
state <= 3;
end
end
3: begin
if (!BUSY_WR) begin
WR <= 1;
state <= 4;
end
end
4: begin
WR <= 0;
state <= 5;
end
5: begin
state <= 0;
end
endcase
end
end
SPI_MASTER MASTER (
.CLK (CLK),
.RESET_N(RESET_N),
.WR (WR),
.DATA(DATA_WR),
.BUSY(BUSY_WR),
.SS (SPI_WR_SS),
.SCLK(SPI_WR_SCK),
.SD (SPI_WR_SD),
.SACK(SPI_WR_SACK)
);
SPI_SLAVE SLAVE (
.CLK (CLK),
.RESET_N(RESET_N),
.RD (RD),
.DATA (DATA_RD),
.VALID(VALID_RD),
.SS (SPI_RD_SS),
.SCLK(SPI_RD_SCK),
.SD (SPI_RD_SD),
.SACK(SPI_RD_SACK)
);
endmodule
| 6.714696 |
module TRANS_TEST_SEND (
input wire CLK,
input wire RESET_N,
output wire SPI_WR_SS, // : AD <- DE1
output wire SPI_WR_SCK, // : AD <- DE1
output wire SPI_WR_SD, // : AD <- DE1
input wire SPI_WR_SACK, // : AD -> DE1
input wire SPI_RD_SS, // : AD -> DE1
input wire SPI_RD_SCK, // : AD -> DE1
input wire SPI_RD_SD, // : AD -> DE1
output reg ERR,
output wire SPI_RD_SACK // : AD <- DE1
);
//reg ERR = 0;
reg [63:0] cnt = 0;
reg [ 7:0] state = 0;
reg WR = 0;
reg RD = 0;
wire VALID_RD;
wire BUSY_WR;
reg [63:0] DATA_WR = 0;
wire [63:0] DATA_RD;
reg [63:0] DATA_RECEIVE = 0;
always @(posedge CLK) begin
if (!RESET_N) begin
WR <= 0;
RD <= 0;
ERR <= 0;
cnt <= 0;
state <= 0;
end else begin
case (state)
0: begin
WR <= 0;
RD <= 0;
DATA_WR <= cnt;
state <= 1;
end
1: begin
if (!BUSY_WR) begin
WR <= 1;
state <= 2;
end
end
2: begin
WR <= 0;
state <= 3;
end
3: begin
if (VALID_RD) begin
DATA_RECEIVE <= DATA_RD;
RD <= 1;
state <= 4;
end
end
4: begin
RD <= 0;
ERR <= (DATA_RECEIVE == DATA_WR) ? 0 : 1;
state <= 5;
end
5: begin
cnt <= cnt + 1;
state <= 0;
end
endcase
end
end
SPI_MASTER MASTER (
.CLK (CLK),
.RESET_N(RESET_N),
.WR (WR),
.DATA(DATA_WR),
.BUSY(BUSY_WR),
.SS (SPI_WR_SS),
.SCLK(SPI_WR_SCK),
.SD (SPI_WR_SD),
.SACK(SPI_WR_SACK)
);
SPI_SLAVE SLAVE (
.CLK (CLK),
.RESET_N(RESET_N),
.RD (RD),
.DATA (DATA_RD),
.VALID(VALID_RD),
.SS (SPI_RD_SS),
.SCLK(SPI_RD_SCK),
.SD (SPI_RD_SD),
.SACK(SPI_RD_SACK)
);
endmodule
| 7.102338 |
module Tran_tb ();
reg [7 : 0] data_in;
reg reset_n,
clk,
start,
byte;
wire [7 : 0] data_o;
wire data_en;
always #5 clk = ~clk;
initial begin
clk = 0;
reset_n = 0;
data_in = 0;
start = 0;
byte = 0;
@(posedge clk);
reset_n = 1;
@(posedge clk);
data_in = 8'b1010_1010;
@(posedge clk);
start = 1;
data_in = 8'b1010_1010;
@(posedge clk);
byte = 1;
data_in = 8'b1111_0000;
@(posedge clk);
byte = 0;
data_in = 8'b0011_0011;
@(posedge clk);
byte = 1;
data_in = 8'b1111_0011;
#10;
$finish;
end
// Tran utran( .clk(clk),
// .reset_n(reset_n),
// .start(start),
// .byte(byte),
// .data_in(data_in),
// .data_o(data_o),
// .data_en(data_en));
// Test Tran2
Tran2 utran( .Clk(clk),
.Rst(reset_n),
.start(start),
.byt(byte),
.DB(data_in),
.Out(data_o),
.Out_en(data_en));
endmodule
| 6.694361 |
module trap (
input aclk,
input aresetn,
// read and write from cpu
//ar
input [3 : 0] arid,
input [ 31:0] araddr,
input [7 : 0] arlen,
input [2 : 0] arsize,
input [1 : 0] arburst,
input [1 : 0] arlock,
input [3 : 0] arcache,
input [2 : 0] arprot,
input arvalid,
output arready,
//r
output [3 : 0] rid,
output [ 31:0] rdata,
output [1 : 0] rresp,
output rlast,
output rvalid,
input rready,
//aw
input [3 : 0] awid,
input [ 31:0] awaddr,
input [7 : 0] awlen,
input [2 : 0] awsize,
input [1 : 0] awburst,
input [1 : 0] awlock,
input [3 : 0] awcache,
input [2 : 0] awprot,
input awvalid,
output awready,
//w
input [3 : 0] wid,
input [ 31:0] wdata,
input [3 : 0] wstrb,
input wlast,
input wvalid,
output wready,
//b
output [3 : 0] bid,
output [1 : 0] bresp,
output bvalid,
input bready
);
assign arready = 1'd1;
assign rvalid = 1'd0;
assign awready = 1'd1;
assign wready = 1'd1;
assign bvalid = 1'd0;
reg w_retire;
reg aw_retire;
reg [31:0] buf_wdata;
reg [31:0] buf_waddr;
always @(posedge aclk) begin
if (!aresetn) begin
w_retire <= 1'd0;
aw_retire <= 1'd0;
buf_wdata <= 32'd0;
buf_waddr <= 32'd0;
end else begin
if (wvalid) begin
w_retire <= 1'd1;
buf_wdata <= wdata;
end
if (awvalid) begin
aw_retire <= 1'd1;
buf_waddr <= awaddr;
end
if (w_retire && aw_retire) begin
if (buf_waddr != 32'h10000000) begin
$display("BAD TRAP ADDR 0x%08x\n", buf_waddr);
end else begin
if (buf_wdata == 32'd0) begin
$display("HIT GOOD TRAP");
end else begin
$display("HIT BAD TRAP");
end
end
$finish;
end
end
end
endmodule
| 6.551649 |
module TRAPHDLR (
input wire i_misaligned,
input wire illegal_i,
input wire l_misaligned,
input wire s_misaligned,
input wire ecall_m,
output wire exception,
output wire [`MXLEN-1:0] mcause
);
function [`MXLEN-1:0] set_mcause;
input instr_misaligned;
input illegal_instr;
input load_misaligned;
input store_misaligned;
input ecall_m;
begin
// The priority of interrupts is determined as below
if (illegal_instr) begin
set_mcause = 32'd2;
end else if (instr_misaligned) begin
set_mcause = 32'd0;
end else if (ecall_m) begin
set_mcause = 32'd11;
end else if (store_misaligned) begin
set_mcause = 32'd6;
end else if (load_misaligned) begin
set_mcause = 32'd4;
end
end
endfunction
assign mcause = set_mcause(i_misaligned, illegal_i, l_misaligned, s_misaligned, ecall_m);
assign exception = (
i_misaligned == 1'b1 ||
illegal_i == 1'b1 ||
l_misaligned == 1'b1 ||
s_misaligned == 1'b1 ||
ecall_m == 1'b1
)? 1'b1 : 1'b0;
endmodule
| 7.817335 |
module TRAP_CTRL (
input wire i_clk,
input wire i_rstn,
//自陷请求
input wire i_trap_vld,
input wire [`trapveclen_def] i_trapvec_id,
/*几个关于中断的重要csr寄存器*/
//需要读的
input wire [`xlen_def] i_csr_mstatus, //状态寄存器
input wire [`xlen_def] i_csr_mtvec, //中断向量表基地址
input wire [`xlen_def] i_csr_mie, //中断使能寄存器
input wire [`xlen_def] i_csr_mip, //中断挂起寄存器
//需要写的
output reg o_trap_update, //自陷更新所需寄存器
output reg [`xlen_def] o_csr_mcause, //异常原因
output reg [`xlen_def] o_csr_mepc, //异常pc
output reg [`xlen_def] o_csr_mstatus, //状态
/****************************/
//连接译码与执行段
input wire i_bpu_inst_vld,
input wire [`xlen_def] i_bpu_iaddr,
input wire i_exu_inst_vld,
input wire [`xlen_def] i_exu_iaddr,
//发生自陷时,替换执行段指令为跳转
output reg o_trap_repl,
output reg [`xlen_def] o_trap_repl_mtvec
);
always @(posedge i_clk or negedge i_rstn) begin
if (~i_rstn) begin
o_trap_update <= 0;
o_trap_repl <= 0;
end else begin
end
end
endmodule
| 6.66964 |
module TrashbinSOC (
input wire CoreClock,
output wire [9:0] LEDS,
output wire [7:0] LEDS_G,
output wire [15:0] HexDisplay
);
wire [31:0] DebugData;
assign LEDS[9:0] = DebugData[29:20];
assign LEDS_G[0] = DebugData[0];
assign LEDS_G[1] = StartupSignal;
assign HexDisplay = {AddressBus[15:0]};
//Memory Wires
wire [31:0] AddressBus;
wire [31:0] DataReadBus;
wire [31:0] DataWriteBus;
wire WriteAssert;
reg StartupSignal = 1'd0;
always @(posedge CoreClock) begin
StartupSignal <= 1'd1;
end
CpuDataInterface cpuDataInterface ();
TempRam datRam (
AddressBus[13:0],
CoreClock,
DataWriteBus,
WriteAssert,
DataReadBus
);
TrashbinCore Core (
CoreClock,
DebugData,
//Memory bus
AddressBus,
DataReadBus,
DataWriteBus,
WriteAssert,
1'b1, //Read OK
1'b1 //Write OK
);
endmodule
| 7.471162 |
module treadmill (
input CLOCK_50,
input CLOCK_27,
input [3:0] KEY,
input [17:0] SW,
output [6:0] HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
output [8:0] LEDG,
output [17:0] LEDR
);
// SLOW THE CLOCK DOWN TO 1HZ
wire clock_1hz;
wire clock_dist;
slow_clock s_clock (
CLOCK_50,
clock_1hz
);
dist_clock d_clock (
CLOCK_50,
clock_dist
);
// Start (up) & Reset (down)
wire reset;
assign reset = SW[0];
// WIRES COMING FROM THE TIMER MODULE
wire [3:0] minute1;
wire [3:0] minute2;
wire [3:0] second1;
wire [3:0] second2;
// WIRES COMING FROM THE DISTANCE MODULE
wire [3:0] distance1;
wire [3:0] distance2;
wire [3:0] distance3;
// Wires coming from the speed module
wire [3:0] speed1;
wire [3:0] speed2;
wire [3:0] speed3;
wire [7:0] speed; // output the speed value in binary (stored in 1/10th of a km/h)
// Wires coming from the slope module
wire [3:0] slope1;
wire [3:0] slope2;
wire [3:0] slope; // output the value in binary
// 4HEX DISPLAYS 0-3 This will be either time passed or distance ran
reg [3:0] display0;
reg [3:0] display1;
reg [3:0] display2;
reg [3:0] display3;
// Wires for PMW
wire [8:0] pmw_wire;
// 2-Hex displays 4/5 wil be used to display the current slope.
reg [3:0] display4;
reg [3:0] display5;
// 2HEX DISPLAYS 7/6 will be used to display the current speed.
reg [3:0] display6;
reg [3:0] display7;
// Track the time
timer time1 (
clock_1hz,
minute1,
minute2,
second1,
second2,
reset
);
// Track the distance
distance dist1 (
clock_dist,
speed,
distance1,
distance2,
distance3
);
// Modify the current speed of the treadmill using KEY3 & KEY2
modify_speed speed_control (
CLOCK_50,
KEY,
speed1,
speed2,
speed3,
speed,
reset
);
// Modify the current slope of the treadmill using KEY1 & KEY0
modify_slope slope_control (
CLOCK_50,
KEY,
slope1,
slope2,
slope,
reset
);
// PWM Stuff
motor pmw (
CLOCK_50,
speed,
pmw_wire
);
// HEX for speed & distance
hex_display dsp0 (
display0,
HEX3
);
hex_display dsp1 (
display1,
HEX2
);
hex_display dsp2 (
display2,
HEX1
);
hex_display dsp3 (
display3,
HEX0
);
// HEX for slope
hex_display dsp4 (
display4,
HEX4
);
hex_display dsp5 (
display5,
HEX5
);
// Hex for speed
hex_display dsp6 (
display6,
HEX6
);
hex_display dsp7 (
display7,
HEX7
);
assign LEDR[8:0] = speed; // debugging to make sure that i am actually changing speed
assign LEDG[8:0] = pmw_wire;
always @(posedge CLOCK_50) begin
if (!SW[17]) begin // show time
display0 = minute1;
display1 = minute2;
display2 = second1;
display3 = second2;
end else if (SW[17]) begin // show distance
display0 = distance1;
display1 = distance2;
display2 = ~3'b1000;
display3 = distance3;
end
if (!SW[16]) begin // show angle
display6 = slope2;
display7 = slope1;
display4 = ~3'b0100;
display5 = ~3'b0100;
end else if (SW[16]) begin // show speed
display4 = speed3;
display5 = ~3'b1000;
display6 = speed2;
display7 = speed1;
end
end
endmodule
| 8.674622 |
module treeadder(din, dout);
/* Parameter definition */
localparam NDATA = 128;
localparam NDATA_IN = 100;
localparam NDATA_LOG = $clog2(NDATA);
/* Input/output definition */
input [NDATA_IN-1:0] din;
output [NDATA_LOG:0] dout;
/* Wire/register declaration */
wire [NDATA-1:0] buffer = {din[NDATA_IN-1:0], {(NDATA-NDATA_IN){1'd0}}};
/* Generator definition */
genvar i,x;
generate
// Iterate to Log2(N) binary tree adder
for(i=1; i<NDATA_LOG;i = i+1) begin: Add
// Get the number of adder in one level
localparam j = (NDATA >> i);
// Create new data wire
wire [i:0] data [0:j-1];
for(x=0; x<j; x = x + 1) begin: Adder
localparam nx = x*2;
if (i == 1)
// Wiring from input wire
assign Add[i].data[x] = buffer[nx:nx] + buffer[nx+1:nx+1];
else
// Wiring from last data wire
assign Add[i].data[x] = Add[i-1].data[nx] + Add[i-1].data[nx+1];
end
end
// Wire output to the last data wire
assign dout = Add[NDATA_LOG-1].data[0] + Add[NDATA_LOG-1].data[1];
endgenerate
endmodule
| 7.086605 |
module TreeComparator(min, sec_min, values);
parameter num_values = 3;
parameter prec = 5;
output [prec-1:0] min;
output [prec-1:0] sec_min;
input [num_values*prec-1:0] values;
wire [prec-1:0] min1;
wire [prec-1:0] min2;
wire [prec-1:0] sec_min1;
wire [prec-1:0] sec_min2;
wire [prec-1:0] _min;
wire [prec-1:0] _sec_min;
genvar log_con;
genvar i;
generate
log_con = 0;
for(i = num_values; i > 0; i = i-1) begin
log_con += i;
end
wire [prec-1:0] min_wires[0:log_con-1];
wire [prec-1:0] sec_min_wires[0:log_con-1];
Comparator JoinTree(min, sec_min, min1, min2, sec_min1, sec_min2);
generate
for(i=0; i < num_values/2; i=i+1) begin
always@(*) begin
if(values[prec*(i+1)-1:prec*i] < values[prec*(i+2)-1:prec*(i+1)]) begin
min_wires[i] <= values[prec*(i+1)-1:prec*i];
sec_min_wires[i] <= values[prec*(i+2)-1:prec*(i+1)];
end
else begin
sec_min_wires[i] <= values[prec*(i+1)-1:prec*i];
min_wires[i] <= values[prec*(i+2)-1:prec*(i+1)];
end
end
min_wires[i] = (values[prec*(i+1)-1:prec*i] < values[prec*(i+2)-1:prec*(i+1)] ?
generate
if(num_values == 1) begin
assign min = values;
assign second_min = {prec{1'b1}};
end
else if(num_values >= 2) begin
assign min = _min;
assign sec_min = _sec_min;
TreeComparator2 #(num_values/2, prec) LeftTree(min1, sec_min1, left_vals);
TreeComparator2 #(num_values-num_values/2, prec) RightTree(min2, sec_min2, right_vals);
end
endgenerate
endmodule
| 6.554052 |
module tree_8prior_sel (
input wire clk, //add module's work clk domin
input wire rst_n,
input wire [1*8-1:0] sel_valid,
input wire [8*8-1:0] sel_prior,
input wire [8*8-1:0] sel_index,
output wire result_valid,
output wire [7:0] result_prior,
output wire [7:0] result_index
);
//***************************************************
// Intermediate variable Declaration
//***************************************************
//all wire/reg/parameter variable
//should be declare below here
wire [1*4-1:0] branch_1_valid;
wire [8*4-1:0] branch_1_prior;
wire [8*4-1:0] branch_1_index;
wire [1*2-1:0] branch_2_valid;
wire [8*2-1:0] branch_2_prior;
wire [8*2-1:0] branch_2_index;
//***************************************************
// Tree Branch 1
//***************************************************
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin : Prior_1_Branch
prior_sel prior_1_branch_inst (
.clk (clk), //add module's work clk domin
.rst_n(rst_n),
.sel_a_valid(sel_valid[i]),
.sel_a_prior(sel_prior[8*i+7:8*i]),
.sel_a_index(sel_index[8*i+7:8*i]),
.sel_b_valid(sel_valid[i+4]),
.sel_b_prior(sel_prior[8*(i+4)+7:8*(i+4)]),
.sel_b_index(sel_index[8*(i+4)+7:8*(i+4)]),
.result_valid(branch_1_valid[i]),
.result_prior(branch_1_prior[8*i+7:8*i]),
.result_index(branch_1_index[8*i+7:8*i])
);
end
endgenerate
//***************************************************
// Tree Branch 2
//***************************************************
generate
genvar j;
for (j = 0; j < 2; j = j + 1) begin : prior_2_Branch
prior_sel prior_2_branch_inst (
.clk (clk), //add module's work clk domjn
.rst_n(rst_n),
.sel_a_valid(branch_1_valid[j]),
.sel_a_prior(branch_1_prior[8*j+7:8*j]),
.sel_a_index(branch_1_index[8*j+7:8*j]),
.sel_b_valid(branch_1_valid[j+2]),
.sel_b_prior(branch_1_prior[8*(j+2)+7:8*(j+2)]),
.sel_b_index(branch_1_index[8*(j+2)+7:8*(j+2)]),
.result_valid(branch_2_valid[j]),
.result_prior(branch_2_prior[8*j+7:8*j]),
.result_index(branch_2_index[8*j+7:8*j])
);
end
endgenerate
//***************************************************
// Tree Branch end
//***************************************************
prior_sel prior_end_branch_inst (
.clk (clk), //add module's work clk domin
.rst_n(rst_n),
.sel_a_valid(branch_2_valid[0]),
.sel_a_prior(branch_2_prior[8*0+7:8*0]),
.sel_a_index(branch_2_index[8*0+7:8*0]),
.sel_b_valid(branch_2_valid[1]),
.sel_b_prior(branch_2_prior[8*1+7:8*1]),
.sel_b_index(branch_2_index[8*1+7:8*1]),
.result_valid(result_valid),
.result_prior(result_prior),
.result_index(result_index)
);
endmodule
| 7.638506 |
module tree_fanout #(
parameter in_w = 128 * 8,
parameter fanout_factor = 3
) (
input clk,
input rst_n,
input up_vld,
input [in_w-1:0] up_dat,
output up_rdy,
output dn_vld,
input dn_rdy,
output [fanout_factor*in_w-1:0] dn_dat
);
assign up_rdy = dn_rdy;
reg [in_w-1:0] up_dats[fanout_factor-1 : 0][fanout_factor-1 : 0];
reg [in_w-1:0] up_vlds[fanout_factor-1 : 0][fanout_factor-1 : 0];
reg dn_vld_r;
wire [fanout_factor*in_w-1:0] dn_dat_w;
reg [fanout_factor*in_w-1:0] dn_dat_r;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dats[0][0] <= 0;
up_vlds[0][0] <= 0;
end else begin
up_dats[0][0] <= up_dat;
up_vlds[0][0] <= up_vld;
end
genvar i;
genvar j;
generate
for (j = 1; j < fanout_factor; j = j + 1) begin : FIRST_ROW_PIPELINING
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dats[0][j] <= 0;
up_vlds[0][j] <= 0;
end else begin
up_dats[0][j] <= up_dats[0][j-1];
up_vlds[0][j] <= up_vlds[0][j-1];
end
end
endgenerate
generate
for (i = 1; i < fanout_factor; i = i + 1) begin : ROW_LOOP
for (j = i; j < fanout_factor; j = j + 1) begin : COLUMN_LOOP
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dats[i][j] <= 0;
up_vlds[i][j] <= 0;
end else begin
up_dats[i][j] <= up_dats[i-1][j-1];
up_vlds[i][j] <= up_vlds[i-1][j-1];
end
end
end
endgenerate
generate
for (i = 0; i < fanout_factor; i = i + 1) begin : GENERATE_OUTPUTS
assign dn_dat_w[(in_w*i+in_w-1) : (in_w*i)] = up_dats[i][fanout_factor-1];
end
endgenerate
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dn_vld_r <= 0;
dn_dat_r <= 0;
end else begin
dn_vld_r <= up_vlds[0][fanout_factor-1];
dn_dat_r <= dn_dat_w;
end
assign dn_vld = dn_vld_r;
assign dn_dat = dn_dat_r;
endmodule
| 8.219726 |
module tree_fanout_double #(
parameter in_w = 128 * 8
) (
input clk,
input rst_n,
input up_vld,
input [in_w-1:0] up_dat,
output up_rdy,
output dn_vld,
input dn_rdy,
output [2*in_w-1:0] dn_dat
);
assign up_rdy = dn_rdy;
reg [in_w-1:0] up_dat_r;
reg up_vld_r;
reg [in_w-1:0] up_dats[2-1 : 0];
reg [in_w-1:0] up_vlds[2-1 : 0];
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dat_r <= 0;
up_vld_r <= 0;
end else begin
up_dat_r <= up_dat;
up_vld_r <= up_vld;
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dats[0] <= 0;
up_vlds[0] <= 0;
end else begin
up_dats[0] <= up_dat_r;
up_vlds[0] <= up_vld_r;
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dats[1] <= 0;
up_vlds[1] <= 0;
end else begin
up_dats[1] <= up_dat_r;
up_vlds[1] <= up_vld_r;
end
assign dn_dat = {up_dats[0], up_dats[1]};
assign dn_vld = up_vlds[0];
endmodule
| 7.449904 |
module tree_nca_routing #(
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
current_addr_encoded, // connected to current router x address
current_level, //connected to current router y address
dest_addr_encoded, // destination address
destport_encoded // router output port
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
localparam Kw = log2(K), LKw = L * Kw, Lw = log2(L), DSPw = log2(K + 1);
input [LKw-1 : 0] current_addr_encoded;
input [Lw-1 : 0] current_level;
input [LKw-1 : 0] dest_addr_encoded;
output [DSPw-1:0] destport_encoded;
/******************
There is always one destination path that can be selected for each destination endpoint
Hence we can use the binary address of destination port
*******************/
wire [Kw-1 : 0] current_addr[L-1 : 0];
wire [Kw-1 : 0] parrent_dest_addr[L-1 : 0];
wire [Kw-1 : 0] dest_addr[L-1 : 0];
wire [DSPw-1 : 0] current_node_dest_port;
wire [L-1 : 0] parrents_node_missmatch;
assign current_addr[0] = {Kw{1'b0}};
assign parrent_dest_addr[0] = {Kw{1'b0}};
genvar i;
generate
for (i = 1; i < L; i = i + 1) begin : caddr
/* verilator lint_off WIDTH */
assign current_addr [i] = (current_level <i)? current_addr_encoded[i*Kw-1 : (i-1)*Kw] : {Kw{1'b0}};
assign parrent_dest_addr [i] = (current_level<i)? dest_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
/* verilator lint_on WIDTH */
end
for (i = 0; i < L; i = i + 1) begin : daddr
// assign current_addr [i] = (current_level >=i)? current_addr_encoded[(i+1)*Kw-1 : i*Kw] : {Kw{1'b0}};
assign dest_addr[i] = dest_addr_encoded[(i+1)*Kw-1 : i*Kw];
assign parrents_node_missmatch[i] = current_addr[i] != parrent_dest_addr[i];
end //for
if (DSPw == Kw) begin : eq
assign current_node_dest_port = dest_addr[current_level];
end else begin : neq
assign current_node_dest_port = {1'b0, dest_addr[current_level]};
end
endgenerate
assign destport_encoded = (parrents_node_missmatch != {L{1'b0}}) ? /*go up*/ K[DSPw-1: 0] : /*go down*/current_node_dest_port;
endmodule
| 6.953444 |
module tree_conventional_routing #(
parameter ROUTE_NAME = "NCA",
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
current_addr_encoded, // connected to current router x address
current_level, //connected to current router y address
dest_addr_encoded, // destination address
destport_encoded // router output port
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
localparam Kw = log2(K), LKw = L * Kw, Lw = log2(L), DSPw = log2(K + 1);
input [LKw-1 : 0] current_addr_encoded;
input [Lw-1 : 0] current_level;
input [LKw-1 : 0] dest_addr_encoded;
output [DSPw-1 : 0] destport_encoded;
tree_nca_routing #(
.K(K),
.L(L)
) nca_random_up (
.current_addr_encoded(current_addr_encoded),
.current_level(current_level),
.dest_addr_encoded(dest_addr_encoded),
.destport_encoded(destport_encoded)
);
endmodule
| 6.733784 |
module tree_deterministic_look_ahead_routing #(
parameter P = 4,
parameter ROUTE_NAME = "NCA_RND_UP",
parameter K = 2, // number of last level individual router`s endpoints.
parameter L = 2 // Fattree layer number (The height of FT)
) (
destport_encoded, // current router destination port
dest_addr_encoded,
neighbors_rx,
neighbors_ry,
lkdestport_encoded // look ahead destination port
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
localparam Kw = log2(
K
), LKw = L * Kw, Lw = log2(
L
), Pw = log2(
P
), PLw = P * Lw, PLKw = P * LKw, DSPw = log2(
K + 1
);
input [DSPw-1 : 0] destport_encoded;
input [LKw-1 : 0] dest_addr_encoded;
input [PLKw-1 : 0] neighbors_rx;
input [PLw-1 : 0] neighbors_ry;
output [DSPw-1:0] lkdestport_encoded;
wire [LKw-1 : 0] next_addr_encoded;
wire [ Lw-1 : 0] next_level;
wire [ DSPw-1:0] lkdestport_encoded;
next_router_addr_selector_bin #(
.P (P),
.RXw(LKw),
.RYw(Lw)
) addr_predictor (
.destport_bin(destport_encoded[Pw-1 : 0]),
.neighbors_rx(neighbors_rx),
.neighbors_ry(neighbors_ry),
.next_rx(next_addr_encoded),
.next_ry(next_level)
);
tree_conventional_routing #(
.ROUTE_NAME(ROUTE_NAME),
.K(K),
.L(L)
) conv_routing (
.current_addr_encoded(next_addr_encoded),
.current_level(next_level),
.dest_addr_encoded(dest_addr_encoded),
.destport_encoded(lkdestport_encoded)
);
endmodule
| 7.514567 |
module tree_look_ahead_routing #(
parameter ROUTE_NAME = "NCA",
parameter P = 4,
parameter L = 2,
parameter K = 2
) (
reset,
clk,
destport_encoded, // current router destination port
dest_addr_encoded,
neighbors_rx,
neighbors_ry,
lkdestport_encoded // look ahead destination port
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1 : 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
localparam Kw = log2(
K
), LKw = L * Kw, Lw = log2(
L
), PLw = P * Lw, PLKw = P * LKw, DSPw = log2(
K + 1
);
input [DSPw-1 : 0] destport_encoded;
input [LKw-1 : 0] dest_addr_encoded;
input [PLKw-1 : 0] neighbors_rx;
input [PLw-1 : 0] neighbors_ry;
output [DSPw-1:0] lkdestport_encoded;
input reset, clk;
wire [DSPw-1 : 0] destport_encoded_delayed;
wire [ LKw-1 : 0] dest_addr_encoded_delayed;
tree_deterministic_look_ahead_routing #(
.P(P),
.ROUTE_NAME(ROUTE_NAME),
.K(K),
.L(L)
) look_ahead_routing (
.destport_encoded(destport_encoded_delayed),
.dest_addr_encoded(dest_addr_encoded_delayed),
.neighbors_rx(neighbors_rx),
.neighbors_ry(neighbors_ry),
.lkdestport_encoded(lkdestport_encoded)
);
pronoc_register #(
.W(DSPw)
) reg1 (
.in(destport_encoded),
.out(destport_encoded_delayed),
.reset(reset),
.clk(clk)
);
pronoc_register #(
.W(LKw)
) reg2 (
.in(dest_addr_encoded),
.out(dest_addr_encoded_delayed),
.reset(reset),
.clk(clk)
);
endmodule
| 6.941724 |
module tree_destp_generator #(
parameter K = 2,
parameter P = K + 1,
parameter SW_LOC = 0,
parameter DSTPw = 4,
parameter SELF_LOOP_EN = "NO"
) (
dest_port_in_encoded,
dest_port_out
);
localparam MAX_P = K + 1, P_1 = (SELF_LOOP_EN == "NO") ? P - 1 : P;
input [DSTPw-1:0] dest_port_in_encoded;
output [P_1-1 : 0] dest_port_out;
wire [MAX_P-1 : 0] destport_decoded;
tree_destport_decoder #(
.K(K)
) destport_decoder (
.destport_encoded_i(dest_port_in_encoded),
.destport_decoded_o(destport_decoded)
);
generate
if (SELF_LOOP_EN == "NO") begin : nslp
remove_sw_loc_one_hot #(
.P(P),
.SW_LOC(SW_LOC)
) conv (
.destport_in (destport_decoded[P-1 : 0]),
.destport_out(dest_port_out[P_1-1 : 0])
);
end else begin : slp
assign dest_port_out = destport_decoded;
end
endgenerate
endmodule
| 8.27829 |
module treg (
input rst,
clk,
input ldt,
ld1,
input [15:0] mulbus,
output reg [15:0] treg
);
always @(posedge clk, posedge rst) begin
if (rst) treg <= 16'b0;
else if (ldt) treg <= mulbus;
else if (ld1) treg <= 16'b0000000100000000;
end
endmodule
| 7.328953 |
module TREG8V (
a,
en,
clk,
rst,
q
);
input [15:0] a;
input rst, clk, en;
output [15:0] q;
reg [15:0] q, val;
always @(posedge clk or posedge rst)
if (rst == 1'b1) val <= {16{1'b0}};
else val <= a;
always @(en or val)
if (en == 1'b1) q <= val;
else q <= 16'bzzzzzzzzzzzzzzzz;
endmodule
| 6.511944 |
module tRegisters;
reg [ 3:0] index;
wire [15:0] bus;
reg rEn, wEn, reset, loadBus;
reg [15:0] busVal;
busDriver driver (
busVal,
bus,
loadBus,
reset
);
register progRegisters (
index,
bus,
rEn,
wEn,
reset
);
initial begin
rEn = 0;
reset = 1;
#5 reset = 0;
#5 busVal = 16'd20;
loadBus = 1;
#5 loadBus = 0;
index = 2'd1;
#5 wEn = 1;
#5 wEn = 0;
rEn = 1;
#5 rEn = 0;
$finish;
end
endmodule
| 7.040998 |
module treg (
input rst,
clk,
input ldt,
ld1,
input [15:0] mulbus,
output reg [15:0] treg
);
always @(posedge clk, posedge rst) begin
if (rst) treg <= 16'b0;
else if (ldt) treg <= mulbus;
else if (ld1) treg <= 16'b0000000100000000;
end
endmodule
| 7.328953 |
module trellshift (
aclr,
clock,
data,
load,
q
);
input aclr;
input clock;
input [3:0] data;
input load;
output [3:0] q;
wire [3:0] sub_wire0;
wire [3:0] q = sub_wire0[3:0];
lpm_shiftreg LPM_SHIFTREG_component (
.aclr(aclr),
.clock(clock),
.data(data),
.load(load),
.q(sub_wire0)
// synopsys translate_off
, .aset(),
.enable(),
.sclr(),
.shiftin(),
.shiftout(),
.sset()
// synopsys translate_on
);
defparam LPM_SHIFTREG_component.lpm_direction = "RIGHT",
LPM_SHIFTREG_component.lpm_type = "LPM_SHIFTREG", LPM_SHIFTREG_component.lpm_width = 4;
endmodule
| 6.701264 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.